Generate SDS control module

[ReinhardKeil]

Suggest to create a generic "sds_control.c" module based on https://github.com/Arm-Examples/SDS-Examples/blob/main/Hardware/DataTest/rec_management.c

Modifications:

• https://github.com/Arm-Examples/SDS-Examples/blob/main/Hardware/DataTest/rec_management.c#L90
  • idle counter can be evaluated in just 10msec.
  • this removes the need for /100 in https://github.com/Arm-Examples/SDS-Examples/blob/main/Hardware/DataTest/rec_management.c#L164

State Machine

• introduce a state machine with states

  • SDSIO_CLOSED (0) - No SDS I/O pipes open.
  • SDSIO_OPEN (1) - SDS I/O pipes are open and ready for read/write operations.
  • SDSIO_CLOSING (2) – Indicates the transition toward the closed state, complete current pending algorithm execution.
  • SDSIO_HALTED – Indicates a completed algorithm execution after SDSIO_CLOSING state.

• https://github.com/Arm-Examples/SDS-Examples/blob/main/Hardware/DataTest/rec_management.c#L57

  • should become 'sdsio_state'.

• This https://github.com/Arm-Examples/SDS-Examples/blob/main/Hardware/DataTest/rec_management.c#L142 becomes SDSIO_OPEN.

• This https://github.com/Arm-Examples/SDS-Examples/blob/main/Hardware/DataTest/rec_management.c#L144 becomes SDSIO_CLOSING.

• State SDSIO_HALTED becomes active when state is SDSIO_CLOSING and test data are written https://github.com/Arm-Examples/SDS-Examples/blob/main/Hardware/DataTest/DataTest.c#L102

• One state SDSIO_HALTED this is executed: https://github.com/Arm-Examples/SDS-Examples/blob/main/Hardware/DataTest/rec_management.c#L146

Allow to measure Jitters
Use a separate timestamp value here
https://github.com/Arm-Examples/SDS-Examples/blob/main/Hardware/DataTest/DataTest.c#L102