-
Notifications
You must be signed in to change notification settings - Fork 1
/
Copy pathaiutils.c
1854 lines (1574 loc) · 50.8 KB
/
aiutils.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* Misc utility routines for accessing chip-specific features
* of the SiliconBackplane-based Broadcom chips.
* Note: this file is used for both dongle and DHD builds.
*
* Copyright (C) 2023, Broadcom.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
*
* <<Broadcom-WL-IPTag/Dual:>>
*/
#include <typedefs.h>
#include <bcmdefs.h>
#include <osl.h>
#include <bcmutils.h>
#include <siutils.h>
#include <hndsoc.h>
#include <sbchipc.h>
#include <pcicfg.h>
#include <pcie_core.h>
#include "siutils_priv.h"
#if !defined(BCMDONGLEHOST) || defined(AXI_TIMEOUTS)
#include "aiutils_priv.h"
#endif
#if defined(ETD)
#include <etd.h>
#endif
#if !defined(BCMDONGLEHOST)
#define PMU_DMP(sii) ((sii)->cores_info->coreid[(sii)->curidx] == PMU_CORE_ID)
#define GCI_DMP(sii) ((sii)->cores_info->coreid[(sii)->curidx] == GCI_CORE_ID)
#else
#define PMU_DMP(sii) (0)
#define GCI_DMP(sii) (0)
#endif /* !defined(BCMDONGLEHOST) */
/* EROM parsing */
static uint32
get_erom_ent(const si_t *sih, uint32 **eromptr, uint32 mask, uint32 match)
{
uint32 ent;
uint inv = 0, nom = 0;
uint32 size = 0;
while (TRUE) {
ent = R_REG(SI_INFO(sih)->osh, *eromptr);
(*eromptr)++;
if (mask == 0)
break;
if ((ent & ER_VALID) == 0) {
inv++;
continue;
}
if (ent == (ER_END | ER_VALID))
break;
if ((ent & mask) == match)
break;
/* escape condition related EROM size if it has invalid values */
size += sizeof(*eromptr);
if (size >= ER_SZ_MAX) {
SI_ERROR(("Failed to find end of EROM marker\n"));
break;
}
nom++;
}
SI_VMSG(("get_erom_ent: Returning ent 0x%08x\n", ent));
if (inv + nom) {
SI_VMSG((" after %d invalid and %d non-matching entries\n", inv, nom));
}
return ent;
}
static uint32
get_asd(const si_t *sih, uint32 **eromptr, uint sp, uint ad, uint st, uint32 *addrl, uint32 *addrh,
uint32 *sizel, uint32 *sizeh)
{
uint32 asd, sz, szd;
BCM_REFERENCE(ad);
asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID);
if (((asd & ER_TAG1) != ER_ADD) ||
(((asd & AD_SP_MASK) >> AD_SP_SHIFT) != sp) ||
((asd & AD_ST_MASK) != st)) {
/* This is not what we want, "push" it back */
(*eromptr)--;
return 0;
}
*addrl = asd & AD_ADDR_MASK;
if (asd & AD_AG32)
*addrh = get_erom_ent(sih, eromptr, 0, 0);
else
*addrh = 0;
*sizeh = 0;
sz = asd & AD_SZ_MASK;
if (sz == AD_SZ_SZD) {
szd = get_erom_ent(sih, eromptr, 0, 0);
*sizel = szd & SD_SZ_MASK;
if (szd & SD_SG32)
*sizeh = get_erom_ent(sih, eromptr, 0, 0);
} else
*sizel = AD_SZ_BASE << (sz >> AD_SZ_SHIFT);
SI_VMSG((" SP %d, ad %d: st = %d, 0x%08x_0x%08x @ 0x%08x_0x%08x\n",
sp, ad, st, *sizeh, *sizel, *addrh, *addrl));
return asd;
}
/* Parse the enumeration rom to identify all cores */
void
BCMATTACHFN(ai_scan)(si_t *sih, void *regs, uint devid)
{
si_info_t *sii = SI_INFO(sih);
si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
chipcregs_t *cc = (chipcregs_t *)regs;
uint32 erombase, *eromptr, *eromlim;
axi_wrapper_t * axi_wrapper = sii->axi_wrapper;
SI_MSG_DBG_REG(("%s: Enter\n", __FUNCTION__));
BCM_REFERENCE(devid);
erombase = R_REG(sii->osh, CC_REG_ADDR(cc, EromPtrOffset));
switch (BUSTYPE(sih->bustype)) {
case SI_BUS:
eromptr = (uint32 *)REG_MAP(erombase, SI_CORE_SIZE);
break;
case PCI_BUS:
/* Set wrappers address */
sii->curwrap = (void *)((uintptr)regs + SI_CORE_SIZE);
/* Now point the window at the erom */
OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, erombase);
eromptr = regs;
break;
#ifdef BCMSDIO
case SPI_BUS:
case SDIO_BUS:
eromptr = (uint32 *)(uintptr)erombase;
break;
#endif /* BCMSDIO */
default:
SI_ERROR(("Don't know how to do AXI enumeration on bus %d\n", sih->bustype));
ASSERT(0);
return;
}
eromlim = eromptr + (ER_REMAPCONTROL / sizeof(uint32));
sii->axi_num_wrappers = 0;
SI_VMSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%p, eromlim = 0x%p\n",
OSL_OBFUSCATE_BUF(regs), erombase,
OSL_OBFUSCATE_BUF(eromptr), OSL_OBFUSCATE_BUF(eromlim)));
while (eromptr < eromlim) {
uint32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp;
uint32 mpd, asd, addrl, addrh, sizel, sizeh;
uint i, j, idx;
bool br;
br = FALSE;
/* Grok a component */
cia = get_erom_ent(sih, &eromptr, ER_TAG, ER_CI);
if (cia == (ER_END | ER_VALID)) {
SI_VMSG(("Found END of erom after %d cores\n", sii->numcores));
SI_MSG_DBG_REG(("%s: Exit\n", __FUNCTION__));
return;
}
cib = get_erom_ent(sih, &eromptr, 0, 0);
if ((cib & ER_TAG) != ER_CI) {
SI_ERROR(("CIA not followed by CIB\n"));
goto error;
}
cid = (cia & CIA_CID_MASK) >> CIA_CID_SHIFT;
mfg = (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
crev = (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
nmw = (cib & CIB_NMW_MASK) >> CIB_NMW_SHIFT;
nsw = (cib & CIB_NSW_MASK) >> CIB_NSW_SHIFT;
nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
#ifdef BCMDBG_SI
SI_VMSG(("Found component 0x%04x/0x%04x rev %d at erom addr 0x%p, with nmw = %d, "
"nsw = %d, nmp = %d & nsp = %d\n",
mfg, cid, crev, OSL_OBFUSCATE_BUF(eromptr - 1), nmw, nsw, nmp, nsp));
#else
BCM_REFERENCE(crev);
#endif
/* Include Default slave wrapper for timeout monitoring */
if ((nsp == 0 && nsw == 0) ||
((mfg == MFGID_ARM) && (cid == DEF_AI_COMP))) {
continue;
}
if ((nmw + nsw == 0)) {
/* A component which is not a core */
/* Should record some info */
if (cid == OOB_ROUTER_CORE_ID) {
asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE,
&addrl, &addrh, &sizel, &sizeh);
if (asd != 0) {
if ((sii->oob_router != 0) && (sii->oob_router != addrl)) {
sii->oob_router1 = addrl;
} else {
sii->oob_router = addrl;
}
}
}
if ((cid != NS_CCB_CORE_ID) && (cid != PMU_CORE_ID) &&
(cid != GCI_CORE_ID) && (cid != SR_CORE_ID) &&
(cid != HUB_CORE_ID) && (cid != HND_OOBR_CORE_ID) &&
(cid != CCI400_CORE_ID) && (cid != SPMI_SLAVE_CORE_ID) &&
#if defined(__ARM_ARCH_7R__)
(cid != SDTC_CORE_ID) &&
#endif /* __ARM_ARCH_7R__ */
TRUE) {
continue;
}
}
idx = sii->numcores;
cores_info->cia[idx] = cia;
cores_info->cib[idx] = cib;
cores_info->coreid[idx] = cid;
/* workaround the fact the variable buscoretype is used in _ai_set_coreidx()
* when checking PCIE_GEN2() for PCI_BUS case before it is setup later...,
* both use and setup happen in si_buscore_setup().
*/
if (BUSTYPE(sih->bustype) == PCI_BUS &&
(cid == PCI_CORE_ID || cid == PCIE_CORE_ID || cid == PCIE2_CORE_ID)) {
sii->pub.buscoretype = (uint16)cid;
}
for (i = 0; i < nmp; i++) {
mpd = get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
if ((mpd & ER_TAG) != ER_MP) {
SI_ERROR(("Not enough MP entries for component 0x%x\n", cid));
goto error;
}
/* Record something? */
SI_VMSG((" Master port %d, mp: %d id: %d\n", i,
(mpd & MPD_MP_MASK) >> MPD_MP_SHIFT,
(mpd & MPD_MUI_MASK) >> MPD_MUI_SHIFT));
}
/* First Slave Address Descriptor should be port 0:
* the main register space for the core
*/
asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh, &sizel, &sizeh);
if (asd == 0) {
do {
/* Try again to see if it is a bridge */
asd = get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl, &addrh,
&sizel, &sizeh);
if (asd != 0)
br = TRUE;
else {
break;
}
} while (1);
} else {
if (addrl == 0 || sizel == 0) {
SI_ERROR((" Invalid ASD %x for slave port \n", asd));
goto error;
}
cores_info->coresba[idx] = addrl;
cores_info->coresba_size[idx] = sizel;
}
/* Get any more ASDs in first port */
j = 1;
do {
asd = get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl, &addrh,
&sizel, &sizeh);
/* Support ARM debug core ASD with address space > 4K */
if ((asd != 0) && (j == 1)) {
SI_VMSG(("Warning: sizel > 0x1000\n"));
cores_info->coresba2[idx] = addrl;
cores_info->coresba2_size[idx] = sizel;
}
j++;
} while (asd != 0);
/* Go through the ASDs for other slave ports */
for (i = 1; i < nsp; i++) {
j = 0;
do {
asd = get_asd(sih, &eromptr, i, j, AD_ST_SLAVE, &addrl, &addrh,
&sizel, &sizeh);
/* To get the first base address of second slave port */
if ((asd != 0) && (i == 1) && (j == 0)) {
cores_info->csp2ba[idx] = addrl;
cores_info->csp2ba_size[idx] = sizel;
}
if (asd == 0)
break;
j++;
} while (1);
if (j == 0) {
SI_ERROR((" SP %d has no address descriptors\n", i));
goto error;
}
}
/* Now get master wrappers */
for (i = 0; i < nmw; i++) {
asd = get_asd(sih, &eromptr, i, 0, AD_ST_MWRAP, &addrl, &addrh,
&sizel, &sizeh);
if (asd == 0) {
SI_ERROR(("Missing descriptor for MW %d\n", i));
goto error;
}
if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
SI_ERROR(("Master wrapper %d is not 4KB\n", i));
goto error;
}
if (i == 0) {
cores_info->wrapba[idx] = addrl;
} else if (i == 1) {
cores_info->wrapba2[idx] = addrl;
} else if (i == 2) {
cores_info->wrapba3[idx] = addrl;
}
if (axi_wrapper && (sii->axi_num_wrappers < SI_MAX_AXI_WRAPPERS)) {
axi_wrapper[sii->axi_num_wrappers].mfg = mfg;
axi_wrapper[sii->axi_num_wrappers].cid = cid;
axi_wrapper[sii->axi_num_wrappers].rev = crev;
axi_wrapper[sii->axi_num_wrappers].wrapper_type = AI_MASTER_WRAPPER;
axi_wrapper[sii->axi_num_wrappers].wrapper_addr = addrl;
sii->axi_num_wrappers++;
SI_VMSG(("MASTER WRAPPER: %d, mfg:%x, cid:%x,"
"rev:%x, addr:%x, size:%x\n",
sii->axi_num_wrappers, mfg, cid, crev, addrl, sizel));
}
}
/* And finally slave wrappers */
for (i = 0; i < nsw; i++) {
uint fwp = (nsp <= 1) ? 0 : 1;
asd = get_asd(sih, &eromptr, fwp + i, 0, AD_ST_SWRAP, &addrl, &addrh,
&sizel, &sizeh);
if (asd == 0) {
SI_ERROR(("Missing descriptor for SW %d cid %x eromp %p fwp %d \n",
i, cid, eromptr, fwp));
goto error;
}
if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
SI_ERROR(("Slave wrapper %d is not 4KB\n", i));
goto error;
}
/* cache APB bridge wrapper address for set/clear timeout */
if ((mfg == MFGID_ARM) && (cid == APB_BRIDGE_ID)) {
ASSERT(sii->num_br < SI_MAXBR);
if (sii->num_br >= SI_MAXBR) {
SI_ERROR(("bridge number %d is overflowed\n", sii->num_br));
goto error;
}
sii->br_wrapba[sii->num_br++] = addrl;
}
if ((mfg == MFGID_ARM) && (cid == ADB_BRIDGE_ID)) {
br = TRUE;
}
BCM_REFERENCE(br);
if ((nmw == 0) && (i == 0)) {
cores_info->wrapba[idx] = addrl;
} else if ((nmw == 0) && (i == 1)) {
cores_info->wrapba2[idx] = addrl;
} else if ((nmw == 0) && (i == 2)) {
cores_info->wrapba3[idx] = addrl;
}
/* Include all slave wrappers to the list to
* enable and monitor watchdog timeouts
*/
if (axi_wrapper && (sii->axi_num_wrappers < SI_MAX_AXI_WRAPPERS)) {
axi_wrapper[sii->axi_num_wrappers].mfg = mfg;
axi_wrapper[sii->axi_num_wrappers].cid = cid;
axi_wrapper[sii->axi_num_wrappers].rev = crev;
axi_wrapper[sii->axi_num_wrappers].wrapper_type = AI_SLAVE_WRAPPER;
axi_wrapper[sii->axi_num_wrappers].wrapper_addr = addrl;
sii->axi_num_wrappers++;
SI_VMSG(("SLAVE WRAPPER: %d, mfg:%x, cid:%x,"
"rev:%x, addr:%x, size:%x\n",
sii->axi_num_wrappers, mfg, cid, crev, addrl, sizel));
}
}
/* Don't record bridges and core with 0 slave ports */
if (br || (nsp == 0)) {
continue;
}
/* Done with core */
sii->numcores++;
}
SI_ERROR(("Reached end of erom without finding END"));
error:
sii->numcores = 0;
SI_MSG_DBG_REG(("%s: Exit\n", __FUNCTION__));
return;
}
#define AI_SETCOREIDX_MAPSIZE(coreid) \
(((coreid) == NS_CCB_CORE_ID) ? 15 * SI_CORE_SIZE : SI_CORE_SIZE)
/* This function changes the logical "focus" to the indicated core.
* Return the current core's virtual address.
*/
static volatile void *
BCMPOSTTRAPFN(_ai_setcoreidx)(si_t *sih, uint coreidx, uint use_wrapn)
{
si_info_t *sii = SI_INFO(sih);
si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
uint32 addr, wrap, wrap2, wrap3;
volatile void *regs;
if (coreidx >= MIN(sii->numcores, SI_MAXCORES))
return (NULL);
addr = cores_info->coresba[coreidx];
wrap = cores_info->wrapba[coreidx];
wrap2 = cores_info->wrapba2[coreidx];
wrap3 = cores_info->wrapba3[coreidx];
/*
* If the user has provided an interrupt mask enabled function,
* then assert interrupts are disabled before switching the core.
*/
ASSERT((sii->intrsenabled_fn == NULL) || !(*(sii)->intrsenabled_fn)((sii)->intr_arg));
switch (BUSTYPE(sih->bustype)) {
case SI_BUS:
/* map new one */
if (!cores_info->regs[coreidx]) {
cores_info->regs[coreidx] = REG_MAP(addr,
AI_SETCOREIDX_MAPSIZE(cores_info->coreid[coreidx]));
ASSERT(GOODREGS(cores_info->regs[coreidx]));
}
sii->curmap = regs = cores_info->regs[coreidx];
if (!cores_info->wrappers[coreidx] && (wrap != 0)) {
cores_info->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);
ASSERT(GOODREGS(cores_info->wrappers[coreidx]));
}
if (!cores_info->wrappers2[coreidx] && (wrap2 != 0)) {
cores_info->wrappers2[coreidx] = REG_MAP(wrap2, SI_CORE_SIZE);
ASSERT(GOODREGS(cores_info->wrappers2[coreidx]));
}
if (!cores_info->wrappers3[coreidx] && (wrap3 != 0)) {
cores_info->wrappers3[coreidx] = REG_MAP(wrap3, SI_CORE_SIZE);
ASSERT(GOODREGS(cores_info->wrappers3[coreidx]));
}
if (use_wrapn == 2) {
sii->curwrap = cores_info->wrappers3[coreidx];
} else if (use_wrapn == 1) {
sii->curwrap = cores_info->wrappers2[coreidx];
} else {
sii->curwrap = cores_info->wrappers[coreidx];
}
break;
case PCI_BUS:
regs = sii->curmap;
/* point bar0 2nd 4KB window to the primary wrapper */
if (use_wrapn == 2) {
wrap = wrap3;
} else if (use_wrapn == 1) {
wrap = wrap2;
}
/* Use BAR0 Window to support dual mac chips... */
/* TODO: the other mac unit can't be supportd by the current BAR0 window.
* need to find other ways to access these cores.
*/
switch (sii->slice) {
case 0: /* main/first slice */
/* point bar0 window */
OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, addr);
if (PCIE_GEN2(sii))
OSL_PCI_WRITE_CONFIG(sii->osh, PCIE2_BAR0_WIN2, 4, wrap);
else
OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN2, 4, wrap);
break;
case 1: /* aux/second slice */
/* PCIE GEN2 only for other slices */
if (!PCIE_GEN2(sii)) {
/* other slices not supported */
SI_ERROR(("PCI GEN not supported for slice %d\n", sii->slice));
OSL_SYS_HALT();
break;
}
/* 0x4000 - 0x4fff: enum space 0x5000 - 0x5fff: wrapper space */
regs = (volatile uint8 *)regs + PCI_SEC_BAR0_WIN_OFFSET;
sii->curwrap = (void *)((uintptr)regs + SI_CORE_SIZE);
/* point bar0 window */
OSL_PCI_WRITE_CONFIG(sii->osh, PCIE2_BAR0_CORE2_WIN, 4, addr);
OSL_PCI_WRITE_CONFIG(sii->osh, PCIE2_BAR0_CORE2_WIN2, 4, wrap);
break;
case 2: /* scan/third slice */
/* PCIE GEN2 only for other slices */
if (!PCIE_GEN2(sii)) {
/* other slices not supported */
SI_ERROR(("PCI GEN not supported for slice %d\n", sii->slice));
OSL_SYS_HALT();
break;
}
/* 0x9000 - 0x9fff: enum space 0xa000 - 0xafff: wrapper space */
regs = (volatile uint8 *)regs + PCI_TER_BAR0_WIN_OFFSET;
sii->curwrap = (void *)((uintptr)regs + SI_CORE_SIZE);
/* point bar0 window */
ai_corereg(sih, sih->buscoreidx,
PCIE_TER_BAR0_WIN_REG(sih->buscorerev), ~0, addr);
ai_corereg(sih, sih->buscoreidx,
PCIE_TER_BAR0_WRAPPER_REG(sih->buscorerev), ~0, wrap);
break;
default: /* other slices */
SI_ERROR(("BAR0 Window not supported for slice %d\n", sii->slice));
OSL_SYS_HALT();
break;
}
break;
#ifdef BCMSDIO
case SPI_BUS:
case SDIO_BUS:
sii->curmap = regs = (void *)((uintptr)addr);
if (use_wrapn)
sii->curwrap = (void *)((uintptr)wrap2);
else
sii->curwrap = (void *)((uintptr)wrap);
break;
#endif /* BCMSDIO */
default:
OSL_SYS_HALT();
sii->curmap = regs = NULL;
break;
}
sii->curidx = coreidx;
if (regs) {
SI_MSG_DBG_REG(("%s: %d\n", __FUNCTION__, coreidx));
}
return regs;
}
volatile void *
BCMPOSTTRAPFN(ai_setcoreidx)(si_t *sih, uint coreidx)
{
return _ai_setcoreidx(sih, coreidx, 0);
}
volatile void *
BCMPOSTTRAPFN(ai_setcoreidx_2ndwrap)(si_t *sih, uint coreidx)
{
return _ai_setcoreidx(sih, coreidx, 1);
}
volatile void *
BCMPOSTTRAPFN(ai_setcoreidx_3rdwrap)(si_t *sih, uint coreidx)
{
return _ai_setcoreidx(sih, coreidx, 2);
}
void
ai_coreaddrspaceX(const si_t *sih, uint asidx, uint32 *addr, uint32 *size)
{
const si_info_t *sii = SI_INFO(sih);
const si_cores_info_t *cores_info = (const si_cores_info_t *)sii->cores_info;
chipcregs_t *cc = NULL;
uint32 erombase, *eromptr, *eromlim;
uint i, j, cidx;
uint32 cia, cib, nmp, nsp;
uint32 asd, addrl, addrh, sizel, sizeh;
for (i = 0; i < sii->numcores; i++) {
if (cores_info->coreid[i] == CC_CORE_ID) {
cc = (chipcregs_t *)cores_info->regs[i];
break;
}
}
if (cc == NULL)
goto error;
BCM_REFERENCE(erombase);
erombase = R_REG(sii->osh, CC_REG_ADDR(cc, EromPtrOffset));
eromptr = (uint32 *)REG_MAP(erombase, SI_CORE_SIZE);
eromlim = eromptr + (ER_REMAPCONTROL / sizeof(uint32));
cidx = sii->curidx;
cia = cores_info->cia[cidx];
cib = cores_info->cib[cidx];
nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
/* scan for cores */
while (eromptr < eromlim) {
if ((get_erom_ent(sih, &eromptr, ER_TAG, ER_CI) == cia) &&
(get_erom_ent(sih, &eromptr, 0, 0) == cib)) {
break;
}
}
/* skip master ports */
for (i = 0; i < nmp; i++)
get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
/* Skip ASDs in port 0 */
asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh, &sizel, &sizeh);
if (asd == 0) {
/* Try again to see if it is a bridge */
asd = get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl, &addrh,
&sizel, &sizeh);
}
j = 1;
do {
asd = get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl, &addrh,
&sizel, &sizeh);
j++;
} while (asd != 0);
/* Go through the ASDs for other slave ports */
for (i = 1; i < nsp; i++) {
j = 0;
do {
asd = get_asd(sih, &eromptr, i, j, AD_ST_SLAVE, &addrl, &addrh,
&sizel, &sizeh);
if (asd == 0)
break;
if (!asidx--) {
*addr = addrl;
*size = sizel;
return;
}
j++;
} while (1);
if (j == 0) {
SI_ERROR((" SP %d has no address descriptors\n", i));
break;
}
}
error:
*size = 0;
return;
}
/* Return the number of address spaces in current core */
int
ai_numaddrspaces(const si_t *sih)
{
/* TODO: Either save it or parse the EROM on demand, currently hardcode 2 */
BCM_REFERENCE(sih);
return 2;
}
/* Return the address of the nth address space in the current core
* Arguments:
* sih : Pointer to struct si_t
* spidx : slave port index
* baidx : base address index
*/
uint32
BCMPOSTTRAPFN(ai_addrspace)(const si_t *sih, uint spidx, uint baidx)
{
const si_info_t *sii = SI_INFO(sih);
const si_cores_info_t *cores_info = (const si_cores_info_t *)sii->cores_info;
uint cidx;
cidx = sii->curidx;
if (spidx == CORE_SLAVE_PORT_0) {
if (baidx == CORE_BASE_ADDR_0)
return cores_info->coresba[cidx];
else if (baidx == CORE_BASE_ADDR_1)
return cores_info->coresba2[cidx];
}
else if (spidx == CORE_SLAVE_PORT_1) {
if (baidx == CORE_BASE_ADDR_0)
return cores_info->csp2ba[cidx];
}
SI_ERROR(("ai_addrspace: Need to parse the erom again to find %d"
" base addr in %d slave port\n", baidx, spidx));
return 0;
}
/* Return the size of the nth address space in the current core
* Arguments:
* sih : Pointer to struct si_t
* spidx : slave port index
* baidx : base address index
*/
uint32
BCMPOSTTRAPFN(ai_addrspacesize)(const si_t *sih, uint spidx, uint baidx)
{
const si_info_t *sii = SI_INFO(sih);
const si_cores_info_t *cores_info = (const si_cores_info_t *)sii->cores_info;
uint cidx;
cidx = sii->curidx;
if (spidx == CORE_SLAVE_PORT_0) {
if (baidx == CORE_BASE_ADDR_0)
return cores_info->coresba_size[cidx];
else if (baidx == CORE_BASE_ADDR_1)
return cores_info->coresba2_size[cidx];
}
else if (spidx == CORE_SLAVE_PORT_1) {
if (baidx == CORE_BASE_ADDR_0)
return cores_info->csp2ba_size[cidx];
}
SI_ERROR(("ai_addrspacesize: Need to parse the erom again to find %d"
" base addr in %d slave port\n",
baidx, spidx));
return 0;
}
uint
ai_flag(si_t *sih)
{
const si_info_t *sii = SI_INFO(sih);
aidmp_t *ai;
if (PMU_DMP(sii)) {
uint idx, flag;
idx = sii->curidx;
ai_setcoreidx(sih, SI_CC_IDX);
flag = ai_flag_alt(sih);
ai_setcoreidx(sih, idx);
return flag;
}
ai = sii->curwrap;
ASSERT(ai != NULL);
return (R_REG(sii->osh, &ai->oobselouta30) & 0x1f);
}
uint
ai_flag_alt(const si_t *sih)
{
const si_info_t *sii = SI_INFO(sih);
aidmp_t *ai = sii->curwrap;
return ((R_REG(sii->osh, &ai->oobselouta30) >> AI_OOBSEL_1_SHIFT) & AI_OOBSEL_MASK);
}
void
ai_setint(const si_t *sih, int siflag)
{
BCM_REFERENCE(sih);
BCM_REFERENCE(siflag);
/* TODO: Figure out how to set interrupt mask in ai */
}
uint
BCMPOSTTRAPFN(ai_wrap_reg)(const si_t *sih, uint32 offset, uint32 mask, uint32 val)
{
const si_info_t *sii = SI_INFO(sih);
uint32 *addr = (uint32 *) ((uintptr)(sii->curwrap) + offset);
if (mask || val) {
uint32 w = R_REG(sii->osh, addr);
w &= ~mask;
w |= val;
W_REG(sii->osh, addr, w);
}
return (R_REG(sii->osh, addr));
}
uint
ai_corevendor(const si_t *sih)
{
const si_info_t *sii = SI_INFO(sih);
const si_cores_info_t *cores_info = (const si_cores_info_t *)sii->cores_info;
uint32 cia;
cia = cores_info->cia[sii->curidx];
return ((cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT);
}
uint
BCMPOSTTRAPFN(ai_corerev)(const si_t *sih)
{
const si_info_t *sii = SI_INFO(sih);
const si_cores_info_t *cores_info = (const si_cores_info_t *)sii->cores_info;
uint32 cib;
cib = cores_info->cib[sii->curidx];
return ((cib & CIB_REV_MASK) >> CIB_REV_SHIFT);
}
uint
ai_corerev_minor(const si_t *sih)
{
return (ai_core_sflags(sih, 0, 0) >> SISF_MINORREV_D11_SHIFT) &
SISF_MINORREV_D11_MASK;
}
bool
BCMPOSTTRAPFN(ai_iscoreup)(const si_t *sih)
{
const si_info_t *sii = SI_INFO(sih);
aidmp_t *ai = sii->curwrap;
return (((R_REG(sii->osh, &ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) == SICF_CLOCK_EN) &&
((R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET) == 0));
}
/*
* Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
* switch back to the original core, and return the new value.
*
* When using the silicon backplane, no fiddling with interrupts or core switches is needed.
*
* Also, when using pci/pcie, we can optimize away the core switching for pci registers
* and (on newer pci cores) chipcommon registers.
*/
uint
BCMPOSTTRAPFN(ai_corereg)(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
{
uint origidx = 0;
volatile uint32 *r = NULL;
uint w;
bcm_int_bitmask_t intr_val;
bool fast = FALSE;
si_info_t *sii = SI_INFO(sih);
si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
ASSERT_FP(GOODIDX(coreidx, sii->numcores) &&
(regoff < SI_CORE_SIZE) &&
((val & ~mask) == 0));
if (coreidx >= SI_MAXCORES)
return 0;
if (BUSTYPE(sih->bustype) == SI_BUS) {
/* If internal bus, we can always get at everything */
fast = TRUE;
/* map if does not exist */
if (!cores_info->regs[coreidx]) {
cores_info->regs[coreidx] = REG_MAP(cores_info->coresba[coreidx],
SI_CORE_SIZE);
ASSERT_FP(GOODREGS(cores_info->regs[coreidx]));
}
r = (volatile uint32 *)((volatile uchar *)cores_info->regs[coreidx] + regoff);
} else if (BUSTYPE(sih->bustype) == PCI_BUS) {
/* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
if ((cores_info->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
/* Chipc registers are mapped at 12KB */
fast = TRUE;
r = (volatile uint32 *)((volatile char *)sii->curmap +
PCI_16KB0_CCREGS_OFFSET + regoff);
} else if (sii->pub.buscoreidx == coreidx) {
/* pci registers are at either in the last 2KB of an 8KB window
* or, in pcie and pci rev 13 at 8KB
*/
fast = TRUE;
if (SI_FAST(sii))
r = (volatile uint32 *)((volatile char *)sii->curmap +
PCI_16KB0_PCIREGS_OFFSET + regoff);
else
r = (volatile uint32 *)((volatile char *)sii->curmap +
((regoff >= SBCONFIGOFF) ?
PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
regoff);
}
}
if (!fast) {
INTR_OFF(sii, &intr_val);
/* save current core index */
origidx = si_coreidx(&sii->pub);
/* switch core */
r = (volatile uint32*) ((volatile uchar*) ai_setcoreidx(&sii->pub, coreidx) +
regoff);
}
/* mask and set */
if (mask || val) {
w = (R_REG(sii->osh, r) & ~mask) | val;
W_REG(sii->osh, r, w);
}
/* readback */
w = R_REG(sii->osh, r);
if (!fast) {
/* restore core index */
if (origidx != coreidx)
ai_setcoreidx(&sii->pub, origidx);
INTR_RESTORE(sii, &intr_val);
}
return (w);
}
uint
BCMPOSTTRAPFN(ai_corereg_writearr)(si_t *sih, uint coreidx, uint regoff, uint *mask, uint *val,
uint num_vals)
{
volatile uint32 *r = NULL;
uint w, i = 0;
si_info_t *sii = SI_INFO(sih);
si_cores_info_t *cores_info = (si_cores_info_t *)sii->cores_info;
if (coreidx >= SI_MAXCORES) {
return 0;
}
ASSERT_FP(GOODIDX(coreidx, sii->numcores) &&
(regoff < SI_CORE_SIZE));
for (i = 0; i < num_vals; i++) {
ASSERT_FP(((val[i] & ~mask[i]) == 0));
}
if (BUSTYPE(sih->bustype) == SI_BUS) {
/* map if does not exist */
if (!cores_info->regs[coreidx]) {
cores_info->regs[coreidx] = REG_MAP(cores_info->coresba[coreidx],
SI_CORE_SIZE);