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bcmspibrcm.c
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/*
* Broadcom BCMSDH to gSPI Protocol Conversion Layer
*
* Copyright (C) 2023, Broadcom.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
*
* <<Broadcom-WL-IPTag/Dual:>>
*/
#ifdef BCMDONGLEHOST
#define HSMODE
#else
#endif /* BCMDONGLEHOST */
#include <typedefs.h>
#include <bcmdevs.h>
#include <bcmendian.h>
#include <bcmutils.h>
#include <osl.h>
#include <hndsoc.h>
#include <siutils.h>
#include <sbchipc.h>
#include <sbsdio.h> /* SDIO device core hardware definitions. */
#include <spid.h>
#include <bcmsdbus.h> /* bcmsdh to/from specific controller APIs */
#include <sdiovar.h> /* ioctl/iovars */
#include <sdio.h> /* SDIO Device and Protocol Specs */
#if defined(__linux__)
#include <pcicfg.h>
#endif
/* Quick NDIS hack */
#ifdef NDIS
#define inline __inline
#define PCI_CFG_VID 0
#define PCI_CFG_BAR0 0x10
#endif
#include <bcmspibrcm.h>
#ifdef BCMSPI_ANDROID
extern void spi_sendrecv(sdioh_info_t *sd, uint8 *msg_out, uint8 *msg_in, int msglen);
#endif /* BCMSPI_ANDROID */
#ifndef BCMSPI_ANDROID
#include <bcmspi.h>
#endif /* BCMSPI_ANDROID */
/* these are for the older cores... for newer cores we have control for each of them */
#define F0_RESPONSE_DELAY 16
#define F1_RESPONSE_DELAY 16
#define F2_RESPONSE_DELAY F0_RESPONSE_DELAY
#define GSPI_F0_RESP_DELAY 0
#define GSPI_F1_RESP_DELAY F1_RESPONSE_DELAY
#define GSPI_F2_RESP_DELAY 0
#define GSPI_F3_RESP_DELAY 0
#define CMDLEN 4
/* Globals */
#if defined(BCMDBG) || defined(DHD_DEBUG)
uint sd_msglevel = SDH_ERROR_VAL;
#else
uint sd_msglevel = 0;
#endif /* BCMDBG || DHD_DEBUG */
uint sd_hiok = FALSE; /* Use hi-speed mode if available? */
uint sd_sdmode = SDIOH_MODE_SPI; /* Use SD4 mode by default */
uint sd_f2_blocksize = 64; /* Default blocksize */
uint sd_divisor = 2;
uint sd_power = 1; /* Default to SD Slot powered ON */
uint sd_clock = 1; /* Default to SD Clock turned ON */
uint sd_crc = 0; /* Default to SPI CRC Check turned OFF */
uint sd_pci_slot = 0xFFFFffff; /* Used to force selection of a particular PCI slot */
uint8 spi_outbuf[SPI_MAX_PKT_LEN];
uint8 spi_inbuf[SPI_MAX_PKT_LEN];
/* 128bytes buffer is enough to clear data-not-available and program response-delay F0 bits
* assuming we will not exceed F0 response delay > 100 bytes at 48MHz.
*/
#define BUF2_PKT_LEN 128
uint8 spi_outbuf2[BUF2_PKT_LEN];
uint8 spi_inbuf2[BUF2_PKT_LEN];
#ifdef BCMSPI_ANDROID
uint *dhd_spi_lockcount = NULL;
#endif /* BCMSPI_ANDROID */
#if !(defined(SPI_PIO_RW_BIGENDIAN) && defined(SPI_PIO_32BIT_RW))
#define SPISWAP_WD4(x) bcmswap32(x);
#define SPISWAP_WD2(x) (bcmswap16(x & 0xffff)) | \
(bcmswap16((x & 0xffff0000) >> 16) << 16);
#else
/* Some SPI host controller changes endianness when writing/reading
* to/from SPI device TX/RX register in case the bits_per_word is more than 1 byte.
*/
#define SPISWAP_WD4(x) x;
#define SPISWAP_WD2(x) bcmswap32by16(x);
#endif
/* Prototypes */
static bool bcmspi_test_card(sdioh_info_t *sd);
static bool bcmspi_host_device_init_adapt(sdioh_info_t *sd);
static int bcmspi_set_highspeed_mode(sdioh_info_t *sd, bool hsmode);
static int bcmspi_cmd_issue(sdioh_info_t *sd, bool use_dma, uint32 cmd_arg,
uint32 *data, uint32 datalen);
static int bcmspi_card_regread(sdioh_info_t *sd, int func, uint32 regaddr,
int regsize, uint32 *data);
static int bcmspi_card_regwrite(sdioh_info_t *sd, int func, uint32 regaddr,
int regsize, uint32 data);
static int bcmspi_card_bytewrite(sdioh_info_t *sd, int func, uint32 regaddr,
uint8 *data);
static int bcmspi_driver_init(sdioh_info_t *sd);
static int bcmspi_card_buf(sdioh_info_t *sd, int rw, int func, bool fifo,
uint32 addr, int nbytes, uint32 *data);
static int bcmspi_card_regread_fixedaddr(sdioh_info_t *sd, int func, uint32 regaddr, int regsize,
uint32 *data);
static void bcmspi_cmd_getdstatus(sdioh_info_t *sd, uint32 *dstatus_buffer);
static int bcmspi_update_stats(sdioh_info_t *sd, uint32 cmd_arg);
/*
* Public entry points & extern's
*/
extern sdioh_info_t *
sdioh_attach(osl_t *osh, void *bar0, uint irq)
{
sdioh_info_t *sd;
sd_trace(("%s\n", __FUNCTION__));
if ((sd = (sdioh_info_t *)MALLOC(osh, sizeof(sdioh_info_t))) == NULL) {
sd_err(("%s: out of memory, malloced %d bytes\n", __FUNCTION__, MALLOCED(osh)));
return NULL;
}
bzero((char *)sd, sizeof(sdioh_info_t));
sd->osh = osh;
if (spi_osinit(sd) != 0) {
sd_err(("%s: spi_osinit() failed\n", __FUNCTION__));
MFREE(sd->osh, sd, sizeof(sdioh_info_t));
return NULL;
}
#ifndef BCMSPI_ANDROID
sd->bar0 = bar0;
#endif /* !BCMSPI_ANDROID */
sd->irq = irq;
#ifndef BCMSPI_ANDROID
sd->intr_handler = NULL;
sd->intr_handler_arg = NULL;
sd->intr_handler_valid = FALSE;
#endif /* !BCMSPI_ANDROID */
/* Set defaults */
sd->use_client_ints = TRUE;
sd->sd_use_dma = FALSE; /* DMA Not supported */
/* Spi device default is 16bit mode, change to 4 when device is changed to 32bit
* mode
*/
sd->wordlen = 2;
#ifdef BCMSPI_ANDROID
dhd_spi_lockcount = &sd->lockcount;
#endif /* BCMSPI_ANDROID */
#ifndef BCMSPI_ANDROID
if (!spi_hw_attach(sd)) {
sd_err(("%s: spi_hw_attach() failed\n", __FUNCTION__));
spi_osfree(sd);
MFREE(sd->osh, sd, sizeof(sdioh_info_t));
return (NULL);
}
#endif /* !BCMSPI_ANDROID */
if (bcmspi_driver_init(sd) != SUCCESS) {
sd_err(("%s: bcmspi_driver_init() failed()\n", __FUNCTION__));
#ifndef BCMSPI_ANDROID
spi_hw_detach(sd);
#endif /* !BCMSPI_ANDROID */
spi_osfree(sd);
MFREE(sd->osh, sd, sizeof(sdioh_info_t));
return (NULL);
}
if (spi_register_irq(sd, irq) != SUCCESS) {
sd_err(("%s: spi_register_irq() failed for irq = %d\n", __FUNCTION__, irq));
#ifndef BCMSPI_ANDROID
spi_hw_detach(sd);
#endif /* !BCMSPI_ANDROID */
spi_osfree(sd);
MFREE(sd->osh, sd, sizeof(sdioh_info_t));
return (NULL);
}
sd_trace(("%s: Done\n", __FUNCTION__));
return sd;
}
extern SDIOH_API_RC
sdioh_detach(osl_t *osh, sdioh_info_t *sd)
{
sd_trace(("%s\n", __FUNCTION__));
if (sd) {
sd_err(("%s: detaching from hardware\n", __FUNCTION__));
spi_free_irq(sd->irq, sd);
#ifndef BCMSPI_ANDROID
spi_hw_detach(sd);
#endif /* !BCMSPI_ANDROID */
spi_osfree(sd);
#ifdef BCMSPI_ANDROID
dhd_spi_lockcount = NULL;
#endif /* BCMSPI_ANDROID */
MFREE(sd->osh, sd, sizeof(sdioh_info_t));
}
return SDIOH_API_RC_SUCCESS;
}
/* Configure callback to client when we receive client interrupt */
extern SDIOH_API_RC
sdioh_interrupt_register(sdioh_info_t *sd, sdioh_cb_fn_t fn, void *argh)
{
sd_trace(("%s: Entering\n", __FUNCTION__));
#if !defined(OOB_INTR_ONLY)
sd->intr_handler = fn;
sd->intr_handler_arg = argh;
sd->intr_handler_valid = TRUE;
#endif /* !defined(OOB_INTR_ONLY) */
return SDIOH_API_RC_SUCCESS;
}
extern SDIOH_API_RC
sdioh_interrupt_deregister(sdioh_info_t *sd)
{
sd_trace(("%s: Entering\n", __FUNCTION__));
#if !defined(OOB_INTR_ONLY)
sd->intr_handler_valid = FALSE;
sd->intr_handler = NULL;
sd->intr_handler_arg = NULL;
#endif /* !defined(OOB_INTR_ONLY) */
return SDIOH_API_RC_SUCCESS;
}
extern SDIOH_API_RC
sdioh_interrupt_query(sdioh_info_t *sd, bool *onoff)
{
#ifndef BCMSPI_ANDROID
sd_trace(("%s: Entering\n", __FUNCTION__));
*onoff = sd->client_intr_enabled;
#endif /* !BCMSPI_ANDROID */
return SDIOH_API_RC_SUCCESS;
}
#if defined(DHD_DEBUG) || defined(BCMDBG)
extern bool
sdioh_interrupt_pending(sdioh_info_t *sd)
{
return 0;
}
#endif
/* Provide dstatus bits of spi-transaction for dhd layers. */
extern uint32
sdioh_get_dstatus(sdioh_info_t *sd)
{
return sd->card_dstatus;
}
extern void
sdioh_chipinfo(sdioh_info_t *sd, uint32 chip, uint32 chiprev)
{
sd->chip = chip;
sd->chiprev = chiprev;
}
extern void
sdioh_dwordmode(sdioh_info_t *sd, bool set)
{
uint8 reg = 0;
int status;
if ((status = sdioh_request_byte(sd, SDIOH_READ, SPI_FUNC_0, SPID_STATUS_ENABLE, ®)) !=
SUCCESS) {
sd_err(("%s: Failed to set dwordmode in gSPI\n", __FUNCTION__));
return;
}
if (set) {
reg |= DWORD_PKT_LEN_EN;
sd->dwordmode = TRUE;
sd->client_block_size[SPI_FUNC_2] = 4096; /* h2spi's limit is 4KB, we support 8KB */
} else {
reg &= ~DWORD_PKT_LEN_EN;
sd->dwordmode = FALSE;
sd->client_block_size[SPI_FUNC_2] = 2048;
}
if ((status = sdioh_request_byte(sd, SDIOH_WRITE, SPI_FUNC_0, SPID_STATUS_ENABLE, ®)) !=
SUCCESS) {
sd_err(("%s: Failed to set dwordmode in gSPI\n", __FUNCTION__));
return;
}
}
uint
sdioh_query_iofnum(sdioh_info_t *sd)
{
return sd->num_funcs;
}
/* IOVar table */
enum {
IOV_MSGLEVEL = 1,
IOV_BLOCKMODE,
IOV_BLOCKSIZE,
IOV_DMA,
IOV_USEINTS,
IOV_NUMINTS,
IOV_NUMLOCALINTS,
IOV_HOSTREG,
IOV_DEVREG,
IOV_DIVISOR,
IOV_SDMODE,
IOV_HISPEED,
IOV_HCIREGS,
IOV_POWER,
IOV_CLOCK,
IOV_SPIERRSTATS,
IOV_RESP_DELAY_ALL
};
const bcm_iovar_t sdioh_iovars[] = {
{"sd_msglevel", IOV_MSGLEVEL, 0, IOVT_UINT32, 0 },
{"sd_blocksize", IOV_BLOCKSIZE, 0, IOVT_UINT32, 0 }, /* ((fn << 16) | size) */
{"sd_dma", IOV_DMA, 0, IOVT_BOOL, 0 },
{"sd_ints", IOV_USEINTS, 0, IOVT_BOOL, 0 },
{"sd_numints", IOV_NUMINTS, 0, IOVT_UINT32, 0 },
{"sd_numlocalints", IOV_NUMLOCALINTS, 0, IOVT_UINT32, 0 },
{"sd_hostreg", IOV_HOSTREG, 0, IOVT_BUFFER, sizeof(sdreg_t) },
{"sd_devreg", IOV_DEVREG, 0, IOVT_BUFFER, sizeof(sdreg_t) },
{"sd_divisor", IOV_DIVISOR, 0, IOVT_UINT32, 0 },
{"sd_power", IOV_POWER, 0, IOVT_UINT32, 0 },
{"sd_clock", IOV_CLOCK, 0, IOVT_UINT32, 0 },
{"sd_mode", IOV_SDMODE, 0, IOVT_UINT32, 100},
{"sd_highspeed", IOV_HISPEED, 0, IOVT_UINT32, 0},
#ifdef BCMDBG
{"sd_hciregs", IOV_HCIREGS, 0, IOVT_BUFFER, 0 },
#endif
{"spi_errstats", IOV_SPIERRSTATS, 0, IOVT_BUFFER, sizeof(struct spierrstats_t) },
{"spi_respdelay", IOV_RESP_DELAY_ALL, 0, IOVT_BOOL, 0 },
{NULL, 0, 0, 0, 0 }
};
int
sdioh_iovar_op(sdioh_info_t *si, const char *name,
void *params, int plen, void *arg, uint len, bool set)
{
const bcm_iovar_t *vi = NULL;
int bcmerror = 0;
uint val_size;
int32 int_val = 0;
bool bool_val;
uint32 actionid;
/*
sdioh_regs_t *regs;
*/
ASSERT(name);
ASSERT(len >= 0);
/* Get must have return space; Set does not take qualifiers */
ASSERT(set || (arg && len));
ASSERT(!set || (!params && !plen));
sd_trace(("%s: Enter (%s %s)\n", __FUNCTION__, (set ? "set" : "get"), name));
if ((vi = bcm_iovar_lookup(sdioh_iovars, name)) == NULL) {
bcmerror = BCME_UNSUPPORTED;
goto exit;
}
if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, set)) != 0)
goto exit;
/* Copied from dhd, copied from wl; certainly overkill here? */
/* Set up params so get and set can share the convenience variables */
if (params == NULL) {
params = arg;
plen = len;
}
if (vi->type == IOVT_VOID)
val_size = 0;
else if (vi->type == IOVT_BUFFER)
val_size = len;
else
val_size = sizeof(int);
if (plen >= (int)sizeof(int_val))
bcopy(params, &int_val, sizeof(int_val));
bool_val = (int_val != 0) ? TRUE : FALSE;
actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
switch (actionid) {
case IOV_GVAL(IOV_MSGLEVEL):
int_val = (int32)sd_msglevel;
bcopy(&int_val, arg, val_size);
break;
case IOV_SVAL(IOV_MSGLEVEL):
sd_msglevel = int_val;
break;
case IOV_GVAL(IOV_BLOCKSIZE):
if ((uint32)int_val > si->num_funcs) {
bcmerror = BCME_BADARG;
break;
}
int_val = (int32)si->client_block_size[int_val];
bcopy(&int_val, arg, val_size);
break;
case IOV_GVAL(IOV_DMA):
int_val = (int32)si->sd_use_dma;
bcopy(&int_val, arg, val_size);
break;
case IOV_SVAL(IOV_DMA):
si->sd_use_dma = (bool)int_val;
break;
case IOV_GVAL(IOV_USEINTS):
int_val = (int32)si->use_client_ints;
bcopy(&int_val, arg, val_size);
break;
case IOV_SVAL(IOV_USEINTS):
break;
case IOV_GVAL(IOV_DIVISOR):
int_val = (uint32)sd_divisor;
bcopy(&int_val, arg, val_size);
break;
#ifndef BCMSPI_ANDROID
case IOV_SVAL(IOV_DIVISOR):
sd_divisor = int_val;
if (!spi_start_clock(si, (uint16)sd_divisor)) {
sd_err(("%s: set clock failed\n", __FUNCTION__));
bcmerror = BCME_ERROR;
}
break;
#endif /* !BCMSPI_ANDROID */
case IOV_GVAL(IOV_POWER):
int_val = (uint32)sd_power;
bcopy(&int_val, arg, val_size);
break;
case IOV_SVAL(IOV_POWER):
sd_power = int_val;
break;
case IOV_GVAL(IOV_CLOCK):
int_val = (uint32)sd_clock;
bcopy(&int_val, arg, val_size);
break;
case IOV_SVAL(IOV_CLOCK):
sd_clock = int_val;
break;
case IOV_GVAL(IOV_SDMODE):
int_val = (uint32)sd_sdmode;
bcopy(&int_val, arg, val_size);
break;
case IOV_SVAL(IOV_SDMODE):
sd_sdmode = int_val;
break;
case IOV_GVAL(IOV_HISPEED):
int_val = (uint32)sd_hiok;
bcopy(&int_val, arg, val_size);
break;
case IOV_SVAL(IOV_HISPEED):
sd_hiok = int_val;
if (!bcmspi_set_highspeed_mode(si, (bool)sd_hiok)) {
sd_err(("%s: Failed changing highspeed mode to %d.\n",
__FUNCTION__, sd_hiok));
bcmerror = BCME_ERROR;
return ERROR;
}
break;
case IOV_GVAL(IOV_NUMINTS):
int_val = (int32)si->intrcount;
bcopy(&int_val, arg, val_size);
break;
case IOV_GVAL(IOV_NUMLOCALINTS):
int_val = (int32)si->local_intrcount;
bcopy(&int_val, arg, val_size);
break;
case IOV_GVAL(IOV_DEVREG):
{
/* Should copy for alignment reasons */
sdreg_t *sd_ptr = (sdreg_t *)params;
uint8 data;
if (sdioh_cfg_read(si, sd_ptr->func, sd_ptr->offset, &data)) {
bcmerror = BCME_SDIO_ERROR;
break;
}
int_val = (int)data;
bcopy(&int_val, arg, sizeof(int_val));
break;
}
case IOV_SVAL(IOV_DEVREG):
{
/* Should copy for alignment reasons */
sdreg_t *sd_ptr = (sdreg_t *)params;
uint8 data = (uint8)sd_ptr->value;
if (sdioh_cfg_write(si, sd_ptr->func, sd_ptr->offset, &data)) {
bcmerror = BCME_SDIO_ERROR;
break;
}
break;
}
#ifdef BCMDBG
case IOV_GVAL(IOV_HCIREGS):
{
struct bcmstrbuf b;
bcm_binit(&b, arg, len);
spi_lock(si);
bcm_bprintf(&b, "Unsupported\n");
spi_unlock(si);
if (!b.size)
bcmerror = BCME_BUFTOOSHORT;
break;
}
#endif /* BCMDBG */
case IOV_GVAL(IOV_SPIERRSTATS):
{
bcopy(&si->spierrstats, arg, sizeof(struct spierrstats_t));
break;
}
case IOV_SVAL(IOV_SPIERRSTATS):
{
bzero(&si->spierrstats, sizeof(struct spierrstats_t));
break;
}
case IOV_GVAL(IOV_RESP_DELAY_ALL):
int_val = (int32)si->resp_delay_all;
bcopy(&int_val, arg, val_size);
break;
case IOV_SVAL(IOV_RESP_DELAY_ALL):
si->resp_delay_all = (bool)int_val;
int_val = STATUS_ENABLE|INTR_WITH_STATUS;
if (si->resp_delay_all)
int_val |= RESP_DELAY_ALL;
else {
if (bcmspi_card_regwrite(si, SPI_FUNC_0, SPID_RESPONSE_DELAY, 1,
F1_RESPONSE_DELAY) != SUCCESS) {
sd_err(("%s: Unable to set response delay.\n", __FUNCTION__));
bcmerror = BCME_SDIO_ERROR;
break;
}
}
if (bcmspi_card_regwrite(si, SPI_FUNC_0, SPID_STATUS_ENABLE, 1, int_val)
!= SUCCESS) {
sd_err(("%s: Unable to set response delay.\n", __FUNCTION__));
bcmerror = BCME_SDIO_ERROR;
break;
}
break;
default:
bcmerror = BCME_UNSUPPORTED;
break;
}
exit:
/* Remove protective lock after clients all clean... */
return bcmerror;
}
extern SDIOH_API_RC
sdioh_cfg_read(sdioh_info_t *sd, uint fnc_num, uint32 addr, uint8 *data)
{
SDIOH_API_RC status;
/* No lock needed since sdioh_request_byte does locking */
status = sdioh_request_byte(sd, SDIOH_READ, fnc_num, addr, data);
return status;
}
extern SDIOH_API_RC
sdioh_cfg_write(sdioh_info_t *sd, uint fnc_num, uint32 addr, uint8 *data)
{
/* No lock needed since sdioh_request_byte does locking */
SDIOH_API_RC status;
/* WAR for gSPI for PR55208: Read SFC_WF_TERM before write for write to be
* successful on address SBSDIO_FUNC1_FRAMECTRL.
*/
if ((fnc_num == SPI_FUNC_1) && (addr == SBSDIO_FUNC1_FRAMECTRL)) {
uint8 dummy_data;
status = sdioh_cfg_read(sd, fnc_num, addr, &dummy_data);
if (status) {
sd_err(("sdioh_cfg_read() failed.\n"));
return status;
}
}
status = sdioh_request_byte(sd, SDIOH_WRITE, fnc_num, addr, data);
return status;
}
extern SDIOH_API_RC
sdioh_cis_read(sdioh_info_t *sd, uint func, uint8 *cisd, uint32 length)
{
uint32 count;
int offset;
uint32 cis_byte;
uint16 *cis = (uint16 *)cisd;
uint bar0 = SI_ENUM_BASE(sd->sih);
int status;
uint8 data;
sd_trace(("%s: Func %d\n", __FUNCTION__, func));
spi_lock(sd);
/* Set sb window address to 0x18000000 */
data = (bar0 >> 8) & SBSDIO_SBADDRLOW_MASK;
status = bcmspi_card_bytewrite(sd, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW, &data);
if (status == SUCCESS) {
data = (bar0 >> 16) & SBSDIO_SBADDRMID_MASK;
status = bcmspi_card_bytewrite(sd, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID, &data);
} else {
sd_err(("%s: Unable to set sb-addr-windows\n", __FUNCTION__));
spi_unlock(sd);
return (BCME_ERROR);
}
if (status == SUCCESS) {
data = (bar0 >> 24) & SBSDIO_SBADDRHIGH_MASK;
status = bcmspi_card_bytewrite(sd, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH, &data);
} else {
sd_err(("%s: Unable to set sb-addr-windows\n", __FUNCTION__));
spi_unlock(sd);
return (BCME_ERROR);
}
offset = CC_REG_OFF(sromotp); /* OTP offset in chipcommon. */
for (count = 0; count < length/2; count++) {
if (bcmspi_card_regread (sd, SDIO_FUNC_1, offset, 2, &cis_byte) < 0) {
sd_err(("%s: regread failed: Can't read CIS\n", __FUNCTION__));
spi_unlock(sd);
return (BCME_ERROR);
}
*cis = (uint16)cis_byte;
cis++;
offset += 2;
}
spi_unlock(sd);
return (BCME_OK);
}
extern SDIOH_API_RC
sdioh_request_byte(sdioh_info_t *sd, uint rw, uint func, uint regaddr, uint8 *byte)
{
int status;
uint32 cmd_arg;
uint32 dstatus;
uint32 data = (uint32)(*byte);
spi_lock(sd);
cmd_arg = 0;
cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1); /* Incremental access */
cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, rw == SDIOH_READ ? 0 : 1);
cmd_arg = SFIELD(cmd_arg, SPI_LEN, 1);
if (rw == SDIOH_READ) {
sd_trace(("%s: RD cmd_arg=0x%x func=%d regaddr=0x%x\n",
__FUNCTION__, cmd_arg, func, regaddr));
} else {
sd_trace(("%s: WR cmd_arg=0x%x func=%d regaddr=0x%x data=0x%x\n",
__FUNCTION__, cmd_arg, func, regaddr, data));
}
if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, &data, 1)) != SUCCESS) {
spi_unlock(sd);
return status;
}
if (rw == SDIOH_READ) {
*byte = (uint8)data;
sd_trace(("%s: RD result=0x%x\n", __FUNCTION__, *byte));
}
bcmspi_cmd_getdstatus(sd, &dstatus);
if (dstatus)
sd_trace(("dstatus=0x%x\n", dstatus));
spi_unlock(sd);
return SDIOH_API_RC_SUCCESS;
}
extern SDIOH_API_RC
sdioh_request_word(sdioh_info_t *sd, uint cmd_type, uint rw, uint func, uint addr,
uint32 *word, uint nbytes)
{
int status;
spi_lock(sd);
if (rw == SDIOH_READ)
status = bcmspi_card_regread(sd, func, addr, nbytes, word);
else
status = bcmspi_card_regwrite(sd, func, addr, nbytes, *word);
spi_unlock(sd);
return (status == SUCCESS ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
}
extern SDIOH_API_RC
sdioh_request_buffer(sdioh_info_t *sd, uint pio_dma, uint fix_inc, uint rw, uint func,
uint addr, uint reg_width, uint buflen_u, uint8 *buffer, void *pkt)
{
int len;
int buflen = (int)buflen_u;
bool fifo = (fix_inc == SDIOH_DATA_FIX);
spi_lock(sd);
ASSERT(reg_width == 4);
ASSERT(buflen_u < (1 << 30));
ASSERT(sd->client_block_size[func]);
sd_data(("%s: %c len %d r_cnt %d t_cnt %d, pkt @0x%p\n",
__FUNCTION__, rw == SDIOH_READ ? 'R' : 'W',
buflen_u, sd->r_cnt, sd->t_cnt, pkt));
/* Break buffer down into blocksize chunks. */
while (buflen > 0) {
len = MIN(sd->client_block_size[func], buflen);
if (bcmspi_card_buf(sd, rw, func, fifo, addr, len, (uint32 *)buffer) != SUCCESS) {
sd_err(("%s: bcmspi_card_buf %s failed\n",
__FUNCTION__, rw == SDIOH_READ ? "Read" : "Write"));
spi_unlock(sd);
return SDIOH_API_RC_FAIL;
}
buffer += len;
buflen -= len;
if (!fifo)
addr += len;
}
spi_unlock(sd);
return SDIOH_API_RC_SUCCESS;
}
/* This function allows write to gspi bus when another rd/wr function is deep down the call stack.
* Its main aim is to have simpler spi writes rather than recursive writes.
* e.g. When there is a need to program response delay on the fly after detecting the SPI-func
* this call will allow to program the response delay.
*/
static int
bcmspi_card_byterewrite(sdioh_info_t *sd, int func, uint32 regaddr, uint8 byte)
{
uint32 cmd_arg;
uint32 datalen = 1;
uint32 hostlen;
cmd_arg = 0;
cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 1);
cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1); /* Incremental access */
cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
cmd_arg = SFIELD(cmd_arg, SPI_LEN, datalen);
sd_trace(("%s cmd_arg = 0x%x\n", __FUNCTION__, cmd_arg));
#ifdef BCMDBG
/* Fill up buffers with a value that generates known dutycycle on MOSI/MISO lines. */
memset(spi_outbuf2, 0xee, BUF2_PKT_LEN);
memset(spi_inbuf2, 0xee, BUF2_PKT_LEN);
#endif /* BCMDBG */
/* Set up and issue the SPI command. MSByte goes out on bus first. Increase datalen
* according to the wordlen mode(16/32bit) the device is in.
*/
ASSERT(sd->wordlen == 4 || sd->wordlen == 2);
datalen = ROUNDUP(datalen, sd->wordlen);
/* Start by copying command in the spi-outbuffer */
if (sd->wordlen == 4) { /* 32bit spid */
*(uint32 *)spi_outbuf2 = SPISWAP_WD4(cmd_arg);
if (datalen & 0x3)
datalen += (4 - (datalen & 0x3));
} else if (sd->wordlen == 2) { /* 16bit spid */
*(uint32 *)spi_outbuf2 = SPISWAP_WD2(cmd_arg);
if (datalen & 0x1)
datalen++;
} else {
sd_err(("%s: Host is %d bit spid, could not create SPI command.\n",
__FUNCTION__, 8 * sd->wordlen));
return ERROR;
}
/* for Write, put the data into the output buffer */
if (datalen != 0) {
if (sd->wordlen == 4) { /* 32bit spid */
*(uint32 *)&spi_outbuf2[CMDLEN] = SPISWAP_WD4(byte);
} else if (sd->wordlen == 2) { /* 16bit spid */
*(uint32 *)&spi_outbuf2[CMDLEN] = SPISWAP_WD2(byte);
}
}
/* +4 for cmd, +4 for dstatus */
hostlen = datalen + 8;
hostlen += (4 - (hostlen & 0x3));
spi_sendrecv(sd, spi_outbuf2, spi_inbuf2, hostlen);
/* Last 4bytes are dstatus. Device is configured to return status bits. */
if (sd->wordlen == 4) { /* 32bit spid */
sd->card_dstatus = SPISWAP_WD4(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
} else if (sd->wordlen == 2) { /* 16bit spid */
sd->card_dstatus = SPISWAP_WD2(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
} else {
sd_err(("%s: Host is %d bit machine, could not read SPI dstatus.\n",
__FUNCTION__, 8 * sd->wordlen));
return ERROR;
}
if (sd->card_dstatus)
sd_trace(("dstatus after byte rewrite = 0x%x\n", sd->card_dstatus));
return (BCME_OK);
}
/* Program the response delay corresponding to the spi function */
static int
bcmspi_prog_resp_delay(sdioh_info_t *sd, int func, uint8 resp_delay)
{
if (sd->resp_delay_all == FALSE)
return (BCME_OK);
if (sd->prev_fun == func)
return (BCME_OK);
if (F0_RESPONSE_DELAY == F1_RESPONSE_DELAY)
return (BCME_OK);
bcmspi_card_byterewrite(sd, SPI_FUNC_0, SPID_RESPONSE_DELAY, resp_delay);
/* Remember function for which to avoid reprogramming resp-delay in next iteration */
sd->prev_fun = func;
return (BCME_OK);
}
#define GSPI_RESYNC_PATTERN 0x0
/* A resync pattern is a 32bit MOSI line with all zeros. Its a special command in gSPI.
* It resets the spi-bkplane logic so that all F1 related ping-pong buffer logic is
* synchronised and all queued resuests are cancelled.
*/
static int
bcmspi_resync_f1(sdioh_info_t *sd)
{
uint32 cmd_arg = GSPI_RESYNC_PATTERN, data = 0, datalen = 0;
#ifdef BCMDBG
/* Fill up buffers with a value that generates known dutycycle on MOSI/MISO lines. */
memset(spi_outbuf2, 0xee, BUF2_PKT_LEN);
memset(spi_inbuf2, 0xee, BUF2_PKT_LEN);
#endif /* BCMDBG */
/* Set up and issue the SPI command. MSByte goes out on bus first. Increase datalen
* according to the wordlen mode(16/32bit) the device is in.
*/
ASSERT(sd->wordlen == 4 || sd->wordlen == 2);
datalen = ROUNDUP(datalen, sd->wordlen);
/* Start by copying command in the spi-outbuffer */
*(uint32 *)spi_outbuf2 = cmd_arg;
/* for Write, put the data into the output buffer */
*(uint32 *)&spi_outbuf2[CMDLEN] = data;
/* +4 for cmd, +4 for dstatus */
spi_sendrecv(sd, spi_outbuf2, spi_inbuf2, datalen + 8);
/* Last 4bytes are dstatus. Device is configured to return status bits. */
if (sd->wordlen == 4) { /* 32bit spid */
sd->card_dstatus = SPISWAP_WD4(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
} else if (sd->wordlen == 2) { /* 16bit spid */
sd->card_dstatus = SPISWAP_WD2(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
} else {
sd_err(("%s: Host is %d bit machine, could not read SPI dstatus.\n",
__FUNCTION__, 8 * sd->wordlen));
return ERROR;
}
if (sd->card_dstatus)
sd_trace(("dstatus after resync pattern write = 0x%x\n", sd->card_dstatus));
return (BCME_OK);
}
uint32 dstatus_count = 0;
static int
bcmspi_update_stats(sdioh_info_t *sd, uint32 cmd_arg)
{
uint32 dstatus = sd->card_dstatus;
struct spierrstats_t *spierrstats = &sd->spierrstats;
int err = SUCCESS;
sd_trace(("cmd = 0x%x, dstatus = 0x%x\n", cmd_arg, dstatus));
/* Store dstatus of last few gSPI transactions */
spierrstats->dstatus[dstatus_count % NUM_PREV_TRANSACTIONS] = dstatus;
spierrstats->spicmd[dstatus_count % NUM_PREV_TRANSACTIONS] = cmd_arg;
dstatus_count++;
if (sd->card_init_done == FALSE)
return err;
if (dstatus & STATUS_DATA_NOT_AVAILABLE) {
spierrstats->dna++;
sd_trace(("Read data not available on F1 addr = 0x%x\n",
GFIELD(cmd_arg, SPI_REG_ADDR)));
/* Clear dna bit */
bcmspi_card_byterewrite(sd, SPI_FUNC_0, SPID_INTR_REG, DATA_UNAVAILABLE);
}
if (dstatus & STATUS_UNDERFLOW) {
spierrstats->rdunderflow++;
sd_err(("FIFO underflow happened due to current F2 read command.\n"));
}
if (dstatus & STATUS_OVERFLOW) {
spierrstats->wroverflow++;
sd_err(("FIFO overflow happened due to current (F1/F2) write command.\n"));
bcmspi_card_byterewrite(sd, SPI_FUNC_0, SPID_INTR_REG, F1_OVERFLOW);
bcmspi_resync_f1(sd);
sd_err(("Recovering from F1 FIFO overflow.\n"));
}
if (dstatus & STATUS_F2_INTR) {
spierrstats->f2interrupt++;
sd_trace(("Interrupt from F2. SW should clear corresponding IntStatus bits\n"));
}