spi: ast2700: Adjust the minimum initial segment window size

On AST2700, due to limited bus memory space, no extra address space
is allocated for SPI memory. As a result, the SSP CPU accesses SPI
memory directly through SPI controller registers. The HW
automatically redirects accesses from the SPI controller register
space to SPI memory. Register offsets starting at 0x200 correspond
to SPI memory, where each byte represents 16MB.

When the FMC CS0 segment window size is 16MB and SSP needs to access
CS1, it must access offset 0x201, including for write operations.
However, the SPI controller does not support byte-aligned
write accesses. Therefore, each segment window must be 64MB aligned
to ensure proper 4-byte accesses by the SPI controller.

Signed-off-by: Chin-Ting Kuo <[email protected]>
Change-Id: I61c82b0570295a1077a21039c1a936c98464d062

Author: chintingkuo

drivers/spi/spi_aspeed_ast2700.c

@@ -95,6 +95,7 @@ LOG_MODULE_REGISTER(spi_aspeed, CONFIG_SPI_LOG_LEVEL);
 #define ASPEED_SPI_USER_INACTIVE    BIT(2)
 
 #define ASPEED_SPI_SZ_16M           0x1000000
+#define ASPEED_SPI_SZ_64M           0x4000000
 #define ASPEED_SPI_SZ_768M          0x30000000
 
 #define ASPEED_DRAM_PHY_BASE        0x400000000
@@ -1025,7 +1026,7 @@ void aspeed_decode_range_pre_init(const struct aspeed_spi_config *config,
 				  struct aspeed_spi_data *data)
 {
 	uint32_t cs;
-	uint32_t unit_sz = ASPEED_SPI_SZ_16M; /* init 256M for each cs */
+	uint32_t unit_sz = ASPEED_SPI_SZ_64M;
 	uint32_t start_addr, end_addr, pre_end_addr = 0;
 	uint32_t max_cs = config->max_cs;