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| 1 | +<?xml version="1.0"?> |
| 2 | + |
| 3 | +<!-- Based on https://github.com/Gigallith/gdb-tricore/blob/main/gdb/features/tricore-core.xml |
| 4 | + Modified according to rizin's TriCore plugin and QEMU's TriCore implementation. |
| 5 | + Added several special registers (syscon, cpu_id, core_id, biv, btv, isp, fcx, lcx, compat, |
| 6 | + pmucon0, cycles, instr, time). --> |
| 7 | + |
| 8 | +<!-- Copyright (C) 2019 Free Software Foundation, Inc. |
| 9 | +
|
| 10 | + Copying and distribution of this file, with or without modification, |
| 11 | + are permitted in any medium without royalty provided the copyright |
| 12 | + notice and this notice are preserved. --> |
| 13 | + |
| 14 | +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> |
| 15 | +<feature name="org.gnu.gdb.tricore.core"> |
| 16 | + <reg name="a0" bitsize="32" type="data_ptr"/> |
| 17 | + <reg name="a1" bitsize="32" type="uint32"/> |
| 18 | + <reg name="a2" bitsize="32" type="uint32"/> |
| 19 | + <reg name="a3" bitsize="32" type="uint32"/> |
| 20 | + <reg name="a4" bitsize="32" type="uint32"/> |
| 21 | + <reg name="a5" bitsize="32" type="uint32"/> |
| 22 | + <reg name="a6" bitsize="32" type="uint32"/> |
| 23 | + <reg name="a7" bitsize="32" type="uint32"/> |
| 24 | + <reg name="a8" bitsize="32" type="uint32"/> |
| 25 | + <reg name="a9" bitsize="32" type="uint32"/> |
| 26 | + <reg name="a10" bitsize="32" type="uint32"/> |
| 27 | + <reg name="a11" bitsize="32" type="uint32"/> |
| 28 | + <reg name="a12" bitsize="32" type="uint32"/> |
| 29 | + <reg name="a13" bitsize="32" type="uint32"/> |
| 30 | + <reg name="a14" bitsize="32" type="uint32"/> |
| 31 | + <reg name="a15" bitsize="32" type="uint32"/> |
| 32 | + |
| 33 | + <reg name="d0" bitsize="32" type="data_ptr"/> |
| 34 | + <reg name="d1" bitsize="32" type="uint32"/> |
| 35 | + <reg name="d2" bitsize="32" type="uint32"/> |
| 36 | + <reg name="d3" bitsize="32" type="uint32"/> |
| 37 | + <reg name="d4" bitsize="32" type="uint32"/> |
| 38 | + <reg name="d5" bitsize="32" type="uint32"/> |
| 39 | + <reg name="d6" bitsize="32" type="uint32"/> |
| 40 | + <reg name="d7" bitsize="32" type="uint32"/> |
| 41 | + <reg name="d8" bitsize="32" type="uint32"/> |
| 42 | + <reg name="d9" bitsize="32" type="uint32"/> |
| 43 | + <reg name="d10" bitsize="32" type="uint32"/> |
| 44 | + <reg name="d11" bitsize="32" type="uint32"/> |
| 45 | + <reg name="d12" bitsize="32" type="uint32"/> |
| 46 | + <reg name="d13" bitsize="32" type="uint32"/> |
| 47 | + <reg name="d14" bitsize="32" type="uint32"/> |
| 48 | + <reg name="d15" bitsize="32" type="uint32"/> |
| 49 | + |
| 50 | + <flags id="psw_flags" size="4"> |
| 51 | + <field name="CDC" start="0" end="6"/> |
| 52 | + <field name="CDE" start="7" end="8"/> |
| 53 | + <field name="C" start="31" end="31"/> |
| 54 | + <field name="V" start="30" end="30"/> |
| 55 | + <field name="SV" start="29" end="29"/> |
| 56 | + <field name="AV" start="28" end="28"/> |
| 57 | + <field name="SAV" start="27" end="27"/> |
| 58 | + <field name="RM" start="24" end="25"/> |
| 59 | + <field name="PRS" start="12" end="13"/> |
| 60 | + <field name="IO" start="10" end="11"/> |
| 61 | + <field name="IS" start="9" end="9"/> |
| 62 | + <field name="GW" start="8" end="8"/> |
| 63 | + </flags> |
| 64 | + |
| 65 | + <reg name="pcxi" bitsize="32" type="data_ptr"/> |
| 66 | + <reg name="psw" bitsize="32" type="psw_flags"/> |
| 67 | + <reg name="pc" bitsize="32" type="code_ptr"/> |
| 68 | + <reg name="icr" bitsize="32" type="uint32"/> |
| 69 | + <reg name="syscon" bitsize="32" type="uint32"/> |
| 70 | + <reg name="cpu_id" bitsize="32" type="uint32"/> |
| 71 | + <reg name="core_id" bitsize="32" type="uint32"/> |
| 72 | + <reg name="biv" bitsize="32" type="uint32"/> |
| 73 | + <reg name="btv" bitsize="32" type="uint32"/> |
| 74 | + <reg name="isp" bitsize="32" type="uint32"/> |
| 75 | + <reg name="icr" bitsize="32" type="uint32"/> |
| 76 | + <reg name="fcx" bitsize="32" type="uint32"/> |
| 77 | + <reg name="lcx" bitsize="32" type="uint32"/> |
| 78 | + <reg name="compat" bitsize="32" type="uint32"/> |
| 79 | + <reg name="pmucon0" bitsize="32"/> |
| 80 | + <reg name="cycles" bitsize="32"/> |
| 81 | + <reg name="instr" bitsize="32"/> |
| 82 | + <reg name="time" bitsize="32"/> |
| 83 | +</feature> |
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