Skip to content

Latest commit

 

History

History
113 lines (69 loc) · 2.83 KB

readme_en.md

File metadata and controls

113 lines (69 loc) · 2.83 KB

SHA series hash algorithm hardware Coprocessor based on RISC-V

Key Words：SHA、Rocket Chip、Chipyard、RoCC


The repositories related to this project：

This project

Chipyard enviroment to run this project ( fork from chipyard v1.11.0 )

spike of sha extension for this project ( fork from riscv-isa-sim v1.1.0 )

fpga-shell which support VCU108 board ( fork from rocket-chip-fpga-shells )



File hierarchy:

.
├── sha3sim
├── sha3acc
|   ├── software
|   └── src
├── sha2sim
├── sha2acc
|   ├── software
|   └── src
└── doc

Simulation

how to use:

project shoud be used in the chipyard-shaacc enviroment.

git clone https://github.com/BriMonzZY/chipyard-shaacc.git

cd chipyard-shaacc


# This step may take a long time and require more than 3GB of storage space. It is recommended to go online scientifically (if you are in China) and to a location with a better network environment, otherwise initialization may fail.
./init_env.sh # initial chipyard env.

project codes are in thechipyard-shaacc/generators/sha-acc folder.

you can runbuild.sh 、chiseltest.sh or run.sh scripts to compile or run this project.

## Enter the directory
cd chipyard-shaacc/generators/sha-acc

## help
./build.sh -h 
./run.sh -h
./fpgabuild.sh -h
./chiseltest.sh -h


./build.sh sha3acc
./build.sh sha3accprint

./build.sh sha2acc
./build.sh sha2accprint

./build.sh test # compile the test programes

./build.sh clean # execute make clean in sims/verilator、sims/vcs and sims/xcelium to clean the files which generated by compile


./run.sh # run the file after compile


## run units test
./chiseltest.sh
./chiseltest.sh sha3
./chiseltest.sh sha2


FPGA Prototype

generate FPGA bitstream file

Default generation for Xilinx VCU108 Bitstream file of the board

First, check if there are any environment variables for the Vivado tool in the script file. Please confirm that the Vivado tool is installed.

./fpgabuild.sh -h # help

After the successful generation of the bitstream, you can find the bitstream file and Vivado checkpoint file in fpga/generated src/<long name>/obj, where you can view information such as resource utilization and timing reports, or use UltraFast to Insert ILA probes into the process for debugging.



Physical demonstration video of SHA series hash algorithm hardware Coprocessor based on RISC-V: https://pan.baidu.com/s/1lb5idFS651VYNDrE4HT7Zg?pwd=rq52 (use baidunetdisk)