SPI flash: dummy bytes calculation for DUAL_IO mode

[loeriver]

Testing the spi_flash modes on my TangNano 9k I noticed that the 1st byte I tried to read was somehow "eaten" in the SPI_FLASH_FAST_READ_DUAL_IO mode, the slower modes worked all perfectly, using 8 "dummy bits" for the ..FAST_READ and ..FAST_READ_DUAL_OUTPUT mode.

After consulting the docs of the flash IC (Puya P25Q32U) I found out that in the ..DUAL_IO (8'hBB) mode the dummy bits are also sent on both channels: so one adds only "dummy cycles / 2" to the cycle count.

I think this is similar for other flash chips, at least the Winbond W25Q128JV behaves also this way.

For me this also meant to change the hardcoded cycle count in the optimized version from 7'd43 to 7'd39.

Can somebody confirm this behavior or did I just overlook something?