Help with Some Scripts and Makefiles

[DoctorWkt]

Hi, firstly thanks so much for creating this set of resources. I've been working my way through part 1 of the Blinky to RISC-V tutorial and I'm having so much fun!

I'm on a Debian system with a ULX3S FPGA board, with Icarus Verilog 13.0,
Verilator 5.043, yosys, nextpnr etc. installed.

When I get to step11.v, the Icarus simulation doesn't work:

$ ./run.sh step11.v 
step11.v:255: error: Unable to bind wire/reg/memory `mem_addr' in `bench.uut'
 ...

and that continues to be the case for the remaining steps.

For step18.v, Verilator gets introduced, and the commands to invoke it are:

$ verilator -DBENCH -DBOARD_FREQ=12 -Wno-fatal --top-module SOC -cc -exe sim_main.cpp step18.v     or
$ run_verilator.sh step18.v

For the first one, I get:

$ verilator -DBENCH -DBOARD_FREQ=12 -Wno-fatal --top-module SOC -cc -exe sim_main.cpp step18.v
%Error: step18.v:549:20: Define or directive not defined: '`CPU_FREQ'
  549 |       .clk_freq_hz(`CPU_FREQ*1000000)
      |                    ^~~~~~~~~
        ... See the manual at https://verilator.org/verilator_doc.html?v=5.043 for more assistance.
%Error: step18.v:549:29: syntax error, unexpected '*', expecting IDENTIFIER-for-type
  549 |       .clk_freq_hz(`CPU_FREQ*1000000)
      |                             ^
%Error: Exiting due to 2 error(s)

and for the second:

$ ./run_verilator.sh step18.v
%Warning-WIDTHTRUNC: riscv_assembly.v:78:10: Bit extraction of array[1535:0] requires 11 bit index, not 30 bits.
  ...
../sim_main.cpp:1:10: fatal error: VfemtoRV32_bench.h: No such file or directory
    1 | #include "VfemtoRV32_bench.h"
      |          ^~~~~~~~~~~~~~~~~~~~
compilation terminated.

Now, back up in learn-fpga/FemtoRV/, the Makefile says: make one of ICESTICK, ICEFEATHER, ULX3S ...

But, when I try, I get:

$ make ULX3S
BOARD=ulx3s TOOLS/make_config.sh -DULX3S
./PROCESSOR/femtorv32_petitbateau.v:78: error: Unable to bind wire/reg/memory `instr['sd14:'sd12]' in `FemtoRV32'
  ... (many more errors)
Elaboration failed
tmp.vvp: Unable to open input file.
BOARD=ulx3s
(cd FIRMWARE; make libs)	
 ...
(cd LIBFEMTOGL;   make clean all) # Compile graphic library
make[2]: Entering directory '/usr/local/src/Github/learn-fpga/FemtoRV/FIRMWARE/LIBFEMTOGL'
Configuring for Linux x86_64
../makefile.inc:104: warning: ignoring prerequisites on suffix rule definition
../makefile.inc:108: warning: ignoring prerequisites on suffix rule definition
../makefile.inc:112: warning: ignoring prerequisites on suffix rule definition
 ...
Assembler messages:
Fatal error: -march=: ISA string must begin with rv32 or rv64
make[2]: *** [../makefile.inc:112: font_8x16.o] Error 1
 ...

Could someone suggest what I can do to fix these issues!

Thanks, Warren