Power-aware timing: IR drop impact on gate delays #13
Description
Summary
Model the effect of IR drop (voltage droop) on gate delays. When many gates switch simultaneously, local supply voltage drops, causing gates to slow down.
Current State
GEM uses fixed gate delays regardless of switching activity. Real designs experience dynamic IR drop that can increase delays by 5-15%.
Proposed Approach
- Track switching activity per region/partition during simulation
- Apply voltage-dependent delay scaling based on switching density
- Would need voltage-delay sensitivity data from Liberty (available in advanced Liberty formats)
- Simpler approach: apply a global IR drop margin as a delay derating factor
Impact
Low-Medium — more important for high-performance designs with tight timing margins.
Effort
Very High for accurate modeling, Low for a simple global margin approach.