wip: board configuration

Author: robtaylor

chipflow_lib/__init__.py

@@ -7,8 +7,12 @@
 import sys
 import tomli
 from pathlib import Path
+from dataclasses import dataclass
+
 from pydantic import ValidationError
 
+from amaranth.lib.wiring import Signature
+
 __version__ = importlib.metadata.version("chipflow_lib")
 
 class ChipFlowError(Exception):
@@ -64,3 +68,63 @@ def _parse_config_file(config_file):
 
         error_str = "\n".join(error_messages)
         raise ChipFlowError(f"Validation error in chipflow.toml:\n{error_str}")
+
+
+def _wire_ulx3s_spi_flash(m: Module, platform: _ULX3SPlatform, port_name: str, flash: Interface) -> None:
+        flash_port = platform.request("spi_flash", dir=dict(cs='-', copi='-', cipo='-', wp='-', hold='-'))
+        # Flash clock requires a special primitive to access in ECP5
+        m.submodules.usrmclk = Instance(
+            "USRMCLK",
+            i_USRMCLKI=flash.clk.o,
+            i_USRMCLKTS=ResetSignal(),  # tristate in reset for programmer accesss
+            a_keep=1,
+        )
+
+        # Flash IO buffers
+        m.submodules += Instance(
+            "OBZ",
+            o_O=flash_port.cs.io,
+            i_I=flash.csn.o,
+            i_T=ResetSignal(),
+        )
+
+        # Connect flash data pins in order
+        data_pins = ["copi", "cipo", "wp", "hold"]
+        for i in range(4):
+            m.submodules += Instance(
+                "BB",
+                io_B=getattr(flash_port, data_pins[i]).io,
+                i_I=flash.d.o[i],
+                i_T=~flash.d.oe[i],
+                o_O=flash.d.i[i]
+            )
+
+PortName = str
+WiringFunc = Callable[[Module, Platform, PortName, Interface], None]
+"""
+A :py:WiringFunc declares a function that is used to wire an :py:`wiring.Interface` to a given named :py:`io.PortLike` on the given :py:`build.Platform`
+"""
+
+@dataclass
+class BoardPrimitive:
+    interface_type: type[amaranth.Signature]
+    wiring_func: WiringFunc
+
+@dataclass
+class BoardVariant:
+"Specification of an FPGA board"
+    board_platform: type[Platform]
+    "The :py:`type` of the :py:`build.Platform` to use for this board."
+    reset_button: Optional[str] = None
+    "Resource name to wire to reset"
+    default_clock: Optional[str] = None
+    "Default clock to use for this BoardVariant or BoardType"
+    primitives: Optional[Dict[str, BoardPrimitive]] = None
+    "A mapping of a Platform Resource name to the primitive that should be used to wire it up"
+
+@dataclass
+class BoardType:
+    types: List[
+
+SUPPORTED_BOARDS = {
+    'ULX3S' 

chipflow_lib/config_models.py

@@ -58,6 +58,13 @@ def validate_pad_dicts(cls, v, info: ValidationInfo):
         return v
 
 
+class BoardType(BaseModel):
+    """Configuration for silicon in chipflow.toml."""
+    board_name: Literal["ULX3S"]
+    board_type: Literal["85F"]
+
+
+
 class StepsConfig(BaseModel):
     """Configuration for steps in chipflow.toml."""
     silicon: str
@@ -69,6 +76,7 @@ class ChipFlowConfig(BaseModel):
     top: Dict[str, Any] = {}
     steps: StepsConfig
     silicon: SiliconConfig
+    board: BoardConfig
     clocks: Optional[Dict[str, str]] = None
     resets: Optional[Dict[str, str]] = None