uart-demo: add reference implementation.

Author: jfng

uart-demo/tests/test_uart.py

@@ -8,4 +8,52 @@
 from uart_demo.ports import PortGroup
 
 
-# TODO
+class LoopbackUARTTestCase(unittest.TestCase):
+    def test_hello(self):
+        ports = PortGroup()
+        ports.rx = io.SimulationPort("i", 1)
+        ports.tx = io.SimulationPort("o", 1)
+
+        dut = LoopbackUART(ports, clk_freq=48e6, baudrate=115200)
+
+        # send "hello" to the UART receiver
+        async def rx_testbench(ctx):
+            ctx.set(ports.rx.i, 1)
+            await ctx.delay(1 / dut.baudrate)
+
+            for rx_chr in "hello":
+                # send the start bit
+                ctx.set(ports.rx.i, 0)
+                await ctx.delay(1 / dut.baudrate)
+
+                # send data bits
+                for rx_bit in reversed(f"{ord(rx_chr):08b}"):
+                    ctx.set(ports.rx.i, int(rx_bit))
+                    await ctx.delay(1 / dut.baudrate)
+
+                # send the stop bit
+                ctx.set(ports.rx.i, 1)
+                await ctx.delay(1 / dut.baudrate)
+
+        # check that "hello" is transmitted back
+        async def tx_testbench(ctx):
+            for tx_chr in "hello":
+                # wait for the start bit
+                await ctx.negedge(ports.tx.o)
+                await ctx.delay(1 / dut.baudrate)
+
+                # check data bits
+                for tx_bit in reversed(f"{ord(tx_chr):08b}"):
+                    self.assertEqual(ctx.get(ports.tx.o), int(tx_bit))
+                    await ctx.delay(1 / dut.baudrate)
+
+                # check the stop bit
+                self.assertEqual(ctx.get(ports.tx.o), 1)
+
+        sim = Simulator(dut)
+        sim.add_clock(period=1 / 48e6)
+        sim.add_testbench(rx_testbench)
+        sim.add_testbench(tx_testbench)
+
+        with sim.write_vcd(vcd_file="test.vcd"):
+            sim.run()

uart-demo/uart_demo/uart.py

@@ -7,4 +7,28 @@
 __all__ = ["LoopbackUART"]
 
 
-# TODO
+class LoopbackUART(wiring.Component):
+    def __init__(self, ports, clk_freq, baudrate=115200):
+        super().__init__({})
+        self.ports = ports
+        self.clk_freq = clk_freq
+        self.baudrate = baudrate
+
+    def elaborate(self, platform):
+        m = Module()
+
+        m.submodules.rx_buffer = rx_buffer = io.Buffer("i", self.ports.rx)
+        m.submodules.tx_buffer = tx_buffer = io.Buffer("o", self.ports.tx)
+
+        m.submodules.uart = uart = AsyncSerial(divisor=int(self.clk_freq // self.baudrate))
+
+        m.d.comb += [
+            uart.rx.i.eq(rx_buffer.i),
+            tx_buffer.o.eq(uart.tx.o),
+
+            uart.rx.ack .eq(uart.tx.rdy),
+            uart.tx.data.eq(uart.rx.data),
+            uart.tx.ack .eq(uart.rx.rdy),
+        ]
+
+        return m