Sketch how soc might work

Author: robtaylor

riscv-demo/riscv_demo/ips/qspi/glasgow_qspi.py

@@ -149,8 +149,8 @@ def elaborate(self, platform):
 
 
 class QSPIController(wiring.Component):
-    def __init__(self, ports, *, chip_count=1, use_ddr_buffers=False):
-        self.ioshape = IOShape({
+    def pins(chip_count=1):
+        return IOShape({
             "sck": ("o",  1),
             "io0": ("io", 1),
             "io1": ("io", 1),
@@ -159,10 +159,10 @@ def __init__(self, ports, *, chip_count=1, use_ddr_buffers=False):
             "cs":  ("o",  chip_count),
         })
 
-        self._ports = self.ioshape.check_ports(ports)
-
+    def __init__(self, *, chip_count=1, use_ddr_buffers=False):
         self._ddr = use_ddr_buffers
         self._chip_count = chip_count
+        self._ioshape = self.pins(chip_count)
 
         super().__init__(PortSignature({
             "o_octets": In(stream.Signature(data.StructLayout({
@@ -182,15 +182,16 @@ def elaborate(self, platform):
 
         m = Module()
 
+        self.ports = platform.get_ports()
         m.submodules.enframer = enframer = QSPIEnframer(chip_count = self._chip_count)
         connect(m, controller=flipped(self.o_octets), enframer=enframer.octets)
 
-        m.submodules.io_clocker = io_clocker = IOClocker(self.ioshape,
+        m.submodules.io_clocker = io_clocker = IOClocker(self._ioshape,
             clock="sck", o_ratio=ratio, meta_layout=QSPIMode)
         connect(m, enframer=enframer.frames, io_clocker=io_clocker.i_stream)
         m.d.comb += io_clocker.divisor.eq(self.divisor)
 
-        m.submodules.io_streamer = io_streamer = IOStreamer(self.ioshape, self._ports, init={
+        m.submodules.io_streamer = io_streamer = IOStreamer(self._ioshape, self._ports, init={
             "sck": {"o": 1, "oe": 1}, # Motorola "Mode 3" with clock idling high
             "cs":  {"o": 0, "oe": 1}, # deselected
         }, ratio=ratio, meta_layout=QSPIMode)

riscv-demo/riscv_demo/soc.py

@@ -7,6 +7,7 @@
 from amaranth_soc.wishbone.sram import WishboneSRAM
 
 from minerva.core import Minerva
+from chipflow_lib.platforms.iostream import IOShape
 
 from .ips.qspi import QSPIController, WishboneQSPIFlashController
 from .ips.uart import UARTPhy, UARTPeripheral
@@ -17,12 +18,15 @@
 
 
 class DemoSoC(wiring.Component):
-    def __init__(self, ports):
-        super().__init__({})
-
-        self.ports = ports
-
-        # Memory regions:
+    pins = IOShape({
+                'qspi': QSPIController.pins(),
+                'uart0': UARTPhy.pins(),
+                'uart1': UARTPhy.pins(),
+                })
+
+    def __init__(self):
+        super().__init__(PortSignature({}))
+       # Memory regions:
         self.mem_spiflash_base = 0x00000000
         self.mem_sram_base     = 0x10000000
 
@@ -37,6 +41,8 @@ def __init__(self, ports):
     def elaborate(self, platform):
         m = Module()
 
+        self.ports = platform.get_ports()
+
         wb_arbiter  = wishbone.Arbiter(addr_width=30, data_width=32, granularity=8)
         wb_decoder  = wishbone.Decoder(addr_width=30, data_width=32, granularity=8)
         csr_decoder = csr.Decoder(addr_width=28, data_width=8)