From 5cbf4639adc7516670b4c6edde5168e9f20d5421 Mon Sep 17 00:00:00 2001 From: 092vk Date: Tue, 10 Jun 2025 11:44:04 +0530 Subject: [PATCH 1/2] added verilog module for jk flip flop --- v1/src/simulator/src/sequential/JKflipFlop.js | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/v1/src/simulator/src/sequential/JKflipFlop.js b/v1/src/simulator/src/sequential/JKflipFlop.js index c02eae3f..f6b03990 100644 --- a/v1/src/simulator/src/sequential/JKflipFlop.js +++ b/v1/src/simulator/src/sequential/JKflipFlop.js @@ -155,6 +155,37 @@ export default class JKflipFlop extends CircuitElement { fillText(ctx, this.slaveState.toString(16), xx, yy + 5) ctx.fill() } + + static moduleVerilog() { + return ` +module JKflipFlop(q,q_inv,j,k,clk,rst,pre,en); + output reg q,q_inv; + input wire j,k,clk,rst,pre,en; + + always @(posedge clk) begin + if (rst) begin + if (pre) begin + q <= 1'b1; + end else begin + q <= 1'b0; + end + end else if (en) begin + if (j && !k) begin + q <= 1'b1; + end else if (!j && k) begin + q <= 1'b0; + end else if (!j && !k) begin + q <= q; // hold state + end else if (j && k) begin + // toggling state + q <= ~q; + end + end + end + assign q_inv = ~q; +endmodule + ` + } } JKflipFlop.prototype.tooltipText = From 7bba0af37a049ea8d243861b684ab96b50c35cd3 Mon Sep 17 00:00:00 2001 From: 092vk Date: Sat, 28 Jun 2025 17:23:27 +0530 Subject: [PATCH 2/2] moved added verilog code from v1 to src --- src/simulator/src/sequential/JKflipFlop.js | 30 ++++++++++++++++++ v1/src/simulator/src/sequential/JKflipFlop.js | 31 ------------------- 2 files changed, 30 insertions(+), 31 deletions(-) diff --git a/src/simulator/src/sequential/JKflipFlop.js b/src/simulator/src/sequential/JKflipFlop.js index 4f975c79..8875ccb4 100644 --- a/src/simulator/src/sequential/JKflipFlop.js +++ b/src/simulator/src/sequential/JKflipFlop.js @@ -146,6 +146,36 @@ export default class JKflipFlop extends CircuitElement { fillText(ctx, this.slaveState.toString(16), xx, yy + 5) ctx.fill() } + static moduleVerilog() { + return ` +module JKflipFlop(q,q_inv,j,k,clk,rst,pre,en); + output reg q,q_inv; + input wire j,k,clk,rst,pre,en; + + always @(posedge clk) begin + if (rst) begin + if (pre) begin + q <= 1'b1; + end else begin + q <= 1'b0; + end + end else if (en) begin + if (j && !k) begin + q <= 1'b1; + end else if (!j && k) begin + q <= 1'b0; + end else if (!j && !k) begin + q <= q; // hold state + end else if (j && k) begin + // toggling state + q <= ~q; + end + end + end + assign q_inv = ~q; +endmodule + ` + } } JKflipFlop.prototype.tooltipText = diff --git a/v1/src/simulator/src/sequential/JKflipFlop.js b/v1/src/simulator/src/sequential/JKflipFlop.js index f6b03990..c02eae3f 100644 --- a/v1/src/simulator/src/sequential/JKflipFlop.js +++ b/v1/src/simulator/src/sequential/JKflipFlop.js @@ -155,37 +155,6 @@ export default class JKflipFlop extends CircuitElement { fillText(ctx, this.slaveState.toString(16), xx, yy + 5) ctx.fill() } - - static moduleVerilog() { - return ` -module JKflipFlop(q,q_inv,j,k,clk,rst,pre,en); - output reg q,q_inv; - input wire j,k,clk,rst,pre,en; - - always @(posedge clk) begin - if (rst) begin - if (pre) begin - q <= 1'b1; - end else begin - q <= 1'b0; - end - end else if (en) begin - if (j && !k) begin - q <= 1'b1; - end else if (!j && k) begin - q <= 1'b0; - end else if (!j && !k) begin - q <= q; // hold state - end else if (j && k) begin - // toggling state - q <= ~q; - end - end - end - assign q_inv = ~q; -endmodule - ` - } } JKflipFlop.prototype.tooltipText =