diff --git a/src/simulator/src/testbench/testbenchInput.js b/src/simulator/src/testbench/testbenchInput.js
index f877aca8..b8e38d8a 100644
--- a/src/simulator/src/testbench/testbenchInput.js
+++ b/src/simulator/src/testbench/testbenchInput.js
@@ -316,6 +316,13 @@ export default class TB_Input extends CircuitElement {
 
         ctx.stroke()
     }
+    static moduleVerilog(){
+        return `
+module TB_Input(input clk);
+        // this circuit element is used for testbench, avoid using this in Verilog Testing and simulation
+endmodule
+        `
+    }
 }
 
 TB_Input.prototype.tooltipText = 'Test Bench Input Selected'
diff --git a/src/simulator/src/testbench/testbenchOutput.js b/src/simulator/src/testbench/testbenchOutput.js
index 49117626..65762d54 100644
--- a/src/simulator/src/testbench/testbenchOutput.js
+++ b/src/simulator/src/testbench/testbenchOutput.js
@@ -274,6 +274,13 @@ export default class TB_Output extends CircuitElement {
             }
         }
     }
+    static moduleVerilog(){
+        return `
+module TB_Output();
+        // this circuit element is used for testbench, avoid using this in Verilog Testing and simulation
+endmodule
+        `
+    }
 }
 
 TB_Output.prototype.tooltipText = 'Test Bench Output Selected'