From 354268bac7ac4dd3d7678a30632dc41f7162faa8 Mon Sep 17 00:00:00 2001 From: 092vk Date: Wed, 18 Jun 2025 17:04:20 +0530 Subject: [PATCH 1/3] added verilog module for testbench element --- v1/src/simulator/src/testbench/testbenchInput.js | 7 +++++++ v1/src/simulator/src/testbench/testbenchOutput.js | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/v1/src/simulator/src/testbench/testbenchInput.js b/v1/src/simulator/src/testbench/testbenchInput.js index bdf7452b..3d494eaa 100644 --- a/v1/src/simulator/src/testbench/testbenchInput.js +++ b/v1/src/simulator/src/testbench/testbenchInput.js @@ -317,6 +317,13 @@ export default class TB_Input extends CircuitElement { ctx.stroke() } + static moduleVerilog(){ + return ` +module TB_Input(clk); + // this circuit element is used for testbench, avoid using this in Verilog Testing and simulation +endmodule + ` + } } TB_Input.prototype.tooltipText = 'Test Bench Input Selected' diff --git a/v1/src/simulator/src/testbench/testbenchOutput.js b/v1/src/simulator/src/testbench/testbenchOutput.js index 865ec258..8b865ab6 100644 --- a/v1/src/simulator/src/testbench/testbenchOutput.js +++ b/v1/src/simulator/src/testbench/testbenchOutput.js @@ -308,6 +308,13 @@ export default class TB_Output extends CircuitElement { } } } + static moduleVerilog(){ + return ` +module TB_Output(clk); + // this circuit element is used for testbench, avoid using this in Verilog Testing and simulation +endmodule + ` + } } TB_Output.prototype.tooltipText = 'Test Bench Output Selected' From 056b8f51932062d3240286153adf0e914f67be3d Mon Sep 17 00:00:00 2001 From: 092vk Date: Wed, 18 Jun 2025 17:17:32 +0530 Subject: [PATCH 2/3] added fix --- v1/src/simulator/src/testbench/testbenchInput.js | 2 +- v1/src/simulator/src/testbench/testbenchOutput.js | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/v1/src/simulator/src/testbench/testbenchInput.js b/v1/src/simulator/src/testbench/testbenchInput.js index 3d494eaa..5069de16 100644 --- a/v1/src/simulator/src/testbench/testbenchInput.js +++ b/v1/src/simulator/src/testbench/testbenchInput.js @@ -319,7 +319,7 @@ export default class TB_Input extends CircuitElement { } static moduleVerilog(){ return ` -module TB_Input(clk); +module TB_Input(input clk); // this circuit element is used for testbench, avoid using this in Verilog Testing and simulation endmodule ` diff --git a/v1/src/simulator/src/testbench/testbenchOutput.js b/v1/src/simulator/src/testbench/testbenchOutput.js index 8b865ab6..59bbc401 100644 --- a/v1/src/simulator/src/testbench/testbenchOutput.js +++ b/v1/src/simulator/src/testbench/testbenchOutput.js @@ -310,7 +310,7 @@ export default class TB_Output extends CircuitElement { } static moduleVerilog(){ return ` -module TB_Output(clk); +module TB_Output(); // this circuit element is used for testbench, avoid using this in Verilog Testing and simulation endmodule ` From e6e0aa9e1e0f3178b108acf6cdea61aa6e3b542a Mon Sep 17 00:00:00 2001 From: 092vk Date: Sat, 28 Jun 2025 19:37:17 +0530 Subject: [PATCH 3/3] moved verilog module from v1 to src --- src/simulator/src/testbench/testbenchInput.js | 7 +++++++ src/simulator/src/testbench/testbenchOutput.js | 7 +++++++ v1/src/simulator/src/testbench/testbenchInput.js | 7 ------- v1/src/simulator/src/testbench/testbenchOutput.js | 7 ------- 4 files changed, 14 insertions(+), 14 deletions(-) diff --git a/src/simulator/src/testbench/testbenchInput.js b/src/simulator/src/testbench/testbenchInput.js index f877aca8..b8e38d8a 100644 --- a/src/simulator/src/testbench/testbenchInput.js +++ b/src/simulator/src/testbench/testbenchInput.js @@ -316,6 +316,13 @@ export default class TB_Input extends CircuitElement { ctx.stroke() } + static moduleVerilog(){ + return ` +module TB_Input(input clk); + // this circuit element is used for testbench, avoid using this in Verilog Testing and simulation +endmodule + ` + } } TB_Input.prototype.tooltipText = 'Test Bench Input Selected' diff --git a/src/simulator/src/testbench/testbenchOutput.js b/src/simulator/src/testbench/testbenchOutput.js index 49117626..65762d54 100644 --- a/src/simulator/src/testbench/testbenchOutput.js +++ b/src/simulator/src/testbench/testbenchOutput.js @@ -274,6 +274,13 @@ export default class TB_Output extends CircuitElement { } } } + static moduleVerilog(){ + return ` +module TB_Output(); + // this circuit element is used for testbench, avoid using this in Verilog Testing and simulation +endmodule + ` + } } TB_Output.prototype.tooltipText = 'Test Bench Output Selected' diff --git a/v1/src/simulator/src/testbench/testbenchInput.js b/v1/src/simulator/src/testbench/testbenchInput.js index 5069de16..bdf7452b 100644 --- a/v1/src/simulator/src/testbench/testbenchInput.js +++ b/v1/src/simulator/src/testbench/testbenchInput.js @@ -317,13 +317,6 @@ export default class TB_Input extends CircuitElement { ctx.stroke() } - static moduleVerilog(){ - return ` -module TB_Input(input clk); - // this circuit element is used for testbench, avoid using this in Verilog Testing and simulation -endmodule - ` - } } TB_Input.prototype.tooltipText = 'Test Bench Input Selected' diff --git a/v1/src/simulator/src/testbench/testbenchOutput.js b/v1/src/simulator/src/testbench/testbenchOutput.js index 59bbc401..865ec258 100644 --- a/v1/src/simulator/src/testbench/testbenchOutput.js +++ b/v1/src/simulator/src/testbench/testbenchOutput.js @@ -308,13 +308,6 @@ export default class TB_Output extends CircuitElement { } } } - static moduleVerilog(){ - return ` -module TB_Output(); - // this circuit element is used for testbench, avoid using this in Verilog Testing and simulation -endmodule - ` - } } TB_Output.prototype.tooltipText = 'Test Bench Output Selected'