arrange: the structure of the project

Author: cebarobot

README.md

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+# 103 计算机 现代硬件电路源码
+
+```
+.
+├── README.md           # 说明文档
+├── core                # 内核部分电路
+│   ├── core_top.v          # 内核部分顶层模块
+│   ├── arith_unit.v        # 运算器 АУ
+│   ├── arith_ctrl.v        # 局部程序发送器 МПД
+│   ├── operator.v          # 操作器 БО
+│   ├── start_reg.v         # 启动寄存器 ПР
+│   ├── select_reg.v        # 选择寄存器 СР
+│   ├── pulse_unit.v        # 脉冲分配器 РИ
+│   ├── memory.v            # 存贮器 ЗУ & МП
+│   └── io_unit.v           # 输入输出电子部件 ЭУВВ
+├── shell               # 外壳部分电路
+│   ├── shell_top.v         # 外壳部分顶层模块
+│   ├── driver_74lv165.v    # 74LV165 串行输入驱动模块
+│   ├── driver_74lv595.v    # 74LV595 串行输出驱动模块
+│   ├── button_pulse.v      # 按钮-脉冲信号
+│   └── switch_level.v      # 开关-电平信号
+├── include             # 涉及的外部模块
+└── docs                # 文档
+```

arith_ctrl.v renamed to core/arith_ctrl.v

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+module button_pulse (
+    input  clk,
+    input  resetn,
+
+    input  btn,         // button
+    output pulse        // pulse
+);
+
+reg  btn_r;
+reg  pulse_r;
+
+always @(posedge clk) begin
+    if (~resetn) begin
+        btn_r <= 1'b0;
+        pulse_r <= 1'b0;
+    end else begin
+        btn_r <= btn;
+        pulse_r <= !btn && btn_r;
+    end
+end
+
+assign pulse = pulse_r;
+
+endmodule

arith_unit.v renamed to core/arith_unit.v

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+module driver_74lv165 (
+    input  clk,
+    input  resetn,
+    
+    output [15:0] data_0,
+    output [15:0] data_1,
+    output [15:0] data_2,
+    output [15:0] data_3,
+    output [15:0] data_4,
+
+    output SH_LDn,          // high for shift, low for load
+    output RCLK,            // clock
+
+    input  QH_0,            // serial input
+    input  QH_1,            // serial input
+    input  QH_2,            // serial input
+    input  QH_3,            // serial input
+    input  QH_4             // serial input
+);
+
+reg serial_clk;
+reg shift_clk;
+reg shiftn_load;
+
+reg [ 4:0] cnt;
+
+reg [15:0] data_0_r;
+reg [15:0] data_1_r;
+reg [15:0] data_2_r;
+reg [15:0] data_3_r;
+reg [15:0] data_4_r;
+
+reg [15:0] data_0_s;
+reg [15:0] data_1_s;
+reg [15:0] data_2_s;
+reg [15:0] data_3_s;
+reg [15:0] data_4_s;
+
+always @(posedge clk) begin
+    if (~resetn) begin
+        serial_clk <= 1'b0;
+    end else begin
+        serial_clk <= ~serial_clk;
+    end
+end
+
+always @(posedge clk) begin
+    if (~resetn) begin
+        cnt <= 5'd0;
+    end else if (!serial_clk) begin
+        if (cnt == 5'd16) begin
+            cnt <= 5'd0;
+        end else begin
+            cnt <= cnt + 5'd1;
+        end
+    end
+end
+
+always @(posedge clk) begin
+    if (~resetn) begin
+        shift_clk <= 1'b0;
+    end else if (serial_clk) begin
+        shift_clk <= 1'b0;
+    end else begin
+        if (cnt == 5'd16) begin
+            shift_clk <= 1'b0;
+        end else begin
+            shift_clk <= 1'b1;
+        end
+    end
+end
+
+always @(posedge clk) begin
+    if (~resetn) begin
+        shiftn_load <= 1'b0;
+    end else if (serial_clk) begin
+        shiftn_load <= 1'b0;
+    end else begin
+        if (cnt == 5'd16) begin
+            shiftn_load <= 1'b1;
+        end else begin
+            shiftn_load <= 1'b0;
+        end
+    end
+end
+
+always @(posedge clk) begin
+    if (~resetn) begin
+        data_0_r <= 16'd0;
+        data_1_r <= 16'd0;
+        data_2_r <= 16'd0;
+        data_3_r <= 16'd0;
+        data_4_r <= 16'd0;
+    end else if (!serial_clk && cnt == 5'd16) begin
+        data_0_r <= data_0_s;
+        data_1_r <= data_1_s;
+        data_2_r <= data_2_s;
+        data_3_r <= data_3_s;
+        data_4_r <= data_4_s;
+    end
+end
+
+always @(posedge clk) begin
+    if (~resetn) begin
+        data_0_s <= 16'd0;
+        data_1_s <= 16'd0;
+        data_2_s <= 16'd0;
+        data_3_s <= 16'd0;
+        data_4_s <= 16'd0;
+    end else if (!serial_clk && cnt != 5'd16) begin
+        data_0_s <= {data_0_s[14:0], QH_0};
+        data_1_s <= {data_1_s[14:0], QH_1};
+        data_2_s <= {data_2_s[14:0], QH_2};
+        data_3_s <= {data_3_s[14:0], QH_3};
+        data_4_s <= {data_4_s[14:0], QH_4};
+    end
+end
+
+assign SH_LDn = !shiftn_load;
+assign RCLK = shift_clk;
+assign data_0 = data_0_r;
+assign data_1 = data_1_r;
+assign data_2 = data_2_r;
+assign data_3 = data_3_r;
+assign data_4 = data_4_r;
+
+endmodule

core_top.v renamed to core/core_top.v

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+module driver_74lv595 (
+    input  clk,
+    input  resetn,
+
+    input  [15:0] data_0,
+    input  [15:0] data_1,
+    input  [15:0] data_2,
+    input  [15:0] data_3,
+
+    output RCLK,            // storage register clock
+    output SRCLK,           // shift register clock
+
+    output SER_0,           // serial output
+    output SER_1,           // serial output
+    output SER_2,           // serial output
+    output SER_3            // serial output
+);
+
+reg serial_clk;
+reg shift_clk;
+reg store_clk;
+
+reg [ 4:0] cnt;
+
+reg [15:0] data_0_r;
+reg [15:0] data_1_r;
+reg [15:0] data_2_r;
+reg [15:0] data_3_r;
+
+always @(posedge clk) begin
+    if (~resetn) begin
+        serial_clk <= 1'b0;
+    end else begin
+        serial_clk <= ~serial_clk;
+    end
+end
+
+always @(posedge clk) begin
+    if (~resetn) begin
+        cnt <= 5'd0;
+    end else if (!serial_clk) begin
+        if (cnt == 5'd16) begin
+            cnt <= 5'd0;
+        end else begin
+            cnt <= cnt + 5'd1;
+        end
+    end
+end
+
+always @(posedge clk) begin
+    if (~resetn) begin
+        shift_clk <= 1'b0;
+    end else if (serial_clk) begin
+        shift_clk <= 1'b0;
+    end else begin
+        if (cnt == 5'd16) begin
+            shift_clk <= 1'b0;
+        end else begin
+            shift_clk <= 1'b1;
+        end
+    end
+end
+
+always @(posedge clk) begin
+    if (~resetn) begin
+        store_clk <= 1'b0;
+    end else if (serial_clk) begin
+        store_clk <= 1'b0;
+    end else begin
+        if (cnt == 5'd16) begin
+            store_clk <= 1'b1;
+        end else begin
+            store_clk <= 1'b0;
+        end
+    end
+end
+
+always @(posedge clk) begin
+    if (~resetn) begin
+        data_0_r <= 16'd0;
+        data_1_r <= 16'd0;
+        data_2_r <= 16'd0;
+        data_3_r <= 16'd0;
+    end else if (serial_clk) begin
+        if (cnt == 5'd0) begin
+            data_0_r <= data_0;
+            data_1_r <= data_1;
+            data_2_r <= data_2;
+            data_3_r <= data_3;
+        end else begin
+            data_0_r <= {data_0_r[14:0], 1'b0};
+            data_1_r <= {data_1_r[14:0], 1'b0};
+            data_2_r <= {data_2_r[14:0], 1'b0};
+            data_3_r <= {data_3_r[14:0], 1'b0};
+        end
+    end
+end
+
+assign RCLK = store_clk;
+assign SRCLK = shift_clk;
+assign SER_0 = data_0_r[15];
+assign SER_1 = data_1_r[15];
+assign SER_2 = data_2_r[15];
+assign SER_3 = data_3_r[15];
+
+endmodule