diff --git a/hub/instruction_handling/halt/return/generalities.tex b/hub/instruction_handling/halt/return/generalities.tex index f036c86..97ea513 100644 --- a/hub/instruction_handling/halt/return/generalities.tex +++ b/hub/instruction_handling/halt/return/generalities.tex @@ -315,11 +315,11 @@ \item \If $\locCheckFirstByte = 1$ \[ \setMmuInstructionParametersInvalidCodePrefix { - anchorRow = i , - relOffset = \locFirstMiscRowOffset , - sourceId = \cn _{i} , - sourceOffsetLo = \locOffsetLo , - successBit = 1 - \stackIcpx _{i - \locStackRowOffset} , + anchorRow = i , + relOffset = \locFirstMiscRowOffset , + sourceId = \cn _{i} , + sourceOffsetLo = \locOffsetLo , + successBit = \stackIcpx _{i - \locStackRowOffset} , } \] \item \If $\locWriteSomeReturnData = 1$ diff --git a/mmu/instructions/invalidCodePrefix/preprocessing.tex b/mmu/instructions/invalidCodePrefix/preprocessing.tex index 5415886..e1adc2e 100644 --- a/mmu/instructions/invalidCodePrefix/preprocessing.tex +++ b/mmu/instructions/invalidCodePrefix/preprocessing.tex @@ -35,7 +35,7 @@ \] and we further impose that \[ - \macroSuccessBit_{i} = 1 - \ppWcpRes_{i + 1} + \macroSuccessBit_{i} = \ppWcpRes_{i + 1} \] we define the following shorthands: \[ @@ -65,5 +65,8 @@ \end{array} \right. \] \end{description} -\saNote{} The value present in $\microLimb_{i + \nppMmuInstInvalidCodePrefixValuePO}$ will be justified in the \mmioMod{} module by the \mmioInstRamToLimbOneSource{} instruction. +\saNote{} +The value present in $\microLimb_{i + \nppMmuInstInvalidCodePrefixValuePO}$ +will be justified in the \mmioMod{} module +via the \mmioInstRamToLimbOneSource{} instruction. It is the byte contained at offset $\macroSrcOffsetLo_{i}$ in the \textsc{ram} of the execution context with context number $\macroSrcId_{i}$.