valid verilog module syntax is not recognized

[cospan]

When building an FPGA image the tool analyzes verilog modules to determine if build depends on them,

A module can be declared with the beginning parenthesis on the first line:

module verilog_module (

or with the parenthesis on the second line

module verilog_module
(

The system is not recognizing the second version

[cospan]

generate statements confuse the verilog parser