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kiram9kiram9
committed
initial commit for SSD/GPU support
Signed-off-by: Kieran Levin <[email protected]>
0 parents  commit 61d7686

8 files changed

+770
-0
lines changed

‎Makefile

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gpu_cfg_generator.o : gpu_cfg_generator.c gpu_cfg_generator.h
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../cosmopolitan/bin/cosmocc -o gpu_cfg_gen gpu_cfg_generator.c
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clean :
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rm gpu_cfg_gen gpu_cfg_gen.aarch64.elf gpu_cfg_gen.com.dbg

‎config_definition.h

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/*
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* The Framework bay descriptor consists of a header and a series of blocks
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* after the header that describe the function of the card.
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*
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* Each block starts with a block header which is 4 bytes, and then block
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* data.
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*
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* -------------
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* HEADER
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* -------------
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* BLOCK1 Header
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* -------------
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* BLOCK1 Data
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* -------------
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* BLOCK2 Header
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* -------------
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* Block2 Data
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* -------------
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*/
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#include <stddef.h>
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#define GPU_MAX_BLOCK_LEN (256)
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#define GPU_SERIAL_LEN 20
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#define BUILD_ASSERT(dummy)
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#define __packed __attribute__((packed))
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struct gpu_cfg_descriptor {
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/* Expansion bay card magic value that is unique */
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char magic[4];
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/* Length of header following this field */
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uint32_t length;
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/* descriptor version, if EC max version is lower than this, ec cannot parse */
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uint16_t descriptor_version_major;
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uint16_t descriptor_version_minor;
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/* Hardware major version */
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uint16_t hardware_version;
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/* Hardware minor revision */
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uint16_t hardware_revision;
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/* 18 digit Framework Serial that starts with FRA
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* the first 10 digits must be allocated by framework
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*/
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char serial[20];
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/* Length of descriptor following header*/
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uint32_t descriptor_length;
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/* CRC of descriptor */
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uint32_t descriptor_crc32;
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/* CRC of header before this value */
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uint32_t crc32;
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} __packed;
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struct gpu_config_header {
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union {
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struct gpu_cfg_descriptor header;
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uint8_t bytes[0x2B];
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};
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} __packed;
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struct gpu_block_header {
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uint8_t block_type;
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uint8_t block_length;
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} __packed;
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BUILD_ASSERT(sizeof(struct gpu_block_header) == 2);
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enum gpucfg_type {
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GPUCFG_TYPE_UNINITIALIZED = 0,
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GPUCFG_TYPE_GPIO = 1,
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GPUCFG_TYPE_THERMAL_SENSOR = 2,
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GPUCFG_TYPE_FAN = 3,
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GPUCFG_TYPE_POWER = 4,
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GPUCFG_TYPE_BATTERY = 5,
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GPUCFG_TYPE_PCIE = 6,
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GPUCFG_TYPE_DPMUX = 7,
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GPUCFG_TYPE_POWEREN = 8,
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GPUCFG_TYPE_SUBSYS = 9,
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GPUCFG_TYPE_VENDOR = 10,
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GPUCFG_TYPE_PD = 11,
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GPUCFG_TYPE_GPUPWR = 12,
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GPUCFG_TYPE_CUSTOM_TEMP = 13,
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GPUCFG_TYPE_MAX = 255, /**< Force enum to be 8 bits */
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} __packed;
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BUILD_ASSERT(sizeof(enum gpucfg_type) == sizeof(uint8_t));
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enum gpu_gpio_idx {
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GPU_GPIO_INVALID = 0,
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GPU_1G1_GPIO0_EC,
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GPU_1H1_GPIO1_EC,
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GPU_2A2_GPIO2_EC,
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GPU_2L7_GPIO3_EC,
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GPU_2L5_TH_OVERTn, /* cannot be controlled directly */
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GPU_1F2_I2C_S5_INT,
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GPU_1L1_DGPU_PWROK, /* connected to APU */
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GPU_1C3_ALW_CLK, /* ALW I2C CLOCK PIN to EC */
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GPU_1D3_ALW_DAT, /* ALW I2C DATA PIN to EC */
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GPU_1F3_MUX1, /* cannot be controlled directly */
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GPU_1G3_MUX2, /* cannot be controlled directly */
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GPU_2B5_ALERTn,
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GPU_EDP_MUX_SEL, /* Select EDP MUX */
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GPU_ECPWM_EN, /**/
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GPU_PCIE_MUX_SEL, /* select between EDP AUX or SSD PCIE2 CLK*/
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GPU_VSYS_EN,
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GPU_VADP_EN,
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GPU_FAN_EN,
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GPU_3V_5V_EN,
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GPU_GPIO_MAX
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} __packed;
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enum gpu_gpio_purpose {
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GPIO_FUNC_UNUSED,
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GPIO_FUNC_HIGH, /* set high */
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GPIO_FUNC_TEMPFAULT,
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GPIO_FUNC_ACDC,
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GPIO_FUNC_HPD,
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GPIO_FUNC_PD_INT,
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GPIO_FUNC_SSD1_POWER,
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GPIO_FUNC_SSD2_POWER,
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GPIO_FUNC_EC_PWM_EN,
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GPIO_FUNC_EDP_MUX_SEL,
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GPIO_FUNC_VSYS_EN,
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GPIO_FUNC_VADP_EN,
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GPIO_FUNC_GPU_PWR,
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GPIO_FUNC_MAX,
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};
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enum power_request_source_t {
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POWER_REQ_INIT,
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POWER_REQ_POWER_ON,
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POWER_REQ_GPU_3V_5V,
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POWER_REQ_COUNT,
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};
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struct gpu_cfg_gpio {
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uint8_t gpio;
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uint8_t function;
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uint32_t flags;
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/* Follow enum power_state, if the system power state is lower than this power state,
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* it will be turned off (low)
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*/
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uint8_t power_domain;
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} __packed;
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enum gpu_thermal_sensor {
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GPU_THERM_INVALID,
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GPU_THERM_F75303,
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} __packed;
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struct gpu_cfg_thermal {
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uint8_t thermal_type;
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uint8_t address;
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uint32_t reserved;
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uint32_t reserved2;
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} __packed;
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struct gpu_cfg_custom_temp {
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uint8_t idx;
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uint16_t temp_fan_off;
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uint16_t temp_fan_max;
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} __packed;
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struct gpu_cfg_fan {
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uint8_t idx;
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uint8_t flags;
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uint16_t min_rpm;
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uint16_t min_temp;
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uint16_t start_rpm;
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uint16_t max_rpm;
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uint16_t max_temp;
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} __packed;
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struct gpu_cfg_power {
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uint8_t device_idx;
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uint8_t battery_power;
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uint8_t average_power;
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uint8_t long_term_power;
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uint8_t short_term_power;
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uint8_t peak_power;
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} __packed;
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struct gpu_cfg_battery {
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uint16_t max_current;
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uint16_t max_mv;
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uint16_t min_mv;
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uint16_t max_charge_current;
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} __packed;
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enum gpu_subsys_type {
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GPU_ASSEMBLY = 0, /* Populated in header, not valid for extended structure */
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GPU_PCB = 1,
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GPU_LEFT_FAN = 2,
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GPU_RIGHT_FAN = 3,
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GPU_HOUSING = 4,
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GPU_SUBSYS_MAX = 10,
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};
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struct gpu_subsys_serial {
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uint8_t gpu_subsys;
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char serial[GPU_SERIAL_LEN];
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} __packed;
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enum gpu_pcie_cfg {
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PCIE_8X1 = 0,
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PCIE_4X1 = 1,
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PCIE_4X2 = 2,
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} __packed;
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BUILD_ASSERT(sizeof(enum gpu_pcie_cfg) == sizeof(uint8_t));
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enum gpu_vendor {
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GPU_VENDOR_INITIALIZING = 0,
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GPU_FAN_ONLY = 1,
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GPU_AMD_R23M = 2,
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GPU_SSD = 3,
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GPU_PCIE_ACCESSORY = 4
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} __packed;
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BUILD_ASSERT(sizeof(enum gpu_vendor) == sizeof(uint8_t));
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enum gpu_pd {
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PD_TYPE_INVALID = 0,
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PD_TYPE_ETRON_EJ889I = 1,
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PD_TYPE_MAX = 0xFF
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} __packed;
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struct gpu_subsys_pd {
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uint8_t gpu_pd_type;
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uint8_t address;
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uint32_t flags;
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uint32_t pdo;
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uint32_t rdo;
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uint8_t power_domain;
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uint8_t gpio_hpd;
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uint8_t gpio_interrupt;
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} __packed;

‎crc.h

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/**
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* The type of the CRC values.
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*
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* This type must be big enough to contain at least 32 bits.
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*/
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typedef uint32_t crc_t;
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/**
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* Calculate the initial crc value.
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*
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* \return The initial crc value.
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*/
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static inline crc_t crc_init(void)
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{
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return 0xffffffff;
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}
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/**
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* Static table used for the table_driven implementation.
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*/
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static const crc_t crc_table[256] = {
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0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,
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0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
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0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
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0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
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0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
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0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
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0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,
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0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
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0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
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0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
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0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106,
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0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
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0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,
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0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
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0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
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0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
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0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,
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0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
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0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,
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0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
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0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
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0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
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0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,
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0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
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0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
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0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
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0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
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0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
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0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,
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0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
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0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,
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0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
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0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
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0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
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0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
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0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
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0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,
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0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
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0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
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0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
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0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,
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0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
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0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
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};
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crc_t crc_update(crc_t crc, const void *data, size_t data_len)
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{
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const unsigned char *d = (const unsigned char *)data;
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unsigned int tbl_idx;
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while (data_len--) {
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tbl_idx = (crc ^ *d) & 0xff;
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crc = (crc_table[tbl_idx] ^ (crc >> 8)) & 0xffffffff;
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d++;
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}
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return crc & 0xffffffff;
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}
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/**
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* Calculate the final crc value.
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*
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* \param[in] crc The current crc value.
84+
* \return The final crc value.
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*/
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static inline crc_t crc_finalize(crc_t crc)
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{
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return crc ^ 0xffffffff;
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}

‎eeprom.bin

194 Bytes
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