diff --git a/GammaALU.vhdl b/GammaALU.vhdl
index ff7c0bf..5b5ba4d 100644
--- a/GammaALU.vhdl
+++ b/GammaALU.vhdl
@@ -7,7 +7,7 @@ entity GammaALU is
         clk: in std_logic; -- Clock signal.
         a : in std_logic_vector(31 downto 0);  -- Operand A.
         b : in std_logic_vector(31 downto 0);  -- Operand B.
-        op : in std_logic_vector(3 downto 0);  -- Operation code.
+        op : in unsigned(15 downto 0);  -- Operation code.
         result : out std_logic_vector(31 downto 0);  -- Result of the operation.
         reset : in std_logic; -- Active high reset.
         enable: in std_logic  -- Active high enable signal.
@@ -21,50 +21,50 @@ begin
         if reset = '1' then
             result <= (others => '0');
         elsif rising_edge(clk) and enable = '1' then
-            case op is
-                when "0000" =>  -- ADD
+            case to_integer(op) is
+                when 0 =>  -- ADD
                     result <= std_logic_vector(signed(a) + signed(b));
-                when "0001" =>  -- SUB
+                when 1 =>  -- SUB
                     result <= std_logic_vector(signed(a) - signed(b));
-                when "0010" =>  -- MUL
+                when 2 =>  -- MUL
                     result <= std_logic_vector(resize(signed(a) * signed(b), 32));  -- Resize to 32 bits
-                when "0011" =>  -- DIV
+                when 3 =>  -- DIV
                     if b /= "00000000000000000000000000000000" then
                         result <= std_logic_vector(signed(a) / signed(b));
                     else
                         result <= (others => '0');  -- Handle division by zero
                     end if;
-                when "0100" => -- equal
+                when 4 => -- equal
                     if a = b then
                         result <= std_logic_vector(to_signed(1, 32));
                     else
                         result <= std_logic_vector(to_signed(0, 32));
                     end if;
-                when "0101" => -- inequality
+                when 5 => -- inequality
                     if a /= b then
                         result <= std_logic_vector(to_signed(1, 32));
                     else
                         result <= std_logic_vector(to_signed(0, 32));
                     end if;
-                when "0110" => -- greater than
+                when 6 => -- greater than
                     if a > b then
                         result <= std_logic_vector(to_signed(1, 32));
                     else
                         result <= std_logic_vector(to_signed(0, 32));
                     end if;
-                when "0111" => -- less than
+                when 7 => -- less than
                     if a < b then
                         result <= std_logic_vector(to_signed(1, 32));
                     else
                         result <= std_logic_vector(to_signed(0, 32));
                     end if;
-                when "1000" => -- greater than or equal to
+                when 8 => -- greater than or equal to
                     if a >= b then
                         result <= std_logic_vector(to_signed(1, 32));
                     else
                         result <= std_logic_vector(to_signed(0, 32));
                     end if;
-                when "1001" => -- less than or equal to
+                when 9 => -- less than or equal to
                     if a <= b then
                         result <= std_logic_vector(to_signed(1, 32));
                     else
diff --git a/GammaCPU.vhdl b/GammaCPU.vhdl
index 3d4b017..c75fb53 100644
--- a/GammaCPU.vhdl
+++ b/GammaCPU.vhdl
@@ -31,7 +31,7 @@ architecture Behavioral of GammaCPU is
         port(
             a : in std_logic_vector(31 downto 0);  -- Operand A.
             b : in std_logic_vector(31 downto 0);  -- Operand B.
-            op : in std_logic_vector(3 downto 0);  -- Operation code.
+            op : in unsigned(15 downto 0);  -- Operation code.
             result : out std_logic_vector(31 downto 0);  -- Result of the operation.
             reset : in std_logic;  -- Active high reset.
             enable : in std_logic;  -- Active high to perform the operation.
@@ -58,7 +58,7 @@ architecture Behavioral of GammaCPU is
     signal alu_result : std_logic_vector(31 downto 0) := (others => '0');
 
     -- ALU inputs and outputs
-    signal alu_op : std_logic_vector(3 downto 0);
+    signal alu_op : unsigned(15 downto 0);
     signal alu_a, alu_b : std_logic_vector(31 downto 0);
     signal alu_enable : std_logic;
 
@@ -125,49 +125,49 @@ begin
                             state <= StackOperation;
 
                         when x"6A" =>  -- i32.add
-                            alu_op <= "0000";  -- ADD
+                            alu_op <= to_unsigned(0, 16); -- ADD
                             state <= Execute;
 
                         when x"6B" =>  -- i32.sub
-                            alu_op <= "0001";  -- SUB
+                            alu_op <= to_unsigned(1, 16);  -- SUB
                             state <= Execute;
 
                         when x"6C" =>  -- i32.mul
-                            alu_op <= "0010";  -- MUL
+                            alu_op <= to_unsigned(2, 16);  -- MUL
                             state <= Execute;
 
                         when x"6D" =>  -- i32.div_s
-                            alu_op <= "0011";  -- DIV
+                            alu_op <= to_unsigned(3, 16);  -- DIV
                             state <= Execute;
 
                         -- Comparisions
                         when x"45" =>  -- i32.eqz
-                            alu_op <= "0100";  -- Equal to zero
+                            alu_op <= to_unsigned(4, 16);  -- Equal to zero
                             only_first_stack <= '1';
                             state <= Execute;
 
                         when x"46" =>  -- i32.eq
-                            alu_op <= "0100";  -- Equal
+                            alu_op <= to_unsigned(5, 16);  -- Equal
                             state <= Execute;
                         
                         when x"47" =>  -- i32.ne
-                            alu_op <= "0101";  -- Not Equal
+                            alu_op <= to_unsigned(6, 16);  -- Not Equal
                             state <= Execute;
 
                         when x"4b" =>  -- i32.gt_s
-                            alu_op <= "0110";  -- Greater than
+                            alu_op <= to_unsigned(7, 16);  -- Greater than
                             state <= Execute;
 
                         when x"48" =>  -- i32.lt_s
-                            alu_op <= "0111";  -- Less than
+                            alu_op <= to_unsigned(8, 16);  -- Less than
                             state <= Execute;
                         
                         when x"4e" =>  -- i32.ge_s
-                            alu_op <= "1000";  -- Greater than or equal
+                            alu_op <= to_unsigned(9, 16);  -- Greater than or equal
                             state <= Execute;
 
                         when x"4C" =>  -- i32.le_s
-                            alu_op <= "1001";  -- Less than or equal
+                            alu_op <= to_unsigned(10, 16);  -- Less than or equal
                             state <= Execute;
 
                         when others =>
diff --git a/test/alu/Testbench.vhdl b/test/alu/Testbench.vhdl
index 122360b..805f640 100644
--- a/test/alu/Testbench.vhdl
+++ b/test/alu/Testbench.vhdl
@@ -8,7 +8,7 @@ end ALUTestbench;
 architecture Behavioral of ALUTestbench is
     signal a : std_logic_vector(31 downto 0);
     signal b : std_logic_vector(31 downto 0);
-    signal op : std_logic_vector(3 downto 0);
+    signal op : unsigned(15 downto 0);
     signal result : std_logic_vector(31 downto 0);
     signal reset : std_logic;
     signal enable : std_logic;
@@ -21,7 +21,7 @@ architecture Behavioral of ALUTestbench is
             clk : in std_logic;  -- Clock.
             a : in std_logic_vector(31 downto 0);  -- Operand A.
             b : in std_logic_vector(31 downto 0);  -- Operand B.
-            op : in std_logic_vector(3 downto 0);  -- Operation code.
+            op : in unsigned(15 downto 0);  -- Operation code.
             result : out std_logic_vector(31 downto 0);  -- Result of the operation.
             reset : in std_logic;  -- Active high reset.
             enable : in std_logic  -- Active high to perform the operation.
@@ -65,7 +65,7 @@ begin
         -- Test 1 - positive addition
         a <= std_logic_vector(to_signed(5, 32));
         b <= std_logic_vector(to_signed(2, 32));
-        op <= "0000";
+        op <= to_unsigned(0, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= 7 then
@@ -75,7 +75,7 @@ begin
         -- Test 2 - two negative numbers addition, a negative result
         a <= std_logic_vector(to_signed(-5, 32));
         b <= std_logic_vector(to_signed(-2, 32));
-        op <= "0000";
+        op <= to_unsigned(0, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= -7 then
@@ -85,7 +85,7 @@ begin
         -- Test 3 - two negative numbers addition, a positive result
         a <= std_logic_vector(to_signed(-5, 32));
         b <= std_logic_vector(to_signed(7, 32));
-        op <= "0000";
+        op <= to_unsigned(0, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= 2 then
@@ -95,7 +95,7 @@ begin
         -- Test 4 - one negative one positive number addition, a negative result
         a <= std_logic_vector(to_signed(-5, 32));
         b <= std_logic_vector(to_signed(2, 32));
-        op <= "0000";
+        op <= to_unsigned(0, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= -3 then
@@ -105,7 +105,7 @@ begin
         -- Test 5 - one negative one positive number addition, a positive result
         a <= std_logic_vector(to_signed(5, 32));
         b <= std_logic_vector(to_signed(-2, 32));
-        op <= "0000";
+        op <= to_unsigned(0, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= 3 then
@@ -115,7 +115,7 @@ begin
         -- Test 6 - positive subtraction
         a <= std_logic_vector(to_signed(5, 32));
         b <= std_logic_vector(to_signed(2, 32));
-        op <= "0001";
+        op <= to_unsigned(1, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= 3 then
@@ -125,7 +125,7 @@ begin
         -- Test 7 - two negative numbers subtraction, a negative result
         a <= std_logic_vector(to_signed(-5, 32));
         b <= std_logic_vector(to_signed(-2, 32));
-        op <= "0001";
+        op <= to_unsigned(1, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= -3 then
@@ -135,7 +135,7 @@ begin
         -- Test 8 - two negative numbers subtraction, a positive result
         a <= std_logic_vector(to_signed(-5, 32));
         b <= std_logic_vector(to_signed(-7, 32));
-        op <= "0001";
+        op <= to_unsigned(1, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= 2 then
@@ -145,7 +145,7 @@ begin
         -- Test 9 - one negative one positive number subtraction, a negative result
         a <= std_logic_vector(to_signed(-5, 32));
         b <= std_logic_vector(to_signed(2, 32));
-        op <= "0001";
+        op <= to_unsigned(1, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= -7 then
@@ -155,7 +155,7 @@ begin
         -- Test 10 - one negative one positive number subtraction, a positive result
         a <= std_logic_vector(to_signed(5, 32));
         b <= std_logic_vector(to_signed(-2, 32));
-        op <= "0001";
+        op <= to_unsigned(1, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= 7 then
@@ -165,7 +165,7 @@ begin
         -- Test 11 - positive multiplication
         a <= std_logic_vector(to_signed(5, 32));
         b <= std_logic_vector(to_signed(2, 32));
-        op <= "0010";
+        op <= to_unsigned(2, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= 10 then
@@ -175,7 +175,7 @@ begin
         -- Test 12 - two negative numbers multiplication, a negative result
         a <= std_logic_vector(to_signed(-5, 32));
         b <= std_logic_vector(to_signed(-2, 32));
-        op <= "0010";
+        op <= to_unsigned(2, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= 10 then
@@ -185,7 +185,7 @@ begin
         -- Test 13 - two negative numbers multiplication, a positive result
         a <= std_logic_vector(to_signed(-5, 32));
         b <= std_logic_vector(to_signed(-7, 32));
-        op <= "0010";
+        op <= to_unsigned(2, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= 35 then
@@ -195,7 +195,7 @@ begin
         -- Test 14 - one negative one positive number multiplication, a negative result
         a <= std_logic_vector(to_signed(-5, 32));
         b <= std_logic_vector(to_signed(2, 32));
-        op <= "0010";
+        op <= to_unsigned(2, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= -10 then
@@ -205,7 +205,7 @@ begin
         -- Test 15 - one negative one positive number multiplication, a positive result
         a <= std_logic_vector(to_signed(5, 32));
         b <= std_logic_vector(to_signed(-2, 32));
-        op <= "0010";
+        op <= to_unsigned(2, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= -10 then
@@ -215,7 +215,7 @@ begin
         -- Test 16 - positive division
         a <= std_logic_vector(to_signed(10, 32));
         b <= std_logic_vector(to_signed(2, 32));
-        op <= "0011";
+        op <= to_unsigned(3, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= 5 then
@@ -225,7 +225,7 @@ begin
         -- Test 17 - two negative numbers division, a negative result
         a <= std_logic_vector(to_signed(-10, 32));
         b <= std_logic_vector(to_signed(-2, 32));
-        op <= "0011";
+        op <= to_unsigned(3, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= 5 then
@@ -235,7 +235,7 @@ begin
         -- Test 18 - one negative (negative first), one positive number division, a negative result
         a <= std_logic_vector(to_signed(-10, 32));
         b <= std_logic_vector(to_signed(2, 32));
-        op <= "0011";
+        op <= to_unsigned(3, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= -5 then
@@ -245,7 +245,7 @@ begin
         -- Test 19 - one negative (positive first), one positive number division, a negative result
         a <= std_logic_vector(to_signed(10, 32));
         b <= std_logic_vector(to_signed(-2, 32));
-        op <= "0011";
+        op <= to_unsigned(3, 16);
 
         if to_integer(signed(result)) /= -5 then
             report "___FAILOUT Can't divide 10 by -2, got " & integer'image(to_integer(signed(result))) & " instead of -5";
@@ -254,7 +254,7 @@ begin
         -- Test 20 - division by zero
         a <= std_logic_vector(to_signed(10, 32));
         b <= std_logic_vector(to_signed(0, 32));
-        op <= "0011";
+        op <= to_unsigned(3, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= 0 then
@@ -264,7 +264,7 @@ begin
         -- Test 21 - divison of zero
         a <= std_logic_vector(to_signed(0, 32));
         b <= std_logic_vector(to_signed(10, 32));
-        op <= "0011";
+        op <= to_unsigned(3, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= 0 then
@@ -275,7 +275,7 @@ begin
         -- Test 1 - A == B results in True
         a <= std_logic_vector(to_signed(10, 32));
         b <= std_logic_vector(to_signed(10, 32));
-        op <= "0100";
+        op <= to_unsigned(4, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= 1 then
@@ -285,7 +285,7 @@ begin
         -- Test 2 - A == B results in False
         a <= std_logic_vector(to_signed(10, 32));
         b <= std_logic_vector(to_signed(5, 32));
-        op <= "0100";
+        op <= to_unsigned(4, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= 0 then
@@ -295,7 +295,7 @@ begin
         -- Test 3 - A != B results in True
         a <= std_logic_vector(to_signed(10, 32));
         b <= std_logic_vector(to_signed(5, 32));
-        op <= "0101";
+        op <= to_unsigned(5, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= 1 then
@@ -305,7 +305,7 @@ begin
         -- Test 4 - A != B results in False
         a <= std_logic_vector(to_signed(10, 32));
         b <= std_logic_vector(to_signed(10, 32));
-        op <= "0101";
+        op <= to_unsigned(5, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= 0 then
@@ -315,7 +315,7 @@ begin
         -- Test 5 - A > B results in True
         a <= std_logic_vector(to_signed(10, 32));
         b <= std_logic_vector(to_signed(5, 32));
-        op <= "0110";
+        op <= to_unsigned(6, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= 1 then
@@ -325,7 +325,7 @@ begin
         -- Test 6 - A > B results in False
         a <= std_logic_vector(to_signed(10, 32));
         b <= std_logic_vector(to_signed(15, 32));
-        op <= "0110";
+        op <= to_unsigned(6, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= 0 then
@@ -335,7 +335,7 @@ begin
         -- Test 7 - A < B results in True
         a <= std_logic_vector(to_signed(5, 32));
         b <= std_logic_vector(to_signed(10, 32));
-        op <= "0111";
+        op <= to_unsigned(7, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= 1 then
@@ -345,7 +345,7 @@ begin
         -- Test 8 - A < B results in False
         a <= std_logic_vector(to_signed(20, 32));
         b <= std_logic_vector(to_signed(15, 32));
-        op <= "0111";
+        op <= to_unsigned(7, 16);
         wait for 10 ns;
 
         if to_integer(signed(result)) /= 0 then