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simd_utils.h
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/*
* Project : SIMD_Utils
* Version : 0.2.6
* Author : JishinMaster
* Licence : BSD-2
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define MAJOR_VERSION 0
#define MINOR_VERSION 2
#define SUB_VERSION 6
#ifdef OMP
#include <omp.h>
#endif
#include <math.h>
#include <fenv.h>
#include <stdint.h>
#include <stdio.h>
#include "simd_utils_constants.h"
#include "mysincosf.h"
/* if the user insures that all of their pointers are aligned,
* they can use ALWAYS_ALIGNED to hope for some minor speedup on small vectors
*/
static inline int isAligned(uintptr_t ptr, size_t alignment)
{
#ifndef ALWAYS_ALIGNED
#ifndef ARM // ARM manages disalignment in hardware
if (((uintptr_t) (ptr) % alignment) == 0)
return 1;
return 0;
#else
return 1;
#endif
#else
return 1;
#endif
}
static inline int areAligned2(uintptr_t ptr1, uintptr_t ptr2, size_t alignment)
{
#ifndef ALWAYS_ALIGNED
#ifndef ARM // ARM manages disalignment in hardware
if (((uintptr_t) (ptr1) % alignment) == 0)
if (((uintptr_t) (ptr2) % alignment) == 0)
return 1;
return 0;
#else
return 1;
#endif
#else
return 1;
#endif
}
static inline int areAligned3(uintptr_t ptr1, uintptr_t ptr2, uintptr_t ptr3, size_t alignment)
{
#ifndef ALWAYS_ALIGNED
#ifndef ARM // ARM manages disalignment in hardware
if (((uintptr_t) (ptr1) % alignment) == 0)
if (((uintptr_t) (ptr2) % alignment) == 0)
if (((uintptr_t) (ptr3) % alignment) == 0)
return 1;
return 0;
#else
return 1;
#endif
#else
return 1;
#endif
}
static inline void simd_utils_get_version(void)
{
printf("Simd Utils Version : %d.%d.%d\n", MAJOR_VERSION, MINOR_VERSION, SUB_VERSION);
}
// Produce value of bit n. n must be less than 32.
#define Bit(n) ((uint32_t) 1 << (n))
// Create a mask of n bits in the low bits. n must be less than 32.
#define Mask(n) (Bit(n) - 1)
/* Convert an IEEE-754 16-bit binary floating-point encoding to an IEEE-754
32-bit binary floating-point encoding.
This code has not been tested.
*/
//From https://stackoverflow.com/questions/71120169/bit-shifting-a-half-float-into-a-float/71125539#71125539
static inline uint32_t Float16ToFloat32(uint16_t x)
{
/* Separate the sign encoding (1 bit starting at bit 15), the exponent
encoding (5 bits starting at bit 10), and the primary significand
(fraction) encoding (10 bits starting at bit 0).
*/
uint32_t s = x >> 15;
uint32_t e = x >> 10 & Mask( 5);
uint32_t f = x & Mask(10);
// Left-adjust the significand field.
f <<= 23 - 10;
// Switch to handle subnormal numbers, normal numbers, and infinities/NaNs.
switch (e)
{
// Exponent code is subnormal.
case 0:
// Zero does need any changes, but subnormals need normalization.
if (f != 0)
{
/* Set the 32-bit exponent code corresponding to the 16-bit
subnormal exponent.
*/
e = 1 + (127 - 15);
/* Normalize the significand by shifting until its leading
bit moves out of the field. (This code could benefit from
a find-first-set instruction or possibly using a conversion
from integer to floating-point to do the normalization.)
*/
while (f < Bit(23))
{
f <<= 1;
e -= 1;
}
// Remove the leading bit.
f &= Mask(23);
}
break;
// Exponent code is normal.
default:
e += 127 - 15; // Adjust from 16-bit bias to 32-bit bias.
break;
// Exponent code indicates infinity or NaN.
case 31:
e = 255; // Set 32-bit exponent code for infinity or NaN.
break;
}
// Assemble and return the 32-bit encoding.
return s << 31 | e << 23 | f;
}
static inline uint32_t float_as_uint32 (float a)
{
float* ret = &a;
return *((uint32_t *)ret);
}
static inline float uint32_as_float (uint32_t a)
{
uint32_t* ret = &a;
return *((float *)ret);
}
//From https://stackoverflow.com/questions/76799117/how-to-convert-a-float-to-a-half-type-and-the-other-way-around-in-c
static inline uint16_t float2half_rn (float a)
{
uint32_t ia = float_as_uint32 (a);
uint16_t ir;
ir = (ia >> 16) & 0x8000;
if ((ia & 0x7f800000) == 0x7f800000) {
if ((ia & 0x7fffffff) == 0x7f800000) {
ir |= 0x7c00; /* infinity */
} else {
ir |= 0x7e00 | ((ia >> (24 - 11)) & 0x1ff); /* NaN, quietened */
}
} else if ((ia & 0x7f800000) >= 0x33000000) {
int shift = (int)((ia >> 23) & 0xff) - 127;
if (shift > 15) {
ir |= 0x7c00; /* infinity */
} else {
ia = (ia & 0x007fffff) | 0x00800000; /* extract mantissa */
if (shift < -14) { /* denormal */
ir |= ia >> (-1 - shift);
ia = ia << (32 - (-1 - shift));
} else { /* normal */
ir |= ia >> (24 - 11);
ia = ia << (32 - (24 - 11));
ir = ir + ((14 + shift) << 10);
}
/* IEEE-754 round to nearest of even */
if ((ia > 0x80000000) || ((ia == 0x80000000) && (ir & 1))) {
ir++;
}
}
}
return ir;
}
static inline void fp32tofp16_C (float* src, uint16_t* dst, size_t len)
{
for (int i = 0; i < len; i ++) {
dst[i] = float2half_rn(src[i]);
}
}
static inline void fp16tofp32_C (uint16_t* src, float* dst, size_t len)
{
for (int i = 0; i < len; i ++) {
dst[i] = uint32_as_float(Float16ToFloat32(src[i]));
}
}
#ifdef SSE
#ifdef NO_SSE3
#define NO_SSE4
static inline __m128 _mm_movehdup_ps(__m128 __X)
{
return _mm_shuffle_ps(__X, __X, 0xF5);
}
static inline __m128 _mm_moveldup_ps(__m128 __X)
{
return _mm_shuffle_ps(__X, __X, 0xA0);
}
#endif
#ifdef NO_SSE4
static inline __m128i _mm_cmpeq_epi64(__m128i __X, __m128i __Y)
{
int64_t *ptr_x = (int64_t *) &__X;
int64_t *ptr_y = (int64_t *) &__Y;
__m128i ret;
int64_t *ptr_ret = (int64_t *) &ret;
ptr_ret[0] = (ptr_x[0] == ptr_y[0]) ? 0xFFFFFFFFFFFFFFFF : 0;
ptr_ret[1] = (ptr_x[1] == ptr_y[1]) ? 0xFFFFFFFFFFFFFFFF : 0;
return ret;
}
static inline __m128d _mm_blendv_pd(__m128d __X, __m128d __Y, __m128d __M)
{
__m128d b_tmp = _mm_and_pd(__Y, __M);
__m128d a_tmp = _mm_and_pd(__X, _mm_cmpeq_pd(__M, *(__m128d *) _pd_zero));
return _mm_or_pd(a_tmp, b_tmp);
}
static inline __m128 _mm_blendv_ps(__m128 __X, __m128 __Y, __m128 __M)
{
__m128 b_tmp = _mm_and_ps(__Y, __M);
__m128 a_tmp = _mm_and_ps(__X, _mm_cmpeq_ps(__M, *(__m128 *) _ps_zero));
return _mm_or_ps(a_tmp, b_tmp);
}
static inline __m128i _mm_stream_load_si128(__m128i *__X)
{
return _mm_load_si128(__X);
}
static inline __m128 _mm_round_ps(__m128 X, int mode)
{
__m128 ret;
__m128i reti;
unsigned int old_mode = _MM_GET_ROUNDING_MODE();
switch (mode) {
case _MM_FROUND_TRUNC:
case _MM_ROUND_TOWARD_ZERO:
case ROUNDTOZERO:
_MM_SET_ROUNDING_MODE(_MM_ROUND_TOWARD_ZERO);
break;
case ROUNDTOCEIL:
case _MM_ROUND_UP:
_MM_SET_ROUNDING_MODE(_MM_ROUND_UP);
break;
case ROUNDTOFLOOR:
case _MM_ROUND_DOWN:
_MM_SET_ROUNDING_MODE(_MM_ROUND_DOWN);
break;
default:
//_MM_SET_ROUNDING_MODE(_MM_ROUND_NEAREST);
break;
}
reti = _mm_cvtps_epi32(X);
ret = _mm_cvtepi32_ps(reti);
_MM_SET_ROUNDING_MODE(old_mode);
return ret;
}
/* not accurate but might do the trick for most cases
where the full range is not needed */
static inline __m128i _mm_packus_epi32(__m128i a, __m128i b)
{
return _mm_packs_epi32(a, b);
}
// https://gist.github.com/cxd4/8137986
#define SWAP(d3, d2, d1, d0) ((d3 << 6) | (d2 << 4) | (d1 << 2) | (d0 << 0))
static __m128i _mm_mullo_epi32(__m128i a, __m128i b)
{
__m128i prod_m; /* alternating FFFFFFFF00000000FFFFFFFF00000000 */
__m128i prod_n; /* alternating 00000000FFFFFFFF00000000FFFFFFFF */
prod_n = _mm_mul_epu32(a, b);
a = _mm_shuffle_epi32(a, SWAP(2, 3, 0, 1)); /* old SWAP(3,2,1,0) */
b = _mm_shuffle_epi32(b, SWAP(2, 3, 0, 1)); /* old SWAP(3,2,1,0) */
prod_m = _mm_mul_epu32(a, b);
/*
* prod_m = { a[0] * b[0], a[2] * b[2] }
* prod_n = { a[1] * b[1], a[3] * b[3] }
*/
a = _mm_unpacklo_epi32(prod_n, prod_m);
a = _mm_slli_si128(a, 64 / 8);
a = _mm_srli_si128(a, 64 / 8);
b = _mm_unpackhi_epi32(prod_n, prod_m);
b = _mm_slli_si128(b, 64 / 8);
b = _mm_or_si128(b, a); /* Ans = (hi << 64) | (lo & 0x00000000FFFFFFFF) */
return (b);
}
// Or : https://stackoverflow.com/questions/17264399/fastest-way-to-multiply-two-vectors-of-32bit-integers-in-c-with-sse
// Vec4i operator * (Vec4i const & a, Vec4i const & b) {
/*
__m128i a13 = _mm_shuffle_epi32(a, 0xF5); // (-,a3,-,a1)
__m128i b13 = _mm_shuffle_epi32(b, 0xF5); // (-,b3,-,b1)
__m128i prod02 = _mm_mul_epu32(a, b); // (-,a2*b2,-,a0*b0)
__m128i prod13 = _mm_mul_epu32(a13, b13); // (-,a3*b3,-,a1*b1)
__m128i prod01 = _mm_unpacklo_epi32(prod02,prod13); // (-,-,a1*b1,a0*b0)
__m128i prod23 = _mm_unpackhi_epi32(prod02,prod13); // (-,-,a3*b3,a2*b2)
__m128i prod = _mm_unpacklo_epi64(prod01,prod23); // (ab3,ab2,ab1,ab0)
*/
#endif
#ifndef ARM
#include "sse_mathfun.h"
#else /* ARM */
#include "neon_mathfun.h"
#endif /* ARM */
//_mm_movehl_ps vs shuffle(1,0,3,2)?
static inline v2sd _mm_cvtps_pd_high(v4sf in){
#if defined(__aarch64__)
return vcvt_high_f64_f32(in);
#else
return _mm_cvtps_pd(_mm_movehl_ps(in, in));
#endif
}
static inline v4sf _mm_cvtpd2_ps(v2sd low, v2sd high){
#if defined(__aarch64__)
return vcombine_f32(vcvt_f32_f64(low), vcvt_f32_f64(high));
#else
return _mm_movelh_ps(_mm_cvtpd_ps(low), _mm_cvtpd_ps(high));
#endif
}
static inline v4sfx2 _mm_load2_ps(float const *mem_addr)
{
#ifdef ARM
return vld2q_f32(mem_addr);
#else
v4sf tmp1 = _mm_load_ps(mem_addr);
v4sf tmp2 = _mm_load_ps(mem_addr + SSE_LEN_FLOAT);
v4sfx2 ret;
ret.val[0] = _mm_shuffle_ps(tmp1, tmp2, _MM_SHUFFLE(2, 0, 2, 0));
ret.val[1] = _mm_shuffle_ps(tmp1, tmp2, _MM_SHUFFLE(3, 1, 3, 1));
return ret;
#endif
}
static inline v4sfx2 _mm_load2u_ps(float const *mem_addr)
{
#ifdef ARM
return vld2q_f32(mem_addr);
#else
v4sf tmp1 = _mm_loadu_ps(mem_addr);
v4sf tmp2 = _mm_loadu_ps(mem_addr + SSE_LEN_FLOAT);
v4sfx2 ret;
ret.val[0] = _mm_shuffle_ps(tmp1, tmp2, _MM_SHUFFLE(2, 0, 2, 0));
ret.val[1] = _mm_shuffle_ps(tmp1, tmp2, _MM_SHUFFLE(3, 1, 3, 1));
return ret;
#endif
}
static inline void _mm_store2_ps(float *mem_addr, v4sfx2 a)
{
#ifdef ARM
vst2q_f32(mem_addr, a);
#else
v4sf tmp1 = _mm_unpacklo_ps(a.val[0], a.val[1]);
v4sf tmp2 = _mm_unpackhi_ps(a.val[0], a.val[1]);
_mm_store_ps(mem_addr, tmp1);
_mm_store_ps(mem_addr + SSE_LEN_FLOAT, tmp2);
#endif
}
static inline void _mm_store2u_ps(float *mem_addr, v4sfx2 a)
{
#ifdef ARM
vst2q_f32(mem_addr, a);
#else
v4sf tmp1 = _mm_unpacklo_ps(a.val[0], a.val[1]);
v4sf tmp2 = _mm_unpackhi_ps(a.val[0], a.val[1]);
_mm_storeu_ps(mem_addr, tmp1);
_mm_storeu_ps(mem_addr + SSE_LEN_FLOAT, tmp2);
#endif
}
static inline v2sdx2 _mm_load2_pd(double const *mem_addr)
{
#if defined(__aarch64__)
return vld2q_f64(mem_addr);
#else
v2sd tmp1 = _mm_load_pd(mem_addr);
v2sd tmp2 = _mm_load_pd(mem_addr + SSE_LEN_DOUBLE);
v2sdx2 ret;
ret.val[0] = _mm_shuffle_pd(tmp1, tmp2, _MM_SHUFFLE2(0, 0));
ret.val[1] = _mm_shuffle_pd(tmp1, tmp2, _MM_SHUFFLE2(1, 1));
return ret;
#endif
}
static inline v2sdx2 _mm_load2u_pd(double const *mem_addr)
{
#if defined(__aarch64__)
return vld2q_f64(mem_addr);
#else
v2sd tmp1 = _mm_loadu_pd(mem_addr);
v2sd tmp2 = _mm_loadu_pd(mem_addr + SSE_LEN_DOUBLE);
v2sdx2 ret;
ret.val[0] = _mm_shuffle_pd(tmp1, tmp2, _MM_SHUFFLE2(0, 0));
ret.val[1] = _mm_shuffle_pd(tmp1, tmp2, _MM_SHUFFLE2(1, 1));
return ret;
#endif
}
static inline void _mm_store2_pd(double *mem_addr, v2sdx2 a)
{
#if defined(__aarch64__)
vst2q_f64(mem_addr, a);
#else
v2sd tmp1 = _mm_unpacklo_pd(a.val[0], a.val[1]);
v2sd tmp2 = _mm_unpackhi_pd(a.val[0], a.val[1]);
_mm_store_pd(mem_addr, tmp1);
_mm_store_pd(mem_addr + SSE_LEN_DOUBLE, tmp2);
#endif
}
static inline void _mm_store2u_pd(double *mem_addr, v2sdx2 a)
{
#if defined(__aarch64__)
vst2q_f64(mem_addr, a);
#else
v2sd tmp1 = _mm_unpacklo_pd(a.val[0], a.val[1]);
v2sd tmp2 = _mm_unpackhi_pd(a.val[0], a.val[1]);
_mm_storeu_pd(mem_addr, tmp1);
_mm_storeu_pd(mem_addr + SSE_LEN_DOUBLE, tmp2);
#endif
}
static inline __m128 _mm_fmadd_ps_custom(__m128 a, __m128 b, __m128 c)
{
// Haswell comes with avx2 and fma
// ARM has vmla instead of fma in 32bits
#if defined(ARM) || defined(FMA)
return _mm_fmadd_ps(a, b, c);
#else
return _mm_add_ps(_mm_mul_ps(a, b), c);
#endif
}
//B is a scalar, some optimizations for ARM NEON
static inline __m128 _mm_fmadd1_ps_custom(__m128 a, __m128 b, __m128 c)
{
#if defined(ARM)
return _mm_fmadd1_ps(a, b, c);
#else
return _mm_fmadd_ps_custom(a,b,c);
#endif
}
#ifndef ARM
//B is a scalar, some optimizations for ARM NEON
static inline __m128 _mm_mul1_ps(__m128 a, __m128 b)
{
return _mm_mul_ps(a, b);
}
#endif
static inline __m128 _mm_fmaddsub_ps_custom(__m128 a, __m128 b, __m128 c)
{
#ifndef FMA // Haswell comes with avx2 and fma
return _mm_addsub_ps(_mm_mul_ps(a, b), c);
#else /* FMA */
return _mm_fmaddsub_ps(a, b, c);
#endif /* FMA */
}
static inline __m128 _mm_fmsubadd_ps_custom(__m128 a, __m128 b, __m128 c)
{
#if !defined(FMA) || defined(ARM)
v4sf d = _mm_mul_ps(*(v4sf *) _ps_conj_mask, c);
return _mm_addsub_ps(_mm_mul_ps(a, b), d);
#else /* FMA */
return _mm_fmsubadd_ps(a, b, c);
#endif /* FMA */
}
static inline __m128 _mm_fnmadd_ps_custom(__m128 a, __m128 b, __m128 c)
{
// Haswell comes with avx2 and fma
// ARM has vmla instead of fma in 32bits
#if defined(ARM) || defined(FMA)
return _mm_fnmadd_ps(a, b, c);
#else
return _mm_sub_ps(c, _mm_mul_ps(a, b));
#endif
}
//B is a scalar, some optimizations for ARM NEON
static inline __m128 _mm_fnmadd1_ps_custom(__m128 a, __m128 b, __m128 c)
{
#if defined(ARM)
return _mm_fnmadd1_ps(a, b, c);
#else
return _mm_fnmadd_ps_custom(a,b,c);
#endif
}
static inline __m128d _mm_fmadd_pd_custom(__m128d a, __m128d b, __m128d c)
{
#ifndef FMA // Haswell comes with avx2 and fma
return _mm_add_pd(_mm_mul_pd(a, b), c);
#else /* FMA */
return _mm_fmadd_pd(a, b, c);
#endif /* FMA */
}
static inline __m128d _mm_fnmadd_pd_custom(__m128d a, __m128d b, __m128d c)
{
#ifndef FMA // Haswell comes with avx2 and fma
return _mm_sub_pd(c, _mm_mul_pd(a, b));
#else /* FMA */
return _mm_fnmadd_pd(a, b, c);
#endif /* FMA */
}
//B is a scalar, some optimizations for ARM NEON
static inline __m128d _mm_fmadd1_pd_custom(__m128d a, __m128d b, __m128d c)
{
#if defined(ARM)
return _mm_fmadd1_pd(a, b, c);
#else
return _mm_fmadd_pd_custom(a,b,c);
#endif
}
//B is a scalar, some optimizations for ARM NEON
static inline __m128d _mm_fnmadd1_pd_custom(__m128d a, __m128d b, __m128d c)
{
#if defined(ARM)
return _mm_fnmadd1_pd(a, b, c);
#else
return _mm_fnmadd_pd_custom(a,b,c);
#endif
}
#ifndef ARM
//B is a scalar, some optimizations for ARM NEON
static inline __m128d _mm_mul1_pd(__m128d a, __m128d b)
{
return _mm_mul_pd(a, b);
}
#endif
// Work in progress
// in SSE, missing _mm_cvtepi64_pd, _mm_cvttpd_epi64
// See : https://stackoverflow.com/questions/41144668/how-to-efficiently-perform-double-int64-conversions-with-sse-avx
static inline v2sd _mm_cvtepi64_pd_custom(v2sid x)
{
#if 0
//Signed
x = _mm_add_epi64(x, _mm_castpd_si128(*(v2sd *) _pd_epi64_mask));
return _mm_sub_pd(_mm_castsi128_pd(x), *(v2sd *) _pd_epi64_mask);
#else
// unsigned
x = _mm_or_si128(x, _mm_castpd_si128(*(v2sd *) _pd_PDEPI64U));
return _mm_sub_pd(_mm_castsi128_pd(x), *(v2sd *) _pd_PDEPI64U);
#endif
}
static inline v2sd _mm_cvtepi64_pd_signed_custom(v2sid x)
{
// Signed
x = _mm_add_epi64(x, _mm_castpd_si128(*(v2sd *) _pd_epi64_mask));
return _mm_sub_pd(_mm_castsi128_pd(x), *(v2sd *) _pd_epi64_mask);
}
static inline v2sid _mm_cvtpd_epi64_custom(v2sd x)
{
#if defined(__aarch64__)
return vcvtq_s64_f64(x);
#else //ARM
// Signed
#if 1
x = _mm_add_pd(x, *(v2sd *) _pd_epi64_mask);
return _mm_sub_epi64(
_mm_castpd_si128(x),
_mm_castpd_si128(*(v2sd *) _pd_epi64_mask));
#else
// Unsigned
x = _mm_add_pd(x, *(v2sd *) _pd_PDEPI64U); //_mm_set1_pd(0x0010000000000000));
return _mm_xor_si128(
_mm_castpd_si128(x),
_mm_castpd_si128(*(v2sd *) _pd_PDEPI64U));
#endif
#endif // ARM
}
#include "simd_utils_sse_double.h"
#include "simd_utils_sse_float.h"
#include "simd_utils_sse_int32.h"
#endif /* SSE */
#ifdef AVX
#ifndef __clang__
#ifndef __INTEL_COMPILER
#ifndef __cplusplus // TODO : it seems to be defined with G++ 9.2 and not GCC 9.2
static inline __m256 _mm256_set_m128(__m128 H, __m128 L) // not present on every GCC version
{
return _mm256_insertf128_ps(_mm256_castps128_ps256(L), H, 1);
}
#endif
#endif
#endif /* __clang__ */
static inline __m256 _mm256_fmadd_ps_custom(__m256 a, __m256 b, __m256 c)
{
#ifndef FMA // Haswell comes with avx2 and fma
return _mm256_add_ps(_mm256_mul_ps(a, b), c);
#else /* FMA */
return _mm256_fmadd_ps(a, b, c);
#endif /* FMA */
}
static inline __m256 _mm256_fmaddsub_ps_custom(__m256 a, __m256 b, __m256 c)
{
#ifndef FMA // Haswell comes with avx2 and fma
return _mm256_addsub_ps(_mm256_mul_ps(a, b), c);
#else /* FMA */
return _mm256_fmaddsub_ps(a, b, c);
#endif /* FMA */
}
static inline __m256 _mm256_fnmadd_ps_custom(__m256 a, __m256 b, __m256 c)
{
#ifndef FMA // Haswell comes with avx2 and fma
return _mm256_sub_ps(c, _mm256_mul_ps(a, b));
#else /* FMA */
return _mm256_fnmadd_ps(a, b, c);
#endif /* FMA */
}
static inline __m256d _mm256_fmadd_pd_custom(__m256d a, __m256d b, __m256d c)
{
#ifndef FMA // Haswell comes with avx2 and fma
return _mm256_add_pd(_mm256_mul_pd(a, b), c);
#else /* FMA */
return _mm256_fmadd_pd(a, b, c);
#endif /* FMA */
}
static inline __m256d _mm256_fnmadd_pd_custom(__m256d a, __m256d b, __m256d c)
{
#ifndef FMA // Haswell comes with avx2 and fma
return _mm256_sub_pd(c, _mm256_mul_pd(a, b));
#else /* FMA */
return _mm256_fnmadd_pd(a, b, c);
#endif /* FMA */
}
// https://stackoverflow.com/questions/41144668/how-to-efficiently-perform-double-int64-conversions-with-sse-avx
// Only works for inputs in the range: [-2^51, 2^51]
static inline __m256i _mm256_cvtpd_epi64_custom(__m256d x)
{
x = _mm256_add_pd(x, *(v4sd *) _pd256_epi64_mask);
return _mm256_sub_epi64(
_mm256_castpd_si256(x),
_mm256_castpd_si256(*(v4sd *) _pd256_epi64_mask));
}
/*
static inline v4sid _mm256_cvtpd_epi64_custom(v4sd x)
{
x = _mm256_add_pd(x, *(v4sd *) _pd256_PDEPI64U);
return _mm256_xor_si256(
_mm256_castpd_si256(x),
_mm256_castpd_si256(*(v4sd *) _pd256_PDEPI64U));
}
*/
static inline v4sd _mm256_cvtepi64_pd_custom(v4sid x)
{
x = _mm256_or_si256(x, _mm256_castpd_si256(*(v4sd *) _pd256_PDEPI64U));
return _mm256_sub_pd(_mm256_castsi256_pd(x), *(v4sd *) _pd256_PDEPI64U);
}
static inline v4sd _mm256_cvtepi64_pd_signed_custom(v4sid x)
{
x = _mm256_add_epi64(x, _mm256_castpd_si256(*(v4sd *) _pd256_epi64_mask));
return _mm256_sub_pd(_mm256_castsi256_pd(x), *(v4sd *) _pd256_epi64_mask);
}
#include "avx_mathfun.h"
static inline v8sfx2 _mm256_load2_ps(float const *mem_addr)
{
v4sfx2 src_1 = _mm_load2_ps(mem_addr);
v4sfx2 src_2 = _mm_load2_ps(mem_addr + 2 * SSE_LEN_FLOAT);
v8sfx2 ret;
ret.val[0] = _mm256_set_m128(src_2.val[0], src_1.val[0]);
ret.val[1] = _mm256_set_m128(src_2.val[1], src_1.val[1]);
return ret;
}
static inline v8sfx2 _mm256_load2u_ps(float const *mem_addr)
{
v4sfx2 src_1 = _mm_load2u_ps(mem_addr);
v4sfx2 src_2 = _mm_load2u_ps(mem_addr + 2 * SSE_LEN_FLOAT);
v8sfx2 ret;
ret.val[0] = _mm256_set_m128(src_2.val[0], src_1.val[0]);
ret.val[1] = _mm256_set_m128(src_2.val[1], src_1.val[1]);
return ret;
}
static inline void _mm256_store2_ps(float *mem_addr, v8sfx2 a)
{
v8sf cplx0 = _mm256_unpacklo_ps(a.val[0], a.val[1]);
v8sf cplx1 = _mm256_unpackhi_ps(a.val[0], a.val[1]);
v8sf perm0 = _mm256_permute2f128_ps(cplx0, cplx1, 0x20); // permute mask [cplx1(127:0],cplx0[127:0])
v8sf perm1 = _mm256_permute2f128_ps(cplx0, cplx1, 0x31); // permute mask [cplx1(255:128],cplx0[255:128])
_mm256_store_ps(mem_addr, perm0);
_mm256_store_ps(mem_addr + AVX_LEN_FLOAT, perm1);
}
static inline void _mm256_store2u_ps(float *mem_addr, v8sfx2 a)
{
v8sf cplx0 = _mm256_unpacklo_ps(a.val[0], a.val[1]);
v8sf cplx1 = _mm256_unpackhi_ps(a.val[0], a.val[1]);
v8sf perm0 = _mm256_permute2f128_ps(cplx0, cplx1, 0x20); // permute mask [cplx1(127:0],cplx0[127:0])
v8sf perm1 = _mm256_permute2f128_ps(cplx0, cplx1, 0x31); // permute mask [cplx1(255:128],cplx0[255:128])
_mm256_storeu_ps(mem_addr, perm0);
_mm256_storeu_ps(mem_addr + AVX_LEN_FLOAT, perm1);
}
static inline v4sdx2 _mm256_load2_pd(double const *mem_addr)
{
v2sdx2 src_1 = _mm_load2_pd(mem_addr);
v2sdx2 src_2 = _mm_load2_pd(mem_addr + 2 * SSE_LEN_DOUBLE);
v4sdx2 ret;
ret.val[0] = _mm256_set_m128d(src_2.val[0], src_1.val[0]);
ret.val[1] = _mm256_set_m128d(src_2.val[1], src_1.val[1]);
return ret;
}
static inline v4sdx2 _mm256_load2u_pd(double const *mem_addr)
{
v2sdx2 src_1 = _mm_load2u_pd(mem_addr);
v2sdx2 src_2 = _mm_load2u_pd(mem_addr + 2 * SSE_LEN_DOUBLE);
v4sdx2 ret;
ret.val[0] = _mm256_set_m128d(src_2.val[0], src_1.val[0]);
ret.val[1] = _mm256_set_m128d(src_2.val[1], src_1.val[1]);
return ret;
}
static inline void _mm256_store2_pd(double *mem_addr, v4sdx2 a)
{
v4sd cplx0 = _mm256_unpacklo_pd(a.val[0], a.val[1]);
v4sd cplx1 = _mm256_unpackhi_pd(a.val[0], a.val[1]);
v4sd perm0 = _mm256_permute2f128_pd(cplx0, cplx1, 0x20); // permute mask [cplx1(127:0],cplx0[127:0])
v4sd perm1 = _mm256_permute2f128_pd(cplx0, cplx1, 0x31); // permute mask [cplx1(255:128],cplx0[255:128])
_mm256_store_pd(mem_addr, perm0);
_mm256_store_pd(mem_addr + AVX_LEN_DOUBLE, perm1);
}
static inline void _mm256_store2u_pd(double *mem_addr, v4sdx2 a)
{
v4sd cplx0 = _mm256_unpacklo_pd(a.val[0], a.val[1]);
v4sd cplx1 = _mm256_unpackhi_pd(a.val[0], a.val[1]);
v4sd perm0 = _mm256_permute2f128_pd(cplx0, cplx1, 0x20); // permute mask [cplx1(127:0],cplx0[127:0])
v4sd perm1 = _mm256_permute2f128_pd(cplx0, cplx1, 0x31); // permute mask [cplx1(255:128],cplx0[255:128])
_mm256_storeu_pd(mem_addr, perm0);
_mm256_storeu_pd(mem_addr + AVX_LEN_DOUBLE, perm1);
}
#include "simd_utils_avx_double.h"
#include "simd_utils_avx_float.h"
#include "simd_utils_avx_int32.h"
#endif /* AVX */
#ifdef AVX512
static const float _ps512_conj_mask[16] __attribute__((aligned(64))) = {1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f,
1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f, 1.0f, -1.0f};
static inline __m512 _mm512_fmadd_ps_custom(__m512 a, __m512 b, __m512 c)
{
return _mm512_fmadd_ps(a, b, c);
}
static inline __m512 _mm512_fmaddsub_ps_custom(__m512 a, __m512 b, __m512 c)
{
return _mm512_fmaddsub_ps(a, b, c);
}
static inline __m512 _mm512_fnmadd_ps_custom(__m512 a, __m512 b, __m512 c)
{
return _mm512_fnmadd_ps(a, b, c);
}
static inline __m512d _mm512_fmadd_pd_custom(__m512d a, __m512d b, __m512d c)
{
return _mm512_fmadd_pd(a, b, c);
}
static inline __m512d _mm512_fnmadd_pd_custom(__m512d a, __m512d b, __m512d c)
{
return _mm512_fnmadd_pd(a, b, c);
}
#include "avx512_mathfun.h"
static inline v16sfx2 _mm512_load2_ps(float const *mem_addr)
{
v16sf vec1 = _mm512_load_ps(mem_addr); // load 0 1 2 3 4 5 6 7
v16sf vec2 = _mm512_load_ps(mem_addr + AVX512_LEN_FLOAT); // load 8 9 10 11 12 13 14 15
v16sfx2 ret;
ret.val[0] = _mm512_permutex2var_ps(vec2, *(v16si *) _pi32_512_idx_re, vec1);
ret.val[1] = _mm512_permutex2var_ps(vec2, *(v16si *) _pi32_512_idx_im, vec1);
return ret;
}
static inline v16sfx2 _mm512_load2u_ps(float const *mem_addr)
{
v16sf vec1 = _mm512_loadu_ps(mem_addr); // load 0 1 2 3 4 5 6 7
v16sf vec2 = _mm512_loadu_ps(mem_addr + AVX512_LEN_FLOAT); // load 8 9 10 11 12 13 14 15
v16sfx2 ret;
ret.val[0] = _mm512_permutex2var_ps(vec2, *(v16si *) _pi32_512_idx_re, vec1);
ret.val[1] = _mm512_permutex2var_ps(vec2, *(v16si *) _pi32_512_idx_im, vec1);
return ret;
}
static inline void _mm512_store2_ps(float *mem_addr, v16sfx2 a)
{
v16sf tmp1 = _mm512_permutex2var_ps(a.val[1], *(v16si *) _pi32_512_idx_cplx_lo, a.val[0]);
v16sf tmp2 = _mm512_permutex2var_ps(a.val[1], *(v16si *) _pi32_512_idx_cplx_hi, a.val[0]);
_mm512_store_ps(mem_addr, tmp1);
_mm512_store_ps(mem_addr + AVX512_LEN_FLOAT, tmp2);
}
static inline void _mm512_store2u_ps(float *mem_addr, v16sfx2 a)
{
v16sf tmp1 = _mm512_permutex2var_ps(a.val[1], *(v16si *) _pi32_512_idx_cplx_lo, a.val[0]);
v16sf tmp2 = _mm512_permutex2var_ps(a.val[1], *(v16si *) _pi32_512_idx_cplx_hi, a.val[0]);
_mm512_storeu_ps(mem_addr, tmp1);
_mm512_storeu_ps(mem_addr + AVX512_LEN_FLOAT, tmp2);
}
static inline v8sdx2 _mm512_load2_pd(double const *mem_addr)
{
v8sd vec1 = _mm512_load_pd(mem_addr); // load 0 1 2 3 4 5 6 7
v8sd vec2 = _mm512_load_pd(mem_addr + AVX512_LEN_DOUBLE); // load 8 9 10 11 12 13 14 15
v8sdx2 ret;
ret.val[0] = _mm512_permutex2var_pd(vec2, *(v8sid *) _pi64_512_idx_re, vec1);
ret.val[1] = _mm512_permutex2var_pd(vec2, *(v8sid *) _pi64_512_idx_im, vec1);
return ret;
}
static inline v8sdx2 _mm512_load2u_pd(double const *mem_addr)
{
v8sd vec1 = _mm512_loadu_pd(mem_addr); // load 0 1 2 3 4 5 6 7
v8sd vec2 = _mm512_loadu_pd(mem_addr + AVX512_LEN_DOUBLE); // load 8 9 10 11 12 13 14 15
v8sdx2 ret;
ret.val[0] = _mm512_permutex2var_pd(vec2, *(v8sid *) _pi64_512_idx_re, vec1);
ret.val[1] = _mm512_permutex2var_pd(vec2, *(v8sid *) _pi64_512_idx_im, vec1);
return ret;
}
static inline void _mm512_store2_pd(double *mem_addr, v8sdx2 a)
{
v8sd tmp1 = _mm512_permutex2var_pd(a.val[1], *(v8sid *) _pi64_512_idx_cplx_lo, a.val[0]);
v8sd tmp2 = _mm512_permutex2var_pd(a.val[1], *(v8sid *) _pi64_512_idx_cplx_hi, a.val[0]);
_mm512_store_pd(mem_addr, tmp1);
_mm512_store_pd(mem_addr + AVX512_LEN_DOUBLE, tmp2);
}
static inline void _mm512_store2u_pd(double *mem_addr, v8sdx2 a)
{
v8sd tmp1 = _mm512_permutex2var_pd(a.val[1], *(v8sid *) _pi64_512_idx_cplx_lo, a.val[0]);
v8sd tmp2 = _mm512_permutex2var_pd(a.val[1], *(v8sid *) _pi64_512_idx_cplx_hi, a.val[0]);
_mm512_storeu_pd(mem_addr, tmp1);
_mm512_storeu_pd(mem_addr + AVX512_LEN_DOUBLE, tmp2);
}
#include "simd_utils_avx512_double.h"
#include "simd_utils_avx512_float.h"
#include "simd_utils_avx512_int32.h"
#endif /* AVX512 */
#ifdef ICC
#include "simd_utils_svml.h"
#endif
#ifdef AMDLIBM
#include "simd_utils_amdlibm.h"
#endif
#ifdef RISCV /* RISCV */
#ifndef __linux__
/* Get current value of CLOCK and store it in TP. */
int clock_gettime(clockid_t clock_id, struct timespec *tp)
{
struct timeval tv;
int retval = gettimeofday(&tv, NULL);
if (retval == 0)
/* Convert into `timespec'. */
TIMEVAL_TO_TIMESPEC(&tv, tp);
return retval;
}
#endif
static inline uint32_t _MM_GET_ROUNDING_MODE()
{
uint32_t reg;
asm volatile("frrm %0"
: "=r"(reg));
return reg;
}
static inline void _MM_SET_ROUNDING_MODE(uint32_t mode)
{
uint32_t reg;
switch (mode) {
case _MM_ROUND_NEAREST: //IEEE 754 round to nearest even
asm volatile("fsrmi %0,0"
: "=r"(reg));
break;
case _MM_ROUND_TOWARD_ZERO: // trunc
asm volatile("fsrmi %0,1"
: "=r"(reg));
break;
case _MM_ROUND_DOWN:
asm volatile("fsrmi %0,2"
: "=r"(reg));
break;
case _MM_ROUND_UP:
asm volatile("fsrmi %0,3"
: "=r"(reg));
break;
case _MM_ROUND_AWAY: //C round away from zero
asm volatile("fsrmi %0,4"
: "=r"(reg));
break;
default:
printf("_MM_SET_ROUNDING_MODE wrong mod requested %d\n", mode);
}
}
#include "simd_utils_riscv_double.h"
#include "simd_utils_riscv_float.h"
#include "simd_utils_riscv_int.h"
#endif /* RISCV */
#ifdef ALTIVEC
#include <altivec.h>
// Compare and perm operations => perm unit