diff --git a/Module.cc b/Module.cc
index 0b8a43a909..d880c00092 100644
--- a/Module.cc
+++ b/Module.cc
@@ -43,7 +43,7 @@ void Module::add_gate(PGate*gate)
 
 unsigned Module::port_count() const
 {
-      return ports.count();
+      return ports.size();
 }
 
 /*
@@ -51,10 +51,10 @@ unsigned Module::port_count() const
  * module. If the port is internally unconnected, return an empty
  * array.
  */
-const svector<PEIdent*>& Module::get_port(unsigned idx) const
+const vector<PEIdent*>& Module::get_port(unsigned idx) const
 {
-      assert(idx < ports.count());
-      static svector<PEIdent*> zero;
+      assert(idx < ports.size());
+      static const vector<PEIdent*> zero;
 
       if (ports[idx])
 	    return ports[idx]->expr;
@@ -65,7 +65,7 @@ const svector<PEIdent*>& Module::get_port(unsigned idx) const
 unsigned Module::find_port(const char*name) const
 {
       assert(name != 0);
-      for (unsigned idx = 0 ;  idx < ports.count() ;  idx += 1) {
+      for (unsigned idx = 0 ;  idx < ports.size() ;  idx += 1) {
 	    if (ports[idx] == 0) {
 		    /* It is possible to have undeclared ports. These
 		       are ports that are skipped in the declaration,
@@ -79,7 +79,7 @@ unsigned Module::find_port(const char*name) const
 		  return idx;
       }
 
-      return ports.count();
+      return ports.size();
 }
 
 
diff --git a/Module.h b/Module.h
index e05aa244e7..d62da62d63 100644
--- a/Module.h
+++ b/Module.h
@@ -22,8 +22,8 @@
 
 # include  <list>
 # include  <map>
+# include  <vector>
 # include  <utility>
-# include  "svector.h"
 # include  "StringHeap.h"
 # include  "HName.h"
 # include  "named.h"
@@ -59,7 +59,7 @@ class Module : public PScope, public LineInfo {
     public:
       struct port_t {
 	    perm_string name;
-	    svector<PEIdent*> expr;
+	    vector<PEIdent*> expr;
       };
 
     public:
@@ -98,7 +98,7 @@ class Module : public PScope, public LineInfo {
 
 	/* This is an array of port descriptors, which is in turn a
 	   named array of PEident pointers. */
-      svector<port_t*> ports;
+      vector<port_t*> ports;
 
       map<perm_string,PExpr*> attributes;
 
@@ -126,7 +126,7 @@ class Module : public PScope, public LineInfo {
       void add_gate(PGate*gate);
 
       unsigned port_count() const;
-      const svector<PEIdent*>& get_port(unsigned idx) const;
+      const vector<PEIdent*>& get_port(unsigned idx) const;
       unsigned find_port(const char*name) const;
 
       PGate* get_gate(perm_string name);
diff --git a/elab_sig.cc b/elab_sig.cc
index 88466637f1..b239aa1fd8 100644
--- a/elab_sig.cc
+++ b/elab_sig.cc
@@ -150,7 +150,7 @@ bool Module::elaborate_sig(Design*des, NetScope*scope) const
 
 	// Scan all the ports of the module, and make sure that each
 	// is connected to wires that have port declarations.
-      for (unsigned idx = 0 ;  idx < ports.count() ;  idx += 1) {
+      for (unsigned idx = 0 ;  idx < ports.size() ;  idx += 1) {
 	    Module::port_t*pp = ports[idx];
 	    if (pp == 0)
 		  continue;
@@ -159,7 +159,7 @@ bool Module::elaborate_sig(Design*des, NetScope*scope) const
 	      // expression are all identifiers that should reference
 	      // wires within the scope.
 	    map<perm_string,PWire*>::const_iterator wt;
-	    for (unsigned cc = 0 ;  cc < pp->expr.count() ;  cc += 1) {
+	    for (unsigned cc = 0 ;  cc < pp->expr.size() ;  cc += 1) {
 		  pform_name_t port_path (pp->expr[cc]->path());
 		    // A concatenated wire of a port really should not
 		    // have any hierarchy.
@@ -365,7 +365,7 @@ bool PGModule::elaborate_sig_mod_(Design*des, NetScope*scope,
 
       NetScope::scope_vec_t instance = scope->instance_arrays[get_name()];
 
-      for (unsigned idx = 0 ;  idx < instance.count() ;  idx += 1) {
+      for (unsigned idx = 0 ;  idx < instance.size() ;  idx += 1) {
 	      // I know a priori that the elaborate_scope created the scope
 	      // already, so just look it up as a child of the current scope.
 	    NetScope*my_scope = instance[idx];
diff --git a/elaborate.cc b/elaborate.cc
index 51e018861c..6a36b50657 100644
--- a/elaborate.cc
+++ b/elaborate.cc
@@ -938,7 +938,7 @@ NetNet*PGModule::resize_net_to_port_(Design*des, NetScope*scope,
       return tmp;
 }
 
-static bool need_bufz_for_input_port(const svector<NetNet*>&prts)
+static bool need_bufz_for_input_port(const vector<NetNet*>&prts)
 {
       if (prts[0]->port_type() != NetNet::PINPUT)
 	    return false;
@@ -1051,7 +1051,7 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
 	// later.
 
       NetScope::scope_vec_t&instance = scope->instance_arrays[get_name()];
-      for (unsigned inst = 0 ;  inst < instance.count() ;  inst += 1) {
+      for (unsigned inst = 0 ;  inst < instance.size() ;  inst += 1) {
 	    rmod->elaborate(des, instance[inst]);
       }
 
@@ -1079,8 +1079,8 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
 		    // input. If so, consider printing a port binding
 		    // warning.
 		  if (warn_portbinding) {
-			svector<PEIdent*> mport = rmod->get_port(idx);
-			if (mport.count() == 0)
+			vector<PEIdent*> mport = rmod->get_port(idx);
+			if (mport.size() == 0)
 			      continue;
 
 			perm_string pname = peek_tail_name(mport[0]->path());
@@ -1105,26 +1105,26 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
 	      // Inside the module, the port is zero or more signals
 	      // that were already elaborated. List all those signals
 	      // and the NetNet equivalents, for all the instances.
-	    svector<PEIdent*> mport = rmod->get_port(idx);
-	    svector<NetNet*>prts (mport.count() * instance.count());
+	    vector<PEIdent*> mport = rmod->get_port(idx);
+	    vector<NetNet*>  prts (mport.size() * instance.size());
 
 	    if (debug_elaborate) {
 		  cerr << get_fileline() << ": debug: " << get_name()
-		       << ": Port " << idx << " has " << prts.count()
+		       << ": Port " << idx << " has " << prts.size()
 		       << " sub-ports." << endl;
 	    }
 
 	      // Count the internal vector bits of the port.
 	    unsigned prts_vector_width = 0;
 
-	    for (unsigned inst = 0 ;  inst < instance.count() ;  inst += 1) {
+	    for (unsigned inst = 0 ;  inst < instance.size() ;  inst += 1) {
 		    // Scan the instances from MSB to LSB. The port
 		    // will be assembled in that order as well.
-		  NetScope*inst_scope = instance[instance.count()-inst-1];
+		  NetScope*inst_scope = instance[instance.size()-inst-1];
 
 		    // Scan the module sub-ports for this instance...
-		  for (unsigned ldx = 0 ;  ldx < mport.count() ;  ldx += 1) {
-			unsigned lbase = inst * mport.count();
+		  for (unsigned ldx = 0 ;  ldx < mport.size() ;  ldx += 1) {
+			unsigned lbase = inst * mport.size();
 			PEIdent*pport = mport[ldx];
 			assert(pport);
 			prts[lbase + ldx]
@@ -1147,10 +1147,10 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
 	      // We know by design that each instance has the same
 	      // width port. Therefore, the prts_pin_count must be an
 	      // even multiple of the instance count.
-	    assert(prts_vector_width % instance.count() == 0);
+	    assert(prts_vector_width % instance.size() == 0);
 
 	    unsigned desired_vector_width = prts_vector_width;
-	    if (instance.count() != 1)
+	    if (instance.size() != 1)
 		  desired_vector_width = 0;
 
 	      // Elaborate the expression that connects to the
@@ -1158,7 +1158,7 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
 	      // that connects to the port.
 
 	    NetNet*sig;
-	    if ((prts.count() == 0)
+	    if ((prts.size() == 0)
 		|| (prts[0]->port_type() == NetNet::PINPUT)) {
 
 		    /* Input to module. elaborate the expression to
@@ -1263,7 +1263,7 @@ v		       NOTE that this also handles the case that the
 	    assert(sig);
 
 #ifndef NDEBUG
-	    if ((prts.count() >= 1)
+	    if ((prts.size() >= 1)
 		&& (prts[0]->port_type() != NetNet::PINPUT)) {
 		  assert(sig->type() != NetNet::REG);
 	    }
@@ -1271,13 +1271,13 @@ v		       NOTE that this also handles the case that the
 
 	      /* If we are working with an instance array, then the
 		 signal width must match the port width exactly. */
-	    if ((instance.count() != 1)
+	    if ((instance.size() != 1)
 		&& (sig->vector_width() != prts_vector_width)
-		&& (sig->vector_width() != prts_vector_width/instance.count())) {
+		&& (sig->vector_width() != prts_vector_width/instance.size())) {
 		  cerr << pins[idx]->get_fileline() << ": error: "
 		       << "Port expression width " << sig->vector_width()
 		       << " does not match expected width "<< prts_vector_width
-		       << " or " << (prts_vector_width/instance.count())
+		       << " or " << (prts_vector_width/instance.size())
 		       << "." << endl;
 		  des->errors += 1;
 		  continue;
@@ -1292,7 +1292,7 @@ v		       NOTE that this also handles the case that the
 	      // Check that the parts have matching pin counts. If
 	      // not, they are different widths. Note that idx is 0
 	      // based, but users count parameter positions from 1.
-	    if ((instance.count() == 1)
+	    if ((instance.size() == 1)
 		&& (prts_vector_width != sig->vector_width())) {
 		  const char *tmp3 = rmod->ports[idx]->name.str();
 		  bool as_signed = false;
@@ -1363,7 +1363,7 @@ v		       NOTE that this also handles the case that the
 	      // Connect this many of the port pins. If the expression
 	      // is too small, then reduce the number of connects.
 	    unsigned ccount = prts_vector_width;
-	    if (instance.count() == 1 && sig->vector_width() < ccount)
+	    if (instance.size() == 1 && sig->vector_width() < ccount)
 		  ccount = sig->vector_width();
 
 	      // The spin_modulus is the width of the signal (not the
@@ -1371,7 +1371,7 @@ v		       NOTE that this also handles the case that the
 	      // signals wide enough for a single instance to be
 	      // connected to all the instances.
 	    unsigned spin_modulus = prts_vector_width;
-	    if (instance.count() != 1)
+	    if (instance.size() != 1)
 		  spin_modulus = sig->vector_width();
 
 	      // Now scan the concatenation that makes up the port,
@@ -1383,7 +1383,7 @@ v		       NOTE that this also handles the case that the
 	    NetConcat*ctmp;
 	    unsigned spin = 0;
 
-	    if (prts.count() == 1) {
+	    if (prts.size() == 1) {
 
 		    // The simplest case, there are no
 		    // parts/concatenations on the inside of the
@@ -1391,33 +1391,32 @@ v		       NOTE that this also handles the case that the
 		    // connected directly.
 		  connect(prts[0]->pin(0), sig->pin(0));
 
-	    } else if (sig->vector_width()==prts_vector_width/instance.count()
-		       && prts.count()/instance.count() == 1) {
+	    } else if (sig->vector_width()==prts_vector_width/instance.size()
+		       && prts.size()/instance.size() == 1) {
 
 		  if (debug_elaborate){
 			cerr << get_fileline() << ": debug: " << get_name()
 			     << ": Replicating " << prts_vector_width
 			     << " bits across all "
-			     << prts_vector_width/instance.count()
+			     << prts_vector_width/instance.size()
 			     << " sub-ports." << endl;
 		  }
 
 		    // The signal width is exactly the width of a
 		    // single instance of the port. In this case,
 		    // connect the sig to all the ports identically.
-		  for (unsigned ldx = 0 ;  ldx < prts.count() ;  ldx += 1)
+		  for (unsigned ldx = 0 ;  ldx < prts.size() ;  ldx += 1)
 			connect(prts[ldx]->pin(0), sig->pin(0));
 
 	    } else switch (prts[0]->port_type()) {
 		case NetNet::POUTPUT:
 		  ctmp = new NetConcat(scope, scope->local_symbol(),
-				       prts_vector_width,
-				       prts.count());
+				       prts_vector_width, prts.size());
 		  des->add_node(ctmp);
 		  connect(ctmp->pin(0), sig->pin(0));
-		  for (unsigned ldx = 0 ;  ldx < prts.count() ;  ldx += 1) {
+		  for (unsigned ldx = 0 ;  ldx < prts.size() ;  ldx += 1) {
 			connect(ctmp->pin(ldx+1),
-				prts[prts.count()-ldx-1]->pin(0));
+				prts[prts.size()-ldx-1]->pin(0));
 		  }
 		  break;
 
@@ -1426,13 +1425,13 @@ v		       NOTE that this also handles the case that the
 			cerr << get_fileline() << ": debug: " << get_name()
 			     << ": Dividing " << prts_vector_width
 			     << " bits across all "
-			     << prts_vector_width/instance.count()
+			     << prts_vector_width/instance.size()
 			     << " input sub-ports of port "
 			     << idx << "." << endl;
 		  }
 
-		  for (unsigned ldx = 0 ;  ldx < prts.count() ;  ldx += 1) {
-			NetNet*sp = prts[prts.count()-ldx-1];
+		  for (unsigned ldx = 0 ;  ldx < prts.size() ;  ldx += 1) {
+			NetNet*sp = prts[prts.size()-ldx-1];
 			NetPartSelect*ptmp = new NetPartSelect(sig, spin,
 							   sp->vector_width(),
 							   NetPartSelect::VP);
diff --git a/netlist.h b/netlist.h
index 022953ff49..43ea14d0c7 100644
--- a/netlist.h
+++ b/netlist.h
@@ -829,7 +829,7 @@ class NetScope : public Attrib {
 
 	/* Module instance arrays are collected here for access during
 	   the multiple elaboration passes. */
-      typedef svector<NetScope*> scope_vec_t;
+      typedef vector<NetScope*> scope_vec_t;
       map<perm_string, scope_vec_t>instance_arrays;
 
 	/* Loop generate uses this as scratch space during
diff --git a/parse.y b/parse.y
index f5b1a1988e..6ea228b8cd 100644
--- a/parse.y
+++ b/parse.y
@@ -108,6 +108,12 @@ static svector<PExpr*>* copy_range(svector<PExpr*>* orig)
       return copy;
 }
 
+template <class T> void append(vector<T>&out, const vector<T>&in)
+{
+      for (size_t idx = 0 ; idx < in.size() ; idx += 1)
+	    out.push_back(in[idx]);
+}
+
 /*
  * This is a shorthand for making a PECallFunction that takes a single
  * arg. This is used by some of the code that detects built-ins.
@@ -158,7 +164,7 @@ static PECallFunction*make_call_function(perm_string tn, PExpr*arg1, PExpr*arg2)
 
       Module::port_t *mport;
       LexicalScope::range_t* value_range;
-      svector<Module::port_t*>*mports;
+      vector<Module::port_t*>*mports;
 
       named_pexpr_t*named_pexpr;
       svector<named_pexpr_t*>*named_pexprs;
@@ -1658,30 +1664,28 @@ list_of_identifiers
 
 list_of_ports
 	: port_opt
-		{ svector<Module::port_t*>*tmp
-			  = new svector<Module::port_t*>(1);
+		{ vector<Module::port_t*>*tmp
+			  = new vector<Module::port_t*>(1);
 		  (*tmp)[0] = $1;
 		  $$ = tmp;
 		}
 	| list_of_ports ',' port_opt
-		{ svector<Module::port_t*>*tmp
-			= new svector<Module::port_t*>(*$1, $3);
-		  delete $1;
+	        { vector<Module::port_t*>*tmp = $1;
+		  tmp->push_back($3);
 		  $$ = tmp;
 		}
 	;
 
 list_of_port_declarations
 	: port_declaration
-		{ svector<Module::port_t*>*tmp
-			  = new svector<Module::port_t*>(1);
+		{ vector<Module::port_t*>*tmp
+			  = new vector<Module::port_t*>(1);
 		  (*tmp)[0] = $1;
 		  $$ = tmp;
 		}
 	| list_of_port_declarations ',' port_declaration
-		{ svector<Module::port_t*>*tmp
-			= new svector<Module::port_t*>(*$1, $3);
-		  delete $1;
+	        { vector<Module::port_t*>*tmp = $1;
+		  tmp->push_back($3);
 		  $$ = tmp;
 		}
 	| list_of_port_declarations ',' IDENTIFIER
@@ -1689,8 +1693,8 @@ list_of_port_declarations
 		  perm_string name = lex_strings.make($3);
 		  ptmp = pform_module_port_reference(name, @3.text,
 						     @3.first_line);
-		  svector<Module::port_t*>*tmp
-			= new svector<Module::port_t*>(*$1, ptmp);
+		  vector<Module::port_t*>*tmp = $1;
+		  tmp->push_back(ptmp);
 
 		    /* Get the port declaration details, the port type
 		       and what not, from context data stored by the
@@ -1700,7 +1704,6 @@ list_of_port_declarations
 					port_declaration_context.port_net_type,
 					port_declaration_context.sign_flag,
 					port_declaration_context.range, 0);
-		  delete $1;
 		  delete[]$3;
 		  $$ = tmp;
 		}
@@ -2776,8 +2779,7 @@ port_reference
 
 	  Module::port_t*ptmp = new Module::port_t;
 	  ptmp->name = perm_string();
-	  ptmp->expr = svector<PEIdent*>(1);
-	  ptmp->expr[0] = wtmp;
+	  ptmp->expr.push_back(wtmp);
 
 	  delete[]$1;
 	  $$ = ptmp;
@@ -2800,8 +2802,7 @@ port_reference
 
 	  Module::port_t*ptmp = new Module::port_t;
 	  ptmp->name = perm_string();
-	  ptmp->expr = svector<PEIdent*>(1);
-	  ptmp->expr[0] = tmp;
+	  ptmp->expr.push_back(tmp);
 	  delete[]$1;
 	  $$ = ptmp;
 	}
@@ -2812,8 +2813,7 @@ port_reference
 	  PEIdent*wtmp = new PEIdent(lex_strings.make($1));
 	  FILE_NAME(wtmp, @1);
 	  ptmp->name = lex_strings.make($1);
-	  ptmp->expr = svector<PEIdent*>(1);
-	  ptmp->expr[0] = wtmp;
+	  ptmp->expr.push_back(wtmp);
 	  delete[]$1;
 	  $$ = ptmp;
 	}
@@ -2825,7 +2825,7 @@ port_reference_list
 		{ $$ = $1; }
 	| port_reference_list ',' port_reference
 		{ Module::port_t*tmp = $1;
-		  tmp->expr = svector<PEIdent*>(tmp->expr, $3->expr);
+		  append(tmp->expr, $3->expr);
 		  delete $3;
 		  $$ = tmp;
 		}
diff --git a/pform.cc b/pform.cc
index 0eb67d899a..814e8aa8de 100644
--- a/pform.cc
+++ b/pform.cc
@@ -384,20 +384,19 @@ Module::port_t* pform_module_port_reference(perm_string name,
       PEIdent*tmp = new PEIdent(name);
       FILE_NAME(tmp, file, lineno);
       ptmp->name = name;
-      ptmp->expr = svector<PEIdent*>(1);
-      ptmp->expr[0] = tmp;
+      ptmp->expr.push_back(tmp);
 
       return ptmp;
 }
 
-void pform_module_set_ports(svector<Module::port_t*>*ports)
+void pform_module_set_ports(vector<Module::port_t*>*ports)
 {
       assert(pform_cur_module);
 
 	/* The parser parses ``module foo()'' as having one
 	   unconnected port, but it is really a module with no
 	   ports. Fix it up here. */
-      if (ports && (ports->count() == 1) && ((*ports)[0] == 0)) {
+      if (ports && (ports->size() == 1) && ((*ports)[0] == 0)) {
 	    delete ports;
 	    ports = 0;
       }
diff --git a/pform.h b/pform.h
index 03f2065fdf..a11a73f1fd 100644
--- a/pform.h
+++ b/pform.h
@@ -143,7 +143,7 @@ extern PWire* pform_get_wire_in_scope(perm_string name);
  */
 extern void pform_startmodule(const char*, const char*file, unsigned lineno,
 			      svector<named_pexpr_t*>*attr);
-extern void pform_module_set_ports(svector<Module::port_t*>*);
+extern void pform_module_set_ports(vector<Module::port_t*>*);
 
 /* This function is used to support the port definition in a
    port_definition_list. In this case, we have everything needed to
diff --git a/pform_dump.cc b/pform_dump.cc
index 438c5c88a6..87159644a4 100644
--- a/pform_dump.cc
+++ b/pform_dump.cc
@@ -1143,7 +1143,7 @@ void Module::dump(ostream&out) const
 
       out << "module " << mod_name() << ";" << endl;
 
-      for (unsigned idx = 0 ;  idx < ports.count() ;  idx += 1) {
+      for (unsigned idx = 0 ;  idx < ports.size() ;  idx += 1) {
 	    port_t*cur = ports[idx];
 
 	    if (cur == 0) {
@@ -1152,7 +1152,7 @@ void Module::dump(ostream&out) const
 	    }
 
 	    out << "    ." << cur->name << "(" << *cur->expr[0];
-	    for (unsigned wdx = 1 ;  wdx < cur->expr.count() ;  wdx += 1) {
+	    for (unsigned wdx = 1 ;  wdx < cur->expr.size() ;  wdx += 1) {
 		  out << ", " << *cur->expr[wdx];
 	    }