RV32IMC_verilog

Computer Architecture: Project 1: RV32IMC Single Cycle and Pipelined Processor

Authors:

• Kirolous Fouty (900212444)
• Basmala Abdelkader (900212406)
• Farida Amin (900192074)

Program Guide (How to use)

0- Download the repo as zip file.

1- Uncompress in a known folder, and open the .xpr project file using Vivado.

2- Run simulation, or program it on an FPGA after configuring a constraints file to map the input and output, matching your FPGA.

Project Status

• Instructions supported and passed initial testing: LW, SW, ADD, SUB, AND, OR, BEQ, LUI, AUIPC, JAL, JALR, BNE, BLT, BGE, BLTU, BGEU, ADDI, SLLI, SLTI, SLTIU, XORI, SRLI, SRAI, ORI, ANDI, SLL, SLT, SLTU, XOR, SRL, and SRA.
• Instructions to be supported: LB, LH, LBU, LHU, SB, SH, ECALL, compressed instructions, and multiplication instructions.

Challenges Faced

• Lack of sources explaining what signals and selection lines are produced and used

Issues and Problems

• None faced in the currently supported instructions.