changes

----------
aparasha    Date: Wed May 13 16:39:23 EDT 2009  CSN: CSN-platform-acp-2
                  Wed May 13 20:39:23 UTC 2009


Directory modules
 bluespec/                 Locally Added               0 

Directory modules/bluespec
 fpgaenv/                  Locally Added               0 

Directory modules/bluespec/fpgaenv
 physical-platform/        Locally Added               0 

Directory modules/bluespec/fpgaenv/physical-platform
 acp-m2c/                  Locally Added               0 

Directory modules/bluespec/fpgaenv/physical-platform/acp-m2c
 xilinx.download           Locally Added               0 
 xilinx.ut                 Locally Added               0 
 acp-m2c.cpp               Locally Added               0 
 acp-m2c.h                 Locally Added               0 
 xilinx.xst                Locally Added               0 
 acp-m2c.awb               Locally Added               0 
 acp-m2c.bsv               Locally Added               0 
 acp-m2c.ucf               Locally Added               0 

Directory modules/bluespec/fpgaenv/physical-platform
 physical-devices/         Locally Added               0 

Directory modules/bluespec/fpgaenv/physical-platform/physical-devices
 arches-mpi/               Locally Added               0 

Directory modules/bluespec/fpgaenv/physical-platform/physical-devices/arches-mpi
 inst_m2_dualcompute_infrastructure_wrapper.ngc Locally Added               0 
 fsl_mpedata_to_vacc_wrapper.ngc Locally Added               0 
 fsl_vacc_to_mpedata_wrapper.ngc Locally Added               0 
 mb_mba_wrapper.ngc        Locally Added               0 
 m2c_f1.ucf                Locally Added               0 
 arches-mpi-vhdl-import.bsv Locally Added               0 
 tmd_mpe_vacc_wrapper.ngc  Locally Added               0 
 plb_gpio_monitor_mba_wrapper.ngc Locally Added               0 
 fsl_l1_to_mpe_wrapper.ngc Locally Added               0 
 fsl_mpe_to_l1_wrapper.ngc Locally Added               0 
 arches-mpi-device.awb     Locally Added               0 
 plb_mdm_mba_wrapper.ngc   Locally Added               0 
 inst_m2_fsl_if_l1_wrapper.ngc Locally Added               0 
 lmb_bram_mba_wrapper.ngc  Locally Added               0 
 inst_util_clk0_pll_wrapper.ngc Locally Added               0 
 inst_util_clk100_pll_wrapper.ngc Locally Added               0 
 dlmb_mba_wrapper.ngc      Locally Added               0 
 system.vhd                Locally Added               0 
 dlmb_cntlr_mba_wrapper.ngc Locally Added               0 
 inst_proc_sys_reset_wrapper.ngc Locally Added               0 
 arches-mpi-device.cpp     Locally Added               0 
 ilmb_mba_wrapper.ngc      Locally Added               0 
 ilmb_cntlr_mba_wrapper.ngc Locally Added               0 
 inst_util_srl_reset_clk0_wrapper.ngc Locally Added               0 
 plb_bus_mba_wrapper.ngc   Locally Added               0 
 arches-mpi-device.h       Locally Added               0 
 fsl_vacc_to_mpecmd_wrapper.ngc Locally Added               0 
 fsl_mpecmd_to_vacc_wrapper.ngc Locally Added               0 
 arches-mpi-device.bsv     Locally Added               0 

Directory modules/bluespec
 common/                   Locally Added               0 

- Added a new ACP M2 Compute Physical Platform
- Added a new Arches MPI Physical Device (does not work yet)

----------
aparasha    Date: Thu May 14 15:39:37 EDT 2009  CSN: CSN-platform-acp-3
                  Thu May 14 19:39:37 UTC 2009


Directory modules/bluespec/fpgaenv
 virtual-platform/         Locally Added               0 

Directory modules/bluespec/fpgaenv/virtual-platform
 channelio/                Locally Added               0 

Directory modules/bluespec/fpgaenv/virtual-platform/channelio
 physical-channel/         Locally Added               0 

Directory modules/bluespec/fpgaenv/virtual-platform/channelio/physical-channel
 arches-mpi/               Locally Added               0 

Directory modules/bluespec/fpgaenv/virtual-platform/channelio/physical-channel/arches-mpi
 arches-mpi-channel.cpp    Locally Added               0 
 arches-mpi-channel.h      Locally Added               0 
 arches-mpi-channel.awb    Locally Added               0 
 arches-mpi-channel.bsv    Locally Added               0 

Directory modules/bluespec/fpgaenv/physical-platform/physical-devices/arches-mpi
 m2_fsl_rx_phy.v           Locally Added               0 
 inst_m2_dualcompute_infrastructure_wrapper.v Locally Added               0 
 m2_fsl_tx_phy.v           Locally Added               0 
 param_delay.v             Locally Added               0 
 metasync.v                Locally Added               0 
 cmp_signed_10bit.vhd      Locally Added               0 
 arches-mpi-device.awb     Locally Modified            2 
 inst_m2_fsl_if_l1_wrapper.v Locally Added               0 
 fht_top.v                 Locally Added               0 
 m2_fsl_rx_top.v           Locally Added               0 
 inst_m2_dualcompute_infrastructure_wrapper.ngc Locally Removed             2 
 m2_fsl_tx_top.v           Locally Added               0 
 m2_dualcompute_infrastructure.v Locally Added               0 
 m2_fsl_tx_ctrl.v          Locally Added               0 
 gen_sync_bram.vhd         Locally Added               0 
 m2_fsl_rx_data.v          Locally Added               0 
 fht_module.v              Locally Added               0 
 m2_fsl_tx_data.v          Locally Added               0 
 fsl_v20.vhd               Locally Added               0 
 m2_fsl_rx_pn.v            Locally Added               0 
 walsh_tx.v                Locally Added               0 
 inst_m2_fsl_if_l1_wrapper.ngc Locally Removed             2 
 sync_fifo.vhd             Locally Added               0 
 async_fifo.vhd            Locally Added               0 
 m2_fsl_rx_clklock.v       Locally Added               0 
 param_delay_1bit.v        Locally Added               0 
 async_fifo_bram.vhd       Locally Added               0 
 system.vhd                Locally Modified            2 
 m2_fsl_if.v               Locally Added               0 
 gen_sync_dpram.vhd        Locally Added               0 
 gen_srlfifo.vhd           Locally Added               0 
 srl_sel_256bit.vhd        Locally Added               0 

Directory config/pm
 hasim/                    Locally Added               0 

Directory config/pm/hasim
 submodels/                Locally Added               0 

Directory config/pm/hasim/submodels
 fpgaenv/                  Locally Added               0 

Directory config/pm/hasim/submodels/fpgaenv
 hasim-fpgaenv-acp-m2c.apm Locally Added               0 

Directory config/pm
 bluespec/                 Locally Added               0 

Directory config/pm/bluespec
 demos/                    Locally Added               0 

Directory config/pm/bluespec/demos
 rrrtest/                  Locally Added               0 

Directory config/pm/bluespec/demos/rrrtest
 rrrtest_hybrid_acp.apm    Locally Added               0 

- Updated Arches MPI device. It now successfully generates a bitfile
  for the ACP M2 Compute module. Since the software side of the stack
  is not ready yet, there's no evidence that this works.

  To generate the bitfile correctly, some SConstruct flags need to be
  added. These will be added in a hasim commit coming shortly.

  The entire fpgaenv directory is slightly mislocated in this
  repository. I will move it as part of the next checkin.

- Added an fpgaenv/virtual platform for the ACP module

- Added a Physical Channel for the ACP module. Implementation for this
  is not yet complete.

----------
aparasha    Date: Thu May 14 15:49:53 EDT 2009  CSN: CSN-platform-acp-4
                  Thu May 14 19:49:53 UTC 2009


Directory modules/bluespec
 fpgaenv/                  Locally Removed             2 

Directory modules/bluespec/common
 fpgaenv/                  Locally Added               0 

Directory modules/bluespec/common/fpgaenv
 virtual-platform/         Locally Added               0 

Directory modules/bluespec/common/fpgaenv/virtual-platform
 channelio/                Locally Added               0 

Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio
 physical-channel/         Locally Added               0 

Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel
 arches-mpi/               Locally Added               0 

Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/arches-mpi
 arches-mpi-channel.cpp    Locally Added               0 
 arches-mpi-channel.h      Locally Added               0 
 arches-mpi-channel.awb    Locally Added               0 
 arches-mpi-channel.bsv    Locally Added               0 

Directory modules/bluespec/common/fpgaenv
 physical-platform/        Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform
 acp-m2c/                  Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c
 xilinx.download           Locally Added               0 
 xilinx.ut                 Locally Added               0 
 acp-m2c.cpp               Locally Added               0 
 acp-m2c.h                 Locally Added               0 
 xilinx.xst                Locally Added               0 
 acp-m2c.awb               Locally Added               0 
 acp-m2c.bsv               Locally Added               0 
 acp-m2c.ucf               Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform
 physical-devices/         Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices
 arches-mpi/               Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/arches-mpi
 m2_fsl_rx_phy.v           Locally Added               0 
 inst_m2_dualcompute_infrastructure_wrapper.v Locally Added               0 
 m2_fsl_tx_phy.v           Locally Added               0 
 param_delay.v             Locally Added               0 
 mb_mba_wrapper.ngc        Locally Added               0 
 fsl_mpedata_to_vacc_wrapper.ngc Locally Added               0 
 fsl_vacc_to_mpedata_wrapper.ngc Locally Added               0 
 m2c_f1.ucf                Locally Added               0 
 plb_gpio_monitor_mba_wrapper.ngc Locally Added               0 
 metasync.v                Locally Added               0 
 cmp_signed_10bit.vhd      Locally Added               0 
 fsl_l1_to_mpe_wrapper.ngc Locally Added               0 
 fsl_mpe_to_l1_wrapper.ngc Locally Added               0 
 arches-mpi-device.awb     Locally Added               0 
 inst_m2_fsl_if_l1_wrapper.v Locally Added               0 
 plb_mdm_mba_wrapper.ngc   Locally Added               0 
 inst_util_clk100_pll_wrapper.ngc Locally Added               0 
 dlmb_mba_wrapper.ngc      Locally Added               0 
 fht_top.v                 Locally Added               0 
 ilmb_cntlr_mba_wrapper.ngc Locally Added               0 
 inst_util_srl_reset_clk0_wrapper.ngc Locally Added               0 
 arches-mpi-device.h       Locally Added               0 
 arches-mpi-device.bsv     Locally Added               0 
 m2_fsl_rx_top.v           Locally Added               0 
 m2_fsl_tx_top.v           Locally Added               0 
 arches-mpi-vhdl-import.bsv Locally Added               0 
 m2_dualcompute_infrastructure.v Locally Added               0 
 m2_fsl_tx_ctrl.v          Locally Added               0 
 gen_sync_bram.vhd         Locally Added               0 
 tmd_mpe_vacc_wrapper.ngc  Locally Added               0 
 m2_fsl_rx_data.v          Locally Added               0 
 fht_module.v              Locally Added               0 
 m2_fsl_tx_data.v          Locally Added               0 
 fsl_v20.vhd               Locally Added               0 
 m2_fsl_rx_pn.v            Locally Added               0 
 walsh_tx.v                Locally Added               0 
 sync_fifo.vhd             Locally Added               0 
 lmb_bram_mba_wrapper.ngc  Locally Added               0 
 inst_util_clk0_pll_wrapper.ngc Locally Added               0 
 async_fifo.vhd            Locally Added               0 
 param_delay_1bit.v        Locally Added               0 
 m2_fsl_rx_clklock.v       Locally Added               0 
 async_fifo_bram.vhd       Locally Added               0 
 system.vhd                Locally Added               0 
 m2_fsl_if.v               Locally Added               0 
 dlmb_cntlr_mba_wrapper.ngc Locally Added               0 
 arches-mpi-device.cpp     Locally Added               0 
 inst_proc_sys_reset_wrapper.ngc Locally Added               0 
 ilmb_mba_wrapper.ngc      Locally Added               0 
 gen_sync_dpram.vhd        Locally Added               0 
 plb_bus_mba_wrapper.ngc   Locally Added               0 
 fsl_mpecmd_to_vacc_wrapper.ngc Locally Added               0 
 fsl_vacc_to_mpecmd_wrapper.ngc Locally Added               0 
 gen_srlfifo.vhd           Locally Added               0 
 srl_sel_256bit.vhd        Locally Added               0 

Moved fpgaenv to its correct location.

----------
aparasha    Date: Thu May 14 15:52:48 EDT 2009  CSN: CSN-platform-acp-5
                  Thu May 14 19:52:48 UTC 2009


Directory config/pm/hasim/submodels/fpgaenv
 hasim-fpgaenv-acp-m2c.apm Locally Modified            3 

Updated config to point to new AWB module locations in fpgaenv

----------
aparasha    Date: Thu May 14 16:58:02 EDT 2009  CSN: CSN-platform-acp-6
                  Thu May 14 20:58:02 UTC 2009


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/arches-mpi
 arches-mpi-device.awb     Locally Modified            4 
 srl_sel_256bit.ngc        Locally Added               0 
 cmp_signed_10bit.ngc      Locally Added               0 

Missed some files in the last checkin.

----------
aparasha    Date: Thu May 21 18:22:24 EDT 2009  CSN: CSN-platform-acp-7
                  Thu May 21 22:22:24 UTC 2009


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/arches-mpi
 mpi_headers.h             Locally Added               0 
 mpi.c                     Locally Added               0 
 mpi_constants.h           Locally Added               0 
 mpi.h                     Locally Added               0 
 arches-mpi-device.h       Locally Modified            5 
 GeneratedConstants.h      Locally Added               0 
 arches-mpi-device.cpp     Locally Modified            5 
 arches-mpi-device.awb     Locally Modified            6 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c
 acp-m2c.awb               Locally Modified            5 

Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/arches-mpi
 arches-mpi-channel.cpp    Locally Modified            5 
 arches-mpi-channel.bsv    Locally Modified            5 

Directory .
 libmpi_x86_threadmpe_linux.a Locally Added               0 
 libacp.a                  Locally Added               0 

Completed implementation of Arches MPI Device and a new Physical Channel
based on the device. An RRRTest model can now be built for the ACP
Platform, but a slight hacking of the SCons script is needed to link
the two libraries libacp.a and libmpi_xxx.a correctly into the host
software executable.

The platform currently does not have a clock divider/multiplier, so only
simple models that can run at 133MHz will work.

----------
aparasha    Date: Fri May 22 16:21:46 EDT 2009  CSN: CSN-platform-acp-8
                  Fri May 22 20:21:46 UTC 2009


Directory config/pm/hasim
 demos/                    Locally Added               0 

Directory config/pm/hasim/demos
 test/                     Locally Added               0 

Directory config/pm/hasim/demos/test
 mem_test/                 Locally Added               0 

Directory config/pm/hasim/demos/test/mem_test
 mem_test_hybrid_nopvt_acp.apm Locally Added               0 

Directory config/pm/hasim/submodels/fpgaenv
 hasim-fpgaenv-acp-m2c.apm Locally Modified            7 

Directory config/pm/bluespec/demos/rrrtest
 rrrtest_hybrid_acp.apm    Locally Modified            7 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c
 xilinx.download           Locally Modified            7 
 acp-m2c.awb               Locally Modified            7 
 acp-m2c.bsv               Locally Modified            7 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/arches-mpi
 arches-mpi-device.awb     Locally Modified            7 
 arches-mpi-device.bsv     Locally Modified            7 
 arches-mpi-device.cpp     Locally Modified            7 

- Added support for user-specified clock transformations to the ACP platform.
  This is currently buggy and only works with a 1:1 transformation.

- Added synchronizers to the Arches MPI device.

----------
aparasha    Date: Fri May 22 18:23:13 EDT 2009  CSN: CSN-platform-acp-9
                  Fri May 22 22:23:13 UTC 2009


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/arches-mpi
 arches-mpi-device.awb     Locally Modified            8 
 arches-mpi-device.bsv     Locally Modified            8 
 arches-mpi-vhdl-import.bsv Locally Modified            8 
 system.vhd                Locally Modified            8 

Arches MPI Device now uses a raw 100MHz FPGA clock to derive the model clock
from, instead of using the MPE clock.

Model Clock transformations work now.

The default mult/div ratios have been set to 3:4, thus giving a 75MHz model
clock.

----------
mcadler     Date: Mon May 25 22:49:59 EDT 2009  CSN: CSN-platform-acp-10
                  Tue May 26 02:49:59 UTC 2009


Directory config/pm/hasim/demos/test/mem_test
 mem_test_hybrid_nopvt_acp.apm Locally Modified            9 
 mem_test_hybrid_acp.apm   Locally Added               0 

Directory config/pm/hasim/submodels/fpgaenv
 hasim-fpgaenv-acp-m2c.apm Locally Modified            9 

- Use more BRAM for local memory.
- Update mem_test.

----------
mcadler     Date: Tue May 26 11:46:31 EDT 2009  CSN: CSN-platform-acp-11
                  Tue May 26 15:46:31 UTC 2009


Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/arches-mpi
 arches-mpi-channel.bsv    Locally Modified            9 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/arches-mpi
 arches-mpi-device.bsv     Locally Modified            9 

Fix timing problems that show up even when the timing score is 0:

- Keep FPGA-side channel I/O send command and data messages in sync across the
  clock crossing.
- Hold model reset for multiple cycles.

----------
mcadler     Date: Mon Aug  3 07:49:32 EDT 2009  CSN: CSN-platform-acp-12
                  Mon Aug  3 11:49:32 UTC 2009


Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c
 acp-m2c.awb               Locally Modified           11 

Add MAP_OPTION required by recent SCons script change.

----------
emer        Date: Tue Sep  1 13:50:41 EDT 2009  CSN: CSN-platform-acp-13
                  Tue Sep  1 17:50:41 UTC 2009


Directory config/pm/hasim/submodels/fpgaenv
 hasim-fpgaenv-acp-m2c.apm Locally Modified           12 

Filling in missing modules in acp fpgaenv.

----------
emer        Date: Tue Sep  8 14:18:23 EDT 2009  CSN: CSN-platform-acp-14
                  Tue Sep  8 18:18:23 UTC 2009


Directory config/pm
 platform-acp/             Locally Removed            13 

Directory config/pm/platform-acp
 README                    Locally Removed            13 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c
 acp-m2c.awb               Locally Modified           13 

Moved MAKE_ALL_TARGET from the root modules (model/project) to the
physical_platform module inside fpgaenv. In the various physical
platforms the default is set appropriately, e.g., exe for simulation,
bit for real hardware. In the physical_platform module, MAKE_ALL_TARGET
is declared as a 'global' parameter so it can be overridden in the
model that requires an fpgaenv.

----------
aparasha    Date: Mon Sep 14 10:58:12 EDT 2009  CSN: CSN-platform-acp-15
                  Mon Sep 14 14:58:12 UTC 2009


Directory config/pm/hasim/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech.apm Locally Added               0 

Directory config/pm/bluespec/demos/rrrtest
 rrrtest_hybrid_acp_nallatech.apm Locally Added               0 

Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel
 nallatech-edge/           Locally Added               0 

Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/nallatech-edge
 npc-marshaller.bsv        Locally Added               0 
 nallatech-edge-channel.cpp Locally Added               0 
 nallatech-edge-channel.h  Locally Added               0 
 npc-demarshaller.bsv      Locally Added               0 
 nallatech-edge-channel.awb Locally Added               0 
 nallatech-edge-channel.bsv Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform
 acp-m2c-nallatech/        Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-nallatech
 xilinx.download           Locally Added               0 
 xilinx.ut                 Locally Added               0 
 acp-m2c.cpp               Locally Added               0 
 acp-m2c.h                 Locally Added               0 
 xilinx.xst                Locally Added               0 
 acp-m2c.awb               Locally Added               0 
 acp-m2c.bsv               Locally Added               0 
 acp-m2c.ucf               Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices
 nallatech-edge/           Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 usr_reg_slave_if_io_example.vhd Locally Added               0 
 nallatech-edge-device.h   Locally Added               0 
 FPGA0_lvds_to_lower_module.ucf Locally Added               0 
 nallatech-edge-device.awb Locally Added               0 
 nallatech-edge-device.bsv Locally Added               0 
 nallatech-edge-device.ucf Locally Added               0 
 nallatech-edge-vhdl-import.bsv Locally Added               0 
 fsb_compute_edge_2rx2tx.ngc Locally Added               0 
 nallatech-edge-device.vhd Locally Added               0 
 usr_reg_slave_if_bram_example.vhd Locally Added               0 
 nallatech-edge-device.cpp Locally Added               0 
 FPGA0_system_interface.ucf Locally Added               0 

- Added a new ACP M2C Platform based on Nallatech's API. The current
  implementation only works with designs that can synthesize at 100MHz because
  instantiating DCMs introduces huge clock skews. This is being worked on.

- Added a new physical channel implementation using the Nallatech API.

- Added a new ACP M2C fpgaenv submodel for the Nallatech-based platform.

- Added a new RRRTest demo model config using the new ACP M2C fpgaenv.

----------
aparasha    Date: Tue Sep 22 14:36:17 EDT 2009  CSN: CSN-platform-acp-16
                  Tue Sep 22 18:36:17 UTC 2009


Directory config/pm/bluespec/demos/rrrtest
 rrrtest_hybrid_acp_nallatech.apm Locally Modified           15 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 FPGA0_lvds_to_lower_module.ucf Locally Removed            15 
 nallatech-edge-device.awb Locally Modified           15 
 nallatech-edge-device.bsv Locally Modified           15 
 nallatech-edge-device.ucf Locally Modified           15 
 FPGA0_system_interface.ucf Locally Removed            15 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-nallatech
 acp-m2c.awb               Locally Modified           15 

Updated Nallatech ACP platform to support user-specified clock frequencies.

----------
aparasha    Date: Tue Sep 22 15:14:57 EDT 2009  CSN: CSN-platform-acp-17
                  Tue Sep 22 19:14:57 UTC 2009


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.cpp Locally Modified           15 

Updated device to construct the name of the FPGA bitfile from the APM_NAME
parameter passed down by the SCons script (this was hardcoded earlier).

----------
mcadler     Date: Wed Sep 23 10:05:40 EDT 2009  CSN: CSN-platform-acp-18
                  Wed Sep 23 14:05:40 UTC 2009


Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c
 xilinx.xst                Locally Modified           17 
 acp-m2c.awb               Locally Modified           17 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-nallatech
 xilinx.download           Locally Removed            17 
 xilinx.xst                Locally Modified           17 
 acp-m2c.awb               Locally Modified           17 

- Use Elliott's new FPGA_PART_XILINX instead of FPGA_PART.
- Don't need an FPGA_POSITION for Nallatech firmware since not loading bit
  file with impact.
- Enable -global_opt in map.  Don't know if it works yet.

----------
aparasha    Date: Wed Sep 23 17:59:23 EDT 2009  CSN: CSN-platform-acp-19
                  Wed Sep 23 21:59:23 UTC 2009


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.ucf Locally Modified           18 

Removed a set of TIG constraints in the UCF that were hard-coded to
particular net-names that the Bluespec compiler was generating for
a certain design. These have been replaced with a wildcard net-name
that should apply to all Bluespec-generated names.

----------
mcadler     Date: Thu Sep 24 17:25:05 EDT 2009  CSN: CSN-platform-acp-20
                  Thu Sep 24 21:25:05 UTC 2009


Directory config/pm/hasim/demos/test/mem_test
 mem_test_hybrid_nopvt_acp.apm Locally Modified           19 
 mem_test_hybrid_acp.apm   Locally Modified           19 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.awb Locally Modified           19 
 nallatech-edge-device.bsv Locally Modified           19 
 nallatech-edge-device.cpp Locally Modified           19 

- Nallatech code now finds the bit file to load using the FPGA_BIT_FILE
  environment variable.
- Default PLL output clock is still 75MHz but with "better" parameters,
  using an input divider.
- mem_test for ACP now uses Nallatech.

----------
mcadler     Date: Thu Sep 24 17:32:45 EDT 2009  CSN: CSN-platform-acp-21
                  Thu Sep 24 21:32:45 UTC 2009


Directory config/pm/hasim
 demos/                    Locally Removed            19 

Moved to hasim repository.

----------
mcadler     Date: Thu Sep 24 17:35:19 EDT 2009  CSN: CSN-platform-acp-22
                  Thu Sep 24 21:35:19 UTC 2009


Directory config/pm/bluespec
 demos/                    Locally Removed            20 

Directory config/pm/bluespec/demos
 rrrtest/                  Locally Removed            20 

Directory config/pm/bluespec/demos/rrrtest
 rrrtest_hybrid_acp_nallatech.apm Locally Removed            20 
 rrrtest_hybrid_acp.apm    Locally Removed            20 

Directory config/pm
 bluespec/                 Locally Removed            20 

Moved to hasim repository.

----------
aparasha    Date: Fri Sep 25 14:35:22 EDT 2009  CSN: CSN-platform-acp-23
                  Fri Sep 25 18:35:22 UTC 2009


Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/nallatech-edge
 nallatech-edge-channel.cpp Locally Modified           22 
 nallatech-edge-channel.h  Locally Modified           22 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.h   Locally Modified           22 
 nallatech-edge-device.awb Locally Modified           22 
 nallatech-edge-device.cpp Locally Modified           22 

- Refactored some code between the Nallatech channel and the Nallatech device.
  The channel is no longer aware of the bugs in the Nallatech firmware that
  impose restrictions on message sizes. All bugfix code now lives in the device
  module.

- Abstracted the Nallatech device workspace into distinct input and output
  windows (as visible from the channel layer).

----------
mcadler     Date: Tue Sep 29 15:01:36 EDT 2009  CSN: CSN-platform-acp-24
                  Tue Sep 29 19:01:36 UTC 2009


Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/nallatech-edge
 nallatech-edge-channel.cpp Locally Modified           23 

The test in the PHYSICAL_CHANNEL_CLASS::Read() loop was inverted, causing a
SEGV due to indirection through a NULL pointer in the caller.

----------
mcadler     Date: Thu Oct  1 07:09:27 EDT 2009  CSN: CSN-platform-acp-27
                  Thu Oct  1 11:09:27 UTC 2009


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.awb Locally Modified           24 
 nallatech-edge-device.bsv Locally Modified           24 

PLL generator no longer requires low level timing parameters.  Just pass in
a target frequency.

----------
aparasha    Date: Thu Oct  8 16:50:03 EDT 2009  CSN: CSN-platform-acp-33
                  Thu Oct  8 20:50:03 UTC 2009


Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/nallatech-edge
 nallatech-edge-channel.cpp Locally Modified           32 
 nallatech-edge-channel.awb Locally Modified           32 
 nallatech-edge-channel.bsv Locally Modified           32 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.cpp Locally Modified           32 

- Decreased message transfer window size from 1024 bytes to 128 bytes.
- Reorganized some code between Channel and Device.

----------
mcadler     Date: Fri Oct 23 15:23:11 EDT 2009  CSN: CSN-platform-acp-34
                  Fri Oct 23 19:23:11 UTC 2009


Directory drivers
 nallatech/                Locally Added               0 

Directory drivers/nallatech
 linux/                    Locally Added               0 

Directory drivers/nallatech/linux
 acpdriver.c               Locally Added               0 
 acp.h                     Locally Added               0 
 Makefile                  Locally Added               0 

Directory .
 drivers/                  Locally Added               0 

Add Nallatech ACP driver.

----------
mcadler     Date: Wed Nov  4 20:29:40 EST 2009  CSN: CSN-platform-acp-35
                  Thu Nov  5 01:29:40 UTC 2009


Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c
 xilinx.xst                Locally Modified           34 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-nallatech
 xilinx.xst                Locally Modified           34 

Changes for new parallel Xst builds.

----------
mcadler     Date: Wed Nov 11 14:07:45 EST 2009  CSN: CSN-platform-acp-36
                  Wed Nov 11 19:07:45 UTC 2009


Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-nallatech
 acp-m2c.awb               Locally Modified           35 

Find ACP libraries through the "latest" link, not a version-specific path.

----------
mcadler     Date: Wed Nov 18 11:48:49 EST 2009  CSN: CSN-platform-acp-37
                  Wed Nov 18 16:48:49 UTC 2009


Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/nallatech-edge
 npc-marshaller.bsv        Locally Modified           36 
 nallatech-edge-channel.cpp Locally Modified           36 
 nallatech-edge-channel.h  Locally Modified           36 
 npc-demarshaller.bsv      Locally Modified           36 
 nallatech-edge-channel.awb Locally Modified           36 
 nallatech-edge-channel.bsv Locally Modified           36 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.h   Locally Modified           36 
 nallatech-edge-device.awb Locally Modified           36 
 nallatech-edge-device.ucf Locally Modified           36 
 nallatech-edge-device.cpp Locally Modified           36 

Performance improvements to Nallatech channel I/O:

- FPGA-side: read and write for a single transaction in parallel.  (Still only
  one read or write transaction at a time due to Nallatech limitations.)
  The dummy buffer is now read/written while the real work is done.

- Variable message sizes.  Software attempts to pick an optimal size during
  the run.  This can probably still be tuned more.

- Software controlled spin loop on the HW side waiting for data to arrive
  from the model during HW -> SW data request.  This seems to have surprisingly
  little effect.

- Unlimited HW -> SW message size (at least by Channel I/O).

- SW -> HW message limit raised to 8KB.

- Marshaller and demarshaller can now enq() and deq() in the same cycle.

Performance is about 2.5x - 3x better, so it has gone from unbelievably terrible
to merely unacceptable.  RRR test reports about 9MB/s for one way HW->SW.

With the current tuning a variety of RRR patterns appear to hit near optimal
buffer sizes.

----------
mcadler     Date: Fri Nov 20 19:51:03 EST 2009  CSN: CSN-platform-acp-38
                  Sat Nov 21 00:51:03 UTC 2009


Directory config/pm/hasim/submodels/fpgaenv
 hasim-fpgaenv-acp-m2c.apm Locally Modified           37 
 fpgaenv-acp-m2c-nallatech.apm Locally Modified           37 

Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/nallatech-edge
 nallatech-edge-channel.cpp Locally Modified           37 
 nallatech-edge-channel.awb Locally Modified           37 
 nallatech-edge-channel.bsv Locally Modified           37 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.h   Locally Modified           37 
 nallatech-edge-device.awb Locally Modified           37 
 nallatech-edge-device.cpp Locally Modified           37 

- Use 64 bit UMF chunks instead of 32.

- Drop the wasted UMF chunk that used to signal the start of a new message.
  Now the physical channel detects the "no message" flag as a CHUNK that is 0.
  UMF header chunks are guaranteed non-zero by setting the phyChannelPvt
  flag I added to the UMF header.

- Tweak the automatic buffer sizing code for data flowing from the FPGA to
  the host.  If a message was always exactly the size of the buffer the old
  code never grew the buffer to see whether multiple messages could be
  delivered together.

----------
mcadler     Date: Mon Nov 23 07:35:37 EST 2009  CSN: CSN-platform-acp-39
                  Mon Nov 23 12:35:37 UTC 2009


Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/nallatech-edge
 nallatech-edge-channel.cpp Locally Modified           38 
 nallatech-edge-channel.bsv Locally Modified           38 

- Fix a bug in which the channel can get stuck in an infinite loop when no
  message is pending from the FPGA to the host.

- Guarantee that the reads are completed before the last write on the FPGA side.
  I don't know whether this matters, but it matches the ACP example code and
  we don't know their buffering algorithm.

----------
mcadler     Date: Mon Nov 23 19:34:25 EST 2009  CSN: CSN-platform-acp-40
                  Tue Nov 24 00:34:25 UTC 2009


Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/nallatech-edge
 nallatech-edge-channel.cpp Locally Modified           39 
 nallatech-edge-channel.h  Locally Modified           39 
 nallatech-edge-channel.bsv Locally Modified           39 

Refactor the FPGA-side pipelines:

- Many fewer states and slightly shorter.

- No more specialized read vs. write operations.  A transaction now has a
  host to FPGA and an FPGA to host component, though the software doesn't yet
  take advantage of this.

- More than one host to FPGA message may be stored in the buffer, though software
  doesn't do this, yet.

----------
mcadler     Date: Tue Dec  1 16:54:39 EST 2009  CSN: CSN-platform-acp-41
                  Tue Dec  1 21:54:39 UTC 2009


Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/nallatech-edge
 nallatech-edge-channel.cpp Locally Modified           40 
 nallatech-edge-channel.h  Locally Modified           40 
 nallatech-edge-channel.bsv Locally Modified           40 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.h   Locally Modified           40 
 nallatech-edge-device.cpp Locally Modified           40 

Move all I/O to the FPGA to a tight loop in an I/O thread.  Multiple buffers
are used to permit parallel host-side read/write on one set of buffers while
another set of buffers are being used to read/write data from/to the FPGA.

Performance is pretty good.  For large messages (128 bytes) RRR Test claims
over 400MB/s for one-way messages and over 600MB/s for two-way pipelined
messages.  Two-way non-pipelined messages and smaller messages are significantly
slower due to channel I/O and software layer overhead.  My most recent
check-in to platforms reduces the software overhead.

----------
pellauer    Date: Thu Dec  3 18:36:57 EST 2009  CSN: CSN-platform-acp-42
                  Thu Dec  3 23:36:57 UTC 2009


Directory modules/bluespec/common/fpgaenv/physical-platform
 acp-m2c-with-sram/        Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-with-sram
 xilinx.ut                 Locally Added               0 
 acp-m2c.cpp               Locally Added               0 
 acp-m2c.h                 Locally Added               0 
 xilinx.xst                Locally Added               0 
 acp-m2c.awb               Locally Added               0 
 acp-m2c.bsv               Locally Added               0 
 acp-m2c.ucf               Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices
 ddr-sram/                 Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddrii_top_ctrl_sm.vhd     Locally Added               0 
 ddrii_phy_dly_cal_sm.vhd  Locally Added               0 
 ddr-sram-device.ucf       Locally Added               0 
 ddrii_phy_io.vhd          Locally Added               0 
 m2c_sram.vhd              Locally Added               0 
 ddrii_idelay_ctrl.vhd     Locally Added               0 
 ddrii_top_addr_cmd_interface.vhd Locally Added               0 
 ddr_sram_vhdl_import.bi   Locally Added               0 
 ddrii_sram.vhd            Locally Added               0 
 ddrii_top.vhd             Locally Added               0 
 ddr-sram-device.bi        Locally Added               0 
 ddr-sram-device.bsv       Locally Added               0 
 ddr_sram_vhdl_import.bo   Locally Added               0 
 ddr-sram-vhdl-import.bi   Locally Added               0 
 ddr-sram-device.bo        Locally Added               0 
 ddrii_phy_cq_io.vhd       Locally Added               0 
 ddrii_phy_write.vhd       Locally Added               0 
 ddr-sram-vhdl-import.bsv  Locally Added               0 
 ddrii_phy_dq_io.vhd       Locally Added               0 
 ddrii_phy_ctrl_io.vhd     Locally Added               0 
 ddrii_phy_bw_io.vhd       Locally Added               0 
 m2c_clocking.vhd          Locally Added               0 
 ddrii_infrastructure.vhd  Locally Added               0 
 ddrii_top_user_interface.vhd Locally Added               0 
 ddr-sram-vhdl-import.bo   Locally Added               0 
 ddrii_phy_top.vhd         Locally Added               0 
 ddrii_phy_en.vhd          Locally Added               0 
 ddrii_phy_init_sm.vhd     Locally Added               0 
 ddrii_top_wr_data_interface.vhd Locally Added               0 
 ddr-sram-device.awb       Locally Added               0 


* Extremely preliminary ddr_sram device for ACP. Still needs a Bluespec driver, as well as some understanding of how it wants to be
  clocked.

* ACP w/SRAM alternative physical platform.

Michael P.

----------
pellauer    Date: Fri Dec  4 17:10:55 EST 2009  CSN: CSN-platform-acp-43
                  Fri Dec  4 22:10:55 UTC 2009


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.bsv Locally Modified           41 
 nallatech-edge-vhdl-import.bsv Locally Modified           41 
 nallatech-edge-device.vhd Locally Modified           41 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.ucf       Locally Modified           42 
 ddrii_sram.vhd            Locally Modified           42 
 ddr-sram-device.bsv       Locally Modified           42 
 ddr-sram-vhdl-import.bsv  Locally Modified           42 
 m2c_clocking.vhd          Locally Modified           42 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-with-sram
 acp-m2c.bsv               Locally Modified           42 


* Updates to the ACP SRAM device - now takes its clocking from the nallatech
edge device. 

* Wires look to be all going to the right place in the .v files - remains to see
if the UCF still needs some tweaking.

* We should be able to start doing the BSV driver now.

Michael P.

----------
mcadler     Date: Mon Dec  7 18:42:54 EST 2009  CSN: CSN-platform-acp-44
                  Mon Dec  7 23:42:54 UTC 2009


Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-with-sram
 acp-m2c.awb               Locally Modified           43 
 acp-m2c.bsv               Locally Modified           43 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr_sram_vhdl_import.bi   Locally Removed            43 
 ddr-sram-device.bi        Locally Removed            43 
 ddr-sram-device.bsv       Locally Modified           43 
 ddr_sram_vhdl_import.bo   Locally Removed            43 
 ddr-sram-vhdl-import.bi   Locally Removed            43 
 ddr-sram-vhdl-import.bsv  Locally Modified           43 
 ddr-sram-device.bo        Locally Removed            43 
 ddr-sram-vhdl-import.bo   Locally Removed            43 
 ddr-sram-device.awb       Locally Modified           43 

- Change interface naming to be consistent with other DDR2 controllers so
  this driver can be used by the generic local memory code in platforms.

- Change memory sizes to fit in with with local memory.

- Still no actual driver code.

----------
mcadler     Date: Thu Dec 10 09:45:32 EST 2009  CSN: CSN-platform-acp-45
                  Thu Dec 10 14:45:32 UTC 2009


Directory config/pm/hasim/submodels/fpgaenv
 fpgaenv-acp-m2c-sram-nallatech.apm Locally Added               0 

Add Nallatech firmware configuration with SRAM.

----------
pellauer    Date: Fri Dec 11 15:16:14 EST 2009  CSN: CSN-platform-acp-46
                  Fri Dec 11 20:16:14 UTC 2009


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.ucf       Locally Modified           45 
 ddrii_sram.vhd            Locally Modified           45 
 ddr-sram-device.bsv       Locally Modified           45 
 ddr-sram-vhdl-import.bsv  Locally Modified           45 
 ddr-sram-device.awb       Locally Modified           45 


* ACP SRAM: now expose two banks of RAM.

* Update the UCF to compile with the correct signal names.

* Pass the output reset from the SRAM to keep the clock-crossing FIFOs happy.

* Put some extremely preliminary synchronization logic in the BSV driver as an
  attempt to keep XST from optimizing things away.

* Currently the build fails in NGDBUILD when some critical signals in the EDGE
  device FIFO are optimized away. The next step will be for Michael A. to make
  an actual driver so that these signals are not optimized away.

* If the EDGE device FIFO line in the UCF is commented out then the build fails
  in MAP when critical RAM-related signals are undriven. Again, hopefully a real
  driver would fix this.

Michael P.


----------
aparasha    Date: Fri Mar 12 17:00:25 EST 2010  CSN: CSN-platform-acp-48
                  Fri Mar 12 22:00:25 UTC 2010


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddrii_top_ctrl_sm.vhd     Locally Modified           47 
 ddrii_phy_dly_cal_sm.vhd  Locally Modified           47 
 ddr-sram-device.ucf       Locally Modified           47 
 ddrii_phy_io.vhd          Locally Modified           47 
 m2c_sram.vhd              Locally Removed            47 
 ddrii_idelay_ctrl.vhd     Locally Modified           47 
 ddrii_top_addr_cmd_interface.vhd Locally Modified           47 
 ddrii_top.vhd             Locally Modified           47 
 ddrii_sram.vhd            Locally Removed            47 
 ddr2_sram.vhd             Locally Added               0 
 ddr-sram-device.bsv       Locally Modified           47 
 ddr-sram-vhdl-import.bsv  Locally Modified           47 
 ddrii_phy_cq_io.vhd       Locally Modified           47 
 ddrii_phy_write.vhd       Locally Modified           47 
 ddrii_phy_ctrl_io.vhd     Locally Modified           47 
 ddrii_phy_dq_io.vhd       Locally Modified           47 
 ddrii_phy_bw_io.vhd       Locally Modified           47 
 m2c_clocking.vhd          Locally Removed            47 
 ddrii_infrastructure.vhd  Locally Modified           47 
 ddrii_top_user_interface.vhd Locally Modified           47 
 ddrii_phy_top.vhd         Locally Modified           47 
 ddrii_phy_init_sm.vhd     Locally Modified           47 
 ddrii_phy_en.vhd          Locally Modified           47 
 ddr-sram-device.awb       Locally Modified           47 
 ddrii_top_wr_data_interface.vhd Locally Modified           47 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.ucf Locally Modified           47 
 nallatech-edge-vhdl-import.bsv Locally Modified           47 
 nallatech-edge-device.vhd Locally Modified           47 

- updated DDR2 SRAM controller for ACP. It now synthesizes into a valid bitfile but
  the SRAM functionality does not work.
- updated UCF and some VHDL code in the Edge Device code to reflect
  re-wiring due to SRAM integration


----------
mcadler     Date: Fri Mar 19 07:13:21 EDT 2010  CSN: CSN-platform-acp-49
                  Fri Mar 19 11:13:21 UTC 2010


Directory config/pm/hasim/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.bsv Locally Modified           48 

- More robust reset logic.  The old version was allowing the model to start
  before the FPGA settled.

- Add a version of the platform with no central cache.

----------
aparasha    Date: Tue Mar 23 15:01:27 EDT 2010  CSN: CSN-platform-acp-50
                  Tue Mar 23 19:01:27 UTC 2010


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.bsv       Locally Modified           49 
 ddr-sram-vhdl-import.bsv  Locally Modified           49 

Updating with Michael Pellauer's debugger updates.

----------
pellauer    Date: Thu Mar 25 15:36:07 EDT 2010  CSN: CSN-platform-acp-51
                  Thu Mar 25 19:36:07 UTC 2010


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device-fake.awb  Locally Added               0 
 ddr2_sram.vhd             Locally Modified           50 
 ddr-sram-device.bsv       Locally Modified           50 
 ddr-sram-vhdl-import.bsv  Locally Modified           50 
 ddr-sram-fake.bsv         Locally Added               0 


Adding "Fake" SRAM -- just a Bluespec RegFile with the correct clock domains.
We should make sure this works before moving to the real SRAM.

Michael P.


----------
aparasha    Date: Thu Mar 25 20:45:02 EDT 2010  CSN: CSN-platform-acp-52
                  Fri Mar 26 00:45:02 UTC 2010


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.ucf       Locally Modified           51 
 ddr-sram-device.bsv       Locally Modified           51 
 ddr-sram-vhdl-import.bsv  Locally Modified           51 

DDR SRAM now works with one SRAM controller. It should be straightforward to extend
this to two controllers. Please keep in mind that some of the logic in the top-level
ddr2_sram.vhd file is common for both controllers (e.g. IDELAY instantiation).

----------
mcadler     Date: Fri Mar 26 20:29:58 EDT 2010  CSN: CSN-platform-acp-53
                  Sat Mar 27 00:29:58 UTC 2010


Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-with-sram
 acp-m2c.bsv               Locally Modified           52 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.ucf       Locally Modified           52 
 ddr-sram-device.bsv       Locally Modified           52 
 ddr-sram-vhdl-import.bsv  Locally Modified           52 

Two SRAM banks now work.  The wrapper instantiates a single bank and the SRAM
device allocates two of them.

The code is now cleaned up in the wrapper.  The device still needs work.

----------
mcadler     Date: Sun Mar 28 20:49:10 EDT 2010  CSN: CSN-platform-acp-54
                  Mon Mar 29 00:49:10 UTC 2010


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.ucf       Locally Modified           53 
 ddr-sram-device.bsv       Locally Modified           53 
 ddr-sram-vhdl-import.bsv  Locally Modified           53 
 ddr-sram-device.awb       Locally Modified           53 

- Expose cal_done from the controller as ddr_device_RDY() in Bluespec.  Wait
  for ddr_device_RDY to be set before making any requests of the RAM.
  Ok, I confess:  I actually read the Xilinx documentation.  Next I'll probably
  stop at gas stations to ask directions.

- Add initialization of RAM to a known pattern (standard Bluespec 0xaaaa....)
  This way programs can't appear to work because they are using some stale
  values.

- Make debugging logic conditionally compiled (default is off).

- Confirmed that 8 is a good choice for the read buffer size.  (Optimal is
  about 6).

- Move all typedefs that are computed from the Bluespec VHDL wrapper to the
  ddr-sram-device.bsv.  Only device-specific values are set in the wrapper.

- All loads and stores are coded with the intent of supporting arbitrary burst
  sizes.  All are debugged on the current hardware that only has a burst of
  one data message.

----------
mcadler     Date: Fri Apr  2 16:30:34 EDT 2010  CSN: CSN-platform-acp-55
                  Fri Apr  2 20:30:34 UTC 2010


Directory config/pm/hasim/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Modified           54 
 fpgaenv-acp-m2c-nallatech.apm Locally Modified           54 
 fpgaenv-acp-m2c-sram-nallatech.apm Locally Removed            54 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.ucf       Locally Modified           54 
 ddr-sram-device.bsv       Locally Modified           54 

- Add DDR to the default Nallatech configuration.
- Correct scratchpad configuration.
- Clean up DDR controller.

----------
mcadler     Date: Tue Apr  6 14:40:06 EDT 2010  CSN: CSN-platform-acp-56
                  Tue Apr  6 18:40:06 UTC 2010


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.bsv       Locally Modified           55 

Add a path during initialization that reads from the SRAM and writes it back,
guaranteeing that the read sync FIFO can't be optimized away.

----------
mcadler     Date: Wed Apr  7 07:58:23 EDT 2010  CSN: CSN-platform-acp-57
                  Wed Apr  7 11:58:23 UTC 2010


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.ucf       Locally Modified           56 

Refine the SRAM TIG rules.

----------
pellauer    Date: Fri Apr  9 10:49:59 EDT 2010  CSN: CSN-platform-acp-58
                  Fri Apr  9 14:49:59 UTC 2010


Directory config/pm/hasim/submodels/fpgaenv
 hasim-fpgaenv-acp-m2c.apm Locally Modified           57 
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Modified           57 
 fpgaenv-acp-m2c-nallatech.apm Locally Modified           57 


* Updating ACP environments with rrr_common. Alfred and Elliott seem to have 
  overlooked these yesterday, possibly because they live in a separate 
  repository.


Michael P.

----------
mcadler     Date: Thu Apr 22 16:18:26 EDT 2010  CSN: CSN-platform-acp-59
                  Thu Apr 22 20:18:26 UTC 2010


Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/nallatech-edge
 nallatech-edge-channel.cpp Locally Modified           58 
 nallatech-edge-channel.h  Locally Modified           58 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.h   Locally Modified           58 

Add support in the I/O ring buffers for more than two read and two write buffers.
Increasing to 3 in each direction improves performance by about 3.5% for
a heavily pipelined workload.  Not much, but it didn't take very long to write
and the code is more robust.

----------
mcadler     Date: Mon May  3 14:28:03 EDT 2010  CSN: CSN-platform-acp-60
                  Mon May  3 18:28:03 UTC 2010


Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/nallatech-edge
 nallatech-edge-channel.cpp Locally Modified           59 
 nallatech-edge-channel.h  Locally Modified           59 

Add a pseudo-DMA path for use by a single client that bypasses the normal
channel I/O and RRR stacks.  The path may read and write messages directly
to the memory shared with the FPGA.

When scratchpads use this path simulation can run in about 2/3rds the time.

----------
pellauer    Date: Mon May 10 18:33:39 EDT 2010  CSN: CSN-platform-acp-61
                  Mon May 10 22:33:39 UTC 2010


Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c
 acp-m2c.awb               Locally Modified           60 
 acp-m2c.sdc               Locally Added               0 
 acp-m2c.sdf               Locally Added               0 


* Adding synplify ACP support for Elliott.

Michael

----------
pellauer    Date: Mon May 10 18:55:44 EDT 2010  CSN: CSN-platform-acp-62
                  Mon May 10 22:55:44 UTC 2010


Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-nallatech
 acp-m2c.awb               Locally Modified           60 
 acp-m2c.sdc               Locally Added               0 
 acp-m2c.sdf               Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-with-sram
 acp-m2c.awb               Locally Modified           60 
 acp-m2c.sdc               Locally Added               0 
 acp-m2c.sdf               Locally Added               0 


* More Synplify support for Elliott.

Michael P.

----------
kfleming    Date: Wed May 19 11:00:37 EDT 2010  CSN: CSN-platform-acp-63
                  Wed May 19 15:00:37 UTC 2010


Directory config/pm/hasim/submodels/fpgaenv
 hasim-fpgaenv-acp-m2c.apm Locally Modified           62
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Modified           62
 fpgaenv-acp-m2c-nallatech.apm Locally Modified           62

Modifying existing fpgaenvs to have associate build pipelines.

----------
pellauer    Date: Wed May 19 13:38:23 EDT 2010  CSN: CSN-platform-acp-63
                  Wed May 19 17:38:23 UTC 2010


Directory config/pm/hasim/submodels/fpgaenv
 hasim-fpgaenv-acp-m2c.apm Locally Modified           62 
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Modified           62 
 fpgaenv-acp-m2c-nallatech.apm Locally Modified           62 

Directory admin
 mytags                    Locally Modified           62 

Directory admin/packages
 platform-acp              Locally Modified           62 

Directory .
 changes                   Locally Modified           62 


Patching ACP FPGAENV for Elliott.

Michael

----------
aparasha    Date: Wed May 26 17:05:12 EDT 2010  CSN: CSN-platform-acp-64
                  Wed May 26 21:05:12 UTC 2010


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices
 nallatech-edge-v2/        Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge-v2
 nallatech-edge-device.h   Locally Added               0 
 nallatech-edge-device.bsv Locally Added               0 
 non_system_edge_component.vhd Locally Added               0 
 nallatech-edge-vhdl-import.bsv Locally Added               0 
 comp_0_base_edge_2rx2tx.ngc Locally Added               0 
 usr_reg_slave_if_io_example.vhd Locally Added               0 
 edge_comp_util_pkg.vhd    Locally Added               0 
 qdr2_ddr2_clocks.vhd      Locally Added               0 
 nallatech-edge-device.awb Locally Added               0 
 edge_comp_defs_pkg.vhd    Locally Added               0 
 nallatech-edge-device.ucf Locally Added               0 
 reset_synchroniser.vhd    Locally Added               0 
 system_edge_component.vhd Locally Added               0 
 nallatech-edge-device.vhd Locally Added               0 
 usr_reg_slave_if_bram_example.vhd Locally Added               0 
 nallatech-edge-device.cpp Locally Added               0 

Checkpoint commit of current debugging state of the new Nallatech firmware.
Doesn't work yet.

----------
mcadler     Date: Fri May 28 08:35:14 EDT 2010  CSN: CSN-platform-acp-65
                  Fri May 28 12:35:14 UTC 2010


Directory config/pm/hasim/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-v2.apm Locally Added               0 
 fpgaenv-acp-m2c-nallatech-no-cache-v2.apm Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-nallatech
 acp-m2c.awb               Locally Modified           64 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-with-sram
 acp-m2c.awb               Locally Modified           64 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge-v2
 nallatech-edge-device.vhd Locally Modified           64 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.ucf       Locally Modified           64 

- V2 for Nallatech works!  We don't understand why it wasn't working for
  Angshuman.
- Add temporary V2 fpgaenv configurations.  These will go away once MIT's machine
  has the new firmware.
- Fix the model clock, putting it back on the 200MHz source.
- Add more TIGs for SRAM sync-FIFOs.

----------
mcadler     Date: Fri May 28 16:30:00 EDT 2010  CSN: CSN-platform-acp-66
                  Fri May 28 20:30:00 UTC 2010


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.ucf       Locally Modified           65 

Tweak another TIG.

----------
mcadler     Date: Wed Jun  2 09:23:53 EDT 2010  CSN: CSN-platform-acp-67
                  Wed Jun  2 13:23:53 UTC 2010


Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/nallatech-edge
 npc-marshaller.bsv        Locally Modified           66 
 nallatech-edge-channel.cpp Locally Modified           66 
 nallatech-edge-channel.h  Locally Modified           66 
 npc-demarshaller.bsv      Locally Modified           66 
 nallatech-edge-channel.awb Locally Modified           66 
 nallatech-edge-channel.bsv Locally Modified           66 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge-v2
 nallatech-edge-device.h   Locally Modified           66 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.h   Locally Modified           66 

Channel integrity testing showed that data errors were in the host -> FPGA
direction.  I have yet to see an FPGA -> host error.

Added optional check bits to the host -> FPGA data stream.  ACP raw messages
are 256 bits wide.  We break those down into 64 bit words.  For now, one
word per 256 bit chunk is reserved for a checksum.  Even on I/O intensive
code the penalty is about a 10% run-time increase since our throughput appears
to be driven by the latency of preparing and initiating I/O transactions on
the CPU.  We could experiment with reducing the UMF chunk size to 32 bits,
thus wasting 1/8th of the buffer instead of 1/4, but that would cut our
on-FPGA UMF throughput by 50%.

Changes:
  - Simplify the marshalling code, forcing the assumption that UMF chunks
    tile evenly into ACP chunks.
  - Put the data-integrity checker directly in the marshaller.  The recipient
    polls the marshaller to find out whether the data stream is accurate.
  - On error the FPGA drops everything following an incorrect message word
    and requests retransmission.
  - The host retransmits the entire block.
  - The FPGA drops the portion already received and continues at the first
    new word.

There are definitely some message patterns that trigger higher probability of
failure than others.

The code was tested by forcing known-bad calibration values -- so bad that
the bit file barely loads correctly.  Runs with over 10K retransmitted blocks
were seen, with no data errors visible outside the physical channel.

Checking is controlled by CHANNEL_H2F_FIX_ERRORS (on by default).

----------
aparasha    Date: Thu Jun  3 18:33:53 EDT 2010  CSN: CSN-platform-acp-68
                  Thu Jun  3 22:33:53 UTC 2010


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge-v2
 nallatech-edge-vhdl-import.bsv Locally Modified           67 
 nallatech-edge-device.vhd Locally Modified           67 

Added Bluespec wrapper around Nallatech's register interface. Use with caution!
Read the comments in the Bluespec import file and/or Nallatech's official
documentation on the interface. The interface itself has not been tested yet,
but the channel functionality has been tested to work correctly with this
update.

----------
mcadler     Date: Mon Jun  7 14:12:42 EDT 2010  CSN: CSN-platform-acp-69
                  Mon Jun  7 18:12:42 UTC 2010


Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/nallatech-edge
 nallatech-edge-channel.cpp Locally Modified           68 
 nallatech-edge-channel.h  Locally Modified           68 
 nallatech-edge-channel.bsv Locally Modified           68 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge-v2
 nallatech-edge-device.h   Locally Modified           68 
 nallatech-edge-device.bsv Locally Modified           68 
 nallatech-edge-vhdl-import.bsv Locally Modified           68 
 nallatech-edge-device.awb Locally Modified           68 
 nallatech-edge-device.ucf Locally Modified           68 
 nallatech-edge-device.vhd Locally Modified           68 
 nallatech-edge-device.cpp Locally Modified           68 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.h   Locally Modified           68 
 nallatech-edge-device.bsv Locally Modified           68 
 nallatech-edge-vhdl-import.bsv Locally Modified           68 

This version fixes the deadlocks I was seeing in ACP I/O with error correction
enabled.  The problem:  I don't know why.  I know the problem is in software
since fixed software works with a multiple versions of FPGA logic.
Adding seemingly gratuitous code makes the deadlock disappear.  I tried
memory barriers around the DoAALTransaction() calls, fearing the optimizer
was hoisting references to the I/O buffers.  No joy.  I don't see any uses
of uninitialized variables.  I'll keep looking.

Improvements with this version:
  - Tested channel interface up to 125 MHz.  Added TIGs to sync FIFOs to
    support this.
  - Added user register debug interface to the V2 physical channel to
    extract some details of the FPGA-side state machine.  (The V1 channel
    just has compatibility hooks but doesn't support actual register reads.)
  - Removed the example user register port 0 connection to BRAM and port 1
    connection to LEDs since we no longer need the examples.

----------
mcadler     Date: Fri Jun 11 01:03:10 EDT 2010  CSN: CSN-platform-acp-70
                  Fri Jun 11 05:03:10 UTC 2010


Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/nallatech-edge
 nallatech-edge-channel.cpp Locally Modified           69 
 nallatech-edge-channel.h  Locally Modified           69 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge-v2
 nallatech-edge-device.bsv Locally Modified           69 
 nallatech-edge-device.awb Locally Modified           69 
 nallatech-edge-device.cpp Locally Modified           69 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.awb Locally Modified           69 

I/O corruption appears to happen only with 8KB buffers.  Reducing the
maximum buffer size to 4KB works and, strangely, has 10% better performance
on the workload I was measuring.

----------
mcadler     Date: Sat Jun 12 17:18:44 EDT 2010  CSN: CSN-platform-acp-71
                  Sat Jun 12 21:18:44 UTC 2010


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge-v2
 nallatech-edge-device.cpp Locally Modified           70 

Small chance of data corruption appears to remain with 4KB packets.  Adding
a very short delay on packets 2KB or greater appears to work well with
essentially no performance hit.  Simulations have been running for a full
day now with no corruption.

----------
kfleming    Date: Mon Jul  5 18:15:57 EDT 2010  CSN: CSN-platform-acp-72
                  Mon Jul  5 22:15:57 UTC 2010


Directory config/pm/hasim/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-jtag-no-cache.apm Locally Added               0 



Preliminary check in of jtag physical channel

----------
mcadler     Date: Wed Jul  7 18:56:59 EDT 2010  CSN: CSN-platform-acp-73
                  Wed Jul  7 22:56:59 UTC 2010


Directory config/pm/hasim/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-v2.apm Locally Removed            72 
 fpgaenv-acp-m2c-nallatech-no-cache-v2.apm Locally Removed            72 
 fpgaenv-acp-m2c-nallatech-local-scratchpad.apm Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices
 nallatech-edge-v2/        Locally Removed            72 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge-v2
 nallatech-edge-device.h   Locally Removed            72 
 nallatech-edge-device.bsv Locally Removed            72 
 non_system_edge_component.vhd Locally Removed            72 
 nallatech-edge-vhdl-import.bsv Locally Removed            72 
 comp_0_base_edge_2rx2tx.ngc Locally Removed            72 
 edge_comp_util_pkg.vhd    Locally Removed            72 
 usr_reg_slave_if_io_example.vhd Locally Removed            72 
 qdr2_ddr2_clocks.vhd      Locally Removed            72 
 nallatech-edge-device.awb Locally Removed            72 
 edge_comp_defs_pkg.vhd    Locally Removed            72 
 nallatech-edge-device.ucf Locally Removed            72 
 reset_synchroniser.vhd    Locally Removed            72 
 nallatech-edge-device.vhd Locally Removed            72 
 system_edge_component.vhd Locally Removed            72 
 usr_reg_slave_if_bram_example.vhd Locally Removed            72 
 nallatech-edge-device.cpp Locally Removed            72 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.bsv       Locally Modified           72 
 ddrii_top_wr_data_interface.vhd Locally Modified           72 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.h   Locally Modified           72 
 nallatech-edge-device.bsv Locally Modified           72 
 non_system_edge_component.vhd Locally Added               - 
 fsb_compute_edge_2rx2tx.ngc Locally Removed            72 
 nallatech-edge-vhdl-import.bsv Locally Modified           72 
 comp_0_base_edge_2rx2tx.ngc Locally Added               - 
 edge_comp_util_pkg.vhd    Locally Added               - 
 qdr2_ddr2_clocks.vhd      Locally Added               - 
 nallatech-edge-device.awb Locally Modified           72 
 edge_comp_defs_pkg.vhd    Locally Added               - 
 nallatech-edge-device.ucf Locally Modified           72 
 reset_synchroniser.vhd    Locally Added               - 
 system_edge_component.vhd Locally Added               - 
 nallatech-edge-device.vhd Locally Modified           72 
 nallatech-edge-device.cpp Locally Modified           72 

- DDR mask bits were broken:
  - Low and high edge positions were swapped in the VHDL
  - Masks cover 9 bit groups (ECC bits appear to be embedded next to each group
    of 8 bits).  Changed the bit mapping so that masks appear to control bytes.

- Replace old driver with Nallatech v2.0.1.

----------
kfleming    Date: Sat Jul 10 17:57:07 EDT 2010  CSN: CSN-platform-acp-74
                  Sat Jul 10 21:57:07 UTC 2010


Directory config/pm/hasim/submodels/fpgaenv
 hasim-fpgaenv-acp-m2c.apm Locally Modified           73 
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Modified           73 
 fpgaenv-acp-m2c-nallatech-jtag-no-cache.apm Locally Modified           73 
 fpgaenv-acp-m2c-nallatech.apm Locally Modified           73 
 fpgaenv-acp-m2c-nallatech-local-scratchpad.apm Locally Modified           73 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.awb Locally Modified           73 


Removed clocking parameters from nallatech-edge-device.  ACP apms now
match the physical platforms for other boards in that clocking
parameters live in the clock device.  This is important since MCD user
code will now be instantiating clocking devices.

----------
kfleming    Date: Fri Jul 16 11:17:02 EDT 2010  CSN: CSN-platform-acp-75
                  Fri Jul 16 15:17:02 UTC 2010


Directory config/pm/hasim/submodels/fpgaenv
 hasim-fpgaenv-acp-m2c.apm Locally Modified           74 
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Modified           74 
 fpgaenv-acp-m2c-nallatech-jtag-no-cache.apm Locally Modified           74 
 fpgaenv-acp-m2c-nallatech.apm Locally Modified           74 
 fpgaenv-acp-m2c-nallatech-local-scratchpad.apm Locally Modified           74 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.bsv       Locally Modified           74 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.bsv Locally Modified           74 


Updated apm to have mcd build tool.  Additionally, fixed major perf
bug in nallatech edge device and sram controller.  The SyncFIFOs in
these designs were too small.  As a result, cycles were needlessly
being lost.  In the case of the SRAM, the performance penalty was as
high as 133% (2.5ns -> 1ns latency).  RRRTest had more modest 10%
gains.  There's actually more perf to be had here by elimating the
sync fifos inthe edge device entirely, but this will require a larger
code rewrite since it involves changing how the model clock gets generated.

----------
kfleming    Date: Sat Jul 17 19:03:05 EDT 2010  CSN: CSN-platform-acp-76
                  Sat Jul 17 23:03:05 UTC 2010


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 inter_intra_mod_mst_edge_0rx4tx.ngc Locally Added               0 
 nallatech-edge-device.bsv Locally Modified           75 
 inter_intra_mod_mst_edge_2rx2tx.ngc Locally Added               0 
 nallatech-edge-0rx0tx-device.bsv Locally Added               0 
 comp_0_base_edge_4rx0tx.ngc Locally Added               0 
 nallatech-edge-2rx2tx-device.bsv Locally Added               0 
 nallatech-intra-device.bsv Locally Added               0 
 exp_0_inter_sys_edge_2rx2tx.ngc Locally Added               0 
 sys_edge_0rx0tx.ngc       Locally Added               0 
 nallatech-intra-vhdl-import.bsv Locally Added               0 
 nallatech-edge-device.vhd Locally Modified           75 
 nallatech-intra-device.vhd Locally Added               0 
 inter_intra_mod_slv_edge_4rx0tx.ngc Locally Added               0 
 inter_intra_mod_slv_edge_2rx2tx.ngc Locally Added               0 
 nallatech-edge-vhdl-import.bsv Locally Modified           75 
 exp_0_base_edge_4rx2tx.ngc Locally Added               0 
 comp_1_base_edge_0rx4tx.ngc Locally Added               0 
 nallatech-intra-2rx2tx-device-fpga0.bsv Locally Added               0 
 nallatech-intra-2rx2tx-device-fpga1.bsv Locally Added               0 
 nallatech-edge-device.awb Locally Modified           75 
 nallatech-edge-device-fpga1.ucf Locally Added               0 
 nallatech-intra-2rx2tx-device.bsv Locally Added               0 
 nallatech-intra-device-fpga0.awb Locally Added               0 
 nallatech-edge-device.ucf Locally Modified           75 
 nallatech-intra-device-fpga1.awb Locally Added               0 
 nallatech-edge-device-null.awb Locally Added               0 
 nallatech-intra-device-fpga0.ucf Locally Added               0 
 nallatech-intra-device-fpga1.ucf Locally Added               0 


The check in is a waypoint along the line to having a multiple FPGA
build.  Here, I have added the nallatech provided communications
primitives and adjusted the existing edge device to support the
interface required for these devices.  I also refactored the edge
device to share as much code as possible between the real edge device
(FPGA0) and the null edge device (FPGA1).  I also added Bluespec
wrappers for the intra ACP communications primitives.  


The next step will be to add a physical platform for FPGA1 and a new
platform with the communication stub for FPGA0.

----------
kfleming    Date: Wed Jul 21 15:56:49 EDT 2010  CSN: CSN-platform-acp-77
                  Wed Jul 21 19:56:49 UTC 2010


Directory config/pm/hasim/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech.apm Locally Modified           76 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.ucf       Locally Modified           76 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.ucf Locally Modified           76 


Modified ucf to support both synplify and xst.

----------
kfleming    Date: Sun Jul 25 14:32:43 EDT 2010  CSN: CSN-platform-acp-78
                  Sun Jul 25 18:32:43 UTC 2010


Directory config/pm/hasim/submodels/fpgaenv
 hasim-fpgaenv-acp-m2c.apm Locally Modified           77 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Added               0 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm Locally Added               0 
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Modified           77 
 fpgaenv-acp-m2c-nallatech-jtag-no-cache.apm Locally Modified           77 
 fpgaenv-acp-m2c-nallatech.apm Locally Modified           77 
 fpgaenv-acp-m2c-nallatech-local-scratchpad.apm Locally Modified           77 

Directory config/pm
 bluespec/                 Locally Added               0 

Directory config/pm/bluespec
 demos/                    Locally Added               0 

Directory config/pm/bluespec/demos
 debugger/                 Locally Added               0 

Directory config/pm/bluespec/demos/debugger
 intra_channel_debugger_nallatech_acp_fpga0.apm Locally Added               0 
 intra_channel_debugger_nallatech_acp_fpga1.apm Locally Added               0 
 intra_channel_debugger_nallatech_acp_jtag.apm Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c
 acp-m2c.awb               Locally Modified           77 

Directory modules/bluespec/common/fpgaenv/physical-platform
 debuggers/                Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/debuggers
 intra-fpga/               Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/debuggers/intra-fpga
 common/                   Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/debuggers/intra-fpga/common
 platform-debugger-common.awb Locally Added               0 
 platform-debugger-common.bsv Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/debuggers/intra-fpga
 fpga0/                    Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/debuggers/intra-fpga/fpga0
 platform-debugger.bsv     Locally Added               0 
 platform-debugger.dic     Locally Added               0 
 platform-debugger.txt     Locally Added               0 
 platform-debugger.cpp     Locally Added               0 
 platform-debugger.rrr     Locally Added               0 
 platform-debugger.h       Locally Added               0 
 platform-debugger.awb     Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/debuggers/intra-fpga
 fpga1/                    Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/debuggers/intra-fpga/fpga1
 platform-debugger.bsv     Locally Added               0 
 platform-debugger.dic     Locally Added               0 
 platform-debugger.txt     Locally Added               0 
 platform-debugger.cpp     Locally Added               0 
 platform-debugger.rrr     Locally Added               0 
 platform-debugger.h       Locally Added               0 
 platform-debugger.awb     Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-nallatech
 acp-m2c.awb               Locally Modified           77 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-with-sram
 acp-m2c.awb               Locally Modified           77 
 acp-m2c.bsv               Locally Modified           77 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.ucf       Locally Modified           77 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.bsv Locally Modified           77 
 nallatech-intra-device.bsv Locally Modified           77 
 nallatech-edge-device-intra-debugger.awb Locally Added               0 
 nallatech-intra-vhdl-import.bsv Locally Modified           77 
 nallatech-edge-device-fpga1.cpp Locally Added               0 
 nallatech-edge-device.vhd Locally Modified           77 
 nallatech-edge-device.cpp Locally Modified           77 
 nallatech-edge-device-null.vhd Locally Added               0 
 nallatech-edge-device-null.cpp Locally Added               0 
 nallatech-intra-device.vhd Locally Modified           77 
 nallatech-edge-vhdl-import.bsv Locally Modified           77 
 nallatech-edge-device-debugger.cpp Locally Added               0 
 nallatech-intra-2rx2tx-device-fpga0.bsv Locally Modified           77 
 nallatech-intra-2rx2tx-device-fpga1.bsv Locally Modified           77 
 nallatech-edge-device-fpga1.ucf Locally Modified           77 
 nallatech-edge-device.awb Locally Modified           77 
 nallatech-intra-2rx2tx-device.bsv Locally Removed            77 
 nallatech-intra-device-fpga0.awb Locally Modified           77 
 nallatech-edge-device.ucf Locally Modified           77 
 nallatech-intra-device-fpga1.awb Locally Modified           77 
 nallatech-edge-device-null.awb Locally Modified           77 
 nallatech-intra-device-fpga0.ucf Locally Modified           77 
 nallatech-intra-device-fpga1.ucf Locally Modified           77 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-nallatech-jtag
 acp-m2c.awb               Locally Modified           77 
 acp-m2c.bsv               Locally Modified           77 


The main addition in this large check-in is a functional test for the
intra-fpga lvds channel.  I also managed to get control of the
on-board leds on the ACP module.  This required setting a marginally
undocumented register.  I also attempted to get the JTAG operational,
but I was uncessful on the ACP.


----------
mcadler     Date: Fri Jul 30 19:45:22 EDT 2010  CSN: CSN-platform-acp-79
                  Fri Jul 30 23:45:22 UTC 2010


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.ucf Locally Modified           78 

Revert to previous specification of 100MHz clock.  New version was causing
failures, even when the result had a timing score of 0.

----------
kfleming    Date: Tue Aug 17 17:01:46 EDT 2010  CSN: CSN-platform-acp-80
                  Tue Aug 17 21:01:46 UTC 2010


Directory config/pm/hasim/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Modified           79 
 hasim-fpgaenv-acp-m2c.apm Locally Modified           79 
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Modified           79 
 fpgaenv-acp-m2c-nallatech-jtag-no-cache.apm Locally Modified           79 
 fpgaenv-acp-m2c-nallatech.apm Locally Modified           79 
 fpgaenv-acp-m2c-nallatech-local-scratchpad.apm Locally Modified           79 

Directory config/pm/bluespec/demos/debugger
 intra_channel_debugger_nallatech_acp_fpga0.apm Locally Modified           79 
 intra_channel_debugger_nallatech_acp_fpga1.apm Locally Modified           79 
 intra_channel_debugger_nallatech_acp_jtag.apm Locally Modified           79 


Fixing apms.

----------
mcadler     Date: Thu Sep  2 17:30:50 EDT 2010  CSN: CSN-platform-acp-81
                  Thu Sep  2 21:30:50 UTC 2010


Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/nallatech-edge
 nallatech-edge-channel.cpp Locally Modified           80 

Uninitialized value caused unpredictable failures in pseudo-DMA load responses.

----------
jsemer      Date: Thu Nov 11 12:02:54 EST 2010  CSN: CSN-platforms-acp-82
                  Thu Nov 11 17:02:54 UTC 2010


Directory admin/packages
 platform-acp              Locally Removed            81 
 platforms-acp             Locally Added               - 

Changed name to platforms-acp.

----------
jsemer      Date: Fri Nov 12 10:26:37 EST 2010  CSN: CSN-platforms-acp-83
                  Fri Nov 12 15:26:37 UTC 2010


Directory config/pm
 bluespec/                 Locally Removed            82 

Directory config/pm/bluespec
 demos/                    Locally Removed            82 

Directory config/pm/bluespec/demos
 debugger/                 Locally Removed            82 

Directory config/pm/bluespec/demos/debugger
 intra_channel_debugger_nallatech_acp_fpga0.apm Locally Removed            82 
 intra_channel_debugger_nallatech_acp_fpga1.apm Locally Removed            82 
 intra_channel_debugger_nallatech_acp_jtag.apm Locally Removed            82 

Directory config/pm
 platforms/                Locally Added               0 

Directory config/pm/platforms/debuggers
 debugger/                 Locally Removed            82 

Directory config/pm/platforms/debuggers/debugger
 intra_channel_debugger_nallatech_acp_fpga0.apm Locally Removed            82 
 intra_channel_debugger_nallatech_acp_fpga1.apm Locally Removed            82 
 intra_channel_debugger_nallatech_acp_jtag.apm Locally Removed            82 

Moved location of acp platform debuggers.

----------
pellauer    Date: Wed Jan 12 16:46:29 EST 2011  CSN: CSN-platforms-acp-84
                  Wed Jan 12 21:46:29 UTC 2011


Directory config/pm/hasim/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Modified           83 
 hasim-fpgaenv-acp-m2c.apm Locally Modified           83 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm Locally Modified           83 
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Modified           83 
 fpgaenv-acp-m2c-nallatech-jtag-no-cache.apm Locally Modified           83 
 fpgaenv-acp-m2c-nallatech.apm Locally Modified           83 
 fpgaenv-acp-m2c-nallatech-local-scratchpad.apm Locally Modified           83 

Directory config/pm/platforms/debuggers/acp
 intra_channel_debugger_nallatech_acp_fpga0.apm Locally Modified           83 
 intra_channel_debugger_nallatech_acp_fpga1.apm Locally Modified           83 
 intra_channel_debugger_nallatech_acp_jtag.apm Locally Modified           83 


* Updating .apm submodels with new file locations, also moving to version 2.2.

Michael P.

----------
pellauer    Date: Tue Jan 18 14:51:41 EST 2011  CSN: CSN-platforms-acp-85
                  Tue Jan 18 19:51:41 UTC 2011


Directory config/pm/hasim/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Modified           84 
 hasim-fpgaenv-acp-m2c.apm Locally Modified           84 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm Locally Modified           84 
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Modified           84 
 fpgaenv-acp-m2c-nallatech-jtag-no-cache.apm Locally Modified           84 
 fpgaenv-acp-m2c-nallatech.apm Locally Modified           84 
 fpgaenv-acp-m2c-nallatech-local-scratchpad.apm Locally Modified           84 

Directory config/pm/platforms/debuggers/acp
 intra_channel_debugger_nallatech_acp_fpga0.apm Locally Modified           84 
 intra_channel_debugger_nallatech_acp_fpga1.apm Locally Modified           84 
 intra_channel_debugger_nallatech_acp_jtag.apm Locally Modified           84 


* Update platforms-acp .apm files to v2.2 format using "awb-shell update model"
* There were two broken .apm files that I had to make guesses on. 
   A) fpgaenv-acp-m2c-nallatech-jtag-no-cache.apm had no intra device. I guessed
      it should have the intra device for fpga0. Perhaps there should be a null
      intra device?
   B) fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm had a broken non-submodel 
      build pipeline that seemed like an out-of-date version of Xilinx pipeline.
      I replaced it with the standard Xilinx build pipeline submodel.
      
   If either of these changes were errors then someone should update these apms.
   

----------
pellauer    Date: Mon Feb 14 15:01:00 MST 2011  CSN: CSN-platforms-acp-86
                  Mon Feb 14 22:01:00 UTC 2011


Directory config/pm/hasim/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Modified           85 
 hasim-fpgaenv-acp-m2c.apm Locally Modified           85 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm Locally Modified           85 
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Modified           85 
 fpgaenv-acp-m2c-nallatech-jtag-no-cache.apm Locally Modified           85 
 fpgaenv-acp-m2c-nallatech.apm Locally Modified           85 
 fpgaenv-acp-m2c-nallatech-local-scratchpad.apm Locally Modified           85 

Directory config/pm/platforms/debuggers/acp
 intra_channel_debugger_nallatech_acp_fpga0.apm Locally Modified           85 
 intra_channel_debugger_nallatech_acp_fpga1.apm Locally Modified           85 
 intra_channel_debugger_nallatech_acp_jtag.apm Locally Modified           85 


* Updating platforms-acp to remove "submodel" bug and get new names of leap     
  submodels.
  

----------
kfleming    Date: Thu Feb 24 15:55:32 EST 2011  CSN: CSN-platforms-acp-87
                  Thu Feb 24 20:55:32 UTC 2011


Directory config/pm/hasim/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Modified           86 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c
 acp-m2c.awb               Locally Modified           86 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-nallatech-fpga0
 acp-m2c.awb               Locally Modified           86 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-nallatech
 acp-m2c.awb               Locally Modified           86 
 acp-m2c.sdc               Locally Modified           86 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-with-sram
 acp-m2c.awb               Locally Modified           86 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-nallatech-jtag
 acp-m2c.awb               Locally Modified           86 


fixed bit/"bit" typo in awb files

----------
mpellaue    Date: Tue Apr  5 15:50:37 EDT 2011  CSN: CSN-platforms-acp-88
                  Tue Apr  5 19:50:37 UTC 2011


Directory config/pm/platforms/debuggers/acp
 intra_channel_debugger_nallatech_acp_fpga0.apm Locally Modified           87 
 intra_channel_debugger_nallatech_acp_fpga1.apm Locally Modified           87 
 intra_channel_debugger_nallatech_acp_jtag.apm Locally Modified           87 


* Change all models to use Build Pipeline.
* Change all models to use full Soft Services.

----------
mcadler     Date: Sun Apr 10 21:55:50 EDT 2011  CSN: CSN-platforms-acp-89
                  Mon Apr 11 01:55:50 UTC 2011


Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c
 acp-m2c.awb               Locally Modified           88 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-nallatech-fpga0
 acp-m2c.awb               Locally Modified           88 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-nallatech
 acp-m2c.awb               Locally Modified           88 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-with-sram
 acp-m2c.cpp               Locally Modified           88 
 acp-m2c.awb               Locally Modified           88 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.cpp Locally Modified           88 
 nallatech-edge-device.awb Locally Modified           88 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-nallatech-jtag
 acp-m2c.awb               Locally Modified           88 

Accept the ACP device ID to use from the command line in order to support
choosing among multiple devices on the host.


----------
joel        Date: Fri Apr 15 20:37:35 EDT 2011  CSN: CSN-leap-platforms-acp-90
                  Sat Apr 16 00:37:35 UTC 2011


Directory admin/packages
 leap-platforms-acp        Locally Added               - 
 platforms-acp             Locally Removed            89 

Changed package name from platforms-acp to leap-platforms-acp.

----------
mcadler     Date: Mon Apr 25 17:18:54 EDT 2011  CSN: CSN-leap-platforms-acp-91
                  Mon Apr 25 21:18:54 UTC 2011


Directory config/pm/hasim/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Modified           90 
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Modified           90 
 fpgaenv-acp-m2c-nallatech.apm Locally Modified           90 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-nallatech-fpga0
 acp-m2c.h                 Locally Modified           90 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-nallatech
 acp-m2c.h                 Locally Modified           90 

- A few modules still needed to include asim/syntax.h
- Update apm dependence.

----------
kfleming    Date: Mon May 16 09:15:49 EDT 2011  CSN: CSN-leap-platforms-acp-92
                  Mon May 16 13:15:49 UTC 2011


Directory config/pm/hasim/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Modified           91 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm Locally Modified           91 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-nallatech-fpga0
 acp-m2c.awb               Locally Modified           91 


Renamed intra-acp modules slightly to match eachother. 

----------
mcadler     Date: Mon May 16 16:40:26 EDT 2011  CSN: CSN-leap-platforms-acp-93
                  Mon May 16 20:40:26 UTC 2011


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.ucf       Locally Modified           92 
 ddr-sram-vhdl-import.bsv  Locally Modified           92 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-vhdl-import.bsv Locally Modified           92 
 nallatech-edge-device.ucf Locally Modified           92 

Significant cleanup of timing for clock-crossing FIFOs.  Bluespec changed the
implementation of SyncFIFO starting with 2011.04.C.  The constraints here
require 2011.04.C or later.

- Describe clock crossing as a transition from one time group to another.
  The old code just listed netlist locations.
- Use INST instead of NET.  NET targets seem to get optimized away
  by Xst unpredictably.
- Remove a bunch of old, commented out, TIGs.

----------
kfleming    Date: Mon May 23 16:21:22 EDT 2011  CSN: CSN-leap-platforms-acp-94
                  Mon May 23 20:21:22 UTC 2011


Directory config/pm/hasim/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Modified           93 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm Locally Modified           93 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device-fpga1.ucf Locally Modified           93 
 nallatech-intra-device-fpga0.ucf Locally Modified           93 
 nallatech-intra-device-fpga1.ucf Locally Modified           93 


Two changes:

1) Intra builds now use multifpga flow (and may be briefly broken by this?)
2) Tweaked ACP ucf accoring to Adler

----------
mcadler     Date: Mon Jun  6 15:51:25 EDT 2011  CSN: CSN-leap-platforms-acp-95
                  Mon Jun  6 19:51:25 UTC 2011


Directory config/pm/hasim/submodels/fpgaenv
 hasim-fpgaenv-acp-m2c.apm Locally Removed            94 
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Modified           94 
 fpgaenv-acp-m2c-nallatech-jtag-no-cache.apm Locally Modified           94 
 fpgaenv-acp-m2c-nallatech.apm Locally Modified           94 
 fpgaenv-acp-m2c-nallatech-local-scratchpad.apm Locally Modified           94 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.ucf       Locally Modified           94 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.vhd Locally Modified           94 
 qdr2_ddr2_clocks.vhd      Locally Modified           94 

- Get rid of the Arches FPGA environment.  As configured, it doesn't work.
- Remove debugging TIGs from SRAM definition.
- Don't request IOBUF insertion for top level modules.  Buffering is already
  provided by the Nallatech libraries.

----------
kfleming    Date: Thu Jun 16 13:22:09 EDT 2011  CSN: CSN-leap-platforms-acp-96
                  Thu Jun 16 17:22:09 UTC 2011


Directory config/pm/hasim/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Modified           95 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm Locally Modified           95 
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Modified           95 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-nallatech-fpga0
 acp-m2c.awb               Locally Modified           95 
 acp-m2c.bsv               Locally Modified           95 
 acp-m2c.bsh               Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-intra-device.bsv Locally Modified           95 
 nallatech-edge-device-fpga1.ucf Locally Modified           95 
 nallatech-intra-device-fpga0.ucf Locally Modified           95 


Upgraded nallatech acp targets to use the new ucf style and added an interface for ucf chunks to the intra physical device.

----------
kfleming    Date: Fri Jun 24 09:24:42 EDT 2011  CSN: CSN-leap-platforms-acp-97
                  Fri Jun 24 13:24:42 UTC 2011


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device-debugger.cpp Locally Modified           96 


Added a helpful warning to remind myself to set environment variables when programming both FPGAs on ACP.

----------
kfleming    Date: Wed Jun 29 17:21:19 EDT 2011  CSN: CSN-leap-platforms-acp-98
                  Wed Jun 29 21:21:19 UTC 2011


Directory config/pm/hasim/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Modified           97 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm Locally Modified           97 
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Modified           97 

Unbroke some apm.

----------
mcadler     Date: Thu Jul  7 16:46:39 EDT 2011  CSN: CSN-leap-platforms-acp-99
                  Thu Jul  7 20:46:39 UTC 2011


Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-with-sram
 acp-m2c.awb               Locally Modified           98 

Don't use the ACP-specific Synplify script.  Clock frequency is specified
as part of the build pipeline.

----------
keflemin    Date: Mon Jul 11 10:32:16 EDT 2011  CSN: CSN-leap-platforms-acp-100
                  Mon Jul 11 14:32:16 UTC 2011


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device-intra-debugger.awb Locally Modified           99 
 nallatech-edge-device-debugger.cpp Locally Modified           99 


Patched the Dual-FPGA stack programmer to handle the new-style FPGA allocator tols in leap-fpga-ctrl.  I can now run dual FPGA implementations of HAsim at Intel. 


----------
kfleming    Date: Wed Aug  3 12:25:13 EDT 2011  CSN: CSN-leap-platforms-acp-101
                  Wed Aug  3 16:25:13 UTC 2011


Directory config/pm/hasim/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-sram-fpga0.apm Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform
 acp-m2c-nallatech-fpga0-with-sram/ Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-nallatech-fpga0-with-sram
 xilinx.ut                 Locally Added               0 
 acp-m2c.cpp               Locally Added               0 
 acp-m2c.h                 Locally Added               0 
 xilinx.xst                Locally Added               0 
 acp-m2c.sdc               Locally Added               0 
 acp-m2c.awb               Locally Added               0 
 acp-m2c.bsv               Locally Added               0 
 acp-m2c.sdf               Locally Added               0 
 acp-m2c.bsh               Locally Added               0 
 acp-m2c.ucf               Locally Added               0 


Added in the SRAM to the multifpga ACP0.  

----------
kfleming    Date: Fri Aug  5 16:28:28 EDT 2011  CSN: CSN-leap-platforms-acp-102
                  Fri Aug  5 20:28:28 UTC 2011


Directory config/pm/platforms/debuggers/acp
 intra_channel_debugger_nallatech_acp_fpga0.apm Locally Modified          101 


Actually added the SRAM to the apm.... Oops. 

----------
keflemin    Date: Mon Aug 15 20:34:49 EDT 2011  CSN: CSN-leap-platforms-acp-103
                  Tue Aug 16 00:34:49 UTC 2011


Directory config/pm/platforms/debuggers/acp
 fpga0_passthrough.apm     Locally Added               0 
 intra_channel_debugger_nallatech_acp_fpga1.apm Locally Modified          102 
 fpga1_scratchpad.apm      Locally Added               0 

Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel
 nallatech-intra/          Locally Added               0 

Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/nallatech-intra
 nallatech-intra-channel.h Locally Added               0 
 nallatech-intra-channel.awb Locally Added               0 
 nallatech-intra-channel.bsv Locally Added               0 
 npc-demarshaller.bsv      Locally Added               0 
 nallatech-intra-channel.cpp Locally Added               0 

Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/nallatech-edge
 nallatech-intra-channel.awb Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/debuggers/intra-fpga/fpga0
 patchthrough/             Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/debuggers/intra-fpga/fpga0/patchthrough
 patch-debugger.awb        Locally Added               0 
 patch-debugger.bsv        Locally Added               0 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device-null.cpp Locally Modified          102 
 nallatech-edge-device-null.awb Locally Modified          102 


Added a passthrough platform from the ACP0 to ACP1.  Now we can build and run any application on the ACP1.  I also verified that the SRAM controller is operational on ACP1.  

----------
kfleming    Date: Fri Aug 19 14:47:31 EDT 2011  CSN: CSN-leap-platforms-acp-104
                  Fri Aug 19 18:47:31 UTC 2011


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-intra-device.bsv Locally Modified          103 


Extended the intra communication channel of the nallatech to be 128 bits.  The multiFPGA compiler can use this information to automatically synthesize a communications protocol. 

----------
mpellaue    Date: Thu Aug 25 18:14:42 EDT 2011  CSN: CSN-leap-platforms-acp-105
                  Thu Aug 25 22:14:42 UTC 2011


Directory config/pm/hasim/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Removed           104 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm Locally Removed           104 
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Removed           104 
 fpgaenv-acp-m2c-nallatech-sram-fpga0.apm Locally Removed           104 
 fpgaenv-acp-m2c-nallatech-jtag-no-cache.apm Locally Removed           104 
 fpgaenv-acp-m2c-nallatech.apm Locally Removed           104 
 fpgaenv-acp-m2c-nallatech-local-scratchpad.apm Locally Removed           104 

Directory config/pm
 leap/                     Locally Added               0 

Directory config/pm/leap
 submodels/                Locally Added               0 

Directory config/pm/leap/submodels
 fpgaenv/                  Locally Added               0 

Directory config/pm/leap/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Added               - 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm Locally Added               - 
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Added               - 
 fpgaenv-acp-m2c-nallatech-sram-fpga0.apm Locally Added               - 
 fpgaenv-acp-m2c-nallatech-jtag-no-cache.apm Locally Added               - 
 fpgaenv-acp-m2c-nallatech.apm Locally Added               - 
 fpgaenv-acp-m2c-nallatech-local-scratchpad.apm Locally Added               - 

Directory config/pm/platforms/debuggers/acp
 fpga0_passthrough.apm     Locally Modified          104 
 intra_channel_debugger_nallatech_acp_fpga0.apm Locally Modified          104 
 intra_channel_debugger_nallatech_acp_fpga1.apm Locally Modified          104 
 fpga1_scratchpad.apm      Locally Modified          104 
 intra_channel_debugger_nallatech_acp_jtag.apm Locally Modified          104 

Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/nallatech-edge
 nallatech-intra-channel.awb Locally Modified          104 


* Updating fpgaenv submodel locations to match leap.
* Updated stale .apm files.

----------
kfleming    Date: Mon Aug 29 23:02:21 EDT 2011  CSN: CSN-leap-platforms-acp-106
                  Tue Aug 30 03:02:21 UTC 2011


Directory config/pm/hasim/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-sram-fpga1.apm Locally Added               0 
 fpgaenv-acp-m2c-nallatech-passthrough-fpga1.apm Locally Added               0 
 fpgaenv-acp-m2c-nallatech-sram-fpga0-syn.apm Locally Added               0 

Directory config/pm/leap/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Modified          105 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm Locally Modified          105 
 fpgaenv-acp-m2c-nallatech-sram-fpga0.apm Locally Modified          105 

Added new apms to support use of SRAM on both FPGA.

----------
kfleming    Date: Mon Aug 29 23:12:04 EDT 2011  CSN: CSN-leap-platforms-acp-106
                  Tue Aug 30 03:12:04 UTC 2011


Directory config/pm/hasim/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-sram-fpga1.apm Locally Added               0 
 fpgaenv-acp-m2c-nallatech-passthrough-fpga1.apm Locally Added               0 
 fpgaenv-acp-m2c-nallatech-sram-fpga0-syn.apm Locally Added               0 

Directory config/pm/leap/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Modified          105 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm Locally Modified          105 
 fpgaenv-acp-m2c-nallatech-sram-fpga0.apm Locally Modified          105 
 fpgaenv-acp-m2c-nallatech-sram-fpga1.apm Locally Added               0 
 fpgaenv-acp-m2c-nallatech-passthrough-fpga1.apm Locally Added               0 
 fpgaenv-acp-m2c-nallatech-sram-fpga0-syn.apm Locally Added               0 

Directory admin
 mytags                    Locally Modified          105 

Directory admin/packages
 leap-platforms-acp        Locally Modified          105 

Directory .
 changes                   Locally Modified          105 


Added some new apm that use the sram on the second fpga.

----------
kfleming    Date: Mon Aug 29 23:13:13 EDT 2011  CSN: CSN-leap-platforms-acp-107
                  Tue Aug 30 03:13:13 UTC 2011


Directory config/pm/hasim/submodels
 fpgaenv/                  Locally Removed           106 

Directory config/pm/hasim/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Removed           106 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm Locally Removed           106 
 fpgaenv-acp-m2c-nallatech-sram-fpga0.apm Locally Removed           106 
 fpgaenv-acp-m2c-nallatech-sram-fpga1.apm Locally Removed           106 
 fpgaenv-acp-m2c-nallatech-passthrough-fpga1.apm Locally Removed           106 
 fpgaenv-acp-m2c-nallatech-sram-fpga0-syn.apm Locally Removed           106 

Deleted old apm.  They came back during the last checkin somehow.  What a strange behavior.

----------
keflemin    Date: Thu Sep  1 15:18:36 EDT 2011  CSN: CSN-leap-platforms-acp-108
                  Thu Sep  1 19:18:36 UTC 2011


Directory config/pm/leap/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Modified          107 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm Locally Modified          107 
 fpgaenv-acp-m2c-nallatech-sram-fpga0.apm Locally Modified          107 
 fpgaenv-acp-m2c-nallatech-sram-fpga1.apm Locally Modified          107 


Updated some apm

----------
mcadler     Date: Thu Sep  1 15:27:01 EDT 2011  CSN: CSN-leap-platforms-acp-109
                  Thu Sep  1 19:27:01 UTC 2011


Directory config/pm/leap/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-passthrough-fpga1.apm Locally Modified          108 
 fpgaenv-acp-m2c-nallatech-sram-fpga0-syn.apm Locally Modified          108 

Update a couple more apms.

----------
mcadler     Date: Sun Sep  4 09:59:10 EDT 2011  CSN: CSN-leap-platforms-acp-110
                  Sun Sep  4 13:59:10 UTC 2011


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.ucf       Locally Modified          109 

Add TIGs to SRAM reset signals.  This appears to have a huge impact on the ability
to meet timing.

----------
mcadler     Date: Sat Sep 10 21:14:53 EDT 2011  CSN: CSN-leap-platforms-acp-111
                  Sun Sep 11 01:14:53 UTC 2011


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device-fpga1.ucf Locally Modified          110 

The wonderful thing about TIGs is TIGs are wonderful things.

----------
mcadler     Date: Mon Sep 12 11:21:43 EDT 2011  CSN: CSN-leap-platforms-acp-112
                  Mon Sep 12 15:21:43 UTC 2011


Directory config/pm/leap/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Modified          111 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm Locally Modified          111 
 fpgaenv-acp-m2c-nallatech-sram-fpga0.apm Locally Modified          111 
 fpgaenv-acp-m2c-nallatech-sram-fpga1.apm Locally Modified          111 
 fpgaenv-acp-m2c-nallatech.apm Locally Modified          111 

- Add "-cm balanced" to mapper options.  It seems to make a small difference
  when resources are tight.

- Change multi-FPGA with SRAM default frequency to 50MHz in order to make
  the first pass likely to meet timing.

----------
mcadler     Date: Thu Sep 15 16:37:53 EDT 2011  CSN: CSN-leap-platforms-acp-113
                  Thu Sep 15 20:37:53 UTC 2011


Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-with-sram
 acp-m2c.h                 Locally Modified          112 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.bsv Locally Modified          112 
 nallatech-edge-device-intra-debugger.awb Locally Modified          112 
 nallatech-edge-device.awb Locally Modified          112 
 nallatech-edge-device-null.awb Locally Modified          112 

- Add the ability to specify the frequency of DDR memory.

- Reduce default memory clock from 200 to 175MHz.  The change has a small effect
  on HAsim models when the model clock is unchanged, but typically allows us
  to raise the model clock frequency.  The RAM clock was often the source of
  timing errors at 200MHz.

----------
mcadler     Date: Fri Sep 16 07:28:27 EDT 2011  CSN: CSN-leap-platforms-acp-114
                  Fri Sep 16 11:28:27 UTC 2011


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.ucf       Locally Modified          113 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.ucf Locally Modified          113 

Add another register to SyncFIFO TIGs.

----------
mcadler     Date: Thu Sep 22 07:01:23 EDT 2011  CSN: CSN-leap-platforms-acp-115
                  Thu Sep 22 11:01:23 UTC 2011


Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-with-sram
 acp-m2c.bsv               Locally Modified          114 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.ucf       Locally Modified          114 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.bsv Locally Modified          114 
 nallatech-edge-device-fpga1.ucf Locally Modified          114 
 nallatech-edge-device.ucf Locally Modified          114 
 nallatech-intra-device-fpga0.ucf Locally Modified          114 
 nallatech-intra-device-fpga1.ucf Locally Modified          114 

- Improve reset:
  - DDR RAM reset now held until its clock stabilizes.
  - Make model reset longer.

- Sync FIFOs:
  - Stop claiming dDoutReg has a global TIG!
  - We really should be claiming a time on cross-clock domain paths instead of
    just TIG.

----------
mcadler     Date: Fri Sep 23 08:30:20 EDT 2011  CSN: CSN-leap-platforms-acp-116
                  Fri Sep 23 12:30:20 UTC 2011


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.ucf       Locally Modified          115 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device-fpga1.ucf Locally Modified          115 
 nallatech-edge-device.ucf Locally Modified          115 
 nallatech-intra-device-fpga0.ucf Locally Modified          115 
 nallatech-intra-device-fpga1.ucf Locally Modified          115 

- Sync FIFO clock crossings are no longer tagged TIG.  They have a real time
  constraint (currently 5ns, to match the 200MHz edge clock).  If a model clock
  faster than 200MHz is ever used we will have to revisit this code, changing
  the build pipeline to update UCF files by converting frequencies to time.

- Reset paths that appear to cross sync FIFO clock domains are now tagged TIG.
  I believe these are false paths.

- Update a few missing entries in FPGA1 constraints.

----------
mcadler     Date: Sat Oct  1 14:30:19 EDT 2011  CSN: CSN-leap-platforms-acp-117
                  Sat Oct  1 18:30:19 UTC 2011


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.ucf       Locally Modified          116 
 ddr2_sram.vhd             Locally Modified          116 
 ddr-sram-device.bsv       Locally Modified          116 
 ddr-sram-vhdl-import.bsv  Locally Modified          116 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.bsv Locally Modified          116 
 nallatech-edge-device-intra-debugger.awb Locally Modified          116 
 nallatech-edge-device.awb Locally Modified          116 
 nallatech-edge-device-null.awb Locally Modified          116 

Sigh.  Some ACP stacks work fine with RAM speeds below 200MHz.  Some do not.
Revert to a 200MHz default.

In the process of experimenting, cleaned up the code:
 - Removed complex start up sequence, replacing it with a RAM controller reset
   that is triggered either by the edge controller or the model reset.
 - Switch to Xilinx-default IODELAY instantiation, instead of the Nallatech
   version.  We were hard wiring one of the two ram controller's IODELAY
   location, but not the other.

----------
kfleming    Date: Fri Oct 28 08:08:21 EDT 2011  CSN: CSN-leap-platforms-acp-118
                  Fri Oct 28 12:08:21 UTC 2011


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-intra-device.bsv Locally Modified          117 


Widened the physical inter-fpga interface to the full 256 bits.


----------
mcadler     Date: Wed Nov  2 15:49:20 EDT 2011  CSN: CSN-leap-platforms-acp-119
                  Wed Nov  2 19:49:20 UTC 2011


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.ucf       Locally Modified          118 
 ddr-sram-device.bsv       Locally Modified          118 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device-fpga1.ucf Locally Modified          118 
 nallatech-edge-device.ucf Locally Modified          118 
 nallatech-intra-device-fpga1.ucf Locally Modified          118 

More timing improvements:

- Tag clock domain crossings DATAPATHONLY to eliminate hold time violations.

- Add buffering in memory controller between syncFIFOs and logic.  The
  buffering barely adds latency in the model, since the memory clock is
  200MHz.

----------
mcadler     Date: Mon Nov  7 15:25:55 EST 2011  CSN: CSN-leap-platforms-acp-120
                  Mon Nov  7 20:25:55 UTC 2011


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-intra-device.bsv Locally Modified          119 
 nallatech-edge-device-debugger.cpp Locally Modified          119 
 nallatech-intra-device-fpga0.awb Locally Modified          119 
 nallatech-intra-device-fpga1.awb Locally Modified          119 

During initialization of a pair of FPGAs within a module, FPGA0 is allowed to
write to FPGA1 in spite of it not being ready.  Added a simple initialization
protocol, where FPGA0 waits to hear from FPGA1 before sending any messages.
I can't find any Nallatech documentation on a better method.  This simple
protocol probably depends on the order in which each FPGA is initialized,
though I didn't test that.  Also added comments to the C++ initialization
code, noting the fragility of the startup sequence.

----------
kfleming    Date: Thu Nov 10 15:01:20 EST 2011  CSN: CSN-leap-platforms-acp-121
                  Thu Nov 10 20:01:20 UTC 2011


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-intra-device.bsv Locally Modified          120 


Modified the nallactech intra device interface to conform to the
interface now expected by the router generation code.

----------
kfleming    Date: Tue Nov 15 12:09:08 EST 2011  CSN: CSN-leap-platforms-acp-122
                  Tue Nov 15 17:09:08 UTC 2011


Directory config/pm/leap/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Modified          121 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm Locally Modified          121 
 fpgaenv-acp-m2c-nallatech-sram-fpga0.apm Locally Modified          121 
 fpgaenv-acp-m2c-nallatech-sram-fpga1.apm Locally Modified          121 
 fpgaenv-acp-m2c-nallatech-sram-fpga0-syn.apm Locally Modified          121 


Updated modules after moving multifpga log generation to the multifpga package. 

----------
mcadler     Date: Tue Nov 22 16:27:15 EST 2011  CSN: CSN-leap-platforms-acp-123
                  Tue Nov 22 21:27:15 UTC 2011


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-intra-device.bsv Locally Modified          122 

Move initialization out of the high frequency clock domain to reduce timing
pressume.

----------
mcadler     Date: Thu Dec  1 14:33:41 EST 2011  CSN: CSN-leap-platforms-acp-124
                  Thu Dec  1 19:33:41 UTC 2011


Directory config/pm/leap/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Modified          123 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm Locally Modified          123 
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Modified          123 
 fpgaenv-acp-m2c-nallatech-sram-fpga0.apm Locally Modified          123 
 fpgaenv-acp-m2c-nallatech-sram-fpga1.apm Locally Modified          123 
 fpgaenv-acp-m2c-nallatech-jtag-no-cache.apm Locally Modified          123 
 fpgaenv-acp-m2c-nallatech.apm Locally Modified          123 
 fpgaenv-acp-m2c-nallatech-passthrough-fpga1.apm Locally Modified          123 
 fpgaenv-acp-m2c-nallatech-local-scratchpad.apm Locally Modified          123 
 fpgaenv-acp-m2c-nallatech-sram-fpga0-syn.apm Locally Modified          123 

Directory config/pm/platforms/debuggers/acp
 fpga0_passthrough.apm     Locally Modified          123 
 intra_channel_debugger_nallatech_acp_fpga0.apm Locally Modified          123 
 intra_channel_debugger_nallatech_acp_fpga1.apm Locally Modified          123 
 fpga1_scratchpad.apm      Locally Modified          123 
 intra_channel_debugger_nallatech_acp_jtag.apm Locally Modified          123 

Update platforms for LEAP changes:  moved platform and soft services to FPGA
environment.

----------
mcadler     Date: Thu Dec  1 22:47:27 EST 2011  CSN: CSN-leap-platforms-acp-125
                  Fri Dec  2 03:47:27 UTC 2011


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.ucf       Locally Modified          124 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device-fpga1.ucf Locally Modified          124 
 nallatech-edge-device.ucf Locally Modified          124 
 nallatech-intra-device-fpga0.ucf Locally Modified          124 
 nallatech-intra-device-fpga1.ucf Locally Modified          124 

LLPI no longer under virtual platform.

----------
mcadler     Date: Wed Dec  7 11:55:30 EST 2011  CSN: CSN-leap-platforms-acp-126
                  Wed Dec  7 16:55:30 UTC 2011


Directory config/pm/leap/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Modified          125 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm Locally Modified          125 
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Modified          125 
 fpgaenv-acp-m2c-nallatech-sram-fpga0.apm Locally Modified          125 
 fpgaenv-acp-m2c-nallatech-sram-fpga1.apm Locally Modified          125 
 fpgaenv-acp-m2c-nallatech-jtag-no-cache.apm Locally Modified          125 
 fpgaenv-acp-m2c-nallatech-passthrough-fpga1.apm Locally Modified          125 
 fpgaenv-acp-m2c-nallatech-sram-fpga0-syn.apm Locally Modified          125 

Virtual devices now requires a local memory device.

----------
mcadler     Date: Sat Dec 10 16:48:29 EST 2011  CSN: CSN-leap-platforms-acp-127
                  Sat Dec 10 21:48:29 UTC 2011


Directory config/pm/leap/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-local-scratchpad.apm Locally Modified          126 

Update configuration.

----------
mcadler     Date: Wed Dec 14 23:30:28 EST 2011  CSN: CSN-leap-platforms-acp-128
                  Thu Dec 15 04:30:28 UTC 2011


Directory config/pm/leap/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Modified          127 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm Locally Modified          127 
 fpgaenv-acp-m2c-nallatech-sram-fpga0.apm Locally Modified          127 
 fpgaenv-acp-m2c-nallatech-sram-fpga1.apm Locally Modified          127 
 fpgaenv-acp-m2c-nallatech.apm Locally Modified          127 

Clean up.

----------
mcadler     Date: Mon Dec 19 09:08:15 EST 2011  CSN: CSN-leap-platforms-acp-129
                  Mon Dec 19 14:08:15 UTC 2011


Directory config/pm/leap/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Modified          128 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm Locally Modified          128 
 fpgaenv-acp-m2c-nallatech-sram-fpga0.apm Locally Modified          128 
 fpgaenv-acp-m2c-nallatech-sram-fpga1.apm Locally Modified          128 
 fpgaenv-acp-m2c-nallatech-sram-fpga0-syn.apm Locally Modified          128 

Use a single virtual devices configuration, taking advantage of automatic
master/slave configuration in virtual devices.

----------
mcadler     Date: Mon Dec 19 12:23:01 EST 2011  CSN: CSN-leap-platforms-acp-130
                  Mon Dec 19 17:23:01 UTC 2011


Directory config/pm/leap/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Modified          129 
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Modified          129 
 fpgaenv-acp-m2c-nallatech-jtag-no-cache.apm Locally Modified          129 
 fpgaenv-acp-m2c-nallatech-passthrough-fpga1.apm Locally Modified          129 
 fpgaenv-acp-m2c-nallatech-local-scratchpad.apm Locally Modified          129 

Clean up after moving modules.

----------
emer        Date: Thu Jan 26 13:55:22 EST 2012  CSN: CSN-leap-platforms-acp-131
                  Thu Jan 26 18:55:22 UTC 2012


Directory admin/packages
 leap-platforms-acp        Locally Modified          130 

Mark package as a 'prerelease'.

----------
mcadler     Date: Wed Feb  8 01:05:37 EST 2012  CSN: CSN-leap-platforms-acp-132
                  Wed Feb  8 06:05:37 UTC 2012


Directory config/pm/leap/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Modified          131 
 fpgaenv-acp-m2c-nallatech-jtag-no-cache.apm Locally Modified          131 
 fpgaenv-acp-m2c-nallatech-passthrough-fpga1.apm Locally Modified          131 
 fpgaenv-acp-m2c-nallatech-sram-fpga0-syn.apm Locally Modified          131 

Updates for removal of debug scan device.

----------
mcadler     Date: Tue Apr 10 19:59:20 EDT 2012  CSN: CSN-leap-platforms-acp-133
                  Tue Apr 10 23:59:20 UTC 2012


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device-debugger.cpp Locally Modified          132 

Correct spelling.

----------
kfleming    Date: Tue Apr 17 14:10:44 EDT 2012  CSN: CSN-leap-platforms-acp-134
                  Tue Apr 17 18:10:44 UTC 2012


Directory config/pm/leap/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Modified          133 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-intra-device-fpga0.awb Locally Modified          133 
 nallatech-intra-device-fpga1.awb Locally Modified          133 


Removed duplicate vhd includes.

----------
mcadler     Date: Sun Apr 29 19:34:13 EDT 2012  CSN: CSN-leap-platforms-acp-135
                  Sun Apr 29 23:34:13 UTC 2012


Directory config/pm/leap/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Modified          134 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm Locally Modified          134 
 fpgaenv-acp-m2c-nallatech-sram-fpga0.apm Locally Modified          134 
 fpgaenv-acp-m2c-nallatech-sram-fpga1.apm Locally Modified          134 
 fpgaenv-acp-m2c-nallatech-sram-fpga0-syn.apm Locally Modified          134 

multi-FPGA Bluespec builds and wrapper generation now handled by leap instead
of leap-multifpga.

----------
mcadler     Date: Fri Jun 29 16:05:44 EDT 2012  CSN: CSN-leap-platforms-acp-136
                  Fri Jun 29 20:05:44 UTC 2012


Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c
 xilinx.download           Locally Removed           135 
 acp-m2c.awb               Locally Modified          135 

Remove unnecessary bitfile download script.

----------
mcadler     Date: Wed Oct 17 07:39:56 EDT 2012  CSN: CSN-leap-platforms-acp-137
                  Wed Oct 17 11:39:56 UTC 2012


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.bsv Locally Modified          136 
 nallatech-intra-device.bsv Locally Modified          136 

Add a buffer next to clock crossing FIFOs to relax timing.

----------
mcadler     Date: Tue Oct 30 20:44:57 EDT 2012  CSN: CSN-leap-platforms-acp-138
                  Wed Oct 31 00:44:57 UTC 2012


Directory config/pm/leap/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-sram-fpga0.apm Locally Modified          137 
 fpgaenv-acp-m2c-nallatech-sram-fpga1.apm Locally Modified          137 
 fpgaenv-acp-m2c-nallatech-jtag-no-cache.apm Locally Modified          137 
 fpgaenv-acp-m2c-nallatech-no-local-mem.apm Locally Added               0 
 fpgaenv-acp-m2c-nallatech.apm Locally Modified          137 
 fpgaenv-acp-m2c-nallatech-passthrough-fpga1.apm Locally Modified          137 
 fpgaenv-acp-m2c-nallatech-local-scratchpad.apm Locally Modified          137 
 fpgaenv-acp-m2c-nallatech-sram-fpga0-syn.apm Locally Modified          137 

Directory config/pm/platforms/debuggers/acp
 intra_channel_debugger_nallatech_acp_fpga0.apm Locally Modified          137 
 fpga0_passthrough.apm     Locally Modified          137 
 fpga1_scratchpad.apm      Locally Modified          137 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-nallatech-fpga0-with-sram
 acp-m2c.awb               Locally Modified          137 
 acp-m2c.bsv               Locally Modified          137 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-with-sram
 acp-m2c.awb               Locally Modified          137 
 acp-m2c.bsv               Locally Modified          137 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device-fake.awb  Locally Modified          137 
 ddr-sram-device.bsv       Locally Modified          137 
 ddr-sram-vhdl-import.bsv  Locally Modified          137 
 ddr-sram-fake.bsv         Locally Modified          137 
 ddr-sram-device.awb       Locally Modified          137 

Update ACP memory configuration to yesterday's SDRAM changes in platforms.
The result is ACP SRAM is called SDRAM.  Sigh.  We're unlikely to encounter
SRAM in future platforms, so the ACP will have to suffer in silence.

----------
mcadler     Date: Thu Nov  1 08:10:48 EDT 2012  CSN: CSN-leap-platforms-acp-139
                  Thu Nov  1 12:10:48 UTC 2012


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.bsv       Locally Modified          138 
 ddr-sram-fake.bsv         Locally Modified          138 
 ddr-sram-device.awb       Locally Modified          138 

Conform to new AWB parameter naming.

----------
mcadler     Date: Mon Nov  5 20:01:18 EST 2012  CSN: CSN-leap-platforms-acp-140
                  Tue Nov  6 01:01:18 UTC 2012


Directory config/pm/leap/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-sram-fpga0.apm Locally Modified          139 
 fpgaenv-acp-m2c-nallatech-sram-fpga1.apm Locally Modified          139 
 fpgaenv-acp-m2c-nallatech.apm Locally Modified          139 
 fpgaenv-acp-m2c-nallatech-local-scratchpad.apm Locally Modified          139 
 fpgaenv-acp-m2c-nallatech-sram-fpga0-syn.apm Locally Modified          139 

Directory config/pm/platforms/debuggers/acp
 fpga0_passthrough.apm     Locally Modified          139 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.bsv       Locally Modified          139 
 ddr-sram-vhdl-import.bsv  Locally Modified          139 

Local memory implementation changed.

----------
mcadler     Date: Mon Nov 12 15:30:21 EST 2012  CSN: CSN-leap-platforms-acp-141
                  Mon Nov 12 20:30:21 UTC 2012


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/ddr-sram
 ddr-sram-device.bsv       Locally Modified          140 

DDR_DRIVER interface now expected to have a list of debug scan objects.

----------
kfleming    Date: Thu Mar  7 11:24:22 EST 2013  CSN: CSN-leap-platforms-acp-142
                  Thu Mar  7 16:24:22 UTC 2013


Directory config/pm/leap/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-debugger-mem.apm Locally Added               - 


Added apm for SRAM debugger.  Existing APMs use BRAM rather than SRAM.

----------
kfleming    Date: Sun May 12 17:07:15 EDT 2013  CSN: CSN-leap-platforms-acp-143
                  Sun May 12 21:07:15 UTC 2013


Directory config/pm/leap/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Modified          142 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm Locally Modified          142 
 fpgaenv-acp-m2c-nallatech-sram-fpga0.apm Locally Modified          142 
 fpgaenv-acp-m2c-nallatech-sram-fpga1.apm Locally Modified          142 
 fpgaenv-acp-m2c-nallatech-sram-fpga0-syn.apm Locally Modified          142 


Updated apm to use new awb parameter parser.

----------
mcadler     Date: Sat May 18 09:10:23 EDT 2013  CSN: CSN-leap-platforms-acp-144
                  Sat May 18 13:10:23 UTC 2013


Directory config/pm/leap/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Modified          143 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm Locally Modified          143 

Fix broken configurations.

----------
mcadler     Date: Sun Dec 22 22:27:46 EST 2013  CSN: CSN-leap-platforms-acp-145
                  Mon Dec 23 03:27:46 UTC 2013


Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/nallatech-edge
 nallatech-edge-channel.cpp Locally Modified          144 
 nallatech-edge-channel.h  Locally Modified          144 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-nallatech-fpga0-with-sram
 acp-m2c.h                 Locally Modified          144 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-nallatech-fpga0
 acp-m2c.h                 Locally Modified          144 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-nallatech
 acp-m2c.h                 Locally Modified          144 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-with-sram
 acp-m2c.h                 Locally Modified          144 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.h   Locally Modified          144 
 nallatech-edge-device.cpp Locally Modified          144 

Update to most recent platforms software interfaces.

----------
mcadler     Date: Mon Jan  6 23:08:15 EST 2014  CSN: CSN-leap-platforms-acp-146
                  Tue Jan  7 04:08:15 UTC 2014


Directory config/pm/leap/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-sram-fpga0.apm Locally Modified          145 
 fpgaenv-acp-m2c-nallatech-sram-fpga1.apm Locally Modified          145 
 fpgaenv-acp-m2c-nallatech.apm Locally Modified          145 

Update multi-FPGA configurations.

----------
mcadler     Date: Wed Jan  8 09:50:23 EST 2014  CSN: CSN-leap-platforms-acp-147
                  Wed Jan  8 14:50:23 UTC 2014


Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device-debugger.cpp Locally Modified          146 

Make multi-FPGA work.

----------
keflemin    Date: Tue Mar  4 16:20:29 EST 2014  CSN: CSN-leap-platforms-acp-148
                  Tue Mar  4 21:20:29 UTC 2014


Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/nallatech-intra
 nallatech-intra-channel.cpp Locally Modified          147 

Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/nallatech-edge
 nallatech-edge-channel.cpp Locally Modified          147 


Changed legacy physical channels to use correct packet endianess.

----------
keflemin    Date: Sat Apr 12 18:23:07 EDT 2014  CSN: CSN-leap-platforms-acp-149
                  Sat Apr 12 22:23:07 UTC 2014


Directory config/pm/leap/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-sram-fpga0.apm Locally Modified          148 
 fpgaenv-acp-m2c-nallatech-sram-fpga1.apm Locally Modified          148 

Directory modules/bluespec/common/fpgaenv/virtual-platform/channelio/physical-channel/nallatech-edge
 nallatech-edge-channel.cpp Locally Modified          148 
 nallatech-edge-channel.h  Locally Modified          148 

Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-with-sram
 acp-m2c.cpp               Locally Modified          148 
 acp-m2c.h                 Locally Modified          148 

Directory modules/bluespec/common/fpgaenv/physical-platform/physical-devices/nallatech-edge
 nallatech-edge-device.h   Locally Modified          148 
 nallatech-edge-device.cpp Locally Modified          148 



Updated ACP channel code to provide new LEAP physical device interfaces. 

----------
keflemin    Date: Mon Apr 14 10:46:10 EDT 2014  CSN: CSN-leap-platforms-acp-150
                  Mon Apr 14 14:46:10 UTC 2014


Directory modules/bluespec/common/fpgaenv/physical-platform/acp-m2c-with-sram
 acp-m2c.cpp               Locally Modified          149 
 acp-m2c.h                 Locally Modified          149 


Added symlinks connecting ACP physical platform codes.

Added comments to base acp physical platform files.


----------
keflemin    Date: Tue May 13 08:33:39 EDT 2014  CSN: CSN-leap-platforms-acp-151
                  Tue May 13 12:33:39 UTC 2014


Directory config/pm/leap/submodels/fpgaenv
 fpgaenv-acp-m2c-nallatech-no-cache-fpga0.apm Locally Modified          150 
 fpgaenv-acp-m2c-nallatech-no-cache-fpga1.apm Locally Modified          150 
 fpgaenv-acp-m2c-nallatech-no-cache.apm Locally Modified          150 
 fpgaenv-acp-m2c-nallatech-sram-fpga0.apm Locally Modified          150 
 fpgaenv-acp-m2c-nallatech-sram-fpga1.apm Locally Modified          150 
 fpgaenv-acp-m2c-nallatech-jtag-no-cache.apm Locally Modified          150 
 fpgaenv-acp-m2c-nallatech-debugger-mem.apm Locally Modified          150 
 fpgaenv-acp-m2c-nallatech-no-local-mem.apm Locally Modified          150 
 fpgaenv-acp-m2c-nallatech.apm Locally Modified          150 
 fpgaenv-acp-m2c-nallatech-passthrough-fpga1.apm Locally Modified          150 
 fpgaenv-acp-m2c-nallatech-local-scratchpad.apm Locally Modified          150 
 fpgaenv-acp-m2c-nallatech-sram-fpga0-syn.apm Locally Modified          150 

Directory config/pm/platforms/debuggers/acp
 fpga0_passthrough.apm     Locally Modified          150 
 intra_channel_debugger_nallatech_acp_fpga0.apm Locally Modified          150 
 intra_channel_debugger_nallatech_acp_fpga1.apm Locally Modified          150 
 fpga1_scratchpad.apm      Locally Modified          150 
 intra_channel_debugger_nallatech_acp_jtag.apm Locally Modified          150 


Updated broken apms.