diff --git a/lab_06/src/01_counter_simple/simulation/02_simulate_with_icarus.sh b/lab_06/src/01_counter_simple/simulation/02_simulate_with_icarus.sh old mode 100755 new mode 100644 diff --git a/lab_06/src/01_counter_simple/synthesis/de2_115.qpf b/lab_06/src/01_counter_simple/synthesis/de10_lite.qpf similarity index 100% rename from lab_06/src/01_counter_simple/synthesis/de2_115.qpf rename to lab_06/src/01_counter_simple/synthesis/de10_lite.qpf diff --git a/lab_06/src/01_counter_simple/synthesis/de10_lite.qsf b/lab_06/src/01_counter_simple/synthesis/de10_lite.qsf new file mode 100644 index 0000000..3f91805 --- /dev/null +++ b/lab_06/src/01_counter_simple/synthesis/de10_lite.qsf @@ -0,0 +1,60 @@ +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 + +set_global_assignment -name TOP_LEVEL_ENTITY de10_lite + +set_global_assignment -name VERILOG_FILE de10_lite.v +set_global_assignment -name VERILOG_FILE ../simple_counter.v +set_global_assignment -name VERILOG_FILE ../../common/led7.v +set_global_assignment -name VERILOG_FILE ../../common/clk_divider.v + +set_global_assignment -name SDC_FILE de10_lite.sdc + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX* +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY* + +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_P11 -to CLOCK_50 + +#============================================================ +# KEY +#============================================================ +set_location_assignment PIN_B8 -to KEY[0] + +#============================================================ +# HEX0 +#============================================================ + +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] + +#============================================================ +# HEX1 +#============================================================ + +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] + +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Standard Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_file +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/lab_06/src/02_counter_with_load/synthesis/de2_115.sdc b/lab_06/src/01_counter_simple/synthesis/de10_lite.sdc similarity index 55% rename from lab_06/src/02_counter_with_load/synthesis/de2_115.sdc rename to lab_06/src/01_counter_simple/synthesis/de10_lite.sdc index 01192ab..bc5f3b2 100644 --- a/lab_06/src/02_counter_with_load/synthesis/de2_115.sdc +++ b/lab_06/src/01_counter_simple/synthesis/de10_lite.sdc @@ -2,6 +2,10 @@ create_clock -period 50MHz [get_ports CLOCK_50] derive_clock_uncertainty +create_generated_clock -name clk_slow\ + -source [get_ports CLOCK_50]\ + [get_registers {clk_divider:clk_div|cnt_div[*]}] + set_false_path -from * -to [get_ports {HEX0[*]}] set_false_path -from * -to [get_ports {HEX1[*]}] diff --git a/lab_06/src/01_counter_simple/synthesis/de2_115.v b/lab_06/src/01_counter_simple/synthesis/de10_lite.v similarity index 91% rename from lab_06/src/01_counter_simple/synthesis/de2_115.v rename to lab_06/src/01_counter_simple/synthesis/de10_lite.v index 5c4f318..d7edb40 100644 --- a/lab_06/src/01_counter_simple/synthesis/de2_115.v +++ b/lab_06/src/01_counter_simple/synthesis/de10_lite.v @@ -1,10 +1,10 @@ -module de2_115 +module de10_lite ( input CLOCK_50, input [0:0] KEY, - output [6:0] HEX1, - output [6:0] HEX0 + output [7:0] HEX1, + output [7:0] HEX0 ); localparam CNT_W = 8; diff --git a/lab_06/src/01_counter_simple/synthesis/de2_115.qsf b/lab_06/src/01_counter_simple/synthesis/de2_115.qsf deleted file mode 100644 index 33dfef8..0000000 --- a/lab_06/src/01_counter_simple/synthesis/de2_115.qsf +++ /dev/null @@ -1,93 +0,0 @@ -set_global_assignment -name DEVICE EP4CE115F29C7 -set_global_assignment -name FAMILY "Cyclone IV E" -set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 - -set_global_assignment -name TOP_LEVEL_ENTITY de2_115 - -set_global_assignment -name VERILOG_FILE de2_115.v -set_global_assignment -name VERILOG_FILE ../simple_counter.v -set_global_assignment -name VERILOG_FILE ../../common/led7.v -set_global_assignment -name VERILOG_FILE ../../common/clk_divider.v - -set_global_assignment -name SDC_FILE de2_115.sdc - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY* - -#============================================================ -# CLOCK -#============================================================ -set_location_assignment PIN_Y2 -to CLOCK_50 - -#============================================================ -# KEY -#============================================================ -set_location_assignment PIN_M23 -to KEY[0] - -#============================================================ -# SEG7 -#============================================================ -set_location_assignment PIN_G18 -to HEX0[0] -set_location_assignment PIN_F22 -to HEX0[1] -set_location_assignment PIN_E17 -to HEX0[2] -set_location_assignment PIN_L26 -to HEX0[3] -set_location_assignment PIN_L25 -to HEX0[4] -set_location_assignment PIN_J22 -to HEX0[5] -set_location_assignment PIN_H22 -to HEX0[6] -set_location_assignment PIN_M24 -to HEX1[0] -set_location_assignment PIN_Y22 -to HEX1[1] -set_location_assignment PIN_W21 -to HEX1[2] -set_location_assignment PIN_W22 -to HEX1[3] -set_location_assignment PIN_W25 -to HEX1[4] -set_location_assignment PIN_U23 -to HEX1[5] -set_location_assignment PIN_U24 -to HEX1[6] -set_location_assignment PIN_AA25 -to HEX2[0] -set_location_assignment PIN_AA26 -to HEX2[1] -set_location_assignment PIN_Y25 -to HEX2[2] -set_location_assignment PIN_W26 -to HEX2[3] -set_location_assignment PIN_Y26 -to HEX2[4] -set_location_assignment PIN_W27 -to HEX2[5] -set_location_assignment PIN_W28 -to HEX2[6] -set_location_assignment PIN_V21 -to HEX3[0] -set_location_assignment PIN_U21 -to HEX3[1] -set_location_assignment PIN_AB20 -to HEX3[2] -set_location_assignment PIN_AA21 -to HEX3[3] -set_location_assignment PIN_AD24 -to HEX3[4] -set_location_assignment PIN_AF23 -to HEX3[5] -set_location_assignment PIN_Y19 -to HEX3[6] -set_location_assignment PIN_AB19 -to HEX4[0] -set_location_assignment PIN_AA19 -to HEX4[1] -set_location_assignment PIN_AG21 -to HEX4[2] -set_location_assignment PIN_AH21 -to HEX4[3] -set_location_assignment PIN_AE19 -to HEX4[4] -set_location_assignment PIN_AF19 -to HEX4[5] -set_location_assignment PIN_AE18 -to HEX4[6] -set_location_assignment PIN_AD18 -to HEX5[0] -set_location_assignment PIN_AC18 -to HEX5[1] -set_location_assignment PIN_AB18 -to HEX5[2] -set_location_assignment PIN_AH19 -to HEX5[3] -set_location_assignment PIN_AG19 -to HEX5[4] -set_location_assignment PIN_AF18 -to HEX5[5] -set_location_assignment PIN_AH18 -to HEX5[6] -set_location_assignment PIN_AA17 -to HEX6[0] -set_location_assignment PIN_AB16 -to HEX6[1] -set_location_assignment PIN_AA16 -to HEX6[2] -set_location_assignment PIN_AB17 -to HEX6[3] -set_location_assignment PIN_AB15 -to HEX6[4] -set_location_assignment PIN_AA15 -to HEX6[5] -set_location_assignment PIN_AC17 -to HEX6[6] -set_location_assignment PIN_AD17 -to HEX7[0] -set_location_assignment PIN_AE17 -to HEX7[1] -set_location_assignment PIN_AG17 -to HEX7[2] -set_location_assignment PIN_AH17 -to HEX7[3] -set_location_assignment PIN_AF17 -to HEX7[4] -set_location_assignment PIN_AG18 -to HEX7[5] -set_location_assignment PIN_AA14 -to HEX7[6] - - -set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Standard Edition" -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top \ No newline at end of file diff --git a/lab_06/src/02_counter_with_load/simulation/01_simulate_with_modelsim.sh b/lab_06/src/02_counter_with_load/simulation/01_simulate_with_modelsim.sh old mode 100755 new mode 100644 diff --git a/lab_06/src/02_counter_with_load/simulation/02_simulate_with_icarus.sh b/lab_06/src/02_counter_with_load/simulation/02_simulate_with_icarus.sh old mode 100755 new mode 100644 diff --git a/lab_06/src/02_counter_with_load/synthesis/de2_115.qpf b/lab_06/src/02_counter_with_load/synthesis/de10_lite.qpf similarity index 100% rename from lab_06/src/02_counter_with_load/synthesis/de2_115.qpf rename to lab_06/src/02_counter_with_load/synthesis/de10_lite.qpf diff --git a/lab_06/src/02_counter_with_load/synthesis/de10_lite.qsf b/lab_06/src/02_counter_with_load/synthesis/de10_lite.qsf new file mode 100644 index 0000000..0d7ff21 --- /dev/null +++ b/lab_06/src/02_counter_with_load/synthesis/de10_lite.qsf @@ -0,0 +1,72 @@ +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 + +set_global_assignment -name TOP_LEVEL_ENTITY de10_lite + +set_global_assignment -name VERILOG_FILE de10_lite.v +set_global_assignment -name VERILOG_FILE ../cnt_load.v +set_global_assignment -name VERILOG_FILE ../../common/led7.v +set_global_assignment -name VERILOG_FILE ../../common/clk_divider.v + +set_global_assignment -name SDC_FILE de10_lite.sdc + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX* +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW* + +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_P11 -to CLOCK_50 + +#============================================================ +# KEY +#============================================================ +set_location_assignment PIN_B8 -to KEY[0] +set_location_assignment PIN_A7 -to KEY[1] + +#============================================================ +# HEX0 +#============================================================ + +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] + +#============================================================ +# HEX1 +#============================================================ + +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] + +#============================================================ +# SW +#============================================================ + +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] + + +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_file diff --git a/lab_06/src/02_counter_with_load/synthesis/de10_lite.sdc b/lab_06/src/02_counter_with_load/synthesis/de10_lite.sdc new file mode 100644 index 0000000..23e7d76 --- /dev/null +++ b/lab_06/src/02_counter_with_load/synthesis/de10_lite.sdc @@ -0,0 +1,11 @@ +create_clock -name clk50 -period 50MHz [get_ports CLOCK_50] +derive_clock_uncertainty +create_generated_clock -name clk_slow\ + -source [get_ports CLOCK_50]\ + [get_registers {clk_divider:clk_div|cnt_div[*]}] + +set_false_path -from * -to [get_ports {HEX0[*]}] +set_false_path -from * -to [get_ports {HEX1[*]}] + +set_false_path -from [get_ports {KEY[*]}] -to [all_clocks] +set_false_path -from [get_ports {SW[*]} ] -to [all_clocks] diff --git a/lab_06/src/02_counter_with_load/synthesis/de2_115.v b/lab_06/src/02_counter_with_load/synthesis/de10_lite.v similarity index 93% rename from lab_06/src/02_counter_with_load/synthesis/de2_115.v rename to lab_06/src/02_counter_with_load/synthesis/de10_lite.v index 6379596..a7fa767 100644 --- a/lab_06/src/02_counter_with_load/synthesis/de2_115.v +++ b/lab_06/src/02_counter_with_load/synthesis/de10_lite.v @@ -1,10 +1,10 @@ -module de2_115 +module de10_lite ( input CLOCK_50, input [1:0] KEY, input [7:0] SW, - output [6:0] HEX1, - output [6:0] HEX0 + output [7:0] HEX1, + output [7:0] HEX0 ); localparam CNT_W = 8; diff --git a/lab_06/src/02_counter_with_load/synthesis/de2_115.qsf b/lab_06/src/02_counter_with_load/synthesis/de2_115.qsf deleted file mode 100644 index c7c6b36..0000000 --- a/lab_06/src/02_counter_with_load/synthesis/de2_115.qsf +++ /dev/null @@ -1,98 +0,0 @@ -set_global_assignment -name DEVICE EP4CE115F29C7 -set_global_assignment -name FAMILY "Cyclone IV E" -set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 - -set_global_assignment -name TOP_LEVEL_ENTITY de2_115 - -set_global_assignment -name VERILOG_FILE de2_115.v -set_global_assignment -name VERILOG_FILE ../cnt_load.v -set_global_assignment -name VERILOG_FILE ../../common/led7.v -set_global_assignment -name VERILOG_FILE ../../common/clk_divider.v - -set_global_assignment -name SDC_FILE de2_115.sdc - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW* - -#============================================================ -# CLOCK -#============================================================ -set_location_assignment PIN_Y2 -to CLOCK_50 - -#============================================================ -# KEY -#============================================================ -set_location_assignment PIN_M23 -to KEY[0] -set_location_assignment PIN_M21 -to KEY[1] -#============================================================ -# SEG7 -#============================================================ -set_location_assignment PIN_G18 -to HEX0[0] -set_location_assignment PIN_F22 -to HEX0[1] -set_location_assignment PIN_E17 -to HEX0[2] -set_location_assignment PIN_L26 -to HEX0[3] -set_location_assignment PIN_L25 -to HEX0[4] -set_location_assignment PIN_J22 -to HEX0[5] -set_location_assignment PIN_H22 -to HEX0[6] -set_location_assignment PIN_M24 -to HEX1[0] -set_location_assignment PIN_Y22 -to HEX1[1] -set_location_assignment PIN_W21 -to HEX1[2] -set_location_assignment PIN_W22 -to HEX1[3] -set_location_assignment PIN_W25 -to HEX1[4] -set_location_assignment PIN_U23 -to HEX1[5] -set_location_assignment PIN_U24 -to HEX1[6] -set_location_assignment PIN_AA25 -to HEX2[0] -set_location_assignment PIN_AA26 -to HEX2[1] -set_location_assignment PIN_Y25 -to HEX2[2] -set_location_assignment PIN_W26 -to HEX2[3] -set_location_assignment PIN_Y26 -to HEX2[4] -set_location_assignment PIN_W27 -to HEX2[5] -set_location_assignment PIN_W28 -to HEX2[6] -set_location_assignment PIN_V21 -to HEX3[0] -set_location_assignment PIN_U21 -to HEX3[1] -set_location_assignment PIN_AB20 -to HEX3[2] -set_location_assignment PIN_AA21 -to HEX3[3] -set_location_assignment PIN_AD24 -to HEX3[4] -set_location_assignment PIN_AF23 -to HEX3[5] -set_location_assignment PIN_Y19 -to HEX3[6] -set_location_assignment PIN_AB19 -to HEX4[0] -set_location_assignment PIN_AA19 -to HEX4[1] -set_location_assignment PIN_AG21 -to HEX4[2] -set_location_assignment PIN_AH21 -to HEX4[3] -set_location_assignment PIN_AE19 -to HEX4[4] -set_location_assignment PIN_AF19 -to HEX4[5] -set_location_assignment PIN_AE18 -to HEX4[6] -set_location_assignment PIN_AD18 -to HEX5[0] -set_location_assignment PIN_AC18 -to HEX5[1] -set_location_assignment PIN_AB18 -to HEX5[2] -set_location_assignment PIN_AH19 -to HEX5[3] -set_location_assignment PIN_AG19 -to HEX5[4] -set_location_assignment PIN_AF18 -to HEX5[5] -set_location_assignment PIN_AH18 -to HEX5[6] -set_location_assignment PIN_AA17 -to HEX6[0] -set_location_assignment PIN_AB16 -to HEX6[1] -set_location_assignment PIN_AA16 -to HEX6[2] -set_location_assignment PIN_AB17 -to HEX6[3] -set_location_assignment PIN_AB15 -to HEX6[4] -set_location_assignment PIN_AA15 -to HEX6[5] -set_location_assignment PIN_AC17 -to HEX6[6] -set_location_assignment PIN_AD17 -to HEX7[0] -set_location_assignment PIN_AE17 -to HEX7[1] -set_location_assignment PIN_AG17 -to HEX7[2] -set_location_assignment PIN_AH17 -to HEX7[3] -set_location_assignment PIN_AF17 -to HEX7[4] -set_location_assignment PIN_AG18 -to HEX7[5] -set_location_assignment PIN_AA14 -to HEX7[6] -#============================================================ -# SW -#============================================================ -set_location_assignment PIN_AB28 -to SW[0] -set_location_assignment PIN_AC28 -to SW[1] -set_location_assignment PIN_AC27 -to SW[2] -set_location_assignment PIN_AD27 -to SW[3] -set_location_assignment PIN_AB27 -to SW[4] -set_location_assignment PIN_AC26 -to SW[5] -set_location_assignment PIN_AD26 -to SW[6] -set_location_assignment PIN_AB26 -to SW[7] diff --git a/lab_06/src/03_counter_updown/simulation/01_simulate_with_modelsim.sh b/lab_06/src/03_counter_updown/simulation/01_simulate_with_modelsim.sh old mode 100755 new mode 100644 diff --git a/lab_06/src/03_counter_updown/simulation/02_simulate_with_icarus.sh b/lab_06/src/03_counter_updown/simulation/02_simulate_with_icarus.sh old mode 100755 new mode 100644 diff --git a/lab_06/src/03_counter_updown/synthsis/de2_115.qpf b/lab_06/src/03_counter_updown/synthesis/de10_lite.qpf similarity index 100% rename from lab_06/src/03_counter_updown/synthsis/de2_115.qpf rename to lab_06/src/03_counter_updown/synthesis/de10_lite.qpf diff --git a/lab_06/src/03_counter_updown/synthesis/de10_lite.qsf b/lab_06/src/03_counter_updown/synthesis/de10_lite.qsf new file mode 100644 index 0000000..c5a7470 --- /dev/null +++ b/lab_06/src/03_counter_updown/synthesis/de10_lite.qsf @@ -0,0 +1,71 @@ +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 + +set_global_assignment -name TOP_LEVEL_ENTITY de10_lite + +set_global_assignment -name VERILOG_FILE de10_lite.v +set_global_assignment -name VERILOG_FILE ../cnt_updown.v +set_global_assignment -name VERILOG_FILE ../../common/led7.v +set_global_assignment -name VERILOG_FILE ../../common/clk_divider.v + +set_global_assignment -name SDC_FILE de10_lite.sdc + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX* +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW* +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_P11 -to CLOCK_50 + + +#============================================================ +# KEY +#============================================================ +set_location_assignment PIN_B8 -to KEY[0] + + +#============================================================ +# HEX0 +#============================================================ + +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] + +#============================================================ +# HEX1 +#============================================================ + +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] + +#============================================================ +# SW +#============================================================ + +set_location_assignment PIN_C10 -to SW[0] + + + +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_file +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Standard Edition" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top diff --git a/lab_06/src/03_counter_updown/synthesis/de10_lite.sdc b/lab_06/src/03_counter_updown/synthesis/de10_lite.sdc new file mode 100644 index 0000000..504ddb9 --- /dev/null +++ b/lab_06/src/03_counter_updown/synthesis/de10_lite.sdc @@ -0,0 +1,12 @@ +create_clock -name clk -period 50MHz [get_ports CLOCK_50] +derive_clock_uncertainty + +create_generated_clock -name clk_slow\ + -source [get_ports CLOCK_50]\ + [get_registers {clk_divider:clk_div|cnt_div[*]}] + +set_false_path -from * -to [get_ports {HEX0[*]}] +set_false_path -from * -to [get_ports {HEX1[*]}] + +set_false_path -from [get_ports {KEY[*]}] -to [all_clocks] +set_false_path -from [get_ports {SW[*]}] -to [all_clocks] diff --git a/lab_06/src/03_counter_updown/synthsis/de2_115.v b/lab_06/src/03_counter_updown/synthesis/de10_lite.v similarity index 92% rename from lab_06/src/03_counter_updown/synthsis/de2_115.v rename to lab_06/src/03_counter_updown/synthesis/de10_lite.v index 630fe22..ff43dc8 100644 --- a/lab_06/src/03_counter_updown/synthsis/de2_115.v +++ b/lab_06/src/03_counter_updown/synthesis/de10_lite.v @@ -1,10 +1,10 @@ -module de2_115 +module de10_lite ( input CLOCK_50, input [0:0] KEY, input [0:0] SW, - output [6:0] HEX1, - output [6:0] HEX0 + output [7:0] HEX1, + output [7:0] HEX0 ); localparam CNT_W = 8; diff --git a/lab_06/src/03_counter_updown/synthsis/de2_115.qsf b/lab_06/src/03_counter_updown/synthsis/de2_115.qsf deleted file mode 100644 index 563dd03..0000000 --- a/lab_06/src/03_counter_updown/synthsis/de2_115.qsf +++ /dev/null @@ -1,91 +0,0 @@ -set_global_assignment -name DEVICE EP4CE115F29C7 -set_global_assignment -name FAMILY "Cyclone IV E" -set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 - -set_global_assignment -name TOP_LEVEL_ENTITY de2_115 - -set_global_assignment -name VERILOG_FILE de2_115.v -set_global_assignment -name VERILOG_FILE ../cnt_updown.v -set_global_assignment -name VERILOG_FILE ../../common/led7.v -set_global_assignment -name VERILOG_FILE ../../common/clk_divider.v - -set_global_assignment -name SDC_FILE de2_115.sdc - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW* -#============================================================ -# CLOCK -#============================================================ -set_location_assignment PIN_Y2 -to CLOCK_50 - -#============================================================ -# KEY -#============================================================ -set_location_assignment PIN_M23 -to KEY[0] - -#============================================================ -# SEG7 -#============================================================ -set_location_assignment PIN_G18 -to HEX0[0] -set_location_assignment PIN_F22 -to HEX0[1] -set_location_assignment PIN_E17 -to HEX0[2] -set_location_assignment PIN_L26 -to HEX0[3] -set_location_assignment PIN_L25 -to HEX0[4] -set_location_assignment PIN_J22 -to HEX0[5] -set_location_assignment PIN_H22 -to HEX0[6] -set_location_assignment PIN_M24 -to HEX1[0] -set_location_assignment PIN_Y22 -to HEX1[1] -set_location_assignment PIN_W21 -to HEX1[2] -set_location_assignment PIN_W22 -to HEX1[3] -set_location_assignment PIN_W25 -to HEX1[4] -set_location_assignment PIN_U23 -to HEX1[5] -set_location_assignment PIN_U24 -to HEX1[6] -set_location_assignment PIN_AA25 -to HEX2[0] -set_location_assignment PIN_AA26 -to HEX2[1] -set_location_assignment PIN_Y25 -to HEX2[2] -set_location_assignment PIN_W26 -to HEX2[3] -set_location_assignment PIN_Y26 -to HEX2[4] -set_location_assignment PIN_W27 -to HEX2[5] -set_location_assignment PIN_W28 -to HEX2[6] -set_location_assignment PIN_V21 -to HEX3[0] -set_location_assignment PIN_U21 -to HEX3[1] -set_location_assignment PIN_AB20 -to HEX3[2] -set_location_assignment PIN_AA21 -to HEX3[3] -set_location_assignment PIN_AD24 -to HEX3[4] -set_location_assignment PIN_AF23 -to HEX3[5] -set_location_assignment PIN_Y19 -to HEX3[6] -set_location_assignment PIN_AB19 -to HEX4[0] -set_location_assignment PIN_AA19 -to HEX4[1] -set_location_assignment PIN_AG21 -to HEX4[2] -set_location_assignment PIN_AH21 -to HEX4[3] -set_location_assignment PIN_AE19 -to HEX4[4] -set_location_assignment PIN_AF19 -to HEX4[5] -set_location_assignment PIN_AE18 -to HEX4[6] -set_location_assignment PIN_AD18 -to HEX5[0] -set_location_assignment PIN_AC18 -to HEX5[1] -set_location_assignment PIN_AB18 -to HEX5[2] -set_location_assignment PIN_AH19 -to HEX5[3] -set_location_assignment PIN_AG19 -to HEX5[4] -set_location_assignment PIN_AF18 -to HEX5[5] -set_location_assignment PIN_AH18 -to HEX5[6] -set_location_assignment PIN_AA17 -to HEX6[0] -set_location_assignment PIN_AB16 -to HEX6[1] -set_location_assignment PIN_AA16 -to HEX6[2] -set_location_assignment PIN_AB17 -to HEX6[3] -set_location_assignment PIN_AB15 -to HEX6[4] -set_location_assignment PIN_AA15 -to HEX6[5] -set_location_assignment PIN_AC17 -to HEX6[6] -set_location_assignment PIN_AD17 -to HEX7[0] -set_location_assignment PIN_AE17 -to HEX7[1] -set_location_assignment PIN_AG17 -to HEX7[2] -set_location_assignment PIN_AH17 -to HEX7[3] -set_location_assignment PIN_AF17 -to HEX7[4] -set_location_assignment PIN_AG18 -to HEX7[5] -set_location_assignment PIN_AA14 -to HEX7[6] -#============================================================ -# SW -#============================================================ -set_location_assignment PIN_AB28 -to SW[0] - diff --git a/lab_06/src/03_counter_updown/synthsis/de2_115.sdc b/lab_06/src/03_counter_updown/synthsis/de2_115.sdc deleted file mode 100644 index 01192ab..0000000 --- a/lab_06/src/03_counter_updown/synthsis/de2_115.sdc +++ /dev/null @@ -1,8 +0,0 @@ -create_clock -period 50MHz [get_ports CLOCK_50] - -derive_clock_uncertainty - -set_false_path -from * -to [get_ports {HEX0[*]}] -set_false_path -from * -to [get_ports {HEX1[*]}] - -set_false_path -from [get_ports {KEY[*]}] -to [all_clocks] diff --git a/lab_06/src/04_counter_divider/cnt_div.v b/lab_06/src/04_counter_divider/cnt_div.v index edca999..24bdec6 100644 --- a/lab_06/src/04_counter_divider/cnt_div.v +++ b/lab_06/src/04_counter_divider/cnt_div.v @@ -24,7 +24,7 @@ module cnt_div cnt <= cnt + 1'b1; end - assign clk_out = (cnt == 0) ? 1 : 0; + assign clk_out = (cnt == 0) ? 1'b1 : 1'b0; endmodule // cnt_div diff --git a/lab_06/src/04_counter_divider/simulation/01_simulate_with_modelsim.sh b/lab_06/src/04_counter_divider/simulation/01_simulate_with_modelsim.sh old mode 100755 new mode 100644 diff --git a/lab_06/src/04_counter_divider/simulation/02_simulate_with_icarus.sh b/lab_06/src/04_counter_divider/simulation/02_simulate_with_icarus.sh old mode 100755 new mode 100644 diff --git a/lab_06/src/04_counter_divider/synthesis/db/de10_lite.db_info b/lab_06/src/04_counter_divider/synthesis/db/de10_lite.db_info new file mode 100644 index 0000000..b69d00e --- /dev/null +++ b/lab_06/src/04_counter_divider/synthesis/db/de10_lite.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition +Version_Index = 419482368 +Creation_Time = Wed Mar 28 18:51:46 2018 diff --git a/lab_06/src/04_counter_divider/synthesis/db/de10_lite.sld_design_entry.sci b/lab_06/src/04_counter_divider/synthesis/db/de10_lite.sld_design_entry.sci new file mode 100644 index 0000000..3dd3ad2 Binary files /dev/null and b/lab_06/src/04_counter_divider/synthesis/db/de10_lite.sld_design_entry.sci differ diff --git a/lab_06/src/04_counter_divider/synthesis/db/de10_lite.tmw_info b/lab_06/src/04_counter_divider/synthesis/db/de10_lite.tmw_info new file mode 100644 index 0000000..e793cdf --- /dev/null +++ b/lab_06/src/04_counter_divider/synthesis/db/de10_lite.tmw_info @@ -0,0 +1,6 @@ +start_full_compilation:s:00:00:25 +start_analysis_synthesis:s:00:00:09-start_full_compilation +start_analysis_elaboration:s-start_full_compilation +start_fitter:s:00:00:09-start_full_compilation +start_assembler:s:00:00:03-start_full_compilation +start_timing_analyzer:s:00:00:04-start_full_compilation diff --git a/lab_06/src/04_counter_divider/synthesis/de2_115.qpf b/lab_06/src/04_counter_divider/synthesis/de10_lite.qpf similarity index 100% rename from lab_06/src/04_counter_divider/synthesis/de2_115.qpf rename to lab_06/src/04_counter_divider/synthesis/de10_lite.qpf diff --git a/lab_06/src/04_counter_divider/synthesis/de10_lite.qsf b/lab_06/src/04_counter_divider/synthesis/de10_lite.qsf new file mode 100644 index 0000000..df57ca7 --- /dev/null +++ b/lab_06/src/04_counter_divider/synthesis/de10_lite.qsf @@ -0,0 +1,88 @@ +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 + +set_global_assignment -name TOP_LEVEL_ENTITY de10_lite + + +set_global_assignment -name VERILOG_FILE de10_lite.v +set_global_assignment -name VERILOG_FILE ../cnt_div.v +set_global_assignment -name VERILOG_FILE ../../01_counter_simple/simple_counter.v +set_global_assignment -name VERILOG_FILE ../../common/led7.v +set_global_assignment -name VERILOG_FILE ../../common/clk_divider.v + +set_global_assignment -name SDC_FILE de10_lite.sdc + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX* +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY* + +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_P11 -to CLOCK_50 + +#============================================================ +# KEY +#============================================================ +set_location_assignment PIN_B8 -to KEY[0] + +#============================================================ +# HEX0 +#============================================================ + +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] + +#============================================================ +# HEX1 +#============================================================ + +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] + +#============================================================ +# HEX2 +#============================================================ + +set_location_assignment PIN_B20 -to HEX2[0] +set_location_assignment PIN_A20 -to HEX2[1] +set_location_assignment PIN_B19 -to HEX2[2] +set_location_assignment PIN_A21 -to HEX2[3] +set_location_assignment PIN_B21 -to HEX2[4] +set_location_assignment PIN_C22 -to HEX2[5] +set_location_assignment PIN_B22 -to HEX2[6] +set_location_assignment PIN_A19 -to HEX2[7] + +#============================================================ +# HEX3 +#============================================================ + +set_location_assignment PIN_F21 -to HEX3[0] +set_location_assignment PIN_E22 -to HEX3[1] +set_location_assignment PIN_E21 -to HEX3[2] +set_location_assignment PIN_C19 -to HEX3[3] +set_location_assignment PIN_C20 -to HEX3[4] +set_location_assignment PIN_D19 -to HEX3[5] +set_location_assignment PIN_E17 -to HEX3[6] +set_location_assignment PIN_D22 -to HEX3[7] + +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_file + +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Standard Edition" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/lab_06/src/04_counter_divider/synthesis/de10_lite.qws b/lab_06/src/04_counter_divider/synthesis/de10_lite.qws new file mode 100644 index 0000000..0ed3a18 Binary files /dev/null and b/lab_06/src/04_counter_divider/synthesis/de10_lite.qws differ diff --git a/lab_06/src/04_counter_divider/synthesis/de10_lite.sdc b/lab_06/src/04_counter_divider/synthesis/de10_lite.sdc new file mode 100644 index 0000000..8ea71b1 --- /dev/null +++ b/lab_06/src/04_counter_divider/synthesis/de10_lite.sdc @@ -0,0 +1,15 @@ +create_clock -name clk -period 50MHz [get_ports CLOCK_50] + +derive_clock_uncertainty + +create_generated_clock -name clk_div_slow \ + -source [get_ports CLOCK_50] \ + [get_registers {clk_divider:clk_div1|cnt_div[*]}] + + +set_false_path -from * -to [get_ports {HEX0[*]}] +set_false_path -from * -to [get_ports {HEX1[*]}] +set_false_path -from * -to [get_ports {HEX2[*]}] +set_false_path -from * -to [get_ports {HEX3[*]}] + +set_false_path -from [get_ports {KEY[*]}] -to [all_clocks] diff --git a/lab_06/src/04_counter_divider/synthesis/de2_115.v b/lab_06/src/04_counter_divider/synthesis/de10_lite.v similarity index 81% rename from lab_06/src/04_counter_divider/synthesis/de2_115.v rename to lab_06/src/04_counter_divider/synthesis/de10_lite.v index 9961e6a..2fbc2cc 100644 --- a/lab_06/src/04_counter_divider/synthesis/de2_115.v +++ b/lab_06/src/04_counter_divider/synthesis/de10_lite.v @@ -1,12 +1,12 @@ -module de2_115 +module de10_lite ( input CLOCK_50, input [0:0] KEY, - output [6:0] HEX3, - output [6:0] HEX2, - output [6:0] HEX1, - output [6:0] HEX0 + output [7:0] HEX3, + output [7:0] HEX2, + output [7:0] HEX1, + output [7:0] HEX0 ); localparam CNT_W = 8; @@ -14,12 +14,13 @@ module de2_115 wire clk_slow; wire clk_global; wire clk_div_slow; + wire clk_out_div; wire [CNT_W - 1:0] cnt_to_seg7_fast; wire [CNT_W - 1:0] cnt_to_seg7_slow; //Clk divide for demonstration - clk_divider #(.WIDTH(24)) clk_div + clk_divider #(.WIDTH(24)) clk_div1 ( .clk_in ( CLOCK_50 ), .rst_n ( KEY[0] ), @@ -35,8 +36,8 @@ module de2_115 Clock divide for example ------------------------------ */ - cnt_div #(.DIV_CNT(16)) - div + cnt_div #(.DIV_CNT(16)) clk_div2 + ( .clk_in ( clk_global ), .rst_n ( KEY[0] ), @@ -46,7 +47,7 @@ module de2_115 global global_net2 ( .in ( clk_out_div ), - .out ( clk_div_slow ) + .out ( clk_div_slow ) ); @@ -54,14 +55,14 @@ module de2_115 ( .clk ( clk_global ), .rst_n ( KEY[0] ), - .cnt ( cnt_to_seg7_fast), + .cnt ( cnt_to_seg7_fast) ); simple_counter #(.WIDTH(CNT_W)) cnt_slow ( .clk ( clk_div_slow ), .rst_n ( KEY[0] ), - .cnt ( cnt_to_seg7_slow), + .cnt ( cnt_to_seg7_slow) ); diff --git a/lab_06/src/04_counter_divider/synthesis/de2_115.qsf b/lab_06/src/04_counter_divider/synthesis/de2_115.qsf deleted file mode 100644 index 8a4872f..0000000 --- a/lab_06/src/04_counter_divider/synthesis/de2_115.qsf +++ /dev/null @@ -1,89 +0,0 @@ -set_global_assignment -name DEVICE EP4CE115F29C7 -set_global_assignment -name FAMILY "Cyclone IV E" -set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 - -set_global_assignment -name TOP_LEVEL_ENTITY de2_115 - - -set_global_assignment -name VERILOG_FILE de2_115.v -set_global_assignment -name VERILOG_FILE ../cnt_div.v -set_global_assignment -name VERILOG_FILE ../../01_counter_simple/simple_counter.v -set_global_assignment -name VERILOG_FILE ../../common/led7.v -set_global_assignment -name VERILOG_FILE ../../common/clk_divider.v - -set_global_assignment -name SDC_FILE de2_115.sdc - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY* - -#============================================================ -# CLOCK -#============================================================ -set_location_assignment PIN_Y2 -to CLOCK_50 - -#============================================================ -# KEY -#============================================================ -set_location_assignment PIN_M23 -to KEY[0] - -#============================================================ -# SEG7 -#============================================================ -set_location_assignment PIN_G18 -to HEX0[0] -set_location_assignment PIN_F22 -to HEX0[1] -set_location_assignment PIN_E17 -to HEX0[2] -set_location_assignment PIN_L26 -to HEX0[3] -set_location_assignment PIN_L25 -to HEX0[4] -set_location_assignment PIN_J22 -to HEX0[5] -set_location_assignment PIN_H22 -to HEX0[6] -set_location_assignment PIN_M24 -to HEX1[0] -set_location_assignment PIN_Y22 -to HEX1[1] -set_location_assignment PIN_W21 -to HEX1[2] -set_location_assignment PIN_W22 -to HEX1[3] -set_location_assignment PIN_W25 -to HEX1[4] -set_location_assignment PIN_U23 -to HEX1[5] -set_location_assignment PIN_U24 -to HEX1[6] -set_location_assignment PIN_AA25 -to HEX2[0] -set_location_assignment PIN_AA26 -to HEX2[1] -set_location_assignment PIN_Y25 -to HEX2[2] -set_location_assignment PIN_W26 -to HEX2[3] -set_location_assignment PIN_Y26 -to HEX2[4] -set_location_assignment PIN_W27 -to HEX2[5] -set_location_assignment PIN_W28 -to HEX2[6] -set_location_assignment PIN_V21 -to HEX3[0] -set_location_assignment PIN_U21 -to HEX3[1] -set_location_assignment PIN_AB20 -to HEX3[2] -set_location_assignment PIN_AA21 -to HEX3[3] -set_location_assignment PIN_AD24 -to HEX3[4] -set_location_assignment PIN_AF23 -to HEX3[5] -set_location_assignment PIN_Y19 -to HEX3[6] -set_location_assignment PIN_AB19 -to HEX4[0] -set_location_assignment PIN_AA19 -to HEX4[1] -set_location_assignment PIN_AG21 -to HEX4[2] -set_location_assignment PIN_AH21 -to HEX4[3] -set_location_assignment PIN_AE19 -to HEX4[4] -set_location_assignment PIN_AF19 -to HEX4[5] -set_location_assignment PIN_AE18 -to HEX4[6] -set_location_assignment PIN_AD18 -to HEX5[0] -set_location_assignment PIN_AC18 -to HEX5[1] -set_location_assignment PIN_AB18 -to HEX5[2] -set_location_assignment PIN_AH19 -to HEX5[3] -set_location_assignment PIN_AG19 -to HEX5[4] -set_location_assignment PIN_AF18 -to HEX5[5] -set_location_assignment PIN_AH18 -to HEX5[6] -set_location_assignment PIN_AA17 -to HEX6[0] -set_location_assignment PIN_AB16 -to HEX6[1] -set_location_assignment PIN_AA16 -to HEX6[2] -set_location_assignment PIN_AB17 -to HEX6[3] -set_location_assignment PIN_AB15 -to HEX6[4] -set_location_assignment PIN_AA15 -to HEX6[5] -set_location_assignment PIN_AC17 -to HEX6[6] -set_location_assignment PIN_AD17 -to HEX7[0] -set_location_assignment PIN_AE17 -to HEX7[1] -set_location_assignment PIN_AG17 -to HEX7[2] -set_location_assignment PIN_AH17 -to HEX7[3] -set_location_assignment PIN_AF17 -to HEX7[4] -set_location_assignment PIN_AG18 -to HEX7[5] -set_location_assignment PIN_AA14 -to HEX7[6] - diff --git a/lab_06/src/05_counter_pwm/simulation/01_simulate_with_modelsim.sh b/lab_06/src/05_counter_pwm/simulation/01_simulate_with_modelsim.sh old mode 100755 new mode 100644 diff --git a/lab_06/src/05_counter_pwm/simulation/02_simulate_with_icarus.sh b/lab_06/src/05_counter_pwm/simulation/02_simulate_with_icarus.sh old mode 100755 new mode 100644 diff --git a/lab_06/src/05_counter_pwm/synthesis/de2_115.qpf b/lab_06/src/05_counter_pwm/synthesis/de10_lite.qpf similarity index 100% rename from lab_06/src/05_counter_pwm/synthesis/de2_115.qpf rename to lab_06/src/05_counter_pwm/synthesis/de10_lite.qpf diff --git a/lab_06/src/05_counter_pwm/synthesis/de10_lite.qsf b/lab_06/src/05_counter_pwm/synthesis/de10_lite.qsf new file mode 100644 index 0000000..345aca9 --- /dev/null +++ b/lab_06/src/05_counter_pwm/synthesis/de10_lite.qsf @@ -0,0 +1,87 @@ +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 + +set_global_assignment -name TOP_LEVEL_ENTITY de10_lite + +set_global_assignment -name VERILOG_FILE de10_lite.v +set_global_assignment -name VERILOG_FILE ../pwm.v +set_global_assignment -name VERILOG_FILE ../../common/led7.v +set_global_assignment -name VERILOG_FILE ../../common/clk_divider.v + +set_global_assignment -name SDC_FILE de10_lite.sdc + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX* +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW* +#============================================================ +# CLOCK +#============================================================ + +set_location_assignment PIN_P11 -to CLOCK_50 + +#============================================================ +# KEY +#============================================================ + +set_location_assignment PIN_B8 -to KEY[0] +set_location_assignment PIN_A7 -to KEY[1] + +#============================================================ +# HEX0 +#============================================================ + +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] + +#============================================================ +# HEX1 +#============================================================ + +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] +#============================================================ +# SW +#============================================================ + +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] + +#============================================================ +# LEDR +#============================================================ + +set_location_assignment PIN_A8 -to LEDR[0] + + +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_file +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Standard Edition" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top diff --git a/lab_06/src/05_counter_pwm/synthesis/de2_115.sdc b/lab_06/src/05_counter_pwm/synthesis/de10_lite.sdc similarity index 54% rename from lab_06/src/05_counter_pwm/synthesis/de2_115.sdc rename to lab_06/src/05_counter_pwm/synthesis/de10_lite.sdc index 69d6605..e2073b9 100644 --- a/lab_06/src/05_counter_pwm/synthesis/de2_115.sdc +++ b/lab_06/src/05_counter_pwm/synthesis/de10_lite.sdc @@ -1,7 +1,11 @@ -create_clock -period 50MHz [get_ports CLOCK_50] +create_clock -name clk -period 50MHz [get_ports CLOCK_50] derive_clock_uncertainty +create_generated_clock -name clk_slow \ + -source [get_ports CLOCK_50] \ + [get_registers {clk_divider:clk_div|cnt_div[*]}] + set_false_path -from * -to [get_ports {HEX0[*]}] set_false_path -from * -to [get_ports {HEX1[*]}] set_false_path -from * -to [get_ports {LEDR[*]}] diff --git a/lab_06/src/05_counter_pwm/synthesis/de2_115.v b/lab_06/src/05_counter_pwm/synthesis/de10_lite.v similarity index 93% rename from lab_06/src/05_counter_pwm/synthesis/de2_115.v rename to lab_06/src/05_counter_pwm/synthesis/de10_lite.v index 92dde30..7a6b2cc 100644 --- a/lab_06/src/05_counter_pwm/synthesis/de2_115.v +++ b/lab_06/src/05_counter_pwm/synthesis/de10_lite.v @@ -1,4 +1,4 @@ -module de2_115 +module de10_lite ( input CLOCK_50, input [0:0] KEY, @@ -7,8 +7,8 @@ module de2_115 output [0:0] LEDR, - output [6:0] HEX1, - output [6:0] HEX0 + output [7:0] HEX1, + output [7:0] HEX0 ); localparam CNT_W = 8; diff --git a/lab_06/src/05_counter_pwm/synthesis/de2_115.qsf b/lab_06/src/05_counter_pwm/synthesis/de2_115.qsf deleted file mode 100644 index c954beb..0000000 --- a/lab_06/src/05_counter_pwm/synthesis/de2_115.qsf +++ /dev/null @@ -1,107 +0,0 @@ -set_global_assignment -name DEVICE EP4CE115F29C7 -set_global_assignment -name FAMILY "Cyclone IV E" -set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 - -set_global_assignment -name TOP_LEVEL_ENTITY de2_115 - -set_global_assignment -name VERILOG_FILE de2_115.v -set_global_assignment -name VERILOG_FILE ../pwm.v -set_global_assignment -name VERILOG_FILE ../../common/led7.v -set_global_assignment -name VERILOG_FILE ../../common/clk_divider.v - -set_global_assignment -name SDC_FILE de2_115.sdc - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK* -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW* -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR* - -#============================================================ -# CLOCK -#============================================================ -set_location_assignment PIN_Y2 -to CLOCK_50 - -#============================================================ -# KEY -#============================================================ -set_location_assignment PIN_M23 -to KEY[0] -#============================================================ -# LED -#============================================================ -set_location_assignment PIN_G19 -to LEDR[0] -#============================================================ -# SW -#============================================================ -set_location_assignment PIN_AB28 -to SW[0] -set_location_assignment PIN_AC28 -to SW[1] -set_location_assignment PIN_AC27 -to SW[2] -set_location_assignment PIN_AD27 -to SW[3] -set_location_assignment PIN_AB27 -to SW[4] -set_location_assignment PIN_AC26 -to SW[5] -set_location_assignment PIN_AD26 -to SW[6] -set_location_assignment PIN_AB26 -to SW[7] - -#============================================================ -# SEG7 -#============================================================ -set_location_assignment PIN_G18 -to HEX0[0] -set_location_assignment PIN_F22 -to HEX0[1] -set_location_assignment PIN_E17 -to HEX0[2] -set_location_assignment PIN_L26 -to HEX0[3] -set_location_assignment PIN_L25 -to HEX0[4] -set_location_assignment PIN_J22 -to HEX0[5] -set_location_assignment PIN_H22 -to HEX0[6] -set_location_assignment PIN_M24 -to HEX1[0] -set_location_assignment PIN_Y22 -to HEX1[1] -set_location_assignment PIN_W21 -to HEX1[2] -set_location_assignment PIN_W22 -to HEX1[3] -set_location_assignment PIN_W25 -to HEX1[4] -set_location_assignment PIN_U23 -to HEX1[5] -set_location_assignment PIN_U24 -to HEX1[6] -set_location_assignment PIN_AA25 -to HEX2[0] -set_location_assignment PIN_AA26 -to HEX2[1] -set_location_assignment PIN_Y25 -to HEX2[2] -set_location_assignment PIN_W26 -to HEX2[3] -set_location_assignment PIN_Y26 -to HEX2[4] -set_location_assignment PIN_W27 -to HEX2[5] -set_location_assignment PIN_W28 -to HEX2[6] -set_location_assignment PIN_V21 -to HEX3[0] -set_location_assignment PIN_U21 -to HEX3[1] -set_location_assignment PIN_AB20 -to HEX3[2] -set_location_assignment PIN_AA21 -to HEX3[3] -set_location_assignment PIN_AD24 -to HEX3[4] -set_location_assignment PIN_AF23 -to HEX3[5] -set_location_assignment PIN_Y19 -to HEX3[6] -set_location_assignment PIN_AB19 -to HEX4[0] -set_location_assignment PIN_AA19 -to HEX4[1] -set_location_assignment PIN_AG21 -to HEX4[2] -set_location_assignment PIN_AH21 -to HEX4[3] -set_location_assignment PIN_AE19 -to HEX4[4] -set_location_assignment PIN_AF19 -to HEX4[5] -set_location_assignment PIN_AE18 -to HEX4[6] -set_location_assignment PIN_AD18 -to HEX5[0] -set_location_assignment PIN_AC18 -to HEX5[1] -set_location_assignment PIN_AB18 -to HEX5[2] -set_location_assignment PIN_AH19 -to HEX5[3] -set_location_assignment PIN_AG19 -to HEX5[4] -set_location_assignment PIN_AF18 -to HEX5[5] -set_location_assignment PIN_AH18 -to HEX5[6] -set_location_assignment PIN_AA17 -to HEX6[0] -set_location_assignment PIN_AB16 -to HEX6[1] -set_location_assignment PIN_AA16 -to HEX6[2] -set_location_assignment PIN_AB17 -to HEX6[3] -set_location_assignment PIN_AB15 -to HEX6[4] -set_location_assignment PIN_AA15 -to HEX6[5] -set_location_assignment PIN_AC17 -to HEX6[6] -set_location_assignment PIN_AD17 -to HEX7[0] -set_location_assignment PIN_AE17 -to HEX7[1] -set_location_assignment PIN_AG17 -to HEX7[2] -set_location_assignment PIN_AH17 -to HEX7[3] -set_location_assignment PIN_AF17 -to HEX7[4] -set_location_assignment PIN_AG18 -to HEX7[5] -set_location_assignment PIN_AA14 -to HEX7[6] - diff --git a/lab_06/src/06_shift_reg/simulation/01_simulate_with_modelsim.sh b/lab_06/src/06_shift_reg/simulation/01_simulate_with_modelsim.sh old mode 100755 new mode 100644 diff --git a/lab_06/src/06_shift_reg/simulation/02_simulate_with_icarus.sh b/lab_06/src/06_shift_reg/simulation/02_simulate_with_icarus.sh old mode 100755 new mode 100644 diff --git a/lab_06/src/06_shift_reg/synthesis/de2_115.qpf b/lab_06/src/06_shift_reg/synthesis/de10_lite.qpf similarity index 100% rename from lab_06/src/06_shift_reg/synthesis/de2_115.qpf rename to lab_06/src/06_shift_reg/synthesis/de10_lite.qpf diff --git a/lab_06/src/06_shift_reg/synthesis/de10_lite.qsf b/lab_06/src/06_shift_reg/synthesis/de10_lite.qsf new file mode 100644 index 0000000..efec20a --- /dev/null +++ b/lab_06/src/06_shift_reg/synthesis/de10_lite.qsf @@ -0,0 +1,87 @@ +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 + + +set_global_assignment -name TOP_LEVEL_ENTITY de10_lite + +set_global_assignment -name VERILOG_FILE de10_lite.v +set_global_assignment -name VERILOG_FILE ../shift_reg.v +set_global_assignment -name VERILOG_FILE ../../common/led7.v +set_global_assignment -name VERILOG_FILE ../../common/clk_divider.v + +set_global_assignment -name SDC_FILE de10_lite.sdc + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX* +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR* + +#============================================================ +# CLOCK +#============================================================ + +set_location_assignment PIN_P11 -to CLOCK_50 + +#============================================================ +# KEY +#============================================================ + +set_location_assignment PIN_B8 -to KEY[0] +set_location_assignment PIN_A7 -to KEY[1] + +#============================================================ +# HEX0 +#============================================================ + +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] + +#============================================================ +# HEX1 +#============================================================ + +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] + +#============================================================ +# SW +#============================================================ + +set_location_assignment PIN_C10 -to SW[0] + +#============================================================ +# LEDR +#============================================================ + +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] + +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_file + +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Standard Edition" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top \ No newline at end of file diff --git a/lab_06/src/06_shift_reg/synthesis/de2_115.sdc b/lab_06/src/06_shift_reg/synthesis/de10_lite.sdc similarity index 54% rename from lab_06/src/06_shift_reg/synthesis/de2_115.sdc rename to lab_06/src/06_shift_reg/synthesis/de10_lite.sdc index 69d6605..e2073b9 100644 --- a/lab_06/src/06_shift_reg/synthesis/de2_115.sdc +++ b/lab_06/src/06_shift_reg/synthesis/de10_lite.sdc @@ -1,7 +1,11 @@ -create_clock -period 50MHz [get_ports CLOCK_50] +create_clock -name clk -period 50MHz [get_ports CLOCK_50] derive_clock_uncertainty +create_generated_clock -name clk_slow \ + -source [get_ports CLOCK_50] \ + [get_registers {clk_divider:clk_div|cnt_div[*]}] + set_false_path -from * -to [get_ports {HEX0[*]}] set_false_path -from * -to [get_ports {HEX1[*]}] set_false_path -from * -to [get_ports {LEDR[*]}] diff --git a/lab_06/src/06_shift_reg/synthesis/de2_115.v b/lab_06/src/06_shift_reg/synthesis/de10_lite.v similarity index 69% rename from lab_06/src/06_shift_reg/synthesis/de2_115.v rename to lab_06/src/06_shift_reg/synthesis/de10_lite.v index 58eb670..05f8679 100644 --- a/lab_06/src/06_shift_reg/synthesis/de2_115.v +++ b/lab_06/src/06_shift_reg/synthesis/de10_lite.v @@ -1,26 +1,27 @@ -module de2_115 +module de10_lite ( input CLOCK_50, input [1:0] KEY, input [0:0] SW, + + output [9:0] LEDR, - output [7:0] LEDR, - output [0:0] LEDG, - - output [6:0] HEX1, - output [6:0] HEX0 + output [7:0] HEX1, + output [7:0] HEX0 ); - - localparam CNT_W = 8; + + localparam CNT_W = 8, + MAX_LED = 10; wire clk_slow; wire clk_global; wire [CNT_W - 1:0] cnt_to_seg7; - - assign LEDR = cnt_to_seg7; - - //Set WIDTH=18 for demostration this example + + assign LEDR[CNT_W - 1:0] = cnt_to_seg7; + assign LEDR[MAX_LED - 2: CNT_W] = {MAX_LED-CNT_W-1{1'b0}}; + + //Set WIDTH=18 for demostration this example clk_divider #(.WIDTH(25)) clk_div ( .clk_in ( CLOCK_50 ), @@ -41,7 +42,7 @@ module de2_115 .data_in ( KEY[1] ), .shift_en ( SW ), .data_out ( cnt_to_seg7 ), - .serial_out( LEDG ) + .serial_out( LEDR[9] ) ); diff --git a/lab_06/src/06_shift_reg/synthesis/de2_115.qsf b/lab_06/src/06_shift_reg/synthesis/de2_115.qsf deleted file mode 100644 index a7d9bae..0000000 --- a/lab_06/src/06_shift_reg/synthesis/de2_115.qsf +++ /dev/null @@ -1,117 +0,0 @@ -set_global_assignment -name DEVICE EP4CE115F29C7 -set_global_assignment -name FAMILY "Cyclone IV E" -set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 - -set_global_assignment -name TOP_LEVEL_ENTITY de2_115 - -set_global_assignment -name VERILOG_FILE de2_115.v -set_global_assignment -name VERILOG_FILE ../shift_reg.v -set_global_assignment -name VERILOG_FILE ../../common/led7.v -set_global_assignment -name VERILOG_FILE ../../common/clk_divider.v - -set_global_assignment -name SDC_FILE de2_115.sdc - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK* -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW* -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR* -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG* -#============================================================ -# CLOCK -#============================================================ -set_location_assignment PIN_Y2 -to CLOCK_50 - -#============================================================ -# KEY -#============================================================ -set_location_assignment PIN_M23 -to KEY[0] -set_location_assignment PIN_M21 -to KEY[1] -#============================================================ -# LED -#============================================================ -set_location_assignment PIN_G19 -to LEDR[0] -set_location_assignment PIN_F19 -to LEDR[1] -set_location_assignment PIN_E19 -to LEDR[2] -set_location_assignment PIN_F21 -to LEDR[3] -set_location_assignment PIN_F18 -to LEDR[4] -set_location_assignment PIN_E18 -to LEDR[5] -set_location_assignment PIN_J19 -to LEDR[6] -set_location_assignment PIN_H19 -to LEDR[7] -set_location_assignment PIN_J17 -to LEDR[8] - -set_location_assignment PIN_E21 -to LEDG[0] -#============================================================ -# SW -#============================================================ -set_location_assignment PIN_AB28 -to SW[0] -set_location_assignment PIN_AC28 -to SW[1] -set_location_assignment PIN_AC27 -to SW[2] -set_location_assignment PIN_AD27 -to SW[3] -set_location_assignment PIN_AB27 -to SW[4] -set_location_assignment PIN_AC26 -to SW[5] -set_location_assignment PIN_AD26 -to SW[6] -set_location_assignment PIN_AB26 -to SW[7] - -#============================================================ -# SEG7 -#============================================================ -set_location_assignment PIN_G18 -to HEX0[0] -set_location_assignment PIN_F22 -to HEX0[1] -set_location_assignment PIN_E17 -to HEX0[2] -set_location_assignment PIN_L26 -to HEX0[3] -set_location_assignment PIN_L25 -to HEX0[4] -set_location_assignment PIN_J22 -to HEX0[5] -set_location_assignment PIN_H22 -to HEX0[6] -set_location_assignment PIN_M24 -to HEX1[0] -set_location_assignment PIN_Y22 -to HEX1[1] -set_location_assignment PIN_W21 -to HEX1[2] -set_location_assignment PIN_W22 -to HEX1[3] -set_location_assignment PIN_W25 -to HEX1[4] -set_location_assignment PIN_U23 -to HEX1[5] -set_location_assignment PIN_U24 -to HEX1[6] -set_location_assignment PIN_AA25 -to HEX2[0] -set_location_assignment PIN_AA26 -to HEX2[1] -set_location_assignment PIN_Y25 -to HEX2[2] -set_location_assignment PIN_W26 -to HEX2[3] -set_location_assignment PIN_Y26 -to HEX2[4] -set_location_assignment PIN_W27 -to HEX2[5] -set_location_assignment PIN_W28 -to HEX2[6] -set_location_assignment PIN_V21 -to HEX3[0] -set_location_assignment PIN_U21 -to HEX3[1] -set_location_assignment PIN_AB20 -to HEX3[2] -set_location_assignment PIN_AA21 -to HEX3[3] -set_location_assignment PIN_AD24 -to HEX3[4] -set_location_assignment PIN_AF23 -to HEX3[5] -set_location_assignment PIN_Y19 -to HEX3[6] -set_location_assignment PIN_AB19 -to HEX4[0] -set_location_assignment PIN_AA19 -to HEX4[1] -set_location_assignment PIN_AG21 -to HEX4[2] -set_location_assignment PIN_AH21 -to HEX4[3] -set_location_assignment PIN_AE19 -to HEX4[4] -set_location_assignment PIN_AF19 -to HEX4[5] -set_location_assignment PIN_AE18 -to HEX4[6] -set_location_assignment PIN_AD18 -to HEX5[0] -set_location_assignment PIN_AC18 -to HEX5[1] -set_location_assignment PIN_AB18 -to HEX5[2] -set_location_assignment PIN_AH19 -to HEX5[3] -set_location_assignment PIN_AG19 -to HEX5[4] -set_location_assignment PIN_AF18 -to HEX5[5] -set_location_assignment PIN_AH18 -to HEX5[6] -set_location_assignment PIN_AA17 -to HEX6[0] -set_location_assignment PIN_AB16 -to HEX6[1] -set_location_assignment PIN_AA16 -to HEX6[2] -set_location_assignment PIN_AB17 -to HEX6[3] -set_location_assignment PIN_AB15 -to HEX6[4] -set_location_assignment PIN_AA15 -to HEX6[5] -set_location_assignment PIN_AC17 -to HEX6[6] -set_location_assignment PIN_AD17 -to HEX7[0] -set_location_assignment PIN_AE17 -to HEX7[1] -set_location_assignment PIN_AG17 -to HEX7[2] -set_location_assignment PIN_AH17 -to HEX7[3] -set_location_assignment PIN_AF17 -to HEX7[4] -set_location_assignment PIN_AG18 -to HEX7[5] -set_location_assignment PIN_AA14 -to HEX7[6] diff --git a/lab_06/src/07_lfsr/simulation/01_simulate_with_modelsim.sh b/lab_06/src/07_lfsr/simulation/01_simulate_with_modelsim.sh old mode 100755 new mode 100644 diff --git a/lab_06/src/07_lfsr/simulation/02_simulate_with_icarus.sh b/lab_06/src/07_lfsr/simulation/02_simulate_with_icarus.sh old mode 100755 new mode 100644 diff --git a/lab_06/src/07_lfsr/synthesis/de2_115.qpf b/lab_06/src/07_lfsr/synthesis/de10_lite.qpf similarity index 100% rename from lab_06/src/07_lfsr/synthesis/de2_115.qpf rename to lab_06/src/07_lfsr/synthesis/de10_lite.qpf diff --git a/lab_06/src/07_lfsr/synthesis/de10_lite.qsf b/lab_06/src/07_lfsr/synthesis/de10_lite.qsf new file mode 100644 index 0000000..eb339cb --- /dev/null +++ b/lab_06/src/07_lfsr/synthesis/de10_lite.qsf @@ -0,0 +1,82 @@ +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 + + +set_global_assignment -name TOP_LEVEL_ENTITY de10_lite + +set_global_assignment -name VERILOG_FILE de10_lite.v +set_global_assignment -name VERILOG_FILE ../lfsr.v +set_global_assignment -name VERILOG_FILE ../../common/led7.v +set_global_assignment -name VERILOG_FILE ../../common/clk_divider.v + +set_global_assignment -name SDC_FILE de10_lite.sdc + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX* +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR* + +#============================================================ +# CLOCK +#============================================================ + +set_location_assignment PIN_P11 -to CLOCK_50 + +#============================================================ +# KEY +#============================================================ + +set_location_assignment PIN_B8 -to KEY[0] + +#============================================================ +# LEDR +#============================================================ + +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] + + + +#============================================================ +# HEX0 +#============================================================ + +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] + +#============================================================ +# HEX1 +#============================================================ + +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] + + +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_file + +set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Standard Edition" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top \ No newline at end of file diff --git a/lab_06/src/07_lfsr/synthesis/de10_lite.sdc b/lab_06/src/07_lfsr/synthesis/de10_lite.sdc new file mode 100644 index 0000000..5027bba --- /dev/null +++ b/lab_06/src/07_lfsr/synthesis/de10_lite.sdc @@ -0,0 +1,13 @@ +create_clock -name clk -period 50MHz [get_ports CLOCK_50] + +derive_clock_uncertainty + +create_generated_clock -name clk_slow \ + -source [get_ports CLOCK_50] \ + [get_registers {clk_divider:clk_div|cnt_div[*]}] + +set_false_path -from * -to [get_ports {HEX0[*]}] +set_false_path -from * -to [get_ports {HEX1[*]}] +set_false_path -from * -to [get_ports {LEDR[*]}] + +set_false_path -from [get_ports {KEY[*]}] -to [all_clocks] diff --git a/lab_06/src/07_lfsr/synthesis/de2_115.v b/lab_06/src/07_lfsr/synthesis/de10_lite.v similarity index 88% rename from lab_06/src/07_lfsr/synthesis/de2_115.v rename to lab_06/src/07_lfsr/synthesis/de10_lite.v index 26c746d..34dc1b6 100644 --- a/lab_06/src/07_lfsr/synthesis/de2_115.v +++ b/lab_06/src/07_lfsr/synthesis/de10_lite.v @@ -1,12 +1,12 @@ -module de2_115 +module de10_lite ( input CLOCK_50, input [0:0] KEY, output [7:0] LEDR, - output [6:0] HEX1, - output [6:0] HEX0 + output [7:0] HEX1, + output [7:0] HEX0 ); localparam CNT_W = 8; @@ -34,7 +34,7 @@ module de2_115 lfsr psrg ( - .clk ( clk_global ), + .clk ( clk_global ), .rst_n ( KEY[0] ), .prg_out ( cnt_to_seg7 ) ); diff --git a/lab_06/src/07_lfsr/synthesis/de2_115.qsf b/lab_06/src/07_lfsr/synthesis/de2_115.qsf deleted file mode 100644 index 0195935..0000000 --- a/lab_06/src/07_lfsr/synthesis/de2_115.qsf +++ /dev/null @@ -1,110 +0,0 @@ -set_global_assignment -name DEVICE EP4CE115F29C7 -set_global_assignment -name FAMILY "Cyclone IV E" -set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 - -set_global_assignment -name TOP_LEVEL_ENTITY de2_115 - -set_global_assignment -name VERILOG_FILE de2_115.v -set_global_assignment -name VERILOG_FILE ../lfsr.v -set_global_assignment -name VERILOG_FILE ../../common/led7.v -set_global_assignment -name VERILOG_FILE ../../common/clk_divider.v - -set_global_assignment -name SDC_FILE de2_115.sdc - -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK* -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX* -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY* -set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR* - -#============================================================ -# CLOCK -#============================================================ -set_location_assignment PIN_Y2 -to CLOCK_50 - -#============================================================ -# KEY -#============================================================ -set_location_assignment PIN_M23 -to KEY[0] - -#============================================================ -# LED -#============================================================ -set_location_assignment PIN_G19 -to LEDR[0] -set_location_assignment PIN_F19 -to LEDR[1] -set_location_assignment PIN_E19 -to LEDR[2] -set_location_assignment PIN_F21 -to LEDR[3] -set_location_assignment PIN_F18 -to LEDR[4] -set_location_assignment PIN_E18 -to LEDR[5] -set_location_assignment PIN_J19 -to LEDR[6] -set_location_assignment PIN_H19 -to LEDR[7] -set_location_assignment PIN_J17 -to LEDR[8] - - -#============================================================ -# SEG7 -#============================================================ -set_location_assignment PIN_G18 -to HEX0[0] -set_location_assignment PIN_F22 -to HEX0[1] -set_location_assignment PIN_E17 -to HEX0[2] -set_location_assignment PIN_L26 -to HEX0[3] -set_location_assignment PIN_L25 -to HEX0[4] -set_location_assignment PIN_J22 -to HEX0[5] -set_location_assignment PIN_H22 -to HEX0[6] -set_location_assignment PIN_M24 -to HEX1[0] -set_location_assignment PIN_Y22 -to HEX1[1] -set_location_assignment PIN_W21 -to HEX1[2] -set_location_assignment PIN_W22 -to HEX1[3] -set_location_assignment PIN_W25 -to HEX1[4] -set_location_assignment PIN_U23 -to HEX1[5] -set_location_assignment PIN_U24 -to HEX1[6] -set_location_assignment PIN_AA25 -to HEX2[0] -set_location_assignment PIN_AA26 -to HEX2[1] -set_location_assignment PIN_Y25 -to HEX2[2] -set_location_assignment PIN_W26 -to HEX2[3] -set_location_assignment PIN_Y26 -to HEX2[4] -set_location_assignment PIN_W27 -to HEX2[5] -set_location_assignment PIN_W28 -to HEX2[6] -set_location_assignment PIN_V21 -to HEX3[0] -set_location_assignment PIN_U21 -to HEX3[1] -set_location_assignment PIN_AB20 -to HEX3[2] -set_location_assignment PIN_AA21 -to HEX3[3] -set_location_assignment PIN_AD24 -to HEX3[4] -set_location_assignment PIN_AF23 -to HEX3[5] -set_location_assignment PIN_Y19 -to HEX3[6] -set_location_assignment PIN_AB19 -to HEX4[0] -set_location_assignment PIN_AA19 -to HEX4[1] -set_location_assignment PIN_AG21 -to HEX4[2] -set_location_assignment PIN_AH21 -to HEX4[3] -set_location_assignment PIN_AE19 -to HEX4[4] -set_location_assignment PIN_AF19 -to HEX4[5] -set_location_assignment PIN_AE18 -to HEX4[6] -set_location_assignment PIN_AD18 -to HEX5[0] -set_location_assignment PIN_AC18 -to HEX5[1] -set_location_assignment PIN_AB18 -to HEX5[2] -set_location_assignment PIN_AH19 -to HEX5[3] -set_location_assignment PIN_AG19 -to HEX5[4] -set_location_assignment PIN_AF18 -to HEX5[5] -set_location_assignment PIN_AH18 -to HEX5[6] -set_location_assignment PIN_AA17 -to HEX6[0] -set_location_assignment PIN_AB16 -to HEX6[1] -set_location_assignment PIN_AA16 -to HEX6[2] -set_location_assignment PIN_AB17 -to HEX6[3] -set_location_assignment PIN_AB15 -to HEX6[4] -set_location_assignment PIN_AA15 -to HEX6[5] -set_location_assignment PIN_AC17 -to HEX6[6] -set_location_assignment PIN_AD17 -to HEX7[0] -set_location_assignment PIN_AE17 -to HEX7[1] -set_location_assignment PIN_AG17 -to HEX7[2] -set_location_assignment PIN_AH17 -to HEX7[3] -set_location_assignment PIN_AF17 -to HEX7[4] -set_location_assignment PIN_AG18 -to HEX7[5] -set_location_assignment PIN_AA14 -to HEX7[6] - -set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Standard Edition" -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/lab_06/src/buzzer/melody.sv b/lab_06/src/buzzer/melody.sv new file mode 100644 index 0000000..d343e8f --- /dev/null +++ b/lab_06/src/buzzer/melody.sv @@ -0,0 +1,188 @@ +`define melody3 +module melody +( + input clk, + input rst_n, + input [7:0] gamma, + input en, + output tone +); + + localparam C4=3'h0, D4=3'h1, E4=3'h2, F4=3'h3, + G4=3'h4, A4=3'h5, B4=3'h6, P4=3'h7; + + + + logic [1:0] dur_cnt; + logic [2:0] sel; + logic [1:0] tone_size; + + +`ifdef melody1 + + localparam integer mel_width = 64; + + typedef struct packed { logic [mel_width-1:0][1:0] size; + logic [mel_width-1:0][2:0] note;} song; + + song s,my_song; + + // Melody №1. A4ntoshka + //------------------------------ + + assign my_song.note = { + A4, G4, P4, A4, + F4, P4, A4, G4, + E4, C4, A4, F4, + A4, G4, P4, A4, + F4, P4, A4, G4, + A4, G4, F4, E4, + D4, C4, P4, A4, + B4, A4, G4, P4, + + G4, A4, G4, F4, + P4, A4, B4, A4, + G4, F4, E4, G4, + F4, A4, B4, A4, + G4, F4, E4, G4, + F4, P4, A4, G4, + P4, E4, P4, F4, + P4, P4, P4, P4 + }; + + assign my_song.size = { + 2'h0, 2'h1, 2'h0, 2'h0, + 2'h1, 2'h0, 2'h0, 2'h1, + 2'h0, 2'h0, 2'h1, 2'h0, + 2'h0, 2'h1, 2'h0, 2'h0, + 2'h1, 2'h0, 2'h0, 2'h0, + 2'h0, 2'h0, 2'h0, 2'h1, + 2'h1, 2'h0, 2'h1, 2'h0, + 2'h0, 2'h0, 2'h0, 2'h1, + + 2'h0, 2'h0, 2'h0, 2'h0, + 2'h1, 2'h0, 2'h0, 2'h0, + 2'h0, 2'h0, 2'h0, 2'h0, + 2'h0, 2'h0, 2'h0, 2'h0, + 2'h0, 2'h0, 2'h0, 2'h0, + 2'h0, 2'h0, 2'h0, 2'h0, + 2'h0, 2'h0, 2'h0, 2'h0, + 2'h0, 2'h0, 2'h0, 2'h0 + }; + + + //============================== +`endif // `ifdef melody1 + + +`ifdef melody2 + + localparam integer mel_width = 32; + + typedef struct packed { logic [mel_width-1:0][1:0] size; + logic [mel_width-1:0][2:0] note;} song; + song s,my_song; + + // Melogy №2. Jingle bells + //------------------------------ + assign my_song.note = { + E4, E4, E4, P4, + E4, E4, E4, P4, + E4, G4, C4, D4, + E4, P4, F4, F4, + F4, F4, P4, F4, + E4, E4, P4, E4, + D4, D4, E4, D4, + G4, P4, P4, P4 + }; + + assign my_song.size = { + 2'h0, 2'h0, 2'h0, 2'h0, + 2'h0, 2'h0, 2'h0, 2'h0, + 2'h0, 2'h0, 2'h0, 2'h0, + 2'h0, 2'h0, 2'h0, 2'h0, + 2'h0, 2'h0, 2'h0, 2'h0, + 2'h0, 2'h0, 2'h0, 2'h0, + 2'h0, 2'h0, 2'h0, 2'h0, + 2'h0, 2'h1, 2'h1, 2'h0 + }; + //============================== + + `endif // `ifdef melody2 + + `ifdef melody3 + + localparam integer mel_width = 32; + + typedef struct packed { logic [mel_width-1:0][1:0] size; + logic [mel_width-1:0][2:0] note;} song; + song s,my_song; + + // Melody №3. Two_merry_geese + //------------------------------ + + assign my_song.note = { + F4, E4, D4, C4, + G4, P4, G4, P4, + F4, E4, D4, C4, + G4, P4, G4, P4, + F4, A4, A4, F4, + E4, G4, G4, E4, + D4, E4, F4, D4, + C4, P4, C4, P4 + }; + + assign my_song.size= { + 2'h0, 2'h0, 2'h0, 2'h0, + 2'h0, 2'h0, 2'h0, 2'h0, + 2'h0, 2'h0, 2'h0, 2'h0, + 2'h0, 2'h0, 2'h0, 2'h0, + 2'h0, 2'h0, 2'h0, 2'h0, + 2'h0, 2'h0, 2'h0, 2'h0, + 2'h0, 2'h0, 2'h0, 2'h0, + 2'h0, 2'h0, 2'h0, 2'h0 + }; + + //============================== + + `endif // `ifdef melody3 + + + + + + + assign sel = s.note[mel_width-1]; + assign tone_size = s.size[mel_width-1]; + + always_comb + case(sel) + C4 : tone = gamma[0]; + D4 : tone = gamma[1]; + E4 : tone = gamma[2]; + F4 : tone = gamma[3]; + G4 : tone = gamma[4]; + A4 : tone = gamma[5]; + B4 : tone = gamma[6]; + P4 : tone = gamma[7]; + endcase // case (sel) + + + always_ff@(posedge clk or negedge rst_n) + if(!rst_n) begin + dur_cnt <= '0; + s.size <= my_song.size; + s.note <= my_song.note; + end + else if(en) + if(dur_cnt == tone_size) + begin + s.size <= {s.size[mel_width-2:0],s.size[mel_width-1]}; + s.note <= {s.note[mel_width-2:0],s.note[mel_width-1]}; + dur_cnt <= '0; + end + else + dur_cnt <= dur_cnt + 1'b1; + +endmodule // melody + diff --git a/lab_06/src/buzzer/simulation/01_simulate_with_modelsim.bat b/lab_06/src/buzzer/simulation/01_simulate_with_modelsim.bat new file mode 100644 index 0000000..a9ce143 --- /dev/null +++ b/lab_06/src/buzzer/simulation/01_simulate_with_modelsim.bat @@ -0,0 +1,13 @@ +rem recreate a temp folder for all the simulation files + +rd /s /q sim +md sim +cd sim + +rem start the simulation + +vsim -do ../modelsim_script.tcl + +rem return to the parent folder + +cd .. diff --git a/lab_06/src/buzzer/simulation/01_simulate_with_modelsim.sh b/lab_06/src/buzzer/simulation/01_simulate_with_modelsim.sh new file mode 100755 index 0000000..7175cea --- /dev/null +++ b/lab_06/src/buzzer/simulation/01_simulate_with_modelsim.sh @@ -0,0 +1,15 @@ +#!/usr/bin/env bash + +# recreate a temp folder for all the simulation files + +rm -rf sim +mkdir sim +cd sim + +# start the simulation + +vsim -do ../modelsim_script.tcl + +# return to the parent folder + +cd .. diff --git a/lab_06/src/buzzer/simulation/02_simulate_with_icarus.bat b/lab_06/src/buzzer/simulation/02_simulate_with_icarus.bat new file mode 100644 index 0000000..0b1525f --- /dev/null +++ b/lab_06/src/buzzer/simulation/02_simulate_with_icarus.bat @@ -0,0 +1,21 @@ +rem recreate a temp folder for all the simulation files + +rd /s /q sim +md sim +cd sim + +rem compile verilog files for simulation + +iverilog -o tone_gen.out -s tone_gen_tb ../../tone_gen.v ../tone_gen_tb.v + +rem run the simulation and finish on $stop + +vvvp -l tone_gen.log -n tone_gen.out + +rem show the simulation results in GTKwave + +gtkwave -T ../../../common/cfg.tcl dump.vcd + +rem return to the parent folder + +cd .. diff --git a/lab_06/src/buzzer/simulation/02_simulate_with_icarus.sh b/lab_06/src/buzzer/simulation/02_simulate_with_icarus.sh new file mode 100755 index 0000000..30d4b79 --- /dev/null +++ b/lab_06/src/buzzer/simulation/02_simulate_with_icarus.sh @@ -0,0 +1,14 @@ +#!/usr/bin/env bash +SIM_DIR="sim/" +## Create simulation directory +echo "################################################" +echo "Recreate a temp folder for all simulation files" +echo "################################################" +rm -rf ${SIM_DIR} +mkdir ${SIM_DIR} +cd ${SIM_DIR} + + +iverilog -o tone_gen.out -s tone_gen_tb ../../tone_gen.v ../tone_gen_tb.v +vvp -l tone_gen.log -n tone_gen.out +gtkwave -T ../../../common/cfg.tcl dump.vcd diff --git a/lab_06/src/buzzer/simulation/modelsim_script.tcl b/lab_06/src/buzzer/simulation/modelsim_script.tcl new file mode 100644 index 0000000..784f15b --- /dev/null +++ b/lab_06/src/buzzer/simulation/modelsim_script.tcl @@ -0,0 +1,28 @@ + +# create modelsim working library + +vlib work + +# compile all the Verilog sources + +vlog ../../tone_gen.v +vlog ../tone_gen_tb.v + +set top=tone_gen_tb +# open the testbench module for simulation + +vsim -novopt work.tone_gen_tb + +# add all testbench signals to time diagram + + +add wave -radix bin sim:/tone_gen_tb/clk +add wave -radix bin sim:/tone_gen_tb/rst_n +add wave -radix bin sim:/tone_gen_tb/tone_freq + +# run the simulation + +run -all + +# expand the signals time diagram + diff --git a/lab_06/src/buzzer/simulation/tone_gen_tb.v b/lab_06/src/buzzer/simulation/tone_gen_tb.v new file mode 100644 index 0000000..87f556a --- /dev/null +++ b/lab_06/src/buzzer/simulation/tone_gen_tb.v @@ -0,0 +1,57 @@ +`timescale 1ns/1ns +module tone_gen_tb; + + reg clk; + reg rst_n; + wire tone_freq; + + time start,stop; + initial begin + clk = 1'b0; + forever + #1 clk = !clk; + end + + tone_gen + #( + .ref_clock ( 50000000 ), + .out_freq_x100 ( 50000 ) + ) + tone_dut + ( + .clk ( clk ), + .rst_n ( rst_n ), + .tone_freq ( tone_freq ) + ); + + task info; + begin + @(posedge tone_freq); + start = $time; + $display("@%0t\ttone_freq activate",$time); + @(negedge tone_freq); + stop = $time; + $display("@%0t\ttone_freq deactive",$time); + $display("----------Pulse duration = %0t----------\n",stop-start); + end + endtask // info + + + + initial begin + $dumpvars(); + + rst_n = 1'b1; + + #11 rst_n = 1'b0; + #11 rst_n = 1'b1; + + repeat(4)begin + info; + end + + #100 $finish; + + end + +endmodule // tone_gen_tb diff --git a/lab_06/src/buzzer/synthesis/de10_lite.qpf b/lab_06/src/buzzer/synthesis/de10_lite.qpf new file mode 100644 index 0000000..68baac6 --- /dev/null +++ b/lab_06/src/buzzer/synthesis/de10_lite.qpf @@ -0,0 +1 @@ +# It is OK for this file to be empty, all the settings are in .qsf file diff --git a/lab_06/src/buzzer/synthesis/de10_lite.qsf b/lab_06/src/buzzer/synthesis/de10_lite.qsf new file mode 100644 index 0000000..d5b95cd --- /dev/null +++ b/lab_06/src/buzzer/synthesis/de10_lite.qsf @@ -0,0 +1,39 @@ +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 + +set_global_assignment -name TOP_LEVEL_ENTITY de10_lite + +set_global_assignment -name SYSTEMVERILOG_FILE de10_lite.sv +set_global_assignment -name VERILOG_FILE ../tone_gen.v +set_global_assignment -name SYSTEMVERILOG_FILE ../melody.sv +set_global_assignment -name VERILOG_FILE ../../common/strobe_gen.v + +set_global_assignment -name SDC_FILE de10_lite.sdc + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK* +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO* + + +#============================================================ +# CLOCK +#============================================================ + +set_location_assignment PIN_P11 -to CLOCK_50 + +#============================================================ +# KEY +#============================================================ + +set_location_assignment PIN_B8 -to KEY[0] + + +#============================================================ +# GPIO, GPIO connect to GPIO Default +#============================================================ + +set_location_assignment PIN_AA2 -to GPIO[35] + + +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_file diff --git a/lab_06/src/buzzer/synthesis/de10_lite.sdc b/lab_06/src/buzzer/synthesis/de10_lite.sdc new file mode 100644 index 0000000..d406a08 --- /dev/null +++ b/lab_06/src/buzzer/synthesis/de10_lite.sdc @@ -0,0 +1,8 @@ +create_clock -name clk -period 50MHz [get_ports CLOCK_50] + +derive_clock_uncertainty + +set_false_path -from * -to [get_ports {GPIO[*]}] +set_false_path -from * -to [get_ports {KEY[*]}] + +set_false_path -from [get_ports {KEY[*]}] -to [all_clocks] diff --git a/lab_06/src/buzzer/synthesis/de10_lite.sv b/lab_06/src/buzzer/synthesis/de10_lite.sv new file mode 100644 index 0000000..7538d3d --- /dev/null +++ b/lab_06/src/buzzer/synthesis/de10_lite.sv @@ -0,0 +1,58 @@ +module de10_lite +( + input CLOCK_50, + input [0:0] KEY, + inout [35:0] GPIO +); + localparam clk_50 = 50000000; + + // TONE= {C,D,E,F,G,A,Bb}; clear B = 52300; + localparam integer tone [0:6] = '{26163,29400, + 32963,34900, + 39200,44000, + 46500}; + logic [8:0] gamma; + logic next_tone; + logic to_buzzer; + + generate + genvar i; + for(i = 0;i < 7;i = i+1)begin:ga + tone_gen + #( + .ref_clock (clk_50), + .out_freq_x100 (tone[i]) + ) + note + ( + .clk ( CLOCK_50 ), + .rst_n ( ~KEY[0] ), + .tone_freq ( gamma[i] ) + ); + end + endgenerate + + assign gamma[7]=1'b0; + + strobe_gen #(.div(24)) + stb + ( + .clk ( CLOCK_50 ), + .rst_n ( ~KEY[0] ), + .strobe ( next_tone ) + ); + + + melody mel + ( + .clk ( CLOCK_50 ), + .rst_n ( ~KEY[0] ), + .gamma ( gamma ), + .en ( next_tone ), + .tone ( to_buzzer ) + ); + + + assign GPIO[35] = to_buzzer; + +endmodule // de10_lite diff --git a/lab_06/src/buzzer/tone_gen.v b/lab_06/src/buzzer/tone_gen.v new file mode 100644 index 0000000..00deb19 --- /dev/null +++ b/lab_06/src/buzzer/tone_gen.v @@ -0,0 +1,36 @@ +module tone_gen +#( + parameter ref_clock = 50000000, + parameter out_freq_x100 = 26163 +) + +( + input clk, + input rst_n, + output reg tone_freq +); + + localparam samp_rate = ref_clock*100/out_freq_x100; + + reg [31:0] cnt; + + always@(posedge clk or negedge rst_n) + if(!rst_n) + begin + cnt <= 16'b0; + tone_freq <= 0; + end + else if(cnt == samp_rate / 2 - 1 ) + begin + cnt <= 16'b0; + tone_freq <= !tone_freq; + end + else + begin + cnt <= cnt + 16'b1; + tone_freq <= tone_freq; + end + + + +endmodule // tone_gen diff --git a/lab_06/src/common/bin2bcd.v b/lab_06/src/common/bin2bcd.v new file mode 100644 index 0000000..ae44d44 --- /dev/null +++ b/lab_06/src/common/bin2bcd.v @@ -0,0 +1,25 @@ +module bin2bcd +#( parameter IN_WIDTH = 10, + DIGITS = 4 +) +( + input [IN_WIDTH - 1:0] bin, + output reg [DIGITS*4 - 1:0] bcd +); + +integer i, j; +//BIN to BCD +always@* +begin + bcd = 0; + for (i=IN_WIDTH-1; i>=0; i=i-1) + begin + for (j=DIGITS-1; j >= 0; j = j - 1) + if (bcd[4*j +: 4] >= 5) + bcd[4*j +: 4] = bcd[4*j +: 4] + 3; + bcd = bcd << 1; + bcd[0] = bin[i]; + end +end + +endmodule diff --git a/lab_06/src/common/cfg.tcl b/lab_06/src/common/cfg.tcl new file mode 100644 index 0000000..9a5fa92 --- /dev/null +++ b/lab_06/src/common/cfg.tcl @@ -0,0 +1,14 @@ +#!/usr/bin/wish + +set sig_list [list] + +set nfacs [ gtkwave::getNumFacs ] + +for {set i 0} {$i < $nfacs } {incr i} { + set facname [ gtkwave::getFacName $i ] + #puts "$i: $facname" + #Only top level show + set d_cnt [expr {[llength [split $facname "."]] - 1}] + if { $d_cnt == 1 } {lappend sig_list $facname}} + +set num_added [ gtkwave::addSignalsFromList $sig_list ] diff --git a/lab_06/src/common/led7.v b/lab_06/src/common/led7.v index 6003514..3ac8833 100644 --- a/lab_06/src/common/led7.v +++ b/lab_06/src/common/led7.v @@ -29,38 +29,38 @@ module led7 #( parameter COUNT = 1 //Quantity of used 7-segs leds )( input [4*COUNT-1:0] data, - output [7*COUNT-1:0] leds + output [8*COUNT-1:0] leds ); wire [3:0] in [0:COUNT-1]; -reg [6:0] out [0:COUNT-1]; +reg [7:0] out [0:COUNT-1]; genvar i; generate for (i=0; i<=COUNT-1; i=i+1) begin : groups assign in[i] = data[4*i +: 4]; - assign leds[7*i +: 7] = out[i]; + assign leds[8*i +: 8] = out[i]; always@ (in[i]) case (in[i]) //6543201 - 4'h0: out[i] = 7'b1000000; - 4'h1: out[i] = 7'b1111001; - 4'h2: out[i] = 7'b0100100; - 4'h3: out[i] = 7'b0110000; - 4'h4: out[i] = 7'b0011001; - 4'h5: out[i] = 7'b0010010; - 4'h6: out[i] = 7'b0000010; - 4'h7: out[i] = 7'b1111000; - 4'h8: out[i] = 7'b0000000; - 4'h9: out[i] = 7'b0010000; - 4'ha: out[i] = 7'b0001000; - 4'hb: out[i] = 7'b0000011; - 4'hc: out[i] = 7'b1000110; - 4'hd: out[i] = 7'b0100001; - 4'he: out[i] = 7'b0000110; - 4'hf: out[i] = 7'b0001110; - default: out[i] = 7'h7f; + 4'h0: out[i] = 8'b11000000; + 4'h1: out[i] = 8'b11111001; + 4'h2: out[i] = 8'b10100100; + 4'h3: out[i] = 8'b10110000; + 4'h4: out[i] = 8'b10011001; + 4'h5: out[i] = 8'b10010010; + 4'h6: out[i] = 8'b10000010; + 4'h7: out[i] = 8'b11111000; + 4'h8: out[i] = 8'b10000000; + 4'h9: out[i] = 8'b10010000; + 4'ha: out[i] = 8'b10001000; + 4'hb: out[i] = 8'b10000011; + 4'hc: out[i] = 8'b11000110; + 4'hd: out[i] = 8'b10100001; + 4'he: out[i] = 8'b10000110; + 4'hf: out[i] = 8'b10001110; + default: out[i] = 8'h7f; endcase end endgenerate diff --git a/lab_06/src/common/strobe_gen.v b/lab_06/src/common/strobe_gen.v new file mode 100644 index 0000000..501e87c --- /dev/null +++ b/lab_06/src/common/strobe_gen.v @@ -0,0 +1,19 @@ +module strobe_gen +#( parameter div=24 ) +( + input clk, + input rst_n, + output strobe +); + + reg [div-1:0] cnt; + + always@(posedge clk or negedge rst_n) + if(!rst_n) + cnt <= {div{1'b0}}; + else + cnt <= cnt + {{(div-1){1'b0}},1'b1}; + + assign strobe = (cnt[div-1:0] == {div{1'b1}}); + +endmodule // strobe_gen diff --git a/lab_06/src/crc32/crc32.v b/lab_06/src/crc32/crc32.v new file mode 100644 index 0000000..6617b9b --- /dev/null +++ b/lab_06/src/crc32/crc32.v @@ -0,0 +1,60 @@ +// -*- Mode: Verilog -*- +// Filename : crc32.v +// Description : x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x^1+x^0 +// Algorithm : CRC-32 MPEG-2 +// Polynomial : 0x04C11DB7 +// Init value : 0xFFFFFFFF +// RefIn : False +// RefOut : False +// Checkout : 0x376E6E7 + +module crc32 +( + input clk, + input rst_n, + input [7:0] data, + input crc_en, + output reg [31:0] crc32 +); + always@(posedge clk or negedge rst_n) + if(!rst_n) + crc32 <= 32'hFFFFFFFF; + else begin + crc32 <= crc_en ? crc32_byte(crc32,data) : crc32; + + end + function [31:0] crc32_bit; + input [31:0] crc; + input data; + begin + crc32_bit = crc << 1; + crc32_bit[0] = crc[31] ^ data; + crc32_bit[1] = crc[31] ^ data ^ crc[0]; + crc32_bit[2] = crc[31] ^ data ^ crc[1]; + crc32_bit[4] = crc[31] ^ data ^ crc[3]; + crc32_bit[5] = crc[31] ^ data ^ crc[4]; + crc32_bit[7] = crc[31] ^ data ^ crc[6]; + crc32_bit[8] = crc[31] ^ data ^ crc[7]; + crc32_bit[10] = crc[31] ^ data ^ crc[9]; + crc32_bit[11] = crc[31] ^ data ^ crc[10]; + crc32_bit[12] = crc[31] ^ data ^ crc[11]; + crc32_bit[16] = crc[31] ^ data ^ crc[15]; + crc32_bit[22] = crc[31] ^ data ^ crc[21]; + crc32_bit[23] = crc[31] ^ data ^ crc[22]; + crc32_bit[26] = crc[31] ^ data ^ crc[25]; + end + endfunction // crc32_bit + + function [31:0] crc32_byte; + input [31:0] crc; + input [7:0] data; + integer i; + begin + crc32_byte = crc; + for(i=0;i<8;i=i+1)begin + crc32_byte = crc32_bit(crc32_byte,data[7-i]); + end + end + endfunction // crc32_byte + +endmodule // crc32 diff --git a/lab_06/src/crc32/simulation/01_simulate_with_modelsim.bat b/lab_06/src/crc32/simulation/01_simulate_with_modelsim.bat new file mode 100644 index 0000000..a9ce143 --- /dev/null +++ b/lab_06/src/crc32/simulation/01_simulate_with_modelsim.bat @@ -0,0 +1,13 @@ +rem recreate a temp folder for all the simulation files + +rd /s /q sim +md sim +cd sim + +rem start the simulation + +vsim -do ../modelsim_script.tcl + +rem return to the parent folder + +cd .. diff --git a/lab_06/src/crc32/simulation/01_simulate_with_modelsim.sh b/lab_06/src/crc32/simulation/01_simulate_with_modelsim.sh new file mode 100755 index 0000000..7175cea --- /dev/null +++ b/lab_06/src/crc32/simulation/01_simulate_with_modelsim.sh @@ -0,0 +1,15 @@ +#!/usr/bin/env bash + +# recreate a temp folder for all the simulation files + +rm -rf sim +mkdir sim +cd sim + +# start the simulation + +vsim -do ../modelsim_script.tcl + +# return to the parent folder + +cd .. diff --git a/lab_06/src/crc32/simulation/02_simulate_with_icarus.bat b/lab_06/src/crc32/simulation/02_simulate_with_icarus.bat new file mode 100644 index 0000000..d9b2d0d --- /dev/null +++ b/lab_06/src/crc32/simulation/02_simulate_with_icarus.bat @@ -0,0 +1,21 @@ +rem recreate a temp folder for all the simulation files + +rd /s /q sim +md sim +cd sim + +rem compile verilog files for simulation + +iverilog -o crc32.out -s crc32_tb ../../crc32.v ../crc32_tb.v + +rem run the simulation and finish on $stop + +vvvp -l crc32.log -n crc32.out + +rem show the simulation results in GTKwave + +gtkwave -T ../../../common/cfg.tcl dump.vcd + +rem return to the parent folder + +cd .. diff --git a/lab_06/src/crc32/simulation/02_simulate_with_icarus.sh b/lab_06/src/crc32/simulation/02_simulate_with_icarus.sh new file mode 100755 index 0000000..71084eb --- /dev/null +++ b/lab_06/src/crc32/simulation/02_simulate_with_icarus.sh @@ -0,0 +1,14 @@ +#!/usr/bin/env bash +SIM_DIR="sim/" +## Create simulation directory +echo "################################################" +echo "Recreate a temp folder for all simulation files" +echo "################################################" +rm -rf ${SIM_DIR} +mkdir ${SIM_DIR} +cd ${SIM_DIR} + + +iverilog -o crc32.out -s crc32_tb ../../crc32.v ../crc32_tb.v +vvp -l crc32.log -n crc32.out +gtkwave -T ../../../common/cfg.tcl dump.vcd diff --git a/lab_06/src/crc32/simulation/crc32_tb.v b/lab_06/src/crc32/simulation/crc32_tb.v new file mode 100644 index 0000000..76b122a --- /dev/null +++ b/lab_06/src/crc32/simulation/crc32_tb.v @@ -0,0 +1,101 @@ +`timescale 1ns/1ns +module crc32_tb; + + reg [7:0] data; + reg clk; + reg rst_n; + reg crc_en; + wire [31:0] crc32; + + + crc32 crc_dut + ( + .crc32 ( crc32[31:0]), + .clk ( clk ), + .rst_n ( rst_n ), + .data ( data[7:0] ), + .crc_en ( crc_en ) + ); + + initial begin + clk = 1'b0; + forever #5 clk = !clk; + end + integer i; + + reg [31:0] crc_out; + reg [63:0] crc_buff; + reg crc_err; + reg [31:0] rnd_data; + + + task send_int(input [31:0] d_in); + begin + for(i=4;i>0;i=i-1)begin + @(negedge clk)begin + crc_en = 1'b1; + data = d_in[i*8-1-:8]; + end + end + @(negedge clk)begin + crc_en = 1'b0; + crc_out = crc32; + end + end + endtask // send_data + + task check_crc(input [31:0] pack,input [31:0] crc); + begin + for(i=8;i>0;i=i-1)begin + @(negedge clk)begin + crc_en = 1'b1; + data = {pack,crc} >> (8*(i-1)); + end + end + @(negedge clk) + crc_en = 1'b0; + if( crc32 != 32'h0000 ) begin + $display("Error in current CRC value"); + crc_err = 1'b1; + end + else + crc_err = 1'b0; + end + endtask // check_crc + + + + task async_rst; + begin + #11 rst_n = 1'b0; + #11 rst_n = 1'b1; + end + endtask // async_rst + + + initial begin + $dumpvars(); + + data = 32'h00000000; + rst_n = 1'b1; + crc_en = 1'b0; + crc_err = 1'b0; + crc_out = 32'h0000; + + + + repeat(10)begin + async_rst(); + rnd_data = $urandom; + send_int(rnd_data); + async_rst(); + check_crc(rnd_data,crc_out); + + end + #30 + $finish; + end + +endmodule // crc32_tb + + diff --git a/lab_06/src/crc32/simulation/modelsim_script.tcl b/lab_06/src/crc32/simulation/modelsim_script.tcl new file mode 100644 index 0000000..8c752ae --- /dev/null +++ b/lab_06/src/crc32/simulation/modelsim_script.tcl @@ -0,0 +1,32 @@ + +# create modelsim working library + +vlib work + +# compile all the Verilog sources + +vlog ../../crc32.v +vlog ../crc32_tb.v + +set top=crc32_tb +# open the testbench module for simulation + +vsim -novopt work.crc32_tb + +# add all testbench signals to time diagram + + +add wave -radix bin sim:/crc32_tb/clk +add wave -radix bin sim:/crc32_tb/rst_n +add wave -radix bin sim:/crc32_tb/crc_en +add wave -radix hex sim:/crc32_tb/crc32 +add wave -radix hex sim:/crc32_tb/crc_out +add wave -radix hex sim:/crc32_tb/data +add wave -radix hex sim:/crc32_tb/rand_data + +# run the simulation + +run -all + +# expand the signals time diagram + diff --git a/lab_06/src/crc5/crc_ser.v b/lab_06/src/crc5/crc_ser.v new file mode 100644 index 0000000..7d1c37d --- /dev/null +++ b/lab_06/src/crc5/crc_ser.v @@ -0,0 +1,31 @@ +// Description : x^5+x^2+1 USB CRC5 + +module crc_ser +( + input data, + input clk, + input rst_n, + input crc_en, + output reg [4:0] crc5 +); + reg [4:0] crc5_s; + + always@(posedge clk or negedge rst_n) + begin + if(!rst_n) + crc5 <= 5'h1f; + else + crc5 <= crc_en ? crc5_s : crc5; + end + + always@* + begin + crc5_s[0] = crc5[4] ^ data ; + crc5_s[1] = crc5[0] ; + crc5_s[2] = crc5[4] ^ crc5[1] ^ data; + crc5_s[3] = crc5[2]; + crc5_s[4] = crc5[3]; + end + + +endmodule // crc_serial diff --git a/lab_06/src/crc5/simulation/01_simulate_with_modelsim.bat b/lab_06/src/crc5/simulation/01_simulate_with_modelsim.bat new file mode 100644 index 0000000..a9ce143 --- /dev/null +++ b/lab_06/src/crc5/simulation/01_simulate_with_modelsim.bat @@ -0,0 +1,13 @@ +rem recreate a temp folder for all the simulation files + +rd /s /q sim +md sim +cd sim + +rem start the simulation + +vsim -do ../modelsim_script.tcl + +rem return to the parent folder + +cd .. diff --git a/lab_06/src/crc5/simulation/01_simulate_with_modelsim.sh b/lab_06/src/crc5/simulation/01_simulate_with_modelsim.sh new file mode 100755 index 0000000..7175cea --- /dev/null +++ b/lab_06/src/crc5/simulation/01_simulate_with_modelsim.sh @@ -0,0 +1,15 @@ +#!/usr/bin/env bash + +# recreate a temp folder for all the simulation files + +rm -rf sim +mkdir sim +cd sim + +# start the simulation + +vsim -do ../modelsim_script.tcl + +# return to the parent folder + +cd .. diff --git a/lab_06/src/crc5/simulation/02_simulate_with_icarus.bat b/lab_06/src/crc5/simulation/02_simulate_with_icarus.bat new file mode 100644 index 0000000..358364d --- /dev/null +++ b/lab_06/src/crc5/simulation/02_simulate_with_icarus.bat @@ -0,0 +1,21 @@ +rem recreate a temp folder for all the simulation files + +rd /s /q sim +md sim +cd sim + +rem compile verilog files for simulation + +iverilog -o crc_ser.out -s crc_ser_tb ../../crc_ser.v ../crc_ser_tb.v + +rem run the simulation and finish on $stop + +vvvp -l crc_ser.log -n crc_ser.out + +rem show the simulation results in GTKwave + +gtkwave -T ../../../common/cfg.tcl dump.vcd + +rem return to the parent folder + +cd .. diff --git a/lab_06/src/crc5/simulation/02_simulate_with_icarus.sh b/lab_06/src/crc5/simulation/02_simulate_with_icarus.sh new file mode 100755 index 0000000..3d8e5d6 --- /dev/null +++ b/lab_06/src/crc5/simulation/02_simulate_with_icarus.sh @@ -0,0 +1,14 @@ +#!/usr/bin/env bash +SIM_DIR="sim/" +## Create simulation directory +echo "################################################" +echo "Recreate a temp folder for all simulation files" +echo "################################################" +rm -rf ${SIM_DIR} +mkdir ${SIM_DIR} +cd ${SIM_DIR} + + +iverilog -o crc_ser.out -s crc_ser_tb ../../crc_ser.v ../crc_ser_tb.v +vvp -l crc_ser.log -n crc_ser.out +gtkwave -T ../../../common/cfg.tcl dump.vcd diff --git a/lab_06/src/crc5/simulation/crc_ser_tb.v b/lab_06/src/crc5/simulation/crc_ser_tb.v new file mode 100644 index 0000000..4890a6e --- /dev/null +++ b/lab_06/src/crc5/simulation/crc_ser_tb.v @@ -0,0 +1,87 @@ +`timescale 1ns/1ns +module crc_ser_tb; + reg clk; + reg rst_n; + reg data; + wire [4:0] crc5; + reg crc_en; + + reg [7:0] buff; + //integer i; + + crc_ser crc (/*AUTOINST*/ + // Outputs + .crc5 (crc5), + // Inputs + .data (data), + .clk (clk), + .rst_n (rst_n), + .crc_en (crc_en)); + initial begin + clk=1'b0; + forever #5 clk = !clk; + end + + task async_rst; + begin + $display("@%0t_########## Reset start! ##########",$time); + #11 rst_n = 1'b0; + #11 rst_n = 1'b1; + $display("@%0t_########## Reset finish! ##########",$time); + end + endtask // async_rst + + task send_byte; + integer i; + begin + buff = $urandom%(255); + + for(i=0;i<8;i=i+1) begin + @(negedge clk)begin + crc_en = 1'b1; + data = buff[7-i]; + end + end + @(negedge clk); + crc_en = 1'b0; + i = 0; + end + endtask // send_byte + + task push_byte(input [7:0] d_byte); + integer k; + begin + buff = d_byte; + for(k=0;k<=7;k=k+1)begin + @(negedge clk)begin + crc_en = 1'b1; + data = d_byte[7-k]; + end + end + @(negedge clk); + crc_en = 1'b0; + k=0; + end + + endtask // push_byte + + + initial begin + $dumpvars(0); + data = 1'b0; + rst_n = 1'b1; + crc_en = 1'b0; + + repeat(10)begin + async_rst(); + push_byte($urandom%(255)); + end + + #20 + $finish; + + + end + +endmodule // crc_ser_tb + diff --git a/lab_06/src/crc5/simulation/modelsim_script.tcl b/lab_06/src/crc5/simulation/modelsim_script.tcl new file mode 100644 index 0000000..392c4bc --- /dev/null +++ b/lab_06/src/crc5/simulation/modelsim_script.tcl @@ -0,0 +1,32 @@ + +# create modelsim working library + +vlib work + +# compile all the Verilog sources + +vlog ../../crc_ser.v +vlog ../crc_ser_tb.v + +set top=crc_ser_tb +# open the testbench module for simulation + +vsim -novopt work.crc_ser_tb + +# add all testbench signals to time diagram + + +add wave -radix bin sim:/crc_ser_tb/clk +add wave -radix bin sim:/crc_ser_tb/rst_n +add wave -radix bin sim:/crc_ser_tb/crc_en +add wave -radix bin sim:/crc_ser_tb/data +add wave -radix hex sim:/crc_ser_tb/buff +add wave -radix hex sim:/crc_ser_tb/crc5 + + +# run the simulation + +run -all + +# expand the signals time diagram + diff --git a/lab_06/src/gray_cnt/bin2gray.v b/lab_06/src/gray_cnt/bin2gray.v new file mode 100644 index 0000000..579040a --- /dev/null +++ b/lab_06/src/gray_cnt/bin2gray.v @@ -0,0 +1,16 @@ +module bin2gray +#( + parameter WIDTH = 4 + ) + ( + input [WIDTH - 1 : 0] bin, + output [WIDTH - 1 : 0] gray + ); + + assign gray = bin ^ (bin>>1); + + +endmodule // bin2gray + + + diff --git a/lab_06/src/gray_cnt/gray2bin.v b/lab_06/src/gray_cnt/gray2bin.v new file mode 100644 index 0000000..8432a66 --- /dev/null +++ b/lab_06/src/gray_cnt/gray2bin.v @@ -0,0 +1,21 @@ +module gray2bin +#( + parameter WIDTH = 4 + ) + ( + input [WIDTH - 1 : 0] gray, + output [WIDTH - 1 : 0] bin + ); + + genvar i; + + generate + for(i=0; i>i); + end + endgenerate + + +endmodule // gray2bin + + diff --git a/lab_06/src/gray_cnt/gray_cnt.v b/lab_06/src/gray_cnt/gray_cnt.v new file mode 100644 index 0000000..6305b43 --- /dev/null +++ b/lab_06/src/gray_cnt/gray_cnt.v @@ -0,0 +1,31 @@ +module gray_cnt +#( + parameter WIDTH = 4 + ) + ( + input clk, + input rst_n, + input enable, + output reg [WIDTH - 1 : 0] gray + ); + + reg [WIDTH - 1 : 0] bin; + wire [WIDTH - 1 : 0] bin_inc; + wire [WIDTH - 1 : 0] bin_to_gray; + + always@(posedge clk or negedge rst_n) + if(!rst_n)begin + bin <= 0; + gray <= 0; + end + else if(enable)begin + bin <= bin_inc; + gray <= bin_to_gray; + end + + + assign bin_inc = bin + 1'b1; + assign bin_to_gray = bin_inc ^ (bin_inc >> 1); + + +endmodule // gray_cnt diff --git a/lab_06/src/gray_cnt/simulation/01_simulate_with_modelsim.bat b/lab_06/src/gray_cnt/simulation/01_simulate_with_modelsim.bat new file mode 100644 index 0000000..a9ce143 --- /dev/null +++ b/lab_06/src/gray_cnt/simulation/01_simulate_with_modelsim.bat @@ -0,0 +1,13 @@ +rem recreate a temp folder for all the simulation files + +rd /s /q sim +md sim +cd sim + +rem start the simulation + +vsim -do ../modelsim_script.tcl + +rem return to the parent folder + +cd .. diff --git a/lab_06/src/gray_cnt/simulation/01_simulate_with_modelsim.sh b/lab_06/src/gray_cnt/simulation/01_simulate_with_modelsim.sh new file mode 100755 index 0000000..7175cea --- /dev/null +++ b/lab_06/src/gray_cnt/simulation/01_simulate_with_modelsim.sh @@ -0,0 +1,15 @@ +#!/usr/bin/env bash + +# recreate a temp folder for all the simulation files + +rm -rf sim +mkdir sim +cd sim + +# start the simulation + +vsim -do ../modelsim_script.tcl + +# return to the parent folder + +cd .. diff --git a/lab_06/src/gray_cnt/simulation/02_simulate_with_icarus.bat b/lab_06/src/gray_cnt/simulation/02_simulate_with_icarus.bat new file mode 100644 index 0000000..bf2e9c0 --- /dev/null +++ b/lab_06/src/gray_cnt/simulation/02_simulate_with_icarus.bat @@ -0,0 +1,21 @@ +rem recreate a temp folder for all the simulation files + +rd /s /q sim +md sim +cd sim + +rem compile verilog files for simulation + +iverilog -o gray_cnt.out -s gray_cnt_out ../../gray_cnt.v ../gray_cnt_tb.v + +rem run the simulation and finish on $stop + +vvp -l gray_cnt.log -n gray_cnt.out + +rem show the simulation results in GTKwave + +gtkwave -T ../../../common/cfg.tcl dump.vcd + +rem return to the parent folder + +cd .. diff --git a/lab_06/src/gray_cnt/simulation/02_simulate_with_icarus.sh b/lab_06/src/gray_cnt/simulation/02_simulate_with_icarus.sh new file mode 100755 index 0000000..4742d1f --- /dev/null +++ b/lab_06/src/gray_cnt/simulation/02_simulate_with_icarus.sh @@ -0,0 +1,14 @@ +#!/usr/bin/env bash +SIM_DIR="sim/" +## Create simulation directory +echo "################################################" +echo "Recreate a temp folder for all simulation files" +echo "################################################" +rm -rf ${SIM_DIR} +mkdir ${SIM_DIR} +cd ${SIM_DIR} + + +iverilog -o gray_cnt.out -s gray_cnt_tb ../../gray_cnt.v ../gray_cnt_tb.v +vvp -l gray_cnt.log -n gray_cnt.out +gtkwave -T ../../../common/cfg.tcl dump.vcd diff --git a/lab_06/src/gray_cnt/simulation/gray_cnt_tb.v b/lab_06/src/gray_cnt/simulation/gray_cnt_tb.v new file mode 100644 index 0000000..26a1886 --- /dev/null +++ b/lab_06/src/gray_cnt/simulation/gray_cnt_tb.v @@ -0,0 +1,51 @@ +`timescale 1ns/1ns + +module gray_cnt_tb; + + localparam W = 4; + + reg clk; + reg rst_n; + reg enable; + wire [W - 1 : 0] gray; + integer en_time; + + gray_cnt #(.WIDTH(W)) + g_cnt + ( + // Outputs + .gray (gray[W - 1:0] ), + // Inputs + .clk ( clk ), + .rst_n ( rst_n ), + .enable ( enable ) + ); + + initial begin + clk = 1'b0; + forever + #5 clk = !clk; + end + + + initial begin + $dumpvars(); + + rst_n = 1'b1; + enable = 1'b0; + //-----Reset----- + #13 rst_n = 1'b0; + #10 rst_n = 1'b1; + //--------------- + + repeat(5) begin + en_time = $urandom%(30)+10; + begin + #11 enable = 1'b1; + #(en_time) enable = 1'b0; + end + end + #30 $finish; + end + +endmodule // gray_cnt_tb diff --git a/lab_06/src/gray_cnt/simulation/modelsim_script.tcl b/lab_06/src/gray_cnt/simulation/modelsim_script.tcl new file mode 100644 index 0000000..e0019cc --- /dev/null +++ b/lab_06/src/gray_cnt/simulation/modelsim_script.tcl @@ -0,0 +1,29 @@ + +# create modelsim working library + +vlib work + +# compile all the Verilog sources + +vlog ../../gray_cnt.v +vlog ../gray_cnt_tb.v + +set top=gray_cnt_tb +# open the testbench module for simulation + +vsim -novopt work.gray_cnt_tb + +# add all testbench signals to time diagram + + +add wave -radix bin sim:/gray_cnt_tb/clk +add wave -radix bin sim:/gray_cnt_tb/rst_n +add wave -radix bin sim:/gray_cnt_tb/enable +add wave -radix bin sim:/gray_cnt_tb/gray + +# run the simulation + +run -all + +# expand the signals time diagram + diff --git a/lab_06/src/gray_cnt/synthesis/de10_lite.qpf b/lab_06/src/gray_cnt/synthesis/de10_lite.qpf new file mode 100644 index 0000000..68baac6 --- /dev/null +++ b/lab_06/src/gray_cnt/synthesis/de10_lite.qpf @@ -0,0 +1 @@ +# It is OK for this file to be empty, all the settings are in .qsf file diff --git a/lab_06/src/gray_cnt/synthesis/de10_lite.qsf b/lab_06/src/gray_cnt/synthesis/de10_lite.qsf new file mode 100644 index 0000000..3026d53 --- /dev/null +++ b/lab_06/src/gray_cnt/synthesis/de10_lite.qsf @@ -0,0 +1,61 @@ +#============================================================ +# Altera DE10-Lite board settings +#============================================================ +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 + +set_global_assignment -name TOP_LEVEL_ENTITY de10_lite + +set_global_assignment -name SDC_FILE de10_lite.sdc + +set_global_assignment -name VERILOG_FILE de10_lite.v +set_global_assignment -name VERILOG_FILE ../gray_cnt.v +set_global_assignment -name VERILOG_FILE ../gray2bin.v +set_global_assignment -name VERILOG_FILE ../../common/strobe_gen.v +set_global_assignment -name VERILOG_FILE ../../common/led7.v + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX* +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY* + +#============================================================ +# CLOCK +#============================================================ + +set_location_assignment PIN_P11 -to CLOCK_50 + +#============================================================ +# KEY +#============================================================ +set_location_assignment PIN_B8 -to KEY[0] +set_location_assignment PIN_A7 -to KEY[1] + +#============================================================ +# LEDR +#============================================================ +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] + +#============================================================ +# HEX0 +#============================================================ +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] + +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_file diff --git a/lab_06/src/07_lfsr/synthesis/de2_115.sdc b/lab_06/src/gray_cnt/synthesis/de10_lite.sdc similarity index 82% rename from lab_06/src/07_lfsr/synthesis/de2_115.sdc rename to lab_06/src/gray_cnt/synthesis/de10_lite.sdc index f3aa73f..b15d33c 100644 --- a/lab_06/src/07_lfsr/synthesis/de2_115.sdc +++ b/lab_06/src/gray_cnt/synthesis/de10_lite.sdc @@ -1,9 +1,7 @@ create_clock -period 50MHz [get_ports CLOCK_50] - derive_clock_uncertainty set_false_path -from * -to [get_ports {HEX0[*]}] -set_false_path -from * -to [get_ports {HEX1[*]}] set_false_path -from * -to [get_ports {LEDR[*]}] set_false_path -from [get_ports {KEY[*]}] -to [all_clocks] diff --git a/lab_06/src/gray_cnt/synthesis/de10_lite.v b/lab_06/src/gray_cnt/synthesis/de10_lite.v new file mode 100644 index 0000000..1b112d7 --- /dev/null +++ b/lab_06/src/gray_cnt/synthesis/de10_lite.v @@ -0,0 +1,54 @@ +module de10_lite +( + input CLOCK_50, + input [1:0] KEY, + output [3:0] LEDR, + output [7:0] HEX0 +); + + localparam cnt_size = 4; + + wire strobe; + wire next_cnt; + wire [cnt_size - 1:0] bin_to_led; + wire [cnt_size - 1:0] gray_data; + + strobe_gen #(.div(24)) + strobe_en + ( + .clk ( CLOCK_50 ), + .rst_n ( KEY[0] ), + .strobe ( strobe ) + ); + + assign next_cnt = (!KEY[1]) ? strobe : 1'b0; + + // Gray counter on ledr + gray_cnt #(.WIDTH(cnt_size)) + gcnt + ( + .clk ( CLOCK_50 ), + .rst_n ( KEY[0] ), + .enable ( next_cnt ), + .gray ( gray_data ) + ); + + assign LEDR = gray_data; + + // Binary representation + + gray2bin #(.WIDTH(cnt_size)) + hex_cnt + ( + .gray ( gray_data ), + .bin ( bin_to_led ) + ); + + led7 #(.COUNT(1)) led7_inst + ( + .data ( bin_to_led ), + .leds ( HEX0 ) + ); + + +endmodule // de10_lite diff --git a/lab_06/src/hcsr04/hcsr04.v b/lab_06/src/hcsr04/hcsr04.v new file mode 100644 index 0000000..3c3550d --- /dev/null +++ b/lab_06/src/hcsr04/hcsr04.v @@ -0,0 +1,82 @@ +module hcsr04 +#( + parameter clk_freq = 50000000, + width = 8 +) +( + input clk, + input rst_n, + input echo, + output reg trig, + output reg [width - 1:0] distance +); + + localparam + max_distance_cm = 400, + + trigger_in_us = 10, + + measurment_cycle_ms = 200, + + vel_of_sound_m_per_s = 340, + + measurment_cycle_tick = ( clk_freq/1000 * measurment_cycle_ms ), + + trigger_in_tick = ( trigger_in_us*clk_freq/1000000), + + max_echo_tick = ( clk_freq/vel_of_sound_m_per_s/100) * max_distance_cm * 2, + + + trig_cnt_width = $clog2(measurment_cycle_tick), + echo_cnt_width = $clog2(max_echo_tick+1); + + + reg [trig_cnt_width - 1 : 0] trig_cnt; + reg [echo_cnt_width - 1 : 0] echo_cnt; + reg echo_buff; + wire echo_rise; + wire echo_fall; + + + always@(posedge clk or negedge rst_n) + if(!rst_n) + trig_cnt <= 0; + else if(trig_cnt == measurment_cycle_tick -1) + trig_cnt <= 0; + else + trig_cnt <= trig_cnt + 1'b1; + + always@(posedge clk or negedge rst_n) + if(!rst_n) + trig <= 1'b0; + else if(trig_cnt == measurment_cycle_tick - trigger_in_tick -1) + trig <= 1'b1; + else if(trig_cnt == measurment_cycle_tick - 1) + trig <= 1'b0; + + + + always@(posedge clk or negedge rst_n) + if(!rst_n) + echo_buff <= 0; + else + echo_buff <= echo; + + assign echo_rise = echo & !echo_buff; + assign echo_fall = !echo & echo_buff; + + + always@(posedge clk or negedge rst_n) + if(!rst_n)begin + echo_cnt <= 0; + distance <= 0; + end + else if(echo_rise) + echo_cnt <= 0; + else if(echo_fall) + distance <= echo_cnt[echo_cnt_width - 1 : echo_cnt_width - width]; + else + echo_cnt <= echo_cnt + 1'b1; + + +endmodule // hcsr04 diff --git a/lab_06/src/hcsr04/simulation/01_simulate_with_modelsim.bat b/lab_06/src/hcsr04/simulation/01_simulate_with_modelsim.bat new file mode 100755 index 0000000..a9ce143 --- /dev/null +++ b/lab_06/src/hcsr04/simulation/01_simulate_with_modelsim.bat @@ -0,0 +1,13 @@ +rem recreate a temp folder for all the simulation files + +rd /s /q sim +md sim +cd sim + +rem start the simulation + +vsim -do ../modelsim_script.tcl + +rem return to the parent folder + +cd .. diff --git a/lab_06/src/hcsr04/simulation/01_simulate_with_modelsim.sh b/lab_06/src/hcsr04/simulation/01_simulate_with_modelsim.sh new file mode 100755 index 0000000..7175cea --- /dev/null +++ b/lab_06/src/hcsr04/simulation/01_simulate_with_modelsim.sh @@ -0,0 +1,15 @@ +#!/usr/bin/env bash + +# recreate a temp folder for all the simulation files + +rm -rf sim +mkdir sim +cd sim + +# start the simulation + +vsim -do ../modelsim_script.tcl + +# return to the parent folder + +cd .. diff --git a/lab_06/src/hcsr04/simulation/02_simulate_with_icarus.bat b/lab_06/src/hcsr04/simulation/02_simulate_with_icarus.bat new file mode 100755 index 0000000..1e70afd --- /dev/null +++ b/lab_06/src/hcsr04/simulation/02_simulate_with_icarus.bat @@ -0,0 +1,21 @@ +rem recreate a temp folder for all the simulation files + +rd /s /q sim +md sim +cd sim + +rem compile verilog files for simulation + +iverilog -o hcsr04.out -s hcsr04_tb ../../hcsr04.v ../hcsr04_tb.v + +rem run the simulation and finish on $stop + +vvp -l hcsr04.log -n hcsr04.out + +rem show the simulation results in GTKwave + +gtkwave dump.vcd + +rem return to the parent folder + +cd .. diff --git a/lab_06/src/hcsr04/simulation/02_simulate_with_icarus.sh b/lab_06/src/hcsr04/simulation/02_simulate_with_icarus.sh new file mode 100755 index 0000000..71e0322 --- /dev/null +++ b/lab_06/src/hcsr04/simulation/02_simulate_with_icarus.sh @@ -0,0 +1,14 @@ +#!/usr/bin/env bash +SIM_DIR="sim/" +## Create simulation directory +echo "################################################" +echo "Recreate a temp folder for all simulation files" +echo "################################################" +rm -rf ${SIM_DIR} +mkdir ${SIM_DIR} +cd ${SIM_DIR} + + +iverilog -o hcsr04.out -s hcsr04_tb ../../hcsr04.v ../hcsr04_tb.v +vvp -l hcsr04.log -n hcsr04.out +gtkwave dump.vcd diff --git a/lab_06/src/hcsr04/simulation/hcsr04_tb.v b/lab_06/src/hcsr04/simulation/hcsr04_tb.v new file mode 100644 index 0000000..962f783 --- /dev/null +++ b/lab_06/src/hcsr04/simulation/hcsr04_tb.v @@ -0,0 +1,59 @@ +`timescale 1ns/1ns +module hcsr04_tb; + + localparam CLK_FREQ = 50000, + WIDTH = 8; + + reg clk; + reg rst_n; + reg echo; + wire trig; + wire [7:0] distance; + + hcsr04 + #( + .clk_freq ( CLK_FREQ ), + .width ( WIDTH ) + ) + hc_dut + ( + .clk ( clk ), + .rst_n ( rst_n ), + .echo ( echo ), + .trig ( trig ), + .distance ( distance ) + ); + + initial begin + clk = 1'b0; + forever + #10 clk = !clk; + end + + task request(input integer del,input integer dur); + // int del,dur + @(negedge trig) begin + #(del) echo = 1'b1; + #(dur) echo = 1'b0; + end + endtask // request + + + initial begin + $dumpvars(); + + rst_n = 1'b1; + echo = 1'b0; + + #14 rst_n = 1'b0; + #12 rst_n = 1'b1; + + request(9000,5000); + request(4000,8888); + + #30000 + + $finish; + + end +endmodule // hcsr04 diff --git a/lab_06/src/hcsr04/simulation/modelsim_script.tcl b/lab_06/src/hcsr04/simulation/modelsim_script.tcl new file mode 100644 index 0000000..d8d7a7d --- /dev/null +++ b/lab_06/src/hcsr04/simulation/modelsim_script.tcl @@ -0,0 +1,30 @@ + +# create modelsim working library + +vlib work + +# compile all the Verilog sources + +vlog ../../hcsr04.v +vlog ../hcsr04_tb.v + +set top=hcsr04_tb +# open the testbench module for simulation + +vsim -novopt work.hcsr04_tb + +# add all testbench signals to time diagram + + +add wave -radix bin sim:/hcsr04_tb/clk +add wave -radix bin sim:/hcsr04_tb/rst_n +add wave -radix bin sim:/hcsr04_tb/trig +add wave -radix bin sim:/hcsr04_tb/echo +add wave -radix hex sim:/hcsr04_tb/distance + +# run the simulation + +run -all + +# expand the signals time diagram + diff --git a/lab_06/src/hcsr04/synthesis/de10_lite.qpf b/lab_06/src/hcsr04/synthesis/de10_lite.qpf new file mode 100644 index 0000000..68baac6 --- /dev/null +++ b/lab_06/src/hcsr04/synthesis/de10_lite.qpf @@ -0,0 +1 @@ +# It is OK for this file to be empty, all the settings are in .qsf file diff --git a/lab_06/src/hcsr04/synthesis/de10_lite.qsf b/lab_06/src/hcsr04/synthesis/de10_lite.qsf new file mode 100644 index 0000000..f9e3433 --- /dev/null +++ b/lab_06/src/hcsr04/synthesis/de10_lite.qsf @@ -0,0 +1,94 @@ +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 + +set_global_assignment -name TOP_LEVEL_ENTITY de10_lite + +set_global_assignment -name VERILOG_FILE de10_lite.v +set_global_assignment -name VERILOG_FILE ../../common/led7.v +set_global_assignment -name VERILOG_FILE ../hcsr04.v + +set_global_assignment -name SDC_FILE de10_lite.sdc + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK* +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO* +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_P11 -to CLOCK_50 + +#============================================================ +# KEY +#============================================================ +set_location_assignment PIN_B8 -to KEY[0] + +#============================================================ +# HEX0 +#============================================================ +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] + +#============================================================ +# HEX1 +#============================================================ +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] + + +#============================================================ +# GPIO, GPIO connect to GPIO Default +#============================================================ +set_location_assignment PIN_V10 -to GPIO[0] +set_location_assignment PIN_W10 -to GPIO[1] +set_location_assignment PIN_V9 -to GPIO[2] +set_location_assignment PIN_W9 -to GPIO[3] +set_location_assignment PIN_V8 -to GPIO[4] +set_location_assignment PIN_W8 -to GPIO[5] +set_location_assignment PIN_V7 -to GPIO[6] +set_location_assignment PIN_W7 -to GPIO[7] +set_location_assignment PIN_W6 -to GPIO[8] +set_location_assignment PIN_V5 -to GPIO[9] +set_location_assignment PIN_W5 -to GPIO[10] +set_location_assignment PIN_AA15 -to GPIO[11] +set_location_assignment PIN_AA14 -to GPIO[12] +set_location_assignment PIN_W13 -to GPIO[13] +set_location_assignment PIN_W12 -to GPIO[14] +set_location_assignment PIN_AB13 -to GPIO[15] +set_location_assignment PIN_AB12 -to GPIO[16] +set_location_assignment PIN_Y11 -to GPIO[17] +set_location_assignment PIN_AB11 -to GPIO[18] +set_location_assignment PIN_W11 -to GPIO[19] +set_location_assignment PIN_AB10 -to GPIO[20] +set_location_assignment PIN_AA10 -to GPIO[21] +set_location_assignment PIN_AA9 -to GPIO[22] +set_location_assignment PIN_Y8 -to GPIO[23] +set_location_assignment PIN_AA8 -to GPIO[24] +set_location_assignment PIN_Y7 -to GPIO[25] +set_location_assignment PIN_AA7 -to GPIO[26] +set_location_assignment PIN_Y6 -to GPIO[27] +set_location_assignment PIN_AA6 -to GPIO[28] +set_location_assignment PIN_Y5 -to GPIO[29] +set_location_assignment PIN_AA5 -to GPIO[30] +set_location_assignment PIN_Y4 -to GPIO[31] +set_location_assignment PIN_AB3 -to GPIO[32] +set_location_assignment PIN_Y3 -to GPIO[33] +set_location_assignment PIN_AB2 -to GPIO[34] +set_location_assignment PIN_AA2 -to GPIO[35] +#============================================================ + +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files + diff --git a/lab_06/src/01_counter_simple/synthesis/de2_115.sdc b/lab_06/src/hcsr04/synthesis/de10_lite.sdc similarity index 52% rename from lab_06/src/01_counter_simple/synthesis/de2_115.sdc rename to lab_06/src/hcsr04/synthesis/de10_lite.sdc index 01192ab..fc74ffd 100644 --- a/lab_06/src/01_counter_simple/synthesis/de2_115.sdc +++ b/lab_06/src/hcsr04/synthesis/de10_lite.sdc @@ -1,8 +1,10 @@ -create_clock -period 50MHz [get_ports CLOCK_50] +create_clock -name clk -period 50MHz [get_ports CLOCK_50] derive_clock_uncertainty set_false_path -from * -to [get_ports {HEX0[*]}] set_false_path -from * -to [get_ports {HEX1[*]}] +set_false_path -from * -to [get_ports {GPIO[*]}] set_false_path -from [get_ports {KEY[*]}] -to [all_clocks] +set_false_path -from [get_ports {GPIO[*]}] -to [all_clocks] diff --git a/lab_06/src/hcsr04/synthesis/de10_lite.v b/lab_06/src/hcsr04/synthesis/de10_lite.v new file mode 100644 index 0000000..f2d30fb --- /dev/null +++ b/lab_06/src/hcsr04/synthesis/de10_lite.v @@ -0,0 +1,44 @@ +module de10_lite +( + input CLOCK_50, + input [0:0] KEY, + output [7:0] HEX1, + output [7:0] HEX0, + inout [35:0] GPIO +); + localparam width=8; + + wire key_rst; + wire trig_pin; + wire echo_pin; + wire [width-1:0] distance; + + + assign key_rst = KEY[0]; + assign GPIO[35] = trig_pin; + assign echo_pin = GPIO[33]; + + hcsr04 + #( + .clk_freq ( 50000000 ), + .width ( width ) + ) + hc + ( + .clk ( CLOCK_50 ), + .rst_n ( key_rst ), + .echo ( echo_pin ), + .trig ( trig_pin ), + .distance ( distance ) + ); + + led7 #(.COUNT(2)) seg7 + ( + .data ( distance ), + .leds ( {HEX1,HEX0} ) + ); + + +endmodule // de10_lite + + diff --git a/lab_06/src/led_matrix/synthesis/de10_lite.qpf b/lab_06/src/led_matrix/synthesis/de10_lite.qpf new file mode 100644 index 0000000..68baac6 --- /dev/null +++ b/lab_06/src/led_matrix/synthesis/de10_lite.qpf @@ -0,0 +1 @@ +# It is OK for this file to be empty, all the settings are in .qsf file diff --git a/lab_06/src/led_matrix/synthesis/de10_lite.qsf b/lab_06/src/led_matrix/synthesis/de10_lite.qsf new file mode 100644 index 0000000..48967e8 --- /dev/null +++ b/lab_06/src/led_matrix/synthesis/de10_lite.qsf @@ -0,0 +1,69 @@ +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 + +set_global_assignment -name TOP_LEVEL_ENTITY de10_lite + +set_global_assignment -name VERILOG_FILE de10_lite.v +set_global_assignment -name VERILOG_FILE ../../common/strobe_gen.v +set_global_assignment -name VERILOG_FILE ../../06_shift_reg/shift_reg.v + +set_global_assignment -name SDC_FILE de10_lite.sdc + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK* +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO* +#============================================================ +# CLOCK +#============================================================ + +set_location_assignment PIN_P11 -to CLOCK_50 + +#============================================================ +# KEY +#============================================================ + +set_location_assignment PIN_B8 -to KEY[0] +set_location_assignment PIN_A7 -to KEY[1] + +#============================================================ +# GPIO, GPIO connect to GPIO Default +#============================================================ +set_location_assignment PIN_V10 -to GPIO[0] +set_location_assignment PIN_W10 -to GPIO[1] +set_location_assignment PIN_V9 -to GPIO[2] +set_location_assignment PIN_W9 -to GPIO[3] +set_location_assignment PIN_V8 -to GPIO[4] +set_location_assignment PIN_W8 -to GPIO[5] +set_location_assignment PIN_V7 -to GPIO[6] +set_location_assignment PIN_W7 -to GPIO[7] +set_location_assignment PIN_W6 -to GPIO[8] +set_location_assignment PIN_V5 -to GPIO[9] +set_location_assignment PIN_W5 -to GPIO[10] +set_location_assignment PIN_AA15 -to GPIO[11] +set_location_assignment PIN_AA14 -to GPIO[12] +set_location_assignment PIN_W13 -to GPIO[13] +set_location_assignment PIN_W12 -to GPIO[14] +set_location_assignment PIN_AB13 -to GPIO[15] +set_location_assignment PIN_AB12 -to GPIO[16] +set_location_assignment PIN_Y11 -to GPIO[17] +set_location_assignment PIN_AB11 -to GPIO[18] +set_location_assignment PIN_W11 -to GPIO[19] +set_location_assignment PIN_AB10 -to GPIO[20] +set_location_assignment PIN_AA10 -to GPIO[21] +set_location_assignment PIN_AA9 -to GPIO[22] +set_location_assignment PIN_Y8 -to GPIO[23] +set_location_assignment PIN_AA8 -to GPIO[24] +set_location_assignment PIN_Y7 -to GPIO[25] +set_location_assignment PIN_AA7 -to GPIO[26] +set_location_assignment PIN_Y6 -to GPIO[27] +set_location_assignment PIN_AA6 -to GPIO[28] +set_location_assignment PIN_Y5 -to GPIO[29] +set_location_assignment PIN_AA5 -to GPIO[30] +set_location_assignment PIN_Y4 -to GPIO[31] +set_location_assignment PIN_AB3 -to GPIO[32] +set_location_assignment PIN_Y3 -to GPIO[33] +set_location_assignment PIN_AB2 -to GPIO[34] +set_location_assignment PIN_AA2 -to GPIO[35] + +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files diff --git a/lab_06/src/led_matrix/synthesis/de10_lite.sdc b/lab_06/src/led_matrix/synthesis/de10_lite.sdc new file mode 100644 index 0000000..5e97d29 --- /dev/null +++ b/lab_06/src/led_matrix/synthesis/de10_lite.sdc @@ -0,0 +1,7 @@ +create_clock -name clk -period 50MHz [get_ports CLOCK_50] + +derive_clock_uncertainty + +set_false_path -from * -to [get_ports {GPIO[*]}] + +set_false_path -from [get_ports {KEY[*]}] -to [all_clocks] diff --git a/lab_06/src/led_matrix/synthesis/de10_lite.v b/lab_06/src/led_matrix/synthesis/de10_lite.v new file mode 100644 index 0000000..b3ab563 --- /dev/null +++ b/lab_06/src/led_matrix/synthesis/de10_lite.v @@ -0,0 +1,65 @@ +module de10_lite +( + input CLOCK_50, + input [1:0] KEY, + inout [35:0] GPIO +); + + reg [15:0] matrix; + wire [7:0] rows,cols; + wire push_button; + wire shift_cols; + wire shift_rows; + + assign push_button = ~KEY[1]; + + always@(posedge CLOCK_50) + matrix = { + ~rows[0],~rows[1], cols[1],~rows[7], + cols[3],~rows[2], cols[0],~rows[4], + cols[4], cols[6],~rows[6],~rows[5], + cols[7],~rows[3], cols[5], cols[2] + }; + + assign { + GPIO[24],GPIO[22],GPIO[20],GPIO[18], + GPIO[16],GPIO[14],GPIO[12],GPIO[10], + GPIO[25],GPIO[23],GPIO[21],GPIO[19], + GPIO[17],GPIO[15],GPIO[13],GPIO[11] + } = matrix; + + strobe_gen #(.div(24)) strobe_rows + ( + .clk ( CLOCK_50 ), + .rst_n ( KEY[0] ), + .strobe ( shift_rows ) + ); + + strobe_gen #(.div(24)) strobe_cols + ( + .clk ( CLOCK_50 ), + .rst_n ( KEY[0] ), + .strobe ( shift_cols ) + ); + + shift_reg #(.WIDTH(8)) s_rows + ( + .clk ( CLOCK_50 ), + .rst_n ( KEY[0] ), + .data_in ( push_button ), + .shift_en ( shift_rows ), + .data_out ( rows ), + .serial_out () + ); + + shift_reg #(.WIDTH(8)) s_cols + ( + .clk ( CLOCK_50 ), + .rst_n ( KEY[0] ), + .data_in ( push_button ), + .shift_en ( shift_cols ), + .data_out ( cols ), + .serial_out() + ); + +endmodule // de10_lite diff --git a/lab_06/src/timer/simulation/01_simulate_with_modelsim.bat b/lab_06/src/timer/simulation/01_simulate_with_modelsim.bat new file mode 100644 index 0000000..e69de29 diff --git a/lab_06/src/timer/simulation/01_simulate_with_modelsim.sh b/lab_06/src/timer/simulation/01_simulate_with_modelsim.sh new file mode 100644 index 0000000..e69de29 diff --git a/lab_06/src/timer/simulation/02_simulate_with_icarus.bat b/lab_06/src/timer/simulation/02_simulate_with_icarus.bat new file mode 100644 index 0000000..e69de29 diff --git a/lab_06/src/timer/simulation/02_simulate_with_icarus.sh b/lab_06/src/timer/simulation/02_simulate_with_icarus.sh new file mode 100755 index 0000000..3195fbc --- /dev/null +++ b/lab_06/src/timer/simulation/02_simulate_with_icarus.sh @@ -0,0 +1,14 @@ +#!/usr/bin/env bash +SIM_DIR=sim/; +## Create simulation directory +echo "################################################" +echo "Recreate a temp folder for all simulation files" +echo "################################################" +rm -rf ${SIM_DIR} +mkdir ${SIM_DIR} +cd ${SIM_DIR} + + +iverilog -o timer.out -s timer_tb ../../timer.v ../timer_tb.v +vvp -l timer.log -n timer.out +gtkwave dump.vcd diff --git a/lab_06/src/timer/simulation/modelsim_script.tcl b/lab_06/src/timer/simulation/modelsim_script.tcl new file mode 100644 index 0000000..8d78eeb --- /dev/null +++ b/lab_06/src/timer/simulation/modelsim_script.tcl @@ -0,0 +1,29 @@ + +# create modelsim working library + +vlib work + +# compile all the Verilog sources + +vlog ../../timer.v +vlog ../timer_tb.v + +set top=timer_tb +# open the testbench module for simulation + +vsim -novopt work.timer_tb + +# add all testbench signals to time diagram + + +add wave -radix bin sim:/timer_tb/clk +add wave -radix bin sim:/timer_tb/rst_n +add wave -radix hex sim:/timer_tb/seconds +add wave -radix hex sim:/timer_tb/minuts + +# run the simulation + +run -all + +# expand the signals time diagram + diff --git a/lab_06/src/timer/simulation/timer_tb.v b/lab_06/src/timer/simulation/timer_tb.v new file mode 100644 index 0000000..6cf3b76 --- /dev/null +++ b/lab_06/src/timer/simulation/timer_tb.v @@ -0,0 +1,38 @@ +//Testbench for timer +`timescale 1ns/1ns +module timer_tb; + + reg clk; + reg rst_n; + wire [7:0] seconds; + wire [7:0] minuts; + + // Select slow + localparam clk_sim = 50; + + timer #(.ref_clock(clk_sim)) t1 + ( + .clk ( clk ), + .rst_n ( rst_n ), + .seconds ( seconds ), + .minuts ( minuts ) + ); + + initial begin + clk = 1'b0; + forever #5 clk = ~clk; + end + + + initial begin + $dumpvars(); + + rst_n = 1'b1; + #14 rst_n = 1'b0; + #23 rst_n = 1'b1; + wait(minuts == 8'd59) + #4000 + $finish; + end + + endmodule // timer_tb diff --git a/lab_06/src/timer/synthesis/de10_lite.qpf b/lab_06/src/timer/synthesis/de10_lite.qpf new file mode 100644 index 0000000..68baac6 --- /dev/null +++ b/lab_06/src/timer/synthesis/de10_lite.qpf @@ -0,0 +1 @@ +# It is OK for this file to be empty, all the settings are in .qsf file diff --git a/lab_06/src/timer/synthesis/de10_lite.qsf b/lab_06/src/timer/synthesis/de10_lite.qsf new file mode 100644 index 0000000..dbdd8ef --- /dev/null +++ b/lab_06/src/timer/synthesis/de10_lite.qsf @@ -0,0 +1,84 @@ +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 + + +set_global_assignment -name TOP_LEVEL_ENTITY de10_lite + +set_global_assignment -name VERILOG_FILE de10_lite.v +set_global_assignment -name VERILOG_FILE ../timer.v +set_global_assignment -name VERILOG_FILE ../../common/led7.v +set_global_assignment -name VERILOG_FILE ../../common/bcd.v + +set_global_assignment -name SDC_FILE de10_lite.sdc + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX* +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY* + + +#============================================================ +# CLOCK +#============================================================ + +set_location_assignment PIN_P11 -to CLOCK_50 + +#============================================================ +# KEY +#============================================================ + +set_location_assignment PIN_B8 -to KEY[0] + +#============================================================ +# HEX0 +#============================================================ + +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] + +#============================================================ +# HEX1 +#============================================================ + +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] + +#============================================================ +# HEX2 +#============================================================ + +set_location_assignment PIN_B20 -to HEX2[0] +set_location_assignment PIN_A20 -to HEX2[1] +set_location_assignment PIN_B19 -to HEX2[2] +set_location_assignment PIN_A21 -to HEX2[3] +set_location_assignment PIN_B21 -to HEX2[4] +set_location_assignment PIN_C22 -to HEX2[5] +set_location_assignment PIN_B22 -to HEX2[6] +set_location_assignment PIN_A19 -to HEX2[7] + +#============================================================ +# HEX3 +#============================================================ + +set_location_assignment PIN_F21 -to HEX3[0] +set_location_assignment PIN_E22 -to HEX3[1] +set_location_assignment PIN_E21 -to HEX3[2] +set_location_assignment PIN_C19 -to HEX3[3] +set_location_assignment PIN_C20 -to HEX3[4] +set_location_assignment PIN_D19 -to HEX3[5] +set_location_assignment PIN_E17 -to HEX3[6] +set_location_assignment PIN_D22 -to HEX3[7] + +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_file diff --git a/lab_06/src/04_counter_divider/synthesis/de2_115.sdc b/lab_06/src/timer/synthesis/de10_lite.sdc similarity index 85% rename from lab_06/src/04_counter_divider/synthesis/de2_115.sdc rename to lab_06/src/timer/synthesis/de10_lite.sdc index f080b42..e98a010 100644 --- a/lab_06/src/04_counter_divider/synthesis/de2_115.sdc +++ b/lab_06/src/timer/synthesis/de10_lite.sdc @@ -1,4 +1,4 @@ -create_clock -period 50MHz [get_ports CLOCK_50] +create_clock -name clk -period 50MHz [get_ports] derive_clock_uncertainty diff --git a/lab_06/src/timer/synthesis/de10_lite.v b/lab_06/src/timer/synthesis/de10_lite.v new file mode 100644 index 0000000..a7d1c44 --- /dev/null +++ b/lab_06/src/timer/synthesis/de10_lite.v @@ -0,0 +1,60 @@ +module de10_lite +( + input CLOCK_50, + input [0:0] KEY0, + output [7:0] HEX3, + output [7:0] HEX2, + output [7:0] HEX1, + output [7:0] HEX0 +); + + wire [7:0] sec_bin; + wire [7:0] sec_dec; + wire [7:0] min_bin; + wire [7:0] min_dec; + + + timer #(.ref_clock(50000000)) + my_clock + ( + .clk ( CLOCK_50 ), + .rst_n ( KEY[0] ), + .seconds ( sec_bin ), + .minuts ( min_bin ) + ); + + // Conversion time to decimal system + bcd + #( .IN_WIDTH (8), + .DIGIT (2) + ) + sec_inst + ( + .bin(sec_bin), + .bcd(sec_dec) + ); + + bcd + #( .IN_WIDTH (8), + .DIGIT (2) + ) + min_inst + ( + .bin(min_bin), + .bcd(min_dec) + ); + + // Time on 7segment display + led7 #(.COUNT(2)) sec_led + ( + .data ( sec_dec ), + .leds ( {HEX1,HEX0} ) + ); + + led7 #(.COUNT(2)) min_led + ( + .data ( min_dec ), + .leds ( {HEX3,HEX2} ) + ); + +endmodule // de10_lite diff --git a/lab_06/src/timer/timer.v b/lab_06/src/timer/timer.v new file mode 100644 index 0000000..cfb81f7 --- /dev/null +++ b/lab_06/src/timer/timer.v @@ -0,0 +1,52 @@ +module timer +#( + // Reference clock value in Hz + parameter ref_clock = 50000000 + ) + +( + input clk, + input rst_n, + output reg [7:0] seconds, + output reg [7:0] minuts + ); + + localparam + sec_tick = ref_clock, + period = 60; + + reg [31:0] tick_cnt; + wire tick_en; + wire sec_en; + + //System time + always@(posedge clk or negedge rst_n) + if(!rst_n) + tick_cnt <= 0; + else if(tick_cnt == sec_tick - 1) + tick_cnt <= 0; + else + tick_cnt <= tick_cnt + 1'b1; + + //Seconds + always@(posedge clk or negedge rst_n) + if(!rst_n) + seconds <= 0; + else if(tick_cnt == sec_tick - 1) + if(seconds == period -1) + seconds <= 0; + else + seconds <= seconds + 1'b1; + + // Minuts + always@(posedge clk or negedge rst_n) + if(!rst_n) + minuts <= 0; + else if(seconds == period - 1 && tick_cnt == sec_tick -1) + if(minuts == period -1) + minuts <= 0; + else + minuts <= minuts + 1'b1; + + +endmodule // timer