There are several places in the code where the SystemVerilog capabilities are used in files with simple Verilog, this is critical for Quartus.
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wire rom_image_fifo_ptr_equal = rom_image_fifo_wr_ptr[IMAGE_FIFO_BITS-1:0] == rom_image_fifo_rd_ptr[IMAGE_FIFO_BITS-1:0]; |
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logic [7:0] fd_dma_rd_ptr = fifo_word_counter - 10'd31; |
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logic [7:0] dbyte = { fifo_out[14], fifo_out[12], fifo_out[10], fifo_out[8], |
But even if you change logic to wire, Quartus can't compile this code correctly and generates structures containing several thousand LE.
There are several places in the code where the SystemVerilog capabilities are used in files with simple Verilog, this is critical for Quartus.
NanoMig/src/misc/sd_card.v
Line 246 in 88bd64a
NanoMig/src/minimig-aga/paula_floppy.v
Line 208 in 88bd64a
NanoMig/src/minimig-aga/paula_floppy.v
Line 778 in 88bd64a
But even if you change logic to wire, Quartus can't compile this code correctly and generates structures containing several thousand LE.