applies clang-format

Author: eyck

src/iss/arch/riscv_hart_common.h

@@ -512,16 +512,16 @@ template <typename BASE = logging::disass> struct riscv_hart_common : public BAS
     uint64_t fromhost = std::numeric_limits<uint64_t>::max();
     std::stringstream io_buf;
 
-    void enable_disass_output(bool enable){
+    void enable_disass_output(bool enable) {
         if(enable)
-            this->disass_func = util::delegate<void(uint64_t, std::string const&, bool)>::from<this_class, &this_class::print_disass_output>(this);
+            this->disass_func =
+                util::delegate<void(uint64_t, std::string const&, bool)>::from<this_class, &this_class::print_disass_output>(this);
         else
             this->disass_func = util::delegate<void(uint64_t, std::string const&, bool)>(nullptr);
     }
 
     void set_semihosting_callback(semihosting_cb_t<reg_t> cb) { semihosting_cb = cb; };
 
-
     std::pair<uint64_t, bool> load_file(std::string const& name, int type) override {
         return std::make_pair(entry_address, read_elf_file(name, sizeof(reg_t) == 4 ? ELFIO::ELFCLASS32 : ELFIO::ELFCLASS64));
     }
@@ -624,10 +624,10 @@ template <typename BASE = logging::disass> struct riscv_hart_common : public BAS
         static CONSTEXPR char const* fmt_str =
             sizeof(reg_t) == 4 ? "0x{:08x}    {:40} [p:{};s:0x{:02x};i:{};c:{}]" : "0x{:012x}    {:40} [p:{};s:0x{:04x};i:{};c:{}]";
         if(printpc) {
-            CLOG(INFO, disass)<<fmt::format(fmt_str, pc, string, lvl[this->reg.PRIV], (reg_t)this->state.mstatus, this->reg.icount,
-                this->reg.cycle + cycle_offset);
+            CLOG(INFO, disass) << fmt::format(fmt_str, pc, string, lvl[this->reg.PRIV], (reg_t)this->state.mstatus, this->reg.icount,
+                                              this->reg.cycle + cycle_offset);
         } else {
-            CLOG(INFO, disass)<<string;
+            CLOG(INFO, disass) << string;
         }
     };
 
@@ -944,7 +944,7 @@ template <typename BASE = logging::disass> struct riscv_hart_common : public BAS
             .read_csr = [this](unsigned addr, reg_t& val) -> iss::status { return read_csr(addr, val); },
             .write_csr = [this](unsigned addr, reg_t val) -> iss::status { return write_csr(addr, val); },
             .get_csr = [this](unsigned addr) -> reg_t { return csr.at(addr); },
-            .set_csr = [this](unsigned addr, reg_t val) -> void { csr.at(addr)=val;},
+            .set_csr = [this](unsigned addr, reg_t val) -> void { csr.at(addr) = val; },
             .exec_htif = [this](uint8_t const* data, unsigned length) -> iss::status { return execute_htif(data, length); },
             .raise_trap =
                 [this](uint16_t trap_id, uint16_t cause, reg_t fault_data) {
@@ -1018,8 +1018,8 @@ template <typename BASE = logging::disass> struct riscv_hart_common : public BAS
     void set_max_irq_num(unsigned i) { mcause_max_irq = std::max(1u << util::ilog2(i), 16u); }
 
     void set_clint_custom_irq_num(unsigned num) {
-        assert(num<=traits<BASE>::XLEN);
-        clint_custom_irq_mask=std::numeric_limits<reg_t>::max()>>(traits<BASE>::XLEN-num);
+        assert(num <= traits<BASE>::XLEN);
+        clint_custom_irq_mask = std::numeric_limits<reg_t>::max() >> (traits<BASE>::XLEN - num);
     }
 
 protected:

src/iss/arch/riscv_hart_m_p.h

@@ -77,7 +77,7 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_m_p : pub
 
     void reset(uint64_t address) override;
 
-    void enable_disass(bool enable) {riscv_hart_common<BASE>::enable_disass_output(enable);}
+    void enable_disass(bool enable) { riscv_hart_common<BASE>::enable_disass_output(enable); }
 
     iss::status read(const addr_t& addr, const unsigned length, uint8_t* const data);
     iss::status write(const addr_t& addr, const unsigned length, const uint8_t* const data);
@@ -461,12 +461,10 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
     if((flags & 0xffffffff) != 0xffffffff) {
         if(trap_id) {
             auto irq_str = cause < this->irq_str.size() ? this->irq_str.at(cause) : "Unknown";
-            this->disass_output(
-                 fmt::format("Interrupt with cause '{}' ({}) occurred  at address {}", irq_str, cause, buffer.data()));
+            this->disass_output(fmt::format("Interrupt with cause '{}' ({}) occurred  at address {}", irq_str, cause, buffer.data()));
         } else {
             auto irq_str = cause < this->trap_str.size() ? this->trap_str.at(cause) : "Unknown";
-            this->disass_output(
-                 fmt::format("Trap with cause '{}' ({}) occurred  at address {}", irq_str, cause, buffer.data()));
+            this->disass_output(fmt::format("Trap with cause '{}' ({}) occurred  at address {}", irq_str, cause, buffer.data()));
         }
     }
     // reset trap state

src/iss/arch/riscv_hart_msu_vp.h

@@ -90,7 +90,7 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_msu_vp :
 
     void reset(uint64_t address) override;
 
-    void enable_disass(bool enable) {riscv_hart_common<BASE>::enable_disass_output(enable);}
+    void enable_disass(bool enable) { riscv_hart_common<BASE>::enable_disass_output(enable); }
 
     iss::status read(const addr_t& addr, const unsigned length, uint8_t* const data);
     iss::status write(const addr_t& addr, const unsigned length, const uint8_t* const data);
@@ -417,7 +417,8 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_msu_vp<BASE, FE
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_msu_vp<BASE, FEAT>::write_ie(unsigned addr, reg_t val) {
     // generate mask from allowed writable bits, the number of custom interrupts and the available ie bits
-    auto mask = riscv_hart_common<BASE>::get_irq_mask((addr >> 8) & 0x3) & this->clint_custom_irq_mask & (FEAT & FEAT_EXT_N?0xbbb:0xaaa);
+    auto mask =
+        riscv_hart_common<BASE>::get_irq_mask((addr >> 8) & 0x3) & this->clint_custom_irq_mask & (FEAT & FEAT_EXT_N ? 0xbbb : 0xaaa);
     this->csr[mie] = (this->csr[mie] & ~mask) | (val & mask);
     check_interrupt();
     return iss::Ok;
@@ -497,8 +498,7 @@ template <typename BASE, features_e FEAT> void riscv_hart_msu_vp<BASE, FEAT>::ch
     }
 }
 
-template <typename BASE, features_e FEAT>
-uint64_t riscv_hart_msu_vp<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t tval) {
+template <typename BASE, features_e FEAT> uint64_t riscv_hart_msu_vp<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t tval) {
     // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
     // calculate and write mcause val
     if(flags == std::numeric_limits<uint32_t>::max())
@@ -638,12 +638,10 @@ uint64_t riscv_hart_msu_vp<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr
     if((flags & 0xffffffff) != 0xffffffff) {
         if(trap_id) {
             auto irq_str = cause < this->irq_str.size() ? this->irq_str.at(cause) : "Unknown";
-            this->disass_output(
-                 fmt::format("Interrupt with cause '{}' ({}) occurred  at address {}", irq_str, cause, buffer.data()));
+            this->disass_output(fmt::format("Interrupt with cause '{}' ({}) occurred  at address {}", irq_str, cause, buffer.data()));
         } else {
             auto irq_str = cause < this->trap_str.size() ? this->trap_str.at(cause) : "Unknown";
-            this->disass_output(
-                 fmt::format("Trap with cause '{}' ({}) occurred  at address {}", irq_str, cause, buffer.data()));
+            this->disass_output(fmt::format("Trap with cause '{}' ({}) occurred  at address {}", irq_str, cause, buffer.data()));
         }
     }
     // reset trap this->state
@@ -686,7 +684,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_msu_vp<BASE, FEAT>
         // sets the pc to the value stored in the x epc register.
         this->reg.NEXT_PC = this->csr[uepc | inst_priv << 8];
         this->disass_output(
-             fmt::format("Executing xRET, changing privilege level from {} to {}", this->lvl[cur_priv], this->lvl[this->reg.PRIV]));
+            fmt::format("Executing xRET, changing privilege level from {} to {}", this->lvl[cur_priv], this->lvl[this->reg.PRIV]));
         check_interrupt();
     }
     this->reg.trap_state = this->reg.pending_trap;

src/iss/arch/riscv_hart_mu_p.h

@@ -80,7 +80,7 @@ template <typename BASE, features_e FEAT = FEAT_NONE> class riscv_hart_mu_p : pu
 
     void reset(uint64_t address) override;
 
-    void enable_disass(bool enable) {riscv_hart_common<BASE>::enable_disass_output(enable);}
+    void enable_disass(bool enable) { riscv_hart_common<BASE>::enable_disass_output(enable); }
 
     iss::status read(const addr_t& addr, const unsigned length, uint8_t* const data);
     iss::status write(const addr_t& addr, const unsigned length, const uint8_t* const data);
@@ -347,7 +347,8 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
 
 template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::write_ie(unsigned addr, reg_t val) {
     // generate mask from allowed writable bits, the number of custom interrupts and the available ie bits
-    auto mask = riscv_hart_common<BASE>::get_irq_mask((addr >> 8) & 0x3) & this->clint_custom_irq_mask & (FEAT & FEAT_EXT_N?0x999:0x888);
+    auto mask =
+        riscv_hart_common<BASE>::get_irq_mask((addr >> 8) & 0x3) & this->clint_custom_irq_mask & (FEAT & FEAT_EXT_N ? 0x999 : 0x888);
     this->csr[mie] = (this->csr[mie] & ~mask) | (val & mask);
     check_interrupt();
     return iss::Ok;
@@ -572,7 +573,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
         // sets the pc to the value stored in the x epc register.
         this->reg.NEXT_PC = this->csr[uepc | inst_priv << 8];
         this->disass_output(
-             fmt::format("Executing xRET, changing privilege level from {} to {}", this->lvl[cur_priv], this->lvl[this->reg.PRIV]));
+            fmt::format("Executing xRET, changing privilege level from {} to {}", this->lvl[cur_priv], this->lvl[this->reg.PRIV]));
         check_interrupt();
     }
     this->reg.trap_state = this->reg.pending_trap;

src/iss/mem/clic.h

@@ -144,14 +144,14 @@ template <typename WORD_TYPE> struct clic : public memory_elem {
 private:
     iss::status read_mem(addr_t const& addr, unsigned length, uint8_t* data) {
         auto end_addr = addr.val - 1 + length;
-        if(addr.space == 0 && addr.val<=end_addr && addr.val >= cfg.clic_base && end_addr <= (cfg.clic_base + 0x7fff))
+        if(addr.space == 0 && addr.val <= end_addr && addr.val >= cfg.clic_base && end_addr <= (cfg.clic_base + 0x7fff))
             return read_clic(addr.val, length, data);
         return down_stream_mem.rd_mem(addr, length, data);
     }
 
     iss::status write_mem(addr_t const& addr, unsigned length, uint8_t const* data) {
         auto end_addr = addr.val - 1 + length;
-        if(addr.space == 0 && addr.val<=end_addr && addr.val >= cfg.clic_base && end_addr <= (cfg.clic_base + 0x7fff))
+        if(addr.space == 0 && addr.val <= end_addr && addr.val >= cfg.clic_base && end_addr <= (cfg.clic_base + 0x7fff))
             return write_clic(addr.val, length, data);
         return down_stream_mem.wr_mem(addr, length, data);
     }
@@ -198,37 +198,37 @@ template <typename WORD_TYPE> struct clic : public memory_elem {
     iss::status write_xtvec(unsigned addr, reg_t val) {
         hart_if.set_csr(addr, val);
         if((val & 0x3) != 0x3) {
-            clic_mprev_lvl = 0xff>>cfg.clic_int_ctl_bits;
-            clic_uprev_lvl = 0xff>>cfg.clic_int_ctl_bits;
+            clic_mprev_lvl = 0xff >> cfg.clic_int_ctl_bits;
+            clic_uprev_lvl = 0xff >> cfg.clic_int_ctl_bits;
         }
         return iss::Ok;
     }
 
     iss::status read_cause(unsigned addr, reg_t& val) {
         val = hart_if.get_csr(addr) & ((1UL << (WORD_LEN - 1)) | (hart_if.max_irq - 1));
         auto xtvec = hart_if.get_csr(arch::mtvec);
-        if((xtvec& 0x3) == 0x3) {
-            if(addr == arch::mcause) { //mcause access
-                val |= hart_if.state.mstatus.MPP<<28 | hart_if.state.mstatus.MPIE<<27 |clic_mprev_lvl<<16;
-            } else if(addr ==arch::ucause) {
-                val |= hart_if.state.mstatus.UPIE<<27 | clic_uprev_lvl<<16;
+        if((xtvec & 0x3) == 0x3) {
+            if(addr == arch::mcause) { // mcause access
+                val |= hart_if.state.mstatus.MPP << 28 | hart_if.state.mstatus.MPIE << 27 | clic_mprev_lvl << 16;
+            } else if(addr == arch::ucause) {
+                val |= hart_if.state.mstatus.UPIE << 27 | clic_uprev_lvl << 16;
             }
         }
         return iss::Ok;
     }
 
     iss::status write_cause(unsigned addr, reg_t val) {
         auto mask = ((1UL << (WORD_LEN - 1)) | (hart_if.max_irq - 1));
-        hart_if.set_csr(addr,(val & mask) | (hart_if.get_csr(addr) & ~mask));
+        hart_if.set_csr(addr, (val & mask) | (hart_if.get_csr(addr) & ~mask));
         auto xtvec = hart_if.get_csr(arch::mtvec);
         if((xtvec & 0x3) == 0x3) {
-            if(addr == arch::mcause){ //mcause access
-                hart_if.state.mstatus.MPIE = (val>>27)&1;
-                clic_mprev_lvl = ((val >> 16) & 0xff) | 0xff>>cfg.clic_int_ctl_bits;
-                hart_if.state.mstatus.MPP = (val <<28)&0x3;
-            } else if(addr ==arch::ucause) {
-                hart_if.state.mstatus.UPIE = (val>>27)&1;
-                clic_uprev_lvl = ((val >> 16) & 0xff) | 0xff>>cfg.clic_int_ctl_bits;
+            if(addr == arch::mcause) { // mcause access
+                hart_if.state.mstatus.MPIE = (val >> 27) & 1;
+                clic_mprev_lvl = ((val >> 16) & 0xff) | 0xff >> cfg.clic_int_ctl_bits;
+                hart_if.state.mstatus.MPP = (val << 28) & 0x3;
+            } else if(addr == arch::ucause) {
+                hart_if.state.mstatus.UPIE = (val >> 27) & 1;
+                clic_uprev_lvl = ((val >> 16) & 0xff) | 0xff >> cfg.clic_int_ctl_bits;
             }
         }
         return iss::Ok;

src/sysc/core2sc_adapter.h

@@ -96,10 +96,11 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
 
     void enable_disass(bool enable) override {
         if(enable)
-            this->disass_func = util::delegate<void(uint64_t, std::string const&, bool)>::from<this_class, &this_class::record_n_print_disass>(this);
+            this->disass_func =
+                util::delegate<void(uint64_t, std::string const&, bool)>::from<this_class, &this_class::record_n_print_disass>(this);
         else
-            this->disass_func = util::delegate<void(uint64_t, std::string const&, bool)>::from<this_class, &this_class::record_n_print_disass>(nullptr);
-
+            this->disass_func =
+                util::delegate<void(uint64_t, std::string const&, bool)>::from<this_class, &this_class::record_n_print_disass>(nullptr);
     }
 
     void register_unknown_instr_handler(util::delegate<iss::arch_if::unknown_instr_cb_t> handler) override {
@@ -163,14 +164,15 @@ template <typename PLAT> class core2sc_adapter : public PLAT, public sc2core_if
     }
 
     void record_n_print_disass(uint64_t pc, std::string const& str, bool printpc) {
-        if(!printpc) owner->disass_output(pc, str);
-        static CONSTEXPR char const* fmt_str =
-            sizeof(reg_t) == 4 ? "[disass] 0x{:08x}    {:40} [p:{};s:0x{:02x};i:{};c:{}]" : "[disass] 0x{:012x}    {:40} [p:{};s:0x{:04x};i:{};c:{}]";
+        if(!printpc)
+            owner->disass_output(pc, str);
+        static CONSTEXPR char const* fmt_str = sizeof(reg_t) == 4 ? "[disass] 0x{:08x}    {:40} [p:{};s:0x{:02x};i:{};c:{}]"
+                                                                  : "[disass] 0x{:012x}    {:40} [p:{};s:0x{:04x};i:{};c:{}]";
         if(printpc) {
-            SCCINFO(owner->hier_name())<<fmt::format(fmt_str, pc, str, this->lvl[this->reg.PRIV], (reg_t)this->state.mstatus, this->reg.icount,
-                this->reg.cycle + this->cycle_offset);
+            SCCINFO(owner->hier_name()) << fmt::format(fmt_str, pc, str, this->lvl[this->reg.PRIV], (reg_t)this->state.mstatus,
+                                                       this->reg.icount, this->reg.cycle + this->cycle_offset);
         } else {
-            SCCINFO(owner->hier_name())<<"[disass] " <<str;
+            SCCINFO(owner->hier_name()) << "[disass] " << str;
         }
     };
 

src/sysc/core_complex.cpp

@@ -233,7 +233,7 @@ template <unsigned int BUSWIDTH, typename QK> void core_complex<BUSWIDTH, QK>::i
 #if SC_VERSION_MAJOR > 2
     sensitive << clint_irq_i;
 #else
-    for(auto& s:clint_irq_i)
+    for(auto& s : clint_irq_i)
         sensitive << s;
 #endif
 #endif

src/sysc/core_complex.h

@@ -218,12 +218,12 @@ class core_complex : public sc_core::sc_module, public scc::traceable, public co
         return finish_evt;
     }
 
-    void register_csr_rd(unsigned csr_addr, sc2core_if::rd_csr_f &func) {
+    void register_csr_rd(unsigned csr_addr, sc2core_if::rd_csr_f& func) {
         assert(core != nullptr);
         core->register_csr_rd(csr_addr, func);
     }
 
-    void register_csr_wr(unsigned csr_addr, sc2core_if::wr_csr_f &func) {
+    void register_csr_wr(unsigned csr_addr, sc2core_if::wr_csr_f& func) {
         assert(core != nullptr);
         core->register_csr_wr(csr_addr, func);
     }

src/sysc/core_complex_if.h

@@ -33,8 +33,8 @@
 #ifndef _SYSC_CORE_COMPLEX__IF_H_
 #define _SYSC_CORE_COMPLEX__IF_H_
 
-#include <iss/vm_types.h>
 #include <iss/mem/clic.h>
+#include <iss/vm_types.h>
 #include <scc/signal_opt_ports.h>
 #include <util/delegate.h>
 
@@ -45,7 +45,7 @@ struct core_complex_if {
     virtual ~core_complex_if() = default;
 
     virtual iss::mem::clic_config get_clic_config() {
-        return iss::mem::clic_config{.clic_base=0, .clic_int_ctl_bits=0, .clic_num_irq=0, .clic_num_trigger=0, .nmode=false};
+        return iss::mem::clic_config{.clic_base = 0, .clic_int_ctl_bits = 0, .clic_num_irq = 0, .clic_num_trigger = 0, .nmode = false};
     }
 
     virtual bool read_mem(const iss::addr_t& addr, unsigned length, uint8_t* const data) = 0;

src/sysc/instr_recorder.h

@@ -2,9 +2,9 @@
 
 #include "scv-tr/scv_tr.h"
 #include <rigtorp/SPSCQueue.h>
+#include <scc/utilities.h>
 #include <tlm/scc/quantum_keeper.h>
 #include <tlm/scc/scv/tlm_recording_extension.h>
-#include <scc/utilities.h>
 #ifdef HAS_SCV
 #include <scv.h>
 #else