Memory In Fabrication V2

[roryyamm]

All the way back in 1.12, I made something I'm rather proud of: A 16-address RAM chip. Worked pretty well, too.

Yesterday, I learned this mod updated to 1.20, and while the new IC system was far more limited, I was more than happy to try and make something like what I did in 1.12. I managed to squeeze a single RAM address of the same design into the 14x14 space currently provided, complete with a rendition of the same pulse generator, only to find that such a system now faces… problems.

Is there a way to make this RAM design work?

[MrTJP]

Hi! So the fabrication system has been significantly reworked. In the older versions, you were basically creating the circuit in the same way as you would in-world with real gate blocks and wires. The entire thing was actually simulated in real time, so ICs were just as performance hungry as building large circuits using full blocks.

Now, it's a little different. The circuit gets analyzed and simplified into a logic-only representation with gets rid of wire-to-wire propagation delays, and some other stuff you get with in-world redstone. It is much more performant, but there's a few rules you need to follow now. In this case, the one you are breaking is the Multiple Drivers rule: A single input of any gate may only be controlled by a single output of another.

You basically have 2 or more gates outputting to a single wire, and that wire is connected to some other gate's input (the ones highlighted in red). To get around this, you need to use something like an OR gate to "combine" the signals before feeding it into those highlighted gates.

I know the dimensions are a bit small. Fabrication is not feature complete yet. Adjusting the design size and multiple layers is one of the next things I will work on as soon as I get time to do so.

Also, I can't believe someone bothered to make a nice texture pack that works with Fabrication, considering the assets are a complete mess at the moment :)

[roryyamm]

Upon further playing around with things, I was able to correct the issues with the Multiple Drivers rule… at the cost of the register's ability to store data.

Seems the non-kosher loop between the Transparent Cells and AND gates was essential in writing to the cell. I cannot think of a RAM design that fits in the space provided, plays nice with this new rule, and actually works.

Is there anything resembling a timetable for implementing 3D and bigger design sizes?