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feat: add example pc file and testbench (#391)
* Update nm4207.md * Create pc.v * Add files via upload
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‎src/getting_started/onboarding/RiSC-16/pc.v‎

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module pc (
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input clk,
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input rst_n,
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input [1:0] MUX_output, // Controlled by Control module
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input [15:0] pc_plus1,
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input [15:0] pc_plus1_imm,
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input [15:0] alu_out, // The output from regB that has been passed through the ALU
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output [15:0] nxt_instr
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);
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reg [15:0] pc_reg; // Internal Register to hold state of pc
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assign nxt_instr = pc_reg; // Assigns output to be linked to pc_reg
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always @(posedge clk or negedge rst_n)
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begin
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if (!rst_n)
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begin
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// On reset, the program counter is initialized to the starting address 0.
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pc_reg <= 16'h0000;
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end
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else
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begin
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// On a clock edge, the next value of the PC is determined by the MUX selector.
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case (MUX_output)
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2'b00:
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pc_reg <= pc_plus1;
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2'b01:
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pc_reg <= pc_plus1_imm;
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2'b10:
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pc_reg <= alu_out;
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default:
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pc_reg <= pc_plus1; // safety
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endcase
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end
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end
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endmodule

‎src/getting_started/onboarding/RiSC-16/pc_tb.v‎

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// Testbench for the Program Counter (pc) module
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`timescale 1ns / 1ps
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module pc_tb;
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// Inputs to the DUT (Device Under Test)
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reg clk;
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reg rst_n;
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reg [1:0] MUX_output;
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reg [15:0] pc_plus1;
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reg [15:0] pc_plus1_imm;
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reg [15:0] alu_out;
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// Output from the DUT
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wire [15:0] nxt_instr;
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// Instantiate the Program Counter module
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pc uut (
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.clk(clk),
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.rst_n(rst_n),
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.MUX_output(MUX_output),
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.pc_plus1(pc_plus1),
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.pc_plus1_imm(pc_plus1_imm),
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.alu_out(alu_out),
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.nxt_instr(nxt_instr)
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);
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// Clock generation: 100MHz clock (10ns period)
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always #5 clk = ~clk;
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// Test sequence
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initial begin
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// 1. Initial state setup
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$display("T=%0t: [SETUP] Initializing testbench...", $time);
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clk = 0;
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rst_n = 1;
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MUX_output = 2'b00;
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pc_plus1 = 16'h0000;
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pc_plus1_imm = 16'h0000;
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alu_out = 16'h0000;
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#10; // Wait for a moment
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// 2. Test Case: Asynchronous Reset
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$display("T=%0t: [TEST] Asserting active-low reset.", $time);
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rst_n = 0;
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#10; // Hold reset for a short period
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if (nxt_instr == 16'h0000) begin
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$display("T=%0t: [PASS] PC reset to 0x%h as expected.", $time, nxt_instr);
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end else begin
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$display("T=%0t: [FAIL] PC is 0x%h, expected 0x0000.", $time, nxt_instr);
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end
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#10;
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rst_n = 1; // De-assert reset
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$display("T=%0t: [SETUP] De-asserting reset.", $time);
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// 3. Test Case: Sequential Increment (MUX_output = 00)
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$display("\n T=%0t: [TEST] Testing sequential increment (MUX_output = 2'b00).", $time);
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MUX_output = 2'b00;
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pc_plus1 = 16'h0001;
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@(posedge clk);
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#1;
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if (nxt_instr === 16'h0001) begin
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$display("T=%0t: [PASS] PC incremented to 0x%h.", $time, nxt_instr);
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end else begin
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$display("T=%0t: [FAIL] PC is 0x%h, expected 0x0001.", $time, nxt_instr);
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end
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pc_plus1 = 16'h0002;
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@(posedge clk);
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#1;
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if (nxt_instr === 16'h0002) begin
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$display("T=%0t: [PASS] PC incremented to 0x%h.", $time, nxt_instr);
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end else begin
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$display("T=%0t: [FAIL] PC is 0x%h, expected 0x0002.", $time, nxt_instr);
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end
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// 4. Test Case: Branch with Immediate (MUX_output = 01)
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$display("\n T=%0t: [TEST] Testing branch with immediate (MUX_output = 2'b01).", $time);
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MUX_output = 2'b01;
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pc_plus1_imm = 16'h1234;
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// Set other inputs to different values to ensure they aren't selected
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pc_plus1 = 16'hFFFF;
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alu_out = 16'hEEEE;
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@(posedge clk);
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#1;
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if (nxt_instr === 16'h1234) begin
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$display("T=%0t: [PASS] PC branched to immediate address 0x%h.", $time, nxt_instr);
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end else begin
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$display("T=%0t: [FAIL] PC is 0x%h, expected 0x1234.", $time, nxt_instr);
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end
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// 5. Test Case: Jump via ALU (MUX_output = 10)
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$display("\n T=%0t: [TEST] Testing jump via ALU output (MUX_output = 2'b10).", $time);
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MUX_output = 2'b10;
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alu_out = 16'hABCD;
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// Set other inputs to different values
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pc_plus1 = 16'hFFFF;
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pc_plus1_imm = 16'hEEEE;
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@(posedge clk);
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#1;
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if (nxt_instr === 16'hABCD) begin
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$display("T=%0t: [PASS] PC jumped to ALU address 0x%h.", $time, nxt_instr);
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end else begin
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$display("T=%0t: [FAIL] PC is 0x%h, expected 0xABCD.", $time, nxt_instr);
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end
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// 6. Test Case: Back-to-back operations
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$display("\n T=%0t: [TEST] Testing mixed back-to-back operations.", $time);
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// a. Increment
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MUX_output = 2'b00;
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pc_plus1 = 16'hABCE;
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@(posedge clk);
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#1;
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$display("T=%0t: [INFO] Current PC: 0x%h (After increment)", $time, nxt_instr);
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// b. Jump
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MUX_output = 2'b10;
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alu_out = 16'hBEEF;
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@(posedge clk);
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#1;
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$display("T=%0t: [INFO] Current PC: 0x%h (After jump)", $time, nxt_instr);
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// c. Branch
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MUX_output = 2'b01;
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pc_plus1_imm = 16'hCAFE;
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@(posedge clk);
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#1;
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$display("T=%0t: [INFO] Current PC: 0x%h (After branch)", $time, nxt_instr);
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if (nxt_instr !== 16'hCAFE) begin
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$display("T=%0t: [FAIL] Back-to-back sequence failed. PC is 0x%h, expected 0xCAFE.", $time, nxt_instr);
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end else begin
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$display("T=%0t: [PASS] Back-to-back sequence successful.", $time);
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end
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// 7. Test Case: Undefined MUX select (2'b11)
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// Since the module's case statement does not define 2'b11, it should perform the default
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// of incrementing the PC
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$display("\n T=%0t: [TEST] Testing undefined MUX select (2'b11).", $time);
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MUX_output = 2'b11;
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pc_plus1 = 16'h0009; // Change inputs to see if they are ignored
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pc_plus1_imm = 16'h000A;
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alu_out = 16'h000B;
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@(posedge clk);
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#1;
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if (nxt_instr === 16'h0009) begin
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$display("T=%0t: [PASS] PC correctly incremented to PC+1 at 16'h0009.", $time, nxt_instr);
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end else begin
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$display("T=%0t: [FAIL] PC changed to 16'h000A or 16'h000B, expected it to go to 16'h0009.", $time, nxt_instr);
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end
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// 8. Test Case: Asynchronous Reset again
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$display("\n T=%0t: [TEST] Asserting active-low reset.", $time);
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rst_n = 0;
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#10; // Hold reset for a short period
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if (nxt_instr == 16'h0000) begin
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$display("T=%0t: [PASS] PC reset to 0x%h as expected.", $time, nxt_instr);
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end else begin
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$display("T=%0t: [FAIL] PC is 0x%h, expected 0x0000.", $time, nxt_instr);
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end
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#10;
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rst_n = 1; // De-assert reset
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$display("T=%0t: [SETUP] De-asserting reset.", $time);
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$display("\n T=%0t: [INFO] All tests completed.", $time);
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$finish; // End simulation
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end
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// Optional: Monitor to see signal changes at every time step
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// initial begin
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// $monitor("T=%0t | clk=%b rst_n=%b | MUX_sel=%b | pc+1=%h pc+1+imm=%h alu_out=%h | nxt_instr_addr=%h",
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// $time, clk, rst_n, MUX_output, pc_plus1, pc_plus1_imm, alu_out, nxt_instr);
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// end
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endmodule

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