docs(dn): Darren Kuo semeseter

Author: dareminion

src/design_notebooks/2024spring/dk4461.md

@@ -1,14 +1,15 @@
 # Darren's Design Notebook
 
-## Week of Febuary 2nd, 2024
+## Week of February 2nd, 2024
 
 ### Project Work
 
 * Created Design notebook for Spring 2024
 
+#### Comments
 This was a good refesher of how to use git, and work with repos, and forks. Also had to spend some time getting WSL to run again after running into issues with Hyper-V on my system.
 
-## Week of Febuary 9th, 2024
+## Week of February 9th, 2024
 
 ### Project Work
 
@@ -18,4 +19,137 @@ This was a good refesher of how to use git, and work with repos, and forks. Also
 
 * When working on the forked repository I need to remember to create a branch first.
 * Asked Vito for some basic help with fixing the mistake of not making a branch first as well as fixing a Cmake issue in Lab 1.
-* Rishayk helped with locating a compilier issue which was just needing to install gcc/g++
+* Rishyak helped with locating a compiler issue which was just needing to install gcc/g++
+  
+## Week of February 16th, 2024
+
+### Project Work
+
+* Completed Exercise 1 and 2 of Onboarding [Lab 2](https://github.com/dareminion/onboarding-lab-2/commit/f320d036a9d8e395a5dbe97bba59f3d622ab18f9#diff-07bdf5b35bcdd1f94e7d819c7ddb65d58fbe554e0918b12f4bf9eadf5e2482e6)
+  
+#### Comments
+
+* Worked on during weekly meeting with help of Vito
+* Ran into some cmakelists.txt issues
+* Refreshed a little on Verilog assign statments
+
+## Week of February 23rd, 2024
+
+### Project Work
+
+* Finished [Lab 2](https://github.com/dareminion/onboarding-lab-2)
+
+#### Comments
+
+* Worked with Rishyak on Exercises 3 and 4
+* Refresh on Verliog always and comb blocks
+* Asked Vito for help on some git and some cmake issues.
+
+## Week of March 1st, 2024
+
+### Project Work
+
+* Started Lab 3 Exercise 1
+
+#### Comments
+
+* Asked Vito during weekly meeting about how to start writing a test for Module 1 which tested simple logic
+* Ran into some issues with the for loop inside of the test
+* Will make neater for loops in the future, or avoid them when possible
+
+## Week of March 8th, 2024
+
+### Project Work
+
+* Continued Lab 3 Exercise 1
+
+#### Comments
+
+* After getting the for loops to run, there were still comparison errors with the logic of the tests
+* Troubleshooting with Vito resulted in some variable declaration issues in C++
+* This took way too long
+
+## Week of March 15th, 2024
+
+### Project Work
+
+* Finished Lab 3 [Exercise 1](https://github.com/NYU-Processor-Design/onboarding-lab-3/commit/3c4739cafb026a2197bfbd29fbf180c61d702722)
+
+#### Comments
+
+* Commit above includes Exercise 2, I need to get in the habit of commiting more often
+* Even though these labs are primarily done locally, commiting more often would allow for ease of work from multiple locations
+
+## Week of March 29th
+
+### Project Work
+
+* Started Lab 3 Exercise 2
+    * Same commit as from the previous week due to my git incompetence
+
+#### Comments
+
+* Vito gave me a quick lesson on how to get the value of a bit by shifting it and then "anding" it
+    * `uint16_t val = (model.out >> 0) & 1;`
+* Learned how to test a register without going through every possible value, rather by testing each bit of the register
+* While test is running and passing, the test could be more comprehensive
+
+## Week of April 5th
+
+### Project Work
+
+* Update ReadME for [Lab 2](https://github.com/NYU-Processor-Design/onboarding-lab-2/commit/1edbc795b286146f185f8bd3ca507ec079b8dbdc)
+* Update ReadME for [Lab 3](https://github.com/NYU-Processor-Design/onboarding-lab-3/commit/9ca3e0de67b53b99ad33551860dea85c3645f43f)
+
+#### Comments
+* Just needed to fill out the ReadMe for Lab 2
+* While Lab 3 is still unfinished, I was able to answer part of the ReadME and thought I would update it alongside Lab 2
+
+## Week of April 12th
+
+### Project Work
+
+* Research into what OpenRAM is
+* Went through the Git Repo for [OpenRAM](https://github.com/VLSIDA/OpenRAM)
+* Watched a [video](https://www.youtube.com/watch?v=Kr3U2Nz-UIc) on a presentation on OpenRAM
+
+#### Comments
+
+* I never quite understood what I was looking at, other than that OpenRAM is a memory compilier, and can produce a file for SPICE simulators to use
+* Stumbled upon a Cornell Grad Git page on OpenRAM simulation, showed me what OpenRAM can generate, which was quite interesting
+
+## Week of April 19th
+
+### Project Work
+
+* Look at the AMBA repo for the AHB Doc
+* Looked at some of the registers/databus information, got confused, and read some more
+* Understood that the Memory communicates with the AHB subordinate
+
+## Week of April 26th
+
+### Project Work
+
+* View End of Semester Presentations
+* Work on my on presentation
+
+#### Comments
+
+* Michael's presenation was very informative, taught me more about the VIP and the Core team
+
+## Week of May 3rd
+
+### Project Work
+
+* End of Semester Presentation
+* Brief discussion with Vito about memory, and how it communicates with the AHB using `Generic`
+
+#### Comments
+
+* This semester has been significantly more eventful than the last, I learned more this semester
+    * Actually asking for help is good
+    * I learned Verilog, Digital Logic really did not teach me much
+    * While taking a Class in C this semester, it has helped me understand more of C++
+    * Writing simple verification tests in C++
+* Great time at the meetings with help on the labs and just great people to talk to all around
+* Looking forward to next semester when I embark on my memory journey