docs(dn):hongtai_du_11_18_2025 (#436)

Author: HongtaiDu

src/design_notebooks/2025fall/hd2609.md

@@ -72,5 +72,21 @@ Summary: I have one midterm and a presentation to prepare this week, so not a lo
 
 Summary: This week I met with team on Wednesday, which is the weekly meeting in this semester. The team will work on Lab 1 and Lab 2 next week. I will prepare to assist on them. Also, due to the bug I met, I plan to debug it next week. 
 
+## Week of November 2nd
 
+### Project Work
+
+* Did more Verilog practice questions on the HDLBits. I finished until "If statement" problem.
+* Figured out bugs I met on VScode. It is the problem with the command I typed in terminal. I need to add -g2012 to allow iVerilog know that it compiles with 2012 version of verilog. The new types, such as "logic" or "byte" cannot be recognized by the version of 2005. If I do not add -g2012 in the command, it compiles with version of 2005, which gives me a lot of errors in both testbench and design files.
+* I tested more codes until module TopLevel(). Mainly understand it because there is no exercise for it.
+
+Summary: This week I spent most of the time on debugging the VScode. I plan to understand the rest of the code in lab 5 next week.
+
+## Week of November 2nd
+
+### Project Work
+
+* Did more Verilog practice questions on the HDLBits. I finished until "Case statement" problem.
+* I tested more codes until title "Parameterized Modules & Interfaces". I feel I am still confused by interface and modport. I understand the concepts in Verilog. interfaces group related signals together and modports define directional views of those signals. I am still confused by how they worked together in Verilog. I think need some simple examples on illustrating them.
 
+Summary: This week I spent most of the time testing the code and understanding concepts in lab 5. I will finish lab 5 next week. Also, I plan to finish lab 7 next week since I see lab 7 is mainly readings, not coding.