docs(dn): James Jin S25 bulk upload part 2 (#366)

Author: jamesjin0516

src/design_notebooks/2025spring/gj2148.md

@@ -29,3 +29,21 @@ Using the [VIP's directions](https://github.com/NYU-Processor-Design/nyu-process
 - [RiSC Implementation](https://github.com/jamesjin0516/NYU_ProcDsgn_RiSC/tree/b03e01fdb5a69faa28d2fa8dd748780a94bcb3f7): arithmetic logic unit finished
 ### working comments
 This week I built the arithmetic logic unit (ALU) of RiSC. I had to refer to [documentation](https://user.eng.umd.edu/~blj/risc/RiSC-seq.pdf) of how different instructions should be executed, and once I knew the purpose of different flags and the roles of the ALU, the arithmetic was quick to implement.
+
+## Apr. 14th - Apr. 20th, 2025
+### Work done
+- [RiSC Implementation](https://github.com/jamesjin0516/NYU_ProcDsgn_RiSC/tree/8bfb92c61cc9ea110bbe27fb458fe3165bc1f410): control unit finished
+### working comments
+I implemented the control unit of RiSC based on the incomplete specifications in [the miniproject documentation](https://github.com/NYU-Processor-Design/nyu-processor-design.github.io/blob/185b4795936a7079428277a00e1476eda72ff4c2/src/getting_started/mini-proc/week4.md). Here, I defined constants for the various opcodes for the first time and will have to also use them in the top level module, which is the work to come.
+
+## Apr. 21st - Apr. 27th, 2025
+### Work done
+- RiSC Implementation: top level module started
+### working comments
+I started outlining the top level module connecting all components of the RiSC processor using the style defined in [the miniproject documentation](https://github.com/NYU-Processor-Design/nyu-processor-design.github.io/blob/185b4795936a7079428277a00e1476eda72ff4c2/src/getting_started/mini-proc/week5.md). I think my design approach will at least use logic for the program counter and some inputs to modules that depend on previous outputs.
+
+## Apr. 28th - May. 4th, 2025
+### Work done
+- [RiSC Implementation](https://github.com/jamesjin0516/NYU_ProcDsgn_RiSC/tree/fae7ab87d04745c5fa7c341b773fc0441434f442): top level module full scaffolding
+### working comments
+I defined all components of the RiSC processor in the top level module and all the input and output connections. The design uses logic to make the opcode, ALU inputs, and register file inputs assignable, as those components need to change based on the instruction.