docs(dn): Oct. 14th - Nov. 3rd (#320)

* docs(dn): James Jin Oct. 14-20th

* docs(dn): James Jin Oct. 21-27th

* docs(dn): James Jin Oct. 28 - Nov. 3rd

Author: jamesjin0516

src/design_notebooks/2024fall/gj2148.md

@@ -1,6 +1,21 @@
 # Design notebook for James Jin (2024 Fall)
 ## Oct. 7th - Oct. 13th, 2024
 ### Work done
-- [Lab 5](https://nyu-processor-design.github.io/getting_started/onboarding/06_advanced_sv.html): "completed" lab 5
+- [Lab 5](https://nyu-processor-design.github.io/getting_started/onboarding/06_advanced_sv.html): read through lab 5
 ### Working comments
-In the past weeks I was fully committed to finishing a journal paper. Now that the urgent work is done, I have read the advanced system verilog tutorial to understand some of the team's rules with verilog usage.
+In the past weeks I was fully committed to finishing a journal paper. Now that the urgent work is done, I have read the advanced system Verilog tutorial to understand some of the team's rules with Verilog usage.
+
+## Oct. 14th - Oct. 20th, 2024
+- [Lab 5](https://github.com/jamesjin0516/onboarding-lab-5/tree/d13a73fd336a90aece51b197180141036d408ebb): further excercises
+### Working comments
+I believe that I still need to brush up on my Verilog knowledge due to not taking further computer systems / hardware courses, so I decided to implement some of the examples shown in Lab 5. Reading the descriptions of concepts such as `logic` and `wire` gives me sufficient conceptual understanding, but I would be more comfortable with their usage through further exercises.
+
+## Oct. 21st - Oct. 27th, 2024
+- [Lab 5](https://github.com/jamesjin0516/onboarding-lab-5/tree/a15ab357a96252da332b8065435b2d75c758b175): practicing Verilog interface modules
+### Working comments
+Lab 5 further introduces a new type of module, namely interfaces. I created an example interface to become more familiar with it, utilizing logic gates as the modports in the interface.
+
+## Oct. 28th - Nov. 3rd, 2024
+- [Lab 5](https://github.com/jamesjin0516/onboarding-lab-5/tree/856e5b084e8593544b584c41ce2d37acd622127e): finished lab 5 by linking interface and submodules with top level module
+### Working comments
+Finally to consolidate my understanding of more advanced Verilog concepts, I connected two logic gates using the interface previously defined.