Updating Design Notebook (#311)

* Contains updates on entries from Mid-Sept to Early-Nov

Will incorporate some back-log work after getting a better understanding
of how to test verilog through C++ and also will try out some mem-team
work after I get briefed on the information

Author: dareminion

src/design_notebooks/2024fall/dk4461.md

@@ -12,7 +12,7 @@
 * Don't press random buttons on gitlens expecting things to work
 * I know cmd git, gitlens should be easy, I just need to think about it
 
-# Week of September 13th
+## Week of September 13th
 
 ### Project Work
 
@@ -21,3 +21,137 @@
 #### Comments
 
 * I need to learn better C++ one way or another during this semester
+
+## Week of September 20th
+
+### Project Work
+
+* Attempted to continue work on Lab 3, got stuck and asked Uma for help during the meeting, still stuck.
+* I understand the concept of what the module does, I just can't seem to figure out how to right a proper test in c++ for it
+
+## Week of September 27th
+
+### Project Work
+
+* I was quite sick this week, unfortunately no work done.
+
+#### Comments
+
+* Why is my immune system so weak
+
+## Week of October 4th
+
+### Project Work
+
+* Discussed with Uma regarding next steps I should take in the VIP since I am stuck on the onboarding labs.
+* Awaiting Vito's response since Rishyak is busy regarding the memory subteam.
+* Looked at last semesters design notebook to see where I was at with researching about memory and OpenRAM
+
+#### Comments
+
+* Glad to be able to work directly on one of the subteams without having to finish these labs, since I think I would learn better by attempting work on the subteam.
+* Will look at the the nyu-mem repo for poential starting points or just a general where-abouts regarding this defunct subteam
+
+## Week of October 11th
+
+### Project Work
+
+* Looked into one of the issues on [nyu-mem](https://github.com/NYU-Processor-Design/nyu-mem) about generating the ROM script using OpenRAM
+* The last commit regarding the ROM and RAM generation stated issues with the ROM Generation
+* Successful RAM generation
+* After reading at the docs available on OpenRAM, I have a slightly better understanding of what a potential config file could look like, but I still am not sure
+* Slight confusion on Rishyak's comments on not tracking files generated by OpenRAM since on [OpenRAM ROM Generation](https://github.com/VLSIDA/OpenRAM/blob/stable/docs/source/basic_rom_usage.md) it states that after a succesful generation there should be additional files such as
+  * GDS(.gds)
+  * SPICE(.sp)
+  * Log(.log)
+  * Configuration (.py) for replication
+
+#### Comments
+
+* The LVS (Layout vs. Schematic)/DRC (Design Rule Check) check in the Config file is to ensure that the RAM and ROM can be physically generated for ICs
+* OpenRAM environment setup questions I need ask either Vito or Rishyak
+
+## Week of October 18th
+
+### Project Work
+
+* Looked into another issue on [nyu-mem](https://github.com/NYU-Processor-Design/nyu-mem), this time on experimenting with the `tech_name` parameter in the `RAM_Config.py` file.
+  * According to OpenRAM, they provide access to 2 different tech models for RAM generation
+    * SCMOS `SCN4M_SUBM` is the current one in use in the config file
+    * FreePDK45 which is a foundry model unlike a generic based one such as the SCMOS
+  * We may want to test out the FreePDK45 model as that might result in a better final product
+  * Current workspace in out repository is based off of Sky130 which is another PDK
+  * First get a working `ROM_Config.py` then potentially moving on to testing with different technology for this as well
+    * Testing out ROM generation using gf180mcu, this is currently not supported for RAM generation according to OpenRAM
+* Hex to Verilog translator is under the HexParser directory
+  * Latest note by Sean is how this will be useful once ROM is generated properly
+  * Will be able to test after being able to get ROM generated successfully
+  * This can be done using a Python Script, which I will need to learn about
+
+#### Comments
+
+* `PDK` stands for Process Design Kit and can be used to create Photonic ICs (PICs)
+* Potentially look into how to make docs for this repo, as the lack of it makes it hard to understand the current status of this repo
+* Still trying to figure out the status quo of this semi-abandoned repo since past members have graduated
+
+## Week of October 25th
+
+### Project Work
+
+* Nothing done this week, 3 midterms to take care of.
+
+#### Comments
+
+* Are EE's just math majors in disguise?
+
+## Week of November 1st
+
+### Project Work
+
+* Looked into Python Scripting
+  * Its just a .py file, or a plain-text file that contains python code to be run directly
+  * Has no association with outside classes as it is self sufficient, *I might wrong regarding this statement, will come back to fix if is the case*
+* Relooked at the open issue on [nyu-mem](https://github.com/NYU-Processor-Design/nyu-mem) regarding the Hex to Verilog python file
+  * Am confused since this is labeled as module on Github, however can be as a script. so is the current file a module a script, or something in between
+* Also read up on the Onboarding Lab 4 regarding the Catch2 framework.
+  * Unfortunately, due to my incompetence, I can not seem to figure out a feasible way to complete lab 3 just yet
+  * The Catch2 Framework makes sense, adding the verilog files that are to be tested, and then linking up the C++ test file and then running the tests that have been changed to work under the framework
+
+#### Comments
+
+* Catching up on Design Notebook entries is actually quite rewarding.
+* Will continue to think about Lab 3, and look read up on Lab 5 soon
+
+## Week of November 8th
+
+### Project Work
+
+* Talked to Uma regarding conferences and how that could help get the VIP get funding
+* Looked into possible conferences we could attend as a VIP related to Semiconductors
+  * Keeping time and location in mind as of right now there are three front running possibilities
+  * [ASMC Albany 2025](https://www.semi.org/en/connect/events/advanced-semiconductor-manufacturing-conference-asmc#overview)
+    * May 5th - May 8th 2025
+    * Technical Conference for improving the manufacturing of semiconductors
+  * [SemiExpo Heartland, Indiana 2025](https://semiexpo.semi.org/)
+    * April 1st - April 2nd 2025
+    * Focuses on Smart Mobility
+      * EVs and Power semiconductors driving sustainability
+      * Autonomus Vehicles powered by AI
+      * Chiplets reshaping Computer Architecture
+  * [MRS Boston 2024](https://www.mrs.org/meetings-events/annual-meetings/2024-mrs-fall-meeting)
+    * December 1st - December 6th 2024
+    * Much tighter time and possible conflict with being close to Finals
+    * Focuses more on Material Engineering such as
+      * Electronics, Optics and Photonics
+      * Nanomaterials
+      * Processing, Manufacturing, and Synthesis
+      * Quantum Materials
+
+### Finance Updates
+
+* There are still none from the start of the Semester
+* Conference thing is a start of getting somwhere, awaiting news on if VIPs are Yearly funded or Semesterly Funded
+
+#### Comments
+
+* I think even if a conference soon is not possible, working towards the process of being able to be funded for one would be very interesting and potentially increase membership if this is something we can get done relatively consistently. All this for more funding for the VIP so that we have the ability to do more