doc(dn):Ben Feng dn 2024-11-9 (#316)

Author: BenFeng666

src/design_notebooks/2024fall/zf2179.md

@@ -48,11 +48,18 @@ Project work:
 
 Still studing for midterm, going to resume to work on lab next week. 
 
-## week 9 of 22 October 2024
+## week 9 of 31 October 2024
 
 Project work: 
   * [onboarding lab 3](https://github.com/BenFeng666/onboarding-lab-3): exercise 1 and 2 done
 
 Restarted the lab with Vivado as WSL and virtualbox is not working for writing in system verilog and have to switch to Vivado and write in Verilog. 
 
-Spent quite a lot of time in figuring out how to diaplay the text in Vivado and how to write the testbench correctly and test all the possible values. Hopefully next week will finished exercise 3 and 4. 
+Spent quite a lot of time in figuring out how to diaplay the text in Vivado and how to write the testbench correctly and test all the possible values. Hopefully next week will finished exercise 3 and 4. 
+
+## week 10 of 9 November 2024
+
+Project work: 
+  * [onboarding lab 3](https://github.com/BenFeng666/onboarding-lab-3): done
+
+Finish lab 3 this weekend. All test run successfully in Vivado and the expected results matches the results in design file. exercise 3 is quite difficult as I don't know how to call the function in the testbench file, so I re-written the design file in verilog so that it still follows the requirements and were able to tested it in the testbench. I still feel not very confidence with Verilog coding as every exercise in the lab 3 I need to learn something new from the internet (sometimes from gpt) to help me fix the issues in the code.