docs(dn): Darren Entries for 11/15 and 11/22 (#318)

* Definitely missing some actual project work, but
its slow and steady progress

Author: dareminion

src/design_notebooks/2024fall/dk4461.md

@@ -50,7 +50,7 @@
 #### Comments
 
 * Glad to be able to work directly on one of the subteams without having to finish these labs, since I think I would learn better by attempting work on the subteam.
-* Will look at the the nyu-mem repo for poential starting points or just a general where-abouts regarding this defunct subteam
+* Will look at the the nyu-mem repo for potential starting points or just a general where-abouts regarding this defunct subteam
 
 ## Week of October 11th
 
@@ -60,7 +60,7 @@
 * The last commit regarding the ROM and RAM generation stated issues with the ROM Generation
 * Successful RAM generation
 * After reading at the docs available on OpenRAM, I have a slightly better understanding of what a potential config file could look like, but I still am not sure
-* Slight confusion on Rishyak's comments on not tracking files generated by OpenRAM since on [OpenRAM ROM Generation](https://github.com/VLSIDA/OpenRAM/blob/stable/docs/source/basic_rom_usage.md) it states that after a succesful generation there should be additional files such as
+* Slight confusion on Rishyak's comments on not tracking files generated by OpenRAM since on [OpenRAM ROM Generation](https://github.com/VLSIDA/OpenRAM/blob/stable/docs/source/basic_rom_usage.md) it states that after a successful generation there should be additional files such as
   * GDS(.gds)
   * SPICE(.sp)
   * Log(.log)
@@ -115,7 +115,7 @@
   * Am confused since this is labeled as module on Github, however can be as a script. so is the current file a module a script, or something in between
 * Also read up on the Onboarding Lab 4 regarding the Catch2 framework.
   * Unfortunately, due to my incompetence, I can not seem to figure out a feasible way to complete lab 3 just yet
-  * The Catch2 Framework makes sense, adding the verilog files that are to be tested, and then linking up the C++ test file and then running the tests that have been changed to work under the framework
+  * The Catch2 Framework makes sense, adding the Verilog files that are to be tested, and then linking up the C++ test file and then running the tests that have been changed to work under the framework
 
 #### Comments
 
@@ -150,8 +150,35 @@
 ### Finance Updates
 
 * There are still none from the start of the Semester
-* Conference thing is a start of getting somwhere, awaiting news on if VIPs are Yearly funded or Semesterly Funded
+* Conference thing is a start of getting somewhere, awaiting news on if VIPs are Yearly funded or Semesterly Funded
 
 #### Comments
 
 * I think even if a conference soon is not possible, working towards the process of being able to be funded for one would be very interesting and potentially increase membership if this is something we can get done relatively consistently. All this for more funding for the VIP so that we have the ability to do more
+
+## Week of November 15th
+
+### Project Work
+
+* Read through Lab 5 regarding SystemVerilog. Seems quite interesting and I am unsure as to how much is needed for the mem-team since some system Verilog files get generated through OpenRAM already. 
+* I may 'borrow' someones code to try working on Lab 4 as it seems learning how to write parts of the toolchain code which will be required for testing different areas of the NYU-Mem Subteam.
+
+#### Comments
+
+* Got slightly busy, was unable to ask for help with setting up dev environment for working with OpenRAM.
+* Will try to setup something by next week and start some potential work.
+
+## Week of November 22nd
+
+### Project Work
+
+* Definitely going to make my end of semester presentation on the Memory Subteam, or what exists of it.
+* Got a fork setup for the [NYU-Mem Fork](https://github.com/dareminion/nyu-mem)  
+* Will work on setting up environment, I already have Conda from a previous course at NYU, need to see what packages I need to install to start development.
+* Need to understand what the development process is here at this VIP
+
+#### Comments
+
+* Joe told me a weird tongue twister - "Irish Wristwatch Swiss Wristwatch", I found this quite intriguing while writing dn entries.
+* At this point I'm trying to *"document"* the mem-repo with my limited knowledge and then begin dev work.
+