From df6c5fe19d9eba78ec2b874b9a20dd1c78bf415c Mon Sep 17 00:00:00 2001 From: Geoffrey Guindine <geoffreyguindine@geoffreys-air.mynetworksettings.com> Date: Tue, 13 Feb 2024 11:33:00 -0500 Subject: [PATCH 1/8] Docs (dn): Geoffrey entry 2/13 --- src/design_notebooks/2024spring/gg2692.md | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/design_notebooks/2024spring/gg2692.md b/src/design_notebooks/2024spring/gg2692.md index e69de29b..513287d1 100644 --- a/src/design_notebooks/2024spring/gg2692.md +++ b/src/design_notebooks/2024spring/gg2692.md @@ -0,0 +1,17 @@ +## 2/12-2/19 Week 1 + +### Work done: + +- Created design notebook and worked on Lab 1. +- Began working on Lab 2 + +### Question Responses: + +- 1. The paths are relative to the "src" folder. +- 2. Cmake and Ninja are both build systems, but Cmake offers a higher level of abstraction than Ninja does, as Ninja is used for mostly speed and efficiency when building programs. +- 3. It is important to run cmake it its own directory because the source tree will be kept clean, and any auto generated files will not be polluted with the cmake files. + +### Questions to be answered: + +- Does the last part of the lab have any output? +- Still a bit confused on the whole Cmake and Ninja toolchain ideas. From e435a52f089de6f2c77b61ad333cabc2764847df Mon Sep 17 00:00:00 2001 From: Geoffrey Guindine <geoffreyguindine@geoffreys-air.mynetworksettings.com> Date: Mon, 19 Feb 2024 00:24:09 -0500 Subject: [PATCH 2/8] dn: Finished design notebook entry rework --- src/design_notebooks/2024spring/gg2692.md | 20 ++++++-------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/src/design_notebooks/2024spring/gg2692.md b/src/design_notebooks/2024spring/gg2692.md index 513287d1..b8615995 100644 --- a/src/design_notebooks/2024spring/gg2692.md +++ b/src/design_notebooks/2024spring/gg2692.md @@ -1,17 +1,9 @@ -## 2/12-2/19 Week 1 +## Week of 2 February 2023 -### Work done: +Project Work: -- Created design notebook and worked on Lab 1. -- Began working on Lab 2 +- [Onboarding Lab 1](https://github.com/geoffguin124/NYUProcDesignLabs): Completed Lab 1 -### Question Responses: - -- 1. The paths are relative to the "src" folder. -- 2. Cmake and Ninja are both build systems, but Cmake offers a higher level of abstraction than Ninja does, as Ninja is used for mostly speed and efficiency when building programs. -- 3. It is important to run cmake it its own directory because the source tree will be kept clean, and any auto generated files will not be polluted with the cmake files. - -### Questions to be answered: - -- Does the last part of the lab have any output? -- Still a bit confused on the whole Cmake and Ninja toolchain ideas. +I spent this week working on Lab 1, and I didn't really have any issues with the lab, except for +forgetting to save my VScode files. I will be continuing to work on the rest of the onboarding labs, +aiming for getting 1-2 done per week. From 38c15a1b0d2d0b7eb687eea6beb84a2e231978bf Mon Sep 17 00:00:00 2001 From: Geoffrey Guindine <geoffreyguindine@geoffreys-air.mynetworksettings.com> Date: Mon, 19 Feb 2024 18:10:49 -0500 Subject: [PATCH 3/8] docs(dn): Finished Lab 2 entry --- src/design_notebooks/2024spring/gg2692.md | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/design_notebooks/2024spring/gg2692.md b/src/design_notebooks/2024spring/gg2692.md index b8615995..41acdc3d 100644 --- a/src/design_notebooks/2024spring/gg2692.md +++ b/src/design_notebooks/2024spring/gg2692.md @@ -7,3 +7,11 @@ Project Work: I spent this week working on Lab 1, and I didn't really have any issues with the lab, except for forgetting to save my VScode files. I will be continuing to work on the rest of the onboarding labs, aiming for getting 1-2 done per week. + +## Week of 18 February 2023 + +Project Work: + +- [Onboarding Lab 2](https://github.com/geoffguin124/NYUProcDesignLabs): Completed Lab 2 + +I spent this week finishing up Lab 2 and trying to familiarize myself with System Verilog. I have worked with VHDL before, so I kind of understand how SV works better than I would if I didn't use VHDL before. I also installed a System Verilog formatter, which makes coding in it a lot easier. From e93dd0ad744852bee070e1901caab3c55cb51284 Mon Sep 17 00:00:00 2001 From: Geoffrey Guindine <geoffreyguindine@geoffreys-air.mynetworksettings.com> Date: Fri, 1 Mar 2024 00:25:16 -0500 Subject: [PATCH 4/8] dn: Design notebook entry for 2/25 --- src/design_notebooks/2024spring/gg2692.md | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/design_notebooks/2024spring/gg2692.md b/src/design_notebooks/2024spring/gg2692.md index 41acdc3d..a14e0a91 100644 --- a/src/design_notebooks/2024spring/gg2692.md +++ b/src/design_notebooks/2024spring/gg2692.md @@ -15,3 +15,11 @@ Project Work: - [Onboarding Lab 2](https://github.com/geoffguin124/NYUProcDesignLabs): Completed Lab 2 I spent this week finishing up Lab 2 and trying to familiarize myself with System Verilog. I have worked with VHDL before, so I kind of understand how SV works better than I would if I didn't use VHDL before. I also installed a System Verilog formatter, which makes coding in it a lot easier. + +## Week of 25 February 2023 + +Project Work: + +- [Onboarding Lab 3](https://github.com/geoffguin124/NYUProcDesignLabs): Completed Lab 3 + +This past 10 days I was working Labs 3 and 4. I just finished up Lab 3, linked in the link above. This lab was a bit confusing at first, but eventually I started to understand. I think this is a great way to understand the Cmake toolchain, especially since I didn't understand it too well intially. I want to practice understanding CMakeLists file more, I will do some more reading to understand that. From 80328d8b1c2566e12ae2f34b97b3864d81670f7f Mon Sep 17 00:00:00 2001 From: Geoffrey Guindine <geoffreyguindine@10-18-216-189.dynapool.wireless.nyu.edu> Date: Sun, 10 Mar 2024 22:22:13 -0400 Subject: [PATCH 5/8] dn: Finished onboarding labs --- src/design_notebooks/2024spring/gg2692.md | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/design_notebooks/2024spring/gg2692.md b/src/design_notebooks/2024spring/gg2692.md index a14e0a91..5eb3d1a6 100644 --- a/src/design_notebooks/2024spring/gg2692.md +++ b/src/design_notebooks/2024spring/gg2692.md @@ -23,3 +23,11 @@ Project Work: - [Onboarding Lab 3](https://github.com/geoffguin124/NYUProcDesignLabs): Completed Lab 3 This past 10 days I was working Labs 3 and 4. I just finished up Lab 3, linked in the link above. This lab was a bit confusing at first, but eventually I started to understand. I think this is a great way to understand the Cmake toolchain, especially since I didn't understand it too well intially. I want to practice understanding CMakeLists file more, I will do some more reading to understand that. + +## Week of March 3 2023 + +Project Work: + +- [Onboarding Lab 3](https://github.com/geoffguin124/NYUProcDesignLabs): Completed onboarding labs + +This past week I have been working on finishing all of the onboarding labs, which can be linked to the above repo containing all of my onboarding labs. The onboarding labs have been relatively straightforward, the most confusing part definitely being the toolchain configuration and how all of these tools work together. The code has been decently challenging to write, considering the lack of a proper IDE for Verilog, so having to memorize the syntax/types has been necessary for doing the labs. I also had a poor understanding of what each tool actually did, so that messed with my projects a bit. I was intially writing tests in SV, while we were supposed to be doing it in C++. I thought that vertilator made the tests for you, while it just produces a verilated module for the user to use. From 120963adcee38f8648dae9db4544273076f5ad5e Mon Sep 17 00:00:00 2001 From: Geoffrey Guindine <geoffreyguindine@10-16-217-50.dynapool.wireless.nyu.edu> Date: Sun, 31 Mar 2024 12:46:40 -0400 Subject: [PATCH 6/8] dn: Addded work for after break --- src/design_notebooks/2024spring/gg2692.md | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/design_notebooks/2024spring/gg2692.md b/src/design_notebooks/2024spring/gg2692.md index 5eb3d1a6..10b594b6 100644 --- a/src/design_notebooks/2024spring/gg2692.md +++ b/src/design_notebooks/2024spring/gg2692.md @@ -31,3 +31,11 @@ Project Work: - [Onboarding Lab 3](https://github.com/geoffguin124/NYUProcDesignLabs): Completed onboarding labs This past week I have been working on finishing all of the onboarding labs, which can be linked to the above repo containing all of my onboarding labs. The onboarding labs have been relatively straightforward, the most confusing part definitely being the toolchain configuration and how all of these tools work together. The code has been decently challenging to write, considering the lack of a proper IDE for Verilog, so having to memorize the syntax/types has been necessary for doing the labs. I also had a poor understanding of what each tool actually did, so that messed with my projects a bit. I was intially writing tests in SV, while we were supposed to be doing it in C++. I thought that vertilator made the tests for you, while it just produces a verilated module for the user to use. + +## Week of March 23 2023 + +Project Work: + +- [Documentation] + +Since a bit before and after spring break, I have been working on reading the documentation for the AMBA team. I am trying to figure out how to implement the memory suboordiate component, but this is proving to be a daunting task, as there is not a lot of material available through the internet. I am going to spend some more time with Rishyak trying to figure out this issue, and I am hoping that I will actually be able to write some code in the very near future. Also still reading up on docs on how SV and C++ work together through the Cmake toolchain with stuff like verilator. From 3205de91a9fdc2d19ae7189bb9b3f4d1adbe67ae Mon Sep 17 00:00:00 2001 From: Geoffrey Guindine <geoffreyguindine@10-18-204-180.dynapool.wireless.nyu.edu> Date: Mon, 8 Apr 2024 10:39:48 -0400 Subject: [PATCH 7/8] dn: 3/30 design notebool entry --- src/design_notebooks/2024spring/gg2692.md | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/design_notebooks/2024spring/gg2692.md b/src/design_notebooks/2024spring/gg2692.md index 10b594b6..7e7f30b1 100644 --- a/src/design_notebooks/2024spring/gg2692.md +++ b/src/design_notebooks/2024spring/gg2692.md @@ -39,3 +39,11 @@ Project Work: - [Documentation] Since a bit before and after spring break, I have been working on reading the documentation for the AMBA team. I am trying to figure out how to implement the memory suboordiate component, but this is proving to be a daunting task, as there is not a lot of material available through the internet. I am going to spend some more time with Rishyak trying to figure out this issue, and I am hoping that I will actually be able to write some code in the very near future. Also still reading up on docs on how SV and C++ work together through the Cmake toolchain with stuff like verilator. + +## Week of March 30 2023 + +Project Work: + +- [AMBA Memory Suboordinate Design](https://github.com/NYU-Processor-Design/nyu-amba/pull/24): Started memory sub work + +This past week I have been working on implementing a general memory suboordinate for the AMBA team. I am currently working on implementing the behavioral model, however I am having some trouble on that. Will ask Rishyak this week for some help, but I think that I got all of the control,signals down. However, that is just kind of copy and pasting from the docs, so the behavioral component will be much harder to accurately implement. From 448f86b5df2a9c7c351c214677d139734d610065 Mon Sep 17 00:00:00 2001 From: Geoffrey Guindine <geoffreyguindine@10-18-175-138.dynapool.wireless.nyu.edu> Date: Sun, 21 Apr 2024 17:40:55 -0400 Subject: [PATCH 8/8] dn: Added entries from the last 2 weeks --- src/design_notebooks/2024spring/gg2692.md | 28 ++++++++++++++++++----- 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/src/design_notebooks/2024spring/gg2692.md b/src/design_notebooks/2024spring/gg2692.md index 7e7f30b1..a7e1858a 100644 --- a/src/design_notebooks/2024spring/gg2692.md +++ b/src/design_notebooks/2024spring/gg2692.md @@ -1,4 +1,4 @@ -## Week of 2 February 2023 +## Week of 2 February 2024 Project Work: @@ -8,7 +8,7 @@ I spent this week working on Lab 1, and I didn't really have any issues with the forgetting to save my VScode files. I will be continuing to work on the rest of the onboarding labs, aiming for getting 1-2 done per week. -## Week of 18 February 2023 +## Week of 18 February 2024 Project Work: @@ -16,7 +16,7 @@ Project Work: I spent this week finishing up Lab 2 and trying to familiarize myself with System Verilog. I have worked with VHDL before, so I kind of understand how SV works better than I would if I didn't use VHDL before. I also installed a System Verilog formatter, which makes coding in it a lot easier. -## Week of 25 February 2023 +## Week of 25 February 2024 Project Work: @@ -24,7 +24,7 @@ Project Work: This past 10 days I was working Labs 3 and 4. I just finished up Lab 3, linked in the link above. This lab was a bit confusing at first, but eventually I started to understand. I think this is a great way to understand the Cmake toolchain, especially since I didn't understand it too well intially. I want to practice understanding CMakeLists file more, I will do some more reading to understand that. -## Week of March 3 2023 +## Week of March 3 2024 Project Work: @@ -32,7 +32,7 @@ Project Work: This past week I have been working on finishing all of the onboarding labs, which can be linked to the above repo containing all of my onboarding labs. The onboarding labs have been relatively straightforward, the most confusing part definitely being the toolchain configuration and how all of these tools work together. The code has been decently challenging to write, considering the lack of a proper IDE for Verilog, so having to memorize the syntax/types has been necessary for doing the labs. I also had a poor understanding of what each tool actually did, so that messed with my projects a bit. I was intially writing tests in SV, while we were supposed to be doing it in C++. I thought that vertilator made the tests for you, while it just produces a verilated module for the user to use. -## Week of March 23 2023 +## Week of March 23 2024 Project Work: @@ -40,10 +40,26 @@ Project Work: Since a bit before and after spring break, I have been working on reading the documentation for the AMBA team. I am trying to figure out how to implement the memory suboordiate component, but this is proving to be a daunting task, as there is not a lot of material available through the internet. I am going to spend some more time with Rishyak trying to figure out this issue, and I am hoping that I will actually be able to write some code in the very near future. Also still reading up on docs on how SV and C++ work together through the Cmake toolchain with stuff like verilator. -## Week of March 30 2023 +## Week of March 30 2024 Project Work: - [AMBA Memory Suboordinate Design](https://github.com/NYU-Processor-Design/nyu-amba/pull/24): Started memory sub work This past week I have been working on implementing a general memory suboordinate for the AMBA team. I am currently working on implementing the behavioral model, however I am having some trouble on that. Will ask Rishyak this week for some help, but I think that I got all of the control,signals down. However, that is just kind of copy and pasting from the docs, so the behavioral component will be much harder to accurately implement. + +## Week of April 10 2024 + +Project Work: + +- [AMBA Memory Suboordinate Design](https://github.com/NYU-Processor-Design/nyu-amba/pull/24): Initial design of memory sub done + +I was able to complete the memory sub work intially, however there are some issues with how I was interfacing with our current libraries, so I need to fix that. I am waiting for Rishyak to make a comment on my PR, and then I will continue with the work I am currently doing. + +## Week of April 17 2024 + +Project Work: + +- [AMBA Memory Suboordinate Design](https://github.com/NYU-Processor-Design/nyu-amba/pull/24): Started memory sub work + +I integrated the AHBCommon_if and MemCommon_if interfaces into the SubMemCtrl module, replacing direct signal definitions with these interfaces. Also I added the ahb_resp_t enum for response status signaling within the module. I think that these changes will smooth out the process of creating the rest of the design.