Support for AARCH64 SVE2 instructions

[CUB3D]

Is your feature request related to a problem? Please describe.
Scalable Vector Extensions 2 is an AArch64 feature that introduces various new SIMD instructions. For official details see SVE2. These instructions are available in various chips like the Neoverse N2. Ghidra cannot currently disassemble these instructions. Here's an example:

void sve2_test() {
    asm volatile(
        "cmla   z2.b, z0.b, z1.b, #90\n"
        "sqrdcmlah z2.h, z0.h, z1.h, #90\n"
        "histseg z2.b, z0.b, z1.b\n"
        "match  p2.b, p0/z, z0.b, z1.b\n"
        "nmatch p2.b, p0/z, z0.b, z1.b\n"
        "eor3   z2.d, z2.d, z0.d, z1.d\n"
        "bsl    z2.d, z2.d, z0.d, z1.d\n"
        "bsl1n  z2.d, z2.d, z0.d, z1.d\n"
        "bsl2n  z2.d, z2.d, z0.d, z1.d\n"
        "nbsl   z2.d, z2.d, z0.d, z1.d\n"
        "xar    z2.d, z2.d, z0.d, #3\n"
        "pmul   z2.b, z0.b, z1.b\n"
        "pmullb z2.h, z0.b, z1.b\n"
        "pmullt z2.h, z0.b, z1.b\n"
        "addhnb z2.b, z0.h, z1.h\n"
        "addhnt z2.b, z0.h, z1.h\n"
        "raddhnb z2.b, z0.h, z1.h\n"
        "subhnb z2.b, z0.h, z1.h\n"
        "subhnt z2.b, z0.h, z1.h\n"
        "sqxtnb z2.b, z0.h\n"
        "sqxtnt z2.b, z0.h\n"
        "smlalb z2.s, z0.h, z1.h\n"
        "smlalt z2.s, z0.h, z1.h\n"
        "umlalb z2.s, z0.h, z1.h\n"
        "umlalt z2.s, z0.h, z1.h\n"
        "tbl    z2.b, {z0.b, z1.b}, z3.b\n"
    );
}

clang-22 --target=aarch64 -march=armv8-a+sve2 -O3 -c test.c

Pre-compiled example:
sve2.zip

Describe the solution you'd like
Support for SVE2 instructions.

Describe alternatives you've considered
Alternative disassemblers and decompilers do support these instructions.