riscv64 zvl256b qemu test

Add interleaving to sgemm and dgemm. Disentangle trmm/symm from gemm. #2181

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Triggered via pull request January 6, 2026 14:19

almayne

synchronize #5573

almayne:sgemm_interleave

Status Success

Total duration 13m 11s

Artifacts –

riscv64_vector.yml

on: pull_request

Matrix: TEST