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Create apb_sb.sv
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apb_sb.sv

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class apb_sb extends uvm_scoreboard;
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`uvm_component_utils(apb_sb)
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`uvm_analysis_imp_decl(_W)
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`uvm_analysis_imp_decl(_R)
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virtual apb_if vif;
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apb_transaction trans_write;
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apb_transaction trans_read;
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uvm_analysis_imp_W #(apb_transaction, apb_sb) sb_export_write;
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uvm_analysis_imp_R #(apb_transaction, apb_sb) sb_export_read;
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bit WPSLVERR, RPSLVERR;
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bit [31:0] read_q[$];
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bit [31:0] write_q[$];
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bit [31:0] write,read;
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int compare_pass =0, compare_fail =0;
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// uvm_tlm_analysis_fifo #(apb_transaction) write_fifo;
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// uvm_tlm_analysis_fifo #(apb_transaction) read_fifo;
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function new (string name ="apb_sb", uvm_component parent);
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super.new(name, parent);
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endfunction
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function void build_phase(uvm_phase phase);
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super.build_phase(phase);
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sb_export_write = new("sb_export_write", this);
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sb_export_read = new("sb_export_read", this);
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if(!uvm_config_db#(virtual apb_if)::get(this,"","vif",vif)) begin
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`uvm_error("build_phase","driver virtual interface failed")
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end
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// write_fifo = new("write_fifo", this);
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// read_fifo = new("read_fifo", this);
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endfunction
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/* function void connect_phase(uvm_phase phase);
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sb_export_write.connect(write_fifo.analysis_export);
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sb_export_read.connect(read_fifo.analysis_export);
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endfunction: connect_phase */
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virtual function void write_W (input apb_transaction trans);
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write_q.push_back(trans.PWDATA);
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WPSLVERR = trans.PSLVERR;
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`uvm_info("SB",$sformatf("Got Write Transaction: write queue size =%0d PRESET =%0d, PSEL =%0d, PWRITE =%0d, PENABLE =%0d, ADDR =%0d, PWDATA =%0d PSLVERR = %0d", write_q.size(),trans.PRESET,trans.PSEL,trans.PWRITE,trans.PENABLE,trans.PADDR,trans.PWDATA,trans.PSLVERR),UVM_LOW)
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endfunction
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virtual function void write_R (input apb_transaction trans);
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read_q.push_back(trans.PRDATA);
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RPSLVERR = trans.PSLVERR;
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`uvm_info("SB",$sformatf("Got Read Transaction: read q size =%0d PRESET =%0d, PSEL =%0d, PWRITE =%0d, PENABLE =%0d, ADDR =%0d, PWDATA =%0d PSLVERR = %0d",read_q.size(), trans.PRESET,trans.PSEL,trans.PWRITE,trans.PENABLE,trans.PADDR,trans.PRDATA,trans.PSLVERR),UVM_LOW)
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endfunction
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task run_phase(uvm_phase phase);
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forever begin
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@(posedge vif.PCLK) begin
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if(WPSLVERR || RPSLVERR) begin
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if(WPSLVERR) begin
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`uvm_info("SB",$sformatf("We are in RUN PHASE: We got PSLVERR"),UVM_LOW)
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write = write_q.pop_front(); end //when error is present we don't want to comapre read and write data
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if(RPSLVERR) begin
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`uvm_info("SB",$sformatf("We are in RUN PHASE: We got PSLVERR"),UVM_LOW)
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read = read_q.pop_front(); end
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end
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else begin
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if(write_q.size() >0 && read_q.size() >0) begin
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write = write_q.pop_front();
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read = read_q.pop_front();
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`uvm_info("SB",$sformatf("We are in RUN PHASE: Wdata =%0d Rdata =%0d",write,read),UVM_LOW)
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compare();
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end
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end
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end
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end
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endtask
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virtual function void compare();
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if(write == read) begin
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`uvm_info("compare", $sformatf("Test: OK! Write Data = %0d Read Data = %0d",write,read), UVM_LOW);
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compare_pass++;
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end else begin
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`uvm_info("compare", $sformatf("Test: Fail! Write Data = %0d Read Data = %0d",write,read), UVM_LOW);
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compare_fail++;
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end
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endfunction: compare
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//Report Phase
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function void report_phase(uvm_phase phase);
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super.report_phase(phase);
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if(compare_fail>0)
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begin
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`uvm_info(get_type_name(), "---------------------------------------", UVM_NONE)
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`uvm_info(get_type_name(), $sformatf("---- TEST FAIL COUNTS %0d ----",compare_fail), UVM_NONE)
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`uvm_info(get_type_name(), "---------------------------------------", UVM_NONE)
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end
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if(compare_pass>0)
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begin
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`uvm_info(get_type_name(), "---------------------------------------", UVM_NONE)
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`uvm_info(get_type_name(), $sformatf("---- TEST PASS COUNTS %0d ----",compare_pass), UVM_NONE)
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`uvm_info(get_type_name(), "---------------------------------------", UVM_NONE)
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end
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endfunction : report_phase
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endclass

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