From 8d6c828f3123dd3ed8052282155b70c93a3f9fbd Mon Sep 17 00:00:00 2001 From: Carlos Delfino - Acer - Estudio 3 Date: Fri, 2 Jul 2021 00:33:42 -0300 Subject: [PATCH] =?UTF-8?q?desenvolvendo=20algoritmo=20para=20dump=20de=20?= =?UTF-8?q?registradores=20e=20mem=C3=B3ria?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Esta proposta de dump atende a demanda do issue #64, ainda é uma prova de conceito. --- src/DataBusControl.v | 28 +++++++++++++++++ src/RISCuin.v | 34 +++++++++++++++++--- src/RISCuin_tb.v | 75 ++++++++++++++++++++++++++++++++++++++------ src/RegisterBank.v | 38 ++++++++++++++++++++++ src/config.vh | 16 ++++++++++ 5 files changed, 177 insertions(+), 14 deletions(-) diff --git a/src/DataBusControl.v b/src/DataBusControl.v index 59b71d8..ecddd41 100644 --- a/src/DataBusControl.v +++ b/src/DataBusControl.v @@ -12,6 +12,9 @@ module DataBusControl ( input [31:0] data_in, output [31:0] data_out +`ifdef RISCUIN_DUMP + ,input dump +`endif ); @@ -121,4 +124,29 @@ always @(posedge clk) begin end end + +`ifdef RISCUIN_DUMP + integer i; + integer fileDesc; + always @(posedge clk) begin + if(dump) begin + $display("DataBusControl: Arquivo Dump: %s, %10t", `RISCUIN_DUMP_FILE_DBC, $realtime); + fileDesc = $fopen({"./dumps/",`RISCUIN_DUMP_FILE_DBC},"a"); + $fwrite(fileDesc,"Dump Data Bus Control inicializado em: %10t\n",$realtime); + $fwrite(fileDesc,"rst: %0b, wd: %0b, rd: %0b, ready: %0b, busy: %0b \n",rst, wd, rd, ready, busy); + $fwrite(fileDesc,"Addr in: %8h, Size: %4h, Data: %8h\n",addr_in,size_in,data_in); + $fwrite(fileDesc,"Addr out: %8h, Size: %4h, Data: %8h\n",addr_out,size_out,data_out); + $fwrite(fileDesc,"========================================================= \n"); + $fwrite(fileDesc," 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 \n"); + for (i=0; i<`DBC_RAM_SIZE; i=i+8) begin:dump_memory + $fwrite(fileDesc,"0x%8h - %8h %8h %8h %8h %8h %8h %8h %8h \n", i, + memory[i+0], memory[i+1], memory[i+2], memory[i+3], + memory[i+4], memory[i+5], memory[i+6], memory[i+7]); + end + $fwrite(fileDesc,"Dump finalizado em: %10t\n",$realtime); + $fwrite(fileDesc,"#########################################################\n"); + $fclose(fileDesc); + end + end +`endif endmodule diff --git a/src/RISCuin.v b/src/RISCuin.v index d05bbcf..3e83752 100644 --- a/src/RISCuin.v +++ b/src/RISCuin.v @@ -3,7 +3,19 @@ module RISCuin( input clk, rst, - output pc_end); + output internal_rst, + output pc_end +`ifdef RISCUIN_DUMP + ,input dump + ,output [`INSTR_ADDR_WIDTH-1:0] pc +`endif +); + +`ifdef RISCUIN_DUMP +initial begin + $display("RISCuin: Dump está ativo, será criado dump de memória e registradores"); +end +`endif localparam TYPE_B = 7'b1100011; localparam TYPE_IJ = 7'b1100111; @@ -39,7 +51,10 @@ wire [ 5:0] alu_op; wire imm_rs2_sel; -wire [`INSTR_ADDR_WIDTH-1:0] pc, pc_plus, pc_next; +`ifndef RISCUIN_DUMP +wire [`INSTR_ADDR_WIDTH-1:0] pc; +`endif +wire [`INSTR_ADDR_WIDTH-1:0] pc_plus, pc_next; wire [`INSTR_ADDR_WIDTH-1:0] pc_branch = alu_out[`INSTR_ADDR_WIDTH-1:2]; wire [`INSTR_ADDR_WIDTH+1:0] pc_ext = {pc,2'b00}; wire pc_enable = !rst && bus_ready && rb_ready && !pc_end && !bus_busy; @@ -134,8 +149,13 @@ InstructionDecoderRV32I id_rv32i(.instr(instr), Banco de Registradores */ RegisterBank rb(.clk(clk), .rst(rst), .ready(rb_ready), - .rs1_sel(rs1_sel), .rs2_sel(rs2_sel), .rd_sel(rd_sel), .reg_w(reg_w), - .rs1_data(rs1_data), .rs2_data(rs2_data), .rd_data(rd_data)); + .reg_w(reg_w), + .rs1_sel(rs1_sel), .rs2_sel(rs2_sel), .rd_sel(rd_sel), + .rs1_data(rs1_data), .rs2_data(rs2_data), .rd_data(rd_data) +`ifdef RISCUIN_DUMP + ,.dump(dump) +`endif +); /* ########### @@ -164,7 +184,11 @@ DataBusControl data_m_ctl( .wd(bus_w), .rd(bus_r), .size_in(bus_size), .size_out(bus_size), .addr_in(bus_w?alu_out:{32'bz}), .addr_out(bus_r?alu_out:{32'bz}), - .data_in(data_in), .data_out(data_out)); + .data_in(data_in), .data_out(data_out) +`ifdef RISCUIN_DUMP + , .dump(dump) +`endif +); /* ######## diff --git a/src/RISCuin_tb.v b/src/RISCuin_tb.v index 89b3670..649fd80 100644 --- a/src/RISCuin_tb.v +++ b/src/RISCuin_tb.v @@ -1,9 +1,16 @@ +`include "./config.vh" + `ifdef __ICARUS__ `timescale 10ns/1ns `endif - +`ifndef RISCUIN_TB +`define RISCUIN_TB 1 +`endif module RISCuin_tb; + + + wire start_rst, finish_rst, internal_rst; reg clk = 1'b0; `ifndef __YOSYS__ @@ -17,25 +24,75 @@ module RISCuin_tb; initial begin - #00000 $display("Iniciado!"); + #00000 $display("RISCuinho Testbentch: Iniciado!"); +`ifdef __ICARUS__ + $display("RISCuin_tb: Icarus ativo"); +`endif +`ifdef __IOSYS__ + $display("RISCuin_tb: IOSYS ativo"); +`endif +`ifdef RISCUIN_DUMP + $display("RISCuin_tb: Dump está ativo, será criado dump de memória e registradores"); +`endif $dumpfile("RISCuin.vcd"); $dumpvars; - #01500 $display("1500 Ticks será finalziado!"); + #02000 $display("RISCuinho Testbentch: 2000 Ticks será finalziado!"); $finish; end wire pc_end; - + reg halt = 1'b0; `ifndef __YOSYS__ - always @(posedge pc_end) - if(pc_end) $finish; + always @(posedge pc_end or posedge internal_rst or posedge finish_rst) + halt <= (pc_end || internal_rst || finish_rst ); + + integer count_halt_clock = `RISCUIN_CLOCK_WAIT_FINISH; + always @(posedge clk) + if(halt)begin + if(count_halt_clock) count_halt_clock <= count_halt_clock - 1; + else $finish; + end `endif - wire rst; - AutoReset aRst(.clk(clk), .count(30), .rst(rst)); - RISCuin cpu(.clk(clk), .rst(rst), .pc_end(pc_end)); +`ifdef RISCUIN_DUMP +// dump sinaliza que deve ser feito o dump geral + wor local_dump; + reg dump = 1'b0; +// o PC aqui é usado para contabilizar quantos endereços +// de instruções foram exectuados + wire [`INSTR_ADDR_WIDTH-1:0] pc; +// futuramente irei contabilizar por instrução e não +// pelo PC, o pc vária positivamente e negativamente, +// já a contagem de instrução valida é sempre continua. +//###### +// usarei o AutoReset para gerar o sinal de dump com base +// no clock, o AutoReset será ajustado para atender melhor +// também esta demanda + AutoReset #(.INVERT_RST(1'b1))aDump + (.clk(clk), .count(`RISCUIN_DUMP_COUNT_CLOCK), .rst(local_dump)); +// bloco que monitora a contagem do pc + assign local_dump = pc == `RISCUIN_DUMP_COUNT_PC; + assign local_dump = pc_end == `RISCUIN_DUMP_PC_END; + reg last_dump = 1'b0; + always @(posedge clk) + if(local_dump && !last_dump) begin + dump <= 1'b1; + last_dump <= 1'b1; + end + always @(posedge clk) + if(dump) dump <= 1'b0; +`endif + + AutoReset aRst(.clk(clk), .count(`RISCUIN_WATCHDOG_START), .rst(start_rst)); + AutoReset aRstFinish(.clk(clk && !start_rst), .count(`RISCUIN_WATCHDOG_RST), .rst(finish_rst)); + RISCuin cpu(.clk(clk), .rst(start_rst|| !finish_rst), .pc_end(pc_end), .internal_rst(internal_rst) +`ifdef RISCUIN_DUMP + , .pc(pc) + , .dump(dump) +`endif + ); endmodule diff --git a/src/RegisterBank.v b/src/RegisterBank.v index 3890003..88f2288 100644 --- a/src/RegisterBank.v +++ b/src/RegisterBank.v @@ -8,6 +8,9 @@ module RegisterBank #( output [REGISTER_WIDTH-1:0] rs1_data, rs2_data, input [REGISTER_WIDTH-1:0] rd_data, output reg ready +`ifdef RISCUIN_DUMP + ,input dump +`endif ); localparam SIZE = 2**BANK_WIDTH; @@ -47,5 +50,40 @@ always @(posedge clk) begin memory[rd_sel] <= rd_data; end end + +`ifdef RISCUIN_DUMP + integer i; + integer fileDesc; + always @(posedge clk) begin + if(dump) begin + $display("RegisterBank: Arquivo Dump: %s, %10t", `RISCUIN_DUMP_FILE_RB, $realtime); + fileDesc = $fopen({"./dumps/",`RISCUIN_DUMP_FILE_RB},"a"); + $fwrite(fileDesc,"Dump Register Bank inicializado em: %10t\n",$realtime); + /* + input clk, rst, + input [BANK_WIDTH-1:0] rs1_sel, rs2_sel, rd_sel, + input reg_w, + output [REGISTER_WIDTH-1:0] rs1_data, rs2_data, + input [REGISTER_WIDTH-1:0] rd_data, + output reg ready +*/ + $fwrite(fileDesc,"rst: %0b, Reg Write: %0b, ready: %0b \n",rst, reg_w, ready); + $fwrite(fileDesc,"Reg Sel 1: %2h, Data: %8h\n",rs1_sel,rs1_data); + $fwrite(fileDesc,"Reg Sel 2: %2h, Data: %8h\n",rs2_sel,rs2_data); + $fwrite(fileDesc,"Reg Sel dest: %2h, Data: %8h\n",rd_sel,rd_data); + $fwrite(fileDesc,"========================================================= \n"); + $fwrite(fileDesc," 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 \n"); + for (i=0; i