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X86: fixup (V)PMADDWD detection
Fix some bugs (missing checks). Add constant support.
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+18
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lib/Target/X86/X86ISelLowering.cpp

+18-4
Original file line numberDiff line numberDiff line change
@@ -41664,9 +41664,11 @@ static SDValue combineMulToPMADDWD(SDNode *N, SelectionDAG &DAG,
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// with zero extends, which should qualify for the optimization.
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// Otherwise just fallback to zero-extension check.
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if (isa<ConstantSDNode>(N0.getOperand(1).getOperand(0)) &&
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N0.getOperand(1).getConstantOperandVal(0) == 16 &&
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isa<ConstantSDNode>(N1.getOperand(1).getOperand(0)) &&
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N1.getOperand(1).getConstantOperandVal(0) == 16) {
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N0.getOperand(1).getConstantOperandVal(0) == 16 &&
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N1.getOperand(1).getConstantOperandVal(0) == 16 &&
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DAG.isSplatValue(N0.getOperand(1)) &&
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DAG.isSplatValue(N1.getOperand(1))) {
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// Nullify mask to pass the following check
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Mask17 = 0;
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N0 = DAG.getNode(ISD::SRL, N0.getNode(), VT, N0.getOperand(0),
@@ -41675,8 +41677,20 @@ static SDValue combineMulToPMADDWD(SDNode *N, SelectionDAG &DAG,
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N1.getOperand(1));
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}
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}
41678-
if (!DAG.MaskedValueIsZero(N1, Mask17) ||
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!DAG.MaskedValueIsZero(N0, Mask17))
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if (!!Mask17 && N0.getOpcode() == ISD::SRA) {
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if (isa<ConstantSDNode>(N0.getOperand(1).getOperand(0)) &&
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DAG.ComputeNumSignBits(N1) >= 17 &&
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DAG.isSplatValue(N0.getOperand(1)) &&
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N0.getOperand(1).getConstantOperandVal(0) == 16) {
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Mask17 = 0;
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N0 = DAG.getNode(ISD::SRL, N0.getNode(), VT, N0.getOperand(0),
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N0.getOperand(1));
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}
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}
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if (!!Mask17 && (!DAG.MaskedValueIsZero(N1, Mask17) ||
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!DAG.MaskedValueIsZero(N0, Mask17)))
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return SDValue();
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// Use SplitOpsAndApply to handle AVX splitting.

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