From 87358175634a16296f7318fe49793ee980561f36 Mon Sep 17 00:00:00 2001 From: shannon Date: Fri, 24 Jan 2025 23:34:35 +0800 Subject: [PATCH] support FRDM-MCXA156 --- .github/workflows/bsp_buildings.yml | 1 + .../mcxa/Libraries/MCXA156/MCXA156/MCXA156.h | 38660 ++++++++++++++++ .../MCXA156/MCXA156/MCXA156_features.h | 793 + .../MCXA156/MCXA156/arm/MCXA156_flash.scf | 71 + .../MCXA156/MCXA156/arm/MCXA156_ram.scf | 68 + .../MCXA156/MCXA156/arm/MCXA15X.dbgconf | 18 + .../MCXA156/MCXA156/arm/MCXA15X_1024.FLM | Bin 0 -> 19216 bytes .../MCXA156/MCXA156/arm/startup_MCXA156.S | 1121 + .../MCXA156/MCXA156/drivers/fsl_aoi.c | 230 + .../MCXA156/MCXA156/drivers/fsl_aoi.h | 186 + .../MCXA156/MCXA156/drivers/fsl_cdog.c | 378 + .../MCXA156/MCXA156/drivers/fsl_cdog.h | 329 + .../MCXA156/MCXA156/drivers/fsl_clock.c | 1353 + .../MCXA156/MCXA156/drivers/fsl_clock.h | 983 + .../MCXA156/MCXA156/drivers/fsl_cmc.c | 310 + .../MCXA156/MCXA156/drivers/fsl_cmc.h | 929 + .../MCXA156/MCXA156/drivers/fsl_common.c | 85 + .../MCXA156/MCXA156/drivers/fsl_common.h | 345 + .../MCXA156/MCXA156/drivers/fsl_common_arm.c | 257 + .../MCXA156/MCXA156/drivers/fsl_common_arm.h | 898 + .../MCXA156/MCXA156/drivers/fsl_crc.c | 371 + .../MCXA156/MCXA156/drivers/fsl_crc.h | 181 + .../MCXA156/MCXA156/drivers/fsl_ctimer.c | 604 + .../MCXA156/MCXA156/drivers/fsl_ctimer.h | 682 + .../MCXA156/MCXA156/drivers/fsl_dac.c | 236 + .../MCXA156/MCXA156/drivers/fsl_dac.h | 442 + .../MCXA156/MCXA156/drivers/fsl_edma.c | 2654 ++ .../MCXA156/MCXA156/drivers/fsl_edma.h | 1893 + .../MCXA156/MCXA156/drivers/fsl_edma_core.h | 357 + .../MCXA156/MCXA156/drivers/fsl_edma_soc.c | 112 + .../MCXA156/MCXA156/drivers/fsl_edma_soc.h | 64 + .../MCXA156/MCXA156/drivers/fsl_eim.c | 312 + .../MCXA156/MCXA156/drivers/fsl_eim.h | 144 + .../MCXA156/MCXA156/drivers/fsl_eqdc.c | 301 + .../MCXA156/MCXA156/drivers/fsl_eqdc.h | 1211 + .../MCXA156/MCXA156/drivers/fsl_erm.c | 317 + .../MCXA156/MCXA156/drivers/fsl_erm.h | 235 + .../MCXA156/MCXA156/drivers/fsl_flexcan.c | 4927 ++ .../MCXA156/MCXA156/drivers/fsl_flexcan.h | 2360 + .../MCXA156/drivers/fsl_flexcan_edma.c | 381 + .../MCXA156/drivers/fsl_flexcan_edma.h | 188 + .../MCXA156/MCXA156/drivers/fsl_flexio.c | 511 + .../MCXA156/MCXA156/drivers/fsl_flexio.h | 917 + .../MCXA156/drivers/fsl_flexio_i2c_master.c | 1377 + .../MCXA156/drivers/fsl_flexio_i2c_master.h | 485 + .../MCXA156/drivers/fsl_flexio_mculcd.c | 1334 + .../MCXA156/drivers/fsl_flexio_mculcd.h | 686 + .../MCXA156/drivers/fsl_flexio_mculcd_edma.c | 568 + .../MCXA156/drivers/fsl_flexio_mculcd_edma.h | 153 + .../MCXA156/MCXA156/drivers/fsl_flexio_spi.c | 1565 + .../MCXA156/MCXA156/drivers/fsl_flexio_spi.h | 718 + .../MCXA156/drivers/fsl_flexio_spi_edma.c | 565 + .../MCXA156/drivers/fsl_flexio_spi_edma.h | 207 + .../MCXA156/MCXA156/drivers/fsl_flexio_uart.c | 1023 + .../MCXA156/MCXA156/drivers/fsl_flexio_uart.h | 588 + .../MCXA156/drivers/fsl_flexio_uart_edma.c | 407 + .../MCXA156/drivers/fsl_flexio_uart_edma.h | 178 + .../MCXA156/MCXA156/drivers/fsl_freqme.c | 155 + .../MCXA156/MCXA156/drivers/fsl_freqme.h | 441 + .../MCXA156/MCXA156/drivers/fsl_glikey.c | 403 + .../MCXA156/MCXA156/drivers/fsl_glikey.h | 311 + .../MCXA156/MCXA156/drivers/fsl_gpio.c | 444 + .../MCXA156/MCXA156/drivers/fsl_gpio.h | 799 + .../MCXA156/MCXA156/drivers/fsl_i3c.c | 3572 ++ .../MCXA156/MCXA156/drivers/fsl_i3c.h | 1899 + .../MCXA156/MCXA156/drivers/fsl_i3c_edma.c | 1057 + .../MCXA156/MCXA156/drivers/fsl_i3c_edma.h | 279 + .../MCXA156/MCXA156/drivers/fsl_inputmux.c | 194 + .../MCXA156/MCXA156/drivers/fsl_inputmux.h | 103 + .../drivers/fsl_inputmux_connections.h | 3635 ++ .../MCXA156/MCXA156/drivers/fsl_lpadc.c | 977 + .../MCXA156/MCXA156/drivers/fsl_lpadc.h | 1529 + .../MCXA156/MCXA156/drivers/fsl_lpcmp.c | 372 + .../MCXA156/MCXA156/drivers/fsl_lpcmp.h | 585 + .../MCXA156/MCXA156/drivers/fsl_lpi2c.c | 2715 ++ .../MCXA156/MCXA156/drivers/fsl_lpi2c.h | 1389 + .../MCXA156/MCXA156/drivers/fsl_lpi2c_edma.c | 659 + .../MCXA156/MCXA156/drivers/fsl_lpi2c_edma.h | 163 + .../MCXA156/MCXA156/drivers/fsl_lpspi.c | 2604 ++ .../MCXA156/MCXA156/drivers/fsl_lpspi.h | 1231 + .../MCXA156/MCXA156/drivers/fsl_lpspi_edma.c | 1324 + .../MCXA156/MCXA156/drivers/fsl_lpspi_edma.h | 353 + .../MCXA156/MCXA156/drivers/fsl_lptmr.c | 183 + .../MCXA156/MCXA156/drivers/fsl_lptmr.h | 384 + .../MCXA156/MCXA156/drivers/fsl_lpuart.c | 2742 ++ .../MCXA156/MCXA156/drivers/fsl_lpuart.h | 1128 + .../MCXA156/MCXA156/drivers/fsl_lpuart_edma.c | 522 + .../MCXA156/MCXA156/drivers/fsl_lpuart_edma.h | 189 + .../MCXA156/MCXA156/drivers/fsl_opamp.c | 193 + .../MCXA156/MCXA156/drivers/fsl_opamp.h | 301 + .../MCXA156/MCXA156/drivers/fsl_ostimer.c | 384 + .../MCXA156/MCXA156/drivers/fsl_ostimer.h | 273 + .../MCXA156/MCXA156/drivers/fsl_port.h | 684 + .../MCXA156/MCXA156/drivers/fsl_pwm.c | 1491 + .../MCXA156/MCXA156/drivers/fsl_pwm.h | 1372 + .../MCXA156/MCXA156/drivers/fsl_reset.c | 141 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.../MCXA156/MCXA156/gcc/MCXA156_ram.ld | 199 + .../MCXA156/MCXA156/gcc/startup_MCXA156.S | 1211 + .../MCXA156/MCXA156/iar/MCXA156_flash.icf | 84 + .../MCXA156/MCXA156/iar/MCXA156_ram.icf | 80 + .../MCXA156/MCXA156/iar/startup_MCXA156.s | 953 + .../MCXA156/MCXA156/system_MCXA156.c | 139 + .../MCXA156/MCXA156/system_MCXA156.h | 107 + bsp/nxp/mcx/mcxa/Libraries/MCXA156/SConscript | 54 + bsp/nxp/mcx/mcxa/frdm-mcxa156/.config | 1340 + bsp/nxp/mcx/mcxa/frdm-mcxa156/Kconfig | 18 + bsp/nxp/mcx/mcxa/frdm-mcxa156/SConscript | 14 + bsp/nxp/mcx/mcxa/frdm-mcxa156/SConstruct | 67 + .../mcxa/frdm-mcxa156/applications/SConscript | 15 + .../mcx/mcxa/frdm-mcxa156/applications/main.c | 39 + bsp/nxp/mcx/mcxa/frdm-mcxa156/board/Kconfig | 173 + .../board/MCUX_Config/board/clock_config.c | 482 + .../board/MCUX_Config/board/clock_config.h | 170 + .../board/MCUX_Config/board/pin_mux.c | 121 + .../board/MCUX_Config/board/pin_mux.h | 51 + .../mcx/mcxa/frdm-mcxa156/board/SConscript | 17 + bsp/nxp/mcx/mcxa/frdm-mcxa156/board/board.c | 105 + bsp/nxp/mcx/mcxa/frdm-mcxa156/board/board.h | 54 + .../board/linker_scripts/MCXA156_flash.ld | 200 + .../board/linker_scripts/MCXA156_flash.scf | 71 + bsp/nxp/mcx/mcxa/frdm-mcxa156/project.uvoptx | 1355 + bsp/nxp/mcx/mcxa/frdm-mcxa156/project.uvprojx | 2387 + bsp/nxp/mcx/mcxa/frdm-mcxa156/rtconfig.h | 420 + bsp/nxp/mcx/mcxa/frdm-mcxa156/rtconfig.py | 198 + bsp/nxp/mcx/mcxa/frdm-mcxa156/template.uvoptx | 179 + .../mcx/mcxa/frdm-mcxa156/template.uvprojx | 401 + 146 files changed, 135645 insertions(+) create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/MCXA156.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/MCXA156_features.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/arm/MCXA156_flash.scf create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/arm/MCXA156_ram.scf create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/arm/MCXA15X.dbgconf create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/arm/MCXA15X_1024.FLM create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/arm/startup_MCXA156.S create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_aoi.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_aoi.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_cdog.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_cdog.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_clock.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_clock.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_cmc.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_cmc.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_common.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_common.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_common_arm.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_common_arm.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_crc.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_crc.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_ctimer.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_ctimer.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_dac.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_dac.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_edma.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_edma.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_edma_core.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_edma_soc.c create mode 100644 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bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_uart.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_uart.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_uart_edma.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_uart_edma.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_freqme.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_freqme.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_glikey.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_glikey.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_gpio.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_gpio.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_i3c.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_i3c.h 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bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpi2c_edma.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpi2c_edma.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpspi.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpspi.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpspi_edma.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpspi_edma.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lptmr.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lptmr.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpuart.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpuart.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpuart_edma.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpuart_edma.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_opamp.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_opamp.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_ostimer.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_ostimer.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_port.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_pwm.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_pwm.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_reset.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_reset.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_romapi.h create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_spc.c create mode 100644 bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_spc.h create mode 100644 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bsp/nxp/mcx/mcxa/frdm-mcxa156/board/linker_scripts/MCXA156_flash.ld create mode 100644 bsp/nxp/mcx/mcxa/frdm-mcxa156/board/linker_scripts/MCXA156_flash.scf create mode 100644 bsp/nxp/mcx/mcxa/frdm-mcxa156/project.uvoptx create mode 100644 bsp/nxp/mcx/mcxa/frdm-mcxa156/project.uvprojx create mode 100644 bsp/nxp/mcx/mcxa/frdm-mcxa156/rtconfig.h create mode 100644 bsp/nxp/mcx/mcxa/frdm-mcxa156/rtconfig.py create mode 100644 bsp/nxp/mcx/mcxa/frdm-mcxa156/template.uvoptx create mode 100644 bsp/nxp/mcx/mcxa/frdm-mcxa156/template.uvprojx diff --git a/.github/workflows/bsp_buildings.yml b/.github/workflows/bsp_buildings.yml index a36bbe26110..dd14e2505b7 100644 --- a/.github/workflows/bsp_buildings.yml +++ b/.github/workflows/bsp_buildings.yml @@ -234,6 +234,7 @@ jobs: - "nxp/mcx/mcxn/frdm-mcxn947" - "nxp/mcx/mcxn/frdm-mcxn236" - "nxp/mcx/mcxa/frdm-mcxa153" + - "nxp/mcx/mcxa/frdm-mcxa156" - "renesas/ebf_qi_min_6m5" - "renesas/ra6m4-cpk" - "renesas/ra6m4-iot" diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/MCXA156.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/MCXA156.h new file mode 100644 index 00000000000..000600c5453 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/MCXA156.h @@ -0,0 +1,38660 @@ +/* +** ################################################################### +** Processors: MCXA156VLL +** MCXA156VMP +** MCXA156VPJ +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXA18 User manual +** Version: rev. 1.0, 2022-03-29 +** Build: b240403 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCXA156 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-03-29) +** Initial version based on v0.1UM +** +** ################################################################### +*/ + +/*! + * @file MCXA156.h + * @version 1.0 + * @date 2022-03-29 + * @brief CMSIS Peripheral Access Layer for MCXA156 + * + * CMSIS Peripheral Access Layer for MCXA156 + */ + +#if !defined(MCXA156_H_) +#define MCXA156_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 105 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M33 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M33 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M33 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M33 Usage Fault Interrupt */ + SecureFault_IRQn = -9, /**< Cortex-M33 Secure Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M33 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M33 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M33 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M33 System Tick Interrupt */ + + /* Device specific interrupts */ + Reserved16_IRQn = 0, /**< OR IRQ1 to IRQ53 */ + CMC_IRQn = 1, /**< Core Mode Controller interrupt */ + DMA_CH0_IRQn = 2, /**< DMA3_0_CH0 error or transfer complete */ + DMA_CH1_IRQn = 3, /**< DMA3_0_CH1 error or transfer complete */ + DMA_CH2_IRQn = 4, /**< DMA3_0_CH2 error or transfer complete */ + DMA_CH3_IRQn = 5, /**< DMA3_0_CH3 error or transfer complete */ + DMA_CH4_IRQn = 6, /**< DMA3_0_CH4 error or transfer complete */ + DMA_CH5_IRQn = 7, /**< DMA3_0_CH5 error or transfer complete */ + DMA_CH6_IRQn = 8, /**< DMA3_0_CH6 error or transfer complete */ + DMA_CH7_IRQn = 9, /**< DMA3_0_CH7 error or transfer complete */ + ERM0_SINGLE_BIT_IRQn = 10, /**< ERM Single Bit error interrupt */ + ERM0_MULTI_BIT_IRQn = 11, /**< ERM Multi Bit error interrupt */ + FMU0_IRQn = 12, /**< Flash Management Unit interrupt */ + GLIKEY0_IRQn = 13, /**< GLIKEY Interrupt */ + MBC0_IRQn = 14, /**< MBC secure violation interrupt */ + SCG0_IRQn = 15, /**< System Clock Generator interrupt */ + SPC0_IRQn = 16, /**< System Power Controller interrupt */ + VBAT0_IRQn = 17, /**< VBAT interrupt */ + WUU0_IRQn = 18, /**< Wake Up Unit interrupt */ + CAN0_IRQn = 19, /**< Controller Area Network 0 interrupt */ + Reserved36_IRQn = 20, /**< Reserved interrupt */ + Reserved37_IRQn = 21, /**< Reserved interrupt */ + Reserved38_IRQn = 22, /**< Reserved interrupt */ + FLEXIO_IRQn = 23, /**< Flexible Input/Output interrupt */ + I3C0_IRQn = 24, /**< Improved Inter Integrated Circuit interrupt 0 */ + Reserved41_IRQn = 25, /**< Reserved interrupt */ + LPI2C0_IRQn = 26, /**< Low-Power Inter Integrated Circuit interrupt */ + LPI2C1_IRQn = 27, /**< Low-Power Inter Integrated Circuit interrupt */ + LPSPI0_IRQn = 28, /**< Low-Power Serial Peripheral Interface interrupt */ + LPSPI1_IRQn = 29, /**< Low-Power Serial Peripheral Interface interrupt */ + Reserved46_IRQn = 30, /**< Reserved interrupt */ + LPUART0_IRQn = 31, /**< Low-Power Universal Asynchronous Receive/Transmit interrupt */ + LPUART1_IRQn = 32, /**< Low-Power Universal Asynchronous Receive/Transmit interrupt */ + LPUART2_IRQn = 33, /**< Low-Power Universal Asynchronous Receive/Transmit interrupt */ + LPUART3_IRQn = 34, /**< Low-Power Universal Asynchronous Receive/Transmit interrupt */ + LPUART4_IRQn = 35, /**< Low-Power Universal Asynchronous Receive/Transmit interrupt */ + USB0_IRQn = 36, /**< Universal Serial Bus - Full Speed interrupt */ + Reserved53_IRQn = 37, /**< Reserved interrupt */ + CDOG0_IRQn = 38, /**< Code Watchdog Timer 0 interrupt */ + CTIMER0_IRQn = 39, /**< Standard counter/timer 0 interrupt */ + CTIMER1_IRQn = 40, /**< Standard counter/timer 1 interrupt */ + CTIMER2_IRQn = 41, /**< Standard counter/timer 2 interrupt */ + CTIMER3_IRQn = 42, /**< Standard counter/timer 3 interrupt */ + CTIMER4_IRQn = 43, /**< Standard counter/timer 4 interrupt */ + FLEXPWM0_RELOAD_ERROR_IRQn = 44, /**< FlexPWM0_reload_error interrupt */ + FLEXPWM0_FAULT_IRQn = 45, /**< FlexPWM0_fault interrupt */ + FLEXPWM0_SUBMODULE0_IRQn = 46, /**< FlexPWM0 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE1_IRQn = 47, /**< FlexPWM0 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM0_SUBMODULE2_IRQn = 48, /**< FlexPWM0 Submodule 2 capture/compare/reload interrupt */ + Reserved65_IRQn = 49, /**< Reserved interrupt */ + QDC0_COMPARE_IRQn = 50, /**< Compare */ + QDC0_HOME_IRQn = 51, /**< Home */ + QDC0_WATCHDOG_IRQn = 52, /**< Watchdog / Simultaneous A and B Change */ + QDC0_INDEX_IRQn = 53, /**< Index / Roll Over / Roll Under */ + FREQME0_IRQn = 54, /**< Frequency Measurement interrupt */ + LPTMR0_IRQn = 55, /**< Low Power Timer 0 interrupt */ + Reserved72_IRQn = 56, /**< Reserved interrupt */ + OS_EVENT_IRQn = 57, /**< OS event timer interrupt */ + WAKETIMER0_IRQn = 58, /**< Wake Timer Interrupt */ + UTICK0_IRQn = 59, /**< Micro-Tick Timer interrupt */ + WWDT0_IRQn = 60, /**< Windowed Watchdog Timer 0 interrupt */ + Reserved77_IRQn = 61, /**< Reserved interrupt */ + ADC0_IRQn = 62, /**< Analog-to-Digital Converter interrupt */ + ADC1_IRQn = 63, /**< Analog-to-Digital Converter interrupt */ + CMP0_IRQn = 64, /**< Comparator interrupt */ + CMP1_IRQn = 65, /**< Comparator interrupt */ + Reserved82_IRQn = 66, /**< Reserved interrupt */ + DAC0_IRQn = 67, /**< Digital-to-Analog Converter 0 - General Purpose interrupt */ + Reserved84_IRQn = 68, /**< Reserved interrupt */ + Reserved85_IRQn = 69, /**< Reserved interrupt */ + Reserved86_IRQn = 70, /**< Reserved interrupt */ + GPIO0_IRQn = 71, /**< General Purpose Input/Output interrupt 0 */ + GPIO1_IRQn = 72, /**< General Purpose Input/Output interrupt 1 */ + GPIO2_IRQn = 73, /**< General Purpose Input/Output interrupt 2 */ + GPIO3_IRQn = 74, /**< General Purpose Input/Output interrupt 3 */ + GPIO4_IRQn = 75, /**< General Purpose Input/Output interrupt 4 */ + Reserved92_IRQn = 76, /**< Reserved interrupt */ + LPI2C2_IRQn = 77, /**< Low-Power Inter Integrated Circuit interrupt */ + LPI2C3_IRQn = 78, /**< Low-Power Inter Integrated Circuit interrupt */ + FLEXPWM1_RELOAD_ERROR_IRQn = 79, /**< FlexPWM1_reload_error interrupt */ + FLEXPWM1_FAULT_IRQn = 80, /**< FlexPWM1_fault interrupt */ + FLEXPWM1_SUBMODULE0_IRQn = 81, /**< FlexPWM1 Submodule 0 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE1_IRQn = 82, /**< FlexPWM1 Submodule 1 capture/compare/reload interrupt */ + FLEXPWM1_SUBMODULE2_IRQn = 83, /**< FlexPWM1 Submodule 2 capture/compare/reload interrupt */ + Reserved100_IRQn = 84, /**< Reserved interrupt */ + QDC1_COMPARE_IRQn = 85, /**< Compare */ + QDC1_HOME_IRQn = 86, /**< Home */ + QDC1_WATCHDOG_IRQn = 87, /**< Watchdog / Simultaneous A and B Change */ + QDC1_INDEX_IRQn = 88 /**< Index / Roll Over / Roll Under */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M33 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M33 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ +#define __DSP_PRESENT 1 /**< Defines if Armv8-M Mainline core supports DSP instructions */ +#define __SAUREGION_PRESENT 0 /**< Defines if an SAU is present or not */ + +#include "core_cm33.h" /* Core Peripheral Access Layer */ +#include "system_MCXA156.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup dma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the DMA hardware request + * + * Defines the structure for the DMA hardware request collections. The user can configure the + * hardware request to trigger the DMA transfer accordingly. The index + * of the hardware request varies according to the to SoC. + */ +typedef enum _dma_request_source +{ + kDma0RequestDisabled = 0U, /**< Disabled */ + kDma0RequestWUU0 = 1U, /**< WUU Wake up event */ + kDma0RequestMuxFlexCan0DmaRequest = 2U, /**< CAN0 DMA request */ + kDma0RequestLPI2C2Rx = 3U, /**< LPI2C2 Receive request */ + kDma0RequestLPI2C2Tx = 4U, /**< LPI2C2 Transmit request */ + kDma0RequestLPI2C3Rx = 5U, /**< LPI2C3 Receive request */ + kDma0RequestLPI2C3Tx = 6U, /**< LPI2C3 Transmit request */ + kDma0RequestMuxI3c0Rx = 7U, /**< I3C0 Receive request */ + kDma0RequestMuxI3c0Tx = 8U, /**< I3C0 Transmit request */ + kDma0RequestLPI2C0Rx = 11U, /**< LPI2C0 Receive request */ + kDma0RequestLPI2C0Tx = 12U, /**< LPI2C0 Transmit request */ + kDma0RequestLPI2C1Rx = 13U, /**< LPI2C1 Receive request */ + kDma0RequestLPI2C1Tx = 14U, /**< LPI2C1 Transmit request */ + kDma0RequestLPSPI0Rx = 15U, /**< LPSPI0 Receive request */ + kDma0RequestLPSPI0Tx = 16U, /**< LPSPI0 Transmit request */ + kDma0RequestLPSPI1Rx = 17U, /**< LPSPI1 Receive request */ + kDma0RequestLPSPI1Tx = 18U, /**< LPSPI1 Transmit request */ + kDma0RequestLPUART0Rx = 21U, /**< LPUART0 Receive request */ + kDma0RequestLPUART0Tx = 22U, /**< LPUART0 Transmit request */ + kDma0RequestLPUART1Rx = 23U, /**< LPUART1 Receive request */ + kDma0RequestLPUART1Tx = 24U, /**< LPUART1 Transmit request */ + kDma0RequestLPUART2Rx = 25U, /**< LPUART2 Receive request */ + kDma0RequestLPUART2Tx = 26U, /**< LPUART2 Transmit request */ + kDma0RequestLPUART3Rx = 27U, /**< LPUART3 Receive request */ + kDma0RequestLPUART3Tx = 28U, /**< LPUART3 Transmit request */ + kDma0RequestLPUART4Rx = 29U, /**< LPUART4 Receive request */ + kDma0RequestLPUART4Tx = 30U, /**< LPUART4 Transmit request */ + kDma0RequestMuxCtimer0M0 = 31U, /**< CTIMER0 Match channel 0 request */ + kDma0RequestMuxCtimer0M1 = 32U, /**< CTIMER0 Match channel 1 request */ + kDma0RequestMuxCtimer1M0 = 33U, /**< CTIMER1 Match channel 0 request */ + kDma0RequestMuxCtimer1M1 = 34U, /**< CTIMER1 Match channel 1 request */ + kDma0RequestMuxCtimer2M0 = 35U, /**< CTIMER2 Match channel 0 request */ + kDma0RequestMuxCtimer2M1 = 36U, /**< CTIMER2 Match channel 1 request */ + kDma0RequestMuxCtimer3M0 = 37U, /**< CTIMER3 Match channel 0 request */ + kDma0RequestMuxCtimer3M1 = 38U, /**< CTIMER3 Match channel 1 request */ + kDma0RequestMuxCtimer4M0 = 39U, /**< CTIMER4 Match channel 0 request */ + kDma0RequestMuxCtimer4M1 = 40U, /**< CTIMER4 Match channel 1 request */ + kDma0RequestMuxFlexPWM0ReqCapt0 = 41U, /**< FlexPWM0 capture0 request */ + kDma0RequestMuxFlexPWM0ReqCapt1 = 42U, /**< FlexPWM0 capture1 request */ + kDma0RequestMuxFlexPWM0ReqCapt2 = 43U, /**< FlexPWM0 capture2 request */ + kDma0RequestMuxFlexPWM0ReqVal0 = 45U, /**< FlexPWM0 value0 request */ + kDma0RequestMuxFlexPWM0ReqVal1 = 46U, /**< FlexPWM0 value1 request */ + kDma0RequestMuxFlexPWM0ReqVal2 = 47U, /**< FlexPWM0 value2 request */ + kDma0RequestMuxLptmr0 = 49U, /**< LPTMR0 Counter match event */ + kDma0RequestMuxAdc0FifoRequest = 51U, /**< ADC0 FIFO request */ + kDma0RequestMuxAdc1FifoRequest = 52U, /**< ADC1 FIFO request */ + kDma0RequestMuxHsCmp0DmaRequest = 53U, /**< CMP0 DMA_request */ + kDma0RequestMuxHsCmp1DmaRequest = 54U, /**< CMP1 DMA_request */ + kDma0RequestMuxDac0FifoRequest = 56U, /**< DAC0 FIFO request */ + kDma0RequestMuxGpio0PinEventRequest0 = 60U, /**< GPIO0 Pin event request 0 */ + kDma0RequestMuxGpio1PinEventRequest0 = 61U, /**< GPIO1 Pin event request 0 */ + kDma0RequestMuxGpio2PinEventRequest0 = 62U, /**< GPIO2 Pin event request 0 */ + kDma0RequestMuxGpio3PinEventRequest0 = 63U, /**< GPIO3 Pin event request 0 */ + kDma0RequestMuxGpio4PinEventRequest0 = 64U, /**< GPIO4 Pin event request 0 */ + kDma0RequestMuxQdc0 = 65U, /**< DMA request for new buffered value */ + kDma0RequestMuxQdc1 = 66U, /**< DMA request for new buffered value */ + kDma0RequestMuxFlexIO0ShiftRegister0Request = 71U, /**< FlexIO0 Shifter0 Status DMA request OR Timer0 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister1Request = 72U, /**< FlexIO0 Shifter1 Status DMA request OR Timer1 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister2Request = 73U, /**< FlexIO0 Shifter2 Status DMA request OR Timer2 Status DMA request */ + kDma0RequestMuxFlexIO0ShiftRegister3Request = 74U, /**< FlexIO0 Shifter3 Status DMA request OR Timer3 Status DMA request */ + kDma0RequestMuxFlexPWM1ReqCapt0 = 79U, /**< FlexPWM1 capture0 request */ + kDma0RequestMuxFlexPWM1ReqCapt1 = 80U, /**< FlexPWM1 capture1 request */ + kDma0RequestMuxFlexPWM1ReqCapt2 = 81U, /**< FlexPWM1 capture2 request */ + kDma0RequestMuxFlexPWM1ReqVal0 = 83U, /**< FlexPWM1 value0 request */ + kDma0RequestMuxFlexPWM1ReqVal1 = 84U, /**< FlexPWM1 value1 request */ + kDma0RequestMuxFlexPWM1ReqVal2 = 85U, /**< FlexPWM1 value2 request */ +} dma_request_source_t; + +/* @} */ + +/*! + * @addtogroup eim_memory_channel + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the eim_memory_channel + * + * Defines the structure for the EIM resource collections. + */ + +typedef enum _eim_memory_channel +{ + kEIM_MemoryChannelRAMA0 = 0U, /**< Memory RAMA0 */ +} eim_memory_channel_t; + +/* @} */ + +/*! + * @addtogroup eim_error_injection_channel_enable + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the eim_error_injection_channel_enable + * + * Defines the structure for the EIM error injection resource collections. + */ + +typedef enum _eim_error_injection_channel_enable +{ + kEIM_MemoryChannelRAMAEnable = 0x80000000U, /**< Memory channel 0(RAMA0) error injection enable */ +} eim_error_injection_channel_enable_t; + +/* @} */ + +/*! + * @addtogroup erm_memory_channel + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Structure for the erm_memory_channel + * + * Defines the structure for the ERM resource collections. + */ + +typedef enum _erm_memory_channel +{ + kERM_MemoryChannelRAMA0 = 0U, /**< Memory RAMA0 */ + kERM_MemoryChannelFLASH = 1U, /**< Memory FLASH */ +} erm_memory_channel_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CTRL; /**< Control Register, offset: 0x10 */ + __IO uint32_t STAT; /**< Status Register, offset: 0x14 */ + __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ + __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ + __IO uint32_t CFG; /**< Configuration Register, offset: 0x20 */ + __IO uint32_t PAUSE; /**< Pause Register, offset: 0x24 */ + uint8_t RESERVED_1[12]; + __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ + __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ + uint8_t RESERVED_2[4]; + __IO uint32_t OFSTRIM; /**< Offset Trim Register, offset: 0x40 */ + uint8_t RESERVED_3[4]; + __IO uint32_t HSTRIM; /**< High Speed Trim Register, offset: 0x48 */ + uint8_t RESERVED_4[84]; + __IO uint32_t TCTRL[4]; /**< Trigger Control Register, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_5[48]; + __IO uint32_t FCTRL; /**< FIFO Control Register, offset: 0xE0 */ + uint8_t RESERVED_6[12]; + __I uint32_t GCC[1]; /**< Gain Calibration Control, array offset: 0xF0, array step: 0x4 */ + uint8_t RESERVED_7[4]; + __IO uint32_t GCR[1]; /**< Gain Calculation Result, array offset: 0xF8, array step: 0x4 */ + uint8_t RESERVED_8[4]; + struct { /* offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDL; /**< Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDH; /**< Command High Buffer Register, array offset: 0x104, array step: 0x8 */ + } CMD[7]; + uint8_t RESERVED_9[200]; + __IO uint32_t CV[7]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_10[228]; + __I uint32_t RESFIFO; /**< Data Result FIFO Register, offset: 0x300 */ + uint8_t RESERVED_11[252]; + __IO uint32_t CAL_GAR0; /**< Calibration General A-Side Registers, offset: 0x400 */ + __IO uint32_t CAL_GAR1; /**< Calibration General A-Side Registers, offset: 0x404 */ + __IO uint32_t CAL_GAR2; /**< Calibration General A-Side Registers, offset: 0x408 */ + __IO uint32_t CAL_GAR3; /**< Calibration General A-Side Registers, offset: 0x40C */ + __IO uint32_t CAL_GAR4; /**< Calibration General A-Side Registers, offset: 0x410 */ + __IO uint32_t CAL_GAR5; /**< Calibration General A-Side Registers, offset: 0x414 */ + __IO uint32_t CAL_GAR6; /**< Calibration General A-Side Registers, offset: 0x418 */ + __IO uint32_t CAL_GAR7; /**< Calibration General A-Side Registers, offset: 0x41C */ + __IO uint32_t CAL_GAR8; /**< Calibration General A-Side Registers, offset: 0x420 */ + __IO uint32_t CAL_GAR9; /**< Calibration General A-Side Registers, offset: 0x424 */ + __IO uint32_t CAL_GAR10; /**< Calibration General A-Side Registers, offset: 0x428 */ + __IO uint32_t CAL_GAR11; /**< Calibration General A-Side Registers, offset: 0x42C */ + __IO uint32_t CAL_GAR12; /**< Calibration General A-Side Registers, offset: 0x430 */ + __IO uint32_t CAL_GAR13; /**< Calibration General A-Side Registers, offset: 0x434 */ + __IO uint32_t CAL_GAR14; /**< Calibration General A-Side Registers, offset: 0x438 */ + __IO uint32_t CAL_GAR15; /**< Calibration General A-Side Registers, offset: 0x43C */ + __IO uint32_t CAL_GAR16; /**< Calibration General A-Side Registers, offset: 0x440 */ + __IO uint32_t CAL_GAR17; /**< Calibration General A-Side Registers, offset: 0x444 */ + __IO uint32_t CAL_GAR18; /**< Calibration General A-Side Registers, offset: 0x448 */ + __IO uint32_t CAL_GAR19; /**< Calibration General A-Side Registers, offset: 0x44C */ + __IO uint32_t CAL_GAR20; /**< Calibration General A-Side Registers, offset: 0x450 */ + __IO uint32_t CAL_GAR21; /**< Calibration General A-Side Registers, offset: 0x454 */ + __IO uint32_t CAL_GAR22; /**< Calibration General A-Side Registers, offset: 0x458 */ + __IO uint32_t CAL_GAR23; /**< Calibration General A-Side Registers, offset: 0x45C */ + __IO uint32_t CAL_GAR24; /**< Calibration General A-Side Registers, offset: 0x460 */ + __IO uint32_t CAL_GAR25; /**< Calibration General A-Side Registers, offset: 0x464 */ + __IO uint32_t CAL_GAR26; /**< Calibration General A-Side Registers, offset: 0x468 */ + __IO uint32_t CAL_GAR27; /**< Calibration General A-Side Registers, offset: 0x46C */ + __IO uint32_t CAL_GAR28; /**< Calibration General A-Side Registers, offset: 0x470 */ + __IO uint32_t CAL_GAR29; /**< Calibration General A-Side Registers, offset: 0x474 */ + __IO uint32_t CAL_GAR30; /**< Calibration General A-Side Registers, offset: 0x478 */ + __IO uint32_t CAL_GAR31; /**< Calibration General A-Side Registers, offset: 0x47C */ + __IO uint32_t CAL_GAR32; /**< Calibration General A-Side Registers, offset: 0x480 */ + __IO uint32_t CAL_GAR33; /**< Calibration General A-Side Registers, offset: 0x484 */ + uint8_t RESERVED_12[2928]; + __IO uint32_t CFG2; /**< Configuration 2 Register, offset: 0xFF8 */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ + +#define ADC_VERID_RES_MASK (0x1U) +#define ADC_VERID_RES_SHIFT (0U) +/*! RES - Resolution + * 0b0..Up to 12-bit single ended resolution supported (and 13-bit differential resolution if VERID[DIFFEN] = 1b). + * 0b1..Up to 16-bit single ended resolution supported (and 16-bit differential resolution if VERID[DIFFEN] = 1b). + */ +#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) + +#define ADC_VERID_DIFFEN_MASK (0x2U) +#define ADC_VERID_DIFFEN_SHIFT (1U) +/*! DIFFEN - Differential Supported + * 0b0..Differential operation not supported. + * 0b1..Differential operation supported. + */ +#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) + +#define ADC_VERID_MVI_MASK (0x8U) +#define ADC_VERID_MVI_SHIFT (3U) +/*! MVI - Multi Vref Implemented + * 0b0..Single voltage reference high (VREFH) input supported. + * 0b1..Multiple voltage reference high (VREFH) inputs supported. + */ +#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) + +#define ADC_VERID_CSW_MASK (0x70U) +#define ADC_VERID_CSW_SHIFT (4U) +/*! CSW - Channel Scale Width + * 0b000..Channel scaling not supported. + * 0b001..Channel scaling supported. 1-bit CSCALE control field. + * 0b110..Channel scaling supported. 6-bit CSCALE control field. + */ +#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) + +#define ADC_VERID_VR1RNGI_MASK (0x100U) +#define ADC_VERID_VR1RNGI_SHIFT (8U) +/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented + * 0b0..Range control not required. CFG[VREF1RNG] is not implemented. + * 0b1..Range control required. CFG[VREF1RNG] is implemented. + */ +#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) + +#define ADC_VERID_IADCKI_MASK (0x200U) +#define ADC_VERID_IADCKI_SHIFT (9U) +/*! IADCKI - Internal ADC Clock Implemented + * 0b0..Internal clock source not implemented. + * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. + */ +#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) + +#define ADC_VERID_CALOFSI_MASK (0x400U) +#define ADC_VERID_CALOFSI_SHIFT (10U) +/*! CALOFSI - Calibration Function Implemented + * 0b0..Calibration Not Implemented. + * 0b1..Calibration Implemented. + */ +#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) + +#define ADC_VERID_NUM_SEC_MASK (0x800U) +#define ADC_VERID_NUM_SEC_SHIFT (11U) +/*! NUM_SEC - Number of Single Ended Outputs Supported + * 0b0..This design supports one single ended conversion at a time. + * 0b1..This design supports two simultaneous single ended conversions. + */ +#define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) + +#define ADC_VERID_NUM_FIFO_MASK (0x7000U) +#define ADC_VERID_NUM_FIFO_SHIFT (12U) +/*! NUM_FIFO - Number of FIFOs + * 0b000..N/A + * 0b001..This design supports one result FIFO. + * 0b010..This design supports two result FIFOs. + * 0b011..This design supports three result FIFOs. + * 0b100..This design supports four result FIFOs. + */ +#define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) + +#define ADC_VERID_MINOR_MASK (0xFF0000U) +#define ADC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) + +#define ADC_VERID_MAJOR_MASK (0xFF000000U) +#define ADC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ + +#define ADC_PARAM_TRIG_NUM_MASK (0xFFU) +#define ADC_PARAM_TRIG_NUM_SHIFT (0U) +/*! TRIG_NUM - Trigger Number */ +#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) + +#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) +#define ADC_PARAM_FIFOSIZE_SHIFT (8U) +/*! FIFOSIZE - Result FIFO Depth + * 0b00000001..Result FIFO depth = 2 dataword. + * 0b00000100..Result FIFO depth = 4 datawords. + * 0b00001000..Result FIFO depth = 8 datawords. + * 0b00010000..Result FIFO depth = 16 datawords. + * 0b00100000..Result FIFO depth = 32 datawords. + * 0b01000000..Result FIFO depth = 64 datawords. + */ +#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) + +#define ADC_PARAM_CV_NUM_MASK (0xFF0000U) +#define ADC_PARAM_CV_NUM_SHIFT (16U) +/*! CV_NUM - Compare Value Number */ +#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) + +#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) +#define ADC_PARAM_CMD_NUM_SHIFT (24U) +/*! CMD_NUM - Command Buffer Number */ +#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) +/*! @} */ + +/*! @name CTRL - Control Register */ +/*! @{ */ + +#define ADC_CTRL_ADCEN_MASK (0x1U) +#define ADC_CTRL_ADCEN_SHIFT (0U) +/*! ADCEN - ADC Enable + * 0b0..ADC is disabled. + * 0b1..ADC is enabled. + */ +#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) + +#define ADC_CTRL_RST_MASK (0x2U) +#define ADC_CTRL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..ADC logic is not reset. + * 0b1..ADC logic is reset. + */ +#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) + +#define ADC_CTRL_DOZEN_MASK (0x4U) +#define ADC_CTRL_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Enable + * 0b0..ADC is enabled in low power mode. + * 0b1..ADC is disabled in low power mode. + */ +#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) + +#define ADC_CTRL_CAL_REQ_MASK (0x8U) +#define ADC_CTRL_CAL_REQ_SHIFT (3U) +/*! CAL_REQ - Auto-Calibration Request + * 0b0..No request for hardware calibration has been made + * 0b1..A request for hardware calibration has been made + */ +#define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) + +#define ADC_CTRL_CALOFS_MASK (0x10U) +#define ADC_CTRL_CALOFS_SHIFT (4U) +/*! CALOFS - Offset Calibration Request + * 0b0..No request for offset calibration has been made + * 0b1..Request for offset calibration function + */ +#define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) + +#define ADC_CTRL_CALHS_MASK (0x40U) +#define ADC_CTRL_CALHS_SHIFT (6U) +/*! CALHS - High Speed Mode Trim Request + * 0b0..No request for high speed mode trim has been made + * 0b1..Request for high speed mode trim has been made + */ +#define ADC_CTRL_CALHS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALHS_SHIFT)) & ADC_CTRL_CALHS_MASK) + +#define ADC_CTRL_RSTFIFO0_MASK (0x100U) +#define ADC_CTRL_RSTFIFO0_SHIFT (8U) +/*! RSTFIFO0 - Reset FIFO 0 + * 0b0..No effect. + * 0b1..FIFO 0 is reset. + */ +#define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) + +#define ADC_CTRL_CAL_AVGS_MASK (0xF0000U) +#define ADC_CTRL_CAL_AVGS_SHIFT (16U) +/*! CAL_AVGS - Auto-Calibration Averages + * 0b0000..Single conversion. + * 0b0001..2 conversions averaged. + * 0b0010..4 conversions averaged. + * 0b0011..8 conversions averaged. + * 0b0100..16 conversions averaged. + * 0b0101..32 conversions averaged. + * 0b0110..64 conversions averaged. + * 0b0111..128 conversions averaged. + * 0b1000..256 conversions averaged. + * 0b1001..512 conversions averaged. + * 0b1010..1024 conversions averaged. + */ +#define ADC_CTRL_CAL_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_AVGS_SHIFT)) & ADC_CTRL_CAL_AVGS_MASK) +/*! @} */ + +/*! @name STAT - Status Register */ +/*! @{ */ + +#define ADC_STAT_RDY0_MASK (0x1U) +#define ADC_STAT_RDY0_SHIFT (0U) +/*! RDY0 - Result FIFO 0 Ready Flag + * 0b0..Result FIFO 0 data level not above watermark level. + * 0b1..Result FIFO 0 holding data above watermark level. + */ +#define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) + +#define ADC_STAT_FOF0_MASK (0x2U) +#define ADC_STAT_FOF0_SHIFT (1U) +/*! FOF0 - Result FIFO 0 Overflow Flag + * 0b0..No result FIFO 0 overflow has occurred since the last time the flag was cleared. + * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. + */ +#define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) + +#define ADC_STAT_TEXC_INT_MASK (0x100U) +#define ADC_STAT_TEXC_INT_SHIFT (8U) +/*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception + * 0b0..No trigger exceptions have occurred. + * 0b1..A trigger exception has occurred and is pending acknowledgement. + */ +#define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) + +#define ADC_STAT_TCOMP_INT_MASK (0x200U) +#define ADC_STAT_TCOMP_INT_SHIFT (9U) +/*! TCOMP_INT - Interrupt Flag For Trigger Completion + * 0b0..Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. + * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. + */ +#define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) + +#define ADC_STAT_CAL_RDY_MASK (0x400U) +#define ADC_STAT_CAL_RDY_SHIFT (10U) +/*! CAL_RDY - Calibration Ready + * 0b0..Calibration is incomplete or hasn't been ran. + * 0b1..The ADC is calibrated. + */ +#define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) + +#define ADC_STAT_ADC_ACTIVE_MASK (0x800U) +#define ADC_STAT_ADC_ACTIVE_SHIFT (11U) +/*! ADC_ACTIVE - ADC Active + * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. + * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. + */ +#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) + +#define ADC_STAT_TRGACT_MASK (0x30000U) +#define ADC_STAT_TRGACT_SHIFT (16U) +/*! TRGACT - Trigger Active + * 0b00..Command (sequence) associated with Trigger 0 currently being executed. + * 0b01..Command (sequence) associated with Trigger 1 currently being executed. + * 0b10..Command (sequence) associated with Trigger 2 currently being executed. + * 0b11..Command (sequence) associated with Trigger 3 currently being executed. + */ +#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) + +#define ADC_STAT_CMDACT_MASK (0x7000000U) +#define ADC_STAT_CMDACT_SHIFT (24U) +/*! CMDACT - Command Active + * 0b000..No command is currently in progress. + * 0b001..Command 1 currently being executed. + * 0b010..Command 2 currently being executed. + * 0b011-0b111..Associated command number is currently being executed. + */ +#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK) +/*! @} */ + +/*! @name IE - Interrupt Enable Register */ +/*! @{ */ + +#define ADC_IE_FWMIE0_MASK (0x1U) +#define ADC_IE_FWMIE0_SHIFT (0U) +/*! FWMIE0 - FIFO 0 Watermark Interrupt Enable + * 0b0..FIFO 0 watermark interrupts are not enabled. + * 0b1..FIFO 0 watermark interrupts are enabled. + */ +#define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) + +#define ADC_IE_FOFIE0_MASK (0x2U) +#define ADC_IE_FOFIE0_SHIFT (1U) +/*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable + * 0b0..FIFO 0 overflow interrupts are not enabled. + * 0b1..FIFO 0 overflow interrupts are enabled. + */ +#define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) + +#define ADC_IE_TEXC_IE_MASK (0x100U) +#define ADC_IE_TEXC_IE_SHIFT (8U) +/*! TEXC_IE - Trigger Exception Interrupt Enable + * 0b0..Trigger exception interrupts are disabled. + * 0b1..Trigger exception interrupts are enabled. + */ +#define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) + +#define ADC_IE_TCOMP_IE_MASK (0xF0000U) +#define ADC_IE_TCOMP_IE_SHIFT (16U) +/*! TCOMP_IE - Trigger Completion Interrupt Enable + * 0b0000..Trigger completion interrupts are disabled. + * 0b0001..Trigger completion interrupts are enabled for trigger source 0 only. + * 0b0010..Trigger completion interrupts are enabled for trigger source 1 only. + * 0b0011-0b1110..Associated trigger completion interrupts are enabled. + * 0b1111..Trigger completion interrupts are enabled for every trigger source. + */ +#define ADC_IE_TCOMP_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TCOMP_IE_SHIFT)) & ADC_IE_TCOMP_IE_MASK) +/*! @} */ + +/*! @name DE - DMA Enable Register */ +/*! @{ */ + +#define ADC_DE_FWMDE0_MASK (0x1U) +#define ADC_DE_FWMDE0_SHIFT (0U) +/*! FWMDE0 - FIFO 0 Watermark DMA Enable + * 0b0..DMA request disabled. + * 0b1..DMA request enabled. + */ +#define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) +/*! @} */ + +/*! @name CFG - Configuration Register */ +/*! @{ */ + +#define ADC_CFG_TPRICTRL_MASK (0x3U) +#define ADC_CFG_TPRICTRL_SHIFT (0U) +/*! TPRICTRL - ADC Trigger Priority Control + * 0b00..If a higher priority trigger is detected during command processing, the current conversion is aborted + * and the new command specified by the trigger is started. + * 0b01..If a higher priority trigger is received during command processing, the current command is stopped after + * completing the current conversion. If averaging is enabled, the averaging loop will be completed. + * However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. + * 0b10..If a higher priority trigger is received during command processing, the current command will be + * completed (averaging, looping, compare) before servicing the higher priority trigger. + * 0b11.. + */ +#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) + +#define ADC_CFG_PWRSEL_MASK (0x20U) +#define ADC_CFG_PWRSEL_SHIFT (5U) +/*! PWRSEL - Power Configuration Select + * 0b0..Low power + * 0b1..High power + */ +#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) + +#define ADC_CFG_REFSEL_MASK (0xC0U) +#define ADC_CFG_REFSEL_SHIFT (6U) +/*! REFSEL - Voltage Reference Selection + * 0b00..(Default) Option 1 setting. + * 0b01..Option 2 setting. + * 0b10..Option 3 setting. + * 0b11..Reserved + */ +#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) + +#define ADC_CFG_TRES_MASK (0x100U) +#define ADC_CFG_TRES_SHIFT (8U) +/*! TRES - Trigger Resume Enable + * 0b0..Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted. + * 0b1..Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted. + */ +#define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) + +#define ADC_CFG_TCMDRES_MASK (0x200U) +#define ADC_CFG_TCMDRES_SHIFT (9U) +/*! TCMDRES - Trigger Command Resume + * 0b0..Trigger sequences interrupted by a high priority trigger exception is automatically restarted. + * 0b1..Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception. + */ +#define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) + +#define ADC_CFG_HPT_EXDI_MASK (0x400U) +#define ADC_CFG_HPT_EXDI_SHIFT (10U) +/*! HPT_EXDI - High Priority Trigger Exception Disable + * 0b0..High priority trigger exceptions are enabled. + * 0b1..High priority trigger exceptions are disabled. + */ +#define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) + +#define ADC_CFG_PUDLY_MASK (0xFF0000U) +#define ADC_CFG_PUDLY_SHIFT (16U) +/*! PUDLY - Power Up Delay */ +#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) + +#define ADC_CFG_PWREN_MASK (0x10000000U) +#define ADC_CFG_PWREN_SHIFT (28U) +/*! PWREN - ADC Analog Pre-Enable + * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. + * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost + * of higher DC current consumption). Note that a single power up delay (CFG[PUDLY]) is executed immediately + * once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has + * passed. After this initial delay expires the analog remains pre-enabled and no additional delays are + * executed. + */ +#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) +/*! @} */ + +/*! @name PAUSE - Pause Register */ +/*! @{ */ + +#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) +#define ADC_PAUSE_PAUSEDLY_SHIFT (0U) +/*! PAUSEDLY - Pause Delay */ +#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) + +#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) +#define ADC_PAUSE_PAUSEEN_SHIFT (31U) +/*! PAUSEEN - PAUSE Option Enable + * 0b0..Pause operation disabled + * 0b1..Pause operation enabled + */ +#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) +/*! @} */ + +/*! @name SWTRIG - Software Trigger Register */ +/*! @{ */ + +#define ADC_SWTRIG_SWT0_MASK (0x1U) +#define ADC_SWTRIG_SWT0_SHIFT (0U) +/*! SWT0 - Software Trigger 0 Event + * 0b0..No trigger 0 event generated. + * 0b1..Trigger 0 event generated. + */ +#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) + +#define ADC_SWTRIG_SWT1_MASK (0x2U) +#define ADC_SWTRIG_SWT1_SHIFT (1U) +/*! SWT1 - Software Trigger 1 Event + * 0b0..No trigger 1 event generated. + * 0b1..Trigger 1 event generated. + */ +#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) + +#define ADC_SWTRIG_SWT2_MASK (0x4U) +#define ADC_SWTRIG_SWT2_SHIFT (2U) +/*! SWT2 - Software Trigger 2 Event + * 0b0..No trigger 2 event generated. + * 0b1..Trigger 2 event generated. + */ +#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) + +#define ADC_SWTRIG_SWT3_MASK (0x8U) +#define ADC_SWTRIG_SWT3_SHIFT (3U) +/*! SWT3 - Software Trigger 3 Event + * 0b0..No trigger 3 event generated. + * 0b1..Trigger 3 event generated. + */ +#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) +/*! @} */ + +/*! @name TSTAT - Trigger Status Register */ +/*! @{ */ + +#define ADC_TSTAT_TEXC_NUM_MASK (0xFU) +#define ADC_TSTAT_TEXC_NUM_SHIFT (0U) +/*! TEXC_NUM - Trigger Exception Number + * 0b0000..No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. + * 0b0001..Trigger 0 has been interrupted by a high priority exception. + * 0b0010..Trigger 1 has been interrupted by a high priority exception. + * 0b0011-0b1110..Associated trigger sequence has interrupted by a high priority exception. + * 0b1111..Every trigger sequence has been interrupted by a high priority exception. + */ +#define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) + +#define ADC_TSTAT_TCOMP_FLAG_MASK (0xF0000U) +#define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) +/*! TCOMP_FLAG - Trigger Completion Flag + * 0b0000..No triggers have been completed. Trigger completion interrupts are disabled. + * 0b0001..Trigger 0 has been completed and trigger 0 has enabled completion interrupts. + * 0b0010..Trigger 1 has been completed and trigger 1 has enabled completion interrupts. + * 0b0011-0b1110..Associated trigger sequence has completed and has enabled completion interrupts. + * 0b1111..Every trigger sequence has been completed and every trigger has enabled completion interrupts. + */ +#define ADC_TSTAT_TCOMP_FLAG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TCOMP_FLAG_SHIFT)) & ADC_TSTAT_TCOMP_FLAG_MASK) +/*! @} */ + +/*! @name OFSTRIM - Offset Trim Register */ +/*! @{ */ + +#define ADC_OFSTRIM_OFSTRIM_MASK (0x3FFU) +#define ADC_OFSTRIM_OFSTRIM_SHIFT (0U) +/*! OFSTRIM - Trim for Offset */ +#define ADC_OFSTRIM_OFSTRIM(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_SHIFT)) & ADC_OFSTRIM_OFSTRIM_MASK) +/*! @} */ + +/*! @name HSTRIM - High Speed Trim Register */ +/*! @{ */ + +#define ADC_HSTRIM_HSTRIM_MASK (0x1FU) +#define ADC_HSTRIM_HSTRIM_SHIFT (0U) +/*! HSTRIM - Trim for High Speed Conversions */ +#define ADC_HSTRIM_HSTRIM(x) (((uint32_t)(((uint32_t)(x)) << ADC_HSTRIM_HSTRIM_SHIFT)) & ADC_HSTRIM_HSTRIM_MASK) +/*! @} */ + +/*! @name TCTRL - Trigger Control Register */ +/*! @{ */ + +#define ADC_TCTRL_HTEN_MASK (0x1U) +#define ADC_TCTRL_HTEN_SHIFT (0U) +/*! HTEN - Trigger Enable + * 0b0..Hardware trigger source disabled + * 0b1..Hardware trigger source enabled + */ +#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) + +#define ADC_TCTRL_TPRI_MASK (0x300U) +#define ADC_TCTRL_TPRI_SHIFT (8U) +/*! TPRI - Trigger Priority Setting + * 0b00..Set to highest priority, Level 1 + * 0b01-0b10..Set to corresponding priority level + * 0b11..Set to lowest priority, Level 4 + */ +#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) + +#define ADC_TCTRL_RSYNC_MASK (0x8000U) +#define ADC_TCTRL_RSYNC_SHIFT (15U) +/*! RSYNC - Trigger Resync */ +#define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) + +#define ADC_TCTRL_TDLY_MASK (0xF0000U) +#define ADC_TCTRL_TDLY_SHIFT (16U) +/*! TDLY - Trigger Delay Select */ +#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) + +#define ADC_TCTRL_TSYNC_MASK (0x800000U) +#define ADC_TCTRL_TSYNC_SHIFT (23U) +/*! TSYNC - Trigger Synchronous Select */ +#define ADC_TCTRL_TSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TSYNC_SHIFT)) & ADC_TCTRL_TSYNC_MASK) + +#define ADC_TCTRL_TCMD_MASK (0x7000000U) +#define ADC_TCTRL_TCMD_SHIFT (24U) +/*! TCMD - Trigger Command Select + * 0b000..Not a valid selection from the command buffer. Trigger event is ignored. + * 0b001..CMD1 is executed + * 0b010-0b110..Corresponding CMD is executed + * 0b111..CMD7 is executed + */ +#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK) +/*! @} */ + +/* The count of ADC_TCTRL */ +#define ADC_TCTRL_COUNT (4U) + +/*! @name FCTRL - FIFO Control Register */ +/*! @{ */ + +#define ADC_FCTRL_FCOUNT_MASK (0xFU) +#define ADC_FCTRL_FCOUNT_SHIFT (0U) +/*! FCOUNT - Result FIFO Counter */ +#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) + +#define ADC_FCTRL_FWMARK_MASK (0x70000U) +#define ADC_FCTRL_FWMARK_SHIFT (16U) +/*! FWMARK - Watermark Level Selection */ +#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) +/*! @} */ + +/*! @name GCC - Gain Calibration Control */ +/*! @{ */ + +#define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) +#define ADC_GCC_GAIN_CAL_SHIFT (0U) +/*! GAIN_CAL - Gain Calibration Value */ +#define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) + +#define ADC_GCC_RDY_MASK (0x1000000U) +#define ADC_GCC_RDY_SHIFT (24U) +/*! RDY - Gain Calibration Value Valid + * 0b0..The GAIN_CAL value is invalid. Run the hardware calibration routine for this value to be set. + * 0b1..The GAIN_CAL value is valid. GAIN_CAL should be used by software to derive GCRa[GCALR]. + */ +#define ADC_GCC_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_RDY_SHIFT)) & ADC_GCC_RDY_MASK) +/*! @} */ + +/* The count of ADC_GCC */ +#define ADC_GCC_COUNT (1U) + +/*! @name GCR - Gain Calculation Result */ +/*! @{ */ + +#define ADC_GCR_GCALR_MASK (0x1FFFFU) +#define ADC_GCR_GCALR_SHIFT (0U) +/*! GCALR - Gain Calculation Result */ +#define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) + +#define ADC_GCR_RDY_MASK (0x1000000U) +#define ADC_GCR_RDY_SHIFT (24U) +/*! RDY - Gain Calculation Ready + * 0b0..The GCALR value is invalid. + * 0b1..The GCALR value is valid. + */ +#define ADC_GCR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_RDY_SHIFT)) & ADC_GCR_RDY_MASK) +/*! @} */ + +/* The count of ADC_GCR */ +#define ADC_GCR_COUNT (1U) + +/*! @name CMDL - Command Low Buffer Register */ +/*! @{ */ + +#define ADC_CMDL_ADCH_MASK (0x1FU) +#define ADC_CMDL_ADCH_SHIFT (0U) +/*! ADCH - Input Channel Select + * 0b00000..Select CH0A. + * 0b00001..Select CH1A. + * 0b00010..Select CH2A. + * 0b00011..Select CH3A. + * 0b00100-0b11101..Select corresponding channel CHnA. + * 0b11110..Select CH30A. + * 0b11111..Select CH31A. + */ +#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) + +#define ADC_CMDL_CTYPE_MASK (0x60U) +#define ADC_CMDL_CTYPE_SHIFT (5U) +/*! CTYPE - Conversion Type + * 0b00..Single-Ended Mode. Only A side channel is converted. + * 0b01-0b11..Reserved. + */ +#define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) + +#define ADC_CMDL_MODE_MASK (0x80U) +#define ADC_CMDL_MODE_SHIFT (7U) +/*! MODE - Select Resolution of Conversions + * 0b0..Standard resolution. Single-ended 12-bit conversion. + * 0b1..High resolution. Single-ended 16-bit conversion. + */ +#define ADC_CMDL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_MODE_SHIFT)) & ADC_CMDL_MODE_MASK) +/*! @} */ + +/* The count of ADC_CMDL */ +#define ADC_CMDL_COUNT (7U) + +/*! @name CMDH - Command High Buffer Register */ +/*! @{ */ + +#define ADC_CMDH_CMPEN_MASK (0x3U) +#define ADC_CMDH_CMPEN_SHIFT (0U) +/*! CMPEN - Compare Function Enable + * 0b00..Compare disabled. + * 0b01..Reserved + * 0b10..Compare enabled. Store on true. + * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. + */ +#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) + +#define ADC_CMDH_WAIT_TRIG_MASK (0x4U) +#define ADC_CMDH_WAIT_TRIG_SHIFT (2U) +/*! WAIT_TRIG - Wait for Trigger Assertion before Execution. + * 0b0..This command will be automatically executed. + * 0b1..The active trigger must be asserted again before executing this command. + */ +#define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) + +#define ADC_CMDH_LWI_MASK (0x80U) +#define ADC_CMDH_LWI_SHIFT (7U) +/*! LWI - Loop with Increment + * 0b0..Auto channel increment disabled + * 0b1..Auto channel increment enabled + */ +#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) + +#define ADC_CMDH_STS_MASK (0x700U) +#define ADC_CMDH_STS_SHIFT (8U) +/*! STS - Sample Time Select + * 0b000..Minimum sample time of 3.5 ADCK cycles. + * 0b001..3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time. + * 0b010..3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time. + * 0b011..3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time. + * 0b100..3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time. + * 0b101..3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time. + * 0b110..3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time. + * 0b111..3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time. + */ +#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) + +#define ADC_CMDH_AVGS_MASK (0xF000U) +#define ADC_CMDH_AVGS_SHIFT (12U) +/*! AVGS - Hardware Average Select + * 0b0000..Single conversion. + * 0b0001..2 conversions averaged. + * 0b0010..4 conversions averaged. + * 0b0011..8 conversions averaged. + * 0b0100..16 conversions averaged. + * 0b0101..32 conversions averaged. + * 0b0110..64 conversions averaged. + * 0b0111..128 conversions averaged. + * 0b1000..256 conversions averaged. + * 0b1001..512 conversions averaged. + * 0b1010..1024 conversions averaged. + */ +#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) + +#define ADC_CMDH_LOOP_MASK (0xF0000U) +#define ADC_CMDH_LOOP_SHIFT (16U) +/*! LOOP - Loop Count Select + * 0b0000..Looping not enabled. Command executes 1 time. + * 0b0001..Loop 1 time. Command executes 2 times. + * 0b0010..Loop 2 times. Command executes 3 times. + * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times. + * 0b1111..Loop 15 times. Command executes 16 times. + */ +#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) + +#define ADC_CMDH_NEXT_MASK (0x7000000U) +#define ADC_CMDH_NEXT_SHIFT (24U) +/*! NEXT - Next Command Select + * 0b000..No next command defined. Terminate conversions at completion of current command. If lower priority + * trigger pending, begin command associated with lower priority trigger. + * 0b001..Select CMD1 command buffer register as next command. + * 0b010-0b110..Select corresponding CMD command buffer register as next command + * 0b111..Select CMD7 command buffer register as next command. + */ +#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK) +/*! @} */ + +/* The count of ADC_CMDH */ +#define ADC_CMDH_COUNT (7U) + +/*! @name CV - Compare Value Register */ +/*! @{ */ + +#define ADC_CV_CVL_MASK (0xFFFFU) +#define ADC_CV_CVL_SHIFT (0U) +/*! CVL - Compare Value Low */ +#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) + +#define ADC_CV_CVH_MASK (0xFFFF0000U) +#define ADC_CV_CVH_SHIFT (16U) +/*! CVH - Compare Value High */ +#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) +/*! @} */ + +/* The count of ADC_CV */ +#define ADC_CV_COUNT (7U) + +/*! @name RESFIFO - Data Result FIFO Register */ +/*! @{ */ + +#define ADC_RESFIFO_D_MASK (0xFFFFU) +#define ADC_RESFIFO_D_SHIFT (0U) +/*! D - Data Result */ +#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) + +#define ADC_RESFIFO_TSRC_MASK (0x30000U) +#define ADC_RESFIFO_TSRC_SHIFT (16U) +/*! TSRC - Trigger Source + * 0b00..Trigger source 0 initiated this conversion. + * 0b01..Trigger source 1 initiated this conversion. + * 0b10..Trigger source 2 initiated this conversion. + * 0b11..Trigger source 3 initiated this conversion. + */ +#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) + +#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) +#define ADC_RESFIFO_LOOPCNT_SHIFT (20U) +/*! LOOPCNT - Loop Count Value + * 0b0000..Result is from initial conversion in command. + * 0b0001..Result is from second conversion in command. + * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command. + * 0b1111..Result is from 16th conversion in command. + */ +#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) + +#define ADC_RESFIFO_CMDSRC_MASK (0x7000000U) +#define ADC_RESFIFO_CMDSRC_SHIFT (24U) +/*! CMDSRC - Command Buffer Source + * 0b000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior + * to an ADC conversion result dataword being stored to a RESFIFO buffer. + * 0b001..CMD1 buffer used as control settings for this conversion. + * 0b010-0b110..Corresponding command buffer used as control settings for this conversion. + * 0b111..CMD7 buffer used as control settings for this conversion. + */ +#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) + +#define ADC_RESFIFO_VALID_MASK (0x80000000U) +#define ADC_RESFIFO_VALID_SHIFT (31U) +/*! VALID - FIFO Entry is Valid + * 0b0..FIFO is empty. Discard any read from RESFIFO. + * 0b1..FIFO record read from RESFIFO is valid. + */ +#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK) +/*! @} */ + +/*! @name CAL_GAR0 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR0_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR0_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR0_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR0_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR0_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR1 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR1_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR1_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR1_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR1_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR1_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR2 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR2_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR2_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR2_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR2_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR2_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR3 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR3_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR3_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR3_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR3_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR3_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR4 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR4_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR4_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR4_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR4_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR4_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR5 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR5_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR5_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR5_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR5_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR5_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR6 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR6_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR6_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR6_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR6_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR6_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR7 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR7_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR7_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR7_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR7_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR7_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR8 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR8_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR8_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR8_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR8_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR8_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR9 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR9_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR9_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR9_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR9_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR9_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR10 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR10_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR10_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR10_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR10_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR10_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR11 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR11_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR11_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR11_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR11_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR11_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR12 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR12_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR12_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR12_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR12_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR12_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR13 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR13_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR13_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR13_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR13_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR13_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR14 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR14_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR14_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR14_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR14_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR14_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR15 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR15_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR15_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR15_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR15_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR15_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR16 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR16_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR16_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR16_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR16_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR16_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR17 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR17_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR17_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR17_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR17_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR17_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR18 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR18_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR18_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR18_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR18_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR18_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR19 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR19_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR19_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR19_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR19_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR19_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR20 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR20_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR20_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR20_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR20_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR20_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR21 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR21_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR21_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR21_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR21_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR21_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR22 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR22_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR22_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR22_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR22_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR22_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR23 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR23_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR23_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR23_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR23_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR23_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR24 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR24_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR24_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR24_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR24_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR24_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR25 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR25_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR25_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR25_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR25_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR25_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR26 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR26_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR26_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR26_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR26_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR26_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR27 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR27_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR27_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR27_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR27_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR27_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR28 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR28_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR28_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR28_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR28_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR28_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR29 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR29_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR29_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR29_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR29_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR29_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR30 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR30_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR30_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR30_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR30_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR30_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR31 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR31_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR31_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR31_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR31_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR31_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR32 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR32_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR32_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR32_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR32_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR32_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CAL_GAR33 - Calibration General A-Side Registers */ +/*! @{ */ + +#define ADC_CAL_GAR33_CAL_GAR_VAL_MASK (0xFFFFU) +#define ADC_CAL_GAR33_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element */ +#define ADC_CAL_GAR33_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR33_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR33_CAL_GAR_VAL_MASK) +/*! @} */ + +/*! @name CFG2 - Configuration 2 Register */ +/*! @{ */ + +#define ADC_CFG2_JLEFT_MASK (0x100U) +#define ADC_CFG2_JLEFT_SHIFT (8U) +/*! JLEFT - Justified Left Enable register */ +#define ADC_CFG2_JLEFT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_JLEFT_SHIFT)) & ADC_CFG2_JLEFT_MASK) + +#define ADC_CFG2_HS_MASK (0x200U) +#define ADC_CFG2_HS_SHIFT (9U) +/*! HS - High Speed Enable register + * 0b0..High speed conversion mode disabled + * 0b1..High speed conversion mode enabled + */ +#define ADC_CFG2_HS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_HS_SHIFT)) & ADC_CFG2_HS_MASK) + +#define ADC_CFG2_HSEXTRA_MASK (0x400U) +#define ADC_CFG2_HSEXTRA_SHIFT (10U) +/*! HSEXTRA - High Speed Extra register + * 0b0..No extra cycle added + * 0b1..Extra cycle added + */ +#define ADC_CFG2_HSEXTRA(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_HSEXTRA_SHIFT)) & ADC_CFG2_HSEXTRA_MASK) + +#define ADC_CFG2_TUNE_MASK (0x3000U) +#define ADC_CFG2_TUNE_SHIFT (12U) +/*! TUNE - Tune Mode register */ +#define ADC_CFG2_TUNE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_TUNE_SHIFT)) & ADC_CFG2_TUNE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x400AF000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Peripheral ADC1 base address */ +#define ADC1_BASE (0x400B0000u) +/** Peripheral ADC1 base pointer */ +#define ADC1 ((ADC_Type *)ADC1_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0, ADC1 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn } +/* Backward compatibility */ +#define ADC_CTRL_RSTFIFO_MASK ADC_CTRL_RSTFIFO0_MASK +#define ADC_CTRL_RSTFIFO_SHIFT ADC_CTRL_RSTFIFO0_SHIFT +#define ADC_CTRL_RSTFIFO(x) ADC_CTRL_RSTFIFO0(x) +#define ADC_STAT_RDY_MASK ADC_STAT_RDY0_MASK +#define ADC_STAT_RDY_SHIFT ADC_STAT_RDY0_SHIFT +#define ADC_STAT_RDY(x) ADC_STAT_RDY0(x) +#define ADC_STAT_FOF_MASK ADC_STAT_FOF0_MASK +#define ADC_STAT_FOF_SHIFT ADC_STAT_FOF0_SHIFT +#define ADC_STAT_FOF(x) ADC_STAT_FOF0(x) +#define ADC_IE_FWMIE_MASK ADC_IE_FWMIE0_MASK +#define ADC_IE_FWMIE_SHIFT ADC_IE_FWMIE0_SHIFT +#define ADC_IE_FWMIE(x) ADC_IE_FWMIE0(x) +#define ADC_IE_FOFIE_MASK ADC_IE_FOFIE0_MASK +#define ADC_IE_FOFIE_SHIFT ADC_IE_FOFIE0_SHIFT +#define ADC_IE_FOFIE(x) ADC_IE_FOFIE0(x) +#define ADC_DE_FWMDE_MASK ADC_DE_FWMDE0_MASK +#define ADC_DE_FWMDE_SHIFT ADC_DE_FWMDE0_SHIFT +#define ADC_DE_FWMDE(x) ADC_DE_FWMDE0(x) + + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- AOI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer + * @{ + */ + +/** AOI - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x4 */ + __IO uint16_t BFCRT01; /**< Boolean Function Term 0 and 1 Configuration for EVENT0..Boolean Function Term 0 and 1 Configuration for EVENT3, array offset: 0x0, array step: 0x4 */ + __IO uint16_t BFCRT23; /**< Boolean Function Term 2 and 3 Configuration for EVENT0..Boolean Function Term 2 and 3 Configuration for EVENT3, array offset: 0x2, array step: 0x4 */ + } BFCRT[4]; +} AOI_Type; + +/* ---------------------------------------------------------------------------- + -- AOI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AOI_Register_Masks AOI Register Masks + * @{ + */ + +/*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration for EVENT0..Boolean Function Term 0 and 1 Configuration for EVENT3 */ +/*! @{ */ + +#define AOI_BFCRT01_PT1_DC_MASK (0x3U) +#define AOI_BFCRT01_PT1_DC_SHIFT (0U) +/*! PT1_DC - Product Term 1, Input D Configuration + * 0b00..Force input D to become 0 + * 0b01..Pass input D + * 0b10..Complement input D + * 0b11..Force input D to become 1 + */ +#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK) + +#define AOI_BFCRT01_PT1_CC_MASK (0xCU) +#define AOI_BFCRT01_PT1_CC_SHIFT (2U) +/*! PT1_CC - Product Term 1, Input C Configuration + * 0b00..Force input C to become 0 + * 0b01..Pass input C + * 0b10..Complement input C + * 0b11..Force input C to become 1 + */ +#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK) + +#define AOI_BFCRT01_PT1_BC_MASK (0x30U) +#define AOI_BFCRT01_PT1_BC_SHIFT (4U) +/*! PT1_BC - Product Term 1, Input B Configuration + * 0b00..Force input B to become 0 + * 0b01..Pass input B + * 0b10..Complement input B + * 0b11..Force input B to become 1 + */ +#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK) + +#define AOI_BFCRT01_PT1_AC_MASK (0xC0U) +#define AOI_BFCRT01_PT1_AC_SHIFT (6U) +/*! PT1_AC - Product Term 1, Input A Configuration + * 0b00..Force input A to become 0 + * 0b01..Pass input A + * 0b10..Complement input A + * 0b11..Force input A to become 1 + */ +#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK) + +#define AOI_BFCRT01_PT0_DC_MASK (0x300U) +#define AOI_BFCRT01_PT0_DC_SHIFT (8U) +/*! PT0_DC - Product Term 0, Input D Configuration + * 0b00..Force input D to become 0 + * 0b01..Pass input D + * 0b10..Complement input D + * 0b11..Force input D to become 1 + */ +#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK) + +#define AOI_BFCRT01_PT0_CC_MASK (0xC00U) +#define AOI_BFCRT01_PT0_CC_SHIFT (10U) +/*! PT0_CC - Product Term 0, Input C Configuration + * 0b00..Force input C to become 0 + * 0b01..Pass input C + * 0b10..Complement input C + * 0b11..Force input C to become 1 + */ +#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK) + +#define AOI_BFCRT01_PT0_BC_MASK (0x3000U) +#define AOI_BFCRT01_PT0_BC_SHIFT (12U) +/*! PT0_BC - Product Term 0, Input B Configuration + * 0b00..Force input B to become 0 + * 0b01..Pass input B + * 0b10..Complement input B + * 0b11..Force input B to become 1 + */ +#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK) + +#define AOI_BFCRT01_PT0_AC_MASK (0xC000U) +#define AOI_BFCRT01_PT0_AC_SHIFT (14U) +/*! PT0_AC - Product Term 0, Input A Configuration + * 0b00..Force input A to become 0 + * 0b01..Pass input A + * 0b10..Complement input A + * 0b11..Force input A to become 1 + */ +#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK) +/*! @} */ + +/* The count of AOI_BFCRT01 */ +#define AOI_BFCRT01_COUNT (4U) + +/*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration for EVENT0..Boolean Function Term 2 and 3 Configuration for EVENT3 */ +/*! @{ */ + +#define AOI_BFCRT23_PT3_DC_MASK (0x3U) +#define AOI_BFCRT23_PT3_DC_SHIFT (0U) +/*! PT3_DC - Product Term 3, Input D Configuration + * 0b00..Force input D to become 0 + * 0b01..Pass input D + * 0b10..Complement input D + * 0b11..Force input D to become 1 + */ +#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK) + +#define AOI_BFCRT23_PT3_CC_MASK (0xCU) +#define AOI_BFCRT23_PT3_CC_SHIFT (2U) +/*! PT3_CC - Product Term 3, Input C Configuration + * 0b00..Force input C to become 0 + * 0b01..Pass input C + * 0b10..Complement input C + * 0b11..Force input C to become 1 + */ +#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK) + +#define AOI_BFCRT23_PT3_BC_MASK (0x30U) +#define AOI_BFCRT23_PT3_BC_SHIFT (4U) +/*! PT3_BC - Product Term 3, Input B Configuration + * 0b00..Force input B to become 0 + * 0b01..Pass input B + * 0b10..Complement input B + * 0b11..Force input B to become 1 + */ +#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK) + +#define AOI_BFCRT23_PT3_AC_MASK (0xC0U) +#define AOI_BFCRT23_PT3_AC_SHIFT (6U) +/*! PT3_AC - Product Term 3, Input A Configuration + * 0b00..Force input A to become 0 + * 0b01..Pass input A + * 0b10..Complement input A + * 0b11..Force input to become 1 + */ +#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK) + +#define AOI_BFCRT23_PT2_DC_MASK (0x300U) +#define AOI_BFCRT23_PT2_DC_SHIFT (8U) +/*! PT2_DC - Product Term 2, Input D Configuration + * 0b00..Force input D to become 0 + * 0b01..Pass input D + * 0b10..Complement input D + * 0b11..Force input D to become 1 + */ +#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK) + +#define AOI_BFCRT23_PT2_CC_MASK (0xC00U) +#define AOI_BFCRT23_PT2_CC_SHIFT (10U) +/*! PT2_CC - Product Term 2, Input C Configuration + * 0b00..Force input C to become 0 + * 0b01..Pass input C + * 0b10..Complement input C + * 0b11..Force input C to become 1 + */ +#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK) + +#define AOI_BFCRT23_PT2_BC_MASK (0x3000U) +#define AOI_BFCRT23_PT2_BC_SHIFT (12U) +/*! PT2_BC - Product Term 2, Input B Configuration + * 0b00..Force input B to become 0 + * 0b01..Pass input B + * 0b10..Complement input B + * 0b11..Force input B to become 1 + */ +#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK) + +#define AOI_BFCRT23_PT2_AC_MASK (0xC000U) +#define AOI_BFCRT23_PT2_AC_SHIFT (14U) +/*! PT2_AC - Product Term 2, Input A Configuration + * 0b00..Force input A to become 0 + * 0b01..Pass input A + * 0b10..Complement input A + * 0b11..Force input A to become 1 + */ +#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK) +/*! @} */ + +/* The count of AOI_BFCRT23 */ +#define AOI_BFCRT23_COUNT (4U) + + +/*! + * @} + */ /* end of group AOI_Register_Masks */ + + +/* AOI - Peripheral instance base addresses */ +/** Peripheral AOI0 base address */ +#define AOI0_BASE (0x40089000u) +/** Peripheral AOI0 base pointer */ +#define AOI0 ((AOI_Type *)AOI0_BASE) +/** Peripheral AOI1 base address */ +#define AOI1_BASE (0x40097000u) +/** Peripheral AOI1 base pointer */ +#define AOI1 ((AOI_Type *)AOI1_BASE) +/** Array initializer of AOI peripheral base addresses */ +#define AOI_BASE_ADDRS { AOI0_BASE, AOI1_BASE } +/** Array initializer of AOI peripheral base pointers */ +#define AOI_BASE_PTRS { AOI0, AOI1 } + +/*! + * @} + */ /* end of group AOI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CAN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer + * @{ + */ + +/** CAN - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCR; /**< Module Configuration, offset: 0x0 */ + __IO uint32_t CTRL1; /**< Control 1, offset: 0x4 */ + __IO uint32_t TIMER; /**< Free-Running Timer, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t RXMGMASK; /**< RX Message Buffers Global Mask, offset: 0x10 */ + __IO uint32_t RX14MASK; /**< Receive 14 Mask, offset: 0x14 */ + __IO uint32_t RX15MASK; /**< Receive 15 Mask, offset: 0x18 */ + __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */ + __IO uint32_t ESR1; /**< Error and Status 1, offset: 0x20 */ + uint8_t RESERVED_1[4]; + __IO uint32_t IMASK1; /**< Interrupt Masks 1, offset: 0x28 */ + uint8_t RESERVED_2[4]; + __IO uint32_t IFLAG1; /**< Interrupt Flags 1, offset: 0x30 */ + __IO uint32_t CTRL2; /**< Control 2, offset: 0x34 */ + __I uint32_t ESR2; /**< Error and Status 2, offset: 0x38 */ + uint8_t RESERVED_3[8]; + __I uint32_t CRCR; /**< Cyclic Redundancy Check, offset: 0x44 */ + __IO uint32_t RXFGMASK; /**< Legacy RX FIFO Global Mask, offset: 0x48 */ + __I uint32_t RXFIR; /**< Legacy RX FIFO Information, offset: 0x4C */ + __IO uint32_t CBT; /**< CAN Bit Timing, offset: 0x50 */ + uint8_t RESERVED_4[44]; + union { /* offset: 0x80 */ + struct { /* offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 31 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 31 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD[2]; /**< Message Buffer 0 WORD_8B Register..Message Buffer 31 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4 */ + } MB_8B[32]; + struct { /* offset: 0x80, array step: 0x18 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x80, array step: 0x18 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x84, array step: 0x18 */ + __IO uint32_t WORD[4]; /**< Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4 */ + } MB_16B[21]; + struct { /* offset: 0x80, array step: 0x28 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x80, array step: 0x28 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x84, array step: 0x28 */ + __IO uint32_t WORD[8]; /**< Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4 */ + } MB_32B[12]; + struct { /* offset: 0x80, array step: 0x48 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x80, array step: 0x48 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x84, array step: 0x48 */ + __IO uint32_t WORD[16]; /**< Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4 */ + } MB_64B[7]; + struct { /* offset: 0x80, array step: 0x10 */ + __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 31 CS Register, array offset: 0x80, array step: 0x10 */ + __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 31 ID Register, array offset: 0x84, array step: 0x10 */ + __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 31 WORD0 Register, array offset: 0x88, array step: 0x10 */ + __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 31 WORD1 Register, array offset: 0x8C, array step: 0x10 */ + } MB[32]; + }; + uint8_t RESERVED_5[1536]; + __IO uint32_t RXIMR[32]; /**< Receive Individual Mask, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_6[512]; + __IO uint32_t CTRL1_PN; /**< Pretended Networking Control 1, offset: 0xB00 */ + __IO uint32_t CTRL2_PN; /**< Pretended Networking Control 2, offset: 0xB04 */ + __IO uint32_t WU_MTC; /**< Pretended Networking Wake-Up Match, offset: 0xB08 */ + __IO uint32_t FLT_ID1; /**< Pretended Networking ID Filter 1, offset: 0xB0C */ + __IO uint32_t FLT_DLC; /**< Pretended Networking Data Length Code (DLC) Filter, offset: 0xB10 */ + __IO uint32_t PL1_LO; /**< Pretended Networking Payload Low Filter 1, offset: 0xB14 */ + __IO uint32_t PL1_HI; /**< Pretended Networking Payload High Filter 1, offset: 0xB18 */ + __IO uint32_t FLT_ID2_IDMASK; /**< Pretended Networking ID Filter 2 or ID Mask, offset: 0xB1C */ + __IO uint32_t PL2_PLMASK_LO; /**< Pretended Networking Payload Low Filter 2 and Payload Low Mask, offset: 0xB20 */ + __IO uint32_t PL2_PLMASK_HI; /**< Pretended Networking Payload High Filter 2 and Payload High Mask, offset: 0xB24 */ + uint8_t RESERVED_7[24]; + struct { /* offset: 0xB40, array step: 0x10 */ + __I uint32_t CS; /**< Wake-Up Message Buffer, array offset: 0xB40, array step: 0x10 */ + __I uint32_t ID; /**< Wake-Up Message Buffer for ID, array offset: 0xB44, array step: 0x10 */ + __I uint32_t D03; /**< Wake-Up Message Buffer for Data 0-3, array offset: 0xB48, array step: 0x10 */ + __I uint32_t D47; /**< Wake-Up Message Buffer Register Data 4-7, array offset: 0xB4C, array step: 0x10 */ + } WMB[4]; + uint8_t RESERVED_8[112]; + __IO uint32_t EPRS; /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */ + __IO uint32_t ENCBT; /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */ + __IO uint32_t EDCBT; /**< Enhanced Data Phase CAN Bit Timing, offset: 0xBF8 */ + __IO uint32_t ETDC; /**< Enhanced Transceiver Delay Compensation, offset: 0xBFC */ + __IO uint32_t FDCTRL; /**< CAN FD Control, offset: 0xC00 */ + __IO uint32_t FDCBT; /**< CAN FD Bit Timing, offset: 0xC04 */ + __I uint32_t FDCRC; /**< CAN FD CRC, offset: 0xC08 */ + __IO uint32_t ERFCR; /**< Enhanced RX FIFO Control, offset: 0xC0C */ + __IO uint32_t ERFIER; /**< Enhanced RX FIFO Interrupt Enable, offset: 0xC10 */ + __IO uint32_t ERFSR; /**< Enhanced RX FIFO Status, offset: 0xC14 */ + uint8_t RESERVED_9[9192]; + __IO uint32_t ERFFEL[32]; /**< Enhanced RX FIFO Filter Element, array offset: 0x3000, array step: 0x4 */ +} CAN_Type; + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration */ +/*! @{ */ + +#define CAN_MCR_MAXMB_MASK (0x7FU) +#define CAN_MCR_MAXMB_SHIFT (0U) +/*! MAXMB - Number of the Last Message Buffer */ +#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) + +#define CAN_MCR_IDAM_MASK (0x300U) +#define CAN_MCR_IDAM_SHIFT (8U) +/*! IDAM - ID Acceptance Mode + * 0b00..Format A: One full ID (standard and extended) per ID filter table element. + * 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element. + * 0b10..Format C: Four partial 8-bit standard IDs per ID filter table element. + * 0b11..Format D: All frames rejected. + */ +#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) + +#define CAN_MCR_FDEN_MASK (0x800U) +#define CAN_MCR_FDEN_SHIFT (11U) +/*! FDEN - CAN FD Operation Enable + * 0b1..Enable + * 0b0..Disable + */ +#define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK) + +#define CAN_MCR_AEN_MASK (0x1000U) +#define CAN_MCR_AEN_SHIFT (12U) +/*! AEN - Abort Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) + +#define CAN_MCR_LPRIOEN_MASK (0x2000U) +#define CAN_MCR_LPRIOEN_SHIFT (13U) +/*! LPRIOEN - Local Priority Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) + +#define CAN_MCR_PNET_EN_MASK (0x4000U) +#define CAN_MCR_PNET_EN_SHIFT (14U) +/*! PNET_EN - Pretended Networking Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_PNET_EN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_PNET_EN_SHIFT)) & CAN_MCR_PNET_EN_MASK) + +#define CAN_MCR_DMA_MASK (0x8000U) +#define CAN_MCR_DMA_SHIFT (15U) +/*! DMA - DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK) + +#define CAN_MCR_IRMQ_MASK (0x10000U) +#define CAN_MCR_IRMQ_SHIFT (16U) +/*! IRMQ - Individual RX Masking and Queue Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) + +#define CAN_MCR_SRXDIS_MASK (0x20000U) +#define CAN_MCR_SRXDIS_SHIFT (17U) +/*! SRXDIS - Self-Reception Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) + +#define CAN_MCR_DOZE_MASK (0x40000U) +#define CAN_MCR_DOZE_SHIFT (18U) +/*! DOZE - Doze Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK) + +#define CAN_MCR_WAKSRC_MASK (0x80000U) +#define CAN_MCR_WAKSRC_SHIFT (19U) +/*! WAKSRC - Wake-Up Source + * 0b0..No filter applied + * 0b1..Filter applied + */ +#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) + +#define CAN_MCR_LPMACK_MASK (0x100000U) +#define CAN_MCR_LPMACK_SHIFT (20U) +/*! LPMACK - Low-Power Mode Acknowledge + * 0b0..Not in a low-power mode + * 0b1..In a low-power mode + */ +#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) + +#define CAN_MCR_WRNEN_MASK (0x200000U) +#define CAN_MCR_WRNEN_SHIFT (21U) +/*! WRNEN - Warning Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) + +#define CAN_MCR_SLFWAK_MASK (0x400000U) +#define CAN_MCR_SLFWAK_SHIFT (22U) +/*! SLFWAK - Self Wake-up + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) + +#define CAN_MCR_FRZACK_MASK (0x1000000U) +#define CAN_MCR_FRZACK_SHIFT (24U) +/*! FRZACK - Freeze Mode Acknowledge + * 0b0..Not in Freeze mode, prescaler running. + * 0b1..In Freeze mode, prescaler stopped. + */ +#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) + +#define CAN_MCR_SOFTRST_MASK (0x2000000U) +#define CAN_MCR_SOFTRST_SHIFT (25U) +/*! SOFTRST - Soft Reset + * 0b0..No reset + * 0b1..Soft reset affects reset registers + */ +#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) + +#define CAN_MCR_WAKMSK_MASK (0x4000000U) +#define CAN_MCR_WAKMSK_SHIFT (26U) +/*! WAKMSK - Wake-up Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) + +#define CAN_MCR_NOTRDY_MASK (0x8000000U) +#define CAN_MCR_NOTRDY_SHIFT (27U) +/*! NOTRDY - FlexCAN Not Ready + * 0b0..FlexCAN is in Normal mode, Listen-Only mode, or Loopback mode. + * 0b1..FlexCAN is in Disable mode, Doze mode, Stop mode, or Freeze mode. + */ +#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) + +#define CAN_MCR_HALT_MASK (0x10000000U) +#define CAN_MCR_HALT_SHIFT (28U) +/*! HALT - Halt FlexCAN + * 0b0..No request + * 0b1..Enter Freeze mode, if MCR[FRZ] = 1. + */ +#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) + +#define CAN_MCR_RFEN_MASK (0x20000000U) +#define CAN_MCR_RFEN_SHIFT (29U) +/*! RFEN - Legacy RX FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) + +#define CAN_MCR_FRZ_MASK (0x40000000U) +#define CAN_MCR_FRZ_SHIFT (30U) +/*! FRZ - Freeze Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) + +#define CAN_MCR_MDIS_MASK (0x80000000U) +#define CAN_MCR_MDIS_SHIFT (31U) +/*! MDIS - Module Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK) +/*! @} */ + +/*! @name CTRL1 - Control 1 */ +/*! @{ */ + +#define CAN_CTRL1_PROPSEG_MASK (0x7U) +#define CAN_CTRL1_PROPSEG_SHIFT (0U) +/*! PROPSEG - Propagation Segment */ +#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) + +#define CAN_CTRL1_LOM_MASK (0x8U) +#define CAN_CTRL1_LOM_SHIFT (3U) +/*! LOM - Listen-Only Mode + * 0b0..Listen-Only mode is deactivated. + * 0b1..FlexCAN module operates in Listen-Only mode. + */ +#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) + +#define CAN_CTRL1_LBUF_MASK (0x10U) +#define CAN_CTRL1_LBUF_SHIFT (4U) +/*! LBUF - Lowest Buffer Transmitted First + * 0b0..Buffer with highest priority is transmitted first. + * 0b1..Lowest number buffer is transmitted first. + */ +#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) + +#define CAN_CTRL1_TSYN_MASK (0x20U) +#define CAN_CTRL1_TSYN_SHIFT (5U) +/*! TSYN - Timer Sync + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) + +#define CAN_CTRL1_BOFFREC_MASK (0x40U) +#define CAN_CTRL1_BOFFREC_SHIFT (6U) +/*! BOFFREC - Bus Off Recovery + * 0b0..Enabled + * 0b1..Disabled + */ +#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) + +#define CAN_CTRL1_SMP_MASK (0x80U) +#define CAN_CTRL1_SMP_SHIFT (7U) +/*! SMP - CAN Bit Sampling + * 0b0..One sample is used to determine the bit value. + * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two + * preceding samples. A majority rule is used. + */ +#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) + +#define CAN_CTRL1_RWRNMSK_MASK (0x400U) +#define CAN_CTRL1_RWRNMSK_SHIFT (10U) +/*! RWRNMSK - RX Warning Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) + +#define CAN_CTRL1_TWRNMSK_MASK (0x800U) +#define CAN_CTRL1_TWRNMSK_SHIFT (11U) +/*! TWRNMSK - TX Warning Interrupt Mask + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) + +#define CAN_CTRL1_LPB_MASK (0x1000U) +#define CAN_CTRL1_LPB_SHIFT (12U) +/*! LPB - Loopback Mode + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) + +#define CAN_CTRL1_ERRMSK_MASK (0x4000U) +#define CAN_CTRL1_ERRMSK_SHIFT (14U) +/*! ERRMSK - Error Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) + +#define CAN_CTRL1_BOFFMSK_MASK (0x8000U) +#define CAN_CTRL1_BOFFMSK_SHIFT (15U) +/*! BOFFMSK - Bus Off Interrupt Mask + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) + +#define CAN_CTRL1_PSEG2_MASK (0x70000U) +#define CAN_CTRL1_PSEG2_SHIFT (16U) +/*! PSEG2 - Phase Segment 2 */ +#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) + +#define CAN_CTRL1_PSEG1_MASK (0x380000U) +#define CAN_CTRL1_PSEG1_SHIFT (19U) +/*! PSEG1 - Phase Segment 1 */ +#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) + +#define CAN_CTRL1_RJW_MASK (0xC00000U) +#define CAN_CTRL1_RJW_SHIFT (22U) +/*! RJW - Resync Jump Width */ +#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) + +#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) +#define CAN_CTRL1_PRESDIV_SHIFT (24U) +/*! PRESDIV - Prescaler Division Factor */ +#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) +/*! @} */ + +/*! @name TIMER - Free-Running Timer */ +/*! @{ */ + +#define CAN_TIMER_TIMER_MASK (0xFFFFU) +#define CAN_TIMER_TIMER_SHIFT (0U) +/*! TIMER - Timer Value */ +#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK) +/*! @} */ + +/*! @name RXMGMASK - RX Message Buffers Global Mask */ +/*! @{ */ + +#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) +#define CAN_RXMGMASK_MG_SHIFT (0U) +/*! MG - Global Mask for RX Message Buffers */ +#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK) +/*! @} */ + +/*! @name RX14MASK - Receive 14 Mask */ +/*! @{ */ + +#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) +#define CAN_RX14MASK_RX14M_SHIFT (0U) +/*! RX14M - RX Buffer 14 Mask Bits */ +#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK) +/*! @} */ + +/*! @name RX15MASK - Receive 15 Mask */ +/*! @{ */ + +#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) +#define CAN_RX15MASK_RX15M_SHIFT (0U) +/*! RX15M - RX Buffer 15 Mask Bits */ +#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK) +/*! @} */ + +/*! @name ECR - Error Counter */ +/*! @{ */ + +#define CAN_ECR_TXERRCNT_MASK (0xFFU) +#define CAN_ECR_TXERRCNT_SHIFT (0U) +/*! TXERRCNT - Transmit Error Counter */ +#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK) + +#define CAN_ECR_RXERRCNT_MASK (0xFF00U) +#define CAN_ECR_RXERRCNT_SHIFT (8U) +/*! RXERRCNT - Receive Error Counter */ +#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK) + +#define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U) +#define CAN_ECR_TXERRCNT_FAST_SHIFT (16U) +/*! TXERRCNT_FAST - Transmit Error Counter for Fast Bits */ +#define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK) + +#define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U) +#define CAN_ECR_RXERRCNT_FAST_SHIFT (24U) +/*! RXERRCNT_FAST - Receive Error Counter for Fast Bits */ +#define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK) +/*! @} */ + +/*! @name ESR1 - Error and Status 1 */ +/*! @{ */ + +#define CAN_ESR1_WAKINT_MASK (0x1U) +#define CAN_ESR1_WAKINT_SHIFT (0U) +/*! WAKINT - Wake-up Interrupt Flag + * 0b0..No such occurrence. + * 0b1..Indicates that a recessive-to-dominant transition was received on the CAN bus. + */ +#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) + +#define CAN_ESR1_ERRINT_MASK (0x2U) +#define CAN_ESR1_ERRINT_SHIFT (1U) +/*! ERRINT - Error Interrupt Flag + * 0b0..No such occurrence. + * 0b1..Indicates setting of any error flag in the Error and Status register. + */ +#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) + +#define CAN_ESR1_BOFFINT_MASK (0x4U) +#define CAN_ESR1_BOFFINT_SHIFT (2U) +/*! BOFFINT - Bus Off Interrupt Flag + * 0b0..No such occurrence. + * 0b1..FlexCAN module entered Bus Off state. + */ +#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) + +#define CAN_ESR1_RX_MASK (0x8U) +#define CAN_ESR1_RX_SHIFT (3U) +/*! RX - FlexCAN in Reception Flag + * 0b0..Not receiving + * 0b1..Receiving + */ +#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) + +#define CAN_ESR1_FLTCONF_MASK (0x30U) +#define CAN_ESR1_FLTCONF_SHIFT (4U) +/*! FLTCONF - Fault Confinement State + * 0b00..Error Active + * 0b01..Error Passive + * 0b1x..Bus Off + */ +#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) + +#define CAN_ESR1_TX_MASK (0x40U) +#define CAN_ESR1_TX_SHIFT (6U) +/*! TX - FlexCAN In Transmission + * 0b0..Not transmitting + * 0b1..Transmitting + */ +#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) + +#define CAN_ESR1_IDLE_MASK (0x80U) +#define CAN_ESR1_IDLE_SHIFT (7U) +/*! IDLE - Idle + * 0b0..Not IDLE + * 0b1..IDLE + */ +#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) + +#define CAN_ESR1_RXWRN_MASK (0x100U) +#define CAN_ESR1_RXWRN_SHIFT (8U) +/*! RXWRN - RX Error Warning Flag + * 0b0..No such occurrence. + * 0b1..RXERRCNT is greater than or equal to 96. + */ +#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) + +#define CAN_ESR1_TXWRN_MASK (0x200U) +#define CAN_ESR1_TXWRN_SHIFT (9U) +/*! TXWRN - TX Error Warning Flag + * 0b0..No such occurrence. + * 0b1..TXERRCNT is 96 or greater. + */ +#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) + +#define CAN_ESR1_STFERR_MASK (0x400U) +#define CAN_ESR1_STFERR_SHIFT (10U) +/*! STFERR - Stuffing Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) + +#define CAN_ESR1_FRMERR_MASK (0x800U) +#define CAN_ESR1_FRMERR_SHIFT (11U) +/*! FRMERR - Form Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) + +#define CAN_ESR1_CRCERR_MASK (0x1000U) +#define CAN_ESR1_CRCERR_SHIFT (12U) +/*! CRCERR - Cyclic Redundancy Check Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) + +#define CAN_ESR1_ACKERR_MASK (0x2000U) +#define CAN_ESR1_ACKERR_SHIFT (13U) +/*! ACKERR - Acknowledge Error Flag + * 0b0..No error + * 0b1..Error occurred since last read of this register. + */ +#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) + +#define CAN_ESR1_BIT0ERR_MASK (0x4000U) +#define CAN_ESR1_BIT0ERR_SHIFT (14U) +/*! BIT0ERR - Bit0 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit sent as dominant is received as recessive. + */ +#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) + +#define CAN_ESR1_BIT1ERR_MASK (0x8000U) +#define CAN_ESR1_BIT1ERR_SHIFT (15U) +/*! BIT1ERR - Bit1 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit sent as recessive is received as dominant. + */ +#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) + +#define CAN_ESR1_RWRNINT_MASK (0x10000U) +#define CAN_ESR1_RWRNINT_SHIFT (16U) +/*! RWRNINT - RX Warning Interrupt Flag + * 0b0..No such occurrence + * 0b1..RX error counter changed from less than 96 to greater than or equal to 96. + */ +#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) + +#define CAN_ESR1_TWRNINT_MASK (0x20000U) +#define CAN_ESR1_TWRNINT_SHIFT (17U) +/*! TWRNINT - TX Warning Interrupt Flag + * 0b0..No such occurrence + * 0b1..TX error counter changed from less than 96 to greater than or equal to 96. + */ +#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) + +#define CAN_ESR1_SYNCH_MASK (0x40000U) +#define CAN_ESR1_SYNCH_SHIFT (18U) +/*! SYNCH - CAN Synchronization Status Flag + * 0b0..Not synchronized + * 0b1..Synchronized + */ +#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) + +#define CAN_ESR1_BOFFDONEINT_MASK (0x80000U) +#define CAN_ESR1_BOFFDONEINT_SHIFT (19U) +/*! BOFFDONEINT - Bus Off Done Interrupt Flag + * 0b0..No such occurrence + * 0b1..FlexCAN module has completed Bus Off process. + */ +#define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK) + +#define CAN_ESR1_ERRINT_FAST_MASK (0x100000U) +#define CAN_ESR1_ERRINT_FAST_SHIFT (20U) +/*! ERRINT_FAST - Fast Error Interrupt Flag + * 0b0..No such occurrence. + * 0b1..Error flag set in the data phase of CAN FD frames that have BRS = 1. + */ +#define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK) + +#define CAN_ESR1_ERROVR_MASK (0x200000U) +#define CAN_ESR1_ERROVR_SHIFT (21U) +/*! ERROVR - Error Overrun Flag + * 0b0..No overrun + * 0b1..Overrun + */ +#define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK) + +#define CAN_ESR1_STFERR_FAST_MASK (0x4000000U) +#define CAN_ESR1_STFERR_FAST_SHIFT (26U) +/*! STFERR_FAST - Fast Stuffing Error Flag + * 0b0..No such occurrence. + * 0b1..A stuffing error occurred since last read of this register. + */ +#define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK) + +#define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U) +#define CAN_ESR1_FRMERR_FAST_SHIFT (27U) +/*! FRMERR_FAST - Fast Form Error Flag + * 0b0..No such occurrence. + * 0b1..A form error occurred since last read of this register. + */ +#define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK) + +#define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U) +#define CAN_ESR1_CRCERR_FAST_SHIFT (28U) +/*! CRCERR_FAST - Fast Cyclic Redundancy Check Error Flag + * 0b0..No such occurrence. + * 0b1..A CRC error occurred since last read of this register. + */ +#define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK) + +#define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U) +#define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U) +/*! BIT0ERR_FAST - Fast Bit0 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit transmitted as dominant is received as recessive. + */ +#define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK) + +#define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U) +#define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U) +/*! BIT1ERR_FAST - Fast Bit1 Error Flag + * 0b0..No such occurrence. + * 0b1..At least one bit transmitted as recessive is received as dominant. + */ +#define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK) +/*! @} */ + +/*! @name IMASK1 - Interrupt Masks 1 */ +/*! @{ */ + +#define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU) +#define CAN_IMASK1_BUF31TO0M_SHIFT (0U) +/*! BUF31TO0M - Buffer MBi Mask */ +#define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK) +/*! @} */ + +/*! @name IFLAG1 - Interrupt Flags 1 */ +/*! @{ */ + +#define CAN_IFLAG1_BUF0I_MASK (0x1U) +#define CAN_IFLAG1_BUF0I_SHIFT (0U) +/*! BUF0I - Buffer MB0 Interrupt or Clear Legacy FIFO bit + * 0b0..MB0 has no occurrence of successfully completed transmission or reception. + * 0b1..MB0 has successfully completed transmission or reception. + */ +#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) + +#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) +#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) +/*! BUF4TO1I - Buffer MBi Interrupt or Reserved */ +#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) + +#define CAN_IFLAG1_BUF5I_MASK (0x20U) +#define CAN_IFLAG1_BUF5I_SHIFT (5U) +/*! BUF5I - Buffer MB5 Interrupt or Frames available in Legacy RX FIFO + * 0b0..No occurrence of completed transmission or reception, or no frames available + * 0b1..MB5 completed transmission or reception, or frames available + */ +#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) + +#define CAN_IFLAG1_BUF6I_MASK (0x40U) +#define CAN_IFLAG1_BUF6I_SHIFT (6U) +/*! BUF6I - Buffer MB6 Interrupt or Legacy RX FIFO Warning + * 0b0..No occurrence of MB6 completing transmission or reception, or FIFO not almost full. + * 0b1..MB6 completed transmission or reception, or FIFO almost full. + */ +#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) + +#define CAN_IFLAG1_BUF7I_MASK (0x80U) +#define CAN_IFLAG1_BUF7I_SHIFT (7U) +/*! BUF7I - Buffer MB7 Interrupt or Legacy RX FIFO Overflow + * 0b0..No occurrence of MB7 completing transmission or reception, or no FIFO overflow. + * 0b1..MB7 completed transmission or reception, or FIFO overflow. + */ +#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) + +#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) +#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) +/*! BUF31TO8I - Buffer MBi Interrupt */ +#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 */ +/*! @{ */ + +#define CAN_CTRL2_PES_MASK (0x1U) +#define CAN_CTRL2_PES_SHIFT (0U) +/*! PES - Payload Byte and Bit Order Selection + * 0b0..Big-endian + * 0b1..Little-endian + */ +#define CAN_CTRL2_PES(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PES_SHIFT)) & CAN_CTRL2_PES_MASK) + +#define CAN_CTRL2_ASD_MASK (0x2U) +#define CAN_CTRL2_ASD_SHIFT (1U) +/*! ASD - ACK Suppression Disable + * 0b0..Enabled + * 0b1..Disabled + */ +#define CAN_CTRL2_ASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ASD_SHIFT)) & CAN_CTRL2_ASD_MASK) + +#define CAN_CTRL2_EDFLTDIS_MASK (0x800U) +#define CAN_CTRL2_EDFLTDIS_SHIFT (11U) +/*! EDFLTDIS - Edge Filter Disable + * 0b0..Enabled + * 0b1..Disabled + */ +#define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK) + +#define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U) +#define CAN_CTRL2_ISOCANFDEN_SHIFT (12U) +/*! ISOCANFDEN - ISO CAN FD Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK) + +#define CAN_CTRL2_BTE_MASK (0x2000U) +#define CAN_CTRL2_BTE_SHIFT (13U) +/*! BTE - Bit Timing Expansion Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_BTE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BTE_SHIFT)) & CAN_CTRL2_BTE_MASK) + +#define CAN_CTRL2_PREXCEN_MASK (0x4000U) +#define CAN_CTRL2_PREXCEN_SHIFT (14U) +/*! PREXCEN - Protocol Exception Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK) + +#define CAN_CTRL2_EACEN_MASK (0x10000U) +#define CAN_CTRL2_EACEN_SHIFT (16U) +/*! EACEN - Entire Frame Arbitration Field Comparison Enable for RX Message Buffers + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) + +#define CAN_CTRL2_RRS_MASK (0x20000U) +#define CAN_CTRL2_RRS_SHIFT (17U) +/*! RRS - Remote Request Storing + * 0b0..Generated + * 0b1..Stored + */ +#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) + +#define CAN_CTRL2_MRP_MASK (0x40000U) +#define CAN_CTRL2_MRP_SHIFT (18U) +/*! MRP - Message Buffers Reception Priority + * 0b0..Matching starts from Legacy RX FIFO or Enhanced RX FIFO and continues on message buffers. + * 0b1..Matching starts from message buffers and continues on Legacy RX FIFO or Enhanced RX FIFO. + */ +#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) + +#define CAN_CTRL2_TASD_MASK (0xF80000U) +#define CAN_CTRL2_TASD_SHIFT (19U) +/*! TASD - Transmission Arbitration Start Delay */ +#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) + +#define CAN_CTRL2_RFFN_MASK (0xF000000U) +#define CAN_CTRL2_RFFN_SHIFT (24U) +/*! RFFN - Number of Legacy Receive FIFO Filters */ +#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) + +#define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U) +#define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U) +/*! BOFFDONEMSK - Bus Off Done Interrupt Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK) + +#define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U) +#define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U) +/*! ERRMSK_FAST - Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK) +/*! @} */ + +/*! @name ESR2 - Error and Status 2 */ +/*! @{ */ + +#define CAN_ESR2_IMB_MASK (0x2000U) +#define CAN_ESR2_IMB_SHIFT (13U) +/*! IMB - Inactive Message Buffer + * 0b0..Message buffer indicated by ESR2[LPTM] is not inactive. + * 0b1..At least one message buffer is inactive. + */ +#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) + +#define CAN_ESR2_VPS_MASK (0x4000U) +#define CAN_ESR2_VPS_SHIFT (14U) +/*! VPS - Valid Priority Status + * 0b0..Invalid + * 0b1..Valid + */ +#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) + +#define CAN_ESR2_LPTM_MASK (0x7F0000U) +#define CAN_ESR2_LPTM_SHIFT (16U) +/*! LPTM - Lowest Priority TX Message Buffer */ +#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK) +/*! @} */ + +/*! @name CRCR - Cyclic Redundancy Check */ +/*! @{ */ + +#define CAN_CRCR_TXCRC_MASK (0x7FFFU) +#define CAN_CRCR_TXCRC_SHIFT (0U) +/*! TXCRC - Transmitted CRC value */ +#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) + +#define CAN_CRCR_MBCRC_MASK (0x7F0000U) +#define CAN_CRCR_MBCRC_SHIFT (16U) +/*! MBCRC - CRC Message Buffer */ +#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK) +/*! @} */ + +/*! @name RXFGMASK - Legacy RX FIFO Global Mask */ +/*! @{ */ + +#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) +#define CAN_RXFGMASK_FGM_SHIFT (0U) +/*! FGM - Legacy RX FIFO Global Mask Bits */ +#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK) +/*! @} */ + +/*! @name RXFIR - Legacy RX FIFO Information */ +/*! @{ */ + +#define CAN_RXFIR_IDHIT_MASK (0x1FFU) +#define CAN_RXFIR_IDHIT_SHIFT (0U) +/*! IDHIT - Identifier Acceptance Filter Hit Indicator */ +#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK) +/*! @} */ + +/*! @name CBT - CAN Bit Timing */ +/*! @{ */ + +#define CAN_CBT_EPSEG2_MASK (0x1FU) +#define CAN_CBT_EPSEG2_SHIFT (0U) +/*! EPSEG2 - Extended Phase Segment 2 */ +#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK) + +#define CAN_CBT_EPSEG1_MASK (0x3E0U) +#define CAN_CBT_EPSEG1_SHIFT (5U) +/*! EPSEG1 - Extended Phase Segment 1 */ +#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK) + +#define CAN_CBT_EPROPSEG_MASK (0xFC00U) +#define CAN_CBT_EPROPSEG_SHIFT (10U) +/*! EPROPSEG - Extended Propagation Segment */ +#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK) + +#define CAN_CBT_ERJW_MASK (0x1F0000U) +#define CAN_CBT_ERJW_SHIFT (16U) +/*! ERJW - Extended Resync Jump Width */ +#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK) + +#define CAN_CBT_EPRESDIV_MASK (0x7FE00000U) +#define CAN_CBT_EPRESDIV_SHIFT (21U) +/*! EPRESDIV - Extended Prescaler Division Factor */ +#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK) + +#define CAN_CBT_BTF_MASK (0x80000000U) +#define CAN_CBT_BTF_SHIFT (31U) +/*! BTF - Bit Timing Format Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK) +/*! @} */ + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB8B (32U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB8B (32U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB8B (32U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB8B2 (2U) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB16B (21U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB16B (21U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB16B (21U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB16B2 (4U) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB32B (12U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB32B (12U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB32B (12U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB32B2 (8U) + +/*! @name CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register */ +/*! @{ */ + +#define CAN_CS_TIME_STAMP_MASK (0xFFFFU) +#define CAN_CS_TIME_STAMP_SHIFT (0U) +/*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running + * Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field + * appears on the CAN bus. + */ +#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) + +#define CAN_CS_DLC_MASK (0xF0000U) +#define CAN_CS_DLC_SHIFT (16U) +/*! DLC - Length of the data to be stored/transmitted. */ +#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) + +#define CAN_CS_RTR_MASK (0x100000U) +#define CAN_CS_RTR_SHIFT (20U) +/*! RTR - Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) + +#define CAN_CS_IDE_MASK (0x200000U) +#define CAN_CS_IDE_SHIFT (21U) +/*! IDE - ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) + +#define CAN_CS_SRR_MASK (0x400000U) +#define CAN_CS_SRR_SHIFT (22U) +/*! SRR - Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) + +#define CAN_CS_CODE_MASK (0xF000000U) +#define CAN_CS_CODE_SHIFT (24U) +/*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by + * the FlexCAN module itself, as part of the message buffer matching and arbitration process. + */ +#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) + +#define CAN_CS_ESI_MASK (0x20000000U) +#define CAN_CS_ESI_SHIFT (29U) +/*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK) + +#define CAN_CS_BRS_MASK (0x40000000U) +#define CAN_CS_BRS_SHIFT (30U) +/*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK) + +#define CAN_CS_EDL_MASK (0x80000000U) +#define CAN_CS_EDL_SHIFT (31U) +/*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. + * The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. + */ +#define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK) +/*! @} */ + +/* The count of CAN_CS */ +#define CAN_CS_COUNT_MB64B (7U) + +/*! @name ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register */ +/*! @{ */ + +#define CAN_ID_EXT_MASK (0x3FFFFU) +#define CAN_ID_EXT_SHIFT (0U) +/*! EXT - Contains extended (LOW word) identifier of message buffer. */ +#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) + +#define CAN_ID_STD_MASK (0x1FFC0000U) +#define CAN_ID_STD_SHIFT (18U) +/*! STD - Contains standard/extended (HIGH word) identifier of message buffer. */ +#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) + +#define CAN_ID_PRIO_MASK (0xE0000000U) +#define CAN_ID_PRIO_SHIFT (29U) +/*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only + * makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular + * ID to define the transmission priority. + */ +#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK) +/*! @} */ + +/* The count of CAN_ID */ +#define CAN_ID_COUNT_MB64B (7U) + +/*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register */ +/*! @{ */ + +#define CAN_WORD_DATA_BYTE_3_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_3_SHIFT (0U) +/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK) + +#define CAN_WORD_DATA_BYTE_7_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_7_SHIFT (0U) +/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK) + +#define CAN_WORD_DATA_BYTE_11_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_11_SHIFT (0U) +/*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK) + +#define CAN_WORD_DATA_BYTE_15_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_15_SHIFT (0U) +/*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK) + +#define CAN_WORD_DATA_BYTE_19_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_19_SHIFT (0U) +/*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK) + +#define CAN_WORD_DATA_BYTE_23_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_23_SHIFT (0U) +/*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK) + +#define CAN_WORD_DATA_BYTE_27_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_27_SHIFT (0U) +/*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK) + +#define CAN_WORD_DATA_BYTE_31_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_31_SHIFT (0U) +/*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK) + +#define CAN_WORD_DATA_BYTE_35_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_35_SHIFT (0U) +/*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK) + +#define CAN_WORD_DATA_BYTE_39_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_39_SHIFT (0U) +/*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK) + +#define CAN_WORD_DATA_BYTE_43_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_43_SHIFT (0U) +/*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK) + +#define CAN_WORD_DATA_BYTE_47_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_47_SHIFT (0U) +/*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK) + +#define CAN_WORD_DATA_BYTE_51_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_51_SHIFT (0U) +/*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK) + +#define CAN_WORD_DATA_BYTE_55_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_55_SHIFT (0U) +/*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK) + +#define CAN_WORD_DATA_BYTE_59_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_59_SHIFT (0U) +/*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK) + +#define CAN_WORD_DATA_BYTE_63_MASK (0xFFU) +#define CAN_WORD_DATA_BYTE_63_SHIFT (0U) +/*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK) + +#define CAN_WORD_DATA_BYTE_2_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_2_SHIFT (8U) +/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK) + +#define CAN_WORD_DATA_BYTE_6_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_6_SHIFT (8U) +/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK) + +#define CAN_WORD_DATA_BYTE_10_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_10_SHIFT (8U) +/*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK) + +#define CAN_WORD_DATA_BYTE_14_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_14_SHIFT (8U) +/*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK) + +#define CAN_WORD_DATA_BYTE_18_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_18_SHIFT (8U) +/*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK) + +#define CAN_WORD_DATA_BYTE_22_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_22_SHIFT (8U) +/*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK) + +#define CAN_WORD_DATA_BYTE_26_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_26_SHIFT (8U) +/*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK) + +#define CAN_WORD_DATA_BYTE_30_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_30_SHIFT (8U) +/*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK) + +#define CAN_WORD_DATA_BYTE_34_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_34_SHIFT (8U) +/*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK) + +#define CAN_WORD_DATA_BYTE_38_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_38_SHIFT (8U) +/*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK) + +#define CAN_WORD_DATA_BYTE_42_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_42_SHIFT (8U) +/*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK) + +#define CAN_WORD_DATA_BYTE_46_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_46_SHIFT (8U) +/*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK) + +#define CAN_WORD_DATA_BYTE_50_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_50_SHIFT (8U) +/*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK) + +#define CAN_WORD_DATA_BYTE_54_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_54_SHIFT (8U) +/*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK) + +#define CAN_WORD_DATA_BYTE_58_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_58_SHIFT (8U) +/*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK) + +#define CAN_WORD_DATA_BYTE_62_MASK (0xFF00U) +#define CAN_WORD_DATA_BYTE_62_SHIFT (8U) +/*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK) + +#define CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_1_SHIFT (16U) +/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK) + +#define CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_5_SHIFT (16U) +/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK) + +#define CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_9_SHIFT (16U) +/*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK) + +#define CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_13_SHIFT (16U) +/*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK) + +#define CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_17_SHIFT (16U) +/*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK) + +#define CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_21_SHIFT (16U) +/*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK) + +#define CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_25_SHIFT (16U) +/*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK) + +#define CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_29_SHIFT (16U) +/*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK) + +#define CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_33_SHIFT (16U) +/*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK) + +#define CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_37_SHIFT (16U) +/*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK) + +#define CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_41_SHIFT (16U) +/*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK) + +#define CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_45_SHIFT (16U) +/*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK) + +#define CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_49_SHIFT (16U) +/*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK) + +#define CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_53_SHIFT (16U) +/*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK) + +#define CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_57_SHIFT (16U) +/*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK) + +#define CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U) +#define CAN_WORD_DATA_BYTE_61_SHIFT (16U) +/*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK) + +#define CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_0_SHIFT (24U) +/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK) + +#define CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_4_SHIFT (24U) +/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK) + +#define CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_8_SHIFT (24U) +/*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK) + +#define CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_12_SHIFT (24U) +/*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK) + +#define CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_16_SHIFT (24U) +/*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK) + +#define CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_20_SHIFT (24U) +/*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK) + +#define CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_24_SHIFT (24U) +/*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK) + +#define CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_28_SHIFT (24U) +/*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK) + +#define CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_32_SHIFT (24U) +/*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK) + +#define CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_36_SHIFT (24U) +/*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK) + +#define CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_40_SHIFT (24U) +/*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK) + +#define CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_44_SHIFT (24U) +/*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK) + +#define CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_48_SHIFT (24U) +/*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK) + +#define CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_52_SHIFT (24U) +/*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK) + +#define CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_56_SHIFT (24U) +/*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK) + +#define CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U) +#define CAN_WORD_DATA_BYTE_60_SHIFT (24U) +/*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD_DATA_BYTE_60(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK) +/*! @} */ + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB64B (7U) + +/* The count of CAN_WORD */ +#define CAN_WORD_COUNT_MB64B2 (16U) + +/* The count of CAN_CS */ +#define CAN_CS_COUNT (32U) + +/* The count of CAN_ID */ +#define CAN_ID_COUNT (32U) + +/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 31 WORD0 Register */ +/*! @{ */ + +#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) +#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) +/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) + +#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) +#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) +/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) + +#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) +#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) +/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) + +#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) +#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) +/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK) +/*! @} */ + +/* The count of CAN_WORD0 */ +#define CAN_WORD0_COUNT (32U) + +/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 31 WORD1 Register */ +/*! @{ */ + +#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) +#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) +/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) + +#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) +#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) +/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) + +#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) +#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) +/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) + +#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) +#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) +/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK) +/*! @} */ + +/* The count of CAN_WORD1 */ +#define CAN_WORD1_COUNT (32U) + +/*! @name RXIMR - Receive Individual Mask */ +/*! @{ */ + +#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) +#define CAN_RXIMR_MI_SHIFT (0U) +/*! MI - Individual Mask Bits */ +#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK) +/*! @} */ + +/* The count of CAN_RXIMR */ +#define CAN_RXIMR_COUNT (32U) + +/*! @name CTRL1_PN - Pretended Networking Control 1 */ +/*! @{ */ + +#define CAN_CTRL1_PN_FCS_MASK (0x3U) +#define CAN_CTRL1_PN_FCS_SHIFT (0U) +/*! FCS - Filtering Combination Selection + * 0b00..Message ID filtering only + * 0b01..Message ID filtering and payload filtering + * 0b10..Message ID filtering occurring a specified number of times + * 0b11..Message ID filtering and payload filtering a specified number of times + */ +#define CAN_CTRL1_PN_FCS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_FCS_SHIFT)) & CAN_CTRL1_PN_FCS_MASK) + +#define CAN_CTRL1_PN_IDFS_MASK (0xCU) +#define CAN_CTRL1_PN_IDFS_SHIFT (2U) +/*! IDFS - ID Filtering Selection + * 0b00..Match ID contents to an exact target value + * 0b01..Match an ID value greater than or equal to a specified target value + * 0b10..Match an ID value smaller than or equal to a specified target value + * 0b11..Match an ID value within a range of values, inclusive + */ +#define CAN_CTRL1_PN_IDFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_IDFS_SHIFT)) & CAN_CTRL1_PN_IDFS_MASK) + +#define CAN_CTRL1_PN_PLFS_MASK (0x30U) +#define CAN_CTRL1_PN_PLFS_SHIFT (4U) +/*! PLFS - Payload Filtering Selection + * 0b00..Match payload contents to an exact target value + * 0b01..Match a payload value greater than or equal to a specified target value + * 0b10..Match a payload value smaller than or equal to a specified target value + * 0b11..Match upon a payload value within a range of values, inclusive + */ +#define CAN_CTRL1_PN_PLFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_PLFS_SHIFT)) & CAN_CTRL1_PN_PLFS_MASK) + +#define CAN_CTRL1_PN_NMATCH_MASK (0xFF00U) +#define CAN_CTRL1_PN_NMATCH_SHIFT (8U) +/*! NMATCH - Number of Messages Matching the Same Filtering Criteria + * 0b00000001..Once + * 0b00000010..Twice + * 0b11111111..255 times + */ +#define CAN_CTRL1_PN_NMATCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_NMATCH_SHIFT)) & CAN_CTRL1_PN_NMATCH_MASK) + +#define CAN_CTRL1_PN_WUMF_MSK_MASK (0x10000U) +#define CAN_CTRL1_PN_WUMF_MSK_SHIFT (16U) +/*! WUMF_MSK - Wake-up by Matching Flag Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL1_PN_WUMF_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WUMF_MSK_SHIFT)) & CAN_CTRL1_PN_WUMF_MSK_MASK) + +#define CAN_CTRL1_PN_WTOF_MSK_MASK (0x20000U) +#define CAN_CTRL1_PN_WTOF_MSK_SHIFT (17U) +/*! WTOF_MSK - Wake-up by Timeout Flag Mask + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_CTRL1_PN_WTOF_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PN_WTOF_MSK_SHIFT)) & CAN_CTRL1_PN_WTOF_MSK_MASK) +/*! @} */ + +/*! @name CTRL2_PN - Pretended Networking Control 2 */ +/*! @{ */ + +#define CAN_CTRL2_PN_MATCHTO_MASK (0xFFFFU) +#define CAN_CTRL2_PN_MATCHTO_SHIFT (0U) +/*! MATCHTO - Timeout for No Message Matching the Filtering Criteria */ +#define CAN_CTRL2_PN_MATCHTO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PN_MATCHTO_SHIFT)) & CAN_CTRL2_PN_MATCHTO_MASK) +/*! @} */ + +/*! @name WU_MTC - Pretended Networking Wake-Up Match */ +/*! @{ */ + +#define CAN_WU_MTC_MCOUNTER_MASK (0xFF00U) +#define CAN_WU_MTC_MCOUNTER_SHIFT (8U) +/*! MCOUNTER - Number of Matches in Pretended Networking */ +#define CAN_WU_MTC_MCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_MCOUNTER_SHIFT)) & CAN_WU_MTC_MCOUNTER_MASK) + +#define CAN_WU_MTC_WUMF_MASK (0x10000U) +#define CAN_WU_MTC_WUMF_SHIFT (16U) +/*! WUMF - Wake-up by Match Flag + * 0b0..No event detected + * 0b1..Event detected + */ +#define CAN_WU_MTC_WUMF(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WUMF_SHIFT)) & CAN_WU_MTC_WUMF_MASK) + +#define CAN_WU_MTC_WTOF_MASK (0x20000U) +#define CAN_WU_MTC_WTOF_SHIFT (17U) +/*! WTOF - Wake-up by Timeout Flag Bit + * 0b0..No event detected + * 0b1..Event detected + */ +#define CAN_WU_MTC_WTOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_WU_MTC_WTOF_SHIFT)) & CAN_WU_MTC_WTOF_MASK) +/*! @} */ + +/*! @name FLT_ID1 - Pretended Networking ID Filter 1 */ +/*! @{ */ + +#define CAN_FLT_ID1_FLT_ID1_MASK (0x1FFFFFFFU) +#define CAN_FLT_ID1_FLT_ID1_SHIFT (0U) +/*! FLT_ID1 - ID Filter 1 for Pretended Networking filtering */ +#define CAN_FLT_ID1_FLT_ID1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_ID1_SHIFT)) & CAN_FLT_ID1_FLT_ID1_MASK) + +#define CAN_FLT_ID1_FLT_RTR_MASK (0x20000000U) +#define CAN_FLT_ID1_FLT_RTR_SHIFT (29U) +/*! FLT_RTR - Remote Transmission Request Filter + * 0b0..Reject remote frame (accept data frame) + * 0b1..Accept remote frame + */ +#define CAN_FLT_ID1_FLT_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_RTR_SHIFT)) & CAN_FLT_ID1_FLT_RTR_MASK) + +#define CAN_FLT_ID1_FLT_IDE_MASK (0x40000000U) +#define CAN_FLT_ID1_FLT_IDE_SHIFT (30U) +/*! FLT_IDE - ID Extended Filter + * 0b0..Standard + * 0b1..Extended + */ +#define CAN_FLT_ID1_FLT_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID1_FLT_IDE_SHIFT)) & CAN_FLT_ID1_FLT_IDE_MASK) +/*! @} */ + +/*! @name FLT_DLC - Pretended Networking Data Length Code (DLC) Filter */ +/*! @{ */ + +#define CAN_FLT_DLC_FLT_DLC_HI_MASK (0xFU) +#define CAN_FLT_DLC_FLT_DLC_HI_SHIFT (0U) +/*! FLT_DLC_HI - Upper Limit for Length of Data Bytes Filter */ +#define CAN_FLT_DLC_FLT_DLC_HI(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_HI_SHIFT)) & CAN_FLT_DLC_FLT_DLC_HI_MASK) + +#define CAN_FLT_DLC_FLT_DLC_LO_MASK (0xF0000U) +#define CAN_FLT_DLC_FLT_DLC_LO_SHIFT (16U) +/*! FLT_DLC_LO - Lower Limit for Length of Data Bytes Filter */ +#define CAN_FLT_DLC_FLT_DLC_LO(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_DLC_FLT_DLC_LO_SHIFT)) & CAN_FLT_DLC_FLT_DLC_LO_MASK) +/*! @} */ + +/*! @name PL1_LO - Pretended Networking Payload Low Filter 1 */ +/*! @{ */ + +#define CAN_PL1_LO_Data_byte_3_MASK (0xFFU) +#define CAN_PL1_LO_Data_byte_3_SHIFT (0U) +/*! Data_byte_3 - Data byte 3 */ +#define CAN_PL1_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_3_SHIFT)) & CAN_PL1_LO_Data_byte_3_MASK) + +#define CAN_PL1_LO_Data_byte_2_MASK (0xFF00U) +#define CAN_PL1_LO_Data_byte_2_SHIFT (8U) +/*! Data_byte_2 - Data byte 2 */ +#define CAN_PL1_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_2_SHIFT)) & CAN_PL1_LO_Data_byte_2_MASK) + +#define CAN_PL1_LO_Data_byte_1_MASK (0xFF0000U) +#define CAN_PL1_LO_Data_byte_1_SHIFT (16U) +/*! Data_byte_1 - Data byte 1 */ +#define CAN_PL1_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_1_SHIFT)) & CAN_PL1_LO_Data_byte_1_MASK) + +#define CAN_PL1_LO_Data_byte_0_MASK (0xFF000000U) +#define CAN_PL1_LO_Data_byte_0_SHIFT (24U) +/*! Data_byte_0 - Data byte 0 */ +#define CAN_PL1_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_LO_Data_byte_0_SHIFT)) & CAN_PL1_LO_Data_byte_0_MASK) +/*! @} */ + +/*! @name PL1_HI - Pretended Networking Payload High Filter 1 */ +/*! @{ */ + +#define CAN_PL1_HI_Data_byte_7_MASK (0xFFU) +#define CAN_PL1_HI_Data_byte_7_SHIFT (0U) +/*! Data_byte_7 - Data byte 7 */ +#define CAN_PL1_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_7_SHIFT)) & CAN_PL1_HI_Data_byte_7_MASK) + +#define CAN_PL1_HI_Data_byte_6_MASK (0xFF00U) +#define CAN_PL1_HI_Data_byte_6_SHIFT (8U) +/*! Data_byte_6 - Data byte 6 */ +#define CAN_PL1_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_6_SHIFT)) & CAN_PL1_HI_Data_byte_6_MASK) + +#define CAN_PL1_HI_Data_byte_5_MASK (0xFF0000U) +#define CAN_PL1_HI_Data_byte_5_SHIFT (16U) +/*! Data_byte_5 - Data byte 5 */ +#define CAN_PL1_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_5_SHIFT)) & CAN_PL1_HI_Data_byte_5_MASK) + +#define CAN_PL1_HI_Data_byte_4_MASK (0xFF000000U) +#define CAN_PL1_HI_Data_byte_4_SHIFT (24U) +/*! Data_byte_4 - Data byte 4 */ +#define CAN_PL1_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL1_HI_Data_byte_4_SHIFT)) & CAN_PL1_HI_Data_byte_4_MASK) +/*! @} */ + +/*! @name FLT_ID2_IDMASK - Pretended Networking ID Filter 2 or ID Mask */ +/*! @{ */ + +#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK (0x1FFFFFFFU) +#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT (0U) +/*! FLT_ID2_IDMASK - ID Filter 2 for Pretended Networking Filtering or ID Mask Bits for Pretended Networking ID Filtering */ +#define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT)) & CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK) + +#define CAN_FLT_ID2_IDMASK_RTR_MSK_MASK (0x20000000U) +#define CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT (29U) +/*! RTR_MSK - Remote Transmission Request Mask + * 0b0..The corresponding bit in the filter is "don't care." + * 0b1..The corresponding bit in the filter is checked. + */ +#define CAN_FLT_ID2_IDMASK_RTR_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_RTR_MSK_MASK) + +#define CAN_FLT_ID2_IDMASK_IDE_MSK_MASK (0x40000000U) +#define CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT (30U) +/*! IDE_MSK - ID Extended Mask + * 0b0..The corresponding bit in the filter is "don't care." + * 0b1..The corresponding bit in the filter is checked. + */ +#define CAN_FLT_ID2_IDMASK_IDE_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT)) & CAN_FLT_ID2_IDMASK_IDE_MSK_MASK) +/*! @} */ + +/*! @name PL2_PLMASK_LO - Pretended Networking Payload Low Filter 2 and Payload Low Mask */ +/*! @{ */ + +#define CAN_PL2_PLMASK_LO_Data_byte_3_MASK (0xFFU) +#define CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT (0U) +/*! Data_byte_3 - Data Byte 3 */ +#define CAN_PL2_PLMASK_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_3_MASK) + +#define CAN_PL2_PLMASK_LO_Data_byte_2_MASK (0xFF00U) +#define CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT (8U) +/*! Data_byte_2 - Data Byte 2 */ +#define CAN_PL2_PLMASK_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_2_MASK) + +#define CAN_PL2_PLMASK_LO_Data_byte_1_MASK (0xFF0000U) +#define CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT (16U) +/*! Data_byte_1 - Data Byte 1 */ +#define CAN_PL2_PLMASK_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_1_MASK) + +#define CAN_PL2_PLMASK_LO_Data_byte_0_MASK (0xFF000000U) +#define CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT (24U) +/*! Data_byte_0 - Data Byte 0 */ +#define CAN_PL2_PLMASK_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT)) & CAN_PL2_PLMASK_LO_Data_byte_0_MASK) +/*! @} */ + +/*! @name PL2_PLMASK_HI - Pretended Networking Payload High Filter 2 and Payload High Mask */ +/*! @{ */ + +#define CAN_PL2_PLMASK_HI_Data_byte_7_MASK (0xFFU) +#define CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT (0U) +/*! Data_byte_7 - Data Byte 7 */ +#define CAN_PL2_PLMASK_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_7_MASK) + +#define CAN_PL2_PLMASK_HI_Data_byte_6_MASK (0xFF00U) +#define CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT (8U) +/*! Data_byte_6 - Data Byte 6 */ +#define CAN_PL2_PLMASK_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_6_MASK) + +#define CAN_PL2_PLMASK_HI_Data_byte_5_MASK (0xFF0000U) +#define CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT (16U) +/*! Data_byte_5 - Data Byte 5 */ +#define CAN_PL2_PLMASK_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_5_MASK) + +#define CAN_PL2_PLMASK_HI_Data_byte_4_MASK (0xFF000000U) +#define CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT (24U) +/*! Data_byte_4 - Data Byte 4 */ +#define CAN_PL2_PLMASK_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT)) & CAN_PL2_PLMASK_HI_Data_byte_4_MASK) +/*! @} */ + +/*! @name WMB_CS - Wake-Up Message Buffer */ +/*! @{ */ + +#define CAN_WMB_CS_DLC_MASK (0xF0000U) +#define CAN_WMB_CS_DLC_SHIFT (16U) +/*! DLC - Length of Data in Bytes */ +#define CAN_WMB_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_DLC_SHIFT)) & CAN_WMB_CS_DLC_MASK) + +#define CAN_WMB_CS_RTR_MASK (0x100000U) +#define CAN_WMB_CS_RTR_SHIFT (20U) +/*! RTR - Remote Transmission Request + * 0b0..Data + * 0b1..Remote + */ +#define CAN_WMB_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_RTR_SHIFT)) & CAN_WMB_CS_RTR_MASK) + +#define CAN_WMB_CS_IDE_MASK (0x200000U) +#define CAN_WMB_CS_IDE_SHIFT (21U) +/*! IDE - ID Extended Bit + * 0b0..Standard + * 0b1..Extended + */ +#define CAN_WMB_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_IDE_SHIFT)) & CAN_WMB_CS_IDE_MASK) + +#define CAN_WMB_CS_SRR_MASK (0x400000U) +#define CAN_WMB_CS_SRR_SHIFT (22U) +/*! SRR - Substitute Remote Request + * 0b0..Dominant + * 0b1..Recessive + */ +#define CAN_WMB_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_CS_SRR_SHIFT)) & CAN_WMB_CS_SRR_MASK) +/*! @} */ + +/* The count of CAN_WMB_CS */ +#define CAN_WMB_CS_COUNT (4U) + +/*! @name WMB_ID - Wake-Up Message Buffer for ID */ +/*! @{ */ + +#define CAN_WMB_ID_ID_MASK (0x1FFFFFFFU) +#define CAN_WMB_ID_ID_SHIFT (0U) +/*! ID - Received ID in Pretended Networking Mode */ +#define CAN_WMB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_ID_ID_SHIFT)) & CAN_WMB_ID_ID_MASK) +/*! @} */ + +/* The count of CAN_WMB_ID */ +#define CAN_WMB_ID_COUNT (4U) + +/*! @name WMB_D03 - Wake-Up Message Buffer for Data 0-3 */ +/*! @{ */ + +#define CAN_WMB_D03_Data_byte_3_MASK (0xFFU) +#define CAN_WMB_D03_Data_byte_3_SHIFT (0U) +/*! Data_byte_3 - Data Byte 3 */ +#define CAN_WMB_D03_Data_byte_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_3_SHIFT)) & CAN_WMB_D03_Data_byte_3_MASK) + +#define CAN_WMB_D03_Data_byte_2_MASK (0xFF00U) +#define CAN_WMB_D03_Data_byte_2_SHIFT (8U) +/*! Data_byte_2 - Data Byte 2 */ +#define CAN_WMB_D03_Data_byte_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_2_SHIFT)) & CAN_WMB_D03_Data_byte_2_MASK) + +#define CAN_WMB_D03_Data_byte_1_MASK (0xFF0000U) +#define CAN_WMB_D03_Data_byte_1_SHIFT (16U) +/*! Data_byte_1 - Data Byte 1 */ +#define CAN_WMB_D03_Data_byte_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_1_SHIFT)) & CAN_WMB_D03_Data_byte_1_MASK) + +#define CAN_WMB_D03_Data_byte_0_MASK (0xFF000000U) +#define CAN_WMB_D03_Data_byte_0_SHIFT (24U) +/*! Data_byte_0 - Data Byte 0 */ +#define CAN_WMB_D03_Data_byte_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D03_Data_byte_0_SHIFT)) & CAN_WMB_D03_Data_byte_0_MASK) +/*! @} */ + +/* The count of CAN_WMB_D03 */ +#define CAN_WMB_D03_COUNT (4U) + +/*! @name WMB_D47 - Wake-Up Message Buffer Register Data 4-7 */ +/*! @{ */ + +#define CAN_WMB_D47_Data_byte_7_MASK (0xFFU) +#define CAN_WMB_D47_Data_byte_7_SHIFT (0U) +/*! Data_byte_7 - Data Byte 7 */ +#define CAN_WMB_D47_Data_byte_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_7_SHIFT)) & CAN_WMB_D47_Data_byte_7_MASK) + +#define CAN_WMB_D47_Data_byte_6_MASK (0xFF00U) +#define CAN_WMB_D47_Data_byte_6_SHIFT (8U) +/*! Data_byte_6 - Data Byte 6 */ +#define CAN_WMB_D47_Data_byte_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_6_SHIFT)) & CAN_WMB_D47_Data_byte_6_MASK) + +#define CAN_WMB_D47_Data_byte_5_MASK (0xFF0000U) +#define CAN_WMB_D47_Data_byte_5_SHIFT (16U) +/*! Data_byte_5 - Data Byte 5 */ +#define CAN_WMB_D47_Data_byte_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_5_SHIFT)) & CAN_WMB_D47_Data_byte_5_MASK) + +#define CAN_WMB_D47_Data_byte_4_MASK (0xFF000000U) +#define CAN_WMB_D47_Data_byte_4_SHIFT (24U) +/*! Data_byte_4 - Data Byte 4 */ +#define CAN_WMB_D47_Data_byte_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WMB_D47_Data_byte_4_SHIFT)) & CAN_WMB_D47_Data_byte_4_MASK) +/*! @} */ + +/* The count of CAN_WMB_D47 */ +#define CAN_WMB_D47_COUNT (4U) + +/*! @name EPRS - Enhanced CAN Bit Timing Prescalers */ +/*! @{ */ + +#define CAN_EPRS_ENPRESDIV_MASK (0x3FFU) +#define CAN_EPRS_ENPRESDIV_SHIFT (0U) +/*! ENPRESDIV - Extended Nominal Prescaler Division Factor */ +#define CAN_EPRS_ENPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_ENPRESDIV_SHIFT)) & CAN_EPRS_ENPRESDIV_MASK) + +#define CAN_EPRS_EDPRESDIV_MASK (0x3FF0000U) +#define CAN_EPRS_EDPRESDIV_SHIFT (16U) +/*! EDPRESDIV - Extended Data Phase Prescaler Division Factor */ +#define CAN_EPRS_EDPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_EDPRESDIV_SHIFT)) & CAN_EPRS_EDPRESDIV_MASK) +/*! @} */ + +/*! @name ENCBT - Enhanced Nominal CAN Bit Timing */ +/*! @{ */ + +#define CAN_ENCBT_NTSEG1_MASK (0xFFU) +#define CAN_ENCBT_NTSEG1_SHIFT (0U) +/*! NTSEG1 - Nominal Time Segment 1 */ +#define CAN_ENCBT_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG1_SHIFT)) & CAN_ENCBT_NTSEG1_MASK) + +#define CAN_ENCBT_NTSEG2_MASK (0x7F000U) +#define CAN_ENCBT_NTSEG2_SHIFT (12U) +/*! NTSEG2 - Nominal Time Segment 2 */ +#define CAN_ENCBT_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG2_SHIFT)) & CAN_ENCBT_NTSEG2_MASK) + +#define CAN_ENCBT_NRJW_MASK (0x1FC00000U) +#define CAN_ENCBT_NRJW_SHIFT (22U) +/*! NRJW - Nominal Resynchronization Jump Width */ +#define CAN_ENCBT_NRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NRJW_SHIFT)) & CAN_ENCBT_NRJW_MASK) +/*! @} */ + +/*! @name EDCBT - Enhanced Data Phase CAN Bit Timing */ +/*! @{ */ + +#define CAN_EDCBT_DTSEG1_MASK (0x1FU) +#define CAN_EDCBT_DTSEG1_SHIFT (0U) +/*! DTSEG1 - Data Phase Segment 1 */ +#define CAN_EDCBT_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG1_SHIFT)) & CAN_EDCBT_DTSEG1_MASK) + +#define CAN_EDCBT_DTSEG2_MASK (0xF000U) +#define CAN_EDCBT_DTSEG2_SHIFT (12U) +/*! DTSEG2 - Data Phase Time Segment 2 */ +#define CAN_EDCBT_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG2_SHIFT)) & CAN_EDCBT_DTSEG2_MASK) + +#define CAN_EDCBT_DRJW_MASK (0x3C00000U) +#define CAN_EDCBT_DRJW_SHIFT (22U) +/*! DRJW - Data Phase Resynchronization Jump Width */ +#define CAN_EDCBT_DRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DRJW_SHIFT)) & CAN_EDCBT_DRJW_MASK) +/*! @} */ + +/*! @name ETDC - Enhanced Transceiver Delay Compensation */ +/*! @{ */ + +#define CAN_ETDC_ETDCVAL_MASK (0xFFU) +#define CAN_ETDC_ETDCVAL_SHIFT (0U) +/*! ETDCVAL - Enhanced Transceiver Delay Compensation Value */ +#define CAN_ETDC_ETDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCVAL_SHIFT)) & CAN_ETDC_ETDCVAL_MASK) + +#define CAN_ETDC_ETDCFAIL_MASK (0x8000U) +#define CAN_ETDC_ETDCFAIL_SHIFT (15U) +/*! ETDCFAIL - Transceiver Delay Compensation Fail + * 0b0..In range + * 0b1..Out of range + */ +#define CAN_ETDC_ETDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCFAIL_SHIFT)) & CAN_ETDC_ETDCFAIL_MASK) + +#define CAN_ETDC_ETDCOFF_MASK (0x7F0000U) +#define CAN_ETDC_ETDCOFF_SHIFT (16U) +/*! ETDCOFF - Enhanced Transceiver Delay Compensation Offset */ +#define CAN_ETDC_ETDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCOFF_SHIFT)) & CAN_ETDC_ETDCOFF_MASK) + +#define CAN_ETDC_TDMDIS_MASK (0x40000000U) +#define CAN_ETDC_TDMDIS_SHIFT (30U) +/*! TDMDIS - Transceiver Delay Measurement Disable + * 0b0..Enable + * 0b1..Disable + */ +#define CAN_ETDC_TDMDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_TDMDIS_SHIFT)) & CAN_ETDC_TDMDIS_MASK) + +#define CAN_ETDC_ETDCEN_MASK (0x80000000U) +#define CAN_ETDC_ETDCEN_SHIFT (31U) +/*! ETDCEN - Transceiver Delay Compensation Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ETDC_ETDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCEN_SHIFT)) & CAN_ETDC_ETDCEN_MASK) +/*! @} */ + +/*! @name FDCTRL - CAN FD Control */ +/*! @{ */ + +#define CAN_FDCTRL_TDCVAL_MASK (0x3FU) +#define CAN_FDCTRL_TDCVAL_SHIFT (0U) +/*! TDCVAL - Transceiver Delay Compensation Value */ +#define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK) + +#define CAN_FDCTRL_TDCOFF_MASK (0x1F00U) +#define CAN_FDCTRL_TDCOFF_SHIFT (8U) +/*! TDCOFF - Transceiver Delay Compensation Offset */ +#define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK) + +#define CAN_FDCTRL_TDCFAIL_MASK (0x4000U) +#define CAN_FDCTRL_TDCFAIL_SHIFT (14U) +/*! TDCFAIL - Transceiver Delay Compensation Fail + * 0b0..In range + * 0b1..Out of range + */ +#define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK) + +#define CAN_FDCTRL_TDCEN_MASK (0x8000U) +#define CAN_FDCTRL_TDCEN_SHIFT (15U) +/*! TDCEN - Transceiver Delay Compensation Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK) + +#define CAN_FDCTRL_MBDSR0_MASK (0x30000U) +#define CAN_FDCTRL_MBDSR0_SHIFT (16U) +/*! MBDSR0 - Message Buffer Data Size for Region 0 + * 0b00..8 bytes + * 0b01..16 bytes + * 0b10..32 bytes + * 0b11..64 bytes + */ +#define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK) + +#define CAN_FDCTRL_FDRATE_MASK (0x80000000U) +#define CAN_FDCTRL_FDRATE_SHIFT (31U) +/*! FDRATE - Bit Rate Switch Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK) +/*! @} */ + +/*! @name FDCBT - CAN FD Bit Timing */ +/*! @{ */ + +#define CAN_FDCBT_FPSEG2_MASK (0x7U) +#define CAN_FDCBT_FPSEG2_SHIFT (0U) +/*! FPSEG2 - Fast Phase Segment 2 */ +#define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK) + +#define CAN_FDCBT_FPSEG1_MASK (0xE0U) +#define CAN_FDCBT_FPSEG1_SHIFT (5U) +/*! FPSEG1 - Fast Phase Segment 1 */ +#define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK) + +#define CAN_FDCBT_FPROPSEG_MASK (0x7C00U) +#define CAN_FDCBT_FPROPSEG_SHIFT (10U) +/*! FPROPSEG - Fast Propagation Segment */ +#define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK) + +#define CAN_FDCBT_FRJW_MASK (0x70000U) +#define CAN_FDCBT_FRJW_SHIFT (16U) +/*! FRJW - Fast Resync Jump Width */ +#define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK) + +#define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U) +#define CAN_FDCBT_FPRESDIV_SHIFT (20U) +/*! FPRESDIV - Fast Prescaler Division Factor */ +#define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK) +/*! @} */ + +/*! @name FDCRC - CAN FD CRC */ +/*! @{ */ + +#define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU) +#define CAN_FDCRC_FD_TXCRC_SHIFT (0U) +/*! FD_TXCRC - Extended Transmitted CRC value */ +#define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK) + +#define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U) +#define CAN_FDCRC_FD_MBCRC_SHIFT (24U) +/*! FD_MBCRC - CRC Message Buffer Number for FD_TXCRC */ +#define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK) +/*! @} */ + +/*! @name ERFCR - Enhanced RX FIFO Control */ +/*! @{ */ + +#define CAN_ERFCR_ERFWM_MASK (0x1FU) +#define CAN_ERFCR_ERFWM_SHIFT (0U) +/*! ERFWM - Enhanced RX FIFO Watermark */ +#define CAN_ERFCR_ERFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFWM_SHIFT)) & CAN_ERFCR_ERFWM_MASK) + +#define CAN_ERFCR_NFE_MASK (0x3F00U) +#define CAN_ERFCR_NFE_SHIFT (8U) +/*! NFE - Number of Enhanced RX FIFO Filter Elements */ +#define CAN_ERFCR_NFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NFE_SHIFT)) & CAN_ERFCR_NFE_MASK) + +#define CAN_ERFCR_NEXIF_MASK (0x7F0000U) +#define CAN_ERFCR_NEXIF_SHIFT (16U) +/*! NEXIF - Number of Extended ID Filter Elements */ +#define CAN_ERFCR_NEXIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NEXIF_SHIFT)) & CAN_ERFCR_NEXIF_MASK) + +#define CAN_ERFCR_DMALW_MASK (0x7C000000U) +#define CAN_ERFCR_DMALW_SHIFT (26U) +/*! DMALW - DMA Last Word */ +#define CAN_ERFCR_DMALW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_DMALW_SHIFT)) & CAN_ERFCR_DMALW_MASK) + +#define CAN_ERFCR_ERFEN_MASK (0x80000000U) +#define CAN_ERFCR_ERFEN_SHIFT (31U) +/*! ERFEN - Enhanced RX FIFO enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFCR_ERFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK) +/*! @} */ + +/*! @name ERFIER - Enhanced RX FIFO Interrupt Enable */ +/*! @{ */ + +#define CAN_ERFIER_ERFDAIE_MASK (0x10000000U) +#define CAN_ERFIER_ERFDAIE_SHIFT (28U) +/*! ERFDAIE - Enhanced RX FIFO Data Available Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFDAIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFDAIE_SHIFT)) & CAN_ERFIER_ERFDAIE_MASK) + +#define CAN_ERFIER_ERFWMIIE_MASK (0x20000000U) +#define CAN_ERFIER_ERFWMIIE_SHIFT (29U) +/*! ERFWMIIE - Enhanced RX FIFO Watermark Indication Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFWMIIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFWMIIE_SHIFT)) & CAN_ERFIER_ERFWMIIE_MASK) + +#define CAN_ERFIER_ERFOVFIE_MASK (0x40000000U) +#define CAN_ERFIER_ERFOVFIE_SHIFT (30U) +/*! ERFOVFIE - Enhanced RX FIFO Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFOVFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFOVFIE_SHIFT)) & CAN_ERFIER_ERFOVFIE_MASK) + +#define CAN_ERFIER_ERFUFWIE_MASK (0x80000000U) +#define CAN_ERFIER_ERFUFWIE_SHIFT (31U) +/*! ERFUFWIE - Enhanced RX FIFO Underflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CAN_ERFIER_ERFUFWIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFUFWIE_SHIFT)) & CAN_ERFIER_ERFUFWIE_MASK) +/*! @} */ + +/*! @name ERFSR - Enhanced RX FIFO Status */ +/*! @{ */ + +#define CAN_ERFSR_ERFEL_MASK (0x3FU) +#define CAN_ERFSR_ERFEL_SHIFT (0U) +/*! ERFEL - Enhanced RX FIFO Elements */ +#define CAN_ERFSR_ERFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFEL_SHIFT)) & CAN_ERFSR_ERFEL_MASK) + +#define CAN_ERFSR_ERFF_MASK (0x10000U) +#define CAN_ERFSR_ERFF_SHIFT (16U) +/*! ERFF - Enhanced RX FIFO Full Flag + * 0b0..Not full + * 0b1..Full + */ +#define CAN_ERFSR_ERFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFF_SHIFT)) & CAN_ERFSR_ERFF_MASK) + +#define CAN_ERFSR_ERFE_MASK (0x20000U) +#define CAN_ERFSR_ERFE_SHIFT (17U) +/*! ERFE - Enhanced RX FIFO Empty Flag + * 0b0..Not empty + * 0b1..Empty + */ +#define CAN_ERFSR_ERFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFE_SHIFT)) & CAN_ERFSR_ERFE_MASK) + +#define CAN_ERFSR_ERFCLR_MASK (0x8000000U) +#define CAN_ERFSR_ERFCLR_SHIFT (27U) +/*! ERFCLR - Enhanced RX FIFO Clear + * 0b0..No effect + * 0b1..Clear enhanced RX FIFO content + */ +#define CAN_ERFSR_ERFCLR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFCLR_SHIFT)) & CAN_ERFSR_ERFCLR_MASK) + +#define CAN_ERFSR_ERFDA_MASK (0x10000000U) +#define CAN_ERFSR_ERFDA_SHIFT (28U) +/*! ERFDA - Enhanced RX FIFO Data Available Flag + * 0b0..No such occurrence + * 0b1..At least one message stored in Enhanced RX FIFO + */ +#define CAN_ERFSR_ERFDA(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFDA_SHIFT)) & CAN_ERFSR_ERFDA_MASK) + +#define CAN_ERFSR_ERFWMI_MASK (0x20000000U) +#define CAN_ERFSR_ERFWMI_SHIFT (29U) +/*! ERFWMI - Enhanced RX FIFO Watermark Indication Flag + * 0b0..No such occurrence + * 0b1..Number of messages in FIFO is greater than the watermark + */ +#define CAN_ERFSR_ERFWMI(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK) + +#define CAN_ERFSR_ERFOVF_MASK (0x40000000U) +#define CAN_ERFSR_ERFOVF_SHIFT (30U) +/*! ERFOVF - Enhanced RX FIFO Overflow Flag + * 0b0..No such occurrence + * 0b1..Overflow + */ +#define CAN_ERFSR_ERFOVF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFOVF_SHIFT)) & CAN_ERFSR_ERFOVF_MASK) + +#define CAN_ERFSR_ERFUFW_MASK (0x80000000U) +#define CAN_ERFSR_ERFUFW_SHIFT (31U) +/*! ERFUFW - Enhanced RX FIFO Underflow Flag + * 0b0..No such occurrence + * 0b1..Underflow + */ +#define CAN_ERFSR_ERFUFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFUFW_SHIFT)) & CAN_ERFSR_ERFUFW_MASK) +/*! @} */ + +/*! @name ERFFEL - Enhanced RX FIFO Filter Element */ +/*! @{ */ + +#define CAN_ERFFEL_FEL_MASK (0xFFFFFFFFU) +#define CAN_ERFFEL_FEL_SHIFT (0U) +/*! FEL - Filter Element Bits */ +#define CAN_ERFFEL_FEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFFEL_FEL_SHIFT)) & CAN_ERFFEL_FEL_MASK) +/*! @} */ + +/* The count of CAN_ERFFEL */ +#define CAN_ERFFEL_COUNT (32U) + + +/*! + * @} + */ /* end of group CAN_Register_Masks */ + + +/* CAN - Peripheral instance base addresses */ +/** Peripheral CAN0 base address */ +#define CAN0_BASE (0x400CC000u) +/** Peripheral CAN0 base pointer */ +#define CAN0 ((CAN_Type *)CAN0_BASE) +/** Array initializer of CAN peripheral base addresses */ +#define CAN_BASE_ADDRS { CAN0_BASE } +/** Array initializer of CAN peripheral base pointers */ +#define CAN_BASE_PTRS { CAN0 } +/** Interrupt vectors for the CAN peripheral type */ +#define CAN_Rx_Warning_IRQS { CAN0_IRQn } +#define CAN_Tx_Warning_IRQS { CAN0_IRQn } +#define CAN_Wake_Up_IRQS { CAN0_IRQn } +#define CAN_Error_IRQS { CAN0_IRQn } +#define CAN_Bus_Off_IRQS { CAN0_IRQn } +#define CAN_ORed_Message_buffer_IRQS { CAN0_IRQn } + +/*! + * @} + */ /* end of group CAN_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CDOG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer + * @{ + */ + +/** CDOG - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */ + __IO uint32_t RELOAD; /**< Instruction Timer Reload Register, offset: 0x4 */ + __I uint32_t INSTRUCTION_TIMER; /**< Instruction Timer Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __I uint32_t STATUS; /**< Status 1 Register, offset: 0x10 */ + __I uint32_t STATUS2; /**< Status 2 Register, offset: 0x14 */ + __IO uint32_t FLAGS; /**< Flags Register, offset: 0x18 */ + __IO uint32_t PERSISTENT; /**< Persistent Data Storage Register, offset: 0x1C */ + __O uint32_t START; /**< START Command Register, offset: 0x20 */ + __O uint32_t STOP; /**< STOP Command Register, offset: 0x24 */ + __O uint32_t RESTART; /**< RESTART Command Register, offset: 0x28 */ + __O uint32_t ADD; /**< ADD Command Register, offset: 0x2C */ + __O uint32_t ADD1; /**< ADD1 Command Register, offset: 0x30 */ + __O uint32_t ADD16; /**< ADD16 Command Register, offset: 0x34 */ + __O uint32_t ADD256; /**< ADD256 Command Register, offset: 0x38 */ + __O uint32_t SUB; /**< SUB Command Register, offset: 0x3C */ + __O uint32_t SUB1; /**< SUB1 Command Register, offset: 0x40 */ + __O uint32_t SUB16; /**< SUB16 Command Register, offset: 0x44 */ + __O uint32_t SUB256; /**< SUB256 Command Register, offset: 0x48 */ + __O uint32_t ASSERT16; /**< ASSERT16 Command Register, offset: 0x4C */ +} CDOG_Type; + +/* ---------------------------------------------------------------------------- + -- CDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CDOG_Register_Masks CDOG Register Masks + * @{ + */ + +/*! @name CONTROL - Control Register */ +/*! @{ */ + +#define CDOG_CONTROL_LOCK_CTRL_MASK (0x3U) +#define CDOG_CONTROL_LOCK_CTRL_SHIFT (0U) +/*! LOCK_CTRL - Lock control + * 0b01..Locked + * 0b10..Unlocked + */ +#define CDOG_CONTROL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK) + +#define CDOG_CONTROL_TIMEOUT_CTRL_MASK (0x1CU) +#define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT (2U) +/*! TIMEOUT_CTRL - TIMEOUT fault control + * 0b100..Disable both reset and interrupt + * 0b001..Enable reset + * 0b010..Enable interrupt + */ +#define CDOG_CONTROL_TIMEOUT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK) + +#define CDOG_CONTROL_MISCOMPARE_CTRL_MASK (0xE0U) +#define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT (5U) +/*! MISCOMPARE_CTRL - MISCOMPARE fault control + * 0b100..Disable both reset and interrupt + * 0b001..Enable reset + * 0b010..Enable interrupt + */ +#define CDOG_CONTROL_MISCOMPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK) + +#define CDOG_CONTROL_SEQUENCE_CTRL_MASK (0x700U) +#define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT (8U) +/*! SEQUENCE_CTRL - SEQUENCE fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_SEQUENCE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK) + +#define CDOG_CONTROL_STATE_CTRL_MASK (0x1C000U) +#define CDOG_CONTROL_STATE_CTRL_SHIFT (14U) +/*! STATE_CTRL - STATE fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_STATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK) + +#define CDOG_CONTROL_ADDRESS_CTRL_MASK (0xE0000U) +#define CDOG_CONTROL_ADDRESS_CTRL_SHIFT (17U) +/*! ADDRESS_CTRL - ADDRESS fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_ADDRESS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK) + +#define CDOG_CONTROL_IRQ_PAUSE_MASK (0x30000000U) +#define CDOG_CONTROL_IRQ_PAUSE_SHIFT (28U) +/*! IRQ_PAUSE - IRQ pause control + * 0b01..Keep the timer running + * 0b10..Stop the timer + */ +#define CDOG_CONTROL_IRQ_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK) + +#define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK (0xC0000000U) +#define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT (30U) +/*! DEBUG_HALT_CTRL - DEBUG_HALT control + * 0b01..Keep the timer running + * 0b10..Stop the timer + */ +#define CDOG_CONTROL_DEBUG_HALT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK) +/*! @} */ + +/*! @name RELOAD - Instruction Timer Reload Register */ +/*! @{ */ + +#define CDOG_RELOAD_RLOAD_MASK (0xFFFFFFFFU) +#define CDOG_RELOAD_RLOAD_SHIFT (0U) +/*! RLOAD - Instruction Timer reload value */ +#define CDOG_RELOAD_RLOAD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK) +/*! @} */ + +/*! @name INSTRUCTION_TIMER - Instruction Timer Register */ +/*! @{ */ + +#define CDOG_INSTRUCTION_TIMER_INSTIM_MASK (0xFFFFFFFFU) +#define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT (0U) +/*! INSTIM - Current value of the Instruction Timer */ +#define CDOG_INSTRUCTION_TIMER_INSTIM(x) (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK) +/*! @} */ + +/*! @name STATUS - Status 1 Register */ +/*! @{ */ + +#define CDOG_STATUS_NUMTOF_MASK (0xFFU) +#define CDOG_STATUS_NUMTOF_SHIFT (0U) +/*! NUMTOF - Number of TIMEOUT faults since the last POR */ +#define CDOG_STATUS_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK) + +#define CDOG_STATUS_NUMMISCOMPF_MASK (0xFF00U) +#define CDOG_STATUS_NUMMISCOMPF_SHIFT (8U) +/*! NUMMISCOMPF - Number of MISCOMPARE faults since the last POR */ +#define CDOG_STATUS_NUMMISCOMPF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK) + +#define CDOG_STATUS_NUMILSEQF_MASK (0xFF0000U) +#define CDOG_STATUS_NUMILSEQF_SHIFT (16U) +/*! NUMILSEQF - Number of SEQUENCE faults since the last POR */ +#define CDOG_STATUS_NUMILSEQF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK) + +#define CDOG_STATUS_CURST_MASK (0xF0000000U) +#define CDOG_STATUS_CURST_SHIFT (28U) +/*! CURST - Current State */ +#define CDOG_STATUS_CURST(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK) +/*! @} */ + +/*! @name STATUS2 - Status 2 Register */ +/*! @{ */ + +#define CDOG_STATUS2_NUMCNTF_MASK (0xFFU) +#define CDOG_STATUS2_NUMCNTF_SHIFT (0U) +/*! NUMCNTF - Number of CONTROL faults since the last POR */ +#define CDOG_STATUS2_NUMCNTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK) + +#define CDOG_STATUS2_NUMILLSTF_MASK (0xFF00U) +#define CDOG_STATUS2_NUMILLSTF_SHIFT (8U) +/*! NUMILLSTF - Number of STATE faults since the last POR */ +#define CDOG_STATUS2_NUMILLSTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK) + +#define CDOG_STATUS2_NUMILLA_MASK (0xFF0000U) +#define CDOG_STATUS2_NUMILLA_SHIFT (16U) +/*! NUMILLA - Number of ADDRESS faults since the last POR */ +#define CDOG_STATUS2_NUMILLA(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK) +/*! @} */ + +/*! @name FLAGS - Flags Register */ +/*! @{ */ + +#define CDOG_FLAGS_TO_FLAG_MASK (0x1U) +#define CDOG_FLAGS_TO_FLAG_SHIFT (0U) +/*! TO_FLAG - TIMEOUT fault flag + * 0b0..A TIMEOUT fault has not occurred + * 0b1..A TIMEOUT fault has occurred + */ +#define CDOG_FLAGS_TO_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK) + +#define CDOG_FLAGS_MISCOM_FLAG_MASK (0x2U) +#define CDOG_FLAGS_MISCOM_FLAG_SHIFT (1U) +/*! MISCOM_FLAG - MISCOMPARE fault flag + * 0b0..A MISCOMPARE fault has not occurred + * 0b1..A MISCOMPARE fault has occurred + */ +#define CDOG_FLAGS_MISCOM_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK) + +#define CDOG_FLAGS_SEQ_FLAG_MASK (0x4U) +#define CDOG_FLAGS_SEQ_FLAG_SHIFT (2U) +/*! SEQ_FLAG - SEQUENCE fault flag + * 0b0..A SEQUENCE fault has not occurred + * 0b1..A SEQUENCE fault has occurred + */ +#define CDOG_FLAGS_SEQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK) + +#define CDOG_FLAGS_CNT_FLAG_MASK (0x8U) +#define CDOG_FLAGS_CNT_FLAG_SHIFT (3U) +/*! CNT_FLAG - CONTROL fault flag + * 0b0..A CONTROL fault has not occurred + * 0b1..A CONTROL fault has occurred + */ +#define CDOG_FLAGS_CNT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK) + +#define CDOG_FLAGS_STATE_FLAG_MASK (0x10U) +#define CDOG_FLAGS_STATE_FLAG_SHIFT (4U) +/*! STATE_FLAG - STATE fault flag + * 0b0..A STATE fault has not occurred + * 0b1..A STATE fault has occurred + */ +#define CDOG_FLAGS_STATE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK) + +#define CDOG_FLAGS_ADDR_FLAG_MASK (0x20U) +#define CDOG_FLAGS_ADDR_FLAG_SHIFT (5U) +/*! ADDR_FLAG - ADDRESS fault flag + * 0b0..An ADDRESS fault has not occurred + * 0b1..An ADDRESS fault has occurred + */ +#define CDOG_FLAGS_ADDR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK) + +#define CDOG_FLAGS_POR_FLAG_MASK (0x10000U) +#define CDOG_FLAGS_POR_FLAG_SHIFT (16U) +/*! POR_FLAG - Power-on reset flag + * 0b0..A Power-on reset event has not occurred + * 0b1..A Power-on reset event has occurred + */ +#define CDOG_FLAGS_POR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK) +/*! @} */ + +/*! @name PERSISTENT - Persistent Data Storage Register */ +/*! @{ */ + +#define CDOG_PERSISTENT_PERSIS_MASK (0xFFFFFFFFU) +#define CDOG_PERSISTENT_PERSIS_SHIFT (0U) +/*! PERSIS - Persistent Storage */ +#define CDOG_PERSISTENT_PERSIS(x) (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK) +/*! @} */ + +/*! @name START - START Command Register */ +/*! @{ */ + +#define CDOG_START_STRT_MASK (0xFFFFFFFFU) +#define CDOG_START_STRT_SHIFT (0U) +/*! STRT - Start command */ +#define CDOG_START_STRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK) +/*! @} */ + +/*! @name STOP - STOP Command Register */ +/*! @{ */ + +#define CDOG_STOP_STP_MASK (0xFFFFFFFFU) +#define CDOG_STOP_STP_SHIFT (0U) +/*! STP - Stop command */ +#define CDOG_STOP_STP(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK) +/*! @} */ + +/*! @name RESTART - RESTART Command Register */ +/*! @{ */ + +#define CDOG_RESTART_RSTRT_MASK (0xFFFFFFFFU) +#define CDOG_RESTART_RSTRT_SHIFT (0U) +/*! RSTRT - Restart command */ +#define CDOG_RESTART_RSTRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK) +/*! @} */ + +/*! @name ADD - ADD Command Register */ +/*! @{ */ + +#define CDOG_ADD_AD_MASK (0xFFFFFFFFU) +#define CDOG_ADD_AD_SHIFT (0U) +/*! AD - ADD Write Value */ +#define CDOG_ADD_AD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK) +/*! @} */ + +/*! @name ADD1 - ADD1 Command Register */ +/*! @{ */ + +#define CDOG_ADD1_AD1_MASK (0xFFFFFFFFU) +#define CDOG_ADD1_AD1_SHIFT (0U) +/*! AD1 - ADD 1 */ +#define CDOG_ADD1_AD1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK) +/*! @} */ + +/*! @name ADD16 - ADD16 Command Register */ +/*! @{ */ + +#define CDOG_ADD16_AD16_MASK (0xFFFFFFFFU) +#define CDOG_ADD16_AD16_SHIFT (0U) +/*! AD16 - ADD 16 */ +#define CDOG_ADD16_AD16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK) +/*! @} */ + +/*! @name ADD256 - ADD256 Command Register */ +/*! @{ */ + +#define CDOG_ADD256_AD256_MASK (0xFFFFFFFFU) +#define CDOG_ADD256_AD256_SHIFT (0U) +/*! AD256 - ADD 256 */ +#define CDOG_ADD256_AD256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK) +/*! @} */ + +/*! @name SUB - SUB Command Register */ +/*! @{ */ + +#define CDOG_SUB_SB_MASK (0xFFFFFFFFU) +#define CDOG_SUB_SB_SHIFT (0U) +/*! SB - Subtract Write Value */ +#define CDOG_SUB_SB(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_SB_SHIFT)) & CDOG_SUB_SB_MASK) +/*! @} */ + +/*! @name SUB1 - SUB1 Command Register */ +/*! @{ */ + +#define CDOG_SUB1_SB1_MASK (0xFFFFFFFFU) +#define CDOG_SUB1_SB1_SHIFT (0U) +/*! SB1 - Subtract 1 */ +#define CDOG_SUB1_SB1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_SB1_SHIFT)) & CDOG_SUB1_SB1_MASK) +/*! @} */ + +/*! @name SUB16 - SUB16 Command Register */ +/*! @{ */ + +#define CDOG_SUB16_SB16_MASK (0xFFFFFFFFU) +#define CDOG_SUB16_SB16_SHIFT (0U) +/*! SB16 - Subtract 16 */ +#define CDOG_SUB16_SB16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK) +/*! @} */ + +/*! @name SUB256 - SUB256 Command Register */ +/*! @{ */ + +#define CDOG_SUB256_SB256_MASK (0xFFFFFFFFU) +#define CDOG_SUB256_SB256_SHIFT (0U) +/*! SB256 - Subtract 256 */ +#define CDOG_SUB256_SB256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK) +/*! @} */ + +/*! @name ASSERT16 - ASSERT16 Command Register */ +/*! @{ */ + +#define CDOG_ASSERT16_AST16_MASK (0xFFFFFFFFU) +#define CDOG_ASSERT16_AST16_SHIFT (0U) +/*! AST16 - ASSERT16 Command */ +#define CDOG_ASSERT16_AST16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ASSERT16_AST16_SHIFT)) & CDOG_ASSERT16_AST16_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CDOG_Register_Masks */ + + +/* CDOG - Peripheral instance base addresses */ +/** Peripheral CDOG base address */ +#define CDOG_BASE (0x40100000u) +/** Peripheral CDOG base pointer */ +#define CDOG ((CDOG_Type *)CDOG_BASE) +/** Array initializer of CDOG peripheral base addresses */ +#define CDOG_BASE_ADDRS { CDOG_BASE } +/** Array initializer of CDOG peripheral base pointers */ +#define CDOG_BASE_PTRS { CDOG } +/** Interrupt vectors for the CDOG peripheral type */ +#define CDOG_IRQS { CDOG0_IRQn } + +/*! + * @} + */ /* end of group CDOG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMC_Peripheral_Access_Layer CMC Peripheral Access Layer + * @{ + */ + +/** CMC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t CKCTRL; /**< Clock Control, offset: 0x10 */ + __IO uint32_t CKSTAT; /**< Clock Status, offset: 0x14 */ + __IO uint32_t PMPROT; /**< Power Mode Protection, offset: 0x18 */ + __O uint32_t GPMCTRL; /**< Global Power Mode Control, offset: 0x1C */ + __IO uint32_t PMCTRL[1]; /**< Power Mode Control, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[92]; + __I uint32_t SRS; /**< System Reset Status, offset: 0x80 */ + __IO uint32_t RPC; /**< Reset Pin Control, offset: 0x84 */ + __IO uint32_t SSRS; /**< Sticky System Reset Status, offset: 0x88 */ + __IO uint32_t SRIE; /**< System Reset Interrupt Enable, offset: 0x8C */ + __IO uint32_t SRIF; /**< System Reset Interrupt Flag, offset: 0x90 */ + uint8_t RESERVED_2[8]; + __I uint32_t RSTCNT; /**< Reset Count Register, offset: 0x9C */ + __IO uint32_t MR[1]; /**< Mode, array offset: 0xA0, array step: 0x4 */ + uint8_t RESERVED_3[12]; + __IO uint32_t FM[1]; /**< Force Mode, array offset: 0xB0, array step: 0x4 */ + uint8_t RESERVED_4[44]; + __IO uint32_t FLASHCR; /**< Flash Control, offset: 0xE0 */ + uint8_t RESERVED_5[44]; + __IO uint32_t CORECTL; /**< Core Control, offset: 0x110 */ + uint8_t RESERVED_6[12]; + __IO uint32_t DBGCTL; /**< Debug Control, offset: 0x120 */ +} CMC_Type; + +/* ---------------------------------------------------------------------------- + -- CMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CMC_Register_Masks CMC Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define CMC_VERID_FEATURE_MASK (0xFFFFU) +#define CMC_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number */ +#define CMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << CMC_VERID_FEATURE_SHIFT)) & CMC_VERID_FEATURE_MASK) + +#define CMC_VERID_MINOR_MASK (0xFF0000U) +#define CMC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define CMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << CMC_VERID_MINOR_SHIFT)) & CMC_VERID_MINOR_MASK) + +#define CMC_VERID_MAJOR_MASK (0xFF000000U) +#define CMC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define CMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << CMC_VERID_MAJOR_SHIFT)) & CMC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name CKCTRL - Clock Control */ +/*! @{ */ + +#define CMC_CKCTRL_CKMODE_MASK (0xFU) +#define CMC_CKCTRL_CKMODE_SHIFT (0U) +/*! CKMODE - Clocking Mode + * 0b0000..No clock gating + * 0b1111..Core, platform, and peripheral clocks are gated, and core enters Low-Power mode. + */ +#define CMC_CKCTRL_CKMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_CKMODE_SHIFT)) & CMC_CKCTRL_CKMODE_MASK) + +#define CMC_CKCTRL_LOCK_MASK (0x80000000U) +#define CMC_CKCTRL_LOCK_SHIFT (31U) +/*! LOCK - Lock + * 0b0..Allowed + * 0b1..Blocked + */ +#define CMC_CKCTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKCTRL_LOCK_SHIFT)) & CMC_CKCTRL_LOCK_MASK) +/*! @} */ + +/*! @name CKSTAT - Clock Status */ +/*! @{ */ + +#define CMC_CKSTAT_CKMODE_MASK (0xFU) +#define CMC_CKSTAT_CKMODE_SHIFT (0U) +/*! CKMODE - Low Power Status + * 0b0000..Core clock not gated + * 0b1111..Core, platform, and peripheral clocks were gated, and power domain entered Low-Power mode + * *.. + */ +#define CMC_CKSTAT_CKMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_CKMODE_SHIFT)) & CMC_CKSTAT_CKMODE_MASK) + +#define CMC_CKSTAT_WAKEUP_MASK (0xFF00U) +#define CMC_CKSTAT_WAKEUP_SHIFT (8U) +/*! WAKEUP - Wake-up Source */ +#define CMC_CKSTAT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_WAKEUP_SHIFT)) & CMC_CKSTAT_WAKEUP_MASK) + +#define CMC_CKSTAT_VALID_MASK (0x80000000U) +#define CMC_CKSTAT_VALID_SHIFT (31U) +/*! VALID - Clock Status Valid + * 0b0..Core clock not gated + * 0b1..Core clock was gated due to Low-Power mode entry + */ +#define CMC_CKSTAT_VALID(x) (((uint32_t)(((uint32_t)(x)) << CMC_CKSTAT_VALID_SHIFT)) & CMC_CKSTAT_VALID_MASK) +/*! @} */ + +/*! @name PMPROT - Power Mode Protection */ +/*! @{ */ + +#define CMC_PMPROT_LPMODE_MASK (0xFU) +#define CMC_PMPROT_LPMODE_SHIFT (0U) +/*! LPMODE - Low-Power Mode + * 0b0000..Not allowed + * 0b0001..Allowed + * 0b0010..Allowed + * 0b0011..Allowed + * 0b0100..Allowed + * 0b0101..Allowed + * 0b0110..Allowed + * 0b0111..Allowed + * 0b1000..Allowed + * 0b1001..Allowed + * 0b1010..Allowed + * 0b1011..Allowed + * 0b1100..Allowed + * 0b1101..Allowed + * 0b1110..Allowed + * 0b1111..Allowed + */ +#define CMC_PMPROT_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_PMPROT_LPMODE_SHIFT)) & CMC_PMPROT_LPMODE_MASK) + +#define CMC_PMPROT_LOCK_MASK (0x80000000U) +#define CMC_PMPROT_LOCK_SHIFT (31U) +/*! LOCK - Lock Register + * 0b0..Allowed + * 0b1..Blocked + */ +#define CMC_PMPROT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CMC_PMPROT_LOCK_SHIFT)) & CMC_PMPROT_LOCK_MASK) +/*! @} */ + +/*! @name GPMCTRL - Global Power Mode Control */ +/*! @{ */ + +#define CMC_GPMCTRL_LPMODE_MASK (0xFU) +#define CMC_GPMCTRL_LPMODE_SHIFT (0U) +/*! LPMODE - Low-Power Mode */ +#define CMC_GPMCTRL_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_GPMCTRL_LPMODE_SHIFT)) & CMC_GPMCTRL_LPMODE_MASK) +/*! @} */ + +/*! @name PMCTRL - Power Mode Control */ +/*! @{ */ + +#define CMC_PMCTRL_LPMODE_MASK (0xFU) +#define CMC_PMCTRL_LPMODE_SHIFT (0U) +/*! LPMODE - Low-Power Mode + * 0b0000..Active/Sleep + * 0b0001..Deep Sleep + * 0b0011..Power Down + * 0b0111..Reserved + * 0b1111..Deep-Power Down + */ +#define CMC_PMCTRL_LPMODE(x) (((uint32_t)(((uint32_t)(x)) << CMC_PMCTRL_LPMODE_SHIFT)) & CMC_PMCTRL_LPMODE_MASK) +/*! @} */ + +/* The count of CMC_PMCTRL */ +#define CMC_PMCTRL_COUNT (1U) + +/*! @name SRS - System Reset Status */ +/*! @{ */ + +#define CMC_SRS_WAKEUP_MASK (0x1U) +#define CMC_SRS_WAKEUP_SHIFT (0U) +/*! WAKEUP - Wake-up Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WAKEUP_SHIFT)) & CMC_SRS_WAKEUP_MASK) + +#define CMC_SRS_POR_MASK (0x2U) +#define CMC_SRS_POR_SHIFT (1U) +/*! POR - Power-on Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_POR_SHIFT)) & CMC_SRS_POR_MASK) + +#define CMC_SRS_VD_MASK (0x4U) +#define CMC_SRS_VD_SHIFT (2U) +/*! VD - Voltage Detect Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_VD(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_VD_SHIFT)) & CMC_SRS_VD_MASK) + +#define CMC_SRS_WARM_MASK (0x10U) +#define CMC_SRS_WARM_SHIFT (4U) +/*! WARM - Warm Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_WARM(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WARM_SHIFT)) & CMC_SRS_WARM_MASK) + +#define CMC_SRS_FATAL_MASK (0x20U) +#define CMC_SRS_FATAL_SHIFT (5U) +/*! FATAL - Fatal Reset + * 0b0..Reset was not generated + * 0b1..Reset was generated + */ +#define CMC_SRS_FATAL(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_FATAL_SHIFT)) & CMC_SRS_FATAL_MASK) + +#define CMC_SRS_PIN_MASK (0x100U) +#define CMC_SRS_PIN_SHIFT (8U) +/*! PIN - Pin Reset + * 0b0..Reset was not generated + * 0b1..Reset was generated + */ +#define CMC_SRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_PIN_SHIFT)) & CMC_SRS_PIN_MASK) + +#define CMC_SRS_DAP_MASK (0x200U) +#define CMC_SRS_DAP_SHIFT (9U) +/*! DAP - Debug Access Port Reset + * 0b0..Reset was not generated + * 0b1..Reset was generated + */ +#define CMC_SRS_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_DAP_SHIFT)) & CMC_SRS_DAP_MASK) + +#define CMC_SRS_RSTACK_MASK (0x400U) +#define CMC_SRS_RSTACK_SHIFT (10U) +/*! RSTACK - Reset Timeout + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_RSTACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_RSTACK_SHIFT)) & CMC_SRS_RSTACK_MASK) + +#define CMC_SRS_LPACK_MASK (0x800U) +#define CMC_SRS_LPACK_SHIFT (11U) +/*! LPACK - Low Power Acknowledge Timeout Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LPACK_SHIFT)) & CMC_SRS_LPACK_MASK) + +#define CMC_SRS_SCG_MASK (0x1000U) +#define CMC_SRS_SCG_SHIFT (12U) +/*! SCG - System Clock Generation Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_SCG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SCG_SHIFT)) & CMC_SRS_SCG_MASK) + +#define CMC_SRS_WWDT0_MASK (0x2000U) +#define CMC_SRS_WWDT0_SHIFT (13U) +/*! WWDT0 - Windowed Watchdog 0 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_WWDT0_SHIFT)) & CMC_SRS_WWDT0_MASK) + +#define CMC_SRS_SW_MASK (0x4000U) +#define CMC_SRS_SW_SHIFT (14U) +/*! SW - Software Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_SW_SHIFT)) & CMC_SRS_SW_MASK) + +#define CMC_SRS_LOCKUP_MASK (0x8000U) +#define CMC_SRS_LOCKUP_SHIFT (15U) +/*! LOCKUP - Lockup Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_LOCKUP_SHIFT)) & CMC_SRS_LOCKUP_MASK) + +#define CMC_SRS_CDOG0_MASK (0x4000000U) +#define CMC_SRS_CDOG0_SHIFT (26U) +/*! CDOG0 - Code Watchdog 0 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SRS_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_CDOG0_SHIFT)) & CMC_SRS_CDOG0_MASK) + +#define CMC_SRS_JTAG_MASK (0x10000000U) +#define CMC_SRS_JTAG_SHIFT (28U) +/*! JTAG - JTAG System Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SRS_JTAG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRS_JTAG_SHIFT)) & CMC_SRS_JTAG_MASK) +/*! @} */ + +/*! @name RPC - Reset Pin Control */ +/*! @{ */ + +#define CMC_RPC_FILTCFG_MASK (0x1FU) +#define CMC_RPC_FILTCFG_SHIFT (0U) +/*! FILTCFG - Reset Filter Configuration */ +#define CMC_RPC_FILTCFG(x) (((uint32_t)(((uint32_t)(x)) << CMC_RPC_FILTCFG_SHIFT)) & CMC_RPC_FILTCFG_MASK) + +#define CMC_RPC_FILTEN_MASK (0x100U) +#define CMC_RPC_FILTEN_SHIFT (8U) +/*! FILTEN - Filter Enable + * 0b0..Disables + * 0b1..Enables + */ +#define CMC_RPC_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << CMC_RPC_FILTEN_SHIFT)) & CMC_RPC_FILTEN_MASK) + +#define CMC_RPC_LPFEN_MASK (0x200U) +#define CMC_RPC_LPFEN_SHIFT (9U) +/*! LPFEN - Low-Power Filter Enable + * 0b0..Disables + * 0b1..Enables + */ +#define CMC_RPC_LPFEN(x) (((uint32_t)(((uint32_t)(x)) << CMC_RPC_LPFEN_SHIFT)) & CMC_RPC_LPFEN_MASK) +/*! @} */ + +/*! @name SSRS - Sticky System Reset Status */ +/*! @{ */ + +#define CMC_SSRS_WAKEUP_MASK (0x1U) +#define CMC_SSRS_WAKEUP_SHIFT (0U) +/*! WAKEUP - Wake-up Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WAKEUP_SHIFT)) & CMC_SSRS_WAKEUP_MASK) + +#define CMC_SSRS_POR_MASK (0x2U) +#define CMC_SSRS_POR_SHIFT (1U) +/*! POR - Power-on Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_POR(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_POR_SHIFT)) & CMC_SSRS_POR_MASK) + +#define CMC_SSRS_VD_MASK (0x4U) +#define CMC_SSRS_VD_SHIFT (2U) +/*! VD - Voltage Detect Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_VD(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_VD_SHIFT)) & CMC_SSRS_VD_MASK) + +#define CMC_SSRS_WARM_MASK (0x10U) +#define CMC_SSRS_WARM_SHIFT (4U) +/*! WARM - Warm Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_WARM(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WARM_SHIFT)) & CMC_SSRS_WARM_MASK) + +#define CMC_SSRS_FATAL_MASK (0x20U) +#define CMC_SSRS_FATAL_SHIFT (5U) +/*! FATAL - Fatal Reset + * 0b0..Reset was not generated + * 0b1..Reset was generated + */ +#define CMC_SSRS_FATAL(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_FATAL_SHIFT)) & CMC_SSRS_FATAL_MASK) + +#define CMC_SSRS_PIN_MASK (0x100U) +#define CMC_SSRS_PIN_SHIFT (8U) +/*! PIN - Pin Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_PIN_SHIFT)) & CMC_SSRS_PIN_MASK) + +#define CMC_SSRS_DAP_MASK (0x200U) +#define CMC_SSRS_DAP_SHIFT (9U) +/*! DAP - DAP Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_DAP_SHIFT)) & CMC_SSRS_DAP_MASK) + +#define CMC_SSRS_RSTACK_MASK (0x400U) +#define CMC_SSRS_RSTACK_SHIFT (10U) +/*! RSTACK - Reset Timeout + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_RSTACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_RSTACK_SHIFT)) & CMC_SSRS_RSTACK_MASK) + +#define CMC_SSRS_LPACK_MASK (0x800U) +#define CMC_SSRS_LPACK_SHIFT (11U) +/*! LPACK - Low Power Acknowledge Timeout Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LPACK_SHIFT)) & CMC_SSRS_LPACK_MASK) + +#define CMC_SSRS_SCG_MASK (0x1000U) +#define CMC_SSRS_SCG_SHIFT (12U) +/*! SCG - System Clock Generation Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_SCG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SCG_SHIFT)) & CMC_SSRS_SCG_MASK) + +#define CMC_SSRS_WWDT0_MASK (0x2000U) +#define CMC_SSRS_WWDT0_SHIFT (13U) +/*! WWDT0 - Windowed Watchdog 0 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_WWDT0_SHIFT)) & CMC_SSRS_WWDT0_MASK) + +#define CMC_SSRS_SW_MASK (0x4000U) +#define CMC_SSRS_SW_SHIFT (14U) +/*! SW - Software Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_SW_SHIFT)) & CMC_SSRS_SW_MASK) + +#define CMC_SSRS_LOCKUP_MASK (0x8000U) +#define CMC_SSRS_LOCKUP_SHIFT (15U) +/*! LOCKUP - Lockup Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_LOCKUP_SHIFT)) & CMC_SSRS_LOCKUP_MASK) + +#define CMC_SSRS_CDOG0_MASK (0x4000000U) +#define CMC_SSRS_CDOG0_SHIFT (26U) +/*! CDOG0 - Code Watchdog 0 Reset + * 0b0..Reset is not generated + * 0b1..Reset is generated + */ +#define CMC_SSRS_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_CDOG0_SHIFT)) & CMC_SSRS_CDOG0_MASK) + +#define CMC_SSRS_JTAG_MASK (0x10000000U) +#define CMC_SSRS_JTAG_SHIFT (28U) +/*! JTAG - JTAG System Reset + * 0b0..Reset not generated + * 0b1..Reset generated + */ +#define CMC_SSRS_JTAG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SSRS_JTAG_SHIFT)) & CMC_SSRS_JTAG_MASK) +/*! @} */ + +/*! @name SRIE - System Reset Interrupt Enable */ +/*! @{ */ + +#define CMC_SRIE_PIN_MASK (0x100U) +#define CMC_SRIE_PIN_SHIFT (8U) +/*! PIN - Pin Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_PIN_SHIFT)) & CMC_SRIE_PIN_MASK) + +#define CMC_SRIE_DAP_MASK (0x200U) +#define CMC_SRIE_DAP_SHIFT (9U) +/*! DAP - DAP Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_DAP_SHIFT)) & CMC_SRIE_DAP_MASK) + +#define CMC_SRIE_LPACK_MASK (0x800U) +#define CMC_SRIE_LPACK_SHIFT (11U) +/*! LPACK - Low Power Acknowledge Timeout Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_LPACK_SHIFT)) & CMC_SRIE_LPACK_MASK) + +#define CMC_SRIE_SCG_MASK (0x1000U) +#define CMC_SRIE_SCG_SHIFT (12U) +/*! SCG - System Clock Generation Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_SCG(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_SCG_SHIFT)) & CMC_SRIE_SCG_MASK) + +#define CMC_SRIE_WWDT0_MASK (0x2000U) +#define CMC_SRIE_WWDT0_SHIFT (13U) +/*! WWDT0 - Windowed Watchdog 0 Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_WWDT0_SHIFT)) & CMC_SRIE_WWDT0_MASK) + +#define CMC_SRIE_SW_MASK (0x4000U) +#define CMC_SRIE_SW_SHIFT (14U) +/*! SW - Software Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_SW_SHIFT)) & CMC_SRIE_SW_MASK) + +#define CMC_SRIE_LOCKUP_MASK (0x8000U) +#define CMC_SRIE_LOCKUP_SHIFT (15U) +/*! LOCKUP - Lockup Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_LOCKUP_SHIFT)) & CMC_SRIE_LOCKUP_MASK) + +#define CMC_SRIE_CDOG0_MASK (0x4000000U) +#define CMC_SRIE_CDOG0_SHIFT (26U) +/*! CDOG0 - Code Watchdog 0 Reset + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled + */ +#define CMC_SRIE_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIE_CDOG0_SHIFT)) & CMC_SRIE_CDOG0_MASK) +/*! @} */ + +/*! @name SRIF - System Reset Interrupt Flag */ +/*! @{ */ + +#define CMC_SRIF_PIN_MASK (0x100U) +#define CMC_SRIF_PIN_SHIFT (8U) +/*! PIN - Pin Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_PIN(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_PIN_SHIFT)) & CMC_SRIF_PIN_MASK) + +#define CMC_SRIF_DAP_MASK (0x200U) +#define CMC_SRIF_DAP_SHIFT (9U) +/*! DAP - DAP Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_DAP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_DAP_SHIFT)) & CMC_SRIF_DAP_MASK) + +#define CMC_SRIF_LPACK_MASK (0x800U) +#define CMC_SRIF_LPACK_SHIFT (11U) +/*! LPACK - Low Power Acknowledge Timeout Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_LPACK(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_LPACK_SHIFT)) & CMC_SRIF_LPACK_MASK) + +#define CMC_SRIF_WWDT0_MASK (0x2000U) +#define CMC_SRIF_WWDT0_SHIFT (13U) +/*! WWDT0 - Windowed Watchdog 0 Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_WWDT0_SHIFT)) & CMC_SRIF_WWDT0_MASK) + +#define CMC_SRIF_SW_MASK (0x4000U) +#define CMC_SRIF_SW_SHIFT (14U) +/*! SW - Software Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_SW(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_SW_SHIFT)) & CMC_SRIF_SW_MASK) + +#define CMC_SRIF_LOCKUP_MASK (0x8000U) +#define CMC_SRIF_LOCKUP_SHIFT (15U) +/*! LOCKUP - Lockup Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_LOCKUP_SHIFT)) & CMC_SRIF_LOCKUP_MASK) + +#define CMC_SRIF_CDOG0_MASK (0x4000000U) +#define CMC_SRIF_CDOG0_SHIFT (26U) +/*! CDOG0 - Code Watchdog 0 Reset + * 0b0..Reset source not pending + * 0b1..Reset source pending + */ +#define CMC_SRIF_CDOG0(x) (((uint32_t)(((uint32_t)(x)) << CMC_SRIF_CDOG0_SHIFT)) & CMC_SRIF_CDOG0_MASK) +/*! @} */ + +/*! @name RSTCNT - Reset Count Register */ +/*! @{ */ + +#define CMC_RSTCNT_COUNT_MASK (0xFFU) +#define CMC_RSTCNT_COUNT_SHIFT (0U) +/*! COUNT - Count */ +#define CMC_RSTCNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CMC_RSTCNT_COUNT_SHIFT)) & CMC_RSTCNT_COUNT_MASK) +/*! @} */ + +/*! @name MR - Mode */ +/*! @{ */ + +#define CMC_MR_ISPMODE_n_MASK (0x1U) +#define CMC_MR_ISPMODE_n_SHIFT (0U) +/*! ISPMODE_n - In System Programming Mode */ +#define CMC_MR_ISPMODE_n(x) (((uint32_t)(((uint32_t)(x)) << CMC_MR_ISPMODE_n_SHIFT)) & CMC_MR_ISPMODE_n_MASK) +/*! @} */ + +/* The count of CMC_MR */ +#define CMC_MR_COUNT (1U) + +/*! @name FM - Force Mode */ +/*! @{ */ + +#define CMC_FM_FORCECFG_MASK (0x1U) +#define CMC_FM_FORCECFG_SHIFT (0U) +/*! FORCECFG - Boot Configuration + * 0b0..No effect + * 0b1..Asserts + */ +#define CMC_FM_FORCECFG(x) (((uint32_t)(((uint32_t)(x)) << CMC_FM_FORCECFG_SHIFT)) & CMC_FM_FORCECFG_MASK) +/*! @} */ + +/* The count of CMC_FM */ +#define CMC_FM_COUNT (1U) + +/*! @name FLASHCR - Flash Control */ +/*! @{ */ + +#define CMC_FLASHCR_FLASHDIS_MASK (0x1U) +#define CMC_FLASHCR_FLASHDIS_SHIFT (0U) +/*! FLASHDIS - Flash Disable + * 0b0..No effect + * 0b1..Flash memory is disabled + */ +#define CMC_FLASHCR_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHDIS_SHIFT)) & CMC_FLASHCR_FLASHDIS_MASK) + +#define CMC_FLASHCR_FLASHDOZE_MASK (0x2U) +#define CMC_FLASHCR_FLASHDOZE_SHIFT (1U) +/*! FLASHDOZE - Flash Doze + * 0b0..No effect + * 0b1..Flash memory is disabled when core is sleeping (CKMODE > 0) + */ +#define CMC_FLASHCR_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHDOZE_SHIFT)) & CMC_FLASHCR_FLASHDOZE_MASK) + +#define CMC_FLASHCR_FLASHWAKE_MASK (0x4U) +#define CMC_FLASHCR_FLASHWAKE_SHIFT (2U) +/*! FLASHWAKE - Flash Wake + * 0b0..No effect + * 0b1..Flash memory is not disabled during flash memory accesses + */ +#define CMC_FLASHCR_FLASHWAKE(x) (((uint32_t)(((uint32_t)(x)) << CMC_FLASHCR_FLASHWAKE_SHIFT)) & CMC_FLASHCR_FLASHWAKE_MASK) +/*! @} */ + +/*! @name CORECTL - Core Control */ +/*! @{ */ + +#define CMC_CORECTL_NPIE_MASK (0x1U) +#define CMC_CORECTL_NPIE_SHIFT (0U) +/*! NPIE - Non-maskable Pin Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define CMC_CORECTL_NPIE(x) (((uint32_t)(((uint32_t)(x)) << CMC_CORECTL_NPIE_SHIFT)) & CMC_CORECTL_NPIE_MASK) +/*! @} */ + +/*! @name DBGCTL - Debug Control */ +/*! @{ */ + +#define CMC_DBGCTL_SOD_MASK (0x1U) +#define CMC_DBGCTL_SOD_SHIFT (0U) +/*! SOD - Sleep Or Debug + * 0b0..Remains enabled + * 0b1..Disabled + */ +#define CMC_DBGCTL_SOD(x) (((uint32_t)(((uint32_t)(x)) << CMC_DBGCTL_SOD_SHIFT)) & CMC_DBGCTL_SOD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CMC_Register_Masks */ + + +/* CMC - Peripheral instance base addresses */ +/** Peripheral CMC base address */ +#define CMC_BASE (0x4008B000u) +/** Peripheral CMC base pointer */ +#define CMC ((CMC_Type *)CMC_BASE) +/** Array initializer of CMC peripheral base addresses */ +#define CMC_BASE_ADDRS { CMC_BASE } +/** Array initializer of CMC peripheral base pointers */ +#define CMC_BASE_PTRS { CMC } + +/*! + * @} + */ /* end of group CMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/** CRC - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + struct { /* offset: 0x0 */ + __IO uint8_t DATALL; /**< CRC_DATALL register, offset: 0x0 */ + __IO uint8_t DATALU; /**< CRC_DATALU register, offset: 0x1 */ + __IO uint8_t DATAHL; /**< CRC_DATAHL register, offset: 0x2 */ + __IO uint8_t DATAHU; /**< CRC_DATAHU register, offset: 0x3 */ + } ACCESS8BIT; + struct { /* offset: 0x0 */ + __IO uint16_t DATAL; /**< CRC_DATAL register, offset: 0x0 */ + __IO uint16_t DATAH; /**< CRC_DATAH register, offset: 0x2 */ + } ACCESS16BIT; + __IO uint32_t DATA; /**< Data, offset: 0x0 */ + }; + union { /* offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register, offset: 0x4 */ + __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register, offset: 0x5 */ + __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register, offset: 0x6 */ + __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register, offset: 0x7 */ + } GPOLY_ACCESS8BIT; + struct { /* offset: 0x4 */ + __IO uint16_t GPOLYL; /**< CRC_GPOLYL register, offset: 0x4 */ + __IO uint16_t GPOLYH; /**< CRC_GPOLYH register, offset: 0x6 */ + } GPOLY_ACCESS16BIT; + __IO uint32_t GPOLY; /**< Polynomial, offset: 0x4 */ + }; + union { /* offset: 0x8 */ + struct { /* offset: 0x8 */ + uint8_t RESERVED_0[3]; + __IO uint8_t CTRLHU; /**< CRC_CTRLHU register, offset: 0xB */ + } CTRL_ACCESS8BIT; + __IO uint32_t CTRL; /**< Control, offset: 0x8 */ + }; +} CRC_Type; + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/*! @name DATALL - CRC_DATALL register */ +/*! @{ */ + +#define CRC_DATALL_DATALL_MASK (0xFFU) +#define CRC_DATALL_DATALL_SHIFT (0U) +#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) +/*! @} */ + +/*! @name DATALU - CRC_DATALU register */ +/*! @{ */ + +#define CRC_DATALU_DATALU_MASK (0xFFU) +#define CRC_DATALU_DATALU_SHIFT (0U) +#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) +/*! @} */ + +/*! @name DATAHL - CRC_DATAHL register */ +/*! @{ */ + +#define CRC_DATAHL_DATAHL_MASK (0xFFU) +#define CRC_DATAHL_DATAHL_SHIFT (0U) +#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) +/*! @} */ + +/*! @name DATAHU - CRC_DATAHU register */ +/*! @{ */ + +#define CRC_DATAHU_DATAHU_MASK (0xFFU) +#define CRC_DATAHU_DATAHU_SHIFT (0U) +#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) +/*! @} */ + +/*! @name DATAL - CRC_DATAL register */ +/*! @{ */ + +#define CRC_DATAL_DATAL_MASK (0xFFFFU) +#define CRC_DATAL_DATAL_SHIFT (0U) +#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) +/*! @} */ + +/*! @name DATAH - CRC_DATAH register */ +/*! @{ */ + +#define CRC_DATAH_DATAH_MASK (0xFFFFU) +#define CRC_DATAH_DATAH_SHIFT (0U) +#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) +/*! @} */ + +/*! @name DATA - Data */ +/*! @{ */ + +#define CRC_DATA_LL_MASK (0xFFU) +#define CRC_DATA_LL_SHIFT (0U) +/*! LL - Lower Part of Low Byte */ +#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) + +#define CRC_DATA_LU_MASK (0xFF00U) +#define CRC_DATA_LU_SHIFT (8U) +/*! LU - Upper Part of Low Byte */ +#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) + +#define CRC_DATA_HL_MASK (0xFF0000U) +#define CRC_DATA_HL_SHIFT (16U) +/*! HL - Lower Part of High Byte */ +#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) + +#define CRC_DATA_HU_MASK (0xFF000000U) +#define CRC_DATA_HU_SHIFT (24U) +/*! HU - Upper Part of High Byte */ +#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) +/*! @} */ + +/*! @name GPOLYLL - CRC_GPOLYLL register */ +/*! @{ */ + +#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) +#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) +#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) +/*! @} */ + +/*! @name GPOLYLU - CRC_GPOLYLU register */ +/*! @{ */ + +#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) +#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) +#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) +/*! @} */ + +/*! @name GPOLYHL - CRC_GPOLYHL register */ +/*! @{ */ + +#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) +#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) +#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) +/*! @} */ + +/*! @name GPOLYHU - CRC_GPOLYHU register */ +/*! @{ */ + +#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) +#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) +#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) +/*! @} */ + +/*! @name GPOLYL - CRC_GPOLYL register */ +/*! @{ */ + +#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) +#define CRC_GPOLYL_GPOLYL_SHIFT (0U) +#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) +/*! @} */ + +/*! @name GPOLYH - CRC_GPOLYH register */ +/*! @{ */ + +#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) +#define CRC_GPOLYH_GPOLYH_SHIFT (0U) +#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) +/*! @} */ + +/*! @name GPOLY - Polynomial */ +/*! @{ */ + +#define CRC_GPOLY_LOW_MASK (0xFFFFU) +#define CRC_GPOLY_LOW_SHIFT (0U) +/*! LOW - Low Half-Word */ +#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) + +#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) +#define CRC_GPOLY_HIGH_SHIFT (16U) +/*! HIGH - High Half-Word */ +#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) +/*! @} */ + +/*! @name CTRLHU - CRC_CTRLHU register */ +/*! @{ */ + +#define CRC_CTRLHU_TCRC_MASK (0x1U) +#define CRC_CTRLHU_TCRC_SHIFT (0U) +/*! TCRC - TCRC + * 0b0..16 bits + * 0b1..32 bits + */ +#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) + +#define CRC_CTRLHU_WAS_MASK (0x2U) +#define CRC_CTRLHU_WAS_SHIFT (1U) +/*! WAS - Write as Seed + * 0b0..Data values + * 0b1..Seed values + */ +#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) + +#define CRC_CTRLHU_FXOR_MASK (0x4U) +#define CRC_CTRLHU_FXOR_SHIFT (2U) +/*! FXOR - Complement Read of CRC Data Register + * 0b0..Disables XOR on reading data. + * 0b1..Inverts or complements the read value of the CRC Data. + */ +#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) + +#define CRC_CTRLHU_TOTR_MASK (0x30U) +#define CRC_CTRLHU_TOTR_SHIFT (4U) +/*! TOTR - Transpose Type for Read + * 0b00..No transposition + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. + */ +#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) + +#define CRC_CTRLHU_TOT_MASK (0xC0U) +#define CRC_CTRLHU_TOT_SHIFT (6U) +/*! TOT - Transpose Type for Write + * 0b00..No transposition + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. + */ +#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) +/*! @} */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define CRC_CTRL_TCRC_MASK (0x1000000U) +#define CRC_CTRL_TCRC_SHIFT (24U) +/*! TCRC - TCRC + * 0b0..16 bits + * 0b1..32 bits + */ +#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) + +#define CRC_CTRL_WAS_MASK (0x2000000U) +#define CRC_CTRL_WAS_SHIFT (25U) +/*! WAS - Write as Seed + * 0b0..Data values + * 0b1..Seed values + */ +#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) + +#define CRC_CTRL_FXOR_MASK (0x4000000U) +#define CRC_CTRL_FXOR_SHIFT (26U) +/*! FXOR - Complement Read of CRC Data Register + * 0b0..Disables XOR on reading data. + * 0b1..Inverts or complements the read value of the CRC Data. + */ +#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) + +#define CRC_CTRL_TOTR_MASK (0x30000000U) +#define CRC_CTRL_TOTR_SHIFT (28U) +/*! TOTR - Transpose Type for Read + * 0b00..No transposition + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. + */ +#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) + +#define CRC_CTRL_TOT_MASK (0xC0000000U) +#define CRC_CTRL_TOT_SHIFT (30U) +/*! TOT - Transpose Type for Write + * 0b00..No transposition + * 0b01..Bits in bytes are transposed, but bytes are not transposed. + * 0b10..Both bits in bytes and bytes are transposed. + * 0b11..Only bytes are transposed, no bits in a byte are transposed. + */ +#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CRC_Register_Masks */ + + +/* CRC - Peripheral instance base addresses */ +/** Peripheral CRC0 base address */ +#define CRC0_BASE (0x4008A000u) +/** Peripheral CRC0 base pointer */ +#define CRC0 ((CRC_Type *)CRC0_BASE) +/** Array initializer of CRC peripheral base addresses */ +#define CRC_BASE_ADDRS { CRC0_BASE } +/** Array initializer of CRC peripheral base pointers */ +#define CRC_BASE_PTRS { CRC0 } + +/*! + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer + * @{ + */ + +/** CTIMER - Register Layout Typedef */ +typedef struct { + __IO uint32_t IR; /**< Interrupt, offset: 0x0 */ + __IO uint32_t TCR; /**< Timer Control, offset: 0x4 */ + __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ + __IO uint32_t PR; /**< Prescale, offset: 0xC */ + __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ + __IO uint32_t MCR; /**< Match Control, offset: 0x14 */ + __IO uint32_t MR[4]; /**< Match, array offset: 0x18, array step: 0x4 */ + __IO uint32_t CCR; /**< Capture Control, offset: 0x28 */ + __I uint32_t CR[4]; /**< Capture, array offset: 0x2C, array step: 0x4 */ + __IO uint32_t EMR; /**< External Match, offset: 0x3C */ + uint8_t RESERVED_0[48]; + __IO uint32_t CTCR; /**< Count Control, offset: 0x70 */ + __IO uint32_t PWMC; /**< PWM Control, offset: 0x74 */ + __IO uint32_t MSR[4]; /**< Match Shadow, array offset: 0x78, array step: 0x4 */ +} CTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- CTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Register_Masks CTIMER Register Masks + * @{ + */ + +/*! @name IR - Interrupt */ +/*! @{ */ + +#define CTIMER_IR_MR0INT_MASK (0x1U) +#define CTIMER_IR_MR0INT_SHIFT (0U) +/*! MR0INT - Interrupt Flag for Match Channel 0 Event */ +#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) + +#define CTIMER_IR_MR1INT_MASK (0x2U) +#define CTIMER_IR_MR1INT_SHIFT (1U) +/*! MR1INT - Interrupt Flag for Match Channel 1 Event */ +#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) + +#define CTIMER_IR_MR2INT_MASK (0x4U) +#define CTIMER_IR_MR2INT_SHIFT (2U) +/*! MR2INT - Interrupt Flag for Match Channel 2 Event */ +#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) + +#define CTIMER_IR_MR3INT_MASK (0x8U) +#define CTIMER_IR_MR3INT_SHIFT (3U) +/*! MR3INT - Interrupt Flag for Match Channel 3 Event */ +#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) + +#define CTIMER_IR_CR0INT_MASK (0x10U) +#define CTIMER_IR_CR0INT_SHIFT (4U) +/*! CR0INT - Interrupt Flag for Capture Channel 0 Event */ +#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) + +#define CTIMER_IR_CR1INT_MASK (0x20U) +#define CTIMER_IR_CR1INT_SHIFT (5U) +/*! CR1INT - Interrupt Flag for Capture Channel 1 Event */ +#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) + +#define CTIMER_IR_CR2INT_MASK (0x40U) +#define CTIMER_IR_CR2INT_SHIFT (6U) +/*! CR2INT - Interrupt Flag for Capture Channel 2 Event */ +#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) + +#define CTIMER_IR_CR3INT_MASK (0x80U) +#define CTIMER_IR_CR3INT_SHIFT (7U) +/*! CR3INT - Interrupt Flag for Capture Channel 3 Event */ +#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) +/*! @} */ + +/*! @name TCR - Timer Control */ +/*! @{ */ + +#define CTIMER_TCR_CEN_MASK (0x1U) +#define CTIMER_TCR_CEN_SHIFT (0U) +/*! CEN - Counter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) + +#define CTIMER_TCR_CRST_MASK (0x2U) +#define CTIMER_TCR_CRST_SHIFT (1U) +/*! CRST - Counter Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) + +#define CTIMER_TCR_AGCEN_MASK (0x10U) +#define CTIMER_TCR_AGCEN_SHIFT (4U) +/*! AGCEN - Allow Global Count Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_TCR_AGCEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_AGCEN_SHIFT)) & CTIMER_TCR_AGCEN_MASK) + +#define CTIMER_TCR_ATCEN_MASK (0x20U) +#define CTIMER_TCR_ATCEN_SHIFT (5U) +/*! ATCEN - Allow Trigger Count Enable + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_TCR_ATCEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_ATCEN_SHIFT)) & CTIMER_TCR_ATCEN_MASK) +/*! @} */ + +/*! @name TC - Timer Counter */ +/*! @{ */ + +#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_TC_TCVAL_SHIFT (0U) +/*! TCVAL - Timer Counter Value */ +#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) +/*! @} */ + +/*! @name PR - Prescale */ +/*! @{ */ + +#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PR_PRVAL_SHIFT (0U) +/*! PRVAL - Prescale Reload Value */ +#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) +/*! @} */ + +/*! @name PC - Prescale Counter */ +/*! @{ */ + +#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PC_PCVAL_SHIFT (0U) +/*! PCVAL - Prescale Counter Value */ +#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) +/*! @} */ + +/*! @name MCR - Match Control */ +/*! @{ */ + +#define CTIMER_MCR_MR0I_MASK (0x1U) +#define CTIMER_MCR_MR0I_SHIFT (0U) +/*! MR0I - Interrupt on MR0 + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) + +#define CTIMER_MCR_MR0R_MASK (0x2U) +#define CTIMER_MCR_MR0R_SHIFT (1U) +/*! MR0R - Reset on MR0 + * 0b0..Does not reset + * 0b1..Resets + */ +#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) + +#define CTIMER_MCR_MR0S_MASK (0x4U) +#define CTIMER_MCR_MR0S_SHIFT (2U) +/*! MR0S - Stop on MR0 + * 0b0..Does not stop + * 0b1..Stops + */ +#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) + +#define CTIMER_MCR_MR1I_MASK (0x8U) +#define CTIMER_MCR_MR1I_SHIFT (3U) +/*! MR1I - Interrupt on MR1 + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) + +#define CTIMER_MCR_MR1R_MASK (0x10U) +#define CTIMER_MCR_MR1R_SHIFT (4U) +/*! MR1R - Reset on MR1 + * 0b0..Does not reset + * 0b1..Resets + */ +#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) + +#define CTIMER_MCR_MR1S_MASK (0x20U) +#define CTIMER_MCR_MR1S_SHIFT (5U) +/*! MR1S - Stop on MR1 + * 0b0..Does not stop + * 0b1..Stops + */ +#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) + +#define CTIMER_MCR_MR2I_MASK (0x40U) +#define CTIMER_MCR_MR2I_SHIFT (6U) +/*! MR2I - Interrupt on MR2 + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) + +#define CTIMER_MCR_MR2R_MASK (0x80U) +#define CTIMER_MCR_MR2R_SHIFT (7U) +/*! MR2R - Reset on MR2 + * 0b0..Does not reset + * 0b1..Resets + */ +#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) + +#define CTIMER_MCR_MR2S_MASK (0x100U) +#define CTIMER_MCR_MR2S_SHIFT (8U) +/*! MR2S - Stop on MR2 + * 0b0..Does not stop + * 0b1..Stops + */ +#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) + +#define CTIMER_MCR_MR3I_MASK (0x200U) +#define CTIMER_MCR_MR3I_SHIFT (9U) +/*! MR3I - Interrupt on MR3 + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) + +#define CTIMER_MCR_MR3R_MASK (0x400U) +#define CTIMER_MCR_MR3R_SHIFT (10U) +/*! MR3R - Reset on MR3 + * 0b0..Does not reset + * 0b1..Resets + */ +#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) + +#define CTIMER_MCR_MR3S_MASK (0x800U) +#define CTIMER_MCR_MR3S_SHIFT (11U) +/*! MR3S - Stop on MR3 + * 0b0..Does not stop + * 0b1..Stops + */ +#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) + +#define CTIMER_MCR_MR0RL_MASK (0x1000000U) +#define CTIMER_MCR_MR0RL_SHIFT (24U) +/*! MR0RL - Reload MR + * 0b0..Does not reload + * 0b1..Reloads + */ +#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) + +#define CTIMER_MCR_MR1RL_MASK (0x2000000U) +#define CTIMER_MCR_MR1RL_SHIFT (25U) +/*! MR1RL - Reload MR + * 0b0..Does not reload + * 0b1..Reloads + */ +#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) + +#define CTIMER_MCR_MR2RL_MASK (0x4000000U) +#define CTIMER_MCR_MR2RL_SHIFT (26U) +/*! MR2RL - Reload MR + * 0b0..Does not reload + * 0b1..Reloads + */ +#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) + +#define CTIMER_MCR_MR3RL_MASK (0x8000000U) +#define CTIMER_MCR_MR3RL_SHIFT (27U) +/*! MR3RL - Reload MR + * 0b0..Does not reload + * 0b1..Reloads + */ +#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) +/*! @} */ + +/*! @name MR - Match */ +/*! @{ */ + +#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) +#define CTIMER_MR_MATCH_SHIFT (0U) +/*! MATCH - Timer Counter Match Value */ +#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) +/*! @} */ + +/* The count of CTIMER_MR */ +#define CTIMER_MR_COUNT (4U) + +/*! @name CCR - Capture Control */ +/*! @{ */ + +#define CTIMER_CCR_CAP0RE_MASK (0x1U) +#define CTIMER_CCR_CAP0RE_SHIFT (0U) +/*! CAP0RE - Rising Edge of Capture Channel 0 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) + +#define CTIMER_CCR_CAP0FE_MASK (0x2U) +#define CTIMER_CCR_CAP0FE_SHIFT (1U) +/*! CAP0FE - Falling Edge of Capture Channel 0 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) + +#define CTIMER_CCR_CAP0I_MASK (0x4U) +#define CTIMER_CCR_CAP0I_SHIFT (2U) +/*! CAP0I - Generate Interrupt on Channel 0 Capture Event + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) + +#define CTIMER_CCR_CAP1RE_MASK (0x8U) +#define CTIMER_CCR_CAP1RE_SHIFT (3U) +/*! CAP1RE - Rising Edge of Capture Channel 1 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) + +#define CTIMER_CCR_CAP1FE_MASK (0x10U) +#define CTIMER_CCR_CAP1FE_SHIFT (4U) +/*! CAP1FE - Falling Edge of Capture Channel 1 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) + +#define CTIMER_CCR_CAP1I_MASK (0x20U) +#define CTIMER_CCR_CAP1I_SHIFT (5U) +/*! CAP1I - Generate Interrupt on Channel 1 Capture Event + * 0b0..Does not generates + * 0b1..Generates + */ +#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) + +#define CTIMER_CCR_CAP2RE_MASK (0x40U) +#define CTIMER_CCR_CAP2RE_SHIFT (6U) +/*! CAP2RE - Rising Edge of Capture Channel 2 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) + +#define CTIMER_CCR_CAP2FE_MASK (0x80U) +#define CTIMER_CCR_CAP2FE_SHIFT (7U) +/*! CAP2FE - Falling Edge of Capture Channel 2 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) + +#define CTIMER_CCR_CAP2I_MASK (0x100U) +#define CTIMER_CCR_CAP2I_SHIFT (8U) +/*! CAP2I - Generate Interrupt on Channel 2 Capture Event + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) + +#define CTIMER_CCR_CAP3RE_MASK (0x200U) +#define CTIMER_CCR_CAP3RE_SHIFT (9U) +/*! CAP3RE - Rising Edge of Capture Channel 3 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) + +#define CTIMER_CCR_CAP3FE_MASK (0x400U) +#define CTIMER_CCR_CAP3FE_SHIFT (10U) +/*! CAP3FE - Falling Edge of Capture Channel 3 + * 0b0..Does not load + * 0b1..Loads + */ +#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) + +#define CTIMER_CCR_CAP3I_MASK (0x800U) +#define CTIMER_CCR_CAP3I_SHIFT (11U) +/*! CAP3I - Generate Interrupt on Channel 3 Capture Event + * 0b0..Does not generate + * 0b1..Generates + */ +#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) +/*! @} */ + +/*! @name CR - Capture */ +/*! @{ */ + +#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) +#define CTIMER_CR_CAP_SHIFT (0U) +/*! CAP - Timer Counter Capture Value */ +#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) +/*! @} */ + +/* The count of CTIMER_CR */ +#define CTIMER_CR_COUNT (4U) + +/*! @name EMR - External Match */ +/*! @{ */ + +#define CTIMER_EMR_EM0_MASK (0x1U) +#define CTIMER_EMR_EM0_SHIFT (0U) +/*! EM0 - External Match 0 + * 0b0..Low + * 0b1..High + */ +#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) + +#define CTIMER_EMR_EM1_MASK (0x2U) +#define CTIMER_EMR_EM1_SHIFT (1U) +/*! EM1 - External Match 1 + * 0b0..Low + * 0b1..High + */ +#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) + +#define CTIMER_EMR_EM2_MASK (0x4U) +#define CTIMER_EMR_EM2_SHIFT (2U) +/*! EM2 - External Match 2 + * 0b0..Low + * 0b1..High + */ +#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) + +#define CTIMER_EMR_EM3_MASK (0x8U) +#define CTIMER_EMR_EM3_SHIFT (3U) +/*! EM3 - External Match 3 + * 0b0..Low + * 0b1..High + */ +#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) + +#define CTIMER_EMR_EMC0_MASK (0x30U) +#define CTIMER_EMR_EMC0_SHIFT (4U) +/*! EMC0 - External Match Control 0 + * 0b00..Does nothing + * 0b01..Goes low + * 0b10..Goes high + * 0b11..Toggles + */ +#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) + +#define CTIMER_EMR_EMC1_MASK (0xC0U) +#define CTIMER_EMR_EMC1_SHIFT (6U) +/*! EMC1 - External Match Control 1 + * 0b00..Does nothing + * 0b01..Goes low + * 0b10..Goes high + * 0b11..Toggles + */ +#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) + +#define CTIMER_EMR_EMC2_MASK (0x300U) +#define CTIMER_EMR_EMC2_SHIFT (8U) +/*! EMC2 - External Match Control 2 + * 0b00..Does nothing + * 0b01..Goes low + * 0b10..Goes high + * 0b11..Toggles + */ +#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) + +#define CTIMER_EMR_EMC3_MASK (0xC00U) +#define CTIMER_EMR_EMC3_SHIFT (10U) +/*! EMC3 - External Match Control 3 + * 0b00..Does nothing + * 0b01..Goes low + * 0b10..Goes high + * 0b11..Toggles + */ +#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) +/*! @} */ + +/*! @name CTCR - Count Control */ +/*! @{ */ + +#define CTIMER_CTCR_CTMODE_MASK (0x3U) +#define CTIMER_CTCR_CTMODE_SHIFT (0U) +/*! CTMODE - Counter Timer Mode + * 0b00..Timer mode + * 0b01..Counter mode rising edge + * 0b10..Counter mode falling edge + * 0b11..Counter mode dual edge + */ +#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) + +#define CTIMER_CTCR_CINSEL_MASK (0xCU) +#define CTIMER_CTCR_CINSEL_SHIFT (2U) +/*! CINSEL - Count Input Select + * 0b00..Channel 0, CAPn[0] for CTIMERn + * 0b01..Channel 1, CAPn[1] for CTIMERn + * 0b10..Channel 2, CAPn[2] for CTIMERn + * 0b11..Channel 3, CAPn[3] for CTIMERn + */ +#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) + +#define CTIMER_CTCR_ENCC_MASK (0x10U) +#define CTIMER_CTCR_ENCC_SHIFT (4U) +/*! ENCC - Capture Channel Enable */ +#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) + +#define CTIMER_CTCR_SELCC_MASK (0xE0U) +#define CTIMER_CTCR_SELCC_SHIFT (5U) +/*! SELCC - Edge Select + * 0b000..Capture channel 0 rising edge + * 0b001..Capture channel 0 falling edge + * 0b010..Capture channel 1 rising edge + * 0b011..Capture channel 1 falling edge + * 0b100..Capture channel 2 rising edge + * 0b101..Capture channel 2 falling edge + */ +#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) +/*! @} */ + +/*! @name PWMC - PWM Control */ +/*! @{ */ + +#define CTIMER_PWMC_PWMEN0_MASK (0x1U) +#define CTIMER_PWMC_PWMEN0_SHIFT (0U) +/*! PWMEN0 - PWM Mode Enable for Channel 0 + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) + +#define CTIMER_PWMC_PWMEN1_MASK (0x2U) +#define CTIMER_PWMC_PWMEN1_SHIFT (1U) +/*! PWMEN1 - PWM Mode Enable for Channel 1 + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) + +#define CTIMER_PWMC_PWMEN2_MASK (0x4U) +#define CTIMER_PWMC_PWMEN2_SHIFT (2U) +/*! PWMEN2 - PWM Mode Enable for Channel 2 + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) + +#define CTIMER_PWMC_PWMEN3_MASK (0x8U) +#define CTIMER_PWMC_PWMEN3_SHIFT (3U) +/*! PWMEN3 - PWM Mode Enable for Channel 3 + * 0b0..Disable + * 0b1..Enable + */ +#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) +/*! @} */ + +/*! @name MSR - Match Shadow */ +/*! @{ */ + +#define CTIMER_MSR_MATCH_SHADOW_MASK (0xFFFFFFFFU) +#define CTIMER_MSR_MATCH_SHADOW_SHIFT (0U) +/*! MATCH_SHADOW - Timer Counter Match Shadow Value */ +#define CTIMER_MSR_MATCH_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_MATCH_SHADOW_SHIFT)) & CTIMER_MSR_MATCH_SHADOW_MASK) +/*! @} */ + +/* The count of CTIMER_MSR */ +#define CTIMER_MSR_COUNT (4U) + + +/*! + * @} + */ /* end of group CTIMER_Register_Masks */ + + +/* CTIMER - Peripheral instance base addresses */ +/** Peripheral CTIMER0 base address */ +#define CTIMER0_BASE (0x40004000u) +/** Peripheral CTIMER0 base pointer */ +#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) +/** Peripheral CTIMER1 base address */ +#define CTIMER1_BASE (0x40005000u) +/** Peripheral CTIMER1 base pointer */ +#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) +/** Peripheral CTIMER2 base address */ +#define CTIMER2_BASE (0x40006000u) +/** Peripheral CTIMER2 base pointer */ +#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) +/** Peripheral CTIMER3 base address */ +#define CTIMER3_BASE (0x40007000u) +/** Peripheral CTIMER3 base pointer */ +#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) +/** Peripheral CTIMER4 base address */ +#define CTIMER4_BASE (0x40008000u) +/** Peripheral CTIMER4 base pointer */ +#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) +/** Array initializer of CTIMER peripheral base addresses */ +#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } +/** Array initializer of CTIMER peripheral base pointers */ +#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } + +/*! + * @} + */ /* end of group CTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DEBUGMAILBOX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DEBUGMAILBOX_Peripheral_Access_Layer DEBUGMAILBOX Peripheral Access Layer + * @{ + */ + +/** DEBUGMAILBOX - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSW; /**< Command and Status Word, offset: 0x0 */ + __IO uint32_t REQUEST; /**< Request Value, offset: 0x4 */ + __IO uint32_t RETURN; /**< Return Value, offset: 0x8 */ + uint8_t RESERVED_0[240]; + __I uint32_t ID; /**< Identification, offset: 0xFC */ +} DEBUGMAILBOX_Type; + +/* ---------------------------------------------------------------------------- + -- DEBUGMAILBOX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DEBUGMAILBOX_Register_Masks DEBUGMAILBOX Register Masks + * @{ + */ + +/*! @name CSW - Command and Status Word */ +/*! @{ */ + +#define DEBUGMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) +#define DEBUGMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) +/*! RESYNCH_REQ - Resynchronization Request + * 0b0..No request + * 0b1..Request for resynchronization + */ +#define DEBUGMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DEBUGMAILBOX_CSW_RESYNCH_REQ_MASK) + +#define DEBUGMAILBOX_CSW_REQ_PENDING_MASK (0x2U) +#define DEBUGMAILBOX_CSW_REQ_PENDING_SHIFT (1U) +/*! REQ_PENDING - Request Pending + * 0b0..No request pending + * 0b1..Request for resynchronization pending + */ +#define DEBUGMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_REQ_PENDING_SHIFT)) & DEBUGMAILBOX_CSW_REQ_PENDING_MASK) + +#define DEBUGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) +#define DEBUGMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) +/*! DBG_OR_ERR - DBGMB Overrun Error + * 0b0..No overrun + * 0b1..Overrun occurred + */ +#define DEBUGMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DEBUGMAILBOX_CSW_DBG_OR_ERR_MASK) + +#define DEBUGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) +#define DEBUGMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) +/*! AHB_OR_ERR - AHB Overrun Error + * 0b0..No overrun + * 0b1..Overrun occurred + */ +#define DEBUGMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DEBUGMAILBOX_CSW_AHB_OR_ERR_MASK) + +#define DEBUGMAILBOX_CSW_SOFT_RESET_MASK (0x10U) +#define DEBUGMAILBOX_CSW_SOFT_RESET_SHIFT (4U) +/*! SOFT_RESET - Soft Reset */ +#define DEBUGMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_SOFT_RESET_SHIFT)) & DEBUGMAILBOX_CSW_SOFT_RESET_MASK) + +#define DEBUGMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) +#define DEBUGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) +/*! CHIP_RESET_REQ - Chip Reset Request */ +#define DEBUGMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DEBUGMAILBOX_CSW_CHIP_RESET_REQ_MASK) +/*! @} */ + +/*! @name REQUEST - Request Value */ +/*! @{ */ + +#define DEBUGMAILBOX_REQUEST_REQUEST_MASK (0xFFFFFFFFU) +#define DEBUGMAILBOX_REQUEST_REQUEST_SHIFT (0U) +/*! REQUEST - Request Value */ +#define DEBUGMAILBOX_REQUEST_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_REQUEST_REQUEST_SHIFT)) & DEBUGMAILBOX_REQUEST_REQUEST_MASK) +/*! @} */ + +/*! @name RETURN - Return Value */ +/*! @{ */ + +#define DEBUGMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) +#define DEBUGMAILBOX_RETURN_RET_SHIFT (0U) +/*! RET - Return Value */ +#define DEBUGMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_RETURN_RET_SHIFT)) & DEBUGMAILBOX_RETURN_RET_MASK) +/*! @} */ + +/*! @name ID - Identification */ +/*! @{ */ + +#define DEBUGMAILBOX_ID_ID_MASK (0xFFFFFFFFU) +#define DEBUGMAILBOX_ID_ID_SHIFT (0U) +/*! ID - Identification Value */ +#define DEBUGMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DEBUGMAILBOX_ID_ID_SHIFT)) & DEBUGMAILBOX_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DEBUGMAILBOX_Register_Masks */ + + +/* DEBUGMAILBOX - Peripheral instance base addresses */ +/** Peripheral DBGMAILBOX base address */ +#define DBGMAILBOX_BASE (0x40101000u) +/** Peripheral DBGMAILBOX base pointer */ +#define DBGMAILBOX ((DEBUGMAILBOX_Type *)DBGMAILBOX_BASE) +/** Array initializer of DEBUGMAILBOX peripheral base addresses */ +#define DEBUGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } +/** Array initializer of DEBUGMAILBOX peripheral base pointers */ +#define DEBUGMAILBOX_BASE_PTRS { DBGMAILBOX } + +/*! + * @} + */ /* end of group DEBUGMAILBOX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t MP_CSR; /**< Management Page Control, offset: 0x0 */ + __I uint32_t MP_ES; /**< Management Page Error Status, offset: 0x4 */ + __I uint32_t MP_INT; /**< Management Page Interrupt Request Status, offset: 0x8 */ + __I uint32_t MP_HRS; /**< Management Page Hardware Request Status, offset: 0xC */ + uint8_t RESERVED_0[240]; + __IO uint32_t CH_GRPRI[8]; /**< Channel Arbitration Group, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_1[3808]; + struct { /* offset: 0x1000, array step: 0x1000 */ + __IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x1000, array step: 0x1000 */ + __IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x1004, array step: 0x1000 */ + __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x1008, array step: 0x1000 */ + __IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0x100C, array step: 0x1000 */ + __IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x1010, array step: 0x1000 */ + __IO uint32_t CH_MUX; /**< Channel Multiplexor Configuration, array offset: 0x1014, array step: 0x1000 */ + uint8_t RESERVED_0[8]; + __IO uint32_t TCD_SADDR; /**< TCD Source Address, array offset: 0x1020, array step: 0x1000 */ + __IO uint16_t TCD_SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1024, array step: 0x1000 */ + __IO uint16_t TCD_ATTR; /**< TCD Transfer Attributes, array offset: 0x1026, array step: 0x1000 */ + union { /* offset: 0x1028, array step: 0x1000 */ + __IO uint32_t TCD_NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, array offset: 0x1028, array step: 0x1000 */ + __IO uint32_t TCD_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x1028, array step: 0x1000 */ + }; + __IO uint32_t TCD_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x102C, array step: 0x1000 */ + __IO uint32_t TCD_DADDR; /**< TCD Destination Address, array offset: 0x1030, array step: 0x1000 */ + __IO uint16_t TCD_DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1034, array step: 0x1000 */ + union { /* offset: 0x1036, array step: 0x1000 */ + __IO uint16_t TCD_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x1036, array step: 0x1000 */ + __IO uint16_t TCD_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x1036, array step: 0x1000 */ + }; + __IO uint32_t TCD_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x1038, array step: 0x1000 */ + __IO uint16_t TCD_CSR; /**< TCD Control and Status, array offset: 0x103C, array step: 0x1000 */ + union { /* offset: 0x103E, array step: 0x1000 */ + __IO uint16_t TCD_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x103E, array step: 0x1000 */ + __IO uint16_t TCD_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x103E, array step: 0x1000 */ + }; + uint8_t RESERVED_1[4032]; + } CH[8]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name MP_CSR - Management Page Control */ +/*! @{ */ + +#define DMA_MP_CSR_EDBG_MASK (0x2U) +#define DMA_MP_CSR_EDBG_SHIFT (1U) +/*! EDBG - Enable Debug + * 0b0..Debug mode disabled + * 0b1..Debug mode is enabled. + */ +#define DMA_MP_CSR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK) + +#define DMA_MP_CSR_ERCA_MASK (0x4U) +#define DMA_MP_CSR_ERCA_SHIFT (2U) +/*! ERCA - Enable Round Robin Channel Arbitration + * 0b0..Round-robin channel arbitration disabled + * 0b1..Round-robin channel arbitration enabled + */ +#define DMA_MP_CSR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK) + +#define DMA_MP_CSR_HAE_MASK (0x10U) +#define DMA_MP_CSR_HAE_SHIFT (4U) +/*! HAE - Halt After Error + * 0b0..Normal operation + * 0b1..Any error causes the HALT field to be set to 1 + */ +#define DMA_MP_CSR_HAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK) + +#define DMA_MP_CSR_HALT_MASK (0x20U) +#define DMA_MP_CSR_HALT_SHIFT (5U) +/*! HALT - Halt DMA Operations + * 0b0..Normal operation + * 0b1..Stall the start of any new channels + */ +#define DMA_MP_CSR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK) + +#define DMA_MP_CSR_GCLC_MASK (0x40U) +#define DMA_MP_CSR_GCLC_SHIFT (6U) +/*! GCLC - Global Channel Linking Control + * 0b0..Channel linking disabled for all channels + * 0b1..Channel linking available and controlled by each channel's link settings + */ +#define DMA_MP_CSR_GCLC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GCLC_SHIFT)) & DMA_MP_CSR_GCLC_MASK) + +#define DMA_MP_CSR_GMRC_MASK (0x80U) +#define DMA_MP_CSR_GMRC_SHIFT (7U) +/*! GMRC - Global Master ID Replication Control + * 0b0..Master ID replication disabled for all channels + * 0b1..Master ID replication available and controlled by each channel's CHn_SBR[EMI] setting + */ +#define DMA_MP_CSR_GMRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK) + +#define DMA_MP_CSR_ECX_MASK (0x100U) +#define DMA_MP_CSR_ECX_SHIFT (8U) +/*! ECX - Cancel Transfer With Error + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer + */ +#define DMA_MP_CSR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK) + +#define DMA_MP_CSR_CX_MASK (0x200U) +#define DMA_MP_CSR_CX_SHIFT (9U) +/*! CX - Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer + */ +#define DMA_MP_CSR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK) + +#define DMA_MP_CSR_ACTIVE_ID_MASK (0x7000000U) +#define DMA_MP_CSR_ACTIVE_ID_SHIFT (24U) +/*! ACTIVE_ID - Active Channel ID */ +#define DMA_MP_CSR_ACTIVE_ID(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK) + +#define DMA_MP_CSR_ACTIVE_MASK (0x80000000U) +#define DMA_MP_CSR_ACTIVE_SHIFT (31U) +/*! ACTIVE - DMA Active Status + * 0b0..eDMA is idle + * 0b1..eDMA is executing a channel + */ +#define DMA_MP_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK) +/*! @} */ + +/*! @name MP_ES - Management Page Error Status */ +/*! @{ */ + +#define DMA_MP_ES_DBE_MASK (0x1U) +#define DMA_MP_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..Last recorded error was a bus error on a destination write + */ +#define DMA_MP_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DBE_SHIFT)) & DMA_MP_ES_DBE_MASK) + +#define DMA_MP_ES_SBE_MASK (0x2U) +#define DMA_MP_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..Last recorded error was a bus error on a source read + */ +#define DMA_MP_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SBE_SHIFT)) & DMA_MP_ES_SBE_MASK) + +#define DMA_MP_ES_SGE_MASK (0x4U) +#define DMA_MP_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field + */ +#define DMA_MP_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SGE_SHIFT)) & DMA_MP_ES_SGE_MASK) + +#define DMA_MP_ES_NCE_MASK (0x8U) +#define DMA_MP_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error + */ +#define DMA_MP_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_NCE_SHIFT)) & DMA_MP_ES_NCE_MASK) + +#define DMA_MP_ES_DOE_MASK (0x10U) +#define DMA_MP_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field + */ +#define DMA_MP_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DOE_SHIFT)) & DMA_MP_ES_DOE_MASK) + +#define DMA_MP_ES_DAE_MASK (0x20U) +#define DMA_MP_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field + */ +#define DMA_MP_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DAE_SHIFT)) & DMA_MP_ES_DAE_MASK) + +#define DMA_MP_ES_SOE_MASK (0x40U) +#define DMA_MP_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field + */ +#define DMA_MP_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SOE_SHIFT)) & DMA_MP_ES_SOE_MASK) + +#define DMA_MP_ES_SAE_MASK (0x80U) +#define DMA_MP_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field + */ +#define DMA_MP_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SAE_SHIFT)) & DMA_MP_ES_SAE_MASK) + +#define DMA_MP_ES_ECX_MASK (0x100U) +#define DMA_MP_ES_ECX_SHIFT (8U) +/*! ECX - Transfer Canceled + * 0b0..No canceled transfers + * 0b1..Last recorded entry was a canceled transfer by the error cancel transfer input + */ +#define DMA_MP_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ECX_SHIFT)) & DMA_MP_ES_ECX_MASK) + +#define DMA_MP_ES_ERRCHN_MASK (0x7000000U) +#define DMA_MP_ES_ERRCHN_SHIFT (24U) +/*! ERRCHN - Error Channel Number or Canceled Channel Number */ +#define DMA_MP_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ERRCHN_SHIFT)) & DMA_MP_ES_ERRCHN_MASK) + +#define DMA_MP_ES_VLD_MASK (0x80000000U) +#define DMA_MP_ES_VLD_SHIFT (31U) +/*! VLD - Valid + * 0b0..No CHn_ES[ERR] fields are set to 1 + * 0b1..At least one CHn_ES[ERR] field is set to 1, indicating a valid error exists that software has not cleared + */ +#define DMA_MP_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_VLD_SHIFT)) & DMA_MP_ES_VLD_MASK) +/*! @} */ + +/*! @name MP_INT - Management Page Interrupt Request Status */ +/*! @{ */ + +#define DMA_MP_INT_INT_MASK (0xFFU) +#define DMA_MP_INT_INT_SHIFT (0U) +/*! INT - Interrupt Request Status */ +#define DMA_MP_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_INT_INT_SHIFT)) & DMA_MP_INT_INT_MASK) +/*! @} */ + +/*! @name MP_HRS - Management Page Hardware Request Status */ +/*! @{ */ + +#define DMA_MP_HRS_HRS_MASK (0xFFFFFFFFU) +#define DMA_MP_HRS_HRS_SHIFT (0U) +/*! HRS - Hardware Request Status */ +#define DMA_MP_HRS_HRS(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_HRS_HRS_SHIFT)) & DMA_MP_HRS_HRS_MASK) +/*! @} */ + +/*! @name CH_GRPRI - Channel Arbitration Group */ +/*! @{ */ + +#define DMA_CH_GRPRI_GRPRI_MASK (0x1FU) +#define DMA_CH_GRPRI_GRPRI_SHIFT (0U) +/*! GRPRI - Arbitration Group For Channel n */ +#define DMA_CH_GRPRI_GRPRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_GRPRI_GRPRI_SHIFT)) & DMA_CH_GRPRI_GRPRI_MASK) +/*! @} */ + +/* The count of DMA_CH_GRPRI */ +#define DMA_CH_GRPRI_COUNT (8U) + +/*! @name CH_CSR - Channel Control and Status */ +/*! @{ */ + +#define DMA_CH_CSR_ERQ_MASK (0x1U) +#define DMA_CH_CSR_ERQ_SHIFT (0U) +/*! ERQ - Enable DMA Request + * 0b0..DMA hardware request signal for corresponding channel disabled + * 0b1..DMA hardware request signal for corresponding channel enabled + */ +#define DMA_CH_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK) + +#define DMA_CH_CSR_EARQ_MASK (0x2U) +#define DMA_CH_CSR_EARQ_SHIFT (1U) +/*! EARQ - Enable Asynchronous DMA Request + * 0b0..Disable asynchronous DMA request for the channel + * 0b1..Enable asynchronous DMA request for the channel + */ +#define DMA_CH_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EARQ_SHIFT)) & DMA_CH_CSR_EARQ_MASK) + +#define DMA_CH_CSR_EEI_MASK (0x4U) +#define DMA_CH_CSR_EEI_SHIFT (2U) +/*! EEI - Enable Error Interrupt + * 0b0..Error signal for corresponding channel does not generate error interrupt + * 0b1..Assertion of error signal for corresponding channel generates error interrupt request + */ +#define DMA_CH_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EEI_SHIFT)) & DMA_CH_CSR_EEI_MASK) + +#define DMA_CH_CSR_EBW_MASK (0x8U) +#define DMA_CH_CSR_EBW_SHIFT (3U) +/*! EBW - Enable Buffered Writes + * 0b0..Buffered writes on system bus disabled + * 0b1..Buffered writes on system bus enabled + */ +#define DMA_CH_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EBW_SHIFT)) & DMA_CH_CSR_EBW_MASK) + +#define DMA_CH_CSR_DONE_MASK (0x40000000U) +#define DMA_CH_CSR_DONE_SHIFT (30U) +/*! DONE - Channel Done */ +#define DMA_CH_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_DONE_SHIFT)) & DMA_CH_CSR_DONE_MASK) + +#define DMA_CH_CSR_ACTIVE_MASK (0x80000000U) +#define DMA_CH_CSR_ACTIVE_SHIFT (31U) +/*! ACTIVE - Channel Active */ +#define DMA_CH_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ACTIVE_SHIFT)) & DMA_CH_CSR_ACTIVE_MASK) +/*! @} */ + +/* The count of DMA_CH_CSR */ +#define DMA_CH_CSR_COUNT (8U) + +/*! @name CH_ES - Channel Error Status */ +/*! @{ */ + +#define DMA_CH_ES_DBE_MASK (0x1U) +#define DMA_CH_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error + * 0b1..Last recorded error was bus error on destination write + */ +#define DMA_CH_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DBE_SHIFT)) & DMA_CH_ES_DBE_MASK) + +#define DMA_CH_ES_SBE_MASK (0x2U) +#define DMA_CH_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error + * 0b1..Last recorded error was bus error on source read + */ +#define DMA_CH_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SBE_SHIFT)) & DMA_CH_ES_SBE_MASK) + +#define DMA_CH_ES_SGE_MASK (0x4U) +#define DMA_CH_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DLAST_SGA field + */ +#define DMA_CH_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SGE_SHIFT)) & DMA_CH_ES_SGE_MASK) + +#define DMA_CH_ES_NCE_MASK (0x8U) +#define DMA_CH_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields + */ +#define DMA_CH_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_NCE_SHIFT)) & DMA_CH_ES_NCE_MASK) + +#define DMA_CH_ES_DOE_MASK (0x10U) +#define DMA_CH_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DOFF field + */ +#define DMA_CH_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DOE_SHIFT)) & DMA_CH_ES_DOE_MASK) + +#define DMA_CH_ES_DAE_MASK (0x20U) +#define DMA_CH_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_DADDR field + */ +#define DMA_CH_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DAE_SHIFT)) & DMA_CH_ES_DAE_MASK) + +#define DMA_CH_ES_SOE_MASK (0x40U) +#define DMA_CH_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SOFF field + */ +#define DMA_CH_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SOE_SHIFT)) & DMA_CH_ES_SOE_MASK) + +#define DMA_CH_ES_SAE_MASK (0x80U) +#define DMA_CH_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error + * 0b1..Last recorded error was a configuration error detected in the TCDn_SADDR field + */ +#define DMA_CH_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SAE_SHIFT)) & DMA_CH_ES_SAE_MASK) + +#define DMA_CH_ES_ERR_MASK (0x80000000U) +#define DMA_CH_ES_ERR_SHIFT (31U) +/*! ERR - Error In Channel + * 0b0..An error in this channel has not occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_CH_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_ERR_SHIFT)) & DMA_CH_ES_ERR_MASK) +/*! @} */ + +/* The count of DMA_CH_ES */ +#define DMA_CH_ES_COUNT (8U) + +/*! @name CH_INT - Channel Interrupt Status */ +/*! @{ */ + +#define DMA_CH_INT_INT_MASK (0x1U) +#define DMA_CH_INT_INT_SHIFT (0U) +/*! INT - Interrupt Request + * 0b0..Interrupt request for corresponding channel cleared + * 0b1..Interrupt request for corresponding channel active + */ +#define DMA_CH_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK) +/*! @} */ + +/* The count of DMA_CH_INT */ +#define DMA_CH_INT_COUNT (8U) + +/*! @name CH_SBR - Channel System Bus */ +/*! @{ */ + +#define DMA_CH_SBR_MID_MASK (0xFU) +#define DMA_CH_SBR_MID_SHIFT (0U) +/*! MID - Master ID */ +#define DMA_CH_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK) + +#define DMA_CH_SBR_PAL_MASK (0x8000U) +#define DMA_CH_SBR_PAL_SHIFT (15U) +/*! PAL - Privileged Access Level + * 0b0..User protection level for DMA transfers + * 0b1..Privileged protection level for DMA transfers + */ +#define DMA_CH_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_PAL_SHIFT)) & DMA_CH_SBR_PAL_MASK) + +#define DMA_CH_SBR_EMI_MASK (0x10000U) +#define DMA_CH_SBR_EMI_SHIFT (16U) +/*! EMI - Enable Master ID Replication + * 0b0..Master ID replication is disabled + * 0b1..Master ID replication is enabled + */ +#define DMA_CH_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_EMI_SHIFT)) & DMA_CH_SBR_EMI_MASK) +/*! @} */ + +/* The count of DMA_CH_SBR */ +#define DMA_CH_SBR_COUNT (8U) + +/*! @name CH_PRI - Channel Priority */ +/*! @{ */ + +#define DMA_CH_PRI_APL_MASK (0x7U) +#define DMA_CH_PRI_APL_SHIFT (0U) +/*! APL - Arbitration Priority Level */ +#define DMA_CH_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_APL_SHIFT)) & DMA_CH_PRI_APL_MASK) + +#define DMA_CH_PRI_DPA_MASK (0x40000000U) +#define DMA_CH_PRI_DPA_SHIFT (30U) +/*! DPA - Disable Preempt Ability + * 0b0..Channel can suspend a lower-priority channel + * 0b1..Channel cannot suspend any other channel, regardless of channel priority + */ +#define DMA_CH_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_DPA_SHIFT)) & DMA_CH_PRI_DPA_MASK) + +#define DMA_CH_PRI_ECP_MASK (0x80000000U) +#define DMA_CH_PRI_ECP_SHIFT (31U) +/*! ECP - Enable Channel Preemption + * 0b0..Channel cannot be suspended by a higher-priority channel's service request + * 0b1..Channel can be temporarily suspended by a higher-priority channel's service request + */ +#define DMA_CH_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_ECP_SHIFT)) & DMA_CH_PRI_ECP_MASK) +/*! @} */ + +/* The count of DMA_CH_PRI */ +#define DMA_CH_PRI_COUNT (8U) + +/*! @name CH_MUX - Channel Multiplexor Configuration */ +/*! @{ */ + +#define DMA_CH_MUX_SRC_MASK (0x7FU) +#define DMA_CH_MUX_SRC_SHIFT (0U) +/*! SRC - Service Request Source */ +#define DMA_CH_MUX_SRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_MUX_SRC_SHIFT)) & DMA_CH_MUX_SRC_MASK) +/*! @} */ + +/* The count of DMA_CH_MUX */ +#define DMA_CH_MUX_COUNT (8U) + +/*! @name TCD_SADDR - TCD Source Address */ +/*! @{ */ + +#define DMA_TCD_SADDR_SADDR_MASK (0xFFFFFFFFU) +#define DMA_TCD_SADDR_SADDR_SHIFT (0U) +/*! SADDR - Source Address */ +#define DMA_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SADDR_SHIFT)) & DMA_TCD_SADDR_SADDR_MASK) +/*! @} */ + +/* The count of DMA_TCD_SADDR */ +#define DMA_TCD_SADDR_COUNT (8U) + +/*! @name TCD_SOFF - TCD Signed Source Address Offset */ +/*! @{ */ + +#define DMA_TCD_SOFF_SOFF_MASK (0xFFFFU) +#define DMA_TCD_SOFF_SOFF_SHIFT (0U) +/*! SOFF - Source Address Signed Offset */ +#define DMA_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_SOFF_SOFF_SHIFT)) & DMA_TCD_SOFF_SOFF_MASK) +/*! @} */ + +/* The count of DMA_TCD_SOFF */ +#define DMA_TCD_SOFF_COUNT (8U) + +/*! @name TCD_ATTR - TCD Transfer Attributes */ +/*! @{ */ + +#define DMA_TCD_ATTR_DSIZE_MASK (0x7U) +#define DMA_TCD_ATTR_DSIZE_SHIFT (0U) +/*! DSIZE - Destination Data Transfer Size */ +#define DMA_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DSIZE_SHIFT)) & DMA_TCD_ATTR_DSIZE_MASK) + +#define DMA_TCD_ATTR_DMOD_MASK (0xF8U) +#define DMA_TCD_ATTR_DMOD_SHIFT (3U) +/*! DMOD - Destination Address Modulo */ +#define DMA_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DMOD_SHIFT)) & DMA_TCD_ATTR_DMOD_MASK) + +#define DMA_TCD_ATTR_SSIZE_MASK (0x700U) +#define DMA_TCD_ATTR_SSIZE_SHIFT (8U) +/*! SSIZE - Source Data Transfer Size + * 0b000..8-bit + * 0b001..16-bit + * 0b010..32-bit + * 0b011..64-bit + * 0b100..16-byte + * 0b101..32-byte + * 0b110.. + * 0b111.. + */ +#define DMA_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SSIZE_SHIFT)) & DMA_TCD_ATTR_SSIZE_MASK) + +#define DMA_TCD_ATTR_SMOD_MASK (0xF800U) +#define DMA_TCD_ATTR_SMOD_SHIFT (11U) +/*! SMOD - Source Address Modulo + * 0b00000..Source address modulo feature disabled + * 0b00001..Source address modulo feature enabled for any non-zero value [1-31] + */ +#define DMA_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK) +/*! @} */ + +/* The count of DMA_TCD_ATTR */ +#define DMA_TCD_ATTR_COUNT (8U) + +/*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ +/*! @{ */ + +#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) +#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) +/*! NBYTES - Number of Bytes To Transfer Per Service Request */ +#define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK) + +#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) +#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to DADDR + * 0b1..Minor loop offset applied to DADDR + */ +#define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK) + +#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) +#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to SADDR + * 0b1..Minor loop offset applied to SADDR + */ +#define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK) +/*! @} */ + +/* The count of DMA_TCD_NBYTES_MLOFFNO */ +#define DMA_TCD_NBYTES_MLOFFNO_COUNT (8U) + +/*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ +/*! @{ */ + +#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) +#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) +/*! NBYTES - Number of Bytes To Transfer Per Service Request */ +#define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK) + +#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) +#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) +/*! MLOFF - Minor Loop Offset */ +#define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK) + +#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) +#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to DADDR + * 0b1..Minor loop offset applied to DADDR + */ +#define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK) + +#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) +#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..Minor loop offset not applied to SADDR + * 0b1..Minor loop offset applied to SADDR + */ +#define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK) +/*! @} */ + +/* The count of DMA_TCD_NBYTES_MLOFFYES */ +#define DMA_TCD_NBYTES_MLOFFYES_COUNT (8U) + +/*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ +/*! @{ */ + +#define DMA_TCD_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) +#define DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT (0U) +/*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address */ +#define DMA_TCD_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_SLAST_SDA_SLAST_SDA_MASK) +/*! @} */ + +/* The count of DMA_TCD_SLAST_SDA */ +#define DMA_TCD_SLAST_SDA_COUNT (8U) + +/*! @name TCD_DADDR - TCD Destination Address */ +/*! @{ */ + +#define DMA_TCD_DADDR_DADDR_MASK (0xFFFFFFFFU) +#define DMA_TCD_DADDR_DADDR_SHIFT (0U) +/*! DADDR - Destination Address */ +#define DMA_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_DADDR_SHIFT)) & DMA_TCD_DADDR_DADDR_MASK) +/*! @} */ + +/* The count of DMA_TCD_DADDR */ +#define DMA_TCD_DADDR_COUNT (8U) + +/*! @name TCD_DOFF - TCD Signed Destination Address Offset */ +/*! @{ */ + +#define DMA_TCD_DOFF_DOFF_MASK (0xFFFFU) +#define DMA_TCD_DOFF_DOFF_SHIFT (0U) +/*! DOFF - Destination Address Signed Offset */ +#define DMA_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_DOFF_DOFF_SHIFT)) & DMA_TCD_DOFF_DOFF_MASK) +/*! @} */ + +/* The count of DMA_TCD_DOFF */ +#define DMA_TCD_DOFF_COUNT (8U) + +/*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ +/*! @{ */ + +#define DMA_TCD_CITER_ELINKNO_CITER_MASK (0x7FFFU) +#define DMA_TCD_CITER_ELINKNO_CITER_SHIFT (0U) +/*! CITER - Current Major Iteration Count */ +#define DMA_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_CITER_ELINKNO_CITER_MASK) + +#define DMA_TCD_CITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enable Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA_TCD_CITER_ELINKNO */ +#define DMA_TCD_CITER_ELINKNO_COUNT (8U) + +/*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ +/*! @{ */ + +#define DMA_TCD_CITER_ELINKYES_CITER_MASK (0x1FFU) +#define DMA_TCD_CITER_ELINKYES_CITER_SHIFT (0U) +/*! CITER - Current Major Iteration Count */ +#define DMA_TCD_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_CITER_ELINKYES_CITER_MASK) + +#define DMA_TCD_CITER_ELINKYES_LINKCH_MASK (0xE00U) +#define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT (9U) +/*! LINKCH - Minor Loop Link Channel Number */ +#define DMA_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_CITER_ELINKYES_LINKCH_MASK) + +#define DMA_TCD_CITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA_TCD_CITER_ELINKYES */ +#define DMA_TCD_CITER_ELINKYES_COUNT (8U) + +/*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ +/*! @{ */ + +#define DMA_TCD_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) +#define DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT (0U) +/*! DLAST_SGA - Last Destination Address Adjustment / Scatter Gather Address */ +#define DMA_TCD_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_DLAST_SGA_DLAST_SGA_MASK) +/*! @} */ + +/* The count of DMA_TCD_DLAST_SGA */ +#define DMA_TCD_DLAST_SGA_COUNT (8U) + +/*! @name TCD_CSR - TCD Control and Status */ +/*! @{ */ + +#define DMA_TCD_CSR_START_MASK (0x1U) +#define DMA_TCD_CSR_START_SHIFT (0U) +/*! START - Channel Start + * 0b0..Channel not explicitly started + * 0b1..Channel explicitly started via a software-initiated service request + */ +#define DMA_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_START_SHIFT)) & DMA_TCD_CSR_START_MASK) + +#define DMA_TCD_CSR_INTMAJOR_MASK (0x2U) +#define DMA_TCD_CSR_INTMAJOR_SHIFT (1U) +/*! INTMAJOR - Enable Interrupt If Major count complete + * 0b0..End-of-major loop interrupt disabled + * 0b1..End-of-major loop interrupt enabled + */ +#define DMA_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTMAJOR_SHIFT)) & DMA_TCD_CSR_INTMAJOR_MASK) + +#define DMA_TCD_CSR_INTHALF_MASK (0x4U) +#define DMA_TCD_CSR_INTHALF_SHIFT (2U) +/*! INTHALF - Enable Interrupt If Major Counter Half-complete + * 0b0..Halfway point interrupt disabled + * 0b1..Halfway point interrupt enabled + */ +#define DMA_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTHALF_SHIFT)) & DMA_TCD_CSR_INTHALF_MASK) + +#define DMA_TCD_CSR_DREQ_MASK (0x8U) +#define DMA_TCD_CSR_DREQ_SHIFT (3U) +/*! DREQ - Disable Request + * 0b0..No operation + * 0b1..Clear the ERQ field to 0 upon major loop completion, thus disabling hardware service requests + */ +#define DMA_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK) + +#define DMA_TCD_CSR_ESG_MASK (0x10U) +#define DMA_TCD_CSR_ESG_SHIFT (4U) +/*! ESG - Enable Scatter/Gather Processing + * 0b0..Current channel's TCD is normal format + * 0b1..Current channel's TCD specifies scatter/gather format. + */ +#define DMA_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESG_SHIFT)) & DMA_TCD_CSR_ESG_MASK) + +#define DMA_TCD_CSR_MAJORELINK_MASK (0x20U) +#define DMA_TCD_CSR_MAJORELINK_SHIFT (5U) +/*! MAJORELINK - Enable Link When Major Loop Complete + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORELINK_SHIFT)) & DMA_TCD_CSR_MAJORELINK_MASK) + +#define DMA_TCD_CSR_EEOP_MASK (0x40U) +#define DMA_TCD_CSR_EEOP_SHIFT (6U) +/*! EEOP - Enable End-Of-Packet Processing + * 0b0..End-of-packet operation disabled + * 0b1..End-of-packet hardware input signal enabled + */ +#define DMA_TCD_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_EEOP_SHIFT)) & DMA_TCD_CSR_EEOP_MASK) + +#define DMA_TCD_CSR_ESDA_MASK (0x80U) +#define DMA_TCD_CSR_ESDA_SHIFT (7U) +/*! ESDA - Enable Store Destination Address + * 0b0..Ability to store destination address to system memory disabled + * 0b1..Ability to store destination address to system memory enabled + */ +#define DMA_TCD_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESDA_SHIFT)) & DMA_TCD_CSR_ESDA_MASK) + +#define DMA_TCD_CSR_MAJORLINKCH_MASK (0x700U) +#define DMA_TCD_CSR_MAJORLINKCH_SHIFT (8U) +/*! MAJORLINKCH - Major Loop Link Channel Number */ +#define DMA_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_CSR_MAJORLINKCH_MASK) + +#define DMA_TCD_CSR_BWC_MASK (0xC000U) +#define DMA_TCD_CSR_BWC_SHIFT (14U) +/*! BWC - Bandwidth Control + * 0b00..No eDMA engine stalls + * 0b01.. + * 0b10..eDMA engine stalls for 4 cycles after each R/W + * 0b11..eDMA engine stalls for 8 cycles after each R/W + */ +#define DMA_TCD_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_BWC_SHIFT)) & DMA_TCD_CSR_BWC_MASK) +/*! @} */ + +/* The count of DMA_TCD_CSR */ +#define DMA_TCD_CSR_COUNT (8U) + +/*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ +/*! @{ */ + +#define DMA_TCD_BITER_ELINKNO_BITER_MASK (0x7FFFU) +#define DMA_TCD_BITER_ELINKNO_BITER_SHIFT (0U) +/*! BITER - Starting Major Iteration Count */ +#define DMA_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_BITER_ELINKNO_BITER_MASK) + +#define DMA_TCD_BITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enables Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKNO_ELINK_MASK) +/*! @} */ + +/* The count of DMA_TCD_BITER_ELINKNO */ +#define DMA_TCD_BITER_ELINKNO_COUNT (8U) + +/*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ +/*! @{ */ + +#define DMA_TCD_BITER_ELINKYES_BITER_MASK (0x1FFU) +#define DMA_TCD_BITER_ELINKYES_BITER_SHIFT (0U) +/*! BITER - Starting Major Iteration Count */ +#define DMA_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_BITER_ELINKYES_BITER_MASK) + +#define DMA_TCD_BITER_ELINKYES_LINKCH_MASK (0xE00U) +#define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT (9U) +/*! LINKCH - Link Channel Number */ +#define DMA_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_BITER_ELINKYES_LINKCH_MASK) + +#define DMA_TCD_BITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable Link + * 0b0..Channel-to-channel linking disabled + * 0b1..Channel-to-channel linking enabled + */ +#define DMA_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKYES_ELINK_MASK) +/*! @} */ + +/* The count of DMA_TCD_BITER_ELINKYES */ +#define DMA_TCD_BITER_ELINKYES_COUNT (8U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA0 base address */ +#define DMA0_BASE (0x40080000u) +/** Peripheral DMA0 base pointer */ +#define DMA0 ((DMA_Type *)DMA0_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA0_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EIM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Peripheral_Access_Layer EIM Peripheral Access Layer + * @{ + */ + +/** EIM - Register Layout Typedef */ +typedef struct { + __IO uint32_t EIMCR; /**< Error Injection Module Configuration Register, offset: 0x0 */ + __IO uint32_t EICHEN; /**< Error Injection Channel Enable register, offset: 0x4 */ + uint8_t RESERVED_0[248]; + __IO uint32_t EICHD0_WORD0; /**< Error Injection Channel Descriptor 0, Word0, offset: 0x100 */ + __IO uint32_t EICHD0_WORD1; /**< Error Injection Channel Descriptor 0, Word1, offset: 0x104 */ +} EIM_Type; + +/* ---------------------------------------------------------------------------- + -- EIM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Register_Masks EIM Register Masks + * @{ + */ + +/*! @name EIMCR - Error Injection Module Configuration Register */ +/*! @{ */ + +#define EIM_EIMCR_GEIEN_MASK (0x1U) +#define EIM_EIMCR_GEIEN_SHIFT (0U) +/*! GEIEN - Global Error Injection Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EIM_EIMCR_GEIEN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EIMCR_GEIEN_SHIFT)) & EIM_EIMCR_GEIEN_MASK) +/*! @} */ + +/*! @name EICHEN - Error Injection Channel Enable register */ +/*! @{ */ + +#define EIM_EICHEN_EICH0EN_MASK (0x80000000U) +#define EIM_EICHEN_EICH0EN_SHIFT (31U) +/*! EICH0EN - Error Injection Channel 0 Enable + * 0b0..Error injection is disabled on Error Injection Channel 0 + * 0b1..Error injection is enabled on Error Injection Channel 0 + */ +#define EIM_EICHEN_EICH0EN(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHEN_EICH0EN_SHIFT)) & EIM_EICHEN_EICH0EN_MASK) +/*! @} */ + +/*! @name EICHD0_WORD0 - Error Injection Channel Descriptor 0, Word0 */ +/*! @{ */ + +#define EIM_EICHD0_WORD0_CHKBIT_MASK_MASK (0xFE000000U) +#define EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT (25U) +/*! CHKBIT_MASK - Checkbit Mask */ +#define EIM_EICHD0_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT)) & EIM_EICHD0_WORD0_CHKBIT_MASK_MASK) +/*! @} */ + +/*! @name EICHD0_WORD1 - Error Injection Channel Descriptor 0, Word1 */ +/*! @{ */ + +#define EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK (0xFFFFFFFFU) +#define EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT (0U) +/*! B0_3DATA_MASK - Data Mask Bytes 0-3 */ +#define EIM_EICHD0_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x)) << EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT)) & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group EIM_Register_Masks */ + + +/* EIM - Peripheral instance base addresses */ +/** Peripheral EIM0 base address */ +#define EIM0_BASE (0x4008C000u) +/** Peripheral EIM0 base pointer */ +#define EIM0 ((EIM_Type *)EIM0_BASE) +/** Array initializer of EIM peripheral base addresses */ +#define EIM_BASE_ADDRS { EIM0_BASE } +/** Array initializer of EIM peripheral base pointers */ +#define EIM_BASE_PTRS { EIM0 } + +/*! + * @} + */ /* end of group EIM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- EQDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EQDC_Peripheral_Access_Layer EQDC Peripheral Access Layer + * @{ + */ + +/** EQDC - Register Layout Typedef */ +typedef struct { + __IO uint16_t CTRL; /**< Control Register, offset: 0x0 */ + __IO uint16_t CTRL2; /**< Control 2 Register, offset: 0x2 */ + __IO uint16_t FILT; /**< Input Filter Register, offset: 0x4 */ + __I uint16_t LASTEDGE; /**< Last Edge Time Register, offset: 0x6 */ + __I uint16_t POSDPER; /**< Position Difference Period Counter Register, offset: 0x8 */ + __I uint16_t POSDPERBFR; /**< Position Difference Period Buffer Register, offset: 0xA */ + __IO uint16_t UPOS; /**< Upper Position Counter Register, offset: 0xC */ + __IO uint16_t LPOS; /**< Lower Position Counter Register, offset: 0xE */ + __IO uint16_t POSD; /**< Position Difference Counter Register, offset: 0x10 */ + __I uint16_t POSDH; /**< Position Difference Hold Register, offset: 0x12 */ + __I uint16_t UPOSH; /**< Upper Position Hold Register, offset: 0x14 */ + __I uint16_t LPOSH; /**< Lower Position Hold Register, offset: 0x16 */ + __I uint16_t LASTEDGEH; /**< Last Edge Time Hold Register, offset: 0x18 */ + __I uint16_t POSDPERH; /**< Position Difference Period Hold Register, offset: 0x1A */ + __I uint16_t REVH; /**< Revolution Hold Register, offset: 0x1C */ + __IO uint16_t REV; /**< Revolution Counter Register, offset: 0x1E */ + __IO uint16_t UINIT; /**< Upper Initialization Register, offset: 0x20 */ + __IO uint16_t LINIT; /**< Lower Initialization Register, offset: 0x22 */ + __IO uint16_t UMOD; /**< Upper Modulus Register, offset: 0x24 */ + __IO uint16_t LMOD; /**< Lower Modulus Register, offset: 0x26 */ + __IO uint16_t UCOMP0; /**< Upper Position Compare Register 0, offset: 0x28 */ + __IO uint16_t LCOMP0; /**< Lower Position Compare Register 0, offset: 0x2A */ + union { /* offset: 0x2C */ + __O uint16_t UCOMP1; /**< Upper Position Compare 1, offset: 0x2C */ + __I uint16_t UPOSH1; /**< Upper Position Holder Register 1, offset: 0x2C */ + }; + union { /* offset: 0x2E */ + __O uint16_t LCOMP1; /**< Lower Position Compare 1, offset: 0x2E */ + __I uint16_t LPOSH1; /**< Lower Position Holder Register 1, offset: 0x2E */ + }; + union { /* offset: 0x30 */ + __O uint16_t UCOMP2; /**< Upper Position Compare 2, offset: 0x30 */ + __I uint16_t UPOSH2; /**< Upper Position Holder Register 3, offset: 0x30 */ + }; + union { /* offset: 0x32 */ + __O uint16_t LCOMP2; /**< Lower Position Compare 2, offset: 0x32 */ + __I uint16_t LPOSH2; /**< Lower Position Holder Register 2, offset: 0x32 */ + }; + union { /* offset: 0x34 */ + __O uint16_t UCOMP3; /**< Upper Position Compare 3, offset: 0x34 */ + __I uint16_t UPOSH3; /**< Upper Position Holder Register 3, offset: 0x34 */ + }; + union { /* offset: 0x36 */ + __O uint16_t LCOMP3; /**< Lower Position Compare 3, offset: 0x36 */ + __I uint16_t LPOSH3; /**< Lower Position Holder Register 3, offset: 0x36 */ + }; + __IO uint16_t INTCTRL; /**< Interrupt Control Register, offset: 0x38 */ + __IO uint16_t WTR; /**< Watchdog Timeout Register, offset: 0x3A */ + __IO uint16_t IMR; /**< Input Monitor Register, offset: 0x3C */ + __IO uint16_t TST; /**< Test Register, offset: 0x3E */ + uint8_t RESERVED_0[16]; + __I uint16_t UVERID; /**< Upper VERID, offset: 0x50 */ + __I uint16_t LVERID; /**< Lower VERID, offset: 0x52 */ +} EQDC_Type; + +/* ---------------------------------------------------------------------------- + -- EQDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EQDC_Register_Masks EQDC Register Masks + * @{ + */ + +/*! @name CTRL - Control Register */ +/*! @{ */ + +#define EQDC_CTRL_LDOK_MASK (0x1U) +#define EQDC_CTRL_LDOK_SHIFT (0U) +/*! LDOK - Load Okay + * 0b0..No loading action taken. Users can write new values to buffered registers (writing into outer-set of these buffered registers) + * 0b1..Outer-set values are ready to be loaded into inner-set and take effect. The loading time point depends on CTRL2[LDMOD]. + */ +#define EQDC_CTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_LDOK_SHIFT)) & EQDC_CTRL_LDOK_MASK) + +#define EQDC_CTRL_DMAEN_MASK (0x2U) +#define EQDC_CTRL_DMAEN_SHIFT (1U) +/*! DMAEN - DMA Enable + * 0b0..DMA is disabled + * 0b1..DMA is enabled. DMA request asserts automatically when the values in the outer-set of buffered compare + * registers (UCOMP0/LCOMP0;UCOMP1/LCOMP1;UCOMP2/LCOMP2;UCOMP3/LCOMP3), initial registers(UINIT/LINIT) and + * modulus registers (UMOD/LMOD) are loaded into the inner-set of buffer and then LDOK is cleared automatically. + * After the completion of this DMA transfer, LDOK is set automatically, it ensures outer-set values can be + * loaded into inner-set which in turn triggers DMA again. + */ +#define EQDC_CTRL_DMAEN(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_DMAEN_SHIFT)) & EQDC_CTRL_DMAEN_MASK) + +#define EQDC_CTRL_WDE_MASK (0x4U) +#define EQDC_CTRL_WDE_SHIFT (2U) +/*! WDE - Watchdog Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_WDE_SHIFT)) & EQDC_CTRL_WDE_MASK) + +#define EQDC_CTRL_WDIE_MASK (0x8U) +#define EQDC_CTRL_WDIE_SHIFT (3U) +/*! WDIE - Watchdog Timeout Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_CTRL_WDIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_WDIE_SHIFT)) & EQDC_CTRL_WDIE_MASK) + +#define EQDC_CTRL_WDIRQ_MASK (0x10U) +#define EQDC_CTRL_WDIRQ_SHIFT (4U) +/*! WDIRQ - Watchdog Timeout Interrupt Request + * 0b0..No Watchdog timeout interrupt has occurred + * 0b1..Watchdog timeout interrupt has occurred + */ +#define EQDC_CTRL_WDIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_WDIRQ_SHIFT)) & EQDC_CTRL_WDIRQ_MASK) + +#define EQDC_CTRL_XNE_MASK (0x20U) +#define EQDC_CTRL_XNE_SHIFT (5U) +/*! XNE - Select Positive/Negative Edge of INDEX/PRESET Pulse + * 0b0..Use positive edge of INDEX/PRESET pulse + * 0b1..Use negative edge of INDEX/PRESET pulse + */ +#define EQDC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_XNE_SHIFT)) & EQDC_CTRL_XNE_MASK) + +#define EQDC_CTRL_XIP_MASK (0x40U) +#define EQDC_CTRL_XIP_SHIFT (6U) +/*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..INDEX pulse does not initialize the position counter + * 0b1..INDEX pulse initializes the position counter + */ +#define EQDC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_XIP_SHIFT)) & EQDC_CTRL_XIP_MASK) + +#define EQDC_CTRL_XIE_MASK (0x80U) +#define EQDC_CTRL_XIE_SHIFT (7U) +/*! XIE - INDEX/PRESET Pulse Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_XIE_SHIFT)) & EQDC_CTRL_XIE_MASK) + +#define EQDC_CTRL_XIRQ_MASK (0x100U) +#define EQDC_CTRL_XIRQ_SHIFT (8U) +/*! XIRQ - INDEX/PRESET Pulse Interrupt Request + * 0b0..INDEX/PRESET pulse has not occurred + * 0b1..INDEX/PRESET pulse has occurred + */ +#define EQDC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_XIRQ_SHIFT)) & EQDC_CTRL_XIRQ_MASK) + +#define EQDC_CTRL_PH1_MASK (0x200U) +#define EQDC_CTRL_PH1_SHIFT (9U) +/*! PH1 - Enable Single Phase Mode + * 0b0..Standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal. + * 0b1..Single phase mode, bypass the quadrature decoder, refer to CTRL2[CMODE] description + */ +#define EQDC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_PH1_SHIFT)) & EQDC_CTRL_PH1_MASK) + +#define EQDC_CTRL_REV_MASK (0x400U) +#define EQDC_CTRL_REV_SHIFT (10U) +/*! REV - Enable Reverse Direction Counting + * 0b0..Count normally and the position counter initialization uses upper/lower initialization register UINIT/LINIT + * 0b1..Count in the reverse direction and the position counter initialization uses upper/lower modulus register UMOD/LMOD + */ +#define EQDC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_REV_SHIFT)) & EQDC_CTRL_REV_MASK) + +#define EQDC_CTRL_SWIP_MASK (0x800U) +#define EQDC_CTRL_SWIP_SHIFT (11U) +/*! SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS + * 0b0..No action + * 0b1..Initialize position counter + */ +#define EQDC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_SWIP_SHIFT)) & EQDC_CTRL_SWIP_MASK) + +#define EQDC_CTRL_HNE_MASK (0x1000U) +#define EQDC_CTRL_HNE_SHIFT (12U) +/*! HNE - Use Negative Edge of HOME/ENABLE Input + * 0b0..When CTRL[OPMODE] = 0,use HOME positive edge to trigger initialization of position counters. When + * CTRL[OPMODE] = 1,use ENABLE high level to enable POS/POSD/WDG/REV counters + * 0b1..When CTRL[OPMODE] = 0,use HOME negative edge to trigger initialization of position counters. When + * CTRL[OPMODE] = 1,use ENABLE low level to enable POS/POSD/WDG/REV counters + */ +#define EQDC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_HNE_SHIFT)) & EQDC_CTRL_HNE_MASK) + +#define EQDC_CTRL_HIP_MASK (0x2000U) +#define EQDC_CTRL_HIP_SHIFT (13U) +/*! HIP - Enable HOME to Initialize Position Counter UPOS/LPOS + * 0b0..No action + * 0b1..HOME signal initializes the position counter + */ +#define EQDC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_HIP_SHIFT)) & EQDC_CTRL_HIP_MASK) + +#define EQDC_CTRL_HIE_MASK (0x4000U) +#define EQDC_CTRL_HIE_SHIFT (14U) +/*! HIE - HOME/ENABLE Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_HIE_SHIFT)) & EQDC_CTRL_HIE_MASK) + +#define EQDC_CTRL_HIRQ_MASK (0x8000U) +#define EQDC_CTRL_HIRQ_SHIFT (15U) +/*! HIRQ - HOME/ENABLE Signal Transition Interrupt Request + * 0b0..No transition on the HOME/ENABLE signal has occurred + * 0b1..A transition on the HOME/ENABLE signal has occurred + */ +#define EQDC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL_HIRQ_SHIFT)) & EQDC_CTRL_HIRQ_MASK) +/*! @} */ + +/*! @name CTRL2 - Control 2 Register */ +/*! @{ */ + +#define EQDC_CTRL2_UPDHLD_MASK (0x1U) +#define EQDC_CTRL2_UPDHLD_SHIFT (0U) +/*! UPDHLD - Update Hold Registers */ +#define EQDC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_UPDHLD_SHIFT)) & EQDC_CTRL2_UPDHLD_MASK) + +#define EQDC_CTRL2_UPDPOS_MASK (0x2U) +#define EQDC_CTRL2_UPDPOS_SHIFT (1U) +/*! UPDPOS - Update Position Registers */ +#define EQDC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_UPDPOS_SHIFT)) & EQDC_CTRL2_UPDPOS_MASK) + +#define EQDC_CTRL2_OPMODE_MASK (0x4U) +#define EQDC_CTRL2_OPMODE_SHIFT (2U) +/*! OPMODE - Operation Mode Select + * 0b0..Decode Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to function of INDEX and HOME. + * 0b1..Count Mode: Input nodes INDEX/PRESET and HOME/ENABLE are assigned to functions of PRESET and ENABLE. In + * this mode: (1)only when ENABLE=1, all counters (position/position difference/revolution/watchdog) can run, + * when ENABLE=0, all counters (position/position difference/revolution/watchdog) can't run. (2) the rising + * edge of PRESET input can initialize position/revolution/watchdog counters (position counter initialization + * also need referring to bit CTRL[REV]). + */ +#define EQDC_CTRL2_OPMODE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_OPMODE_SHIFT)) & EQDC_CTRL2_OPMODE_MASK) + +#define EQDC_CTRL2_LDMOD_MASK (0x8U) +#define EQDC_CTRL2_LDMOD_SHIFT (3U) +/*! LDMOD - Buffered Register Load (Update) Mode Select + * 0b0..Buffered registers are loaded and take effect immediately upon CTRL[LDOK] is set. + * 0b1..Buffered registers are loaded and take effect at the next roll-over or roll-under if CTRL[LDOK] is set. + */ +#define EQDC_CTRL2_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_LDMOD_SHIFT)) & EQDC_CTRL2_LDMOD_MASK) + +#define EQDC_CTRL2_REVMOD_MASK (0x100U) +#define EQDC_CTRL2_REVMOD_SHIFT (8U) +/*! REVMOD - Revolution Counter Modulus Enable + * 0b0..Use INDEX pulse to increment/decrement revolution counter (REV) + * 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV) + */ +#define EQDC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_REVMOD_SHIFT)) & EQDC_CTRL2_REVMOD_MASK) + +#define EQDC_CTRL2_OUTCTL_MASK (0x200U) +#define EQDC_CTRL2_OUTCTL_SHIFT (9U) +/*! OUTCTL - Output Control + * 0b0..POS_MATCH[x](x range is 0-3) is asserted when the Position Counter is equal to according compare value + * (UCOMPx/LCOMPx)(x range is 0-3), and de-asserted when the Position Counter not equal to the compare value + * (UCOMPx/LCOMPx)(x range is 0-3) + * 0b1..All POS_MATCH[x](x range is 0-3) are asserted a pulse, when the UPOS, LPOS, REV, or POSD registers are read + */ +#define EQDC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_OUTCTL_SHIFT)) & EQDC_CTRL2_OUTCTL_MASK) + +#define EQDC_CTRL2_PMEN_MASK (0x400U) +#define EQDC_CTRL2_PMEN_SHIFT (10U) +/*! PMEN - Period measurement function enable + * 0b0..Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS or REV is read. + * 0b1..Period measurement functions are used. POSD is loaded into POSDH and then cleared only when POSD is read. + */ +#define EQDC_CTRL2_PMEN(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_PMEN_SHIFT)) & EQDC_CTRL2_PMEN_MASK) + +#define EQDC_CTRL2_EMIP_MASK (0x800U) +#define EQDC_CTRL2_EMIP_SHIFT (11U) +/*! EMIP - Enables/disables the position counter to be initialized by Index Event Edge Mark + * 0b0..disables the position counter to be initialized by Index Event Edge Mark + * 0b1..enables the position counter to be initialized by Index Event Edge Mark. + */ +#define EQDC_CTRL2_EMIP(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_EMIP_SHIFT)) & EQDC_CTRL2_EMIP_MASK) + +#define EQDC_CTRL2_INITPOS_MASK (0x1000U) +#define EQDC_CTRL2_INITPOS_SHIFT (12U) +/*! INITPOS - Initial Position Register + * 0b0..Don't initialize position counter on rising edge of TRIGGER + * 0b1..Initialize position counter on rising edge of TRIGGER + */ +#define EQDC_CTRL2_INITPOS(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_INITPOS_SHIFT)) & EQDC_CTRL2_INITPOS_MASK) + +#define EQDC_CTRL2_ONCE_MASK (0x2000U) +#define EQDC_CTRL2_ONCE_SHIFT (13U) +/*! ONCE - Count Once + * 0b0..Position counter counts repeatedly + * 0b1..Position counter counts until roll-over or roll-under, then stop. + */ +#define EQDC_CTRL2_ONCE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_ONCE_SHIFT)) & EQDC_CTRL2_ONCE_MASK) + +#define EQDC_CTRL2_CMODE_MASK (0xC000U) +#define EQDC_CTRL2_CMODE_SHIFT (14U) +/*! CMODE - Counting Mode */ +#define EQDC_CTRL2_CMODE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_CTRL2_CMODE_SHIFT)) & EQDC_CTRL2_CMODE_MASK) +/*! @} */ + +/*! @name FILT - Input Filter Register */ +/*! @{ */ + +#define EQDC_FILT_FILT_PER_MASK (0xFFU) +#define EQDC_FILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Input Filter Sample Period */ +#define EQDC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << EQDC_FILT_FILT_PER_SHIFT)) & EQDC_FILT_FILT_PER_MASK) + +#define EQDC_FILT_FILT_CNT_MASK (0x700U) +#define EQDC_FILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Input Filter Sample Count */ +#define EQDC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << EQDC_FILT_FILT_CNT_SHIFT)) & EQDC_FILT_FILT_CNT_MASK) + +#define EQDC_FILT_FILT_CS_MASK (0x800U) +#define EQDC_FILT_FILT_CS_SHIFT (11U) +/*! FILT_CS - Filter Clock Source selection + * 0b0..Peripheral Clock + * 0b1..Prescaled peripheral clock by PRSC + */ +#define EQDC_FILT_FILT_CS(x) (((uint16_t)(((uint16_t)(x)) << EQDC_FILT_FILT_CS_SHIFT)) & EQDC_FILT_FILT_CS_MASK) + +#define EQDC_FILT_PRSC_MASK (0xF000U) +#define EQDC_FILT_PRSC_SHIFT (12U) +/*! PRSC - Prescaler */ +#define EQDC_FILT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << EQDC_FILT_PRSC_SHIFT)) & EQDC_FILT_PRSC_MASK) +/*! @} */ + +/*! @name LASTEDGE - Last Edge Time Register */ +/*! @{ */ + +#define EQDC_LASTEDGE_LASTEDGE_MASK (0xFFFFU) +#define EQDC_LASTEDGE_LASTEDGE_SHIFT (0U) +/*! LASTEDGE - Last Edge Time Counter */ +#define EQDC_LASTEDGE_LASTEDGE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LASTEDGE_LASTEDGE_SHIFT)) & EQDC_LASTEDGE_LASTEDGE_MASK) +/*! @} */ + +/*! @name POSDPER - Position Difference Period Counter Register */ +/*! @{ */ + +#define EQDC_POSDPER_POSDPER_MASK (0xFFFFU) +#define EQDC_POSDPER_POSDPER_SHIFT (0U) +/*! POSDPER - Position difference period */ +#define EQDC_POSDPER_POSDPER(x) (((uint16_t)(((uint16_t)(x)) << EQDC_POSDPER_POSDPER_SHIFT)) & EQDC_POSDPER_POSDPER_MASK) +/*! @} */ + +/*! @name POSDPERBFR - Position Difference Period Buffer Register */ +/*! @{ */ + +#define EQDC_POSDPERBFR_POSDPERBFR_MASK (0xFFFFU) +#define EQDC_POSDPERBFR_POSDPERBFR_SHIFT (0U) +/*! POSDPERBFR - Position difference period buffer */ +#define EQDC_POSDPERBFR_POSDPERBFR(x) (((uint16_t)(((uint16_t)(x)) << EQDC_POSDPERBFR_POSDPERBFR_SHIFT)) & EQDC_POSDPERBFR_POSDPERBFR_MASK) +/*! @} */ + +/*! @name UPOS - Upper Position Counter Register */ +/*! @{ */ + +#define EQDC_UPOS_POS_MASK (0xFFFFU) +#define EQDC_UPOS_POS_SHIFT (0U) +/*! POS - POS */ +#define EQDC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UPOS_POS_SHIFT)) & EQDC_UPOS_POS_MASK) +/*! @} */ + +/*! @name LPOS - Lower Position Counter Register */ +/*! @{ */ + +#define EQDC_LPOS_POS_MASK (0xFFFFU) +#define EQDC_LPOS_POS_SHIFT (0U) +/*! POS - POS */ +#define EQDC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LPOS_POS_SHIFT)) & EQDC_LPOS_POS_MASK) +/*! @} */ + +/*! @name POSD - Position Difference Counter Register */ +/*! @{ */ + +#define EQDC_POSD_POSD_MASK (0xFFFFU) +#define EQDC_POSD_POSD_SHIFT (0U) +/*! POSD - POSD */ +#define EQDC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_POSD_POSD_SHIFT)) & EQDC_POSD_POSD_MASK) +/*! @} */ + +/*! @name POSDH - Position Difference Hold Register */ +/*! @{ */ + +#define EQDC_POSDH_POSDH_MASK (0xFFFFU) +#define EQDC_POSDH_POSDH_SHIFT (0U) +/*! POSDH - POSDH */ +#define EQDC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_POSDH_POSDH_SHIFT)) & EQDC_POSDH_POSDH_MASK) +/*! @} */ + +/*! @name UPOSH - Upper Position Hold Register */ +/*! @{ */ + +#define EQDC_UPOSH_POSH_MASK (0xFFFFU) +#define EQDC_UPOSH_POSH_SHIFT (0U) +/*! POSH - POSH */ +#define EQDC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UPOSH_POSH_SHIFT)) & EQDC_UPOSH_POSH_MASK) +/*! @} */ + +/*! @name LPOSH - Lower Position Hold Register */ +/*! @{ */ + +#define EQDC_LPOSH_LPOSH_MASK (0xFFFFU) +#define EQDC_LPOSH_LPOSH_SHIFT (0U) +/*! LPOSH - POSH */ +#define EQDC_LPOSH_LPOSH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LPOSH_LPOSH_SHIFT)) & EQDC_LPOSH_LPOSH_MASK) +/*! @} */ + +/*! @name LASTEDGEH - Last Edge Time Hold Register */ +/*! @{ */ + +#define EQDC_LASTEDGEH_LASTEDGEH_MASK (0xFFFFU) +#define EQDC_LASTEDGEH_LASTEDGEH_SHIFT (0U) +/*! LASTEDGEH - Last Edge Time Hold */ +#define EQDC_LASTEDGEH_LASTEDGEH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LASTEDGEH_LASTEDGEH_SHIFT)) & EQDC_LASTEDGEH_LASTEDGEH_MASK) +/*! @} */ + +/*! @name POSDPERH - Position Difference Period Hold Register */ +/*! @{ */ + +#define EQDC_POSDPERH_POSDPERH_MASK (0xFFFFU) +#define EQDC_POSDPERH_POSDPERH_SHIFT (0U) +/*! POSDPERH - Position difference period hold */ +#define EQDC_POSDPERH_POSDPERH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_POSDPERH_POSDPERH_SHIFT)) & EQDC_POSDPERH_POSDPERH_MASK) +/*! @} */ + +/*! @name REVH - Revolution Hold Register */ +/*! @{ */ + +#define EQDC_REVH_REVH_MASK (0xFFFFU) +#define EQDC_REVH_REVH_SHIFT (0U) +/*! REVH - REVH */ +#define EQDC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_REVH_REVH_SHIFT)) & EQDC_REVH_REVH_MASK) +/*! @} */ + +/*! @name REV - Revolution Counter Register */ +/*! @{ */ + +#define EQDC_REV_REV_MASK (0xFFFFU) +#define EQDC_REV_REV_SHIFT (0U) +/*! REV - REV */ +#define EQDC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << EQDC_REV_REV_SHIFT)) & EQDC_REV_REV_MASK) +/*! @} */ + +/*! @name UINIT - Upper Initialization Register */ +/*! @{ */ + +#define EQDC_UINIT_INIT_MASK (0xFFFFU) +#define EQDC_UINIT_INIT_SHIFT (0U) +/*! INIT - INIT */ +#define EQDC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UINIT_INIT_SHIFT)) & EQDC_UINIT_INIT_MASK) +/*! @} */ + +/*! @name LINIT - Lower Initialization Register */ +/*! @{ */ + +#define EQDC_LINIT_INIT_MASK (0xFFFFU) +#define EQDC_LINIT_INIT_SHIFT (0U) +/*! INIT - INIT */ +#define EQDC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LINIT_INIT_SHIFT)) & EQDC_LINIT_INIT_MASK) +/*! @} */ + +/*! @name UMOD - Upper Modulus Register */ +/*! @{ */ + +#define EQDC_UMOD_MOD_MASK (0xFFFFU) +#define EQDC_UMOD_MOD_SHIFT (0U) +/*! MOD - MOD */ +#define EQDC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UMOD_MOD_SHIFT)) & EQDC_UMOD_MOD_MASK) +/*! @} */ + +/*! @name LMOD - Lower Modulus Register */ +/*! @{ */ + +#define EQDC_LMOD_MOD_MASK (0xFFFFU) +#define EQDC_LMOD_MOD_SHIFT (0U) +/*! MOD - MOD */ +#define EQDC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LMOD_MOD_SHIFT)) & EQDC_LMOD_MOD_MASK) +/*! @} */ + +/*! @name UCOMP0 - Upper Position Compare Register 0 */ +/*! @{ */ + +#define EQDC_UCOMP0_UCOMP0_MASK (0xFFFFU) +#define EQDC_UCOMP0_UCOMP0_SHIFT (0U) +/*! UCOMP0 - UCOMP0 */ +#define EQDC_UCOMP0_UCOMP0(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UCOMP0_UCOMP0_SHIFT)) & EQDC_UCOMP0_UCOMP0_MASK) +/*! @} */ + +/*! @name LCOMP0 - Lower Position Compare Register 0 */ +/*! @{ */ + +#define EQDC_LCOMP0_LCOMP0_MASK (0xFFFFU) +#define EQDC_LCOMP0_LCOMP0_SHIFT (0U) +/*! LCOMP0 - LCOMP0 */ +#define EQDC_LCOMP0_LCOMP0(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LCOMP0_LCOMP0_SHIFT)) & EQDC_LCOMP0_LCOMP0_MASK) +/*! @} */ + +/*! @name UCOMP1 - Upper Position Compare 1 */ +/*! @{ */ + +#define EQDC_UCOMP1_UCOMP1_MASK (0xFFFFU) +#define EQDC_UCOMP1_UCOMP1_SHIFT (0U) +/*! UCOMP1 - UCOMP1 */ +#define EQDC_UCOMP1_UCOMP1(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UCOMP1_UCOMP1_SHIFT)) & EQDC_UCOMP1_UCOMP1_MASK) +/*! @} */ + +/*! @name UPOSH1 - Upper Position Holder Register 1 */ +/*! @{ */ + +#define EQDC_UPOSH1_UPOSH1_MASK (0xFFFFU) +#define EQDC_UPOSH1_UPOSH1_SHIFT (0U) +/*! UPOSH1 - UPOSH1 */ +#define EQDC_UPOSH1_UPOSH1(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UPOSH1_UPOSH1_SHIFT)) & EQDC_UPOSH1_UPOSH1_MASK) +/*! @} */ + +/*! @name LCOMP1 - Lower Position Compare 1 */ +/*! @{ */ + +#define EQDC_LCOMP1_LCOMP1_MASK (0xFFFFU) +#define EQDC_LCOMP1_LCOMP1_SHIFT (0U) +/*! LCOMP1 - LCOMP1 */ +#define EQDC_LCOMP1_LCOMP1(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LCOMP1_LCOMP1_SHIFT)) & EQDC_LCOMP1_LCOMP1_MASK) +/*! @} */ + +/*! @name LPOSH1 - Lower Position Holder Register 1 */ +/*! @{ */ + +#define EQDC_LPOSH1_LPOSH1_MASK (0xFFFFU) +#define EQDC_LPOSH1_LPOSH1_SHIFT (0U) +/*! LPOSH1 - LPOSH1 */ +#define EQDC_LPOSH1_LPOSH1(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LPOSH1_LPOSH1_SHIFT)) & EQDC_LPOSH1_LPOSH1_MASK) +/*! @} */ + +/*! @name UCOMP2 - Upper Position Compare 2 */ +/*! @{ */ + +#define EQDC_UCOMP2_UCOMP2_MASK (0xFFFFU) +#define EQDC_UCOMP2_UCOMP2_SHIFT (0U) +/*! UCOMP2 - UCOMP2 */ +#define EQDC_UCOMP2_UCOMP2(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UCOMP2_UCOMP2_SHIFT)) & EQDC_UCOMP2_UCOMP2_MASK) +/*! @} */ + +/*! @name UPOSH2 - Upper Position Holder Register 3 */ +/*! @{ */ + +#define EQDC_UPOSH2_UPOSH2_MASK (0xFFFFU) +#define EQDC_UPOSH2_UPOSH2_SHIFT (0U) +/*! UPOSH2 - UPOSH2 */ +#define EQDC_UPOSH2_UPOSH2(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UPOSH2_UPOSH2_SHIFT)) & EQDC_UPOSH2_UPOSH2_MASK) +/*! @} */ + +/*! @name LCOMP2 - Lower Position Compare 2 */ +/*! @{ */ + +#define EQDC_LCOMP2_LCOMP2_MASK (0xFFFFU) +#define EQDC_LCOMP2_LCOMP2_SHIFT (0U) +/*! LCOMP2 - LCOMP2 */ +#define EQDC_LCOMP2_LCOMP2(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LCOMP2_LCOMP2_SHIFT)) & EQDC_LCOMP2_LCOMP2_MASK) +/*! @} */ + +/*! @name LPOSH2 - Lower Position Holder Register 2 */ +/*! @{ */ + +#define EQDC_LPOSH2_LPOSH2_MASK (0xFFFFU) +#define EQDC_LPOSH2_LPOSH2_SHIFT (0U) +/*! LPOSH2 - LPOSH2 */ +#define EQDC_LPOSH2_LPOSH2(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LPOSH2_LPOSH2_SHIFT)) & EQDC_LPOSH2_LPOSH2_MASK) +/*! @} */ + +/*! @name UCOMP3 - Upper Position Compare 3 */ +/*! @{ */ + +#define EQDC_UCOMP3_UCOMP3_MASK (0xFFFFU) +#define EQDC_UCOMP3_UCOMP3_SHIFT (0U) +/*! UCOMP3 - UCOMP3 */ +#define EQDC_UCOMP3_UCOMP3(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UCOMP3_UCOMP3_SHIFT)) & EQDC_UCOMP3_UCOMP3_MASK) +/*! @} */ + +/*! @name UPOSH3 - Upper Position Holder Register 3 */ +/*! @{ */ + +#define EQDC_UPOSH3_UPOSH3_MASK (0xFFFFU) +#define EQDC_UPOSH3_UPOSH3_SHIFT (0U) +/*! UPOSH3 - UPOSH3 */ +#define EQDC_UPOSH3_UPOSH3(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UPOSH3_UPOSH3_SHIFT)) & EQDC_UPOSH3_UPOSH3_MASK) +/*! @} */ + +/*! @name LCOMP3 - Lower Position Compare 3 */ +/*! @{ */ + +#define EQDC_LCOMP3_LCOMP3_MASK (0xFFFFU) +#define EQDC_LCOMP3_LCOMP3_SHIFT (0U) +/*! LCOMP3 - LCOMP3 */ +#define EQDC_LCOMP3_LCOMP3(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LCOMP3_LCOMP3_SHIFT)) & EQDC_LCOMP3_LCOMP3_MASK) +/*! @} */ + +/*! @name LPOSH3 - Lower Position Holder Register 3 */ +/*! @{ */ + +#define EQDC_LPOSH3_LPOSH3_MASK (0xFFFFU) +#define EQDC_LPOSH3_LPOSH3_SHIFT (0U) +/*! LPOSH3 - LPOSH3 */ +#define EQDC_LPOSH3_LPOSH3(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LPOSH3_LPOSH3_SHIFT)) & EQDC_LPOSH3_LPOSH3_MASK) +/*! @} */ + +/*! @name INTCTRL - Interrupt Control Register */ +/*! @{ */ + +#define EQDC_INTCTRL_SABIE_MASK (0x1U) +#define EQDC_INTCTRL_SABIE_SHIFT (0U) +/*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_INTCTRL_SABIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_SABIE_SHIFT)) & EQDC_INTCTRL_SABIE_MASK) + +#define EQDC_INTCTRL_SABIRQ_MASK (0x2U) +#define EQDC_INTCTRL_SABIRQ_SHIFT (1U) +/*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request + * 0b0..No simultaneous change of PHASEA and PHASEB has occurred + * 0b1..A simultaneous change of PHASEA and PHASEB has occurred + */ +#define EQDC_INTCTRL_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_SABIRQ_SHIFT)) & EQDC_INTCTRL_SABIRQ_MASK) + +#define EQDC_INTCTRL_DIRIE_MASK (0x4U) +#define EQDC_INTCTRL_DIRIE_SHIFT (2U) +/*! DIRIE - Count direction change interrupt enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_INTCTRL_DIRIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_DIRIE_SHIFT)) & EQDC_INTCTRL_DIRIE_MASK) + +#define EQDC_INTCTRL_DIRIRQ_MASK (0x8U) +#define EQDC_INTCTRL_DIRIRQ_SHIFT (3U) +/*! DIRIRQ - Count direction change interrupt + * 0b0..Count direction unchanged + * 0b1..Count direction changed + */ +#define EQDC_INTCTRL_DIRIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_DIRIRQ_SHIFT)) & EQDC_INTCTRL_DIRIRQ_MASK) + +#define EQDC_INTCTRL_RUIE_MASK (0x10U) +#define EQDC_INTCTRL_RUIE_SHIFT (4U) +/*! RUIE - Roll-under Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_INTCTRL_RUIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_RUIE_SHIFT)) & EQDC_INTCTRL_RUIE_MASK) + +#define EQDC_INTCTRL_RUIRQ_MASK (0x20U) +#define EQDC_INTCTRL_RUIRQ_SHIFT (5U) +/*! RUIRQ - Roll-under Interrupt Request + * 0b0..No roll-under has occurred + * 0b1..Roll-under has occurred + */ +#define EQDC_INTCTRL_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_RUIRQ_SHIFT)) & EQDC_INTCTRL_RUIRQ_MASK) + +#define EQDC_INTCTRL_ROIE_MASK (0x40U) +#define EQDC_INTCTRL_ROIE_SHIFT (6U) +/*! ROIE - Roll-over Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_INTCTRL_ROIE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_ROIE_SHIFT)) & EQDC_INTCTRL_ROIE_MASK) + +#define EQDC_INTCTRL_ROIRQ_MASK (0x80U) +#define EQDC_INTCTRL_ROIRQ_SHIFT (7U) +/*! ROIRQ - Roll-over Interrupt Request + * 0b0..No roll-over has occurred + * 0b1..Roll-over has occurred + */ +#define EQDC_INTCTRL_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_ROIRQ_SHIFT)) & EQDC_INTCTRL_ROIRQ_MASK) + +#define EQDC_INTCTRL_CMP0IE_MASK (0x100U) +#define EQDC_INTCTRL_CMP0IE_SHIFT (8U) +/*! CMP0IE - Compare 0 Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_INTCTRL_CMP0IE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP0IE_SHIFT)) & EQDC_INTCTRL_CMP0IE_MASK) + +#define EQDC_INTCTRL_CMP0IRQ_MASK (0x200U) +#define EQDC_INTCTRL_CMP0IRQ_SHIFT (9U) +/*! CMP0IRQ - Compare 0 Interrupt Request + * 0b0..No match has occurred (the position counter does not match the COMP0 value) + * 0b1..COMP match has occurred (the position counter matches the COMP0 value) + */ +#define EQDC_INTCTRL_CMP0IRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP0IRQ_SHIFT)) & EQDC_INTCTRL_CMP0IRQ_MASK) + +#define EQDC_INTCTRL_CMP1IE_MASK (0x400U) +#define EQDC_INTCTRL_CMP1IE_SHIFT (10U) +/*! CMP1IE - Compare1 Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_INTCTRL_CMP1IE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP1IE_SHIFT)) & EQDC_INTCTRL_CMP1IE_MASK) + +#define EQDC_INTCTRL_CMP1IRQ_MASK (0x800U) +#define EQDC_INTCTRL_CMP1IRQ_SHIFT (11U) +/*! CMP1IRQ - Compare1 Interrupt Request + * 0b0..No match has occurred (the position counter does not match the COMP1 value) + * 0b1..COMP1 match has occurred (the position counter matches the COMP1 value) + */ +#define EQDC_INTCTRL_CMP1IRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP1IRQ_SHIFT)) & EQDC_INTCTRL_CMP1IRQ_MASK) + +#define EQDC_INTCTRL_CMP2IE_MASK (0x1000U) +#define EQDC_INTCTRL_CMP2IE_SHIFT (12U) +/*! CMP2IE - Compare2 Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_INTCTRL_CMP2IE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP2IE_SHIFT)) & EQDC_INTCTRL_CMP2IE_MASK) + +#define EQDC_INTCTRL_CMP2IRQ_MASK (0x2000U) +#define EQDC_INTCTRL_CMP2IRQ_SHIFT (13U) +/*! CMP2IRQ - Compare2 Interrupt Request + * 0b0..No match has occurred (the position counter does not match the COMP2 value) + * 0b1..COMP2 match has occurred (the position counter matches the COMP2 value) + */ +#define EQDC_INTCTRL_CMP2IRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP2IRQ_SHIFT)) & EQDC_INTCTRL_CMP2IRQ_MASK) + +#define EQDC_INTCTRL_CMP3IE_MASK (0x4000U) +#define EQDC_INTCTRL_CMP3IE_SHIFT (14U) +/*! CMP3IE - Compare3 Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_INTCTRL_CMP3IE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP3IE_SHIFT)) & EQDC_INTCTRL_CMP3IE_MASK) + +#define EQDC_INTCTRL_CMP3IRQ_MASK (0x8000U) +#define EQDC_INTCTRL_CMP3IRQ_SHIFT (15U) +/*! CMP3IRQ - Compare3 Interrupt Request + * 0b0..No match has occurred (the position counter does not match the COMP3 value) + * 0b1..COMP3 match has occurred (the position counter matches the COMP3 value) + */ +#define EQDC_INTCTRL_CMP3IRQ(x) (((uint16_t)(((uint16_t)(x)) << EQDC_INTCTRL_CMP3IRQ_SHIFT)) & EQDC_INTCTRL_CMP3IRQ_MASK) +/*! @} */ + +/*! @name WTR - Watchdog Timeout Register */ +/*! @{ */ + +#define EQDC_WTR_WDOG_MASK (0xFFFFU) +#define EQDC_WTR_WDOG_SHIFT (0U) +/*! WDOG - WDOG */ +#define EQDC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << EQDC_WTR_WDOG_SHIFT)) & EQDC_WTR_WDOG_MASK) +/*! @} */ + +/*! @name IMR - Input Monitor Register */ +/*! @{ */ + +#define EQDC_IMR_HOME_ENABLE_MASK (0x1U) +#define EQDC_IMR_HOME_ENABLE_SHIFT (0U) +/*! HOME_ENABLE - HOME_ENABLE */ +#define EQDC_IMR_HOME_ENABLE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_HOME_ENABLE_SHIFT)) & EQDC_IMR_HOME_ENABLE_MASK) + +#define EQDC_IMR_INDEX_PRESET_MASK (0x2U) +#define EQDC_IMR_INDEX_PRESET_SHIFT (1U) +/*! INDEX_PRESET - INDEX_PRESET */ +#define EQDC_IMR_INDEX_PRESET(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_INDEX_PRESET_SHIFT)) & EQDC_IMR_INDEX_PRESET_MASK) + +#define EQDC_IMR_PHB_MASK (0x4U) +#define EQDC_IMR_PHB_SHIFT (2U) +/*! PHB - PHB */ +#define EQDC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_PHB_SHIFT)) & EQDC_IMR_PHB_MASK) + +#define EQDC_IMR_PHA_MASK (0x8U) +#define EQDC_IMR_PHA_SHIFT (3U) +/*! PHA - PHA */ +#define EQDC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_PHA_SHIFT)) & EQDC_IMR_PHA_MASK) + +#define EQDC_IMR_FHOM_ENA_MASK (0x10U) +#define EQDC_IMR_FHOM_ENA_SHIFT (4U) +/*! FHOM_ENA - filter operation on HOME/ENABLE input */ +#define EQDC_IMR_FHOM_ENA(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_FHOM_ENA_SHIFT)) & EQDC_IMR_FHOM_ENA_MASK) + +#define EQDC_IMR_FIND_PRE_MASK (0x20U) +#define EQDC_IMR_FIND_PRE_SHIFT (5U) +/*! FIND_PRE - filter operation on INDEX/PRESET input */ +#define EQDC_IMR_FIND_PRE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_FIND_PRE_SHIFT)) & EQDC_IMR_FIND_PRE_MASK) + +#define EQDC_IMR_FPHB_MASK (0x40U) +#define EQDC_IMR_FPHB_SHIFT (6U) +/*! FPHB - filter operation on PHASEB input */ +#define EQDC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_FPHB_SHIFT)) & EQDC_IMR_FPHB_MASK) + +#define EQDC_IMR_FPHA_MASK (0x80U) +#define EQDC_IMR_FPHA_SHIFT (7U) +/*! FPHA - filter operation on PHASEA input */ +#define EQDC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_FPHA_SHIFT)) & EQDC_IMR_FPHA_MASK) + +#define EQDC_IMR_CMPF0_MASK (0x100U) +#define EQDC_IMR_CMPF0_SHIFT (8U) +/*! CMPF0 - Position Compare 0 Flag Output + * 0b0..When the position counter is less than value of COMP0 register + * 0b1..When the position counter is greater or equal than value of COMP0 register + */ +#define EQDC_IMR_CMPF0(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_CMPF0_SHIFT)) & EQDC_IMR_CMPF0_MASK) + +#define EQDC_IMR_CMP1F_MASK (0x200U) +#define EQDC_IMR_CMP1F_SHIFT (9U) +/*! CMP1F - Position Compare1 Flag Output + * 0b0..When the position counter is less than value of COMP1 register + * 0b1..When the position counter is greater or equal than value of COMP1 register + */ +#define EQDC_IMR_CMP1F(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_CMP1F_SHIFT)) & EQDC_IMR_CMP1F_MASK) + +#define EQDC_IMR_CMP2F_MASK (0x400U) +#define EQDC_IMR_CMP2F_SHIFT (10U) +/*! CMP2F - Position Compare2 Flag Output + * 0b0..When the position counter is less than value of COMP2 register + * 0b1..When the position counter is greater or equal than value of COMP2 register + */ +#define EQDC_IMR_CMP2F(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_CMP2F_SHIFT)) & EQDC_IMR_CMP2F_MASK) + +#define EQDC_IMR_CMP3F_MASK (0x800U) +#define EQDC_IMR_CMP3F_SHIFT (11U) +/*! CMP3F - Position Compare3 Flag Output + * 0b0..When the position counter value is less than value of COMP3 register + * 0b1..When the position counter is greater or equal than value of COMP3 register + */ +#define EQDC_IMR_CMP3F(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_CMP3F_SHIFT)) & EQDC_IMR_CMP3F_MASK) + +#define EQDC_IMR_DIRH_MASK (0x4000U) +#define EQDC_IMR_DIRH_SHIFT (14U) +/*! DIRH - Count Direction Flag Hold */ +#define EQDC_IMR_DIRH(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_DIRH_SHIFT)) & EQDC_IMR_DIRH_MASK) + +#define EQDC_IMR_DIR_MASK (0x8000U) +#define EQDC_IMR_DIR_SHIFT (15U) +/*! DIR - Count Direction Flag Output + * 0b0..Current count was in the down direction + * 0b1..Current count was in the up direction + */ +#define EQDC_IMR_DIR(x) (((uint16_t)(((uint16_t)(x)) << EQDC_IMR_DIR_SHIFT)) & EQDC_IMR_DIR_MASK) +/*! @} */ + +/*! @name TST - Test Register */ +/*! @{ */ + +#define EQDC_TST_TEST_COUNT_MASK (0xFFU) +#define EQDC_TST_TEST_COUNT_SHIFT (0U) +/*! TEST_COUNT - TEST_COUNT */ +#define EQDC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << EQDC_TST_TEST_COUNT_SHIFT)) & EQDC_TST_TEST_COUNT_MASK) + +#define EQDC_TST_TEST_PERIOD_MASK (0x1F00U) +#define EQDC_TST_TEST_PERIOD_SHIFT (8U) +/*! TEST_PERIOD - TEST_PERIOD */ +#define EQDC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << EQDC_TST_TEST_PERIOD_SHIFT)) & EQDC_TST_TEST_PERIOD_MASK) + +#define EQDC_TST_QDN_MASK (0x2000U) +#define EQDC_TST_QDN_SHIFT (13U) +/*! QDN - Quadrature Decoder Negative Signal + * 0b0..Generates a positive quadrature decoder signal + * 0b1..Generates a negative quadrature decoder signal + */ +#define EQDC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << EQDC_TST_QDN_SHIFT)) & EQDC_TST_QDN_MASK) + +#define EQDC_TST_TCE_MASK (0x4000U) +#define EQDC_TST_TCE_SHIFT (14U) +/*! TCE - Test Counter Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << EQDC_TST_TCE_SHIFT)) & EQDC_TST_TCE_MASK) + +#define EQDC_TST_TEN_MASK (0x8000U) +#define EQDC_TST_TEN_SHIFT (15U) +/*! TEN - Test Mode Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define EQDC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << EQDC_TST_TEN_SHIFT)) & EQDC_TST_TEN_MASK) +/*! @} */ + +/*! @name UVERID - Upper VERID */ +/*! @{ */ + +#define EQDC_UVERID_UVERID_MASK (0xFFFFU) +#define EQDC_UVERID_UVERID_SHIFT (0U) +/*! UVERID - UVERID */ +#define EQDC_UVERID_UVERID(x) (((uint16_t)(((uint16_t)(x)) << EQDC_UVERID_UVERID_SHIFT)) & EQDC_UVERID_UVERID_MASK) +/*! @} */ + +/*! @name LVERID - Lower VERID */ +/*! @{ */ + +#define EQDC_LVERID_LVERID_MASK (0xFFFFU) +#define EQDC_LVERID_LVERID_SHIFT (0U) +/*! LVERID - LVERID */ +#define EQDC_LVERID_LVERID(x) (((uint16_t)(((uint16_t)(x)) << EQDC_LVERID_LVERID_SHIFT)) & EQDC_LVERID_LVERID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group EQDC_Register_Masks */ + + +/* EQDC - Peripheral instance base addresses */ +/** Peripheral QDC0 base address */ +#define QDC0_BASE (0x400A7000u) +/** Peripheral QDC0 base pointer */ +#define QDC0 ((EQDC_Type *)QDC0_BASE) +/** Peripheral QDC1 base address */ +#define QDC1_BASE (0x400A8000u) +/** Peripheral QDC1 base pointer */ +#define QDC1 ((EQDC_Type *)QDC1_BASE) +/** Array initializer of EQDC peripheral base addresses */ +#define EQDC_BASE_ADDRS { QDC0_BASE, QDC1_BASE } +/** Array initializer of EQDC peripheral base pointers */ +#define EQDC_BASE_PTRS { QDC0, QDC1 } +/** Interrupt vectors for the EQDC peripheral type */ +#define EQDC_COMPARE_IRQS { QDC0_COMPARE_IRQn, QDC1_COMPARE_IRQn } +#define EQDC_HOME_IRQS { QDC0_HOME_IRQn, QDC1_HOME_IRQn } +#define EQDC_WDOG_IRQS { QDC0_WATCHDOG_IRQn, QDC1_WATCHDOG_IRQn } +#define EQDC_INDEX_IRQS { QDC0_INDEX_IRQn, QDC1_INDEX_IRQn } +#define EQDC_INPUT_SWITCH_IRQS { QDC0_WATCHDOG_IRQn, QDC1_WATCHDOG_IRQn } + +/*! + * @} + */ /* end of group EQDC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ERM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ERM_Peripheral_Access_Layer ERM Peripheral Access Layer + * @{ + */ + +/** ERM - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR0; /**< ERM Configuration Register 0, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t SR0; /**< ERM Status Register 0, offset: 0x10 */ + uint8_t RESERVED_1[236]; + __I uint32_t EAR0; /**< ERM Memory 0 Error Address Register, offset: 0x100 */ + __I uint32_t SYN0; /**< ERM Memory 0 Syndrome Register, offset: 0x104 */ + __IO uint32_t CORR_ERR_CNT0; /**< ERM Memory 0 Correctable Error Count Register, offset: 0x108 */ + uint8_t RESERVED_2[12]; + __IO uint32_t CORR_ERR_CNT1; /**< ERM Memory 1 Correctable Error Count Register, offset: 0x118 */ +} ERM_Type; + +/* ---------------------------------------------------------------------------- + -- ERM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ERM_Register_Masks ERM Register Masks + * @{ + */ + +/*! @name CR0 - ERM Configuration Register 0 */ +/*! @{ */ + +#define ERM_CR0_ENCIE1_MASK (0x4000000U) +#define ERM_CR0_ENCIE1_SHIFT (26U) +/*! ENCIE1 - ENCIE1 + * 0b0..Interrupt notification of Memory 1 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 1 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE1_SHIFT)) & ERM_CR0_ENCIE1_MASK) + +#define ERM_CR0_ESCIE1_MASK (0x8000000U) +#define ERM_CR0_ESCIE1_SHIFT (27U) +/*! ESCIE1 - ESCIE1 + * 0b0..Interrupt notification of Memory 1 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 1 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE1_SHIFT)) & ERM_CR0_ESCIE1_MASK) + +#define ERM_CR0_ENCIE0_MASK (0x40000000U) +#define ERM_CR0_ENCIE0_SHIFT (30U) +/*! ENCIE0 - ENCIE0 + * 0b0..Interrupt notification of Memory 0 non-correctable error events is disabled. + * 0b1..Interrupt notification of Memory 0 non-correctable error events is enabled. + */ +#define ERM_CR0_ENCIE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE0_SHIFT)) & ERM_CR0_ENCIE0_MASK) + +#define ERM_CR0_ESCIE0_MASK (0x80000000U) +#define ERM_CR0_ESCIE0_SHIFT (31U) +/*! ESCIE0 - ESCIE0 + * 0b0..Interrupt notification of Memory 0 single-bit correction events is disabled. + * 0b1..Interrupt notification of Memory 0 single-bit correction events is enabled. + */ +#define ERM_CR0_ESCIE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE0_SHIFT)) & ERM_CR0_ESCIE0_MASK) +/*! @} */ + +/*! @name SR0 - ERM Status Register 0 */ +/*! @{ */ + +#define ERM_SR0_NCE1_MASK (0x4000000U) +#define ERM_SR0_NCE1_SHIFT (26U) +/*! NCE1 - NCE1 + * 0b0..No non-correctable error event on Memory 1 detected. + * 0b1..Non-correctable error event on Memory 1 detected. + */ +#define ERM_SR0_NCE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE1_SHIFT)) & ERM_SR0_NCE1_MASK) + +#define ERM_SR0_SBC1_MASK (0x8000000U) +#define ERM_SR0_SBC1_SHIFT (27U) +/*! SBC1 - SBC1 + * 0b0..No single-bit correction event on Memory 1 detected. + * 0b1..Single-bit correction event on Memory 1 detected. + */ +#define ERM_SR0_SBC1(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC1_SHIFT)) & ERM_SR0_SBC1_MASK) + +#define ERM_SR0_NCE0_MASK (0x40000000U) +#define ERM_SR0_NCE0_SHIFT (30U) +/*! NCE0 - NCE0 + * 0b0..No non-correctable error event on Memory 0 detected. + * 0b1..Non-correctable error event on Memory 0 detected. + */ +#define ERM_SR0_NCE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE0_SHIFT)) & ERM_SR0_NCE0_MASK) + +#define ERM_SR0_SBC0_MASK (0x80000000U) +#define ERM_SR0_SBC0_SHIFT (31U) +/*! SBC0 - SBC0 + * 0b0..No single-bit correction event on Memory 0 detected. + * 0b1..Single-bit correction event on Memory 0 detected. + */ +#define ERM_SR0_SBC0(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC0_SHIFT)) & ERM_SR0_SBC0_MASK) +/*! @} */ + +/*! @name EAR0 - ERM Memory 0 Error Address Register */ +/*! @{ */ + +#define ERM_EAR0_EAR_MASK (0xFFFFFFFFU) +#define ERM_EAR0_EAR_SHIFT (0U) +/*! EAR - EAR */ +#define ERM_EAR0_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR0_EAR_SHIFT)) & ERM_EAR0_EAR_MASK) +/*! @} */ + +/*! @name SYN0 - ERM Memory 0 Syndrome Register */ +/*! @{ */ + +#define ERM_SYN0_SYNDROME_MASK (0xFF000000U) +#define ERM_SYN0_SYNDROME_SHIFT (24U) +/*! SYNDROME - SYNDROME */ +#define ERM_SYN0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN0_SYNDROME_SHIFT)) & ERM_SYN0_SYNDROME_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT0 - ERM Memory 0 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT0_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT0_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT0_COUNT_SHIFT)) & ERM_CORR_ERR_CNT0_COUNT_MASK) +/*! @} */ + +/*! @name CORR_ERR_CNT1 - ERM Memory 1 Correctable Error Count Register */ +/*! @{ */ + +#define ERM_CORR_ERR_CNT1_COUNT_MASK (0xFFU) +#define ERM_CORR_ERR_CNT1_COUNT_SHIFT (0U) +/*! COUNT - Memory n Correctable Error Count */ +#define ERM_CORR_ERR_CNT1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT1_COUNT_SHIFT)) & ERM_CORR_ERR_CNT1_COUNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ERM_Register_Masks */ + + +/* ERM - Peripheral instance base addresses */ +/** Peripheral ERM0 base address */ +#define ERM0_BASE (0x4008D000u) +/** Peripheral ERM0 base pointer */ +#define ERM0 ((ERM_Type *)ERM0_BASE) +/** Array initializer of ERM peripheral base addresses */ +#define ERM_BASE_ADDRS { ERM0_BASE } +/** Array initializer of ERM peripheral base pointers */ +#define ERM_BASE_PTRS { ERM0 } + +/*! + * @} + */ /* end of group ERM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer + * @{ + */ + +/** FLEXIO - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t CTRL; /**< FLEXIO Control, offset: 0x8 */ + __I uint32_t PIN; /**< Pin State, offset: 0xC */ + __IO uint32_t SHIFTSTAT; /**< Shifter Status, offset: 0x10 */ + __IO uint32_t SHIFTERR; /**< Shifter Error, offset: 0x14 */ + __IO uint32_t TIMSTAT; /**< Timer Status Flag, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ + __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ + __IO uint32_t TIMIEN; /**< Timer Interrupt Enable, offset: 0x28 */ + uint8_t RESERVED_1[4]; + __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ + uint8_t RESERVED_2[4]; + __IO uint32_t TIMERSDEN; /**< Timer Status DMA Enable, offset: 0x38 */ + uint8_t RESERVED_3[4]; + __IO uint32_t SHIFTSTATE; /**< Shifter State, offset: 0x40 */ + uint8_t RESERVED_4[4]; + __IO uint32_t TRGSTAT; /**< Trigger Status, offset: 0x48 */ + __IO uint32_t TRIGIEN; /**< External Trigger Interrupt Enable, offset: 0x4C */ + __IO uint32_t PINSTAT; /**< Pin Status, offset: 0x50 */ + __IO uint32_t PINIEN; /**< Pin Interrupt Enable, offset: 0x54 */ + __IO uint32_t PINREN; /**< Pin Rising Edge Enable, offset: 0x58 */ + __IO uint32_t PINFEN; /**< Pin Falling Edge Enable, offset: 0x5C */ + __IO uint32_t PINOUTD; /**< Pin Output Data, offset: 0x60 */ + __IO uint32_t PINOUTE; /**< Pin Output Enable, offset: 0x64 */ + __O uint32_t PINOUTDIS; /**< Pin Output Disable, offset: 0x68 */ + __O uint32_t PINOUTCLR; /**< Pin Output Clear, offset: 0x6C */ + __O uint32_t PINOUTSET; /**< Pin Output Set, offset: 0x70 */ + __O uint32_t PINOUTTOG; /**< Pin Output Toggle, offset: 0x74 */ + uint8_t RESERVED_5[8]; + __IO uint32_t SHIFTCTL[4]; /**< Shifter Control, array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_6[112]; + __IO uint32_t SHIFTCFG[4]; /**< Shifter Configuration, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_7[240]; + __IO uint32_t SHIFTBUF[4]; /**< Shifter Buffer, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_8[112]; + __IO uint32_t SHIFTBUFBIS[4]; /**< Shifter Buffer Bit Swapped, array offset: 0x280, array step: 0x4 */ + uint8_t RESERVED_9[112]; + __IO uint32_t SHIFTBUFBYS[4]; /**< Shifter Buffer Byte Swapped, array offset: 0x300, array step: 0x4 */ + uint8_t RESERVED_10[112]; + __IO uint32_t SHIFTBUFBBS[4]; /**< Shifter Buffer Bit Byte Swapped, array offset: 0x380, array step: 0x4 */ + uint8_t RESERVED_11[112]; + __IO uint32_t TIMCTL[4]; /**< Timer Control, array offset: 0x400, array step: 0x4 */ + uint8_t RESERVED_12[112]; + __IO uint32_t TIMCFG[4]; /**< Timer Configuration, array offset: 0x480, array step: 0x4 */ + uint8_t RESERVED_13[112]; + __IO uint32_t TIMCMP[4]; /**< Timer Compare, array offset: 0x500, array step: 0x4 */ + uint8_t RESERVED_14[368]; + __IO uint32_t SHIFTBUFNBS[4]; /**< Shifter Buffer Nibble Byte Swapped, array offset: 0x680, array step: 0x4 */ + uint8_t RESERVED_15[112]; + __IO uint32_t SHIFTBUFHWS[4]; /**< Shifter Buffer Halfword Swapped, array offset: 0x700, array step: 0x4 */ + uint8_t RESERVED_16[112]; + __IO uint32_t SHIFTBUFNIS[4]; /**< Shifter Buffer Nibble Swapped, array offset: 0x780, array step: 0x4 */ + uint8_t RESERVED_17[112]; + __IO uint32_t SHIFTBUFOES[4]; /**< Shifter Buffer Odd Even Swapped, array offset: 0x800, array step: 0x4 */ + uint8_t RESERVED_18[112]; + __IO uint32_t SHIFTBUFEOS[4]; /**< Shifter Buffer Even Odd Swapped, array offset: 0x880, array step: 0x4 */ + uint8_t RESERVED_19[112]; + __IO uint32_t SHIFTBUFHBS[4]; /**< Shifter Buffer Halfword Byte Swapped, array offset: 0x900, array step: 0x4 */ +} FLEXIO_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) +#define FLEXIO_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features implemented + * 0b0000000000000001..State, logic, and parallel modes supported + * 0b0000000000000010..Pin control registers supported + * 0b0000000000000011..State, logic, and parallel modes, plus pin control registers supported + */ +#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) + +#define FLEXIO_VERID_MINOR_MASK (0xFF0000U) +#define FLEXIO_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) + +#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) +#define FLEXIO_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) +#define FLEXIO_PARAM_SHIFTER_SHIFT (0U) +/*! SHIFTER - Shifter Number */ +#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) + +#define FLEXIO_PARAM_TIMER_MASK (0xFF00U) +#define FLEXIO_PARAM_TIMER_SHIFT (8U) +/*! TIMER - Timer Number */ +#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) + +#define FLEXIO_PARAM_PIN_MASK (0xFF0000U) +#define FLEXIO_PARAM_PIN_SHIFT (16U) +/*! PIN - Pin Number */ +#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) + +#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) +#define FLEXIO_PARAM_TRIGGER_SHIFT (24U) +/*! TRIGGER - Trigger Number */ +#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) +/*! @} */ + +/*! @name CTRL - FLEXIO Control */ +/*! @{ */ + +#define FLEXIO_CTRL_FLEXEN_MASK (0x1U) +#define FLEXIO_CTRL_FLEXEN_SHIFT (0U) +/*! FLEXEN - FLEXIO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) + +#define FLEXIO_CTRL_SWRST_MASK (0x2U) +#define FLEXIO_CTRL_SWRST_SHIFT (1U) +/*! SWRST - Software Reset + * 0b0..Disabled + * 0b1..Enabled + */ +#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) + +#define FLEXIO_CTRL_FASTACC_MASK (0x4U) +#define FLEXIO_CTRL_FASTACC_SHIFT (2U) +/*! FASTACC - Fast Access + * 0b0..Normal + * 0b1..Fast + */ +#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) + +#define FLEXIO_CTRL_DBGE_MASK (0x40000000U) +#define FLEXIO_CTRL_DBGE_SHIFT (30U) +/*! DBGE - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) + +#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) +#define FLEXIO_CTRL_DOZEN_SHIFT (31U) +/*! DOZEN - Doze Enable + * 0b0..Enable + * 0b1..Disable + */ +#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) +/*! @} */ + +/*! @name PIN - Pin State */ +/*! @{ */ + +#define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) +#define FLEXIO_PIN_PDI_SHIFT (0U) +/*! PDI - Pin Data Input */ +#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) +/*! @} */ + +/*! @name SHIFTSTAT - Shifter Status */ +/*! @{ */ + +#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFU) +#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) +/*! SSF - Shifter Status Flag + * 0b0000..Clear + * 0b0001..Set + * 0b0000..No effect + * 0b0001..Clear the flag + */ +#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) +/*! @} */ + +/*! @name SHIFTERR - Shifter Error */ +/*! @{ */ + +#define FLEXIO_SHIFTERR_SEF_MASK (0xFU) +#define FLEXIO_SHIFTERR_SEF_SHIFT (0U) +/*! SEF - Shifter Error Flag + * 0b0000..Clear + * 0b0001..Set + * 0b0000..No effect + * 0b0001..Clear the flag + */ +#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) +/*! @} */ + +/*! @name TIMSTAT - Timer Status Flag */ +/*! @{ */ + +#define FLEXIO_TIMSTAT_TSF_MASK (0xFU) +#define FLEXIO_TIMSTAT_TSF_SHIFT (0U) +/*! TSF - Timer Status Flag + * 0b0000..Clear + * 0b0001..Set + * 0b0000..No effect + * 0b0001..Clear the flag + */ +#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) +/*! @} */ + +/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFU) +#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) +/*! SSIE - Shifter Status Interrupt Enable */ +#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) +/*! @} */ + +/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFU) +#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) +/*! SEIE - Shifter Error Interrupt Enable */ +#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) +/*! @} */ + +/*! @name TIMIEN - Timer Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_TIMIEN_TEIE_MASK (0xFU) +#define FLEXIO_TIMIEN_TEIE_SHIFT (0U) +/*! TEIE - Timer Status Interrupt Enable */ +#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) +/*! @} */ + +/*! @name SHIFTSDEN - Shifter Status DMA Enable */ +/*! @{ */ + +#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFU) +#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) +/*! SSDE - Shifter Status DMA Enable */ +#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) +/*! @} */ + +/*! @name TIMERSDEN - Timer Status DMA Enable */ +/*! @{ */ + +#define FLEXIO_TIMERSDEN_TSDE_MASK (0xFU) +#define FLEXIO_TIMERSDEN_TSDE_SHIFT (0U) +/*! TSDE - Timer Status DMA Enable */ +#define FLEXIO_TIMERSDEN_TSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK) +/*! @} */ + +/*! @name SHIFTSTATE - Shifter State */ +/*! @{ */ + +#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) +#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) +/*! STATE - Current State Pointer */ +#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) +/*! @} */ + +/*! @name TRGSTAT - Trigger Status */ +/*! @{ */ + +#define FLEXIO_TRGSTAT_ETSF_MASK (0xFU) +#define FLEXIO_TRGSTAT_ETSF_SHIFT (0U) +/*! ETSF - External Trigger Status Flag + * 0b0000..Clear + * 0b0001..Set + * 0b0000..No effect + * 0b0001..Clear the flag + */ +#define FLEXIO_TRGSTAT_ETSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRGSTAT_ETSF_SHIFT)) & FLEXIO_TRGSTAT_ETSF_MASK) +/*! @} */ + +/*! @name TRIGIEN - External Trigger Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_TRIGIEN_TRIE_MASK (0xFU) +#define FLEXIO_TRIGIEN_TRIE_SHIFT (0U) +/*! TRIE - External Trigger Interrupt Enable */ +#define FLEXIO_TRIGIEN_TRIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TRIGIEN_TRIE_SHIFT)) & FLEXIO_TRIGIEN_TRIE_MASK) +/*! @} */ + +/*! @name PINSTAT - Pin Status */ +/*! @{ */ + +#define FLEXIO_PINSTAT_PSF_MASK (0xFFFFFFFFU) +#define FLEXIO_PINSTAT_PSF_SHIFT (0U) +/*! PSF - Pin Status Flag + * 0b00000000000000000000000000000000..Clear + * 0b00000000000000000000000000000001..Set + * 0b00000000000000000000000000000000..No effect + * 0b00000000000000000000000000000001..Clear the flag + */ +#define FLEXIO_PINSTAT_PSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINSTAT_PSF_SHIFT)) & FLEXIO_PINSTAT_PSF_MASK) +/*! @} */ + +/*! @name PINIEN - Pin Interrupt Enable */ +/*! @{ */ + +#define FLEXIO_PINIEN_PSIE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINIEN_PSIE_SHIFT (0U) +/*! PSIE - Pin Status Interrupt Enable */ +#define FLEXIO_PINIEN_PSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINIEN_PSIE_SHIFT)) & FLEXIO_PINIEN_PSIE_MASK) +/*! @} */ + +/*! @name PINREN - Pin Rising Edge Enable */ +/*! @{ */ + +#define FLEXIO_PINREN_PRE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINREN_PRE_SHIFT (0U) +/*! PRE - Pin Rising Edge */ +#define FLEXIO_PINREN_PRE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINREN_PRE_SHIFT)) & FLEXIO_PINREN_PRE_MASK) +/*! @} */ + +/*! @name PINFEN - Pin Falling Edge Enable */ +/*! @{ */ + +#define FLEXIO_PINFEN_PFE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINFEN_PFE_SHIFT (0U) +/*! PFE - Pin Falling Edge */ +#define FLEXIO_PINFEN_PFE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINFEN_PFE_SHIFT)) & FLEXIO_PINFEN_PFE_MASK) +/*! @} */ + +/*! @name PINOUTD - Pin Output Data */ +/*! @{ */ + +#define FLEXIO_PINOUTD_OUTD_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTD_OUTD_SHIFT (0U) +/*! OUTD - Output Data */ +#define FLEXIO_PINOUTD_OUTD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTD_OUTD_SHIFT)) & FLEXIO_PINOUTD_OUTD_MASK) +/*! @} */ + +/*! @name PINOUTE - Pin Output Enable */ +/*! @{ */ + +#define FLEXIO_PINOUTE_OUTE_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTE_OUTE_SHIFT (0U) +/*! OUTE - Output Enable */ +#define FLEXIO_PINOUTE_OUTE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTE_OUTE_SHIFT)) & FLEXIO_PINOUTE_OUTE_MASK) +/*! @} */ + +/*! @name PINOUTDIS - Pin Output Disable */ +/*! @{ */ + +#define FLEXIO_PINOUTDIS_OUTDIS_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTDIS_OUTDIS_SHIFT (0U) +/*! OUTDIS - Output Disable */ +#define FLEXIO_PINOUTDIS_OUTDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTDIS_OUTDIS_SHIFT)) & FLEXIO_PINOUTDIS_OUTDIS_MASK) +/*! @} */ + +/*! @name PINOUTCLR - Pin Output Clear */ +/*! @{ */ + +#define FLEXIO_PINOUTCLR_OUTCLR_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTCLR_OUTCLR_SHIFT (0U) +/*! OUTCLR - Output Clear */ +#define FLEXIO_PINOUTCLR_OUTCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTCLR_OUTCLR_SHIFT)) & FLEXIO_PINOUTCLR_OUTCLR_MASK) +/*! @} */ + +/*! @name PINOUTSET - Pin Output Set */ +/*! @{ */ + +#define FLEXIO_PINOUTSET_OUTSET_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTSET_OUTSET_SHIFT (0U) +/*! OUTSET - Output Set */ +#define FLEXIO_PINOUTSET_OUTSET(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTSET_OUTSET_SHIFT)) & FLEXIO_PINOUTSET_OUTSET_MASK) +/*! @} */ + +/*! @name PINOUTTOG - Pin Output Toggle */ +/*! @{ */ + +#define FLEXIO_PINOUTTOG_OUTTOG_MASK (0xFFFFFFFFU) +#define FLEXIO_PINOUTTOG_OUTTOG_SHIFT (0U) +/*! OUTTOG - Output Toggle */ +#define FLEXIO_PINOUTTOG_OUTTOG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PINOUTTOG_OUTTOG_SHIFT)) & FLEXIO_PINOUTTOG_OUTTOG_MASK) +/*! @} */ + +/*! @name SHIFTCTL - Shifter Control */ +/*! @{ */ + +#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) +#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) +/*! SMOD - Shifter Mode + * 0b000..Disable + * 0b001..Receive mode; capture the current shifter content into SHIFTBUF on expiration of the timer + * 0b010..Transmit mode; load SHIFTBUF contents into the shifter on expiration of the timer + * 0b011..Reserved + * 0b100..Match Store mode; shifter data is compared to SHIFTBUF content on expiration of the timer + * 0b101..Match Continuous mode; shifter data is continuously compared to SHIFTBUF contents + * 0b110..State mode; SHIFTBUF contents store programmable state attributes + * 0b111..Logic mode; SHIFTBUF contents implement programmable logic lookup table + */ +#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) + +#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) +#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Shifter Pin Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) + +#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) +#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) +/*! PINSEL - Shifter Pin Select */ +#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) + +#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Shifter Pin Configuration + * 0b00..Shifter pin output disabled + * 0b01..Shifter pin open-drain or bidirectional output enable + * 0b10..Shifter pin bidirectional output data + * 0b11..Shifter pin output + */ +#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) + +#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) +#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) +/*! TIMPOL - Timer Polarity + * 0b0..Positive edge + * 0b1..Negative edge + */ +#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) + +#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x3000000U) +#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) +/*! TIMSEL - Timer Select */ +#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTCTL */ +#define FLEXIO_SHIFTCTL_COUNT (4U) + +/*! @name SHIFTCFG - Shifter Configuration */ +/*! @{ */ + +#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) +#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) +/*! SSTART - Shifter Start + * 0b00..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on enable + * 0b01..Start bit disabled for Transmitter, Receiver, and Match Store modes; Transmitter mode loads data on first shift + * 0b10..Transmitter mode outputs start bit value 0 before loading data on first shift; if start bit is not 0, + * Receiver and Match Store modes set error flag + * 0b11..Transmitter mode outputs start bit value 1 before loading data on first shift; if start bit is not 1, + * Receiver and Match Store modes set error flag + */ +#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) + +#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) +#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) +/*! SSTOP - Shifter Stop + * 0b00..Stop bit disabled for Transmitter, Receiver, and Match Store modes + * 0b01..Stop bit disabled for Transmitter, Receiver, and Match Store modes; when timer is in stop condition, + * Receiver and Match Store modes store receive data on the configured shift edge + * 0b10..Transmitter mode outputs stop bit value 0 in Match Store mode; if stop bit is not 0, Receiver and Match + * Store modes set error flag (when timer is in stop condition, these modes also store receive data on the + * configured shift edge) + * 0b11..Transmitter mode outputs stop bit value 1 in Match Store mode; if stop bit is not 1, Receiver and Match + * Store modes set error flag (when timer is in stop condition, these modes also store receive data on the + * configured shift edge) + */ +#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) + +#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) +#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) +/*! INSRC - Input Source + * 0b0..Pin + * 0b1..Shifter n+1 output + */ +#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) + +#define FLEXIO_SHIFTCFG_LATST_MASK (0x200U) +#define FLEXIO_SHIFTCFG_LATST_SHIFT (9U) +/*! LATST - Late Store + * 0b0..Store the pre-shift register state + * 0b1..Store the post-shift register state + */ +#define FLEXIO_SHIFTCFG_LATST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK) + +#define FLEXIO_SHIFTCFG_SSIZE_MASK (0x1000U) +#define FLEXIO_SHIFTCFG_SSIZE_SHIFT (12U) +/*! SSIZE - Shifter Size + * 0b0..32-bit + * 0b1..24-bit + */ +#define FLEXIO_SHIFTCFG_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSIZE_SHIFT)) & FLEXIO_SHIFTCFG_SSIZE_MASK) + +#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) +#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) +/*! PWIDTH - Parallel Width */ +#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTCFG */ +#define FLEXIO_SHIFTCFG_COUNT (4U) + +/*! @name SHIFTBUF - Shifter Buffer */ +/*! @{ */ + +#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) +/*! SHIFTBUF - Shift Buffer */ +#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUF */ +#define FLEXIO_SHIFTBUF_COUNT (4U) + +/*! @name SHIFTBUFBIS - Shifter Buffer Bit Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) +/*! SHIFTBUFBIS - Shift Buffer */ +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBIS */ +#define FLEXIO_SHIFTBUFBIS_COUNT (4U) + +/*! @name SHIFTBUFBYS - Shifter Buffer Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) +/*! SHIFTBUFBYS - Shift Buffer */ +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBYS */ +#define FLEXIO_SHIFTBUFBYS_COUNT (4U) + +/*! @name SHIFTBUFBBS - Shifter Buffer Bit Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) +/*! SHIFTBUFBBS - Shift Buffer */ +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFBBS */ +#define FLEXIO_SHIFTBUFBBS_COUNT (4U) + +/*! @name TIMCTL - Timer Control */ +/*! @{ */ + +#define FLEXIO_TIMCTL_TIMOD_MASK (0x7U) +#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) +/*! TIMOD - Timer Mode + * 0b000..Timer disabled + * 0b001..Dual 8-bit counters baud mode + * 0b010..Dual 8-bit counters PWM high mode + * 0b011..Single 16-bit counter mode + * 0b100..Single 16-bit counter disable mode + * 0b101..Dual 8-bit counters word mode + * 0b110..Dual 8-bit counters PWM low mode + * 0b111..Single 16-bit input capture mode + */ +#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) + +#define FLEXIO_TIMCTL_ONETIM_MASK (0x20U) +#define FLEXIO_TIMCTL_ONETIM_SHIFT (5U) +/*! ONETIM - Timer One Time Operation + * 0b0..Generate the timer enable event as normal + * 0b1..Block the timer enable event unless the timer status flag is clear + */ +#define FLEXIO_TIMCTL_ONETIM(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK) + +#define FLEXIO_TIMCTL_PININS_MASK (0x40U) +#define FLEXIO_TIMCTL_PININS_SHIFT (6U) +/*! PININS - Timer Pin Input Select + * 0b0..PINSEL selects timer pin input and output + * 0b1..PINSEL + 1 selects the timer pin input; timer pin output remains selected by PINSEL + */ +#define FLEXIO_TIMCTL_PININS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK) + +#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) +#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) +/*! PINPOL - Timer Pin Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) + +#define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) +#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) +/*! PINSEL - Timer Pin Select */ +#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) + +#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) +#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) +/*! PINCFG - Timer Pin Configuration + * 0b00..Timer pin output disabled + * 0b01..Timer pin open-drain or bidirectional output enable + * 0b10..Timer pin bidirectional output data + * 0b11..Timer pin output + */ +#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) + +#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) +#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) +/*! TRGSRC - Trigger Source + * 0b0..External + * 0b1..Internal + */ +#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) + +#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) +#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) +/*! TRGPOL - Trigger Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) + +#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) +#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) +/*! TRGSEL - Trigger Select */ +#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCTL */ +#define FLEXIO_TIMCTL_COUNT (4U) + +/*! @name TIMCFG - Timer Configuration */ +/*! @{ */ + +#define FLEXIO_TIMCFG_TSTART_MASK (0x2U) +#define FLEXIO_TIMCFG_TSTART_SHIFT (1U) +/*! TSTART - Timer Start + * 0b0..Disabled + * 0b1..Enabled + */ +#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) + +#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) +#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) +/*! TSTOP - Timer Stop + * 0b00..Disabled + * 0b01..Enabled on timer compare + * 0b10..Enabled on timer disable + * 0b11..Enabled on timer compare and timer disable + */ +#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) + +#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) +#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) +/*! TIMENA - Timer Enable + * 0b000..Timer always enabled + * 0b001..Timer enabled on timer n-1 enable + * 0b010..Timer enabled on trigger high + * 0b011..Timer enabled on trigger high and pin high + * 0b100..Timer enabled on pin rising edge + * 0b101..Timer enabled on pin rising edge and trigger high + * 0b110..Timer enabled on trigger rising edge + * 0b111..Timer enabled on trigger rising or falling edge + */ +#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) + +#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) +#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) +/*! TIMDIS - Timer Disable + * 0b000..Timer never disabled + * 0b001..Timer disabled on timer n-1 disable + * 0b010..Timer disabled on timer compare (upper 8 bits match and decrement) + * 0b011..Timer disabled on timer compare (upper 8 bits match and decrement) and trigger low + * 0b100..Timer disabled on pin rising or falling edge + * 0b101..Timer disabled on pin rising or falling edge provided trigger is high + * 0b110..Timer disabled on trigger falling edge + * 0b111..Reserved + */ +#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) + +#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) +#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) +/*! TIMRST - Timer Reset + * 0b000..Never reset timer + * 0b001..Timer reset on timer output high. + * 0b010..Timer reset on timer pin equal to timer output + * 0b011..Timer reset on timer trigger equal to timer output + * 0b100..Timer reset on timer pin rising edge + * 0b101..Reserved + * 0b110..Timer reset on trigger rising edge + * 0b111..Timer reset on trigger rising or falling edge + */ +#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) + +#define FLEXIO_TIMCFG_TIMDEC_MASK (0x700000U) +#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) +/*! TIMDEC - Timer Decrement + * 0b000..Decrement counter on FLEXIO clock; shift clock equals timer output + * 0b001..Decrement counter on trigger input (both edges); shift clock equals timer output + * 0b010..Decrement counter on pin input (both edges); shift clock equals pin input + * 0b011..Decrement counter on trigger input (both edges); shift clock equals trigger input + * 0b100..Decrement counter on FLEXIO clock divided by 16; shift clock equals timer output + * 0b101..Decrement counter on FLEXIO clock divided by 256; shift clock equals timer output + * 0b110..Decrement counter on pin input (rising edge); shift clock equals pin input + * 0b111..Decrement counter on trigger input (rising edge); shift clock equals trigger input + */ +#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) + +#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) +#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) +/*! TIMOUT - Timer Output + * 0b00..Logic one when enabled; not affected by timer reset + * 0b01..Logic zero when enabled; not affected by timer reset + * 0b10..Logic one when enabled and on timer reset + * 0b11..Logic zero when enabled and on timer reset + */ +#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCFG */ +#define FLEXIO_TIMCFG_COUNT (4U) + +/*! @name TIMCMP - Timer Compare */ +/*! @{ */ + +#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) +#define FLEXIO_TIMCMP_CMP_SHIFT (0U) +/*! CMP - Timer Compare Value */ +#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) +/*! @} */ + +/* The count of FLEXIO_TIMCMP */ +#define FLEXIO_TIMCMP_COUNT (4U) + +/*! @name SHIFTBUFNBS - Shifter Buffer Nibble Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) +/*! SHIFTBUFNBS - Shift Buffer */ +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFNBS */ +#define FLEXIO_SHIFTBUFNBS_COUNT (4U) + +/*! @name SHIFTBUFHWS - Shifter Buffer Halfword Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) +/*! SHIFTBUFHWS - Shift Buffer */ +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFHWS */ +#define FLEXIO_SHIFTBUFHWS_COUNT (4U) + +/*! @name SHIFTBUFNIS - Shifter Buffer Nibble Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) +/*! SHIFTBUFNIS - Shift Buffer */ +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFNIS */ +#define FLEXIO_SHIFTBUFNIS_COUNT (4U) + +/*! @name SHIFTBUFOES - Shifter Buffer Odd Even Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT (0U) +/*! SHIFTBUFOES - Shift Buffer */ +#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFOES */ +#define FLEXIO_SHIFTBUFOES_COUNT (4U) + +/*! @name SHIFTBUFEOS - Shifter Buffer Even Odd Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT (0U) +/*! SHIFTBUFEOS - Shift Buffer */ +#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFEOS */ +#define FLEXIO_SHIFTBUFEOS_COUNT (4U) + +/*! @name SHIFTBUFHBS - Shifter Buffer Halfword Byte Swapped */ +/*! @{ */ + +#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK (0xFFFFFFFFU) +#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT (0U) +/*! SHIFTBUFHBS - Shift Buffer */ +#define FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_SHIFT)) & FLEXIO_SHIFTBUFHBS_SHIFTBUFHBS_MASK) +/*! @} */ + +/* The count of FLEXIO_SHIFTBUFHBS */ +#define FLEXIO_SHIFTBUFHBS_COUNT (4U) + + +/*! + * @} + */ /* end of group FLEXIO_Register_Masks */ + + +/* FLEXIO - Peripheral instance base addresses */ +/** Peripheral FLEXIO0 base address */ +#define FLEXIO0_BASE (0x40099000u) +/** Peripheral FLEXIO0 base pointer */ +#define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) +/** Array initializer of FLEXIO peripheral base addresses */ +#define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } +/** Array initializer of FLEXIO peripheral base pointers */ +#define FLEXIO_BASE_PTRS { FLEXIO0 } +/** Interrupt vectors for the FLEXIO peripheral type */ +#define FLEXIO_IRQS { FLEXIO_IRQn } + +/*! + * @} + */ /* end of group FLEXIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer + * @{ + */ + +/** FMC - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[32]; + __IO uint32_t REMAP; /**< Data Remap, offset: 0x20 */ +} FMC_Type; + +/* ---------------------------------------------------------------------------- + -- FMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMC_Register_Masks FMC Register Masks + * @{ + */ + +/*! @name REMAP - Data Remap */ +/*! @{ */ + +#define FMC_REMAP_REMAPLK_MASK (0x1U) +#define FMC_REMAP_REMAPLK_SHIFT (0U) +/*! REMAPLK - Remap Lock Enable + * 0b1..Lock enabled: cannot write to REMAP + * 0b0..Lock disabled: can write to REMAP + */ +#define FMC_REMAP_REMAPLK(x) (((uint32_t)(((uint32_t)(x)) << FMC_REMAP_REMAPLK_SHIFT)) & FMC_REMAP_REMAPLK_MASK) + +#define FMC_REMAP_LIM_MASK (0x7F0000U) +#define FMC_REMAP_LIM_SHIFT (16U) +/*! LIM - LIM Remapping Address */ +#define FMC_REMAP_LIM(x) (((uint32_t)(((uint32_t)(x)) << FMC_REMAP_LIM_SHIFT)) & FMC_REMAP_LIM_MASK) + +#define FMC_REMAP_LIMDP_MASK (0x7F000000U) +#define FMC_REMAP_LIMDP_SHIFT (24U) +/*! LIMDP - LIMDP Remapping Address */ +#define FMC_REMAP_LIMDP(x) (((uint32_t)(((uint32_t)(x)) << FMC_REMAP_LIMDP_SHIFT)) & FMC_REMAP_LIMDP_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FMC_Register_Masks */ + + +/* FMC - Peripheral instance base addresses */ +/** Peripheral FMC0 base address */ +#define FMC0_BASE (0x40094000u) +/** Peripheral FMC0 base pointer */ +#define FMC0 ((FMC_Type *)FMC0_BASE) +/** Array initializer of FMC peripheral base addresses */ +#define FMC_BASE_ADDRS { FMC0_BASE } +/** Array initializer of FMC peripheral base pointers */ +#define FMC_BASE_PTRS { FMC0 } + +/*! + * @} + */ /* end of group FMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FMU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMU_Peripheral_Access_Layer FMU Peripheral Access Layer + * @{ + */ + +/** FMU - Register Layout Typedef */ +typedef struct { + __IO uint32_t FSTAT; /**< Flash Status Register, offset: 0x0 */ + __IO uint32_t FCNFG; /**< Flash Configuration Register, offset: 0x4 */ + __IO uint32_t FCTRL; /**< Flash Control Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t FCCOB[8]; /**< Flash Common Command Object Registers, array offset: 0x10, array step: 0x4 */ +} FMU_Type; + +/* ---------------------------------------------------------------------------- + -- FMU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMU_Register_Masks FMU Register Masks + * @{ + */ + +/*! @name FSTAT - Flash Status Register */ +/*! @{ */ + +#define FMU_FSTAT_FAIL_MASK (0x1U) +#define FMU_FSTAT_FAIL_SHIFT (0U) +/*! FAIL - Command Fail Flag + * 0b0..Error not detected + * 0b1..Error detected + */ +#define FMU_FSTAT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_FAIL_SHIFT)) & FMU_FSTAT_FAIL_MASK) + +#define FMU_FSTAT_CMDABT_MASK (0x4U) +#define FMU_FSTAT_CMDABT_SHIFT (2U) +/*! CMDABT - Command Abort Flag + * 0b0..No command abort detected + * 0b1..Command abort detected + */ +#define FMU_FSTAT_CMDABT(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDABT_SHIFT)) & FMU_FSTAT_CMDABT_MASK) + +#define FMU_FSTAT_PVIOL_MASK (0x10U) +#define FMU_FSTAT_PVIOL_SHIFT (4U) +/*! PVIOL - Command Protection Violation Flag + * 0b0..No protection violation detected + * 0b1..Protection violation detected + */ +#define FMU_FSTAT_PVIOL(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PVIOL_SHIFT)) & FMU_FSTAT_PVIOL_MASK) + +#define FMU_FSTAT_ACCERR_MASK (0x20U) +#define FMU_FSTAT_ACCERR_SHIFT (5U) +/*! ACCERR - Command Access Error Flag + * 0b0..No access error detected + * 0b1..Access error detected + */ +#define FMU_FSTAT_ACCERR(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_ACCERR_SHIFT)) & FMU_FSTAT_ACCERR_MASK) + +#define FMU_FSTAT_CWSABT_MASK (0x40U) +#define FMU_FSTAT_CWSABT_SHIFT (6U) +/*! CWSABT - Command Write Sequence Abort Flag + * 0b0..Command write sequence not aborted + * 0b1..Command write sequence aborted + */ +#define FMU_FSTAT_CWSABT(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CWSABT_SHIFT)) & FMU_FSTAT_CWSABT_MASK) + +#define FMU_FSTAT_CCIF_MASK (0x80U) +#define FMU_FSTAT_CCIF_SHIFT (7U) +/*! CCIF - Command Complete Interrupt Flag + * 0b0..Flash command, initialization, or power mode recovery in progress + * 0b1..Flash command, initialization, or power mode recovery has completed + */ +#define FMU_FSTAT_CCIF(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CCIF_SHIFT)) & FMU_FSTAT_CCIF_MASK) + +#define FMU_FSTAT_CMDPRT_MASK (0x300U) +#define FMU_FSTAT_CMDPRT_SHIFT (8U) +/*! CMDPRT - Command protection level + * 0b00..Secure, normal access + * 0b01..Secure, privileged access + * 0b10..Nonsecure, normal access + * 0b11..Nonsecure, privileged access + */ +#define FMU_FSTAT_CMDPRT(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDPRT_SHIFT)) & FMU_FSTAT_CMDPRT_MASK) + +#define FMU_FSTAT_CMDP_MASK (0x800U) +#define FMU_FSTAT_CMDP_SHIFT (11U) +/*! CMDP - Command protection status flag + * 0b0..Command protection level and domain ID are stale + * 0b1..Command protection level (CMDPRT) and domain ID (CMDDID) are set + */ +#define FMU_FSTAT_CMDP(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDP_SHIFT)) & FMU_FSTAT_CMDP_MASK) + +#define FMU_FSTAT_CMDDID_MASK (0xF000U) +#define FMU_FSTAT_CMDDID_SHIFT (12U) +/*! CMDDID - Command domain ID */ +#define FMU_FSTAT_CMDDID(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_CMDDID_SHIFT)) & FMU_FSTAT_CMDDID_MASK) + +#define FMU_FSTAT_DFDIF_MASK (0x10000U) +#define FMU_FSTAT_DFDIF_SHIFT (16U) +/*! DFDIF - Double Bit Fault Detect Interrupt Flag + * 0b0..Double bit fault not detected during a valid flash read access + * 0b1..Double bit fault detected (or FCTRL[FDFD] is set) during a valid flash read access + */ +#define FMU_FSTAT_DFDIF(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_DFDIF_SHIFT)) & FMU_FSTAT_DFDIF_MASK) + +#define FMU_FSTAT_SALV_USED_MASK (0x20000U) +#define FMU_FSTAT_SALV_USED_SHIFT (17U) +/*! SALV_USED - Salvage Used for Erase operation + * 0b0..Salvage not used during last operation + * 0b1..Salvage used during the last erase operation + */ +#define FMU_FSTAT_SALV_USED(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_SALV_USED_SHIFT)) & FMU_FSTAT_SALV_USED_MASK) + +#define FMU_FSTAT_PEWEN_MASK (0x3000000U) +#define FMU_FSTAT_PEWEN_SHIFT (24U) +/*! PEWEN - Program-Erase Write Enable Control + * 0b00..Writes are not enabled + * 0b01..Writes are enabled for one flash or IFR phrase (phrase programming, sector erase) + * 0b10..Writes are enabled for one flash or IFR page (page programming) + * 0b11..Reserved + */ +#define FMU_FSTAT_PEWEN(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PEWEN_SHIFT)) & FMU_FSTAT_PEWEN_MASK) + +#define FMU_FSTAT_PERDY_MASK (0x80000000U) +#define FMU_FSTAT_PERDY_SHIFT (31U) +/*! PERDY - Program-Erase Ready Control/Status Flag + * 0b0..Program or sector erase command operation not stalled + * 0b1..Program or sector erase command operation ready to execute + */ +#define FMU_FSTAT_PERDY(x) (((uint32_t)(((uint32_t)(x)) << FMU_FSTAT_PERDY_SHIFT)) & FMU_FSTAT_PERDY_MASK) +/*! @} */ + +/*! @name FCNFG - Flash Configuration Register */ +/*! @{ */ + +#define FMU_FCNFG_CCIE_MASK (0x80U) +#define FMU_FCNFG_CCIE_SHIFT (7U) +/*! CCIE - Command Complete Interrupt Enable + * 0b0..Command complete interrupt disabled + * 0b1..Command complete interrupt enabled + */ +#define FMU_FCNFG_CCIE(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_CCIE_SHIFT)) & FMU_FCNFG_CCIE_MASK) + +#define FMU_FCNFG_ERSREQ_MASK (0x100U) +#define FMU_FCNFG_ERSREQ_SHIFT (8U) +/*! ERSREQ - Mass Erase Request + * 0b0..No request or request complete + * 0b1..Request to run the Mass Erase operation + */ +#define FMU_FCNFG_ERSREQ(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSREQ_SHIFT)) & FMU_FCNFG_ERSREQ_MASK) + +#define FMU_FCNFG_DFDIE_MASK (0x10000U) +#define FMU_FCNFG_DFDIE_SHIFT (16U) +/*! DFDIE - Double Bit Fault Detect Interrupt Enable + * 0b0..Double bit fault detect interrupt disabled + * 0b1..Double bit fault detect interrupt enabled + */ +#define FMU_FCNFG_DFDIE(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_DFDIE_SHIFT)) & FMU_FCNFG_DFDIE_MASK) + +#define FMU_FCNFG_ERSIEN0_MASK (0xF000000U) +#define FMU_FCNFG_ERSIEN0_SHIFT (24U) +/*! ERSIEN0 - Erase IFR Sector Enable - Block 0 + * 0b0000..Block 0 IFR Sector X is protected from erase by ERSSCR command + * 0b0001..Block 0 IFR Sector X is not protected from erase by ERSSCR command + */ +#define FMU_FCNFG_ERSIEN0(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN0_SHIFT)) & FMU_FCNFG_ERSIEN0_MASK) + +#define FMU_FCNFG_ERSIEN1_MASK (0xF0000000U) +#define FMU_FCNFG_ERSIEN1_SHIFT (28U) +/*! ERSIEN1 - Erase IFR Sector Enable - Block 1 (for dual block configs) + * 0b0000..Block 1 IFR Sector X is protected from erase by ERSSCR command + * 0b0001..Block 1 IFR Sector X is not protected from erase by ERSSCR command + */ +#define FMU_FCNFG_ERSIEN1(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCNFG_ERSIEN1_SHIFT)) & FMU_FCNFG_ERSIEN1_MASK) +/*! @} */ + +/*! @name FCTRL - Flash Control Register */ +/*! @{ */ + +#define FMU_FCTRL_RWSC_MASK (0xFU) +#define FMU_FCTRL_RWSC_SHIFT (0U) +/*! RWSC - Read Wait-State Control */ +#define FMU_FCTRL_RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_RWSC_SHIFT)) & FMU_FCTRL_RWSC_MASK) + +#define FMU_FCTRL_LSACTIVE_MASK (0x100U) +#define FMU_FCTRL_LSACTIVE_SHIFT (8U) +/*! LSACTIVE - Low speed active mode + * 0b0..Full speed active mode requested + * 0b1..Low speed active mode requested + */ +#define FMU_FCTRL_LSACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_LSACTIVE_SHIFT)) & FMU_FCTRL_LSACTIVE_MASK) + +#define FMU_FCTRL_FDFD_MASK (0x10000U) +#define FMU_FCTRL_FDFD_SHIFT (16U) +/*! FDFD - Force Double Bit Fault Detect + * 0b0..FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the platform flash controller + * 0b1..FSTAT[DFDIF] sets during any valid flash read access from the platform flash controller. An interrupt + * request is generated if the DFDIE bit is set. + */ +#define FMU_FCTRL_FDFD(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_FDFD_SHIFT)) & FMU_FCTRL_FDFD_MASK) + +#define FMU_FCTRL_ABTREQ_MASK (0x1000000U) +#define FMU_FCTRL_ABTREQ_SHIFT (24U) +/*! ABTREQ - Abort Request + * 0b0..No request to abort a command write sequence + * 0b1..Request to abort a command write sequence + */ +#define FMU_FCTRL_ABTREQ(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCTRL_ABTREQ_SHIFT)) & FMU_FCTRL_ABTREQ_MASK) +/*! @} */ + +/*! @name FCCOB - Flash Common Command Object Registers */ +/*! @{ */ + +#define FMU_FCCOB_CCOBn_MASK (0xFFFFFFFFU) +#define FMU_FCCOB_CCOBn_SHIFT (0U) +/*! CCOBn - CCOBn */ +#define FMU_FCCOB_CCOBn(x) (((uint32_t)(((uint32_t)(x)) << FMU_FCCOB_CCOBn_SHIFT)) & FMU_FCCOB_CCOBn_MASK) +/*! @} */ + +/* The count of FMU_FCCOB */ +#define FMU_FCCOB_COUNT (8U) + + +/*! + * @} + */ /* end of group FMU_Register_Masks */ + + +/* FMU - Peripheral instance base addresses */ +/** Peripheral FMU0 base address */ +#define FMU0_BASE (0x40095000u) +/** Peripheral FMU0 base pointer */ +#define FMU0 ((FMU_Type *)FMU0_BASE) +/** Array initializer of FMU peripheral base addresses */ +#define FMU_BASE_ADDRS { FMU0_BASE } +/** Array initializer of FMU peripheral base pointers */ +#define FMU_BASE_PTRS { FMU0 } + +/*! + * @} + */ /* end of group FMU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FMUTEST Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMUTEST_Peripheral_Access_Layer FMUTEST Peripheral Access Layer + * @{ + */ + +/** FMUTEST - Register Layout Typedef */ +typedef struct { + __IO uint32_t FSTAT; /**< Flash Status Register, offset: 0x0 */ + __IO uint32_t FCNFG; /**< Flash Configuration Register, offset: 0x4 */ + __IO uint32_t FCTRL; /**< Flash Control Register, offset: 0x8 */ + __I uint32_t FTEST; /**< Flash Test Register, offset: 0xC */ + __IO uint32_t FCCOB0; /**< Flash Command Control 0 Register, offset: 0x10 */ + __IO uint32_t FCCOB1; /**< Flash Command Control 1 Register, offset: 0x14 */ + __IO uint32_t FCCOB2; /**< Flash Command Control 2 Register, offset: 0x18 */ + __IO uint32_t FCCOB3; /**< Flash Command Control 3 Register, offset: 0x1C */ + __IO uint32_t FCCOB4; /**< Flash Command Control 4 Register, offset: 0x20 */ + __IO uint32_t FCCOB5; /**< Flash Command Control 5 Register, offset: 0x24 */ + __IO uint32_t FCCOB6; /**< Flash Command Control 6 Register, offset: 0x28 */ + __IO uint32_t FCCOB7; /**< Flash Command Control 7 Register, offset: 0x2C */ + uint8_t RESERVED_0[208]; + __IO uint32_t RESET_STATUS; /**< FMU Initialization Tracking Register, offset: 0x100 */ + __IO uint32_t MCTL; /**< FMU Control Register, offset: 0x104 */ + __I uint32_t BSEL_GEN; /**< FMU Block Select Generation Register, offset: 0x108 */ + __IO uint32_t PWR_OPT; /**< Power Mode Options Register, offset: 0x10C */ + __I uint32_t CMD_CHECK; /**< FMU Command Check Register, offset: 0x110 */ + uint8_t RESERVED_1[12]; + __IO uint32_t BSEL; /**< FMU Block Select Register, offset: 0x120 */ + __IO uint32_t MSIZE; /**< FMU Memory Size Register, offset: 0x124 */ + __IO uint32_t FLASH_RD_ADD; /**< Flash Read Address Register, offset: 0x128 */ + uint8_t RESERVED_2[4]; + __IO uint32_t FLASH_STOP_ADD; /**< Flash Stop Address Register, offset: 0x130 */ + __IO uint32_t FLASH_RD_CTRL; /**< Flash Read Control Register, offset: 0x134 */ + __IO uint32_t MM_ADDR; /**< Memory Map Address Register, offset: 0x138 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MM_WDATA; /**< Memory Map Write Data Register, offset: 0x140 */ + __IO uint32_t MM_CTL; /**< Memory Map Control Register, offset: 0x144 */ + __IO uint32_t UINT_CTL; /**< User Interface Control Register, offset: 0x148 */ + __IO uint32_t RD_DATA0; /**< Read Data 0 Register, offset: 0x14C */ + __IO uint32_t RD_DATA1; /**< Read Data 1 Register, offset: 0x150 */ + __IO uint32_t RD_DATA2; /**< Read Data 2 Register, offset: 0x154 */ + __IO uint32_t RD_DATA3; /**< Read Data 3 Register, offset: 0x158 */ + __IO uint32_t PARITY; /**< Parity Register, offset: 0x15C */ + __IO uint32_t RD_PATH_CTRL_STATUS; /**< Read Path Control and Status Register, offset: 0x160 */ + __IO uint32_t SMW_DIN0; /**< SMW DIN 0 Register, offset: 0x164 */ + __IO uint32_t SMW_DIN1; /**< SMW DIN 1 Register, offset: 0x168 */ + __IO uint32_t SMW_DIN2; /**< SMW DIN 2 Register, offset: 0x16C */ + __IO uint32_t SMW_DIN3; /**< SMW DIN 3 Register, offset: 0x170 */ + __IO uint32_t SMW_ADDR; /**< SMW Address Register, offset: 0x174 */ + __IO uint32_t SMW_CMD_WAIT; /**< SMW Command and Wait Register, offset: 0x178 */ + __I uint32_t SMW_STATUS; /**< SMW Status Register, offset: 0x17C */ + __IO uint32_t SOCTRIM0_0; /**< SoC Trim Phrase 0 Word 0 Register, offset: 0x180 */ + __IO uint32_t SOCTRIM0_1; /**< SoC Trim Phrase 0 Word 1 Register, offset: 0x184 */ + __IO uint32_t SOCTRIM0_2; /**< SoC Trim Phrase 0 Word 2 Register, offset: 0x188 */ + __IO uint32_t SOCTRIM0_3; /**< SoC Trim Phrase 0 Word 3 Register, offset: 0x18C */ + __IO uint32_t SOCTRIM1_0; /**< SoC Trim Phrase 1 Word 0 Register, offset: 0x190 */ + __IO uint32_t SOCTRIM1_1; /**< SoC Trim Phrase 1 Word 1 Register, offset: 0x194 */ + __IO uint32_t SOCTRIM1_2; /**< SoC Trim Phrase 1 Word 2 Register, offset: 0x198 */ + __IO uint32_t SOCTRIM1_3; /**< SoC Trim Phrase 1 Word 3 Register, offset: 0x19C */ + __IO uint32_t SOCTRIM2_0; /**< SoC Trim Phrase 2 Word 0 Register, offset: 0x1A0 */ + __IO uint32_t SOCTRIM2_1; /**< SoC Trim Phrase 2 Word 1 Register, offset: 0x1A4 */ + __IO uint32_t SOCTRIM2_2; /**< SoC Trim Phrase 2 Word 2 Register, offset: 0x1A8 */ + __IO uint32_t SOCTRIM2_3; /**< SoC Trim Phrase 2 Word 3 Register, offset: 0x1AC */ + __IO uint32_t SOCTRIM3_0; /**< SoC Trim Phrase 3 Word 0 Register, offset: 0x1B0 */ + __IO uint32_t SOCTRIM3_1; /**< SoC Trim Phrase 3 Word 1 Register, offset: 0x1B4 */ + __IO uint32_t SOCTRIM3_2; /**< SoC Trim Phrase 3 Word 2 Register, offset: 0x1B8 */ + __IO uint32_t SOCTRIM3_3; /**< SoC Trim Phrase 3 Word 3 Register, offset: 0x1BC */ + __IO uint32_t SOCTRIM4_0; /**< SoC Trim Phrase 4 Word 0 Register, offset: 0x1C0 */ + __IO uint32_t SOCTRIM4_1; /**< SoC Trim Phrase 4 Word 1 Register, offset: 0x1C4 */ + __IO uint32_t SOCTRIM4_2; /**< SoC Trim Phrase 4 Word 2 Register, offset: 0x1C8 */ + __IO uint32_t SOCTRIM4_3; /**< SoC Trim Phrase 4 Word 3 Register, offset: 0x1CC */ + __IO uint32_t SOCTRIM5_0; /**< SoC Trim Phrase 5 Word 0 Register, offset: 0x1D0 */ + __IO uint32_t SOCTRIM5_1; /**< SoC Trim Phrase 5 Word 1 Register, offset: 0x1D4 */ + __IO uint32_t SOCTRIM5_2; /**< SoC Trim Phrase 5 Word 2 Register, offset: 0x1D8 */ + __IO uint32_t SOCTRIM5_3; /**< SoC Trim Phrase 5 Word 3 Register, offset: 0x1DC */ + __IO uint32_t SOCTRIM6_0; /**< SoC Trim Phrase 6 Word 0 Register, offset: 0x1E0 */ + __IO uint32_t SOCTRIM6_1; /**< SoC Trim Phrase 6 Word 1 Register, offset: 0x1E4 */ + __IO uint32_t SOCTRIM6_2; /**< SoC Trim Phrase 6 Word 2 Register, offset: 0x1E8 */ + __IO uint32_t SOCTRIM6_3; /**< SoC Trim Phrase 6 Word 3 Register, offset: 0x1EC */ + __IO uint32_t SOCTRIM7_0; /**< SoC Trim Phrase 7 Word 0 Register, offset: 0x1F0 */ + __IO uint32_t SOCTRIM7_1; /**< SoC Trim Phrase 7 Word 1 Register, offset: 0x1F4 */ + __IO uint32_t SOCTRIM7_2; /**< SoC Trim Phrase 7 Word 2 Register, offset: 0x1F8 */ + __IO uint32_t SOCTRIM7_3; /**< SoC Trim Phrase 7 Word 3 Register, offset: 0x1FC */ + uint8_t RESERVED_4[4]; + __IO uint32_t R_IP_CONFIG; /**< BIST Configuration Register, offset: 0x204 */ + __IO uint32_t R_TESTCODE; /**< BIST Test Code Register, offset: 0x208 */ + __IO uint32_t R_DFT_CTRL; /**< BIST DFT Control Register, offset: 0x20C */ + __IO uint32_t R_ADR_CTRL; /**< BIST Address Control Register, offset: 0x210 */ + __IO uint32_t R_DATA_CTRL0; /**< BIST Data Control 0 Register, offset: 0x214 */ + __IO uint32_t R_PIN_CTRL; /**< BIST Pin Control Register, offset: 0x218 */ + __IO uint32_t R_CNT_LOOP_CTRL; /**< BIST Loop Count Control Register, offset: 0x21C */ + __IO uint32_t R_TIMER_CTRL; /**< BIST Timer Control Register, offset: 0x220 */ + __IO uint32_t R_TEST_CTRL; /**< BIST Test Control Register, offset: 0x224 */ + __O uint32_t R_ABORT_LOOP; /**< BIST Abort Loop Register, offset: 0x228 */ + __I uint32_t R_ADR_QUERY; /**< BIST Address Query Register, offset: 0x22C */ + __I uint32_t R_DOUT_QUERY0; /**< BIST DOUT Query 0 Register, offset: 0x230 */ + uint8_t RESERVED_5[8]; + __I uint32_t R_SMW_QUERY; /**< BIST SMW Query Register, offset: 0x23C */ + __IO uint32_t R_SMW_SETTING0; /**< BIST SMW Setting 0 Register, offset: 0x240 */ + __IO uint32_t R_SMW_SETTING1; /**< BIST SMW Setting 1 Register, offset: 0x244 */ + __IO uint32_t R_SMP_WHV0; /**< BIST SMP WHV Setting 0 Register, offset: 0x248 */ + __IO uint32_t R_SMP_WHV1; /**< BIST SMP WHV Setting 1 Register, offset: 0x24C */ + __IO uint32_t R_SME_WHV0; /**< BIST SME WHV Setting 0 Register, offset: 0x250 */ + __IO uint32_t R_SME_WHV1; /**< BIST SME WHV Setting 1 Register, offset: 0x254 */ + __IO uint32_t R_SMW_SETTING2; /**< BIST SMW Setting 2 Register, offset: 0x258 */ + __I uint32_t R_D_MISR0; /**< BIST DIN MISR 0 Register, offset: 0x25C */ + __I uint32_t R_A_MISR0; /**< BIST Address MISR 0 Register, offset: 0x260 */ + __I uint32_t R_C_MISR0; /**< BIST Control MISR 0 Register, offset: 0x264 */ + __IO uint32_t R_SMW_SETTING3; /**< BIST SMW Setting 3 Register, offset: 0x268 */ + __IO uint32_t R_DATA_CTRL1; /**< BIST Data Control 1 Register, offset: 0x26C */ + __IO uint32_t R_DATA_CTRL2; /**< BIST Data Control 2 Register, offset: 0x270 */ + __IO uint32_t R_DATA_CTRL3; /**< BIST Data Control 3 Register, offset: 0x274 */ + uint8_t RESERVED_6[8]; + __I uint32_t R_REPAIR0_0; /**< BIST Repair 0 for Block 0 Register, offset: 0x280 */ + __I uint32_t R_REPAIR0_1; /**< BIST Repair 1 Block 0 Register, offset: 0x284 */ + __I uint32_t R_REPAIR1_0; /**< BIST Repair 0 Block 1 Register, offset: 0x288 */ + __I uint32_t R_REPAIR1_1; /**< BIST Repair 1 Block 1 Register, offset: 0x28C */ + uint8_t RESERVED_7[132]; + __IO uint32_t R_DATA_CTRL0_EX; /**< BIST Data Control 0 Extension Register, offset: 0x314 */ + uint8_t RESERVED_8[8]; + __IO uint32_t R_TIMER_CTRL_EX; /**< BIST Timer Control Extension Register, offset: 0x320 */ + uint8_t RESERVED_9[12]; + __I uint32_t R_DOUT_QUERY1; /**< BIST DOUT Query 1 Register, offset: 0x330 */ + uint8_t RESERVED_10[40]; + __I uint32_t R_D_MISR1; /**< BIST DIN MISR 1 Register, offset: 0x35C */ + __I uint32_t R_A_MISR1; /**< BIST Address MISR 1 Register, offset: 0x360 */ + __I uint32_t R_C_MISR1; /**< BIST Control MISR 1 Register, offset: 0x364 */ + uint8_t RESERVED_11[4]; + __IO uint32_t R_DATA_CTRL1_EX; /**< BIST Data Control 1 Extension Register, offset: 0x36C */ + __IO uint32_t R_DATA_CTRL2_EX; /**< BIST Data Control 2 Extension Register, offset: 0x370 */ + __IO uint32_t R_DATA_CTRL3_EX; /**< BIST Data Control 3 Extension Register, offset: 0x374 */ + uint8_t RESERVED_12[136]; + __IO uint32_t SMW_TIMER_OPTION; /**< SMW Timer Option Register, offset: 0x400 */ + __IO uint32_t SMW_SETTING_OPTION0; /**< SMW Setting Option 0 Register, offset: 0x404 */ + __IO uint32_t SMW_SETTING_OPTION2; /**< SMW Setting Option 2 Register, offset: 0x408 */ + __IO uint32_t SMW_SETTING_OPTION3; /**< SMW Setting Option 3 Register, offset: 0x40C */ + __IO uint32_t SMW_SMP_WHV_OPTION0; /**< SMW SMP WHV Option 0 Register, offset: 0x410 */ + __IO uint32_t SMW_SME_WHV_OPTION0; /**< SMW SME WHV Option 0 Register, offset: 0x414 */ + __IO uint32_t SMW_SETTING_OPTION1; /**< SMW Setting Option 1 Register, offset: 0x418 */ + __IO uint32_t SMW_SMP_WHV_OPTION1; /**< SMW SMP WHV Option 1 Register, offset: 0x41C */ + __IO uint32_t SMW_SME_WHV_OPTION1; /**< SMW SME WHV Option 1 Register, offset: 0x420 */ + uint8_t RESERVED_13[220]; + __IO uint32_t REPAIR0_0; /**< FMU Repair 0 Block 0 Register, offset: 0x500 */ + __IO uint32_t REPAIR0_1; /**< FMU Repair 1 Block 0 Register, offset: 0x504 */ + __IO uint32_t REPAIR1_0; /**< FMU Repair 0 Block 1 Register, offset: 0x508 */ + __IO uint32_t REPAIR1_1; /**< FMU Repair 1 Block 1 Register, offset: 0x50C */ + uint8_t RESERVED_14[240]; + __IO uint32_t SMW_HB_SIGNALS; /**< SMW HB Signals Register, offset: 0x600 */ + __IO uint32_t BIST_DUMP_CTRL; /**< BIST Datadump Control Register, offset: 0x604 */ + uint8_t RESERVED_15[4]; + __IO uint32_t ATX_PIN_CTRL; /**< ATX Pin Control Register, offset: 0x60C */ + __IO uint32_t FAILCNT; /**< Fail Count Register, offset: 0x610 */ + __IO uint32_t PGM_PULSE_CNT0; /**< Block 0 Program Pulse Count Register, offset: 0x614 */ + __IO uint32_t PGM_PULSE_CNT1; /**< Block 1 Program Pulse Count Register, offset: 0x618 */ + __IO uint32_t ERS_PULSE_CNT; /**< Erase Pulse Count Register, offset: 0x61C */ + __IO uint32_t MAX_PULSE_CNT; /**< Maximum Pulse Count Register, offset: 0x620 */ + __IO uint32_t PORT_CTRL; /**< Port Control Register, offset: 0x624 */ +} FMUTEST_Type; + +/* ---------------------------------------------------------------------------- + -- FMUTEST Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMUTEST_Register_Masks FMUTEST Register Masks + * @{ + */ + +/*! @name FSTAT - Flash Status Register */ +/*! @{ */ + +#define FMUTEST_FSTAT_FAIL_MASK (0x1U) +#define FMUTEST_FSTAT_FAIL_SHIFT (0U) +/*! FAIL - Command Fail Flag + * 0b0..Error not detected + * 0b1..Error detected + */ +#define FMUTEST_FSTAT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_FAIL_SHIFT)) & FMUTEST_FSTAT_FAIL_MASK) + +#define FMUTEST_FSTAT_CMDABT_MASK (0x4U) +#define FMUTEST_FSTAT_CMDABT_SHIFT (2U) +/*! CMDABT - Command Abort Flag + * 0b0..No command abort detected + * 0b1..Command abort detected + */ +#define FMUTEST_FSTAT_CMDABT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDABT_SHIFT)) & FMUTEST_FSTAT_CMDABT_MASK) + +#define FMUTEST_FSTAT_PVIOL_MASK (0x10U) +#define FMUTEST_FSTAT_PVIOL_SHIFT (4U) +/*! PVIOL - Command Protection Violation Flag + * 0b0..No protection violation detected + * 0b1..Protection violation detected + */ +#define FMUTEST_FSTAT_PVIOL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_PVIOL_SHIFT)) & FMUTEST_FSTAT_PVIOL_MASK) + +#define FMUTEST_FSTAT_ACCERR_MASK (0x20U) +#define FMUTEST_FSTAT_ACCERR_SHIFT (5U) +/*! ACCERR - Command Access Error Flag + * 0b0..No access error detected + * 0b1..Access error detected + */ +#define FMUTEST_FSTAT_ACCERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_ACCERR_SHIFT)) & FMUTEST_FSTAT_ACCERR_MASK) + +#define FMUTEST_FSTAT_CWSABT_MASK (0x40U) +#define FMUTEST_FSTAT_CWSABT_SHIFT (6U) +/*! CWSABT - Command Write Sequence Abort Flag + * 0b0..Command write sequence not aborted + * 0b1..Command write sequence aborted + */ +#define FMUTEST_FSTAT_CWSABT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CWSABT_SHIFT)) & FMUTEST_FSTAT_CWSABT_MASK) + +#define FMUTEST_FSTAT_CCIF_MASK (0x80U) +#define FMUTEST_FSTAT_CCIF_SHIFT (7U) +/*! CCIF - Command Complete Interrupt Flag + * 0b0..Flash command or initialization in progress + * 0b1..Flash command or initialization has completed + */ +#define FMUTEST_FSTAT_CCIF(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CCIF_SHIFT)) & FMUTEST_FSTAT_CCIF_MASK) + +#define FMUTEST_FSTAT_CMDPRT_MASK (0x300U) +#define FMUTEST_FSTAT_CMDPRT_SHIFT (8U) +/*! CMDPRT - Command Protection Level + * 0b00..Secure, normal access + * 0b01..Secure, privileged access + * 0b10..Nonsecure, normal access + * 0b11..Nonsecure, privileged access + */ +#define FMUTEST_FSTAT_CMDPRT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDPRT_SHIFT)) & FMUTEST_FSTAT_CMDPRT_MASK) + +#define FMUTEST_FSTAT_CMDP_MASK (0x800U) +#define FMUTEST_FSTAT_CMDP_SHIFT (11U) +/*! CMDP - Command Protection Status Flag + * 0b0..Command protection level and domain ID are stale + * 0b1..Command protection level (CMDPRT) and domain ID (CMDDID) are set + */ +#define FMUTEST_FSTAT_CMDP(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDP_SHIFT)) & FMUTEST_FSTAT_CMDP_MASK) + +#define FMUTEST_FSTAT_CMDDID_MASK (0xF000U) +#define FMUTEST_FSTAT_CMDDID_SHIFT (12U) +/*! CMDDID - Command Domain ID */ +#define FMUTEST_FSTAT_CMDDID(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_CMDDID_SHIFT)) & FMUTEST_FSTAT_CMDDID_MASK) + +#define FMUTEST_FSTAT_DFDIF_MASK (0x10000U) +#define FMUTEST_FSTAT_DFDIF_SHIFT (16U) +/*! DFDIF - Double Bit Fault Detect Interrupt Flag + * 0b0..Double bit fault not detected during a valid flash read access from the FMC + * 0b1..Double bit fault detected (or FCTRL[FDFD] is set) during a valid flash read access from the FMC + */ +#define FMUTEST_FSTAT_DFDIF(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_DFDIF_SHIFT)) & FMUTEST_FSTAT_DFDIF_MASK) + +#define FMUTEST_FSTAT_SALV_USED_MASK (0x20000U) +#define FMUTEST_FSTAT_SALV_USED_SHIFT (17U) +/*! SALV_USED - Salvage Used for Erase operation + * 0b0..Salvage not used during the last operation + * 0b1..Salvage used during the last erase operation + */ +#define FMUTEST_FSTAT_SALV_USED(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_SALV_USED_SHIFT)) & FMUTEST_FSTAT_SALV_USED_MASK) + +#define FMUTEST_FSTAT_PEWEN_MASK (0x3000000U) +#define FMUTEST_FSTAT_PEWEN_SHIFT (24U) +/*! PEWEN - Program-Erase Write Enable Control + * 0b00..Writes are not enabled + * 0b01..Writes are enabled for one flash or IFR phrase (phrase programming, sector erase) + * 0b10..Writes are enabled for one flash or IFR page (page programming) + * 0b11..Reserved + */ +#define FMUTEST_FSTAT_PEWEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_PEWEN_SHIFT)) & FMUTEST_FSTAT_PEWEN_MASK) + +#define FMUTEST_FSTAT_PERDY_MASK (0x80000000U) +#define FMUTEST_FSTAT_PERDY_SHIFT (31U) +/*! PERDY - Program/Erase Ready Control/Status Flag + * 0b0..Program or sector erase command operation is not stalled + * 0b1..Program or sector erase command operation is stalled + */ +#define FMUTEST_FSTAT_PERDY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FSTAT_PERDY_SHIFT)) & FMUTEST_FSTAT_PERDY_MASK) +/*! @} */ + +/*! @name FCNFG - Flash Configuration Register */ +/*! @{ */ + +#define FMUTEST_FCNFG_CCIE_MASK (0x80U) +#define FMUTEST_FCNFG_CCIE_SHIFT (7U) +/*! CCIE - Command Complete Interrupt Enable + * 0b0..Command complete interrupt disabled + * 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. + */ +#define FMUTEST_FCNFG_CCIE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_CCIE_SHIFT)) & FMUTEST_FCNFG_CCIE_MASK) + +#define FMUTEST_FCNFG_ERSREQ_MASK (0x100U) +#define FMUTEST_FCNFG_ERSREQ_SHIFT (8U) +/*! ERSREQ - Mass Erase (Erase All) Request + * 0b0..No request or request complete + * 0b1..Request to run the Mass Erase operation + */ +#define FMUTEST_FCNFG_ERSREQ(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_ERSREQ_SHIFT)) & FMUTEST_FCNFG_ERSREQ_MASK) + +#define FMUTEST_FCNFG_DFDIE_MASK (0x10000U) +#define FMUTEST_FCNFG_DFDIE_SHIFT (16U) +/*! DFDIE - Double Bit Fault Detect Interrupt Enable + * 0b0..Double bit fault detect interrupt disabled + * 0b1..Double bit fault detect interrupt enabled; an interrupt request is generated whenever the FSTAT[DFDIF] flag is set + */ +#define FMUTEST_FCNFG_DFDIE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_DFDIE_SHIFT)) & FMUTEST_FCNFG_DFDIE_MASK) + +#define FMUTEST_FCNFG_ERSIEN0_MASK (0xF000000U) +#define FMUTEST_FCNFG_ERSIEN0_SHIFT (24U) +/*! ERSIEN0 - Erase IFR Sector Enable - Block 0 + * 0b0000..Block 0 IFR Sector X is protected from erase by ERSSCR command + * 0b0001..Block 0 IFR Sector X is not protected from erase by ERSSCR command + */ +#define FMUTEST_FCNFG_ERSIEN0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_ERSIEN0_SHIFT)) & FMUTEST_FCNFG_ERSIEN0_MASK) + +#define FMUTEST_FCNFG_ERSIEN1_MASK (0xF0000000U) +#define FMUTEST_FCNFG_ERSIEN1_SHIFT (28U) +/*! ERSIEN1 - Erase IFR Sector Enable - Block 1 (for dual block configs) + * 0b0000..Block 1 IFR Sector X is protected from erase by ERSSCR command + * 0b0001..Block 1 IFR Sector X is not protected from erase by ERSSCR command + */ +#define FMUTEST_FCNFG_ERSIEN1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCNFG_ERSIEN1_SHIFT)) & FMUTEST_FCNFG_ERSIEN1_MASK) +/*! @} */ + +/*! @name FCTRL - Flash Control Register */ +/*! @{ */ + +#define FMUTEST_FCTRL_RWSC_MASK (0xFU) +#define FMUTEST_FCTRL_RWSC_SHIFT (0U) +/*! RWSC - Read Wait-State Control + * 0b0000..no additional wait-states are added (single cycle access) + * 0b0001..1 additional wait-state is added + * 0b0010..2 additional wait-states are added + * 0b0011..3 additional wait-states are added + * 0b0100..4 additional wait-states are added + * 0b0101..5 additional wait-states are added + * 0b0110..6 additional wait-states are added + * 0b0111..7 additional wait-states are added + * 0b1000..8 additional wait-states are added + * 0b1001..9 additional wait-states are added + * 0b1010..10 additional wait-states are added + * 0b1011..11 additional wait-states are added + * 0b1100..12 additional wait-states are added + * 0b1101..13 additional wait-states are added + * 0b1110..14 additional wait-states are added + * 0b1111..15 additional wait-states are added + */ +#define FMUTEST_FCTRL_RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_RWSC_SHIFT)) & FMUTEST_FCTRL_RWSC_MASK) + +#define FMUTEST_FCTRL_LSACTIVE_MASK (0x100U) +#define FMUTEST_FCTRL_LSACTIVE_SHIFT (8U) +/*! LSACTIVE - Low Speed Active Mode + * 0b0..Full speed active mode requested + * 0b1..Low speed active mode requested + */ +#define FMUTEST_FCTRL_LSACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_LSACTIVE_SHIFT)) & FMUTEST_FCTRL_LSACTIVE_MASK) + +#define FMUTEST_FCTRL_FDFD_MASK (0x10000U) +#define FMUTEST_FCTRL_FDFD_SHIFT (16U) +/*! FDFD - Force Double Bit Fault Detect + * 0b0..FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the FMC + * 0b1..FSTAT[DFDIF] sets during any valid flash read access from the FMC; an interrupt request is generated if the DFDIE bit is set + */ +#define FMUTEST_FCTRL_FDFD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_FDFD_SHIFT)) & FMUTEST_FCTRL_FDFD_MASK) + +#define FMUTEST_FCTRL_ABTREQ_MASK (0x1000000U) +#define FMUTEST_FCTRL_ABTREQ_SHIFT (24U) +/*! ABTREQ - Abort Request + * 0b0..No request to abort a command write sequence + * 0b1..Request to abort a command write sequence + */ +#define FMUTEST_FCTRL_ABTREQ(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCTRL_ABTREQ_SHIFT)) & FMUTEST_FCTRL_ABTREQ_MASK) +/*! @} */ + +/*! @name FTEST - Flash Test Register */ +/*! @{ */ + +#define FMUTEST_FTEST_TMECTL_MASK (0x1U) +#define FMUTEST_FTEST_TMECTL_SHIFT (0U) +/*! TMECTL - Test Mode Entry Control + * 0b0..FTEST register always reads 0 and writes to FTEST are ignored + * 0b1..FTEST register is readable and can be written to enable writability of TME + */ +#define FMUTEST_FTEST_TMECTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMECTL_SHIFT)) & FMUTEST_FTEST_TMECTL_MASK) + +#define FMUTEST_FTEST_TMEWR_MASK (0x2U) +#define FMUTEST_FTEST_TMEWR_SHIFT (1U) +/*! TMEWR - Test Mode Entry Writable + * 0b0..TME bit is not writable + * 0b1..TME bit is writable + */ +#define FMUTEST_FTEST_TMEWR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMEWR_SHIFT)) & FMUTEST_FTEST_TMEWR_MASK) + +#define FMUTEST_FTEST_TME_MASK (0x4U) +#define FMUTEST_FTEST_TME_SHIFT (2U) +/*! TME - Test Mode Entry + * 0b0..Test mode entry not requested + * 0b1..Test mode entry requested + */ +#define FMUTEST_FTEST_TME(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TME_SHIFT)) & FMUTEST_FTEST_TME_MASK) + +#define FMUTEST_FTEST_TMODE_MASK (0x8U) +#define FMUTEST_FTEST_TMODE_SHIFT (3U) +/*! TMODE - Test Mode Status + * 0b0..Test mode not active + * 0b1..Test mode active + */ +#define FMUTEST_FTEST_TMODE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMODE_SHIFT)) & FMUTEST_FTEST_TMODE_MASK) + +#define FMUTEST_FTEST_TMELOCK_MASK (0x10U) +#define FMUTEST_FTEST_TMELOCK_SHIFT (4U) +/*! TMELOCK - Test Mode Entry Lock + * 0b0..FTEST register not locked from accepting writes + * 0b1..FTEST register locked from accepting writes + */ +#define FMUTEST_FTEST_TMELOCK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FTEST_TMELOCK_SHIFT)) & FMUTEST_FTEST_TMELOCK_MASK) +/*! @} */ + +/*! @name FCCOB0 - Flash Command Control 0 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB0_CMDCODE_MASK (0xFFU) +#define FMUTEST_FCCOB0_CMDCODE_SHIFT (0U) +/*! CMDCODE - Command code */ +#define FMUTEST_FCCOB0_CMDCODE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB0_CMDCODE_SHIFT)) & FMUTEST_FCCOB0_CMDCODE_MASK) +/*! @} */ + +/*! @name FCCOB1 - Flash Command Control 1 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB1_CMDOPT_MASK (0xFFU) +#define FMUTEST_FCCOB1_CMDOPT_SHIFT (0U) +/*! CMDOPT - Command options */ +#define FMUTEST_FCCOB1_CMDOPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB1_CMDOPT_SHIFT)) & FMUTEST_FCCOB1_CMDOPT_MASK) +/*! @} */ + +/*! @name FCCOB2 - Flash Command Control 2 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB2_CMDADDR_MASK (0xFFFFFFFFU) +#define FMUTEST_FCCOB2_CMDADDR_SHIFT (0U) +/*! CMDADDR - Command starting address */ +#define FMUTEST_FCCOB2_CMDADDR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB2_CMDADDR_SHIFT)) & FMUTEST_FCCOB2_CMDADDR_MASK) +/*! @} */ + +/*! @name FCCOB3 - Flash Command Control 3 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB3_CMDADDRE_MASK (0xFFFFFFFFU) +#define FMUTEST_FCCOB3_CMDADDRE_SHIFT (0U) +/*! CMDADDRE - Command ending address */ +#define FMUTEST_FCCOB3_CMDADDRE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB3_CMDADDRE_SHIFT)) & FMUTEST_FCCOB3_CMDADDRE_MASK) +/*! @} */ + +/*! @name FCCOB4 - Flash Command Control 4 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB4_CMDDATA0_MASK (0xFFFFFFFFU) +#define FMUTEST_FCCOB4_CMDDATA0_SHIFT (0U) +/*! CMDDATA0 - Command data word 0 */ +#define FMUTEST_FCCOB4_CMDDATA0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB4_CMDDATA0_SHIFT)) & FMUTEST_FCCOB4_CMDDATA0_MASK) +/*! @} */ + +/*! @name FCCOB5 - Flash Command Control 5 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB5_CMDDATA1_MASK (0xFFFFFFFFU) +#define FMUTEST_FCCOB5_CMDDATA1_SHIFT (0U) +/*! CMDDATA1 - Command data word 1 */ +#define FMUTEST_FCCOB5_CMDDATA1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB5_CMDDATA1_SHIFT)) & FMUTEST_FCCOB5_CMDDATA1_MASK) +/*! @} */ + +/*! @name FCCOB6 - Flash Command Control 6 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB6_CMDDATA2_MASK (0xFFFFFFFFU) +#define FMUTEST_FCCOB6_CMDDATA2_SHIFT (0U) +/*! CMDDATA2 - Command data word 2 */ +#define FMUTEST_FCCOB6_CMDDATA2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB6_CMDDATA2_SHIFT)) & FMUTEST_FCCOB6_CMDDATA2_MASK) +/*! @} */ + +/*! @name FCCOB7 - Flash Command Control 7 Register */ +/*! @{ */ + +#define FMUTEST_FCCOB7_CMDDATA3_MASK (0xFFFFFFFFU) +#define FMUTEST_FCCOB7_CMDDATA3_SHIFT (0U) +/*! CMDDATA3 - Command data word 3 */ +#define FMUTEST_FCCOB7_CMDDATA3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FCCOB7_CMDDATA3_SHIFT)) & FMUTEST_FCCOB7_CMDDATA3_MASK) +/*! @} */ + +/*! @name RESET_STATUS - FMU Initialization Tracking Register */ +/*! @{ */ + +#define FMUTEST_RESET_STATUS_ARY_TRIM_DONE_MASK (0x1U) +#define FMUTEST_RESET_STATUS_ARY_TRIM_DONE_SHIFT (0U) +/*! ARY_TRIM_DONE - Array Trim Complete + * 0b0..Recall register load operation has not been completed + * 0b1..Recall register load operation has completed + */ +#define FMUTEST_RESET_STATUS_ARY_TRIM_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_ARY_TRIM_DONE_SHIFT)) & FMUTEST_RESET_STATUS_ARY_TRIM_DONE_MASK) + +#define FMUTEST_RESET_STATUS_FMU_PARM_EN_MASK (0x2U) +#define FMUTEST_RESET_STATUS_FMU_PARM_EN_SHIFT (1U) +/*! FMU_PARM_EN - Status of the C0DE_C0DEh check to enable loading of the FMU parameters + * 0b0..C0DE_C0DEh check not attempted + * 0b1..C0DE_C0DEh check completed + */ +#define FMUTEST_RESET_STATUS_FMU_PARM_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_FMU_PARM_EN_SHIFT)) & FMUTEST_RESET_STATUS_FMU_PARM_EN_MASK) + +#define FMUTEST_RESET_STATUS_FMU_PARM_DONE_MASK (0x4U) +#define FMUTEST_RESET_STATUS_FMU_PARM_DONE_SHIFT (2U) +/*! FMU_PARM_DONE - FMU Register Load Complete + * 0b0..FMU registers have not been loaded + * 0b1..FMU registers have been loaded + */ +#define FMUTEST_RESET_STATUS_FMU_PARM_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_FMU_PARM_DONE_SHIFT)) & FMUTEST_RESET_STATUS_FMU_PARM_DONE_MASK) + +#define FMUTEST_RESET_STATUS_SOC_TRIM_EN_MASK (0x8U) +#define FMUTEST_RESET_STATUS_SOC_TRIM_EN_SHIFT (3U) +/*! SOC_TRIM_EN - Status of the C0DE_C0DEh check to enable loading of the SoC trim settings + * 0b0..C0DE_C0DEh check not attempted + * 0b1..C0DE_C0DEh check completed + */ +#define FMUTEST_RESET_STATUS_SOC_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_EN_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_EN_MASK) + +#define FMUTEST_RESET_STATUS_SOC_TRIM_ECC_MASK (0x10U) +#define FMUTEST_RESET_STATUS_SOC_TRIM_ECC_SHIFT (4U) +/*! SOC_TRIM_ECC - Status of the C0DE_C0DEh check for enabling ECC decoder during reads of SoC trim settings + * 0b0..C0DE_C0DEh check failed + * 0b1..C0DE_C0DEh check passed + */ +#define FMUTEST_RESET_STATUS_SOC_TRIM_ECC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_ECC_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_ECC_MASK) + +#define FMUTEST_RESET_STATUS_SOC_TRIM_DONE_MASK (0x20U) +#define FMUTEST_RESET_STATUS_SOC_TRIM_DONE_SHIFT (5U) +/*! SOC_TRIM_DONE - SoC Trim Complete + * 0b0..SoC Trim registers have not been updated + * 0b1..All SoC Trim registers have been updated + */ +#define FMUTEST_RESET_STATUS_SOC_TRIM_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_DONE_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_DONE_MASK) + +#define FMUTEST_RESET_STATUS_RPR_DONE_MASK (0x40U) +#define FMUTEST_RESET_STATUS_RPR_DONE_SHIFT (6U) +/*! RPR_DONE - Array Repair Complete + * 0b0..Repair registers have not been loaded + * 0b1..Repair registers have been loaded + */ +#define FMUTEST_RESET_STATUS_RPR_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RPR_DONE_SHIFT)) & FMUTEST_RESET_STATUS_RPR_DONE_MASK) + +#define FMUTEST_RESET_STATUS_INIT_DONE_MASK (0x80U) +#define FMUTEST_RESET_STATUS_INIT_DONE_SHIFT (7U) +/*! INIT_DONE - Initialization Done + * 0b0..All initialization steps did not complete + * 0b1..All initialization steps completed + */ +#define FMUTEST_RESET_STATUS_INIT_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_INIT_DONE_SHIFT)) & FMUTEST_RESET_STATUS_INIT_DONE_MASK) + +#define FMUTEST_RESET_STATUS_RST_SF_ERR_MASK (0x100U) +#define FMUTEST_RESET_STATUS_RST_SF_ERR_SHIFT (8U) +/*! RST_SF_ERR - ECC Single Fault during Reset Recovery + * 0b0..No single-bit faults detected during initialization + * 0b1..At least one single ECC fault was detected during initialization + */ +#define FMUTEST_RESET_STATUS_RST_SF_ERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RST_SF_ERR_SHIFT)) & FMUTEST_RESET_STATUS_RST_SF_ERR_MASK) + +#define FMUTEST_RESET_STATUS_RST_DF_ERR_MASK (0x200U) +#define FMUTEST_RESET_STATUS_RST_DF_ERR_SHIFT (9U) +/*! RST_DF_ERR - ECC Double Fault during Reset Recovery + * 0b0..No double-bit faults detected during initialization + * 0b1..Double-bit ECC fault was detected during initialization + */ +#define FMUTEST_RESET_STATUS_RST_DF_ERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RST_DF_ERR_SHIFT)) & FMUTEST_RESET_STATUS_RST_DF_ERR_MASK) + +#define FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_MASK (0x3FC00U) +#define FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_SHIFT (10U) +/*! SOC_TRIM_DF_ERR - ECC Double Fault during load of SoC Trim phrases */ +#define FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_SHIFT)) & FMUTEST_RESET_STATUS_SOC_TRIM_DF_ERR_MASK) + +#define FMUTEST_RESET_STATUS_RST_PATCH_LD_MASK (0x40000U) +#define FMUTEST_RESET_STATUS_RST_PATCH_LD_SHIFT (18U) +/*! RST_PATCH_LD - Reset Patch Required + * 0b0..No patch required to be loaded during reset + * 0b1..Patch loaded during reset + */ +#define FMUTEST_RESET_STATUS_RST_PATCH_LD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RST_PATCH_LD_SHIFT)) & FMUTEST_RESET_STATUS_RST_PATCH_LD_MASK) + +#define FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_MASK (0x80000U) +#define FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_SHIFT (19U) +/*! RECALL_DATA_MISMATCH - Recall Data Mismatch + * 0b0..Data read towards end of reset matched data read for Recall + * 0b1..Data read towards end of reset did not match data read for recall + */ +#define FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_SHIFT)) & FMUTEST_RESET_STATUS_RECALL_DATA_MISMATCH_MASK) +/*! @} */ + +/*! @name MCTL - FMU Control Register */ +/*! @{ */ + +#define FMUTEST_MCTL_COREHLD_MASK (0x1U) +#define FMUTEST_MCTL_COREHLD_SHIFT (0U) +/*! COREHLD - Core Hold + * 0b0..CPU access is allowed + * 0b1..CPU access must be blocked + */ +#define FMUTEST_MCTL_COREHLD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_COREHLD_SHIFT)) & FMUTEST_MCTL_COREHLD_MASK) + +#define FMUTEST_MCTL_LSACT_EN_MASK (0x4U) +#define FMUTEST_MCTL_LSACT_EN_SHIFT (2U) +/*! LSACT_EN - LSACTIVE Feature Enable + * 0b0..LSACTIVE feature disabled completely: FCTRL[LSACTIVE] is forced low and no longer writable, LVE cannot assert at the TSMC array interface. + * 0b1..LSACTIVE feature fully enabled and controllable by SoC and internal UINT SM. + */ +#define FMUTEST_MCTL_LSACT_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_LSACT_EN_SHIFT)) & FMUTEST_MCTL_LSACT_EN_MASK) + +#define FMUTEST_MCTL_LSACTWREN_MASK (0x8U) +#define FMUTEST_MCTL_LSACTWREN_SHIFT (3U) +/*! LSACTWREN - LSACTIVE Write Enable + * 0b0..Unrestricted write access allowed + * 0b1..Write access while CMP set must match CMDDID and CMDPRT + */ +#define FMUTEST_MCTL_LSACTWREN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_LSACTWREN_SHIFT)) & FMUTEST_MCTL_LSACTWREN_MASK) + +#define FMUTEST_MCTL_MASTER_REPAIR_EN_MASK (0x10U) +#define FMUTEST_MCTL_MASTER_REPAIR_EN_SHIFT (4U) +/*! MASTER_REPAIR_EN - Master Repair Enable + * 0b0..Repair disabled + * 0b1..Repair enable determined by bit 0 of each REPAIR register + */ +#define FMUTEST_MCTL_MASTER_REPAIR_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MASTER_REPAIR_EN_SHIFT)) & FMUTEST_MCTL_MASTER_REPAIR_EN_MASK) + +#define FMUTEST_MCTL_RFCMDEN_MASK (0x20U) +#define FMUTEST_MCTL_RFCMDEN_SHIFT (5U) +/*! RFCMDEN - RF Active Command Enable Control + * 0b0..Flash commands blocked (CCIF not writable) + * 0b1..Flash commands allowed + */ +#define FMUTEST_MCTL_RFCMDEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_RFCMDEN_SHIFT)) & FMUTEST_MCTL_RFCMDEN_MASK) + +#define FMUTEST_MCTL_CWSABTEN_MASK (0x40U) +#define FMUTEST_MCTL_CWSABTEN_SHIFT (6U) +/*! CWSABTEN - Command Write Sequence Abort Enable + * 0b0..CWS abort feature is disabled + * 0b1..CWS abort feature is enabled + */ +#define FMUTEST_MCTL_CWSABTEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_CWSABTEN_SHIFT)) & FMUTEST_MCTL_CWSABTEN_MASK) + +#define FMUTEST_MCTL_MRGRDDIS_MASK (0x80U) +#define FMUTEST_MCTL_MRGRDDIS_SHIFT (7U) +/*! MRGRDDIS - Margin Read Disable + * 0b0..Margin Read Settings are enabled + * 0b1..Margin Read Settings are disabled + */ +#define FMUTEST_MCTL_MRGRDDIS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MRGRDDIS_SHIFT)) & FMUTEST_MCTL_MRGRDDIS_MASK) + +#define FMUTEST_MCTL_MRGRD0_MASK (0xF00U) +#define FMUTEST_MCTL_MRGRD0_SHIFT (8U) +/*! MRGRD0 - Margin Read Setting for Program */ +#define FMUTEST_MCTL_MRGRD0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MRGRD0_SHIFT)) & FMUTEST_MCTL_MRGRD0_MASK) + +#define FMUTEST_MCTL_MRGRD1_MASK (0xF000U) +#define FMUTEST_MCTL_MRGRD1_SHIFT (12U) +/*! MRGRD1 - Margin Read Setting for Erase */ +#define FMUTEST_MCTL_MRGRD1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_MRGRD1_SHIFT)) & FMUTEST_MCTL_MRGRD1_MASK) + +#define FMUTEST_MCTL_ERSAACK_MASK (0x10000U) +#define FMUTEST_MCTL_ERSAACK_SHIFT (16U) +/*! ERSAACK - Mass Erase (Erase All) Acknowledge + * 0b0..Mass Erase operation is not active (operation has completed or has not started) + * 0b1..Mass Erase operation is active (controller acknowledges that the soc_ersall_req input is asserted and will continue with the operation) + */ +#define FMUTEST_MCTL_ERSAACK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_ERSAACK_SHIFT)) & FMUTEST_MCTL_ERSAACK_MASK) + +#define FMUTEST_MCTL_SCAN_OBS_MASK (0x80000U) +#define FMUTEST_MCTL_SCAN_OBS_SHIFT (19U) +/*! SCAN_OBS - Scan Observability Control + * 0b0..Normal functional behavior + * 0b1..Enables observation of signals that may otherwise be ATPG untestable + */ +#define FMUTEST_MCTL_SCAN_OBS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SCAN_OBS_SHIFT)) & FMUTEST_MCTL_SCAN_OBS_MASK) + +#define FMUTEST_MCTL_BIST_CTL_MASK (0x100000U) +#define FMUTEST_MCTL_BIST_CTL_SHIFT (20U) +/*! BIST_CTL - BIST IP Control + * 0b0..BIST IP disabled + * 0b1..BIST IP enabled + */ +#define FMUTEST_MCTL_BIST_CTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_BIST_CTL_SHIFT)) & FMUTEST_MCTL_BIST_CTL_MASK) + +#define FMUTEST_MCTL_SMWR_CTL_MASK (0x200000U) +#define FMUTEST_MCTL_SMWR_CTL_SHIFT (21U) +/*! SMWR_CTL - SMWR IP Control + * 0b0..SMWR IP disabled + * 0b1..SMWR IP enabled + */ +#define FMUTEST_MCTL_SMWR_CTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SMWR_CTL_SHIFT)) & FMUTEST_MCTL_SMWR_CTL_MASK) + +#define FMUTEST_MCTL_SALV_DIS_MASK (0x1000000U) +#define FMUTEST_MCTL_SALV_DIS_SHIFT (24U) +/*! SALV_DIS - Salvage Disable + * 0b0..Salvage enabled (ECC used during erase verify) + * 0b1..Salvage disabled (ECC not used during erase verify) + */ +#define FMUTEST_MCTL_SALV_DIS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SALV_DIS_SHIFT)) & FMUTEST_MCTL_SALV_DIS_MASK) + +#define FMUTEST_MCTL_SOC_ECC_CTL_MASK (0x2000000U) +#define FMUTEST_MCTL_SOC_ECC_CTL_SHIFT (25U) +/*! SOC_ECC_CTL - SOC ECC Control + * 0b0..ECC is enabled for SOC read access + * 0b1..ECC is disabled for SOC read access + */ +#define FMUTEST_MCTL_SOC_ECC_CTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_SOC_ECC_CTL_SHIFT)) & FMUTEST_MCTL_SOC_ECC_CTL_MASK) + +#define FMUTEST_MCTL_FMU_ECC_CTL_MASK (0x4000000U) +#define FMUTEST_MCTL_FMU_ECC_CTL_SHIFT (26U) +/*! FMU_ECC_CTL - FMU ECC Control + * 0b0..ECC is enabled for FMU program operations + * 0b1..ECC is disabled for FMU program operations + */ +#define FMUTEST_MCTL_FMU_ECC_CTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_FMU_ECC_CTL_SHIFT)) & FMUTEST_MCTL_FMU_ECC_CTL_MASK) + +#define FMUTEST_MCTL_BIST_PWR_DIS_MASK (0x20000000U) +#define FMUTEST_MCTL_BIST_PWR_DIS_SHIFT (29U) +/*! BIST_PWR_DIS - BIST Power Mode Disable + * 0b0..BIST DFT logic has full control of SLM and LVE when BIST is enabled (including during commands) + * 0b1..BIST DFT logic has no control of SLM and LVE; power mode RTL is in complete control of SLM and LVE values + */ +#define FMUTEST_MCTL_BIST_PWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_BIST_PWR_DIS_SHIFT)) & FMUTEST_MCTL_BIST_PWR_DIS_MASK) + +#define FMUTEST_MCTL_OSC_H_MASK (0x80000000U) +#define FMUTEST_MCTL_OSC_H_SHIFT (31U) +/*! OSC_H - Oscillator control + * 0b0..Use APB clock + * 0b1..Use a known fixed-frequency clock, e.g. 12 MHz + */ +#define FMUTEST_MCTL_OSC_H(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MCTL_OSC_H_SHIFT)) & FMUTEST_MCTL_OSC_H_MASK) +/*! @} */ + +/*! @name BSEL_GEN - FMU Block Select Generation Register */ +/*! @{ */ + +#define FMUTEST_BSEL_GEN_SBSEL_GEN_MASK (0x3U) +#define FMUTEST_BSEL_GEN_SBSEL_GEN_SHIFT (0U) +/*! SBSEL_GEN - Generated SBSEL */ +#define FMUTEST_BSEL_GEN_SBSEL_GEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_GEN_SBSEL_GEN_SHIFT)) & FMUTEST_BSEL_GEN_SBSEL_GEN_MASK) + +#define FMUTEST_BSEL_GEN_MBSEL_GEN_MASK (0x300U) +#define FMUTEST_BSEL_GEN_MBSEL_GEN_SHIFT (8U) +/*! MBSEL_GEN - Generated MBSEL */ +#define FMUTEST_BSEL_GEN_MBSEL_GEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_GEN_MBSEL_GEN_SHIFT)) & FMUTEST_BSEL_GEN_MBSEL_GEN_MASK) +/*! @} */ + +/*! @name PWR_OPT - Power Mode Options Register */ +/*! @{ */ + +#define FMUTEST_PWR_OPT_PD_CDIV_MASK (0xFFU) +#define FMUTEST_PWR_OPT_PD_CDIV_SHIFT (0U) +/*! PD_CDIV - Power Down Clock Divider Setting */ +#define FMUTEST_PWR_OPT_PD_CDIV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PWR_OPT_PD_CDIV_SHIFT)) & FMUTEST_PWR_OPT_PD_CDIV_MASK) + +#define FMUTEST_PWR_OPT_SLM_COUNT_MASK (0x3FF0000U) +#define FMUTEST_PWR_OPT_SLM_COUNT_SHIFT (16U) +/*! SLM_COUNT - Sleep Recovery Timer Count */ +#define FMUTEST_PWR_OPT_SLM_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PWR_OPT_SLM_COUNT_SHIFT)) & FMUTEST_PWR_OPT_SLM_COUNT_MASK) + +#define FMUTEST_PWR_OPT_PD_TIMER_EN_MASK (0x80000000U) +#define FMUTEST_PWR_OPT_PD_TIMER_EN_SHIFT (31U) +/*! PD_TIMER_EN - Power Down BIST Timer Enable + * 0b0..BIST timer is not triggered during Power Down recovery + * 0b1..BIST timer is triggered during Power Down recovery (default behavior) + */ +#define FMUTEST_PWR_OPT_PD_TIMER_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PWR_OPT_PD_TIMER_EN_SHIFT)) & FMUTEST_PWR_OPT_PD_TIMER_EN_MASK) +/*! @} */ + +/*! @name CMD_CHECK - FMU Command Check Register */ +/*! @{ */ + +#define FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_MASK (0x1U) +#define FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_SHIFT (0U) +/*! ALIGNFAIL_PHR - Phrase Alignment Fail + * 0b0..The address is phrase-aligned + * 0b1..The address is not phrase-aligned + */ +#define FMUTEST_CMD_CHECK_ALIGNFAIL_PHR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_PHR_MASK) + +#define FMUTEST_CMD_CHECK_ALIGNFAIL_PG_MASK (0x2U) +#define FMUTEST_CMD_CHECK_ALIGNFAIL_PG_SHIFT (1U) +/*! ALIGNFAIL_PG - Page Alignment Fail + * 0b0..The address is page-aligned + * 0b1..The address is not page-aligned + */ +#define FMUTEST_CMD_CHECK_ALIGNFAIL_PG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_PG_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_PG_MASK) + +#define FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_MASK (0x4U) +#define FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_SHIFT (2U) +/*! ALIGNFAIL_SCR - Sector Alignment Fail + * 0b0..The address is sector-aligned + * 0b1..The address is not sector-aligned + */ +#define FMUTEST_CMD_CHECK_ALIGNFAIL_SCR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_SCR_MASK) + +#define FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_MASK (0x8U) +#define FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_SHIFT (3U) +/*! ALIGNFAIL_BLK - Block Alignment Fail + * 0b0..The address is block-aligned + * 0b1..The address is not block-aligned + */ +#define FMUTEST_CMD_CHECK_ALIGNFAIL_BLK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_SHIFT)) & FMUTEST_CMD_CHECK_ALIGNFAIL_BLK_MASK) + +#define FMUTEST_CMD_CHECK_ADDR_FAIL_MASK (0x10U) +#define FMUTEST_CMD_CHECK_ADDR_FAIL_SHIFT (4U) +/*! ADDR_FAIL - Address Fail + * 0b0..The address is within the flash or IFR address space + * 0b1..The address is outside the flash or IFR address space + */ +#define FMUTEST_CMD_CHECK_ADDR_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ADDR_FAIL_SHIFT)) & FMUTEST_CMD_CHECK_ADDR_FAIL_MASK) + +#define FMUTEST_CMD_CHECK_IFR_CMD_MASK (0x20U) +#define FMUTEST_CMD_CHECK_IFR_CMD_SHIFT (5U) +/*! IFR_CMD - IFR Command + * 0b0..The command operates on a main flash address + * 0b1..The command operates on an IFR address + */ +#define FMUTEST_CMD_CHECK_IFR_CMD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_IFR_CMD_SHIFT)) & FMUTEST_CMD_CHECK_IFR_CMD_MASK) + +#define FMUTEST_CMD_CHECK_ALL_CMD_MASK (0x40U) +#define FMUTEST_CMD_CHECK_ALL_CMD_SHIFT (6U) +/*! ALL_CMD - All Blocks Command + * 0b0..The command operates on a single flash block + * 0b1..The command operates on all flash blocks + */ +#define FMUTEST_CMD_CHECK_ALL_CMD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ALL_CMD_SHIFT)) & FMUTEST_CMD_CHECK_ALL_CMD_MASK) + +#define FMUTEST_CMD_CHECK_RANGE_FAIL_MASK (0x80U) +#define FMUTEST_CMD_CHECK_RANGE_FAIL_SHIFT (7U) +/*! RANGE_FAIL - Address Range Fail + * 0b0..The address range is valid + * 0b1..The address range is invalid + */ +#define FMUTEST_CMD_CHECK_RANGE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_RANGE_FAIL_SHIFT)) & FMUTEST_CMD_CHECK_RANGE_FAIL_MASK) + +#define FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_MASK (0x100U) +#define FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_SHIFT (8U) +/*! SCR_ALIGN_CHK - Sector Alignment Check + * 0b0..No sector alignment check + * 0b1..Sector alignment check + */ +#define FMUTEST_CMD_CHECK_SCR_ALIGN_CHK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_SHIFT)) & FMUTEST_CMD_CHECK_SCR_ALIGN_CHK_MASK) + +#define FMUTEST_CMD_CHECK_OPTION_FAIL_MASK (0x200U) +#define FMUTEST_CMD_CHECK_OPTION_FAIL_SHIFT (9U) +/*! OPTION_FAIL - Option Check Fail + * 0b0..Option check passes for read command or command is not a read command + * 0b1..Option check fails for read command + */ +#define FMUTEST_CMD_CHECK_OPTION_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_OPTION_FAIL_SHIFT)) & FMUTEST_CMD_CHECK_OPTION_FAIL_MASK) + +#define FMUTEST_CMD_CHECK_ILLEGAL_CMD_MASK (0x400U) +#define FMUTEST_CMD_CHECK_ILLEGAL_CMD_SHIFT (10U) +/*! ILLEGAL_CMD - Illegal Command + * 0b0..Command is legal + * 0b1..Command is illegal + */ +#define FMUTEST_CMD_CHECK_ILLEGAL_CMD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_CMD_CHECK_ILLEGAL_CMD_SHIFT)) & FMUTEST_CMD_CHECK_ILLEGAL_CMD_MASK) +/*! @} */ + +/*! @name BSEL - FMU Block Select Register */ +/*! @{ */ + +#define FMUTEST_BSEL_SBSEL_MASK (0x3U) +#define FMUTEST_BSEL_SBSEL_SHIFT (0U) +/*! SBSEL - Slave Block Select */ +#define FMUTEST_BSEL_SBSEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_SBSEL_SHIFT)) & FMUTEST_BSEL_SBSEL_MASK) + +#define FMUTEST_BSEL_MBSEL_MASK (0x300U) +#define FMUTEST_BSEL_MBSEL_SHIFT (8U) +/*! MBSEL - Master Block Select */ +#define FMUTEST_BSEL_MBSEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BSEL_MBSEL_SHIFT)) & FMUTEST_BSEL_MBSEL_MASK) +/*! @} */ + +/*! @name MSIZE - FMU Memory Size Register */ +/*! @{ */ + +#define FMUTEST_MSIZE_MAXADDR0_MASK (0xFFU) +#define FMUTEST_MSIZE_MAXADDR0_SHIFT (0U) +/*! MAXADDR0 - Size of Flash Block 0 */ +#define FMUTEST_MSIZE_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MSIZE_MAXADDR0_SHIFT)) & FMUTEST_MSIZE_MAXADDR0_MASK) +/*! @} */ + +/*! @name FLASH_RD_ADD - Flash Read Address Register */ +/*! @{ */ + +#define FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_MASK (0xFFFFFFFFU) +#define FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_SHIFT (0U) +/*! FLASH_RD_ADD - Flash Read Address */ +#define FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_SHIFT)) & FMUTEST_FLASH_RD_ADD_FLASH_RD_ADD_MASK) +/*! @} */ + +/*! @name FLASH_STOP_ADD - Flash Stop Address Register */ +/*! @{ */ + +#define FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_MASK (0xFFFFFFFFU) +#define FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_SHIFT (0U) +/*! FLASH_STOP_ADD - Flash Stop Address */ +#define FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_SHIFT)) & FMUTEST_FLASH_STOP_ADD_FLASH_STOP_ADD_MASK) +/*! @} */ + +/*! @name FLASH_RD_CTRL - Flash Read Control Register */ +/*! @{ */ + +#define FMUTEST_FLASH_RD_CTRL_FLASH_RD_MASK (0x1U) +#define FMUTEST_FLASH_RD_CTRL_FLASH_RD_SHIFT (0U) +/*! FLASH_RD - Flash Read Enable + * 0b0..Manual flash read not enabled.(default) + * 0b1..Manual flash read enabled + */ +#define FMUTEST_FLASH_RD_CTRL_FLASH_RD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_CTRL_FLASH_RD_SHIFT)) & FMUTEST_FLASH_RD_CTRL_FLASH_RD_MASK) + +#define FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_MASK (0x2U) +#define FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_SHIFT (1U) +/*! WIDE_LOAD - Wide Load Enable + * 0b0..Wide load mode disabled (default) + * 0b1..Wide load mode enabled + */ +#define FMUTEST_FLASH_RD_CTRL_WIDE_LOAD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_SHIFT)) & FMUTEST_FLASH_RD_CTRL_WIDE_LOAD_MASK) + +#define FMUTEST_FLASH_RD_CTRL_SINGLE_RD_MASK (0x4U) +#define FMUTEST_FLASH_RD_CTRL_SINGLE_RD_SHIFT (2U) +/*! SINGLE_RD - Single Flash Read + * 0b0..Normal UINT operation + * 0b1..UINT configured for single cycle reads + */ +#define FMUTEST_FLASH_RD_CTRL_SINGLE_RD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FLASH_RD_CTRL_SINGLE_RD_SHIFT)) & FMUTEST_FLASH_RD_CTRL_SINGLE_RD_MASK) +/*! @} */ + +/*! @name MM_ADDR - Memory Map Address Register */ +/*! @{ */ + +#define FMUTEST_MM_ADDR_MM_ADDR_MASK (0xFFFFFFFFU) +#define FMUTEST_MM_ADDR_MM_ADDR_SHIFT (0U) +/*! MM_ADDR - Memory Map Address */ +#define FMUTEST_MM_ADDR_MM_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_ADDR_MM_ADDR_SHIFT)) & FMUTEST_MM_ADDR_MM_ADDR_MASK) +/*! @} */ + +/*! @name MM_WDATA - Memory Map Write Data Register */ +/*! @{ */ + +#define FMUTEST_MM_WDATA_MM_WDATA_MASK (0xFFFFFFFFU) +#define FMUTEST_MM_WDATA_MM_WDATA_SHIFT (0U) +/*! MM_WDATA - Memory Map Write Data */ +#define FMUTEST_MM_WDATA_MM_WDATA(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_WDATA_MM_WDATA_SHIFT)) & FMUTEST_MM_WDATA_MM_WDATA_MASK) +/*! @} */ + +/*! @name MM_CTL - Memory Map Control Register */ +/*! @{ */ + +#define FMUTEST_MM_CTL_MM_SEL_MASK (0x1U) +#define FMUTEST_MM_CTL_MM_SEL_SHIFT (0U) +/*! MM_SEL - Register Access Enable */ +#define FMUTEST_MM_CTL_MM_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_MM_SEL_SHIFT)) & FMUTEST_MM_CTL_MM_SEL_MASK) + +#define FMUTEST_MM_CTL_MM_RD_MASK (0x2U) +#define FMUTEST_MM_CTL_MM_RD_SHIFT (1U) +/*! MM_RD - Register R/W Control + * 0b0..Write to register + * 0b1..Read register + */ +#define FMUTEST_MM_CTL_MM_RD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_MM_RD_SHIFT)) & FMUTEST_MM_CTL_MM_RD_MASK) + +#define FMUTEST_MM_CTL_BIST_ON_MASK (0x4U) +#define FMUTEST_MM_CTL_BIST_ON_SHIFT (2U) +/*! BIST_ON - BIST on + * 0b0..BIST enable not forced by user interface + * 0b1..BIST enable control by user interface + */ +#define FMUTEST_MM_CTL_BIST_ON(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_BIST_ON_SHIFT)) & FMUTEST_MM_CTL_BIST_ON_MASK) + +#define FMUTEST_MM_CTL_FORCE_SW_CLK_MASK (0x8U) +#define FMUTEST_MM_CTL_FORCE_SW_CLK_SHIFT (3U) +/*! FORCE_SW_CLK - Force Switch Clock + * 0b0..Switch clock not forced on (gated normally) + * 0b1..Switch clock forced on + */ +#define FMUTEST_MM_CTL_FORCE_SW_CLK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MM_CTL_FORCE_SW_CLK_SHIFT)) & FMUTEST_MM_CTL_FORCE_SW_CLK_MASK) +/*! @} */ + +/*! @name UINT_CTL - User Interface Control Register */ +/*! @{ */ + +#define FMUTEST_UINT_CTL_SET_FAIL_MASK (0x1U) +#define FMUTEST_UINT_CTL_SET_FAIL_SHIFT (0U) +/*! SET_FAIL - Set Fail On Exit + * 0b0..FAIL flag should not be set on command exit (no failure detected) + * 0b1..FAIL flag should be set on command exit + */ +#define FMUTEST_UINT_CTL_SET_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_UINT_CTL_SET_FAIL_SHIFT)) & FMUTEST_UINT_CTL_SET_FAIL_MASK) + +#define FMUTEST_UINT_CTL_DBERR_MASK (0x2U) +#define FMUTEST_UINT_CTL_DBERR_SHIFT (1U) +/*! DBERR - Double-Bit ECC Fault Detect + * 0b0..No double-bit fault detected during UINT-driven read sequence + * 0b1..Double-bit fault detected during UINT-driven read sequence + */ +#define FMUTEST_UINT_CTL_DBERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_UINT_CTL_DBERR_SHIFT)) & FMUTEST_UINT_CTL_DBERR_MASK) +/*! @} */ + +/*! @name RD_DATA0 - Read Data 0 Register */ +/*! @{ */ + +#define FMUTEST_RD_DATA0_RD_DATA0_MASK (0xFFFFFFFFU) +#define FMUTEST_RD_DATA0_RD_DATA0_SHIFT (0U) +/*! RD_DATA0 - Read Data 0 */ +#define FMUTEST_RD_DATA0_RD_DATA0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA0_RD_DATA0_SHIFT)) & FMUTEST_RD_DATA0_RD_DATA0_MASK) +/*! @} */ + +/*! @name RD_DATA1 - Read Data 1 Register */ +/*! @{ */ + +#define FMUTEST_RD_DATA1_RD_DATA1_MASK (0xFFFFFFFFU) +#define FMUTEST_RD_DATA1_RD_DATA1_SHIFT (0U) +/*! RD_DATA1 - Read Data 1 */ +#define FMUTEST_RD_DATA1_RD_DATA1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA1_RD_DATA1_SHIFT)) & FMUTEST_RD_DATA1_RD_DATA1_MASK) +/*! @} */ + +/*! @name RD_DATA2 - Read Data 2 Register */ +/*! @{ */ + +#define FMUTEST_RD_DATA2_RD_DATA2_MASK (0xFFFFFFFFU) +#define FMUTEST_RD_DATA2_RD_DATA2_SHIFT (0U) +/*! RD_DATA2 - Read Data 2 */ +#define FMUTEST_RD_DATA2_RD_DATA2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA2_RD_DATA2_SHIFT)) & FMUTEST_RD_DATA2_RD_DATA2_MASK) +/*! @} */ + +/*! @name RD_DATA3 - Read Data 3 Register */ +/*! @{ */ + +#define FMUTEST_RD_DATA3_RD_DATA3_MASK (0xFFFFFFFFU) +#define FMUTEST_RD_DATA3_RD_DATA3_SHIFT (0U) +/*! RD_DATA3 - Read Data 3 */ +#define FMUTEST_RD_DATA3_RD_DATA3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_DATA3_RD_DATA3_SHIFT)) & FMUTEST_RD_DATA3_RD_DATA3_MASK) +/*! @} */ + +/*! @name PARITY - Parity Register */ +/*! @{ */ + +#define FMUTEST_PARITY_PARITY_MASK (0x1FFU) +#define FMUTEST_PARITY_PARITY_SHIFT (0U) +/*! PARITY - Read data [136:128] */ +#define FMUTEST_PARITY_PARITY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PARITY_PARITY_SHIFT)) & FMUTEST_PARITY_PARITY_MASK) +/*! @} */ + +/*! @name RD_PATH_CTRL_STATUS - Read Path Control and Status Register */ +/*! @{ */ + +#define FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_MASK (0xFFU) +#define FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_SHIFT (0U) +/*! RD_CAPT - Read Capture Clock Periods */ +#define FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_RD_CAPT_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_MASK (0xFF00U) +#define FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_SHIFT (8U) +/*! SE_SIZE - SE Clock Periods */ +#define FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_SE_SIZE_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_MASK (0x10000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_SHIFT (16U) +/*! ECC_ENABLEB - ECC Decoder Control + * 0b0..ECC decoder enabled (default) + * 0b1..ECC decoder disabled + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_ECC_ENABLEB_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_MASK (0x20000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_SHIFT (17U) +/*! MISR_EN - MISR Enable + * 0b0..MISR option disabled (default) + * 0b1..MISR option enabled + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_MISR_EN_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_MASK (0x40000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_SHIFT (18U) +/*! CPY_PAR_EN - Copy Parity Enable + * 0b0..Copy parity disabled + * 0b1..Copy parity enabled + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_CPY_PAR_EN_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_MASK (0x80000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_SHIFT (19U) +/*! BIST_MUX_TO_SMW - BIST Mux to SMW + * 0b0..BIST drives fields + * 0b1..SMW registers drive fields + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_MASK (0xF00000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_SHIFT (20U) +/*! AD_SET - Multi-Cycle Address Setup Time */ +#define FMUTEST_RD_PATH_CTRL_STATUS_AD_SET(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_AD_SET_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_MASK (0x1000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_SHIFT (24U) +/*! WR_PATH_EN - Write Path Enable + * 0b0..Writes to BIST setting registers driven by MM_WDATA + * 0b1..Writes to BIST setting registers driven by SMW_DIN + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_EN_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_MASK (0x2000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_SHIFT (25U) +/*! WR_PATH_ECC_EN - Write Path ECC Enable + * 0b0..ECC encoding disabled + * 0b1..ECC encoding enabled + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_MASK (0x4000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_SHIFT (26U) +/*! DBERR_REG - Double-Bit Error + * 0b0..Double-bit fault not detected + * 0b1..Double-bit fault detected on previous UINT flash read + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_DBERR_REG_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_MASK (0x8000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_SHIFT (27U) +/*! SBERR_REG - Single-Bit Error + * 0b0..Single-bit fault not detected + * 0b1..Single-bit fault detected on previous UINT flash read + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_SBERR_REG_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_MASK (0x10000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_SHIFT (28U) +/*! CPY_PHRASE_EN - Copy Phrase Enable + * 0b0..Copy Flash read data disabled + * 0b1..Copy Flash read data enabled + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_CPY_PHRASE_EN_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_MASK (0x20000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_SHIFT (29U) +/*! SMW_ARRAY1_SMW0_SEL - SMW_ARRAY1_SMW0_SEL + * 0b0..Select block 0 + * 0b1..Select block 1 + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_MASK (0x40000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_SHIFT (30U) +/*! BIST_ECC_EN - BIST ECC Enable + * 0b0..ECC correction disabled + * 0b1..ECC correction enabled + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_BIST_ECC_EN_MASK) + +#define FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_MASK (0x80000000U) +#define FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_SHIFT (31U) +/*! LAST_READ - Last Read + * 0b0..Latest read not last in multi-address operation + * 0b1..Latest read last in multi-address operation + */ +#define FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_SHIFT)) & FMUTEST_RD_PATH_CTRL_STATUS_LAST_READ_MASK) +/*! @} */ + +/*! @name SMW_DIN0 - SMW DIN 0 Register */ +/*! @{ */ + +#define FMUTEST_SMW_DIN0_SMW_DIN0_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_DIN0_SMW_DIN0_SHIFT (0U) +/*! SMW_DIN0 - SMW DIN 0 */ +#define FMUTEST_SMW_DIN0_SMW_DIN0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN0_SMW_DIN0_SHIFT)) & FMUTEST_SMW_DIN0_SMW_DIN0_MASK) +/*! @} */ + +/*! @name SMW_DIN1 - SMW DIN 1 Register */ +/*! @{ */ + +#define FMUTEST_SMW_DIN1_SMW_DIN1_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_DIN1_SMW_DIN1_SHIFT (0U) +/*! SMW_DIN1 - SMW DIN 1 */ +#define FMUTEST_SMW_DIN1_SMW_DIN1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN1_SMW_DIN1_SHIFT)) & FMUTEST_SMW_DIN1_SMW_DIN1_MASK) +/*! @} */ + +/*! @name SMW_DIN2 - SMW DIN 2 Register */ +/*! @{ */ + +#define FMUTEST_SMW_DIN2_SMW_DIN2_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_DIN2_SMW_DIN2_SHIFT (0U) +/*! SMW_DIN2 - SMW DIN 2 */ +#define FMUTEST_SMW_DIN2_SMW_DIN2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN2_SMW_DIN2_SHIFT)) & FMUTEST_SMW_DIN2_SMW_DIN2_MASK) +/*! @} */ + +/*! @name SMW_DIN3 - SMW DIN 3 Register */ +/*! @{ */ + +#define FMUTEST_SMW_DIN3_SMW_DIN3_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_DIN3_SMW_DIN3_SHIFT (0U) +/*! SMW_DIN3 - SMW DIN 3 */ +#define FMUTEST_SMW_DIN3_SMW_DIN3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_DIN3_SMW_DIN3_SHIFT)) & FMUTEST_SMW_DIN3_SMW_DIN3_MASK) +/*! @} */ + +/*! @name SMW_ADDR - SMW Address Register */ +/*! @{ */ + +#define FMUTEST_SMW_ADDR_SMW_ADDR_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_ADDR_SMW_ADDR_SHIFT (0U) +/*! SMW_ADDR - SMW Address */ +#define FMUTEST_SMW_ADDR_SMW_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_ADDR_SMW_ADDR_SHIFT)) & FMUTEST_SMW_ADDR_SMW_ADDR_MASK) +/*! @} */ + +/*! @name SMW_CMD_WAIT - SMW Command and Wait Register */ +/*! @{ */ + +#define FMUTEST_SMW_CMD_WAIT_CMD_MASK (0x7U) +#define FMUTEST_SMW_CMD_WAIT_CMD_SHIFT (0U) +/*! CMD - SMW Command + * 0b000..IDLE + * 0b001..ABORT + * 0b010..SME2 to one-shot mass erase + * 0b011..SME3 to sector erase on selected array + * 0b100..SMP1 to program phrase or page on selected array with shot disabled on previously programmed bit + * 0b101..Reserved for SME4 (multi-sector erase) + * 0b110..SMP2 to program phrase or page on selected array to repair cells of weak program after power loss + * 0b111..Reserved + */ +#define FMUTEST_SMW_CMD_WAIT_CMD(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_CMD_WAIT_CMD_SHIFT)) & FMUTEST_SMW_CMD_WAIT_CMD_MASK) + +#define FMUTEST_SMW_CMD_WAIT_WAIT_EN_MASK (0x8U) +#define FMUTEST_SMW_CMD_WAIT_WAIT_EN_SHIFT (3U) +/*! WAIT_EN - SMW Wait Enable + * 0b0..Wait feature disabled + * 0b1..Wait feature enabled + */ +#define FMUTEST_SMW_CMD_WAIT_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_CMD_WAIT_WAIT_EN_SHIFT)) & FMUTEST_SMW_CMD_WAIT_WAIT_EN_MASK) + +#define FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_MASK (0x10U) +#define FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_SHIFT (4U) +/*! WAIT_AUTO_SET - SMW Wait Auto Set */ +#define FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_SHIFT)) & FMUTEST_SMW_CMD_WAIT_WAIT_AUTO_SET_MASK) +/*! @} */ + +/*! @name SMW_STATUS - SMW Status Register */ +/*! @{ */ + +#define FMUTEST_SMW_STATUS_SMW_ERR_MASK (0x1U) +#define FMUTEST_SMW_STATUS_SMW_ERR_SHIFT (0U) +/*! SMW_ERR - SMW Error + * 0b0..Error not detected + * 0b1..Error detected + */ +#define FMUTEST_SMW_STATUS_SMW_ERR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_STATUS_SMW_ERR_SHIFT)) & FMUTEST_SMW_STATUS_SMW_ERR_MASK) + +#define FMUTEST_SMW_STATUS_SMW_BUSY_MASK (0x2U) +#define FMUTEST_SMW_STATUS_SMW_BUSY_SHIFT (1U) +/*! SMW_BUSY - SMW Busy + * 0b0..SMW command not active + * 0b1..SMW command is active + */ +#define FMUTEST_SMW_STATUS_SMW_BUSY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_STATUS_SMW_BUSY_SHIFT)) & FMUTEST_SMW_STATUS_SMW_BUSY_MASK) + +#define FMUTEST_SMW_STATUS_BIST_BUSY_MASK (0x4U) +#define FMUTEST_SMW_STATUS_BIST_BUSY_SHIFT (2U) +/*! BIST_BUSY - BIST Busy + * 0b0..BIST Command not active + * 0b1..BIST Command is active + */ +#define FMUTEST_SMW_STATUS_BIST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_STATUS_BIST_BUSY_SHIFT)) & FMUTEST_SMW_STATUS_BIST_BUSY_MASK) +/*! @} */ + +/*! @name SOCTRIM0_0 - SoC Trim Phrase 0 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM0_0_TRIM0_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM0_0_TRIM0_0_SHIFT (0U) +/*! TRIM0_0 - TRIM0_0 */ +#define FMUTEST_SOCTRIM0_0_TRIM0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_0_TRIM0_0_SHIFT)) & FMUTEST_SOCTRIM0_0_TRIM0_0_MASK) +/*! @} */ + +/*! @name SOCTRIM0_1 - SoC Trim Phrase 0 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM0_1_TRIM0_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM0_1_TRIM0_1_SHIFT (0U) +/*! TRIM0_1 - TRIM0_1 */ +#define FMUTEST_SOCTRIM0_1_TRIM0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_1_TRIM0_1_SHIFT)) & FMUTEST_SOCTRIM0_1_TRIM0_1_MASK) +/*! @} */ + +/*! @name SOCTRIM0_2 - SoC Trim Phrase 0 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM0_2_TRIM0_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM0_2_TRIM0_2_SHIFT (0U) +/*! TRIM0_2 - TRIM0_2 */ +#define FMUTEST_SOCTRIM0_2_TRIM0_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_2_TRIM0_2_SHIFT)) & FMUTEST_SOCTRIM0_2_TRIM0_2_MASK) +/*! @} */ + +/*! @name SOCTRIM0_3 - SoC Trim Phrase 0 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM0_3_TRIM0_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM0_3_TRIM0_3_SHIFT (0U) +/*! TRIM0_3 - TRIM0_3 */ +#define FMUTEST_SOCTRIM0_3_TRIM0_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM0_3_TRIM0_3_SHIFT)) & FMUTEST_SOCTRIM0_3_TRIM0_3_MASK) +/*! @} */ + +/*! @name SOCTRIM1_0 - SoC Trim Phrase 1 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM1_0_TRIM1_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM1_0_TRIM1_0_SHIFT (0U) +/*! TRIM1_0 - TRIM1_0 */ +#define FMUTEST_SOCTRIM1_0_TRIM1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_0_TRIM1_0_SHIFT)) & FMUTEST_SOCTRIM1_0_TRIM1_0_MASK) +/*! @} */ + +/*! @name SOCTRIM1_1 - SoC Trim Phrase 1 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM1_1_TRIM1_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM1_1_TRIM1_1_SHIFT (0U) +/*! TRIM1_1 - TRIM1_1 */ +#define FMUTEST_SOCTRIM1_1_TRIM1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_1_TRIM1_1_SHIFT)) & FMUTEST_SOCTRIM1_1_TRIM1_1_MASK) +/*! @} */ + +/*! @name SOCTRIM1_2 - SoC Trim Phrase 1 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM1_2_TRIM1_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM1_2_TRIM1_2_SHIFT (0U) +/*! TRIM1_2 - TRIM1_2 */ +#define FMUTEST_SOCTRIM1_2_TRIM1_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_2_TRIM1_2_SHIFT)) & FMUTEST_SOCTRIM1_2_TRIM1_2_MASK) +/*! @} */ + +/*! @name SOCTRIM1_3 - SoC Trim Phrase 1 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM1_3_TRIM1_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM1_3_TRIM1_3_SHIFT (0U) +/*! TRIM1_3 - TRIM1_3 */ +#define FMUTEST_SOCTRIM1_3_TRIM1_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM1_3_TRIM1_3_SHIFT)) & FMUTEST_SOCTRIM1_3_TRIM1_3_MASK) +/*! @} */ + +/*! @name SOCTRIM2_0 - SoC Trim Phrase 2 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM2_0_TRIM2_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM2_0_TRIM2_0_SHIFT (0U) +/*! TRIM2_0 - TRIM2_0 */ +#define FMUTEST_SOCTRIM2_0_TRIM2_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_0_TRIM2_0_SHIFT)) & FMUTEST_SOCTRIM2_0_TRIM2_0_MASK) +/*! @} */ + +/*! @name SOCTRIM2_1 - SoC Trim Phrase 2 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM2_1_TRIM2_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM2_1_TRIM2_1_SHIFT (0U) +/*! TRIM2_1 - TRIM2_1 */ +#define FMUTEST_SOCTRIM2_1_TRIM2_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_1_TRIM2_1_SHIFT)) & FMUTEST_SOCTRIM2_1_TRIM2_1_MASK) +/*! @} */ + +/*! @name SOCTRIM2_2 - SoC Trim Phrase 2 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM2_2_TRIM2_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM2_2_TRIM2_2_SHIFT (0U) +/*! TRIM2_2 - TRIM2_2 */ +#define FMUTEST_SOCTRIM2_2_TRIM2_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_2_TRIM2_2_SHIFT)) & FMUTEST_SOCTRIM2_2_TRIM2_2_MASK) +/*! @} */ + +/*! @name SOCTRIM2_3 - SoC Trim Phrase 2 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM2_3_TRIM2_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM2_3_TRIM2_3_SHIFT (0U) +/*! TRIM2_3 - TRIM2_3 */ +#define FMUTEST_SOCTRIM2_3_TRIM2_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM2_3_TRIM2_3_SHIFT)) & FMUTEST_SOCTRIM2_3_TRIM2_3_MASK) +/*! @} */ + +/*! @name SOCTRIM3_0 - SoC Trim Phrase 3 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM3_0_TRIM3_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM3_0_TRIM3_0_SHIFT (0U) +/*! TRIM3_0 - TRIM3_0 */ +#define FMUTEST_SOCTRIM3_0_TRIM3_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_0_TRIM3_0_SHIFT)) & FMUTEST_SOCTRIM3_0_TRIM3_0_MASK) +/*! @} */ + +/*! @name SOCTRIM3_1 - SoC Trim Phrase 3 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM3_1_TRIM3_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM3_1_TRIM3_1_SHIFT (0U) +/*! TRIM3_1 - TRIM3_1 */ +#define FMUTEST_SOCTRIM3_1_TRIM3_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_1_TRIM3_1_SHIFT)) & FMUTEST_SOCTRIM3_1_TRIM3_1_MASK) +/*! @} */ + +/*! @name SOCTRIM3_2 - SoC Trim Phrase 3 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM3_2_TRIM3_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM3_2_TRIM3_2_SHIFT (0U) +/*! TRIM3_2 - TRIM3_2 */ +#define FMUTEST_SOCTRIM3_2_TRIM3_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_2_TRIM3_2_SHIFT)) & FMUTEST_SOCTRIM3_2_TRIM3_2_MASK) +/*! @} */ + +/*! @name SOCTRIM3_3 - SoC Trim Phrase 3 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM3_3_TRIM3_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM3_3_TRIM3_3_SHIFT (0U) +/*! TRIM3_3 - TRIM3_3 */ +#define FMUTEST_SOCTRIM3_3_TRIM3_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM3_3_TRIM3_3_SHIFT)) & FMUTEST_SOCTRIM3_3_TRIM3_3_MASK) +/*! @} */ + +/*! @name SOCTRIM4_0 - SoC Trim Phrase 4 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM4_0_TRIM4_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM4_0_TRIM4_0_SHIFT (0U) +/*! TRIM4_0 - TRIM4_0 */ +#define FMUTEST_SOCTRIM4_0_TRIM4_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_0_TRIM4_0_SHIFT)) & FMUTEST_SOCTRIM4_0_TRIM4_0_MASK) +/*! @} */ + +/*! @name SOCTRIM4_1 - SoC Trim Phrase 4 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM4_1_TRIM4_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM4_1_TRIM4_1_SHIFT (0U) +/*! TRIM4_1 - TRIM4_1 */ +#define FMUTEST_SOCTRIM4_1_TRIM4_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_1_TRIM4_1_SHIFT)) & FMUTEST_SOCTRIM4_1_TRIM4_1_MASK) +/*! @} */ + +/*! @name SOCTRIM4_2 - SoC Trim Phrase 4 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM4_2_TRIM4_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM4_2_TRIM4_2_SHIFT (0U) +/*! TRIM4_2 - TRIM4_2 */ +#define FMUTEST_SOCTRIM4_2_TRIM4_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_2_TRIM4_2_SHIFT)) & FMUTEST_SOCTRIM4_2_TRIM4_2_MASK) +/*! @} */ + +/*! @name SOCTRIM4_3 - SoC Trim Phrase 4 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM4_3_TRIM4_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM4_3_TRIM4_3_SHIFT (0U) +/*! TRIM4_3 - TRIM4_3 */ +#define FMUTEST_SOCTRIM4_3_TRIM4_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM4_3_TRIM4_3_SHIFT)) & FMUTEST_SOCTRIM4_3_TRIM4_3_MASK) +/*! @} */ + +/*! @name SOCTRIM5_0 - SoC Trim Phrase 5 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM5_0_TRIM5_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM5_0_TRIM5_0_SHIFT (0U) +/*! TRIM5_0 - TRIM5_0 */ +#define FMUTEST_SOCTRIM5_0_TRIM5_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_0_TRIM5_0_SHIFT)) & FMUTEST_SOCTRIM5_0_TRIM5_0_MASK) +/*! @} */ + +/*! @name SOCTRIM5_1 - SoC Trim Phrase 5 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM5_1_TRIM5_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM5_1_TRIM5_1_SHIFT (0U) +/*! TRIM5_1 - TRIM5_1 */ +#define FMUTEST_SOCTRIM5_1_TRIM5_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_1_TRIM5_1_SHIFT)) & FMUTEST_SOCTRIM5_1_TRIM5_1_MASK) +/*! @} */ + +/*! @name SOCTRIM5_2 - SoC Trim Phrase 5 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM5_2_TRIM5_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM5_2_TRIM5_2_SHIFT (0U) +/*! TRIM5_2 - TRIM5_2 */ +#define FMUTEST_SOCTRIM5_2_TRIM5_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_2_TRIM5_2_SHIFT)) & FMUTEST_SOCTRIM5_2_TRIM5_2_MASK) +/*! @} */ + +/*! @name SOCTRIM5_3 - SoC Trim Phrase 5 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM5_3_TRIM5_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM5_3_TRIM5_3_SHIFT (0U) +/*! TRIM5_3 - TRIM5_3 */ +#define FMUTEST_SOCTRIM5_3_TRIM5_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM5_3_TRIM5_3_SHIFT)) & FMUTEST_SOCTRIM5_3_TRIM5_3_MASK) +/*! @} */ + +/*! @name SOCTRIM6_0 - SoC Trim Phrase 6 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM6_0_TRIM6_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM6_0_TRIM6_0_SHIFT (0U) +/*! TRIM6_0 - TRIM6_0 */ +#define FMUTEST_SOCTRIM6_0_TRIM6_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_0_TRIM6_0_SHIFT)) & FMUTEST_SOCTRIM6_0_TRIM6_0_MASK) +/*! @} */ + +/*! @name SOCTRIM6_1 - SoC Trim Phrase 6 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM6_1_TRIM6_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM6_1_TRIM6_1_SHIFT (0U) +/*! TRIM6_1 - TRIM6_1 */ +#define FMUTEST_SOCTRIM6_1_TRIM6_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_1_TRIM6_1_SHIFT)) & FMUTEST_SOCTRIM6_1_TRIM6_1_MASK) +/*! @} */ + +/*! @name SOCTRIM6_2 - SoC Trim Phrase 6 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM6_2_TRIM6_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM6_2_TRIM6_2_SHIFT (0U) +/*! TRIM6_2 - TRIM6_2 */ +#define FMUTEST_SOCTRIM6_2_TRIM6_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_2_TRIM6_2_SHIFT)) & FMUTEST_SOCTRIM6_2_TRIM6_2_MASK) +/*! @} */ + +/*! @name SOCTRIM6_3 - SoC Trim Phrase 6 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM6_3_TRIM6_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM6_3_TRIM6_3_SHIFT (0U) +/*! TRIM6_3 - TRIM6_3 */ +#define FMUTEST_SOCTRIM6_3_TRIM6_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM6_3_TRIM6_3_SHIFT)) & FMUTEST_SOCTRIM6_3_TRIM6_3_MASK) +/*! @} */ + +/*! @name SOCTRIM7_0 - SoC Trim Phrase 7 Word 0 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM7_0_TRIM7_0_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM7_0_TRIM7_0_SHIFT (0U) +/*! TRIM7_0 - TRIM7_0 */ +#define FMUTEST_SOCTRIM7_0_TRIM7_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_0_TRIM7_0_SHIFT)) & FMUTEST_SOCTRIM7_0_TRIM7_0_MASK) +/*! @} */ + +/*! @name SOCTRIM7_1 - SoC Trim Phrase 7 Word 1 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM7_1_TRIM7_1_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM7_1_TRIM7_1_SHIFT (0U) +/*! TRIM7_1 - TRIM7_1 */ +#define FMUTEST_SOCTRIM7_1_TRIM7_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_1_TRIM7_1_SHIFT)) & FMUTEST_SOCTRIM7_1_TRIM7_1_MASK) +/*! @} */ + +/*! @name SOCTRIM7_2 - SoC Trim Phrase 7 Word 2 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM7_2_TRIM7_2_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM7_2_TRIM7_2_SHIFT (0U) +/*! TRIM7_2 - TRIM7_2 */ +#define FMUTEST_SOCTRIM7_2_TRIM7_2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_2_TRIM7_2_SHIFT)) & FMUTEST_SOCTRIM7_2_TRIM7_2_MASK) +/*! @} */ + +/*! @name SOCTRIM7_3 - SoC Trim Phrase 7 Word 3 Register */ +/*! @{ */ + +#define FMUTEST_SOCTRIM7_3_TRIM7_3_MASK (0xFFFFFFFFU) +#define FMUTEST_SOCTRIM7_3_TRIM7_3_SHIFT (0U) +/*! TRIM7_3 - TRIM7_3 */ +#define FMUTEST_SOCTRIM7_3_TRIM7_3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SOCTRIM7_3_TRIM7_3_SHIFT)) & FMUTEST_SOCTRIM7_3_TRIM7_3_MASK) +/*! @} */ + +/*! @name R_IP_CONFIG - BIST Configuration Register */ +/*! @{ */ + +#define FMUTEST_R_IP_CONFIG_IPSEL0_MASK (0x3U) +#define FMUTEST_R_IP_CONFIG_IPSEL0_SHIFT (0U) +/*! IPSEL0 - Block 0 Select Control + * 0b00..Unselect block 0 + * 0b01..not used, reserved + * 0b10..Enable block 0 test, repair off (default) + * 0b11..Enable block 0 test, repair on + */ +#define FMUTEST_R_IP_CONFIG_IPSEL0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_IPSEL0_SHIFT)) & FMUTEST_R_IP_CONFIG_IPSEL0_MASK) + +#define FMUTEST_R_IP_CONFIG_IPSEL1_MASK (0xCU) +#define FMUTEST_R_IP_CONFIG_IPSEL1_SHIFT (2U) +/*! IPSEL1 - Block 1 Select Control + * 0b00..Unselect block 1 + * 0b01..not used, reserved + * 0b10..Enable block 1 test, repair off (default) + * 0b11..Enable block 1 test, repair on + */ +#define FMUTEST_R_IP_CONFIG_IPSEL1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_IPSEL1_SHIFT)) & FMUTEST_R_IP_CONFIG_IPSEL1_MASK) + +#define FMUTEST_R_IP_CONFIG_BIST_CDIVL_MASK (0xFF0U) +#define FMUTEST_R_IP_CONFIG_BIST_CDIVL_SHIFT (4U) +/*! BIST_CDIVL - Clock Divide Scalar for Long Pulse */ +#define FMUTEST_R_IP_CONFIG_BIST_CDIVL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_BIST_CDIVL_SHIFT)) & FMUTEST_R_IP_CONFIG_BIST_CDIVL_MASK) + +#define FMUTEST_R_IP_CONFIG_CDIVS_MASK (0x7000U) +#define FMUTEST_R_IP_CONFIG_CDIVS_SHIFT (12U) +/*! CDIVS - Number of clock cycles to generate short pulse */ +#define FMUTEST_R_IP_CONFIG_CDIVS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_CDIVS_SHIFT)) & FMUTEST_R_IP_CONFIG_CDIVS_MASK) + +#define FMUTEST_R_IP_CONFIG_BIST_TVFY_MASK (0xF8000U) +#define FMUTEST_R_IP_CONFIG_BIST_TVFY_SHIFT (15U) +/*! BIST_TVFY - Timer adjust for verify */ +#define FMUTEST_R_IP_CONFIG_BIST_TVFY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_BIST_TVFY_SHIFT)) & FMUTEST_R_IP_CONFIG_BIST_TVFY_MASK) + +#define FMUTEST_R_IP_CONFIG_TSTCTL_MASK (0x300000U) +#define FMUTEST_R_IP_CONFIG_TSTCTL_SHIFT (20U) +/*! TSTCTL - BIST self-test control + * 0b00..Default, disable both BIST self-test and MISR + * 0b01..Enable BIST self-test mode DOUT from macro will be forced to '0', and disable MISR. + * 0b10..Enable MISR + * 0b11..Enable both BIST self-test mode and MISR + */ +#define FMUTEST_R_IP_CONFIG_TSTCTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_TSTCTL_SHIFT)) & FMUTEST_R_IP_CONFIG_TSTCTL_MASK) + +#define FMUTEST_R_IP_CONFIG_DBGCTL_MASK (0x400000U) +#define FMUTEST_R_IP_CONFIG_DBGCTL_SHIFT (22U) +/*! DBGCTL - Debug feature control + * 0b0..Default + * 0b1..Enable debug feature to collect failure address and data. + */ +#define FMUTEST_R_IP_CONFIG_DBGCTL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_DBGCTL_SHIFT)) & FMUTEST_R_IP_CONFIG_DBGCTL_MASK) + +#define FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_MASK (0x800000U) +#define FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_SHIFT (23U) +/*! BIST_CLK_SEL - BIST Clock Select */ +#define FMUTEST_R_IP_CONFIG_BIST_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_SHIFT)) & FMUTEST_R_IP_CONFIG_BIST_CLK_SEL_MASK) + +#define FMUTEST_R_IP_CONFIG_SMWTST_MASK (0x3000000U) +#define FMUTEST_R_IP_CONFIG_SMWTST_SHIFT (24U) +/*! SMWTST - SMWR DOUT Function Control + * 0b00..Default + * 0b01..Enable SMWR self-test mode, DOUT from macro will be forced to all 0 + * 0b10..Enable SMWR self-test mode, DOUT from macro will be forced to all 1 + * 0b11..Reserved (unused) + */ +#define FMUTEST_R_IP_CONFIG_SMWTST(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_SMWTST_SHIFT)) & FMUTEST_R_IP_CONFIG_SMWTST_MASK) + +#define FMUTEST_R_IP_CONFIG_ECCEN_MASK (0x4000000U) +#define FMUTEST_R_IP_CONFIG_ECCEN_SHIFT (26U) +/*! ECCEN - BIST ECC Control + * 0b0..Default mode (no ECC encode or decode) + * 0b1..Enable ECC encode/decode + */ +#define FMUTEST_R_IP_CONFIG_ECCEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_IP_CONFIG_ECCEN_SHIFT)) & FMUTEST_R_IP_CONFIG_ECCEN_MASK) +/*! @} */ + +/*! @name R_TESTCODE - BIST Test Code Register */ +/*! @{ */ + +#define FMUTEST_R_TESTCODE_TESTCODE_MASK (0x3FU) +#define FMUTEST_R_TESTCODE_TESTCODE_SHIFT (0U) +/*! TESTCODE - Used to store test code information before running TMR-RST/TMRSET BIST command */ +#define FMUTEST_R_TESTCODE_TESTCODE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TESTCODE_TESTCODE_SHIFT)) & FMUTEST_R_TESTCODE_TESTCODE_MASK) +/*! @} */ + +/*! @name R_DFT_CTRL - BIST DFT Control Register */ +/*! @{ */ + +#define FMUTEST_R_DFT_CTRL_DFT_XADR_MASK (0xFU) +#define FMUTEST_R_DFT_CTRL_DFT_XADR_SHIFT (0U) +/*! DFT_XADR - DFT XADR Pattern + * 0b0000..XADR fixed, no change at all + * 0b0001..XADR increased by 1 after row. For READ operation, XADR increases by 1 after reading the last word of + * row. For PROG operation, XADR increases by 1 after NVSTR falls. + * 0b0010..XADR increased for diagonal. For PROG-DIAGONAL operation, XADR is increased to create diagonal pattern. + * 0b0011..XADR increased by sector. During ERASE operation, XADR increased by number of rows in a sector when NVSTR falls. + * 0b0100..XADR inversed. XADR is inversed after reading one word or after programming one row when NVSTR falls. + * 0b0101..XADR increased by 2 after row. For READ operation, XADR is increased by 2 after reading the last word + * of a row. For PROG operation, XADR is increased by 2 when NVSTR falls. + * 0b0110..XADR[0] inversed. XADR[0] is inversed after reading one word or after programming one row when NVSTR falls. + * 0b0111..XADR increased by 1. For READ operations only, XADR increased by 1 after each read cycle. + * 0b1000..XADR decreased by 1 after row. For READ operations only, XADR is decreased by 1 after YADR decreases to 0. + * 0b1001..XADR decreased by 1. For READ operations only, XADR is decreased by 1 after each read cycle. + */ +#define FMUTEST_R_DFT_CTRL_DFT_XADR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_XADR_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_XADR_MASK) + +#define FMUTEST_R_DFT_CTRL_DFT_YADR_MASK (0xF0U) +#define FMUTEST_R_DFT_CTRL_DFT_YADR_SHIFT (4U) +/*! DFT_YADR - DFT YADR Pattern + * 0b0000..YADR fixed, no change at all + * 0b0001..YADR for ICKBD. For PROG and READ operations, YADR changed to generate inverse checkerboard pattern. + * 0b0010..YADR for CKBD. For PROG and READ operations, YADR changed to generate checkerboard pattern. + * 0b0011..YADR increased by 1. For READ operations, YADR increased by 1 after each read cycle. For PROG + * operations, YADR increased by 1 after YE falls. + * 0b0100..YADR increased for diagonal. For PROG-DIAGONAL operation, YADR is increased to create diagonal pattern. + * 0b0101..YADR inversed. YADR is inversed after reading one word or after programming one word when YE falls. + * 0b0110..YADR[0] inversed. YADR[0] is inversed after reading one word or after programming one word when YE falls. + * 0b0111..YADR increased by 1 after last row. For READ operations only, YADR is increased by 1 after XADR reaches last row. + * 0b1000..YADR decreased by 1. For READ operations only, YADR is decreased by 1 after each read cycle. + * 0b1001..YADR decreased by 1 after first row. For READ operations only, YADR is decreased by 1 after XADR decreases to 0. + */ +#define FMUTEST_R_DFT_CTRL_DFT_YADR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_YADR_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_YADR_MASK) + +#define FMUTEST_R_DFT_CTRL_DFT_DATA_MASK (0xF00U) +#define FMUTEST_R_DFT_CTRL_DFT_DATA_SHIFT (8U) +/*! DFT_DATA - DFT Data Pattern + * 0b0000..CKBD pattern. For READ operations only, compare DOUT with checkerboard data pattern for each read cycle. + * 0b0001..ICKBD pattern. For READ operations only, compare DOUT with inverse checkerboard data pattern for each read cycle. + * 0b0010..Diagonal pattern. Used for READ operations only, compare DOUT to diagonal pattern. + * 0b0011..Fixed data pattern. For READ operations, comparison to DOUT for selected groups; refer to + * R_ADR_CTRL[GRPSEL] for modules with multiple groups. + * 0b0100..Random data pattern which will be generated based on the initial seed set in R_DATA; for READ + * operations, used for DOUT comparison of selected groups. For PROG operations, used to control DIN of selected + * groups. + * 0b0101..DOUT based pattern. For READ operations only, DOUT of selected group will be latched in R_DATA. If + * more than one group is selected in R_ADR_CTRL[GRPSEL], the group with the lower index will be latched. + * 0b0110..R_DATA based pattern. For READ operations, expected DOUT value of selected groups equals to R_DATA + * when XADR[0]==YADR[0] or ~R_DATA when XADR[0]!=YADR[0]. For PROG operations, DIN of selected groups equals + * R_DATA when XADR[0]==YADR[0] or ~R_DATA when XADR[0]!=YADR[0]. + * 0b0111..SCAN-IO pattern. For READ operations, control expected DOUT value of selected groups to SCAN-IO data + * pattern. For PROG operations, control DIN of selected groups to SCAN-IO data pattern. + * 0b1000..REPAIR set. For PROG operation to IFR1(7,1) and IFR1(7,2), R_REPAIR0_0 and R_REPAIR0_1 or R_REPAIR1_0 + * and R_REPAIR1_1 will control DIN. For READ operation on IFR1(7,1) and IFR1(7,2), DOUT will be compared + * against R_REPAIR0_0 and R_REPAIR0_1 or R_REPAIR1_0 andR_REPAIR1_1. When this option is selected, only + * one flash block can be selected. + * 0b1001..REPAIR load. For READ operation only, DOUT from IFR1(7,1) and IFR1(7,2) is loaded to R_REPAIR0 and R_REPAIR1. + */ +#define FMUTEST_R_DFT_CTRL_DFT_DATA(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_DATA_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_DATA_MASK) + +#define FMUTEST_R_DFT_CTRL_CMP_MASK_MASK (0x3000U) +#define FMUTEST_R_DFT_CTRL_CMP_MASK_SHIFT (12U) +/*! CMP_MASK - Data Compare Mask + * 0b00..Expected data is compared to DOUT + * 0b01..Expected data (only 0s are considered) are compared to DOUT + * 0b10..Expected data (only 1s are considered) are compared to DOUT + */ +#define FMUTEST_R_DFT_CTRL_CMP_MASK(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_CMP_MASK_SHIFT)) & FMUTEST_R_DFT_CTRL_CMP_MASK_MASK) + +#define FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_MASK (0x4000U) +#define FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_SHIFT (14U) +/*! DFT_DATA_SRC - DFT Data Source + * 0b0..{R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0} is used + * 0b1..{R_DATA_CTRL3,R_DATA_CTRL2_EX[2:0],R_DATA_CTRL2,R_DATA_CTRL1_EX[2:0],R_DATA_CTRL1,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0} is used + */ +#define FMUTEST_R_DFT_CTRL_DFT_DATA_SRC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_SHIFT)) & FMUTEST_R_DFT_CTRL_DFT_DATA_SRC_MASK) +/*! @} */ + +/*! @name R_ADR_CTRL - BIST Address Control Register */ +/*! @{ */ + +#define FMUTEST_R_ADR_CTRL_GRPSEL_MASK (0xFU) +#define FMUTEST_R_ADR_CTRL_GRPSEL_SHIFT (0U) +/*! GRPSEL - Data Group Select + * 0b0000..Select no data + * 0b0001..Select data slice [34:0] + * 0b0010..Select data slice [69:35] + * 0b0100..Select data slice [104:70] + * 0b1000..Select data slice [136:105] + * 0b1111..Select data [136:0] + */ +#define FMUTEST_R_ADR_CTRL_GRPSEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_GRPSEL_SHIFT)) & FMUTEST_R_ADR_CTRL_GRPSEL_MASK) + +#define FMUTEST_R_ADR_CTRL_XADR_MASK (0xFFF0U) +#define FMUTEST_R_ADR_CTRL_XADR_SHIFT (4U) +/*! XADR - BIST XADR */ +#define FMUTEST_R_ADR_CTRL_XADR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_XADR_SHIFT)) & FMUTEST_R_ADR_CTRL_XADR_MASK) + +#define FMUTEST_R_ADR_CTRL_YADR_MASK (0x1F0000U) +#define FMUTEST_R_ADR_CTRL_YADR_SHIFT (16U) +/*! YADR - BIST YADR */ +#define FMUTEST_R_ADR_CTRL_YADR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_YADR_SHIFT)) & FMUTEST_R_ADR_CTRL_YADR_MASK) + +#define FMUTEST_R_ADR_CTRL_PROG_ATTR_MASK (0xE00000U) +#define FMUTEST_R_ADR_CTRL_PROG_ATTR_SHIFT (21U) +/*! PROG_ATTR - Program Attribute + * 0b000..One YE pulse will program one data slice group + * 0b001..One YE pulse will program two data slice groups + * 0b010..One YE pulse will program three data slice groups (reserved) + * 0b011..One YE pulse will program four data slice groups + * 0b100..One YE pulse will program five data slice groups (reserved) + * 0b101..One YE pulse will program six data slice groups (reserved) + * 0b110..One YE pulse will program seven data slice groups (reserved) + * 0b111..One YE pulse will program eight data slice groups (reserved) + */ +#define FMUTEST_R_ADR_CTRL_PROG_ATTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_CTRL_PROG_ATTR_SHIFT)) & FMUTEST_R_ADR_CTRL_PROG_ATTR_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL0 - BIST Data Control 0 Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL0_DATA0_MASK (0xFFFFFFFFU) +#define FMUTEST_R_DATA_CTRL0_DATA0_SHIFT (0U) +/*! DATA0 - BIST Data 0 Low */ +#define FMUTEST_R_DATA_CTRL0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL0_DATA0_SHIFT)) & FMUTEST_R_DATA_CTRL0_DATA0_MASK) +/*! @} */ + +/*! @name R_PIN_CTRL - BIST Pin Control Register */ +/*! @{ */ + +#define FMUTEST_R_PIN_CTRL_MAS1_MASK (0x1U) +#define FMUTEST_R_PIN_CTRL_MAS1_SHIFT (0U) +/*! MAS1 - Mass Erase */ +#define FMUTEST_R_PIN_CTRL_MAS1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_MAS1_SHIFT)) & FMUTEST_R_PIN_CTRL_MAS1_MASK) + +#define FMUTEST_R_PIN_CTRL_IFREN_MASK (0x2U) +#define FMUTEST_R_PIN_CTRL_IFREN_SHIFT (1U) +/*! IFREN - IFR Enable */ +#define FMUTEST_R_PIN_CTRL_IFREN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_IFREN_SHIFT)) & FMUTEST_R_PIN_CTRL_IFREN_MASK) + +#define FMUTEST_R_PIN_CTRL_IFREN1_MASK (0x4U) +#define FMUTEST_R_PIN_CTRL_IFREN1_SHIFT (2U) +/*! IFREN1 - IFR1 Enable */ +#define FMUTEST_R_PIN_CTRL_IFREN1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_IFREN1_SHIFT)) & FMUTEST_R_PIN_CTRL_IFREN1_MASK) + +#define FMUTEST_R_PIN_CTRL_REDEN_MASK (0x8U) +#define FMUTEST_R_PIN_CTRL_REDEN_SHIFT (3U) +/*! REDEN - Redundancy Block Enable */ +#define FMUTEST_R_PIN_CTRL_REDEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_REDEN_SHIFT)) & FMUTEST_R_PIN_CTRL_REDEN_MASK) + +#define FMUTEST_R_PIN_CTRL_LVE_MASK (0x10U) +#define FMUTEST_R_PIN_CTRL_LVE_SHIFT (4U) +/*! LVE - Low Voltage Enable */ +#define FMUTEST_R_PIN_CTRL_LVE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_LVE_SHIFT)) & FMUTEST_R_PIN_CTRL_LVE_MASK) + +#define FMUTEST_R_PIN_CTRL_PV_MASK (0x20U) +#define FMUTEST_R_PIN_CTRL_PV_SHIFT (5U) +/*! PV - Program Verify Enable */ +#define FMUTEST_R_PIN_CTRL_PV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_PV_SHIFT)) & FMUTEST_R_PIN_CTRL_PV_MASK) + +#define FMUTEST_R_PIN_CTRL_EV_MASK (0x40U) +#define FMUTEST_R_PIN_CTRL_EV_SHIFT (6U) +/*! EV - Erase Verify Enable */ +#define FMUTEST_R_PIN_CTRL_EV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_EV_SHIFT)) & FMUTEST_R_PIN_CTRL_EV_MASK) + +#define FMUTEST_R_PIN_CTRL_WIPGM_MASK (0x180U) +#define FMUTEST_R_PIN_CTRL_WIPGM_SHIFT (7U) +/*! WIPGM - Program Current */ +#define FMUTEST_R_PIN_CTRL_WIPGM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_WIPGM_SHIFT)) & FMUTEST_R_PIN_CTRL_WIPGM_MASK) + +#define FMUTEST_R_PIN_CTRL_WHV_MASK (0x1E00U) +#define FMUTEST_R_PIN_CTRL_WHV_SHIFT (9U) +/*! WHV - High Voltage Level */ +#define FMUTEST_R_PIN_CTRL_WHV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_WHV_SHIFT)) & FMUTEST_R_PIN_CTRL_WHV_MASK) + +#define FMUTEST_R_PIN_CTRL_WMV_MASK (0xE000U) +#define FMUTEST_R_PIN_CTRL_WMV_SHIFT (13U) +/*! WMV - Medium Voltage Level */ +#define FMUTEST_R_PIN_CTRL_WMV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_WMV_SHIFT)) & FMUTEST_R_PIN_CTRL_WMV_MASK) + +#define FMUTEST_R_PIN_CTRL_XE_MASK (0x10000U) +#define FMUTEST_R_PIN_CTRL_XE_SHIFT (16U) +/*! XE - X Address Enable */ +#define FMUTEST_R_PIN_CTRL_XE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_XE_SHIFT)) & FMUTEST_R_PIN_CTRL_XE_MASK) + +#define FMUTEST_R_PIN_CTRL_YE_MASK (0x20000U) +#define FMUTEST_R_PIN_CTRL_YE_SHIFT (17U) +/*! YE - Y Address Enable */ +#define FMUTEST_R_PIN_CTRL_YE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_YE_SHIFT)) & FMUTEST_R_PIN_CTRL_YE_MASK) + +#define FMUTEST_R_PIN_CTRL_SE_MASK (0x40000U) +#define FMUTEST_R_PIN_CTRL_SE_SHIFT (18U) +/*! SE - Sense Amp Enable */ +#define FMUTEST_R_PIN_CTRL_SE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_SE_SHIFT)) & FMUTEST_R_PIN_CTRL_SE_MASK) + +#define FMUTEST_R_PIN_CTRL_ERASE_MASK (0x80000U) +#define FMUTEST_R_PIN_CTRL_ERASE_SHIFT (19U) +/*! ERASE - Erase Mode */ +#define FMUTEST_R_PIN_CTRL_ERASE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_ERASE_SHIFT)) & FMUTEST_R_PIN_CTRL_ERASE_MASK) + +#define FMUTEST_R_PIN_CTRL_PROG_MASK (0x100000U) +#define FMUTEST_R_PIN_CTRL_PROG_SHIFT (20U) +/*! PROG - Program Mode */ +#define FMUTEST_R_PIN_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_PROG_SHIFT)) & FMUTEST_R_PIN_CTRL_PROG_MASK) + +#define FMUTEST_R_PIN_CTRL_NVSTR_MASK (0x200000U) +#define FMUTEST_R_PIN_CTRL_NVSTR_SHIFT (21U) +/*! NVSTR - NVM Store */ +#define FMUTEST_R_PIN_CTRL_NVSTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_NVSTR_SHIFT)) & FMUTEST_R_PIN_CTRL_NVSTR_MASK) + +#define FMUTEST_R_PIN_CTRL_SLM_MASK (0x400000U) +#define FMUTEST_R_PIN_CTRL_SLM_SHIFT (22U) +/*! SLM - Sleep Mode Enable */ +#define FMUTEST_R_PIN_CTRL_SLM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_SLM_SHIFT)) & FMUTEST_R_PIN_CTRL_SLM_MASK) + +#define FMUTEST_R_PIN_CTRL_RECALL_MASK (0x800000U) +#define FMUTEST_R_PIN_CTRL_RECALL_SHIFT (23U) +/*! RECALL - Recall Trim Code */ +#define FMUTEST_R_PIN_CTRL_RECALL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_RECALL_SHIFT)) & FMUTEST_R_PIN_CTRL_RECALL_MASK) + +#define FMUTEST_R_PIN_CTRL_HEM_MASK (0x1000000U) +#define FMUTEST_R_PIN_CTRL_HEM_SHIFT (24U) +/*! HEM - HEM Control */ +#define FMUTEST_R_PIN_CTRL_HEM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_PIN_CTRL_HEM_SHIFT)) & FMUTEST_R_PIN_CTRL_HEM_MASK) +/*! @} */ + +/*! @name R_CNT_LOOP_CTRL - BIST Loop Count Control Register */ +/*! @{ */ + +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_MASK (0xFFFU) +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_SHIFT (0U) +/*! LOOPCNT - Loop Count Control */ +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPCNT_MASK) + +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_MASK (0x7000U) +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_SHIFT (12U) +/*! LOOPOPT - Loop Option + * 0b000..Loop is disabled; selected BIST operation is run once + * 0b001..Loop is enabled; XADR increments by 1 XADR increments by 1 for each new loop. Stops when total loop count meets LOOPCNT+1. + * 0b010..Loop is enabled; YADR increments by 1 YADR increments by 1 for each new loop. Stops when total loop count meets LOOPCNT+1. + * 0b011..Loop is enabled; XADR increments by 2 XADR increments by 2 for each new loop. Stops when total loop count meets LOOPCNT+1. + * 0b100..Loop is enabled; XADR increments by sector XADR increments by 16 for each new loop. Stops when total loop count meets LOOPCNT+1. + */ +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPOPT_MASK) + +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_MASK (0x38000U) +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_SHIFT (15U) +/*! LOOPUNIT - Loop Time Unit + * 0b000..Clock cycles + * 0b001..0.5 usec + * 0b010..1 usec + * 0b011..10 usec + * 0b100..100 usec + * 0b101..1 msec + * 0b110..10 msec + * 0b111..100 msec + */ +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPUNIT_MASK) + +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_MASK (0x1FC0000U) +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_SHIFT (18U) +/*! LOOPDLY - Loop Time Delay Scalar */ +#define FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_SHIFT)) & FMUTEST_R_CNT_LOOP_CTRL_LOOPDLY_MASK) +/*! @} */ + +/*! @name R_TIMER_CTRL - BIST Timer Control Register */ +/*! @{ */ + +#define FMUTEST_R_TIMER_CTRL_TNVSUNIT_MASK (0x7U) +#define FMUTEST_R_TIMER_CTRL_TNVSUNIT_SHIFT (0U) +/*! TNVSUNIT - Tnvs Time Unit + * 0b000..Clock cycles + * 0b001..0.5 usec + * 0b010..1 usec + * 0b011..10 usec + * 0b100..100 usec + * 0b101..1 msec + * 0b110..10 msec + * 0b111..100 msec + */ +#define FMUTEST_R_TIMER_CTRL_TNVSUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVSUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVSUNIT_MASK) + +#define FMUTEST_R_TIMER_CTRL_TNVSDLY_MASK (0x78U) +#define FMUTEST_R_TIMER_CTRL_TNVSDLY_SHIFT (3U) +/*! TNVSDLY - Tnvs Time Delay Scalar */ +#define FMUTEST_R_TIMER_CTRL_TNVSDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVSDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVSDLY_MASK) + +#define FMUTEST_R_TIMER_CTRL_TNVHUNIT_MASK (0x380U) +#define FMUTEST_R_TIMER_CTRL_TNVHUNIT_SHIFT (7U) +/*! TNVHUNIT - Tnvh Time Unit + * 0b000..Clock cycles + * 0b001..0.5 usec + * 0b010..1 usec + * 0b011..10 usec + * 0b100..100 usec + * 0b101..1 msec + * 0b110..10 msec + * 0b111..100 msec + */ +#define FMUTEST_R_TIMER_CTRL_TNVHUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVHUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVHUNIT_MASK) + +#define FMUTEST_R_TIMER_CTRL_TNVHDLY_MASK (0x3C00U) +#define FMUTEST_R_TIMER_CTRL_TNVHDLY_SHIFT (10U) +/*! TNVHDLY - Tnvh Time Delay Scalar */ +#define FMUTEST_R_TIMER_CTRL_TNVHDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TNVHDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TNVHDLY_MASK) + +#define FMUTEST_R_TIMER_CTRL_TPGSUNIT_MASK (0x1C000U) +#define FMUTEST_R_TIMER_CTRL_TPGSUNIT_SHIFT (14U) +/*! TPGSUNIT - Tpgs Time Unit + * 0b000..Clock cycles + * 0b001..0.5 usec + * 0b010..1 usec + * 0b011..10 usec + * 0b100..100 usec + * 0b101..1 msec + * 0b110..10 msec + * 0b111..100 msec + */ +#define FMUTEST_R_TIMER_CTRL_TPGSUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TPGSUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TPGSUNIT_MASK) + +#define FMUTEST_R_TIMER_CTRL_TPGSDLY_MASK (0x1E0000U) +#define FMUTEST_R_TIMER_CTRL_TPGSDLY_SHIFT (17U) +/*! TPGSDLY - Tpgs Time Delay Scalar */ +#define FMUTEST_R_TIMER_CTRL_TPGSDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TPGSDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TPGSDLY_MASK) + +#define FMUTEST_R_TIMER_CTRL_TRCVUNIT_MASK (0xE00000U) +#define FMUTEST_R_TIMER_CTRL_TRCVUNIT_SHIFT (21U) +/*! TRCVUNIT - Trcv Time Unit + * 0b000..Clock cycles + * 0b001..0.5 usec + * 0b010..1 usec + * 0b011..10 usec + * 0b100..100 usec + * 0b101..1 msec + * 0b110..10 msec + * 0b111..100 msec + */ +#define FMUTEST_R_TIMER_CTRL_TRCVUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TRCVUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TRCVUNIT_MASK) + +#define FMUTEST_R_TIMER_CTRL_TRCVDLY_MASK (0xF000000U) +#define FMUTEST_R_TIMER_CTRL_TRCVDLY_SHIFT (24U) +/*! TRCVDLY - Trcv Time Delay Scalar */ +#define FMUTEST_R_TIMER_CTRL_TRCVDLY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TRCVDLY_SHIFT)) & FMUTEST_R_TIMER_CTRL_TRCVDLY_MASK) + +#define FMUTEST_R_TIMER_CTRL_TLVSUNIT_MASK (0x70000000U) +#define FMUTEST_R_TIMER_CTRL_TLVSUNIT_SHIFT (28U) +/*! TLVSUNIT - Tlvs Time Unit + * 0b000..Clock cycles + * 0b001..0.5 usec + * 0b010..1 usec + * 0b011..10 usec + * 0b100..100 usec + * 0b101..1 msec + * 0b110..10 msec + * 0b111..100 msec + */ +#define FMUTEST_R_TIMER_CTRL_TLVSUNIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TLVSUNIT_SHIFT)) & FMUTEST_R_TIMER_CTRL_TLVSUNIT_MASK) + +#define FMUTEST_R_TIMER_CTRL_TLVSDLY_L_MASK (0x80000000U) +#define FMUTEST_R_TIMER_CTRL_TLVSDLY_L_SHIFT (31U) +/*! TLVSDLY_L - Tlvs Time Delay Scalar Low */ +#define FMUTEST_R_TIMER_CTRL_TLVSDLY_L(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_TLVSDLY_L_SHIFT)) & FMUTEST_R_TIMER_CTRL_TLVSDLY_L_MASK) +/*! @} */ + +/*! @name R_TEST_CTRL - BIST Test Control Register */ +/*! @{ */ + +#define FMUTEST_R_TEST_CTRL_BUSY_MASK (0x1U) +#define FMUTEST_R_TEST_CTRL_BUSY_SHIFT (0U) +/*! BUSY - BIST Busy Status + * 0b0..BIST is idle + * 0b1..BIST is busy + */ +#define FMUTEST_R_TEST_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_BUSY_SHIFT)) & FMUTEST_R_TEST_CTRL_BUSY_MASK) + +#define FMUTEST_R_TEST_CTRL_DEBUG_MASK (0x2U) +#define FMUTEST_R_TEST_CTRL_DEBUG_SHIFT (1U) +/*! DEBUG - BIST Debug Status */ +#define FMUTEST_R_TEST_CTRL_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DEBUG_SHIFT)) & FMUTEST_R_TEST_CTRL_DEBUG_MASK) + +#define FMUTEST_R_TEST_CTRL_STATUS0_MASK (0x4U) +#define FMUTEST_R_TEST_CTRL_STATUS0_SHIFT (2U) +/*! STATUS0 - BIST Status 0 + * 0b0..BIST test passed on flash block 0 + * 0b1..BIST test failed on flash block 0 + */ +#define FMUTEST_R_TEST_CTRL_STATUS0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_STATUS0_SHIFT)) & FMUTEST_R_TEST_CTRL_STATUS0_MASK) + +#define FMUTEST_R_TEST_CTRL_STATUS1_MASK (0x8U) +#define FMUTEST_R_TEST_CTRL_STATUS1_SHIFT (3U) +/*! STATUS1 - BIST status 1 + * 0b0..BIST test passed on flash block 1 + * 0b1..BIST test failed on flash block 1 + */ +#define FMUTEST_R_TEST_CTRL_STATUS1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_STATUS1_SHIFT)) & FMUTEST_R_TEST_CTRL_STATUS1_MASK) + +#define FMUTEST_R_TEST_CTRL_DEBUGRUN_MASK (0x10U) +#define FMUTEST_R_TEST_CTRL_DEBUGRUN_SHIFT (4U) +/*! DEBUGRUN - BIST Continue Debug Run */ +#define FMUTEST_R_TEST_CTRL_DEBUGRUN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DEBUGRUN_SHIFT)) & FMUTEST_R_TEST_CTRL_DEBUGRUN_MASK) + +#define FMUTEST_R_TEST_CTRL_STARTRUN_MASK (0x20U) +#define FMUTEST_R_TEST_CTRL_STARTRUN_SHIFT (5U) +/*! STARTRUN - Run New BIST Operation */ +#define FMUTEST_R_TEST_CTRL_STARTRUN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_STARTRUN_SHIFT)) & FMUTEST_R_TEST_CTRL_STARTRUN_MASK) + +#define FMUTEST_R_TEST_CTRL_CMDINDEX_MASK (0xFFC0U) +#define FMUTEST_R_TEST_CTRL_CMDINDEX_SHIFT (6U) +/*! CMDINDEX - BIST Command Index (code) */ +#define FMUTEST_R_TEST_CTRL_CMDINDEX(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_CMDINDEX_SHIFT)) & FMUTEST_R_TEST_CTRL_CMDINDEX_MASK) + +#define FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK (0x10000U) +#define FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT (16U) +/*! DISABLE_IP1 - BIST Disable IP1 */ +#define FMUTEST_R_TEST_CTRL_DISABLE_IP1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TEST_CTRL_DISABLE_IP1_SHIFT)) & FMUTEST_R_TEST_CTRL_DISABLE_IP1_MASK) +/*! @} */ + +/*! @name R_ABORT_LOOP - BIST Abort Loop Register */ +/*! @{ */ + +#define FMUTEST_R_ABORT_LOOP_ABORT_LOOP_MASK (0x1U) +#define FMUTEST_R_ABORT_LOOP_ABORT_LOOP_SHIFT (0U) +/*! ABORT_LOOP - Abort Loop + * 0b0..No effect + * 0b1..Abort BIST loop commands and force the loop counter to return to 0x0 + */ +#define FMUTEST_R_ABORT_LOOP_ABORT_LOOP(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ABORT_LOOP_ABORT_LOOP_SHIFT)) & FMUTEST_R_ABORT_LOOP_ABORT_LOOP_MASK) +/*! @} */ + +/*! @name R_ADR_QUERY - BIST Address Query Register */ +/*! @{ */ + +#define FMUTEST_R_ADR_QUERY_YADRFAIL_MASK (0x1FU) +#define FMUTEST_R_ADR_QUERY_YADRFAIL_SHIFT (0U) +/*! YADRFAIL - Failing YADR */ +#define FMUTEST_R_ADR_QUERY_YADRFAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_QUERY_YADRFAIL_SHIFT)) & FMUTEST_R_ADR_QUERY_YADRFAIL_MASK) + +#define FMUTEST_R_ADR_QUERY_XADRFAIL_MASK (0x1FFE0U) +#define FMUTEST_R_ADR_QUERY_XADRFAIL_SHIFT (5U) +/*! XADRFAIL - Failing XADR */ +#define FMUTEST_R_ADR_QUERY_XADRFAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_ADR_QUERY_XADRFAIL_SHIFT)) & FMUTEST_R_ADR_QUERY_XADRFAIL_MASK) +/*! @} */ + +/*! @name R_DOUT_QUERY0 - BIST DOUT Query 0 Register */ +/*! @{ */ + +#define FMUTEST_R_DOUT_QUERY0_DOUTFAIL_MASK (0xFFFFFFFFU) +#define FMUTEST_R_DOUT_QUERY0_DOUTFAIL_SHIFT (0U) +/*! DOUTFAIL - Failing DOUT Low */ +#define FMUTEST_R_DOUT_QUERY0_DOUTFAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DOUT_QUERY0_DOUTFAIL_SHIFT)) & FMUTEST_R_DOUT_QUERY0_DOUTFAIL_MASK) +/*! @} */ + +/*! @name R_SMW_QUERY - BIST SMW Query Register */ +/*! @{ */ + +#define FMUTEST_R_SMW_QUERY_SMWLOOP_MASK (0x3FFU) +#define FMUTEST_R_SMW_QUERY_SMWLOOP_SHIFT (0U) +/*! SMWLOOP - SMW Total Loop Count */ +#define FMUTEST_R_SMW_QUERY_SMWLOOP(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_QUERY_SMWLOOP_SHIFT)) & FMUTEST_R_SMW_QUERY_SMWLOOP_MASK) + +#define FMUTEST_R_SMW_QUERY_SMWLAST_MASK (0x7FC00U) +#define FMUTEST_R_SMW_QUERY_SMWLAST_SHIFT (10U) +/*! SMWLAST - SMW Last Voltage Setting */ +#define FMUTEST_R_SMW_QUERY_SMWLAST(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_QUERY_SMWLAST_SHIFT)) & FMUTEST_R_SMW_QUERY_SMWLAST_MASK) +/*! @} */ + +/*! @name R_SMW_SETTING0 - BIST SMW Setting 0 Register */ +/*! @{ */ + +#define FMUTEST_R_SMW_SETTING0_SMWPARM0_MASK (0x7FFFFFFFU) +#define FMUTEST_R_SMW_SETTING0_SMWPARM0_SHIFT (0U) +/*! SMWPARM0 - SMW Parameter Set 0 */ +#define FMUTEST_R_SMW_SETTING0_SMWPARM0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING0_SMWPARM0_SHIFT)) & FMUTEST_R_SMW_SETTING0_SMWPARM0_MASK) +/*! @} */ + +/*! @name R_SMW_SETTING1 - BIST SMW Setting 1 Register */ +/*! @{ */ + +#define FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK (0xFFFFFFFU) +#define FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT (0U) +/*! SMWPARM1 - SMW Parameter Set 1 */ +#define FMUTEST_R_SMW_SETTING1_SMWPARM1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING1_SMWPARM1_SHIFT)) & FMUTEST_R_SMW_SETTING1_SMWPARM1_MASK) +/*! @} */ + +/*! @name R_SMP_WHV0 - BIST SMP WHV Setting 0 Register */ +/*! @{ */ + +#define FMUTEST_R_SMP_WHV0_SMPWHV0_MASK (0xFFFFFFFFU) +#define FMUTEST_R_SMP_WHV0_SMPWHV0_SHIFT (0U) +/*! SMPWHV0 - SMP WHV Parameter Set 0 */ +#define FMUTEST_R_SMP_WHV0_SMPWHV0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMP_WHV0_SMPWHV0_SHIFT)) & FMUTEST_R_SMP_WHV0_SMPWHV0_MASK) +/*! @} */ + +/*! @name R_SMP_WHV1 - BIST SMP WHV Setting 1 Register */ +/*! @{ */ + +#define FMUTEST_R_SMP_WHV1_SMPWHV1_MASK (0xFFFFFFFFU) +#define FMUTEST_R_SMP_WHV1_SMPWHV1_SHIFT (0U) +/*! SMPWHV1 - SMP WHV Parameter Set 1 */ +#define FMUTEST_R_SMP_WHV1_SMPWHV1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMP_WHV1_SMPWHV1_SHIFT)) & FMUTEST_R_SMP_WHV1_SMPWHV1_MASK) +/*! @} */ + +/*! @name R_SME_WHV0 - BIST SME WHV Setting 0 Register */ +/*! @{ */ + +#define FMUTEST_R_SME_WHV0_SMEWHV0_MASK (0xFFFFFFFFU) +#define FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT (0U) +/*! SMEWHV0 - SME WHV Parameter Set 0 */ +#define FMUTEST_R_SME_WHV0_SMEWHV0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV0_SMEWHV0_SHIFT)) & FMUTEST_R_SME_WHV0_SMEWHV0_MASK) +/*! @} */ + +/*! @name R_SME_WHV1 - BIST SME WHV Setting 1 Register */ +/*! @{ */ + +#define FMUTEST_R_SME_WHV1_SMEWHV1_MASK (0xFFFFFFFFU) +#define FMUTEST_R_SME_WHV1_SMEWHV1_SHIFT (0U) +/*! SMEWHV1 - SME WHV Parameter Set 1 */ +#define FMUTEST_R_SME_WHV1_SMEWHV1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SME_WHV1_SMEWHV1_SHIFT)) & FMUTEST_R_SME_WHV1_SMEWHV1_MASK) +/*! @} */ + +/*! @name R_SMW_SETTING2 - BIST SMW Setting 2 Register */ +/*! @{ */ + +#define FMUTEST_R_SMW_SETTING2_SMWPARM2_MASK (0x1FFFFFFFU) +#define FMUTEST_R_SMW_SETTING2_SMWPARM2_SHIFT (0U) +/*! SMWPARM2 - SMW Parameter Set 2 */ +#define FMUTEST_R_SMW_SETTING2_SMWPARM2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING2_SMWPARM2_SHIFT)) & FMUTEST_R_SMW_SETTING2_SMWPARM2_MASK) +/*! @} */ + +/*! @name R_D_MISR0 - BIST DIN MISR 0 Register */ +/*! @{ */ + +#define FMUTEST_R_D_MISR0_DATASIG0_MASK (0xFFFFFFFFU) +#define FMUTEST_R_D_MISR0_DATASIG0_SHIFT (0U) +/*! DATASIG0 - Data Signature */ +#define FMUTEST_R_D_MISR0_DATASIG0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_D_MISR0_DATASIG0_SHIFT)) & FMUTEST_R_D_MISR0_DATASIG0_MASK) +/*! @} */ + +/*! @name R_A_MISR0 - BIST Address MISR 0 Register */ +/*! @{ */ + +#define FMUTEST_R_A_MISR0_ADRSIG0_MASK (0xFFFFFFFFU) +#define FMUTEST_R_A_MISR0_ADRSIG0_SHIFT (0U) +/*! ADRSIG0 - Address Signature */ +#define FMUTEST_R_A_MISR0_ADRSIG0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_A_MISR0_ADRSIG0_SHIFT)) & FMUTEST_R_A_MISR0_ADRSIG0_MASK) +/*! @} */ + +/*! @name R_C_MISR0 - BIST Control MISR 0 Register */ +/*! @{ */ + +#define FMUTEST_R_C_MISR0_CTRLSIG0_MASK (0xFFFFFFFFU) +#define FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT (0U) +/*! CTRLSIG0 - Control Signature */ +#define FMUTEST_R_C_MISR0_CTRLSIG0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR0_CTRLSIG0_SHIFT)) & FMUTEST_R_C_MISR0_CTRLSIG0_MASK) +/*! @} */ + +/*! @name R_SMW_SETTING3 - BIST SMW Setting 3 Register */ +/*! @{ */ + +#define FMUTEST_R_SMW_SETTING3_SMWPARM3_MASK (0x1FFFFU) +#define FMUTEST_R_SMW_SETTING3_SMWPARM3_SHIFT (0U) +/*! SMWPARM3 - SMW Parameter Set 3 */ +#define FMUTEST_R_SMW_SETTING3_SMWPARM3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_SMW_SETTING3_SMWPARM3_SHIFT)) & FMUTEST_R_SMW_SETTING3_SMWPARM3_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL1 - BIST Data Control 1 Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL1_DATA1_MASK (0xFFFFFFFFU) +#define FMUTEST_R_DATA_CTRL1_DATA1_SHIFT (0U) +/*! DATA1 - BIST Data 1 Low */ +#define FMUTEST_R_DATA_CTRL1_DATA1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL1_DATA1_SHIFT)) & FMUTEST_R_DATA_CTRL1_DATA1_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL2 - BIST Data Control 2 Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL2_DATA2_MASK (0xFFFFFFFFU) +#define FMUTEST_R_DATA_CTRL2_DATA2_SHIFT (0U) +/*! DATA2 - BIST Data 2 Low */ +#define FMUTEST_R_DATA_CTRL2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL2_DATA2_SHIFT)) & FMUTEST_R_DATA_CTRL2_DATA2_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL3 - BIST Data Control 3 Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL3_DATA3_MASK (0xFFFFFFFFU) +#define FMUTEST_R_DATA_CTRL3_DATA3_SHIFT (0U) +/*! DATA3 - BIST Data 3 Low */ +#define FMUTEST_R_DATA_CTRL3_DATA3(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL3_DATA3_SHIFT)) & FMUTEST_R_DATA_CTRL3_DATA3_MASK) +/*! @} */ + +/*! @name R_REPAIR0_0 - BIST Repair 0 for Block 0 Register */ +/*! @{ */ + +#define FMUTEST_R_REPAIR0_0_RDIS0_0_MASK (0x1U) +#define FMUTEST_R_REPAIR0_0_RDIS0_0_SHIFT (0U) +/*! RDIS0_0 - Control Repair 0 in Block 0. + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_R_REPAIR0_0_RDIS0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_0_RDIS0_0_SHIFT)) & FMUTEST_R_REPAIR0_0_RDIS0_0_MASK) + +#define FMUTEST_R_REPAIR0_0_RADR0_0_MASK (0x1FEU) +#define FMUTEST_R_REPAIR0_0_RADR0_0_SHIFT (1U) +/*! RADR0_0 - XADR for Repair 0 in Block 0 */ +#define FMUTEST_R_REPAIR0_0_RADR0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_0_RADR0_0_SHIFT)) & FMUTEST_R_REPAIR0_0_RADR0_0_MASK) +/*! @} */ + +/*! @name R_REPAIR0_1 - BIST Repair 1 Block 0 Register */ +/*! @{ */ + +#define FMUTEST_R_REPAIR0_1_RDIS0_1_MASK (0x1U) +#define FMUTEST_R_REPAIR0_1_RDIS0_1_SHIFT (0U) +/*! RDIS0_1 - Control Repair 1 in Block 0. + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_R_REPAIR0_1_RDIS0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_1_RDIS0_1_SHIFT)) & FMUTEST_R_REPAIR0_1_RDIS0_1_MASK) + +#define FMUTEST_R_REPAIR0_1_RADR0_1_MASK (0x1FEU) +#define FMUTEST_R_REPAIR0_1_RADR0_1_SHIFT (1U) +/*! RADR0_1 - XADR for Repair 1 in Block 0. */ +#define FMUTEST_R_REPAIR0_1_RADR0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR0_1_RADR0_1_SHIFT)) & FMUTEST_R_REPAIR0_1_RADR0_1_MASK) +/*! @} */ + +/*! @name R_REPAIR1_0 - BIST Repair 0 Block 1 Register */ +/*! @{ */ + +#define FMUTEST_R_REPAIR1_0_RDIS1_0_MASK (0x1U) +#define FMUTEST_R_REPAIR1_0_RDIS1_0_SHIFT (0U) +/*! RDIS1_0 - Control Repair 0 in Block 1. + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_R_REPAIR1_0_RDIS1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_0_RDIS1_0_SHIFT)) & FMUTEST_R_REPAIR1_0_RDIS1_0_MASK) + +#define FMUTEST_R_REPAIR1_0_RADR1_0_MASK (0x1FEU) +#define FMUTEST_R_REPAIR1_0_RADR1_0_SHIFT (1U) +/*! RADR1_0 - XADR for Repair 0 in Block 1. */ +#define FMUTEST_R_REPAIR1_0_RADR1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_0_RADR1_0_SHIFT)) & FMUTEST_R_REPAIR1_0_RADR1_0_MASK) +/*! @} */ + +/*! @name R_REPAIR1_1 - BIST Repair 1 Block 1 Register */ +/*! @{ */ + +#define FMUTEST_R_REPAIR1_1_RDIS1_1_MASK (0x1U) +#define FMUTEST_R_REPAIR1_1_RDIS1_1_SHIFT (0U) +/*! RDIS1_1 - Control Repair 1 in Block 1. + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_R_REPAIR1_1_RDIS1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_1_RDIS1_1_SHIFT)) & FMUTEST_R_REPAIR1_1_RDIS1_1_MASK) + +#define FMUTEST_R_REPAIR1_1_RADR1_1_MASK (0x1FEU) +#define FMUTEST_R_REPAIR1_1_RADR1_1_SHIFT (1U) +/*! RADR1_1 - XADR for Repair 1 in Block 1. */ +#define FMUTEST_R_REPAIR1_1_RADR1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_REPAIR1_1_RADR1_1_SHIFT)) & FMUTEST_R_REPAIR1_1_RADR1_1_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL0_EX - BIST Data Control 0 Extension Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL0_EX_DATA0X_MASK (0x7U) +#define FMUTEST_R_DATA_CTRL0_EX_DATA0X_SHIFT (0U) +/*! DATA0X - BIST Data 0 High */ +#define FMUTEST_R_DATA_CTRL0_EX_DATA0X(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL0_EX_DATA0X_SHIFT)) & FMUTEST_R_DATA_CTRL0_EX_DATA0X_MASK) +/*! @} */ + +/*! @name R_TIMER_CTRL_EX - BIST Timer Control Extension Register */ +/*! @{ */ + +#define FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_MASK (0x7U) +#define FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_SHIFT (0U) +/*! TLVSDLY_H - Tlvs Time Delay Scalar High */ +#define FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_SHIFT)) & FMUTEST_R_TIMER_CTRL_EX_TLVSDLY_H_MASK) +/*! @} */ + +/*! @name R_DOUT_QUERY1 - BIST DOUT Query 1 Register */ +/*! @{ */ + +#define FMUTEST_R_DOUT_QUERY1_DOUT_MASK (0x7U) +#define FMUTEST_R_DOUT_QUERY1_DOUT_SHIFT (0U) +/*! DOUT - Failing DOUT High */ +#define FMUTEST_R_DOUT_QUERY1_DOUT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DOUT_QUERY1_DOUT_SHIFT)) & FMUTEST_R_DOUT_QUERY1_DOUT_MASK) +/*! @} */ + +/*! @name R_D_MISR1 - BIST DIN MISR 1 Register */ +/*! @{ */ + +#define FMUTEST_R_D_MISR1_DATASIG1_MASK (0xFFU) +#define FMUTEST_R_D_MISR1_DATASIG1_SHIFT (0U) +/*! DATASIG1 - MISR Data Signature High */ +#define FMUTEST_R_D_MISR1_DATASIG1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_D_MISR1_DATASIG1_SHIFT)) & FMUTEST_R_D_MISR1_DATASIG1_MASK) +/*! @} */ + +/*! @name R_A_MISR1 - BIST Address MISR 1 Register */ +/*! @{ */ + +#define FMUTEST_R_A_MISR1_ADRSIG1_MASK (0xFFU) +#define FMUTEST_R_A_MISR1_ADRSIG1_SHIFT (0U) +/*! ADRSIG1 - MISR Address Signature High */ +#define FMUTEST_R_A_MISR1_ADRSIG1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_A_MISR1_ADRSIG1_SHIFT)) & FMUTEST_R_A_MISR1_ADRSIG1_MASK) +/*! @} */ + +/*! @name R_C_MISR1 - BIST Control MISR 1 Register */ +/*! @{ */ + +#define FMUTEST_R_C_MISR1_CTRLSIG1_MASK (0xFFU) +#define FMUTEST_R_C_MISR1_CTRLSIG1_SHIFT (0U) +/*! CTRLSIG1 - MISR Control Signature High */ +#define FMUTEST_R_C_MISR1_CTRLSIG1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_C_MISR1_CTRLSIG1_SHIFT)) & FMUTEST_R_C_MISR1_CTRLSIG1_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL1_EX - BIST Data Control 1 Extension Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL1_EX_DATA1X_MASK (0x7U) +#define FMUTEST_R_DATA_CTRL1_EX_DATA1X_SHIFT (0U) +/*! DATA1X - BIST Data 1 High */ +#define FMUTEST_R_DATA_CTRL1_EX_DATA1X(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL1_EX_DATA1X_SHIFT)) & FMUTEST_R_DATA_CTRL1_EX_DATA1X_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL2_EX - BIST Data Control 2 Extension Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL2_EX_DATA2X_MASK (0x7U) +#define FMUTEST_R_DATA_CTRL2_EX_DATA2X_SHIFT (0U) +/*! DATA2X - BIST Data 2 High */ +#define FMUTEST_R_DATA_CTRL2_EX_DATA2X(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL2_EX_DATA2X_SHIFT)) & FMUTEST_R_DATA_CTRL2_EX_DATA2X_MASK) +/*! @} */ + +/*! @name R_DATA_CTRL3_EX - BIST Data Control 3 Extension Register */ +/*! @{ */ + +#define FMUTEST_R_DATA_CTRL3_EX_DATA3X_MASK (0x7U) +#define FMUTEST_R_DATA_CTRL3_EX_DATA3X_SHIFT (0U) +/*! DATA3X - BIST Data 3 High */ +#define FMUTEST_R_DATA_CTRL3_EX_DATA3X(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_R_DATA_CTRL3_EX_DATA3X_SHIFT)) & FMUTEST_R_DATA_CTRL3_EX_DATA3X_MASK) +/*! @} */ + +/*! @name SMW_TIMER_OPTION - SMW Timer Option Register */ +/*! @{ */ + +#define FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_MASK (0xFFU) +#define FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_SHIFT (0U) +/*! SMW_CDIVL - Clock Divide Scalar for Long Pulse */ +#define FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_SHIFT)) & FMUTEST_SMW_TIMER_OPTION_SMW_CDIVL_MASK) + +#define FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_MASK (0x1F00U) +#define FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_SHIFT (8U) +/*! SMW_TVFY - Timer Adjust for Verify */ +#define FMUTEST_SMW_TIMER_OPTION_SMW_TVFY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_SHIFT)) & FMUTEST_SMW_TIMER_OPTION_SMW_TVFY_MASK) +/*! @} */ + +/*! @name SMW_SETTING_OPTION0 - SMW Setting Option 0 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SETTING_OPTION0_MV_INIT_MASK (0x1C000U) +#define FMUTEST_SMW_SETTING_OPTION0_MV_INIT_SHIFT (14U) +/*! MV_INIT - Medium Voltage Level Select Initial */ +#define FMUTEST_SMW_SETTING_OPTION0_MV_INIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_MV_INIT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_MV_INIT_MASK) + +#define FMUTEST_SMW_SETTING_OPTION0_MV_END_MASK (0xE0000U) +#define FMUTEST_SMW_SETTING_OPTION0_MV_END_SHIFT (17U) +/*! MV_END - Medium Voltage Level Select Final */ +#define FMUTEST_SMW_SETTING_OPTION0_MV_END(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_MV_END_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_MV_END_MASK) + +#define FMUTEST_SMW_SETTING_OPTION0_MV_MISC_MASK (0xF00000U) +#define FMUTEST_SMW_SETTING_OPTION0_MV_MISC_SHIFT (20U) +/*! MV_MISC - Medium Voltage Control Misc */ +#define FMUTEST_SMW_SETTING_OPTION0_MV_MISC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_MV_MISC_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_MV_MISC_MASK) + +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_MASK (0x3000000U) +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_SHIFT (24U) +/*! IPGM_INIT - Program Current Control Initial */ +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_IPGM_INIT_MASK) + +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_END_MASK (0xC000000U) +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_END_SHIFT (26U) +/*! IPGM_END - Program Current Control Final */ +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_END(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_IPGM_END_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_IPGM_END_MASK) + +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_MASK (0x70000000U) +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_SHIFT (28U) +/*! IPGM_MISC - Program Current Control Misc */ +#define FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_SHIFT)) & FMUTEST_SMW_SETTING_OPTION0_IPGM_MISC_MASK) +/*! @} */ + +/*! @name SMW_SETTING_OPTION2 - SMW Setting Option 2 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_MASK (0x7U) +#define FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_SHIFT (0U) +/*! THVS_CTRL - Thvs control */ +#define FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_THVS_CTRL_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_MASK (0x38U) +#define FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_SHIFT (3U) +/*! TRCV_CTRL - Trcv Control */ +#define FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_TRCV_CTRL_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_MASK (0xC0U) +#define FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_SHIFT (6U) +/*! XTRA_ERS - Number of Post Shots for SME */ +#define FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_XTRA_ERS_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_MASK (0x300U) +#define FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_SHIFT (8U) +/*! XTRA_PGM - Number of Post Shots for SMP */ +#define FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_XTRA_PGM_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_MASK (0x3FC00U) +#define FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_SHIFT (10U) +/*! WHV_CNTR - WHV Counter */ +#define FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_WHV_CNTR_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_POST_TERS_MASK (0x1C0000U) +#define FMUTEST_SMW_SETTING_OPTION2_POST_TERS_SHIFT (18U) +/*! POST_TERS - Post Ters Time + * 0b000..50 usec + * 0b001..100 usec + * 0b010..200 usec + * 0b011..300 usec + * 0b100..500 usec + * 0b101..1 msec + * 0b110..1.5 msec + * 0b111..2 msec + */ +#define FMUTEST_SMW_SETTING_OPTION2_POST_TERS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_POST_TERS_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_POST_TERS_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_MASK (0x600000U) +#define FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_SHIFT (21U) +/*! POST_TPGM - Post Tpgm Time + * 0b00..1 usec + * 0b01..2 usec + * 0b10..4 usec + * 0b11..8 usec + */ +#define FMUTEST_SMW_SETTING_OPTION2_POST_TPGM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_POST_TPGM_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_MASK (0x1800000U) +#define FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_SHIFT (23U) +/*! VFY_OPT - Verify Option + * 0b00..Skip verify for post shot only, verify for all other shots + * 0b01..Skip verify for the 1st and post shots + * 0b10..Skip the 1st, 2nd, and post shots + * 0b11..Skip verify for all shots + */ +#define FMUTEST_SMW_SETTING_OPTION2_VFY_OPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_VFY_OPT_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_MASK (0x6000000U) +#define FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_SHIFT (25U) +/*! TPGM_OPT - Tpgm Option + * 0b00..Fixed Tpgm for all shots, except post shot + * 0b01..Increase Tpgm option by 1 for each loop until Tpgm reaches 4 usec + * 0b10..Increase Tpgm option by 1 for each loop until Tpgm reaches 8 usec + * 0b11..Unused + */ +#define FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_TPGM_OPT_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK (0x8000000U) +#define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT (27U) +/*! MASK0_OPT - MASK0_OPT + * 0b0..Mask programmed bits passing PV until extra shot + * 0b1..Always program bits even if they pass PV + */ +#define FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_MASK0_OPT_MASK) + +#define FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_MASK (0x10000000U) +#define FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_SHIFT (28U) +/*! DIS_PRER - Disable pre-PV Read before First Program Shot + * 0b0..Enable pre-PV read before first program shot + * 0b1..Disable pre-PV read before first program shot + */ +#define FMUTEST_SMW_SETTING_OPTION2_DIS_PRER(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_SHIFT)) & FMUTEST_SMW_SETTING_OPTION2_DIS_PRER_MASK) +/*! @} */ + +/*! @name SMW_SETTING_OPTION3 - SMW Setting Option 3 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_MASK (0xFFU) +#define FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_SHIFT (0U) +/*! HEM_WHV_CNTR - WHV_COUNTER for HEM-erase Cycle */ +#define FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_SHIFT)) & FMUTEST_SMW_SETTING_OPTION3_HEM_WHV_CNTR_MASK) + +#define FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_MASK (0x1FF00U) +#define FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_SHIFT (8U) +/*! HEM_MAX_ERS - HEM Max Erase Shot Count */ +#define FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_SHIFT)) & FMUTEST_SMW_SETTING_OPTION3_HEM_MAX_ERS_MASK) +/*! @} */ + +/*! @name SMW_SMP_WHV_OPTION0 - SMW SMP WHV Option 0 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_SHIFT (0U) +/*! SMP_WHV_OPT0 - Smart Program WHV Option Low */ +#define FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_SHIFT)) & FMUTEST_SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0_MASK) +/*! @} */ + +/*! @name SMW_SME_WHV_OPTION0 - SMW SME WHV Option 0 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_SHIFT (0U) +/*! SME_WHV_OPT0 - Smart Erase WHV Option Low */ +#define FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_SHIFT)) & FMUTEST_SMW_SME_WHV_OPTION0_SME_WHV_OPT0_MASK) +/*! @} */ + +/*! @name SMW_SETTING_OPTION1 - SMW Setting Option 1 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_MASK (0x7U) +#define FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_SHIFT (0U) +/*! TERS_CTRL0 - Ters Control + * 0b000..50 usec + * 0b001..100 usec + * 0b010..200 usec + * 0b011..300 usec + * 0b100..500 usec + * 0b101..1 msec + * 0b110..1.5 msec + * 0b111..2 msec + */ +#define FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TERS_CTRL0_MASK) + +#define FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_MASK (0x18U) +#define FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_SHIFT (3U) +/*! TPGM_CTRL - Tpgm Control + * 0b00..1 usec + * 0b01..2 usec + * 0b10..4 usec + * 0b11..8 usec + */ +#define FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TPGM_CTRL_MASK) + +#define FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_MASK (0xE0U) +#define FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_SHIFT (5U) +/*! TNVS_CTRL - Tnvs Control + * 0b000..5 usec + * 0b001..8 usec + * 0b010..11 usec + * 0b011..14 usec + * 0b100..17 usec + * 0b101..20 usec + * 0b110..23 usec + * 0b111..26 usec + */ +#define FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TNVS_CTRL_MASK) + +#define FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_MASK (0x700U) +#define FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_SHIFT (8U) +/*! TNVH_CTRL - Tnvh Control + * 0b000..2 usec + * 0b001..2.5 usec + * 0b010..3 usec + * 0b011..3.5 usec + * 0b100..4 usec + * 0b101..4.5 usec + * 0b110..5 usec + * 0b111..5.5 usec + */ +#define FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TNVH_CTRL_MASK) + +#define FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_MASK (0x3800U) +#define FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_SHIFT (11U) +/*! TPGS_CTRL - Tpgs Control + * 0b000..1 usec + * 0b001..2 usec + * 0b010..3 usec + * 0b011..4 usec + * 0b100..5 usec + * 0b101..6 usec + * 0b110..7 usec + * 0b111..8 usec + */ +#define FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_TPGS_CTRL_MASK) + +#define FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_MASK (0x7FC000U) +#define FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_SHIFT (14U) +/*! MAX_ERASE - Number of Erase Shots */ +#define FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_MAX_ERASE_MASK) + +#define FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_MASK (0xF800000U) +#define FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_SHIFT (23U) +/*! MAX_PROG - Number of Program Shots */ +#define FMUTEST_SMW_SETTING_OPTION1_MAX_PROG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_SHIFT)) & FMUTEST_SMW_SETTING_OPTION1_MAX_PROG_MASK) +/*! @} */ + +/*! @name SMW_SMP_WHV_OPTION1 - SMW SMP WHV Option 1 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_SHIFT (0U) +/*! SMP_WHV_OPT1 - Smart Program WHV Option High */ +#define FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_SHIFT)) & FMUTEST_SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1_MASK) +/*! @} */ + +/*! @name SMW_SME_WHV_OPTION1 - SMW SME WHV Option 1 Register */ +/*! @{ */ + +#define FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_MASK (0xFFFFFFFFU) +#define FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_SHIFT (0U) +/*! SME_WHV_OPT1 - Smart Erase WHV Option High */ +#define FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_SHIFT)) & FMUTEST_SMW_SME_WHV_OPTION1_SME_WHV_OPT1_MASK) +/*! @} */ + +/*! @name REPAIR0_0 - FMU Repair 0 Block 0 Register */ +/*! @{ */ + +#define FMUTEST_REPAIR0_0_RDIS0_0_MASK (0x1U) +#define FMUTEST_REPAIR0_0_RDIS0_0_SHIFT (0U) +/*! RDIS0_0 - RDIS0_0 + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_REPAIR0_0_RDIS0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_0_RDIS0_0_SHIFT)) & FMUTEST_REPAIR0_0_RDIS0_0_MASK) + +#define FMUTEST_REPAIR0_0_RADR0_0_MASK (0x1FEU) +#define FMUTEST_REPAIR0_0_RADR0_0_SHIFT (1U) +/*! RADR0_0 - RADR0_0 */ +#define FMUTEST_REPAIR0_0_RADR0_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_0_RADR0_0_SHIFT)) & FMUTEST_REPAIR0_0_RADR0_0_MASK) +/*! @} */ + +/*! @name REPAIR0_1 - FMU Repair 1 Block 0 Register */ +/*! @{ */ + +#define FMUTEST_REPAIR0_1_RDIS0_1_MASK (0x1U) +#define FMUTEST_REPAIR0_1_RDIS0_1_SHIFT (0U) +/*! RDIS0_1 - RDIS0_1 + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_REPAIR0_1_RDIS0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_1_RDIS0_1_SHIFT)) & FMUTEST_REPAIR0_1_RDIS0_1_MASK) + +#define FMUTEST_REPAIR0_1_RADR0_1_MASK (0x1FEU) +#define FMUTEST_REPAIR0_1_RADR0_1_SHIFT (1U) +/*! RADR0_1 - RADR0_1 */ +#define FMUTEST_REPAIR0_1_RADR0_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR0_1_RADR0_1_SHIFT)) & FMUTEST_REPAIR0_1_RADR0_1_MASK) +/*! @} */ + +/*! @name REPAIR1_0 - FMU Repair 0 Block 1 Register */ +/*! @{ */ + +#define FMUTEST_REPAIR1_0_RDIS1_0_MASK (0x1U) +#define FMUTEST_REPAIR1_0_RDIS1_0_SHIFT (0U) +/*! RDIS1_0 - RDIS1_0 + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_REPAIR1_0_RDIS1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_0_RDIS1_0_SHIFT)) & FMUTEST_REPAIR1_0_RDIS1_0_MASK) + +#define FMUTEST_REPAIR1_0_RADR1_0_MASK (0x1FEU) +#define FMUTEST_REPAIR1_0_RADR1_0_SHIFT (1U) +/*! RADR1_0 - RADR1_0 */ +#define FMUTEST_REPAIR1_0_RADR1_0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_0_RADR1_0_SHIFT)) & FMUTEST_REPAIR1_0_RADR1_0_MASK) +/*! @} */ + +/*! @name REPAIR1_1 - FMU Repair 1 Block 1 Register */ +/*! @{ */ + +#define FMUTEST_REPAIR1_1_RDIS1_1_MASK (0x1U) +#define FMUTEST_REPAIR1_1_RDIS1_1_SHIFT (0U) +/*! RDIS1_1 - RDIS1_1 + * 0b0..Repair address is valid + * 0b1..Repair address is not valid + */ +#define FMUTEST_REPAIR1_1_RDIS1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_1_RDIS1_1_SHIFT)) & FMUTEST_REPAIR1_1_RDIS1_1_MASK) + +#define FMUTEST_REPAIR1_1_RADR1_1_MASK (0x1FEU) +#define FMUTEST_REPAIR1_1_RADR1_1_SHIFT (1U) +/*! RADR1_1 - RADR1_1 */ +#define FMUTEST_REPAIR1_1_RADR1_1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_REPAIR1_1_RADR1_1_SHIFT)) & FMUTEST_REPAIR1_1_RADR1_1_MASK) +/*! @} */ + +/*! @name SMW_HB_SIGNALS - SMW HB Signals Register */ +/*! @{ */ + +#define FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_MASK (0x7U) +#define FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_SHIFT (0U) +/*! SMW_ARRAY - SMW Region Select + * 0b000..Main array + * 0b001..IFR space only or main (and REDEN space) with IFR space for mass erase + * 0b010..IFR1 space + * 0b100..REDEN space + */ +#define FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_SMW_ARRAY_MASK) + +#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_MASK (0x8U) +#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_SHIFT (3U) +/*! USER_IFREN1 - IFR1 Enable + * 0b0..IFREN1 input to the flash array is driven LOW + * 0b1..IFREN1 input to the flash array is driven HIGH + */ +#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_IFREN1_MASK) + +#define FMUTEST_SMW_HB_SIGNALS_USER_PV_MASK (0x10U) +#define FMUTEST_SMW_HB_SIGNALS_USER_PV_SHIFT (4U) +/*! USER_PV - Program Verify + * 0b0..PV input to the flash array is driven LOW + * 0b1..PV input to the flash array is driven HIGH + */ +#define FMUTEST_SMW_HB_SIGNALS_USER_PV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_PV_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_PV_MASK) + +#define FMUTEST_SMW_HB_SIGNALS_USER_EV_MASK (0x20U) +#define FMUTEST_SMW_HB_SIGNALS_USER_EV_SHIFT (5U) +/*! USER_EV - Erase Verify + * 0b0..EV input to the flash array is driven LOW + * 0b1..EV input to the flash array is driven HIGH + */ +#define FMUTEST_SMW_HB_SIGNALS_USER_EV(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_EV_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_EV_MASK) + +#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN_MASK (0x40U) +#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN_SHIFT (6U) +/*! USER_IFREN - IFR Enable + * 0b0..IFREN input to the flash array is driven LOW + * 0b1..IFREN input to the flash array is driven HIGH + */ +#define FMUTEST_SMW_HB_SIGNALS_USER_IFREN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_IFREN_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_IFREN_MASK) + +#define FMUTEST_SMW_HB_SIGNALS_USER_REDEN_MASK (0x80U) +#define FMUTEST_SMW_HB_SIGNALS_USER_REDEN_SHIFT (7U) +/*! USER_REDEN - Repair Read Enable + * 0b0..REDEN input to the flash array is driven LOW + * 0b1..REDEN input to the flash array is driven HIGH + */ +#define FMUTEST_SMW_HB_SIGNALS_USER_REDEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_REDEN_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_REDEN_MASK) + +#define FMUTEST_SMW_HB_SIGNALS_USER_HEM_MASK (0x100U) +#define FMUTEST_SMW_HB_SIGNALS_USER_HEM_SHIFT (8U) +/*! USER_HEM - High Endurance Enable + * 0b0..HEM input to SMW / BIST PIN_CTRL[24] is driven LOW + * 0b1..HEM input to SMW / BIST PIN_CTRL[24] is driven HIGH + */ +#define FMUTEST_SMW_HB_SIGNALS_USER_HEM(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_SMW_HB_SIGNALS_USER_HEM_SHIFT)) & FMUTEST_SMW_HB_SIGNALS_USER_HEM_MASK) +/*! @} */ + +/*! @name BIST_DUMP_CTRL - BIST Datadump Control Register */ +/*! @{ */ + +#define FMUTEST_BIST_DUMP_CTRL_BIST_DONE_MASK (0x10000U) +#define FMUTEST_BIST_DUMP_CTRL_BIST_DONE_SHIFT (16U) +/*! BIST_DONE - BIST Done + * 0b0..The BIST (or data dump) is running + * 0b1..The BIST (or data dump) has completed + */ +#define FMUTEST_BIST_DUMP_CTRL_BIST_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_BIST_DONE_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_BIST_DONE_MASK) + +#define FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_MASK (0x20000U) +#define FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_SHIFT (17U) +/*! BIST_FAIL - BIST Fail + * 0b0..The last BIST operation completed successfully (or could not fail) + * 0b1..The last BIST operation failed + */ +#define FMUTEST_BIST_DUMP_CTRL_BIST_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_BIST_FAIL_MASK) + +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MASK (0x40000U) +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_SHIFT (18U) +/*! DATADUMP - Data Dump Enable */ +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_MASK) + +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_MASK (0x80000U) +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_SHIFT (19U) +/*! DATADUMP_TRIG - Data Dump Trigger */ +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_TRIG_MASK) + +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_MASK (0x300000U) +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_SHIFT (20U) +/*! DATADUMP_PATT - Data Dump Pattern Select + * 0b00..All ones + * 0b01..All zeroes + * 0b10..Checkerboard + * 0b11..Inverse checkerboard + */ +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_PATT_MASK) + +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_MASK (0x400000U) +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_SHIFT (22U) +/*! DATADUMP_MRGEN - Data Dump Margin Enable + * 0b0..Normal read pulse shape + * 0b1..Margin read pulse shape + */ +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGEN_MASK) + +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_MASK (0x800000U) +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_SHIFT (23U) +/*! DATADUMP_MRGTYPE - Data Dump Margin Type + * 0b0..DIN method used + * 0b1..TM method used + */ +#define FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_SHIFT)) & FMUTEST_BIST_DUMP_CTRL_DATADUMP_MRGTYPE_MASK) +/*! @} */ + +/*! @name ATX_PIN_CTRL - ATX Pin Control Register */ +/*! @{ */ + +#define FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_MASK (0xFFU) +#define FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_SHIFT (0U) +/*! TM_TO_ATX - TM to ATX + * 0b00000001..TM[0] to ATX0 + * 0b00000010..TM[1] to ATX0 + * 0b00000100..TM[2] to ATX0 + * 0b00001000..TM[3] to ATX0 + * 0b00010000..TM[0] to ATX1 + * 0b00100000..TM[1] to ATX1 + * 0b01000000..TM[2] to ATX1 + * 0b10000000..TM[3] to ATX1 + */ +#define FMUTEST_ATX_PIN_CTRL_TM_TO_ATX(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_SHIFT)) & FMUTEST_ATX_PIN_CTRL_TM_TO_ATX_MASK) +/*! @} */ + +/*! @name FAILCNT - Fail Count Register */ +/*! @{ */ + +#define FMUTEST_FAILCNT_FAILCNT_MASK (0xFFFFFFFFU) +#define FMUTEST_FAILCNT_FAILCNT_SHIFT (0U) +/*! FAILCNT - Fail Count */ +#define FMUTEST_FAILCNT_FAILCNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_FAILCNT_FAILCNT_SHIFT)) & FMUTEST_FAILCNT_FAILCNT_MASK) +/*! @} */ + +/*! @name PGM_PULSE_CNT0 - Block 0 Program Pulse Count Register */ +/*! @{ */ + +#define FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_MASK (0xFFFFFFFFU) +#define FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_SHIFT (0U) +/*! PGM_CNT0 - Program Pulse Count */ +#define FMUTEST_PGM_PULSE_CNT0_PGM_CNT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_SHIFT)) & FMUTEST_PGM_PULSE_CNT0_PGM_CNT0_MASK) +/*! @} */ + +/*! @name PGM_PULSE_CNT1 - Block 1 Program Pulse Count Register */ +/*! @{ */ + +#define FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_MASK (0xFFFFFFFFU) +#define FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_SHIFT (0U) +/*! PGM_CNT1 - Program Pulse Count */ +#define FMUTEST_PGM_PULSE_CNT1_PGM_CNT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_SHIFT)) & FMUTEST_PGM_PULSE_CNT1_PGM_CNT1_MASK) +/*! @} */ + +/*! @name ERS_PULSE_CNT - Erase Pulse Count Register */ +/*! @{ */ + +#define FMUTEST_ERS_PULSE_CNT_ERS_CNT0_MASK (0xFFFFU) +#define FMUTEST_ERS_PULSE_CNT_ERS_CNT0_SHIFT (0U) +/*! ERS_CNT0 - Block 0 Erase Pulse Count */ +#define FMUTEST_ERS_PULSE_CNT_ERS_CNT0(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_ERS_PULSE_CNT_ERS_CNT0_SHIFT)) & FMUTEST_ERS_PULSE_CNT_ERS_CNT0_MASK) + +#define FMUTEST_ERS_PULSE_CNT_ERS_CNT1_MASK (0xFFFF0000U) +#define FMUTEST_ERS_PULSE_CNT_ERS_CNT1_SHIFT (16U) +/*! ERS_CNT1 - Block 1 Erase Pulse Count */ +#define FMUTEST_ERS_PULSE_CNT_ERS_CNT1(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_ERS_PULSE_CNT_ERS_CNT1_SHIFT)) & FMUTEST_ERS_PULSE_CNT_ERS_CNT1_MASK) +/*! @} */ + +/*! @name MAX_PULSE_CNT - Maximum Pulse Count Register */ +/*! @{ */ + +#define FMUTEST_MAX_PULSE_CNT_LAST_PCNT_MASK (0x1FFU) +#define FMUTEST_MAX_PULSE_CNT_LAST_PCNT_SHIFT (0U) +/*! LAST_PCNT - Last SMW Operation's Pulse Count */ +#define FMUTEST_MAX_PULSE_CNT_LAST_PCNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MAX_PULSE_CNT_LAST_PCNT_SHIFT)) & FMUTEST_MAX_PULSE_CNT_LAST_PCNT_MASK) + +#define FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_MASK (0x1FF0000U) +#define FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_SHIFT (16U) +/*! MAX_ERS_CNT - Maximum Erase Pulse Count */ +#define FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_SHIFT)) & FMUTEST_MAX_PULSE_CNT_MAX_ERS_CNT_MASK) + +#define FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_MASK (0xF8000000U) +#define FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_SHIFT (27U) +/*! MAX_PGM_CNT - Maximum Program Pulse Count */ +#define FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_SHIFT)) & FMUTEST_MAX_PULSE_CNT_MAX_PGM_CNT_MASK) +/*! @} */ + +/*! @name PORT_CTRL - Port Control Register */ +/*! @{ */ + +#define FMUTEST_PORT_CTRL_BDONE_SEL_MASK (0x3U) +#define FMUTEST_PORT_CTRL_BDONE_SEL_SHIFT (0U) +/*! BDONE_SEL - BIST Done Select + * 0b00..Select internal bist_done signal from current module instantiation + * 0b01..Select ipt_bist_fail signal from current module instantiation + * 0b10..Select ipt_bist_done signal from other module instantiation + * 0b11..Select AND of internal bist_done signal from current module instantiation with ipt_bist_done signal from other module instantiation + */ +#define FMUTEST_PORT_CTRL_BDONE_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PORT_CTRL_BDONE_SEL_SHIFT)) & FMUTEST_PORT_CTRL_BDONE_SEL_MASK) + +#define FMUTEST_PORT_CTRL_BSDO_SEL_MASK (0xCU) +#define FMUTEST_PORT_CTRL_BSDO_SEL_SHIFT (2U) +/*! BSDO_SEL - BIST Serial Data Output Select + * 0b00..Select internal bist_sdo signal from current module instantiation + * 0b01..Select ipt_bist_done signal from current module instantiation + * 0b10..Select ipt_bist_sdo signal from other module instantiation + * 0b11..Select ipt_bist_done signal from other module instantiation + */ +#define FMUTEST_PORT_CTRL_BSDO_SEL(x) (((uint32_t)(((uint32_t)(x)) << FMUTEST_PORT_CTRL_BSDO_SEL_SHIFT)) & FMUTEST_PORT_CTRL_BSDO_SEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FMUTEST_Register_Masks */ + + +/* FMUTEST - Peripheral instance base addresses */ +/** Peripheral FMU0TEST base address */ +#define FMU0TEST_BASE (0x40096000u) +/** Peripheral FMU0TEST base pointer */ +#define FMU0TEST ((FMUTEST_Type *)FMU0TEST_BASE) +/** Array initializer of FMUTEST peripheral base addresses */ +#define FMUTEST_BASE_ADDRS { FMU0TEST_BASE } +/** Array initializer of FMUTEST peripheral base pointers */ +#define FMUTEST_BASE_PTRS { FMU0TEST } + +/*! + * @} + */ /* end of group FMUTEST_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FREQME Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FREQME_Peripheral_Access_Layer FREQME Peripheral Access Layer + * @{ + */ + +/** FREQME - Register Layout Typedef */ +typedef struct { + union { /* offset: 0x0 */ + __I uint32_t CTRL_R; /**< Control (in Read mode), offset: 0x0 */ + __O uint32_t CTRL_W; /**< Control (in Write mode), offset: 0x0 */ + }; + __IO uint32_t CTRLSTAT; /**< Control Status, offset: 0x4 */ + __IO uint32_t MIN; /**< Minimum, offset: 0x8 */ + __IO uint32_t MAX; /**< Maximum, offset: 0xC */ +} FREQME_Type; + +/* ---------------------------------------------------------------------------- + -- FREQME Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FREQME_Register_Masks FREQME Register Masks + * @{ + */ + +/*! @name CTRL_R - Control (in Read mode) */ +/*! @{ */ + +#define FREQME_CTRL_R_RESULT_MASK (0x7FFFFFFFU) +#define FREQME_CTRL_R_RESULT_SHIFT (0U) +#define FREQME_CTRL_R_RESULT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_R_RESULT_SHIFT)) & FREQME_CTRL_R_RESULT_MASK) + +#define FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK (0x80000000U) +#define FREQME_CTRL_R_MEASURE_IN_PROGRESS_SHIFT (31U) +/*! MEASURE_IN_PROGRESS - Measurement In Progress + * 0b0..Complete + * 0b1..In progress + */ +#define FREQME_CTRL_R_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_R_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK) +/*! @} */ + +/*! @name CTRL_W - Control (in Write mode) */ +/*! @{ */ + +#define FREQME_CTRL_W_REF_SCALE_MASK (0x1FU) +#define FREQME_CTRL_W_REF_SCALE_SHIFT (0U) +/*! REF_SCALE - Reference Clock Scaling Factor */ +#define FREQME_CTRL_W_REF_SCALE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_REF_SCALE_SHIFT)) & FREQME_CTRL_W_REF_SCALE_MASK) + +#define FREQME_CTRL_W_PULSE_MODE_MASK (0x100U) +#define FREQME_CTRL_W_PULSE_MODE_SHIFT (8U) +/*! PULSE_MODE - Pulse Width Measurement Mode Select + * 0b0..Frequency Measurement mode + * 0b1..Pulse Width Measurement mode + */ +#define FREQME_CTRL_W_PULSE_MODE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_PULSE_MODE_SHIFT)) & FREQME_CTRL_W_PULSE_MODE_MASK) + +#define FREQME_CTRL_W_PULSE_POL_MASK (0x200U) +#define FREQME_CTRL_W_PULSE_POL_SHIFT (9U) +/*! PULSE_POL - Pulse Polarity + * 0b0..High period + * 0b1..Low period + */ +#define FREQME_CTRL_W_PULSE_POL(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_PULSE_POL_SHIFT)) & FREQME_CTRL_W_PULSE_POL_MASK) + +#define FREQME_CTRL_W_LT_MIN_INT_EN_MASK (0x1000U) +#define FREQME_CTRL_W_LT_MIN_INT_EN_SHIFT (12U) +/*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_CTRL_W_LT_MIN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_LT_MIN_INT_EN_SHIFT)) & FREQME_CTRL_W_LT_MIN_INT_EN_MASK) + +#define FREQME_CTRL_W_GT_MAX_INT_EN_MASK (0x2000U) +#define FREQME_CTRL_W_GT_MAX_INT_EN_SHIFT (13U) +/*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_CTRL_W_GT_MAX_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_GT_MAX_INT_EN_SHIFT)) & FREQME_CTRL_W_GT_MAX_INT_EN_MASK) + +#define FREQME_CTRL_W_RESULT_READY_INT_EN_MASK (0x4000U) +#define FREQME_CTRL_W_RESULT_READY_INT_EN_SHIFT (14U) +/*! RESULT_READY_INT_EN - Result Ready Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_CTRL_W_RESULT_READY_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_RESULT_READY_INT_EN_SHIFT)) & FREQME_CTRL_W_RESULT_READY_INT_EN_MASK) + +#define FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK (0x40000000U) +#define FREQME_CTRL_W_CONTINUOUS_MODE_EN_SHIFT (30U) +/*! CONTINUOUS_MODE_EN - Continuous Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define FREQME_CTRL_W_CONTINUOUS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK) + +#define FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK (0x80000000U) +#define FREQME_CTRL_W_MEASURE_IN_PROGRESS_SHIFT (31U) +/*! MEASURE_IN_PROGRESS - Measurement In Progress + * 0b0..Terminates measurement + * 0b1..Initiates measurement + */ +#define FREQME_CTRL_W_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRL_W_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK) +/*! @} */ + +/*! @name CTRLSTAT - Control Status */ +/*! @{ */ + +#define FREQME_CTRLSTAT_REF_SCALE_MASK (0x1FU) +#define FREQME_CTRLSTAT_REF_SCALE_SHIFT (0U) +/*! REF_SCALE - Reference Scale */ +#define FREQME_CTRLSTAT_REF_SCALE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_REF_SCALE_SHIFT)) & FREQME_CTRLSTAT_REF_SCALE_MASK) + +#define FREQME_CTRLSTAT_PULSE_MODE_MASK (0x100U) +#define FREQME_CTRLSTAT_PULSE_MODE_SHIFT (8U) +/*! PULSE_MODE - Pulse Mode + * 0b0..Frequency Measurement mode + * 0b1..Pulse Width Measurement mode + */ +#define FREQME_CTRLSTAT_PULSE_MODE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_PULSE_MODE_SHIFT)) & FREQME_CTRLSTAT_PULSE_MODE_MASK) + +#define FREQME_CTRLSTAT_PULSE_POL_MASK (0x200U) +#define FREQME_CTRLSTAT_PULSE_POL_SHIFT (9U) +/*! PULSE_POL - Pulse Polarity + * 0b0..High period + * 0b1..Low period + */ +#define FREQME_CTRLSTAT_PULSE_POL(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_PULSE_POL_SHIFT)) & FREQME_CTRLSTAT_PULSE_POL_MASK) + +#define FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK (0x1000U) +#define FREQME_CTRLSTAT_LT_MIN_INT_EN_SHIFT (12U) +/*! LT_MIN_INT_EN - Less Than Minimum Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define FREQME_CTRLSTAT_LT_MIN_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_LT_MIN_INT_EN_SHIFT)) & FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK) + +#define FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK (0x2000U) +#define FREQME_CTRLSTAT_GT_MAX_INT_EN_SHIFT (13U) +/*! GT_MAX_INT_EN - Greater Than Maximum Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define FREQME_CTRLSTAT_GT_MAX_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_GT_MAX_INT_EN_SHIFT)) & FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK) + +#define FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK (0x4000U) +#define FREQME_CTRLSTAT_RESULT_READY_INT_EN_SHIFT (14U) +/*! RESULT_READY_INT_EN - Result Ready Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define FREQME_CTRLSTAT_RESULT_READY_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_RESULT_READY_INT_EN_SHIFT)) & FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK) + +#define FREQME_CTRLSTAT_LT_MIN_STAT_MASK (0x1000000U) +#define FREQME_CTRLSTAT_LT_MIN_STAT_SHIFT (24U) +/*! LT_MIN_STAT - Less Than Minimum Results Status + * 0b0..Greater than MIN[MIN_VALUE] + * 0b1..Less than MIN[MIN_VALUE] + */ +#define FREQME_CTRLSTAT_LT_MIN_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_LT_MIN_STAT_SHIFT)) & FREQME_CTRLSTAT_LT_MIN_STAT_MASK) + +#define FREQME_CTRLSTAT_GT_MAX_STAT_MASK (0x2000000U) +#define FREQME_CTRLSTAT_GT_MAX_STAT_SHIFT (25U) +/*! GT_MAX_STAT - Greater Than Maximum Result Status + * 0b0..Less than MAX[MAX_VALUE] + * 0b1..Greater than MAX[MAX_VALUE] + */ +#define FREQME_CTRLSTAT_GT_MAX_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_GT_MAX_STAT_SHIFT)) & FREQME_CTRLSTAT_GT_MAX_STAT_MASK) + +#define FREQME_CTRLSTAT_RESULT_READY_STAT_MASK (0x4000000U) +#define FREQME_CTRLSTAT_RESULT_READY_STAT_SHIFT (26U) +/*! RESULT_READY_STAT - Result Ready Status + * 0b0..Not complete + * 0b1..Complete + */ +#define FREQME_CTRLSTAT_RESULT_READY_STAT(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_RESULT_READY_STAT_SHIFT)) & FREQME_CTRLSTAT_RESULT_READY_STAT_MASK) + +#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK (0x40000000U) +#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_SHIFT (30U) +/*! CONTINUOUS_MODE_EN - Continuous Mode Enable Status + * 0b0..Disabled + * 0b1..Enabled + */ +#define FREQME_CTRLSTAT_CONTINUOUS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_SHIFT)) & FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK) + +#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK (0x80000000U) +#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_SHIFT (31U) +/*! MEASURE_IN_PROGRESS - Measurement in Progress Status + * 0b0..Not in progress + * 0b1..In progress + */ +#define FREQME_CTRLSTAT_MEASURE_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_SHIFT)) & FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK) +/*! @} */ + +/*! @name MIN - Minimum */ +/*! @{ */ + +#define FREQME_MIN_MIN_VALUE_MASK (0x7FFFFFFFU) +#define FREQME_MIN_MIN_VALUE_SHIFT (0U) +/*! MIN_VALUE - Minimum Value */ +#define FREQME_MIN_MIN_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_MIN_MIN_VALUE_SHIFT)) & FREQME_MIN_MIN_VALUE_MASK) +/*! @} */ + +/*! @name MAX - Maximum */ +/*! @{ */ + +#define FREQME_MAX_MAX_VALUE_MASK (0x7FFFFFFFU) +#define FREQME_MAX_MAX_VALUE_SHIFT (0U) +/*! MAX_VALUE - Maximum Value */ +#define FREQME_MAX_MAX_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FREQME_MAX_MAX_VALUE_SHIFT)) & FREQME_MAX_MAX_VALUE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FREQME_Register_Masks */ + + +/* FREQME - Peripheral instance base addresses */ +/** Peripheral FREQME0 base address */ +#define FREQME0_BASE (0x40009000u) +/** Peripheral FREQME0 base pointer */ +#define FREQME0 ((FREQME_Type *)FREQME0_BASE) +/** Array initializer of FREQME peripheral base addresses */ +#define FREQME_BASE_ADDRS { FREQME0_BASE } +/** Array initializer of FREQME peripheral base pointers */ +#define FREQME_BASE_PTRS { FREQME0 } + +/*! + * @} + */ /* end of group FREQME_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GLIKEY Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GLIKEY_Peripheral_Access_Layer GLIKEY Peripheral Access Layer + * @{ + */ + +/** GLIKEY - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL_0; /**< Control Register 0 SFR, offset: 0x0 */ + __IO uint32_t CTRL_1; /**< Control Regsiter 1 SFR, offset: 0x4 */ + __IO uint32_t INTR_CTRL; /**< Interrupt Control, offset: 0x8 */ + __I uint32_t STATUS; /**< Status, offset: 0xC */ + uint8_t RESERVED_0[236]; + __I uint32_t VERSION; /**< IP Version, offset: 0xFC */ +} GLIKEY_Type; + +/* ---------------------------------------------------------------------------- + -- GLIKEY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GLIKEY_Register_Masks GLIKEY Register Masks + * @{ + */ + +/*! @name CTRL_0 - Control Register 0 SFR */ +/*! @{ */ + +#define GLIKEY_CTRL_0_WRITE_INDEX_MASK (0xFFU) +#define GLIKEY_CTRL_0_WRITE_INDEX_SHIFT (0U) +/*! WRITE_INDEX - Write Index */ +#define GLIKEY_CTRL_0_WRITE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_WRITE_INDEX_SHIFT)) & GLIKEY_CTRL_0_WRITE_INDEX_MASK) + +#define GLIKEY_CTRL_0_RESERVED15_MASK (0xFF00U) +#define GLIKEY_CTRL_0_RESERVED15_SHIFT (8U) +/*! RESERVED15 - Reserved for Future Use */ +#define GLIKEY_CTRL_0_RESERVED15(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_RESERVED15_SHIFT)) & GLIKEY_CTRL_0_RESERVED15_MASK) + +#define GLIKEY_CTRL_0_WR_EN_0_MASK (0x30000U) +#define GLIKEY_CTRL_0_WR_EN_0_SHIFT (16U) +/*! WR_EN_0 - Write Enable 0 */ +#define GLIKEY_CTRL_0_WR_EN_0(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_WR_EN_0_SHIFT)) & GLIKEY_CTRL_0_WR_EN_0_MASK) + +#define GLIKEY_CTRL_0_SFT_RST_MASK (0x40000U) +#define GLIKEY_CTRL_0_SFT_RST_SHIFT (18U) +/*! SFT_RST - Soft reset for the core reset (SFR configuration will be preseved).This register reads as 0 + * 0b0..No effect + * 0b1..Triggers the soft reset + */ +#define GLIKEY_CTRL_0_SFT_RST(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_SFT_RST_SHIFT)) & GLIKEY_CTRL_0_SFT_RST_MASK) + +#define GLIKEY_CTRL_0_RESERVED31_MASK (0xFFF80000U) +#define GLIKEY_CTRL_0_RESERVED31_SHIFT (19U) +/*! RESERVED31 - Reserved for Future Use */ +#define GLIKEY_CTRL_0_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_0_RESERVED31_SHIFT)) & GLIKEY_CTRL_0_RESERVED31_MASK) +/*! @} */ + +/*! @name CTRL_1 - Control Regsiter 1 SFR */ +/*! @{ */ + +#define GLIKEY_CTRL_1_READ_INDEX_MASK (0xFFU) +#define GLIKEY_CTRL_1_READ_INDEX_SHIFT (0U) +/*! READ_INDEX - Index status, Writing an index value to this register will request the block to return the lock status of this index. */ +#define GLIKEY_CTRL_1_READ_INDEX(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_READ_INDEX_SHIFT)) & GLIKEY_CTRL_1_READ_INDEX_MASK) + +#define GLIKEY_CTRL_1_RESERVED15_MASK (0xFF00U) +#define GLIKEY_CTRL_1_RESERVED15_SHIFT (8U) +/*! RESERVED15 - Reserved for Future Use */ +#define GLIKEY_CTRL_1_RESERVED15(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_RESERVED15_SHIFT)) & GLIKEY_CTRL_1_RESERVED15_MASK) + +#define GLIKEY_CTRL_1_WR_EN_1_MASK (0x30000U) +#define GLIKEY_CTRL_1_WR_EN_1_SHIFT (16U) +/*! WR_EN_1 - Write Enable One */ +#define GLIKEY_CTRL_1_WR_EN_1(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_WR_EN_1_SHIFT)) & GLIKEY_CTRL_1_WR_EN_1_MASK) + +#define GLIKEY_CTRL_1_SFR_LOCK_MASK (0x3C0000U) +#define GLIKEY_CTRL_1_SFR_LOCK_SHIFT (18U) +/*! SFR_LOCK - LOCK register for GLIKEY */ +#define GLIKEY_CTRL_1_SFR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_SFR_LOCK_SHIFT)) & GLIKEY_CTRL_1_SFR_LOCK_MASK) + +#define GLIKEY_CTRL_1_RESERVED31_MASK (0xFFC00000U) +#define GLIKEY_CTRL_1_RESERVED31_SHIFT (22U) +/*! RESERVED31 - Reserved for Future Use */ +#define GLIKEY_CTRL_1_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_CTRL_1_RESERVED31_SHIFT)) & GLIKEY_CTRL_1_RESERVED31_MASK) +/*! @} */ + +/*! @name INTR_CTRL - Interrupt Control */ +/*! @{ */ + +#define GLIKEY_INTR_CTRL_INT_EN_MASK (0x1U) +#define GLIKEY_INTR_CTRL_INT_EN_SHIFT (0U) +/*! INT_EN - Interrupt Enable. Writing a 1, Interrupt asserts on Interrupt output port */ +#define GLIKEY_INTR_CTRL_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_INTR_CTRL_INT_EN_SHIFT)) & GLIKEY_INTR_CTRL_INT_EN_MASK) + +#define GLIKEY_INTR_CTRL_INT_CLR_MASK (0x2U) +#define GLIKEY_INTR_CTRL_INT_CLR_SHIFT (1U) +/*! INT_CLR - Interrupt Clear. Writing a 1 to this register creates a single interrupt clear pulse. This register reads as 0 */ +#define GLIKEY_INTR_CTRL_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_INTR_CTRL_INT_CLR_SHIFT)) & GLIKEY_INTR_CTRL_INT_CLR_MASK) + +#define GLIKEY_INTR_CTRL_INT_SET_MASK (0x4U) +#define GLIKEY_INTR_CTRL_INT_SET_SHIFT (2U) +/*! INT_SET - Interrupt Set. Writing a 1 to this register asserts the interrupt. This register reads as 0 + * 0b0..No effect + * 0b1..Triggers interrupt + */ +#define GLIKEY_INTR_CTRL_INT_SET(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_INTR_CTRL_INT_SET_SHIFT)) & GLIKEY_INTR_CTRL_INT_SET_MASK) + +#define GLIKEY_INTR_CTRL_RESERVED31_MASK (0xFFFFFFF8U) +#define GLIKEY_INTR_CTRL_RESERVED31_SHIFT (3U) +/*! RESERVED31 - Reserved for Future Use */ +#define GLIKEY_INTR_CTRL_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_INTR_CTRL_RESERVED31_SHIFT)) & GLIKEY_INTR_CTRL_RESERVED31_MASK) +/*! @} */ + +/*! @name STATUS - Status */ +/*! @{ */ + +#define GLIKEY_STATUS_INT_STATUS_MASK (0x1U) +#define GLIKEY_STATUS_INT_STATUS_SHIFT (0U) +/*! INT_STATUS - Interrupt Status. + * 0b0..No effect + * 0b1..Triggers interrupt + */ +#define GLIKEY_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_INT_STATUS_SHIFT)) & GLIKEY_STATUS_INT_STATUS_MASK) + +#define GLIKEY_STATUS_LOCK_STATUS_MASK (0x2U) +#define GLIKEY_STATUS_LOCK_STATUS_SHIFT (1U) +/*! LOCK_STATUS - Provides the current lock status of indexes. + * 0b0..Current read index is not locked + * 0b1..Current read index is locked + */ +#define GLIKEY_STATUS_LOCK_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_LOCK_STATUS_SHIFT)) & GLIKEY_STATUS_LOCK_STATUS_MASK) + +#define GLIKEY_STATUS_ERROR_STATUS_MASK (0x1CU) +#define GLIKEY_STATUS_ERROR_STATUS_SHIFT (2U) +/*! ERROR_STATUS - Status of the Error + * 0b000..No error + * 0b001..FSM error has occurred + * 0b010..Write index out of the bound (OOB) error + * 0b011..Write index OOB and FSM error + * 0b100..Read index OOB error + * 0b110..Write index and read index OOB error + * 0b111..Read index OOB, write index OOB, and FSM error + */ +#define GLIKEY_STATUS_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_ERROR_STATUS_SHIFT)) & GLIKEY_STATUS_ERROR_STATUS_MASK) + +#define GLIKEY_STATUS_RESERVED18_MASK (0x7FFE0U) +#define GLIKEY_STATUS_RESERVED18_SHIFT (5U) +/*! RESERVED18 - Reserved for Future Use */ +#define GLIKEY_STATUS_RESERVED18(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_RESERVED18_SHIFT)) & GLIKEY_STATUS_RESERVED18_MASK) + +#define GLIKEY_STATUS_FSM_STATE_MASK (0xFFF80000U) +#define GLIKEY_STATUS_FSM_STATE_SHIFT (19U) +/*! FSM_STATE - Status of FSM */ +#define GLIKEY_STATUS_FSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_STATUS_FSM_STATE_SHIFT)) & GLIKEY_STATUS_FSM_STATE_MASK) +/*! @} */ + +/*! @name VERSION - IP Version */ +/*! @{ */ + +#define GLIKEY_VERSION_RESERVED3_MASK (0xFU) +#define GLIKEY_VERSION_RESERVED3_SHIFT (0U) +/*! Reserved3 - Reserved */ +#define GLIKEY_VERSION_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED3_SHIFT)) & GLIKEY_VERSION_RESERVED3_MASK) + +#define GLIKEY_VERSION_RESERVED7_MASK (0xF0U) +#define GLIKEY_VERSION_RESERVED7_SHIFT (4U) +/*! Reserved7 - Reserved */ +#define GLIKEY_VERSION_RESERVED7(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED7_SHIFT)) & GLIKEY_VERSION_RESERVED7_MASK) + +#define GLIKEY_VERSION_RESERVED11_MASK (0xF00U) +#define GLIKEY_VERSION_RESERVED11_SHIFT (8U) +/*! Reserved11 - Reserved */ +#define GLIKEY_VERSION_RESERVED11(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED11_SHIFT)) & GLIKEY_VERSION_RESERVED11_MASK) + +#define GLIKEY_VERSION_RESERVED15_MASK (0xF000U) +#define GLIKEY_VERSION_RESERVED15_SHIFT (12U) +/*! Reserved15 - Reserved */ +#define GLIKEY_VERSION_RESERVED15(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED15_SHIFT)) & GLIKEY_VERSION_RESERVED15_MASK) + +#define GLIKEY_VERSION_RESERVED16_MASK (0x30000U) +#define GLIKEY_VERSION_RESERVED16_SHIFT (16U) +/*! Reserved16 - Reserved */ +#define GLIKEY_VERSION_RESERVED16(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED16_SHIFT)) & GLIKEY_VERSION_RESERVED16_MASK) + +#define GLIKEY_VERSION_FSM_CONFIG_MASK (0x40000U) +#define GLIKEY_VERSION_FSM_CONFIG_SHIFT (18U) +/*! FSM_CONFIG - 0:4 step, 1:8 step */ +#define GLIKEY_VERSION_FSM_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_FSM_CONFIG_SHIFT)) & GLIKEY_VERSION_FSM_CONFIG_MASK) + +#define GLIKEY_VERSION_INDEX_CONFIG_MASK (0x7F80000U) +#define GLIKEY_VERSION_INDEX_CONFIG_SHIFT (19U) +/*! INDEX_CONFIG - Configured number of addressable indexes */ +#define GLIKEY_VERSION_INDEX_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_INDEX_CONFIG_SHIFT)) & GLIKEY_VERSION_INDEX_CONFIG_MASK) + +#define GLIKEY_VERSION_RESERVED31_MASK (0xF8000000U) +#define GLIKEY_VERSION_RESERVED31_SHIFT (27U) +/*! Reserved31 - Reserved for Future Use */ +#define GLIKEY_VERSION_RESERVED31(x) (((uint32_t)(((uint32_t)(x)) << GLIKEY_VERSION_RESERVED31_SHIFT)) & GLIKEY_VERSION_RESERVED31_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group GLIKEY_Register_Masks */ + + +/* GLIKEY - Peripheral instance base addresses */ +/** Peripheral GLIKEY0 base address */ +#define GLIKEY0_BASE (0x40091D00u) +/** Peripheral GLIKEY0 base pointer */ +#define GLIKEY0 ((GLIKEY_Type *)GLIKEY0_BASE) +/** Array initializer of GLIKEY peripheral base addresses */ +#define GLIKEY_BASE_ADDRS { GLIKEY0_BASE } +/** Array initializer of GLIKEY peripheral base pointers */ +#define GLIKEY_BASE_PTRS { GLIKEY0 } + +/*! + * @} + */ /* end of group GLIKEY_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + uint8_t RESERVED_0[56]; + __IO uint32_t PDOR; /**< Port Data Output, offset: 0x40 */ + __O uint32_t PSOR; /**< Port Set Output, offset: 0x44 */ + __O uint32_t PCOR; /**< Port Clear Output, offset: 0x48 */ + __O uint32_t PTOR; /**< Port Toggle Output, offset: 0x4C */ + __I uint32_t PDIR; /**< Port Data Input, offset: 0x50 */ + __IO uint32_t PDDR; /**< Port Data Direction, offset: 0x54 */ + __IO uint32_t PIDR; /**< Port Input Disable, offset: 0x58 */ + uint8_t RESERVED_1[4]; + __IO uint8_t PDR[32]; /**< Pin Data, array offset: 0x60, array step: 0x1 */ + __IO uint32_t ICR[32]; /**< Interrupt Control 0..Interrupt Control 31, array offset: 0x80, array step: 0x4 */ + __O uint32_t GICLR; /**< Global Interrupt Control Low, offset: 0x100 */ + __O uint32_t GICHR; /**< Global Interrupt Control High, offset: 0x104 */ + uint8_t RESERVED_2[24]; + __IO uint32_t ISFR[1]; /**< Interrupt Status Flag, array offset: 0x120, array step: 0x4 */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define GPIO_VERID_FEATURE_MASK (0xFFFFU) +#define GPIO_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Basic implementation + * 0b0000000000000001..Protection registers implemented + */ +#define GPIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_FEATURE_SHIFT)) & GPIO_VERID_FEATURE_MASK) + +#define GPIO_VERID_MINOR_MASK (0xFF0000U) +#define GPIO_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define GPIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_MINOR_SHIFT)) & GPIO_VERID_MINOR_MASK) + +#define GPIO_VERID_MAJOR_MASK (0xFF000000U) +#define GPIO_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define GPIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_VERID_MAJOR_SHIFT)) & GPIO_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define GPIO_PARAM_IRQNUM_MASK (0xFU) +#define GPIO_PARAM_IRQNUM_SHIFT (0U) +/*! IRQNUM - Interrupt Number */ +#define GPIO_PARAM_IRQNUM(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PARAM_IRQNUM_SHIFT)) & GPIO_PARAM_IRQNUM_MASK) +/*! @} */ + +/*! @name PDOR - Port Data Output */ +/*! @{ */ + +#define GPIO_PDOR_PDO0_MASK (0x1U) +#define GPIO_PDOR_PDO0_SHIFT (0U) +/*! PDO0 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO0_SHIFT)) & GPIO_PDOR_PDO0_MASK) + +#define GPIO_PDOR_PDO1_MASK (0x2U) +#define GPIO_PDOR_PDO1_SHIFT (1U) +/*! PDO1 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO1_SHIFT)) & GPIO_PDOR_PDO1_MASK) + +#define GPIO_PDOR_PDO2_MASK (0x4U) +#define GPIO_PDOR_PDO2_SHIFT (2U) +/*! PDO2 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO2_SHIFT)) & GPIO_PDOR_PDO2_MASK) + +#define GPIO_PDOR_PDO3_MASK (0x8U) +#define GPIO_PDOR_PDO3_SHIFT (3U) +/*! PDO3 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO3_SHIFT)) & GPIO_PDOR_PDO3_MASK) + +#define GPIO_PDOR_PDO4_MASK (0x10U) +#define GPIO_PDOR_PDO4_SHIFT (4U) +/*! PDO4 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO4_SHIFT)) & GPIO_PDOR_PDO4_MASK) + +#define GPIO_PDOR_PDO5_MASK (0x20U) +#define GPIO_PDOR_PDO5_SHIFT (5U) +/*! PDO5 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO5_SHIFT)) & GPIO_PDOR_PDO5_MASK) + +#define GPIO_PDOR_PDO6_MASK (0x40U) +#define GPIO_PDOR_PDO6_SHIFT (6U) +/*! PDO6 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO6_SHIFT)) & GPIO_PDOR_PDO6_MASK) + +#define GPIO_PDOR_PDO7_MASK (0x80U) +#define GPIO_PDOR_PDO7_SHIFT (7U) +/*! PDO7 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO7_SHIFT)) & GPIO_PDOR_PDO7_MASK) + +#define GPIO_PDOR_PDO8_MASK (0x100U) +#define GPIO_PDOR_PDO8_SHIFT (8U) +/*! PDO8 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO8_SHIFT)) & GPIO_PDOR_PDO8_MASK) + +#define GPIO_PDOR_PDO9_MASK (0x200U) +#define GPIO_PDOR_PDO9_SHIFT (9U) +/*! PDO9 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO9_SHIFT)) & GPIO_PDOR_PDO9_MASK) + +#define GPIO_PDOR_PDO10_MASK (0x400U) +#define GPIO_PDOR_PDO10_SHIFT (10U) +/*! PDO10 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO10_SHIFT)) & GPIO_PDOR_PDO10_MASK) + +#define GPIO_PDOR_PDO11_MASK (0x800U) +#define GPIO_PDOR_PDO11_SHIFT (11U) +/*! PDO11 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO11_SHIFT)) & GPIO_PDOR_PDO11_MASK) + +#define GPIO_PDOR_PDO12_MASK (0x1000U) +#define GPIO_PDOR_PDO12_SHIFT (12U) +/*! PDO12 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO12_SHIFT)) & GPIO_PDOR_PDO12_MASK) + +#define GPIO_PDOR_PDO13_MASK (0x2000U) +#define GPIO_PDOR_PDO13_SHIFT (13U) +/*! PDO13 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO13_SHIFT)) & GPIO_PDOR_PDO13_MASK) + +#define GPIO_PDOR_PDO14_MASK (0x4000U) +#define GPIO_PDOR_PDO14_SHIFT (14U) +/*! PDO14 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO14_SHIFT)) & GPIO_PDOR_PDO14_MASK) + +#define GPIO_PDOR_PDO15_MASK (0x8000U) +#define GPIO_PDOR_PDO15_SHIFT (15U) +/*! PDO15 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO15_SHIFT)) & GPIO_PDOR_PDO15_MASK) + +#define GPIO_PDOR_PDO16_MASK (0x10000U) +#define GPIO_PDOR_PDO16_SHIFT (16U) +/*! PDO16 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO16_SHIFT)) & GPIO_PDOR_PDO16_MASK) + +#define GPIO_PDOR_PDO17_MASK (0x20000U) +#define GPIO_PDOR_PDO17_SHIFT (17U) +/*! PDO17 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO17_SHIFT)) & GPIO_PDOR_PDO17_MASK) + +#define GPIO_PDOR_PDO18_MASK (0x40000U) +#define GPIO_PDOR_PDO18_SHIFT (18U) +/*! PDO18 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO18_SHIFT)) & GPIO_PDOR_PDO18_MASK) + +#define GPIO_PDOR_PDO19_MASK (0x80000U) +#define GPIO_PDOR_PDO19_SHIFT (19U) +/*! PDO19 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO19_SHIFT)) & GPIO_PDOR_PDO19_MASK) + +#define GPIO_PDOR_PDO20_MASK (0x100000U) +#define GPIO_PDOR_PDO20_SHIFT (20U) +/*! PDO20 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO20_SHIFT)) & GPIO_PDOR_PDO20_MASK) + +#define GPIO_PDOR_PDO21_MASK (0x200000U) +#define GPIO_PDOR_PDO21_SHIFT (21U) +/*! PDO21 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO21_SHIFT)) & GPIO_PDOR_PDO21_MASK) + +#define GPIO_PDOR_PDO22_MASK (0x400000U) +#define GPIO_PDOR_PDO22_SHIFT (22U) +/*! PDO22 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO22_SHIFT)) & GPIO_PDOR_PDO22_MASK) + +#define GPIO_PDOR_PDO23_MASK (0x800000U) +#define GPIO_PDOR_PDO23_SHIFT (23U) +/*! PDO23 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO23_SHIFT)) & GPIO_PDOR_PDO23_MASK) + +#define GPIO_PDOR_PDO24_MASK (0x1000000U) +#define GPIO_PDOR_PDO24_SHIFT (24U) +/*! PDO24 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO24_SHIFT)) & GPIO_PDOR_PDO24_MASK) + +#define GPIO_PDOR_PDO25_MASK (0x2000000U) +#define GPIO_PDOR_PDO25_SHIFT (25U) +/*! PDO25 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO25_SHIFT)) & GPIO_PDOR_PDO25_MASK) + +#define GPIO_PDOR_PDO26_MASK (0x4000000U) +#define GPIO_PDOR_PDO26_SHIFT (26U) +/*! PDO26 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO26_SHIFT)) & GPIO_PDOR_PDO26_MASK) + +#define GPIO_PDOR_PDO27_MASK (0x8000000U) +#define GPIO_PDOR_PDO27_SHIFT (27U) +/*! PDO27 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO27_SHIFT)) & GPIO_PDOR_PDO27_MASK) + +#define GPIO_PDOR_PDO28_MASK (0x10000000U) +#define GPIO_PDOR_PDO28_SHIFT (28U) +/*! PDO28 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO28_SHIFT)) & GPIO_PDOR_PDO28_MASK) + +#define GPIO_PDOR_PDO29_MASK (0x20000000U) +#define GPIO_PDOR_PDO29_SHIFT (29U) +/*! PDO29 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO29_SHIFT)) & GPIO_PDOR_PDO29_MASK) + +#define GPIO_PDOR_PDO30_MASK (0x40000000U) +#define GPIO_PDOR_PDO30_SHIFT (30U) +/*! PDO30 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO30_SHIFT)) & GPIO_PDOR_PDO30_MASK) + +#define GPIO_PDOR_PDO31_MASK (0x80000000U) +#define GPIO_PDOR_PDO31_SHIFT (31U) +/*! PDO31 - Port Data Output + * 0b0..Logic level 0 + * 0b1..Logic level 1 + */ +#define GPIO_PDOR_PDO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO31_SHIFT)) & GPIO_PDOR_PDO31_MASK) +/*! @} */ + +/*! @name PSOR - Port Set Output */ +/*! @{ */ + +#define GPIO_PSOR_PTSO0_MASK (0x1U) +#define GPIO_PSOR_PTSO0_SHIFT (0U) +/*! PTSO0 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO0_SHIFT)) & GPIO_PSOR_PTSO0_MASK) + +#define GPIO_PSOR_PTSO1_MASK (0x2U) +#define GPIO_PSOR_PTSO1_SHIFT (1U) +/*! PTSO1 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO1_SHIFT)) & GPIO_PSOR_PTSO1_MASK) + +#define GPIO_PSOR_PTSO2_MASK (0x4U) +#define GPIO_PSOR_PTSO2_SHIFT (2U) +/*! PTSO2 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO2_SHIFT)) & GPIO_PSOR_PTSO2_MASK) + +#define GPIO_PSOR_PTSO3_MASK (0x8U) +#define GPIO_PSOR_PTSO3_SHIFT (3U) +/*! PTSO3 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO3_SHIFT)) & GPIO_PSOR_PTSO3_MASK) + +#define GPIO_PSOR_PTSO4_MASK (0x10U) +#define GPIO_PSOR_PTSO4_SHIFT (4U) +/*! PTSO4 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO4_SHIFT)) & GPIO_PSOR_PTSO4_MASK) + +#define GPIO_PSOR_PTSO5_MASK (0x20U) +#define GPIO_PSOR_PTSO5_SHIFT (5U) +/*! PTSO5 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO5_SHIFT)) & GPIO_PSOR_PTSO5_MASK) + +#define GPIO_PSOR_PTSO6_MASK (0x40U) +#define GPIO_PSOR_PTSO6_SHIFT (6U) +/*! PTSO6 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO6_SHIFT)) & GPIO_PSOR_PTSO6_MASK) + +#define GPIO_PSOR_PTSO7_MASK (0x80U) +#define GPIO_PSOR_PTSO7_SHIFT (7U) +/*! PTSO7 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO7_SHIFT)) & GPIO_PSOR_PTSO7_MASK) + +#define GPIO_PSOR_PTSO8_MASK (0x100U) +#define GPIO_PSOR_PTSO8_SHIFT (8U) +/*! PTSO8 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO8_SHIFT)) & GPIO_PSOR_PTSO8_MASK) + +#define GPIO_PSOR_PTSO9_MASK (0x200U) +#define GPIO_PSOR_PTSO9_SHIFT (9U) +/*! PTSO9 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO9_SHIFT)) & GPIO_PSOR_PTSO9_MASK) + +#define GPIO_PSOR_PTSO10_MASK (0x400U) +#define GPIO_PSOR_PTSO10_SHIFT (10U) +/*! PTSO10 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO10_SHIFT)) & GPIO_PSOR_PTSO10_MASK) + +#define GPIO_PSOR_PTSO11_MASK (0x800U) +#define GPIO_PSOR_PTSO11_SHIFT (11U) +/*! PTSO11 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO11_SHIFT)) & GPIO_PSOR_PTSO11_MASK) + +#define GPIO_PSOR_PTSO12_MASK (0x1000U) +#define GPIO_PSOR_PTSO12_SHIFT (12U) +/*! PTSO12 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO12_SHIFT)) & GPIO_PSOR_PTSO12_MASK) + +#define GPIO_PSOR_PTSO13_MASK (0x2000U) +#define GPIO_PSOR_PTSO13_SHIFT (13U) +/*! PTSO13 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO13_SHIFT)) & GPIO_PSOR_PTSO13_MASK) + +#define GPIO_PSOR_PTSO14_MASK (0x4000U) +#define GPIO_PSOR_PTSO14_SHIFT (14U) +/*! PTSO14 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO14_SHIFT)) & GPIO_PSOR_PTSO14_MASK) + +#define GPIO_PSOR_PTSO15_MASK (0x8000U) +#define GPIO_PSOR_PTSO15_SHIFT (15U) +/*! PTSO15 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO15_SHIFT)) & GPIO_PSOR_PTSO15_MASK) + +#define GPIO_PSOR_PTSO16_MASK (0x10000U) +#define GPIO_PSOR_PTSO16_SHIFT (16U) +/*! PTSO16 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO16_SHIFT)) & GPIO_PSOR_PTSO16_MASK) + +#define GPIO_PSOR_PTSO17_MASK (0x20000U) +#define GPIO_PSOR_PTSO17_SHIFT (17U) +/*! PTSO17 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO17_SHIFT)) & GPIO_PSOR_PTSO17_MASK) + +#define GPIO_PSOR_PTSO18_MASK (0x40000U) +#define GPIO_PSOR_PTSO18_SHIFT (18U) +/*! PTSO18 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO18_SHIFT)) & GPIO_PSOR_PTSO18_MASK) + +#define GPIO_PSOR_PTSO19_MASK (0x80000U) +#define GPIO_PSOR_PTSO19_SHIFT (19U) +/*! PTSO19 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO19_SHIFT)) & GPIO_PSOR_PTSO19_MASK) + +#define GPIO_PSOR_PTSO20_MASK (0x100000U) +#define GPIO_PSOR_PTSO20_SHIFT (20U) +/*! PTSO20 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO20_SHIFT)) & GPIO_PSOR_PTSO20_MASK) + +#define GPIO_PSOR_PTSO21_MASK (0x200000U) +#define GPIO_PSOR_PTSO21_SHIFT (21U) +/*! PTSO21 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO21_SHIFT)) & GPIO_PSOR_PTSO21_MASK) + +#define GPIO_PSOR_PTSO22_MASK (0x400000U) +#define GPIO_PSOR_PTSO22_SHIFT (22U) +/*! PTSO22 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO22_SHIFT)) & GPIO_PSOR_PTSO22_MASK) + +#define GPIO_PSOR_PTSO23_MASK (0x800000U) +#define GPIO_PSOR_PTSO23_SHIFT (23U) +/*! PTSO23 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO23_SHIFT)) & GPIO_PSOR_PTSO23_MASK) + +#define GPIO_PSOR_PTSO24_MASK (0x1000000U) +#define GPIO_PSOR_PTSO24_SHIFT (24U) +/*! PTSO24 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO24_SHIFT)) & GPIO_PSOR_PTSO24_MASK) + +#define GPIO_PSOR_PTSO25_MASK (0x2000000U) +#define GPIO_PSOR_PTSO25_SHIFT (25U) +/*! PTSO25 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO25_SHIFT)) & GPIO_PSOR_PTSO25_MASK) + +#define GPIO_PSOR_PTSO26_MASK (0x4000000U) +#define GPIO_PSOR_PTSO26_SHIFT (26U) +/*! PTSO26 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO26_SHIFT)) & GPIO_PSOR_PTSO26_MASK) + +#define GPIO_PSOR_PTSO27_MASK (0x8000000U) +#define GPIO_PSOR_PTSO27_SHIFT (27U) +/*! PTSO27 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO27_SHIFT)) & GPIO_PSOR_PTSO27_MASK) + +#define GPIO_PSOR_PTSO28_MASK (0x10000000U) +#define GPIO_PSOR_PTSO28_SHIFT (28U) +/*! PTSO28 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO28_SHIFT)) & GPIO_PSOR_PTSO28_MASK) + +#define GPIO_PSOR_PTSO29_MASK (0x20000000U) +#define GPIO_PSOR_PTSO29_SHIFT (29U) +/*! PTSO29 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO29_SHIFT)) & GPIO_PSOR_PTSO29_MASK) + +#define GPIO_PSOR_PTSO30_MASK (0x40000000U) +#define GPIO_PSOR_PTSO30_SHIFT (30U) +/*! PTSO30 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO30_SHIFT)) & GPIO_PSOR_PTSO30_MASK) + +#define GPIO_PSOR_PTSO31_MASK (0x80000000U) +#define GPIO_PSOR_PTSO31_SHIFT (31U) +/*! PTSO31 - Port Set Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 1 + */ +#define GPIO_PSOR_PTSO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO31_SHIFT)) & GPIO_PSOR_PTSO31_MASK) +/*! @} */ + +/*! @name PCOR - Port Clear Output */ +/*! @{ */ + +#define GPIO_PCOR_PTCO0_MASK (0x1U) +#define GPIO_PCOR_PTCO0_SHIFT (0U) +/*! PTCO0 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO0_SHIFT)) & GPIO_PCOR_PTCO0_MASK) + +#define GPIO_PCOR_PTCO1_MASK (0x2U) +#define GPIO_PCOR_PTCO1_SHIFT (1U) +/*! PTCO1 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO1_SHIFT)) & GPIO_PCOR_PTCO1_MASK) + +#define GPIO_PCOR_PTCO2_MASK (0x4U) +#define GPIO_PCOR_PTCO2_SHIFT (2U) +/*! PTCO2 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO2_SHIFT)) & GPIO_PCOR_PTCO2_MASK) + +#define GPIO_PCOR_PTCO3_MASK (0x8U) +#define GPIO_PCOR_PTCO3_SHIFT (3U) +/*! PTCO3 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO3_SHIFT)) & GPIO_PCOR_PTCO3_MASK) + +#define GPIO_PCOR_PTCO4_MASK (0x10U) +#define GPIO_PCOR_PTCO4_SHIFT (4U) +/*! PTCO4 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO4_SHIFT)) & GPIO_PCOR_PTCO4_MASK) + +#define GPIO_PCOR_PTCO5_MASK (0x20U) +#define GPIO_PCOR_PTCO5_SHIFT (5U) +/*! PTCO5 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO5_SHIFT)) & GPIO_PCOR_PTCO5_MASK) + +#define GPIO_PCOR_PTCO6_MASK (0x40U) +#define GPIO_PCOR_PTCO6_SHIFT (6U) +/*! PTCO6 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO6_SHIFT)) & GPIO_PCOR_PTCO6_MASK) + +#define GPIO_PCOR_PTCO7_MASK (0x80U) +#define GPIO_PCOR_PTCO7_SHIFT (7U) +/*! PTCO7 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO7_SHIFT)) & GPIO_PCOR_PTCO7_MASK) + +#define GPIO_PCOR_PTCO8_MASK (0x100U) +#define GPIO_PCOR_PTCO8_SHIFT (8U) +/*! PTCO8 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO8_SHIFT)) & GPIO_PCOR_PTCO8_MASK) + +#define GPIO_PCOR_PTCO9_MASK (0x200U) +#define GPIO_PCOR_PTCO9_SHIFT (9U) +/*! PTCO9 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO9_SHIFT)) & GPIO_PCOR_PTCO9_MASK) + +#define GPIO_PCOR_PTCO10_MASK (0x400U) +#define GPIO_PCOR_PTCO10_SHIFT (10U) +/*! PTCO10 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO10_SHIFT)) & GPIO_PCOR_PTCO10_MASK) + +#define GPIO_PCOR_PTCO11_MASK (0x800U) +#define GPIO_PCOR_PTCO11_SHIFT (11U) +/*! PTCO11 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO11_SHIFT)) & GPIO_PCOR_PTCO11_MASK) + +#define GPIO_PCOR_PTCO12_MASK (0x1000U) +#define GPIO_PCOR_PTCO12_SHIFT (12U) +/*! PTCO12 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO12_SHIFT)) & GPIO_PCOR_PTCO12_MASK) + +#define GPIO_PCOR_PTCO13_MASK (0x2000U) +#define GPIO_PCOR_PTCO13_SHIFT (13U) +/*! PTCO13 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO13_SHIFT)) & GPIO_PCOR_PTCO13_MASK) + +#define GPIO_PCOR_PTCO14_MASK (0x4000U) +#define GPIO_PCOR_PTCO14_SHIFT (14U) +/*! PTCO14 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO14_SHIFT)) & GPIO_PCOR_PTCO14_MASK) + +#define GPIO_PCOR_PTCO15_MASK (0x8000U) +#define GPIO_PCOR_PTCO15_SHIFT (15U) +/*! PTCO15 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO15_SHIFT)) & GPIO_PCOR_PTCO15_MASK) + +#define GPIO_PCOR_PTCO16_MASK (0x10000U) +#define GPIO_PCOR_PTCO16_SHIFT (16U) +/*! PTCO16 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO16_SHIFT)) & GPIO_PCOR_PTCO16_MASK) + +#define GPIO_PCOR_PTCO17_MASK (0x20000U) +#define GPIO_PCOR_PTCO17_SHIFT (17U) +/*! PTCO17 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO17_SHIFT)) & GPIO_PCOR_PTCO17_MASK) + +#define GPIO_PCOR_PTCO18_MASK (0x40000U) +#define GPIO_PCOR_PTCO18_SHIFT (18U) +/*! PTCO18 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO18_SHIFT)) & GPIO_PCOR_PTCO18_MASK) + +#define GPIO_PCOR_PTCO19_MASK (0x80000U) +#define GPIO_PCOR_PTCO19_SHIFT (19U) +/*! PTCO19 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO19_SHIFT)) & GPIO_PCOR_PTCO19_MASK) + +#define GPIO_PCOR_PTCO20_MASK (0x100000U) +#define GPIO_PCOR_PTCO20_SHIFT (20U) +/*! PTCO20 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO20_SHIFT)) & GPIO_PCOR_PTCO20_MASK) + +#define GPIO_PCOR_PTCO21_MASK (0x200000U) +#define GPIO_PCOR_PTCO21_SHIFT (21U) +/*! PTCO21 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO21_SHIFT)) & GPIO_PCOR_PTCO21_MASK) + +#define GPIO_PCOR_PTCO22_MASK (0x400000U) +#define GPIO_PCOR_PTCO22_SHIFT (22U) +/*! PTCO22 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO22_SHIFT)) & GPIO_PCOR_PTCO22_MASK) + +#define GPIO_PCOR_PTCO23_MASK (0x800000U) +#define GPIO_PCOR_PTCO23_SHIFT (23U) +/*! PTCO23 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO23_SHIFT)) & GPIO_PCOR_PTCO23_MASK) + +#define GPIO_PCOR_PTCO24_MASK (0x1000000U) +#define GPIO_PCOR_PTCO24_SHIFT (24U) +/*! PTCO24 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO24_SHIFT)) & GPIO_PCOR_PTCO24_MASK) + +#define GPIO_PCOR_PTCO25_MASK (0x2000000U) +#define GPIO_PCOR_PTCO25_SHIFT (25U) +/*! PTCO25 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO25_SHIFT)) & GPIO_PCOR_PTCO25_MASK) + +#define GPIO_PCOR_PTCO26_MASK (0x4000000U) +#define GPIO_PCOR_PTCO26_SHIFT (26U) +/*! PTCO26 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO26_SHIFT)) & GPIO_PCOR_PTCO26_MASK) + +#define GPIO_PCOR_PTCO27_MASK (0x8000000U) +#define GPIO_PCOR_PTCO27_SHIFT (27U) +/*! PTCO27 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO27_SHIFT)) & GPIO_PCOR_PTCO27_MASK) + +#define GPIO_PCOR_PTCO28_MASK (0x10000000U) +#define GPIO_PCOR_PTCO28_SHIFT (28U) +/*! PTCO28 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO28_SHIFT)) & GPIO_PCOR_PTCO28_MASK) + +#define GPIO_PCOR_PTCO29_MASK (0x20000000U) +#define GPIO_PCOR_PTCO29_SHIFT (29U) +/*! PTCO29 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO29_SHIFT)) & GPIO_PCOR_PTCO29_MASK) + +#define GPIO_PCOR_PTCO30_MASK (0x40000000U) +#define GPIO_PCOR_PTCO30_SHIFT (30U) +/*! PTCO30 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO30_SHIFT)) & GPIO_PCOR_PTCO30_MASK) + +#define GPIO_PCOR_PTCO31_MASK (0x80000000U) +#define GPIO_PCOR_PTCO31_SHIFT (31U) +/*! PTCO31 - Port Clear Output + * 0b0..No change + * 0b1..Corresponding field in PDOR becomes 0 + */ +#define GPIO_PCOR_PTCO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO31_SHIFT)) & GPIO_PCOR_PTCO31_MASK) +/*! @} */ + +/*! @name PTOR - Port Toggle Output */ +/*! @{ */ + +#define GPIO_PTOR_PTTO0_MASK (0x1U) +#define GPIO_PTOR_PTTO0_SHIFT (0U) +/*! PTTO0 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO0_SHIFT)) & GPIO_PTOR_PTTO0_MASK) + +#define GPIO_PTOR_PTTO1_MASK (0x2U) +#define GPIO_PTOR_PTTO1_SHIFT (1U) +/*! PTTO1 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO1_SHIFT)) & GPIO_PTOR_PTTO1_MASK) + +#define GPIO_PTOR_PTTO2_MASK (0x4U) +#define GPIO_PTOR_PTTO2_SHIFT (2U) +/*! PTTO2 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO2_SHIFT)) & GPIO_PTOR_PTTO2_MASK) + +#define GPIO_PTOR_PTTO3_MASK (0x8U) +#define GPIO_PTOR_PTTO3_SHIFT (3U) +/*! PTTO3 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO3_SHIFT)) & GPIO_PTOR_PTTO3_MASK) + +#define GPIO_PTOR_PTTO4_MASK (0x10U) +#define GPIO_PTOR_PTTO4_SHIFT (4U) +/*! PTTO4 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO4_SHIFT)) & GPIO_PTOR_PTTO4_MASK) + +#define GPIO_PTOR_PTTO5_MASK (0x20U) +#define GPIO_PTOR_PTTO5_SHIFT (5U) +/*! PTTO5 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO5_SHIFT)) & GPIO_PTOR_PTTO5_MASK) + +#define GPIO_PTOR_PTTO6_MASK (0x40U) +#define GPIO_PTOR_PTTO6_SHIFT (6U) +/*! PTTO6 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO6_SHIFT)) & GPIO_PTOR_PTTO6_MASK) + +#define GPIO_PTOR_PTTO7_MASK (0x80U) +#define GPIO_PTOR_PTTO7_SHIFT (7U) +/*! PTTO7 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO7_SHIFT)) & GPIO_PTOR_PTTO7_MASK) + +#define GPIO_PTOR_PTTO8_MASK (0x100U) +#define GPIO_PTOR_PTTO8_SHIFT (8U) +/*! PTTO8 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO8_SHIFT)) & GPIO_PTOR_PTTO8_MASK) + +#define GPIO_PTOR_PTTO9_MASK (0x200U) +#define GPIO_PTOR_PTTO9_SHIFT (9U) +/*! PTTO9 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO9_SHIFT)) & GPIO_PTOR_PTTO9_MASK) + +#define GPIO_PTOR_PTTO10_MASK (0x400U) +#define GPIO_PTOR_PTTO10_SHIFT (10U) +/*! PTTO10 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO10_SHIFT)) & GPIO_PTOR_PTTO10_MASK) + +#define GPIO_PTOR_PTTO11_MASK (0x800U) +#define GPIO_PTOR_PTTO11_SHIFT (11U) +/*! PTTO11 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO11_SHIFT)) & GPIO_PTOR_PTTO11_MASK) + +#define GPIO_PTOR_PTTO12_MASK (0x1000U) +#define GPIO_PTOR_PTTO12_SHIFT (12U) +/*! PTTO12 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO12_SHIFT)) & GPIO_PTOR_PTTO12_MASK) + +#define GPIO_PTOR_PTTO13_MASK (0x2000U) +#define GPIO_PTOR_PTTO13_SHIFT (13U) +/*! PTTO13 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO13_SHIFT)) & GPIO_PTOR_PTTO13_MASK) + +#define GPIO_PTOR_PTTO14_MASK (0x4000U) +#define GPIO_PTOR_PTTO14_SHIFT (14U) +/*! PTTO14 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO14_SHIFT)) & GPIO_PTOR_PTTO14_MASK) + +#define GPIO_PTOR_PTTO15_MASK (0x8000U) +#define GPIO_PTOR_PTTO15_SHIFT (15U) +/*! PTTO15 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO15_SHIFT)) & GPIO_PTOR_PTTO15_MASK) + +#define GPIO_PTOR_PTTO16_MASK (0x10000U) +#define GPIO_PTOR_PTTO16_SHIFT (16U) +/*! PTTO16 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO16_SHIFT)) & GPIO_PTOR_PTTO16_MASK) + +#define GPIO_PTOR_PTTO17_MASK (0x20000U) +#define GPIO_PTOR_PTTO17_SHIFT (17U) +/*! PTTO17 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO17_SHIFT)) & GPIO_PTOR_PTTO17_MASK) + +#define GPIO_PTOR_PTTO18_MASK (0x40000U) +#define GPIO_PTOR_PTTO18_SHIFT (18U) +/*! PTTO18 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO18_SHIFT)) & GPIO_PTOR_PTTO18_MASK) + +#define GPIO_PTOR_PTTO19_MASK (0x80000U) +#define GPIO_PTOR_PTTO19_SHIFT (19U) +/*! PTTO19 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO19_SHIFT)) & GPIO_PTOR_PTTO19_MASK) + +#define GPIO_PTOR_PTTO20_MASK (0x100000U) +#define GPIO_PTOR_PTTO20_SHIFT (20U) +/*! PTTO20 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO20_SHIFT)) & GPIO_PTOR_PTTO20_MASK) + +#define GPIO_PTOR_PTTO21_MASK (0x200000U) +#define GPIO_PTOR_PTTO21_SHIFT (21U) +/*! PTTO21 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO21_SHIFT)) & GPIO_PTOR_PTTO21_MASK) + +#define GPIO_PTOR_PTTO22_MASK (0x400000U) +#define GPIO_PTOR_PTTO22_SHIFT (22U) +/*! PTTO22 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO22_SHIFT)) & GPIO_PTOR_PTTO22_MASK) + +#define GPIO_PTOR_PTTO23_MASK (0x800000U) +#define GPIO_PTOR_PTTO23_SHIFT (23U) +/*! PTTO23 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO23_SHIFT)) & GPIO_PTOR_PTTO23_MASK) + +#define GPIO_PTOR_PTTO24_MASK (0x1000000U) +#define GPIO_PTOR_PTTO24_SHIFT (24U) +/*! PTTO24 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO24_SHIFT)) & GPIO_PTOR_PTTO24_MASK) + +#define GPIO_PTOR_PTTO25_MASK (0x2000000U) +#define GPIO_PTOR_PTTO25_SHIFT (25U) +/*! PTTO25 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO25_SHIFT)) & GPIO_PTOR_PTTO25_MASK) + +#define GPIO_PTOR_PTTO26_MASK (0x4000000U) +#define GPIO_PTOR_PTTO26_SHIFT (26U) +/*! PTTO26 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO26_SHIFT)) & GPIO_PTOR_PTTO26_MASK) + +#define GPIO_PTOR_PTTO27_MASK (0x8000000U) +#define GPIO_PTOR_PTTO27_SHIFT (27U) +/*! PTTO27 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO27_SHIFT)) & GPIO_PTOR_PTTO27_MASK) + +#define GPIO_PTOR_PTTO28_MASK (0x10000000U) +#define GPIO_PTOR_PTTO28_SHIFT (28U) +/*! PTTO28 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO28_SHIFT)) & GPIO_PTOR_PTTO28_MASK) + +#define GPIO_PTOR_PTTO29_MASK (0x20000000U) +#define GPIO_PTOR_PTTO29_SHIFT (29U) +/*! PTTO29 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO29_SHIFT)) & GPIO_PTOR_PTTO29_MASK) + +#define GPIO_PTOR_PTTO30_MASK (0x40000000U) +#define GPIO_PTOR_PTTO30_SHIFT (30U) +/*! PTTO30 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO30_SHIFT)) & GPIO_PTOR_PTTO30_MASK) + +#define GPIO_PTOR_PTTO31_MASK (0x80000000U) +#define GPIO_PTOR_PTTO31_SHIFT (31U) +/*! PTTO31 - Port Toggle Output + * 0b0..No change + * 0b1..Set to the inverse of its current logic state + */ +#define GPIO_PTOR_PTTO31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO31_SHIFT)) & GPIO_PTOR_PTTO31_MASK) +/*! @} */ + +/*! @name PDIR - Port Data Input */ +/*! @{ */ + +#define GPIO_PDIR_PDI0_MASK (0x1U) +#define GPIO_PDIR_PDI0_SHIFT (0U) +/*! PDI0 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI0_SHIFT)) & GPIO_PDIR_PDI0_MASK) + +#define GPIO_PDIR_PDI1_MASK (0x2U) +#define GPIO_PDIR_PDI1_SHIFT (1U) +/*! PDI1 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI1_SHIFT)) & GPIO_PDIR_PDI1_MASK) + +#define GPIO_PDIR_PDI2_MASK (0x4U) +#define GPIO_PDIR_PDI2_SHIFT (2U) +/*! PDI2 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI2_SHIFT)) & GPIO_PDIR_PDI2_MASK) + +#define GPIO_PDIR_PDI3_MASK (0x8U) +#define GPIO_PDIR_PDI3_SHIFT (3U) +/*! PDI3 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI3_SHIFT)) & GPIO_PDIR_PDI3_MASK) + +#define GPIO_PDIR_PDI4_MASK (0x10U) +#define GPIO_PDIR_PDI4_SHIFT (4U) +/*! PDI4 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI4_SHIFT)) & GPIO_PDIR_PDI4_MASK) + +#define GPIO_PDIR_PDI5_MASK (0x20U) +#define GPIO_PDIR_PDI5_SHIFT (5U) +/*! PDI5 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI5_SHIFT)) & GPIO_PDIR_PDI5_MASK) + +#define GPIO_PDIR_PDI6_MASK (0x40U) +#define GPIO_PDIR_PDI6_SHIFT (6U) +/*! PDI6 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI6_SHIFT)) & GPIO_PDIR_PDI6_MASK) + +#define GPIO_PDIR_PDI7_MASK (0x80U) +#define GPIO_PDIR_PDI7_SHIFT (7U) +/*! PDI7 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI7_SHIFT)) & GPIO_PDIR_PDI7_MASK) + +#define GPIO_PDIR_PDI8_MASK (0x100U) +#define GPIO_PDIR_PDI8_SHIFT (8U) +/*! PDI8 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI8_SHIFT)) & GPIO_PDIR_PDI8_MASK) + +#define GPIO_PDIR_PDI9_MASK (0x200U) +#define GPIO_PDIR_PDI9_SHIFT (9U) +/*! PDI9 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI9_SHIFT)) & GPIO_PDIR_PDI9_MASK) + +#define GPIO_PDIR_PDI10_MASK (0x400U) +#define GPIO_PDIR_PDI10_SHIFT (10U) +/*! PDI10 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI10_SHIFT)) & GPIO_PDIR_PDI10_MASK) + +#define GPIO_PDIR_PDI11_MASK (0x800U) +#define GPIO_PDIR_PDI11_SHIFT (11U) +/*! PDI11 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI11_SHIFT)) & GPIO_PDIR_PDI11_MASK) + +#define GPIO_PDIR_PDI12_MASK (0x1000U) +#define GPIO_PDIR_PDI12_SHIFT (12U) +/*! PDI12 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI12_SHIFT)) & GPIO_PDIR_PDI12_MASK) + +#define GPIO_PDIR_PDI13_MASK (0x2000U) +#define GPIO_PDIR_PDI13_SHIFT (13U) +/*! PDI13 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI13_SHIFT)) & GPIO_PDIR_PDI13_MASK) + +#define GPIO_PDIR_PDI14_MASK (0x4000U) +#define GPIO_PDIR_PDI14_SHIFT (14U) +/*! PDI14 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI14_SHIFT)) & GPIO_PDIR_PDI14_MASK) + +#define GPIO_PDIR_PDI15_MASK (0x8000U) +#define GPIO_PDIR_PDI15_SHIFT (15U) +/*! PDI15 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI15_SHIFT)) & GPIO_PDIR_PDI15_MASK) + +#define GPIO_PDIR_PDI16_MASK (0x10000U) +#define GPIO_PDIR_PDI16_SHIFT (16U) +/*! PDI16 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI16_SHIFT)) & GPIO_PDIR_PDI16_MASK) + +#define GPIO_PDIR_PDI17_MASK (0x20000U) +#define GPIO_PDIR_PDI17_SHIFT (17U) +/*! PDI17 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI17_SHIFT)) & GPIO_PDIR_PDI17_MASK) + +#define GPIO_PDIR_PDI18_MASK (0x40000U) +#define GPIO_PDIR_PDI18_SHIFT (18U) +/*! PDI18 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI18_SHIFT)) & GPIO_PDIR_PDI18_MASK) + +#define GPIO_PDIR_PDI19_MASK (0x80000U) +#define GPIO_PDIR_PDI19_SHIFT (19U) +/*! PDI19 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI19_SHIFT)) & GPIO_PDIR_PDI19_MASK) + +#define GPIO_PDIR_PDI20_MASK (0x100000U) +#define GPIO_PDIR_PDI20_SHIFT (20U) +/*! PDI20 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI20_SHIFT)) & GPIO_PDIR_PDI20_MASK) + +#define GPIO_PDIR_PDI21_MASK (0x200000U) +#define GPIO_PDIR_PDI21_SHIFT (21U) +/*! PDI21 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI21_SHIFT)) & GPIO_PDIR_PDI21_MASK) + +#define GPIO_PDIR_PDI22_MASK (0x400000U) +#define GPIO_PDIR_PDI22_SHIFT (22U) +/*! PDI22 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI22_SHIFT)) & GPIO_PDIR_PDI22_MASK) + +#define GPIO_PDIR_PDI23_MASK (0x800000U) +#define GPIO_PDIR_PDI23_SHIFT (23U) +/*! PDI23 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI23_SHIFT)) & GPIO_PDIR_PDI23_MASK) + +#define GPIO_PDIR_PDI24_MASK (0x1000000U) +#define GPIO_PDIR_PDI24_SHIFT (24U) +/*! PDI24 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI24_SHIFT)) & GPIO_PDIR_PDI24_MASK) + +#define GPIO_PDIR_PDI25_MASK (0x2000000U) +#define GPIO_PDIR_PDI25_SHIFT (25U) +/*! PDI25 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI25_SHIFT)) & GPIO_PDIR_PDI25_MASK) + +#define GPIO_PDIR_PDI26_MASK (0x4000000U) +#define GPIO_PDIR_PDI26_SHIFT (26U) +/*! PDI26 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI26_SHIFT)) & GPIO_PDIR_PDI26_MASK) + +#define GPIO_PDIR_PDI27_MASK (0x8000000U) +#define GPIO_PDIR_PDI27_SHIFT (27U) +/*! PDI27 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI27_SHIFT)) & GPIO_PDIR_PDI27_MASK) + +#define GPIO_PDIR_PDI28_MASK (0x10000000U) +#define GPIO_PDIR_PDI28_SHIFT (28U) +/*! PDI28 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI28_SHIFT)) & GPIO_PDIR_PDI28_MASK) + +#define GPIO_PDIR_PDI29_MASK (0x20000000U) +#define GPIO_PDIR_PDI29_SHIFT (29U) +/*! PDI29 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI29_SHIFT)) & GPIO_PDIR_PDI29_MASK) + +#define GPIO_PDIR_PDI30_MASK (0x40000000U) +#define GPIO_PDIR_PDI30_SHIFT (30U) +/*! PDI30 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI30_SHIFT)) & GPIO_PDIR_PDI30_MASK) + +#define GPIO_PDIR_PDI31_MASK (0x80000000U) +#define GPIO_PDIR_PDI31_SHIFT (31U) +/*! PDI31 - Port Data Input + * 0b0..Logic 0 + * 0b1..Logic 1 + */ +#define GPIO_PDIR_PDI31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI31_SHIFT)) & GPIO_PDIR_PDI31_MASK) +/*! @} */ + +/*! @name PDDR - Port Data Direction */ +/*! @{ */ + +#define GPIO_PDDR_PDD0_MASK (0x1U) +#define GPIO_PDDR_PDD0_SHIFT (0U) +/*! PDD0 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD0_SHIFT)) & GPIO_PDDR_PDD0_MASK) + +#define GPIO_PDDR_PDD1_MASK (0x2U) +#define GPIO_PDDR_PDD1_SHIFT (1U) +/*! PDD1 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD1_SHIFT)) & GPIO_PDDR_PDD1_MASK) + +#define GPIO_PDDR_PDD2_MASK (0x4U) +#define GPIO_PDDR_PDD2_SHIFT (2U) +/*! PDD2 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD2_SHIFT)) & GPIO_PDDR_PDD2_MASK) + +#define GPIO_PDDR_PDD3_MASK (0x8U) +#define GPIO_PDDR_PDD3_SHIFT (3U) +/*! PDD3 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD3_SHIFT)) & GPIO_PDDR_PDD3_MASK) + +#define GPIO_PDDR_PDD4_MASK (0x10U) +#define GPIO_PDDR_PDD4_SHIFT (4U) +/*! PDD4 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD4_SHIFT)) & GPIO_PDDR_PDD4_MASK) + +#define GPIO_PDDR_PDD5_MASK (0x20U) +#define GPIO_PDDR_PDD5_SHIFT (5U) +/*! PDD5 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD5_SHIFT)) & GPIO_PDDR_PDD5_MASK) + +#define GPIO_PDDR_PDD6_MASK (0x40U) +#define GPIO_PDDR_PDD6_SHIFT (6U) +/*! PDD6 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD6_SHIFT)) & GPIO_PDDR_PDD6_MASK) + +#define GPIO_PDDR_PDD7_MASK (0x80U) +#define GPIO_PDDR_PDD7_SHIFT (7U) +/*! PDD7 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD7_SHIFT)) & GPIO_PDDR_PDD7_MASK) + +#define GPIO_PDDR_PDD8_MASK (0x100U) +#define GPIO_PDDR_PDD8_SHIFT (8U) +/*! PDD8 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD8_SHIFT)) & GPIO_PDDR_PDD8_MASK) + +#define GPIO_PDDR_PDD9_MASK (0x200U) +#define GPIO_PDDR_PDD9_SHIFT (9U) +/*! PDD9 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD9_SHIFT)) & GPIO_PDDR_PDD9_MASK) + +#define GPIO_PDDR_PDD10_MASK (0x400U) +#define GPIO_PDDR_PDD10_SHIFT (10U) +/*! PDD10 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD10_SHIFT)) & GPIO_PDDR_PDD10_MASK) + +#define GPIO_PDDR_PDD11_MASK (0x800U) +#define GPIO_PDDR_PDD11_SHIFT (11U) +/*! PDD11 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD11_SHIFT)) & GPIO_PDDR_PDD11_MASK) + +#define GPIO_PDDR_PDD12_MASK (0x1000U) +#define GPIO_PDDR_PDD12_SHIFT (12U) +/*! PDD12 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD12_SHIFT)) & GPIO_PDDR_PDD12_MASK) + +#define GPIO_PDDR_PDD13_MASK (0x2000U) +#define GPIO_PDDR_PDD13_SHIFT (13U) +/*! PDD13 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD13_SHIFT)) & GPIO_PDDR_PDD13_MASK) + +#define GPIO_PDDR_PDD14_MASK (0x4000U) +#define GPIO_PDDR_PDD14_SHIFT (14U) +/*! PDD14 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD14_SHIFT)) & GPIO_PDDR_PDD14_MASK) + +#define GPIO_PDDR_PDD15_MASK (0x8000U) +#define GPIO_PDDR_PDD15_SHIFT (15U) +/*! PDD15 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD15_SHIFT)) & GPIO_PDDR_PDD15_MASK) + +#define GPIO_PDDR_PDD16_MASK (0x10000U) +#define GPIO_PDDR_PDD16_SHIFT (16U) +/*! PDD16 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD16_SHIFT)) & GPIO_PDDR_PDD16_MASK) + +#define GPIO_PDDR_PDD17_MASK (0x20000U) +#define GPIO_PDDR_PDD17_SHIFT (17U) +/*! PDD17 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD17_SHIFT)) & GPIO_PDDR_PDD17_MASK) + +#define GPIO_PDDR_PDD18_MASK (0x40000U) +#define GPIO_PDDR_PDD18_SHIFT (18U) +/*! PDD18 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD18_SHIFT)) & GPIO_PDDR_PDD18_MASK) + +#define GPIO_PDDR_PDD19_MASK (0x80000U) +#define GPIO_PDDR_PDD19_SHIFT (19U) +/*! PDD19 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD19_SHIFT)) & GPIO_PDDR_PDD19_MASK) + +#define GPIO_PDDR_PDD20_MASK (0x100000U) +#define GPIO_PDDR_PDD20_SHIFT (20U) +/*! PDD20 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD20_SHIFT)) & GPIO_PDDR_PDD20_MASK) + +#define GPIO_PDDR_PDD21_MASK (0x200000U) +#define GPIO_PDDR_PDD21_SHIFT (21U) +/*! PDD21 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD21_SHIFT)) & GPIO_PDDR_PDD21_MASK) + +#define GPIO_PDDR_PDD22_MASK (0x400000U) +#define GPIO_PDDR_PDD22_SHIFT (22U) +/*! PDD22 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD22_SHIFT)) & GPIO_PDDR_PDD22_MASK) + +#define GPIO_PDDR_PDD23_MASK (0x800000U) +#define GPIO_PDDR_PDD23_SHIFT (23U) +/*! PDD23 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD23_SHIFT)) & GPIO_PDDR_PDD23_MASK) + +#define GPIO_PDDR_PDD24_MASK (0x1000000U) +#define GPIO_PDDR_PDD24_SHIFT (24U) +/*! PDD24 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD24_SHIFT)) & GPIO_PDDR_PDD24_MASK) + +#define GPIO_PDDR_PDD25_MASK (0x2000000U) +#define GPIO_PDDR_PDD25_SHIFT (25U) +/*! PDD25 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD25_SHIFT)) & GPIO_PDDR_PDD25_MASK) + +#define GPIO_PDDR_PDD26_MASK (0x4000000U) +#define GPIO_PDDR_PDD26_SHIFT (26U) +/*! PDD26 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD26_SHIFT)) & GPIO_PDDR_PDD26_MASK) + +#define GPIO_PDDR_PDD27_MASK (0x8000000U) +#define GPIO_PDDR_PDD27_SHIFT (27U) +/*! PDD27 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD27_SHIFT)) & GPIO_PDDR_PDD27_MASK) + +#define GPIO_PDDR_PDD28_MASK (0x10000000U) +#define GPIO_PDDR_PDD28_SHIFT (28U) +/*! PDD28 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD28_SHIFT)) & GPIO_PDDR_PDD28_MASK) + +#define GPIO_PDDR_PDD29_MASK (0x20000000U) +#define GPIO_PDDR_PDD29_SHIFT (29U) +/*! PDD29 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD29_SHIFT)) & GPIO_PDDR_PDD29_MASK) + +#define GPIO_PDDR_PDD30_MASK (0x40000000U) +#define GPIO_PDDR_PDD30_SHIFT (30U) +/*! PDD30 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD30_SHIFT)) & GPIO_PDDR_PDD30_MASK) + +#define GPIO_PDDR_PDD31_MASK (0x80000000U) +#define GPIO_PDDR_PDD31_SHIFT (31U) +/*! PDD31 - Port Data Direction + * 0b0..Input + * 0b1..Output + */ +#define GPIO_PDDR_PDD31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD31_SHIFT)) & GPIO_PDDR_PDD31_MASK) +/*! @} */ + +/*! @name PIDR - Port Input Disable */ +/*! @{ */ + +#define GPIO_PIDR_PID0_MASK (0x1U) +#define GPIO_PIDR_PID0_SHIFT (0U) +/*! PID0 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID0_SHIFT)) & GPIO_PIDR_PID0_MASK) + +#define GPIO_PIDR_PID1_MASK (0x2U) +#define GPIO_PIDR_PID1_SHIFT (1U) +/*! PID1 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID1_SHIFT)) & GPIO_PIDR_PID1_MASK) + +#define GPIO_PIDR_PID2_MASK (0x4U) +#define GPIO_PIDR_PID2_SHIFT (2U) +/*! PID2 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID2_SHIFT)) & GPIO_PIDR_PID2_MASK) + +#define GPIO_PIDR_PID3_MASK (0x8U) +#define GPIO_PIDR_PID3_SHIFT (3U) +/*! PID3 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID3_SHIFT)) & GPIO_PIDR_PID3_MASK) + +#define GPIO_PIDR_PID4_MASK (0x10U) +#define GPIO_PIDR_PID4_SHIFT (4U) +/*! PID4 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID4_SHIFT)) & GPIO_PIDR_PID4_MASK) + +#define GPIO_PIDR_PID5_MASK (0x20U) +#define GPIO_PIDR_PID5_SHIFT (5U) +/*! PID5 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID5_SHIFT)) & GPIO_PIDR_PID5_MASK) + +#define GPIO_PIDR_PID6_MASK (0x40U) +#define GPIO_PIDR_PID6_SHIFT (6U) +/*! PID6 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID6_SHIFT)) & GPIO_PIDR_PID6_MASK) + +#define GPIO_PIDR_PID7_MASK (0x80U) +#define GPIO_PIDR_PID7_SHIFT (7U) +/*! PID7 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID7_SHIFT)) & GPIO_PIDR_PID7_MASK) + +#define GPIO_PIDR_PID8_MASK (0x100U) +#define GPIO_PIDR_PID8_SHIFT (8U) +/*! PID8 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID8_SHIFT)) & GPIO_PIDR_PID8_MASK) + +#define GPIO_PIDR_PID9_MASK (0x200U) +#define GPIO_PIDR_PID9_SHIFT (9U) +/*! PID9 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID9_SHIFT)) & GPIO_PIDR_PID9_MASK) + +#define GPIO_PIDR_PID10_MASK (0x400U) +#define GPIO_PIDR_PID10_SHIFT (10U) +/*! PID10 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID10_SHIFT)) & GPIO_PIDR_PID10_MASK) + +#define GPIO_PIDR_PID11_MASK (0x800U) +#define GPIO_PIDR_PID11_SHIFT (11U) +/*! PID11 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID11_SHIFT)) & GPIO_PIDR_PID11_MASK) + +#define GPIO_PIDR_PID12_MASK (0x1000U) +#define GPIO_PIDR_PID12_SHIFT (12U) +/*! PID12 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID12_SHIFT)) & GPIO_PIDR_PID12_MASK) + +#define GPIO_PIDR_PID13_MASK (0x2000U) +#define GPIO_PIDR_PID13_SHIFT (13U) +/*! PID13 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID13_SHIFT)) & GPIO_PIDR_PID13_MASK) + +#define GPIO_PIDR_PID14_MASK (0x4000U) +#define GPIO_PIDR_PID14_SHIFT (14U) +/*! PID14 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID14_SHIFT)) & GPIO_PIDR_PID14_MASK) + +#define GPIO_PIDR_PID15_MASK (0x8000U) +#define GPIO_PIDR_PID15_SHIFT (15U) +/*! PID15 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID15_SHIFT)) & GPIO_PIDR_PID15_MASK) + +#define GPIO_PIDR_PID16_MASK (0x10000U) +#define GPIO_PIDR_PID16_SHIFT (16U) +/*! PID16 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID16_SHIFT)) & GPIO_PIDR_PID16_MASK) + +#define GPIO_PIDR_PID17_MASK (0x20000U) +#define GPIO_PIDR_PID17_SHIFT (17U) +/*! PID17 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID17_SHIFT)) & GPIO_PIDR_PID17_MASK) + +#define GPIO_PIDR_PID18_MASK (0x40000U) +#define GPIO_PIDR_PID18_SHIFT (18U) +/*! PID18 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID18_SHIFT)) & GPIO_PIDR_PID18_MASK) + +#define GPIO_PIDR_PID19_MASK (0x80000U) +#define GPIO_PIDR_PID19_SHIFT (19U) +/*! PID19 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID19_SHIFT)) & GPIO_PIDR_PID19_MASK) + +#define GPIO_PIDR_PID20_MASK (0x100000U) +#define GPIO_PIDR_PID20_SHIFT (20U) +/*! PID20 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID20_SHIFT)) & GPIO_PIDR_PID20_MASK) + +#define GPIO_PIDR_PID21_MASK (0x200000U) +#define GPIO_PIDR_PID21_SHIFT (21U) +/*! PID21 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID21_SHIFT)) & GPIO_PIDR_PID21_MASK) + +#define GPIO_PIDR_PID22_MASK (0x400000U) +#define GPIO_PIDR_PID22_SHIFT (22U) +/*! PID22 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID22_SHIFT)) & GPIO_PIDR_PID22_MASK) + +#define GPIO_PIDR_PID23_MASK (0x800000U) +#define GPIO_PIDR_PID23_SHIFT (23U) +/*! PID23 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID23_SHIFT)) & GPIO_PIDR_PID23_MASK) + +#define GPIO_PIDR_PID24_MASK (0x1000000U) +#define GPIO_PIDR_PID24_SHIFT (24U) +/*! PID24 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID24_SHIFT)) & GPIO_PIDR_PID24_MASK) + +#define GPIO_PIDR_PID25_MASK (0x2000000U) +#define GPIO_PIDR_PID25_SHIFT (25U) +/*! PID25 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID25_SHIFT)) & GPIO_PIDR_PID25_MASK) + +#define GPIO_PIDR_PID26_MASK (0x4000000U) +#define GPIO_PIDR_PID26_SHIFT (26U) +/*! PID26 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID26_SHIFT)) & GPIO_PIDR_PID26_MASK) + +#define GPIO_PIDR_PID27_MASK (0x8000000U) +#define GPIO_PIDR_PID27_SHIFT (27U) +/*! PID27 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID27_SHIFT)) & GPIO_PIDR_PID27_MASK) + +#define GPIO_PIDR_PID28_MASK (0x10000000U) +#define GPIO_PIDR_PID28_SHIFT (28U) +/*! PID28 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID28_SHIFT)) & GPIO_PIDR_PID28_MASK) + +#define GPIO_PIDR_PID29_MASK (0x20000000U) +#define GPIO_PIDR_PID29_SHIFT (29U) +/*! PID29 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID29_SHIFT)) & GPIO_PIDR_PID29_MASK) + +#define GPIO_PIDR_PID30_MASK (0x40000000U) +#define GPIO_PIDR_PID30_SHIFT (30U) +/*! PID30 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID30_SHIFT)) & GPIO_PIDR_PID30_MASK) + +#define GPIO_PIDR_PID31_MASK (0x80000000U) +#define GPIO_PIDR_PID31_SHIFT (31U) +/*! PID31 - Port Input Disable + * 0b0..Configured for general-purpose input + * 0b1..Disabled for general-purpose input + */ +#define GPIO_PIDR_PID31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID31_SHIFT)) & GPIO_PIDR_PID31_MASK) +/*! @} */ + +/*! @name PDR - Pin Data */ +/*! @{ */ + +#define GPIO_PDR_PD_MASK (0x1U) +#define GPIO_PDR_PD_SHIFT (0U) +/*! PD - Pin Data (I/O) + * 0b0..Logic zero + * 0b1..Logic one + */ +#define GPIO_PDR_PD(x) (((uint8_t)(((uint8_t)(x)) << GPIO_PDR_PD_SHIFT)) & GPIO_PDR_PD_MASK) +/*! @} */ + +/* The count of GPIO_PDR */ +#define GPIO_PDR_COUNT (32U) + +/*! @name ICR - Interrupt Control 0..Interrupt Control 31 */ +/*! @{ */ + +#define GPIO_ICR_IRQC_MASK (0xF0000U) +#define GPIO_ICR_IRQC_SHIFT (16U) +/*! IRQC - Interrupt Configuration + * 0b0000..ISF is disabled + * 0b0001..ISF and DMA request on rising edge + * 0b0010..ISF and DMA request on falling edge + * 0b0011..ISF and DMA request on either edge + * 0b0100..Reserved + * 0b0101..ISF sets on rising edge + * 0b0110..ISF sets on falling edge + * 0b0111..ISF sets on either edge + * 0b1000..ISF and interrupt when logic 0 + * 0b1001..ISF and interrupt on rising edge + * 0b1010..ISF and interrupt on falling edge + * 0b1011..ISF and Interrupt on either edge + * 0b1100..ISF and interrupt when logic 1 + * 0b1101..Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers + * to generate the output trigger for use by other peripherals) + * 0b1110..Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other + * enabled triggers to generate the output trigger for use by other peripherals) + * 0b1111..Reserved + */ +#define GPIO_ICR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_IRQC_SHIFT)) & GPIO_ICR_IRQC_MASK) + +#define GPIO_ICR_ISF_MASK (0x1000000U) +#define GPIO_ICR_ISF_SHIFT (24U) +/*! ISF - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ICR_ISF(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR_ISF_SHIFT)) & GPIO_ICR_ISF_MASK) +/*! @} */ + +/* The count of GPIO_ICR */ +#define GPIO_ICR_COUNT (32U) + +/*! @name GICLR - Global Interrupt Control Low */ +/*! @{ */ + +#define GPIO_GICLR_GIWE0_MASK (0x1U) +#define GPIO_GICLR_GIWE0_SHIFT (0U) +/*! GIWE0 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE0_SHIFT)) & GPIO_GICLR_GIWE0_MASK) + +#define GPIO_GICLR_GIWE1_MASK (0x2U) +#define GPIO_GICLR_GIWE1_SHIFT (1U) +/*! GIWE1 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE1_SHIFT)) & GPIO_GICLR_GIWE1_MASK) + +#define GPIO_GICLR_GIWE2_MASK (0x4U) +#define GPIO_GICLR_GIWE2_SHIFT (2U) +/*! GIWE2 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE2_SHIFT)) & GPIO_GICLR_GIWE2_MASK) + +#define GPIO_GICLR_GIWE3_MASK (0x8U) +#define GPIO_GICLR_GIWE3_SHIFT (3U) +/*! GIWE3 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE3_SHIFT)) & GPIO_GICLR_GIWE3_MASK) + +#define GPIO_GICLR_GIWE4_MASK (0x10U) +#define GPIO_GICLR_GIWE4_SHIFT (4U) +/*! GIWE4 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE4_SHIFT)) & GPIO_GICLR_GIWE4_MASK) + +#define GPIO_GICLR_GIWE5_MASK (0x20U) +#define GPIO_GICLR_GIWE5_SHIFT (5U) +/*! GIWE5 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE5_SHIFT)) & GPIO_GICLR_GIWE5_MASK) + +#define GPIO_GICLR_GIWE6_MASK (0x40U) +#define GPIO_GICLR_GIWE6_SHIFT (6U) +/*! GIWE6 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE6_SHIFT)) & GPIO_GICLR_GIWE6_MASK) + +#define GPIO_GICLR_GIWE7_MASK (0x80U) +#define GPIO_GICLR_GIWE7_SHIFT (7U) +/*! GIWE7 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE7_SHIFT)) & GPIO_GICLR_GIWE7_MASK) + +#define GPIO_GICLR_GIWE8_MASK (0x100U) +#define GPIO_GICLR_GIWE8_SHIFT (8U) +/*! GIWE8 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE8_SHIFT)) & GPIO_GICLR_GIWE8_MASK) + +#define GPIO_GICLR_GIWE9_MASK (0x200U) +#define GPIO_GICLR_GIWE9_SHIFT (9U) +/*! GIWE9 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE9_SHIFT)) & GPIO_GICLR_GIWE9_MASK) + +#define GPIO_GICLR_GIWE10_MASK (0x400U) +#define GPIO_GICLR_GIWE10_SHIFT (10U) +/*! GIWE10 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE10_SHIFT)) & GPIO_GICLR_GIWE10_MASK) + +#define GPIO_GICLR_GIWE11_MASK (0x800U) +#define GPIO_GICLR_GIWE11_SHIFT (11U) +/*! GIWE11 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE11_SHIFT)) & GPIO_GICLR_GIWE11_MASK) + +#define GPIO_GICLR_GIWE12_MASK (0x1000U) +#define GPIO_GICLR_GIWE12_SHIFT (12U) +/*! GIWE12 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE12_SHIFT)) & GPIO_GICLR_GIWE12_MASK) + +#define GPIO_GICLR_GIWE13_MASK (0x2000U) +#define GPIO_GICLR_GIWE13_SHIFT (13U) +/*! GIWE13 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE13_SHIFT)) & GPIO_GICLR_GIWE13_MASK) + +#define GPIO_GICLR_GIWE14_MASK (0x4000U) +#define GPIO_GICLR_GIWE14_SHIFT (14U) +/*! GIWE14 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE14_SHIFT)) & GPIO_GICLR_GIWE14_MASK) + +#define GPIO_GICLR_GIWE15_MASK (0x8000U) +#define GPIO_GICLR_GIWE15_SHIFT (15U) +/*! GIWE15 - Global Interrupt Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define GPIO_GICLR_GIWE15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWE15_SHIFT)) & GPIO_GICLR_GIWE15_MASK) + +#define GPIO_GICLR_GIWD_MASK (0xFFFF0000U) +#define GPIO_GICLR_GIWD_SHIFT (16U) +/*! GIWD - Global Interrupt Write Data */ +#define GPIO_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICLR_GIWD_SHIFT)) & GPIO_GICLR_GIWD_MASK) +/*! @} */ + +/*! @name GICHR - Global Interrupt Control High */ +/*! @{ */ + +#define GPIO_GICHR_GIWE16_MASK (0x1U) +#define GPIO_GICHR_GIWE16_SHIFT (0U) +/*! GIWE16 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE16_SHIFT)) & GPIO_GICHR_GIWE16_MASK) + +#define GPIO_GICHR_GIWE17_MASK (0x2U) +#define GPIO_GICHR_GIWE17_SHIFT (1U) +/*! GIWE17 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE17_SHIFT)) & GPIO_GICHR_GIWE17_MASK) + +#define GPIO_GICHR_GIWE18_MASK (0x4U) +#define GPIO_GICHR_GIWE18_SHIFT (2U) +/*! GIWE18 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE18_SHIFT)) & GPIO_GICHR_GIWE18_MASK) + +#define GPIO_GICHR_GIWE19_MASK (0x8U) +#define GPIO_GICHR_GIWE19_SHIFT (3U) +/*! GIWE19 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE19_SHIFT)) & GPIO_GICHR_GIWE19_MASK) + +#define GPIO_GICHR_GIWE20_MASK (0x10U) +#define GPIO_GICHR_GIWE20_SHIFT (4U) +/*! GIWE20 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE20_SHIFT)) & GPIO_GICHR_GIWE20_MASK) + +#define GPIO_GICHR_GIWE21_MASK (0x20U) +#define GPIO_GICHR_GIWE21_SHIFT (5U) +/*! GIWE21 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE21_SHIFT)) & GPIO_GICHR_GIWE21_MASK) + +#define GPIO_GICHR_GIWE22_MASK (0x40U) +#define GPIO_GICHR_GIWE22_SHIFT (6U) +/*! GIWE22 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE22_SHIFT)) & GPIO_GICHR_GIWE22_MASK) + +#define GPIO_GICHR_GIWE23_MASK (0x80U) +#define GPIO_GICHR_GIWE23_SHIFT (7U) +/*! GIWE23 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE23_SHIFT)) & GPIO_GICHR_GIWE23_MASK) + +#define GPIO_GICHR_GIWE24_MASK (0x100U) +#define GPIO_GICHR_GIWE24_SHIFT (8U) +/*! GIWE24 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE24_SHIFT)) & GPIO_GICHR_GIWE24_MASK) + +#define GPIO_GICHR_GIWE25_MASK (0x200U) +#define GPIO_GICHR_GIWE25_SHIFT (9U) +/*! GIWE25 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE25_SHIFT)) & GPIO_GICHR_GIWE25_MASK) + +#define GPIO_GICHR_GIWE26_MASK (0x400U) +#define GPIO_GICHR_GIWE26_SHIFT (10U) +/*! GIWE26 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE26_SHIFT)) & GPIO_GICHR_GIWE26_MASK) + +#define GPIO_GICHR_GIWE27_MASK (0x800U) +#define GPIO_GICHR_GIWE27_SHIFT (11U) +/*! GIWE27 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE27_SHIFT)) & GPIO_GICHR_GIWE27_MASK) + +#define GPIO_GICHR_GIWE28_MASK (0x1000U) +#define GPIO_GICHR_GIWE28_SHIFT (12U) +/*! GIWE28 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE28_SHIFT)) & GPIO_GICHR_GIWE28_MASK) + +#define GPIO_GICHR_GIWE29_MASK (0x2000U) +#define GPIO_GICHR_GIWE29_SHIFT (13U) +/*! GIWE29 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE29_SHIFT)) & GPIO_GICHR_GIWE29_MASK) + +#define GPIO_GICHR_GIWE30_MASK (0x4000U) +#define GPIO_GICHR_GIWE30_SHIFT (14U) +/*! GIWE30 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE30_SHIFT)) & GPIO_GICHR_GIWE30_MASK) + +#define GPIO_GICHR_GIWE31_MASK (0x8000U) +#define GPIO_GICHR_GIWE31_SHIFT (15U) +/*! GIWE31 - Global Interrupt Write Enable + * 0b0..Not updated. + * 0b1..Updated + */ +#define GPIO_GICHR_GIWE31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWE31_SHIFT)) & GPIO_GICHR_GIWE31_MASK) + +#define GPIO_GICHR_GIWD_MASK (0xFFFF0000U) +#define GPIO_GICHR_GIWD_SHIFT (16U) +/*! GIWD - Global Interrupt Write Data */ +#define GPIO_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GICHR_GIWD_SHIFT)) & GPIO_GICHR_GIWD_MASK) +/*! @} */ + +/*! @name ISFR - Interrupt Status Flag */ +/*! @{ */ + +#define GPIO_ISFR_ISF0_MASK (0x1U) +#define GPIO_ISFR_ISF0_SHIFT (0U) +/*! ISF0 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF0_SHIFT)) & GPIO_ISFR_ISF0_MASK) + +#define GPIO_ISFR_ISF1_MASK (0x2U) +#define GPIO_ISFR_ISF1_SHIFT (1U) +/*! ISF1 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF1_SHIFT)) & GPIO_ISFR_ISF1_MASK) + +#define GPIO_ISFR_ISF2_MASK (0x4U) +#define GPIO_ISFR_ISF2_SHIFT (2U) +/*! ISF2 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF2_SHIFT)) & GPIO_ISFR_ISF2_MASK) + +#define GPIO_ISFR_ISF3_MASK (0x8U) +#define GPIO_ISFR_ISF3_SHIFT (3U) +/*! ISF3 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF3_SHIFT)) & GPIO_ISFR_ISF3_MASK) + +#define GPIO_ISFR_ISF4_MASK (0x10U) +#define GPIO_ISFR_ISF4_SHIFT (4U) +/*! ISF4 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF4_SHIFT)) & GPIO_ISFR_ISF4_MASK) + +#define GPIO_ISFR_ISF5_MASK (0x20U) +#define GPIO_ISFR_ISF5_SHIFT (5U) +/*! ISF5 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF5_SHIFT)) & GPIO_ISFR_ISF5_MASK) + +#define GPIO_ISFR_ISF6_MASK (0x40U) +#define GPIO_ISFR_ISF6_SHIFT (6U) +/*! ISF6 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF6_SHIFT)) & GPIO_ISFR_ISF6_MASK) + +#define GPIO_ISFR_ISF7_MASK (0x80U) +#define GPIO_ISFR_ISF7_SHIFT (7U) +/*! ISF7 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF7_SHIFT)) & GPIO_ISFR_ISF7_MASK) + +#define GPIO_ISFR_ISF8_MASK (0x100U) +#define GPIO_ISFR_ISF8_SHIFT (8U) +/*! ISF8 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF8_SHIFT)) & GPIO_ISFR_ISF8_MASK) + +#define GPIO_ISFR_ISF9_MASK (0x200U) +#define GPIO_ISFR_ISF9_SHIFT (9U) +/*! ISF9 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF9_SHIFT)) & GPIO_ISFR_ISF9_MASK) + +#define GPIO_ISFR_ISF10_MASK (0x400U) +#define GPIO_ISFR_ISF10_SHIFT (10U) +/*! ISF10 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF10_SHIFT)) & GPIO_ISFR_ISF10_MASK) + +#define GPIO_ISFR_ISF11_MASK (0x800U) +#define GPIO_ISFR_ISF11_SHIFT (11U) +/*! ISF11 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF11_SHIFT)) & GPIO_ISFR_ISF11_MASK) + +#define GPIO_ISFR_ISF12_MASK (0x1000U) +#define GPIO_ISFR_ISF12_SHIFT (12U) +/*! ISF12 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF12_SHIFT)) & GPIO_ISFR_ISF12_MASK) + +#define GPIO_ISFR_ISF13_MASK (0x2000U) +#define GPIO_ISFR_ISF13_SHIFT (13U) +/*! ISF13 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF13_SHIFT)) & GPIO_ISFR_ISF13_MASK) + +#define GPIO_ISFR_ISF14_MASK (0x4000U) +#define GPIO_ISFR_ISF14_SHIFT (14U) +/*! ISF14 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF14_SHIFT)) & GPIO_ISFR_ISF14_MASK) + +#define GPIO_ISFR_ISF15_MASK (0x8000U) +#define GPIO_ISFR_ISF15_SHIFT (15U) +/*! ISF15 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF15_SHIFT)) & GPIO_ISFR_ISF15_MASK) + +#define GPIO_ISFR_ISF16_MASK (0x10000U) +#define GPIO_ISFR_ISF16_SHIFT (16U) +/*! ISF16 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF16_SHIFT)) & GPIO_ISFR_ISF16_MASK) + +#define GPIO_ISFR_ISF17_MASK (0x20000U) +#define GPIO_ISFR_ISF17_SHIFT (17U) +/*! ISF17 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF17_SHIFT)) & GPIO_ISFR_ISF17_MASK) + +#define GPIO_ISFR_ISF18_MASK (0x40000U) +#define GPIO_ISFR_ISF18_SHIFT (18U) +/*! ISF18 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF18_SHIFT)) & GPIO_ISFR_ISF18_MASK) + +#define GPIO_ISFR_ISF19_MASK (0x80000U) +#define GPIO_ISFR_ISF19_SHIFT (19U) +/*! ISF19 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF19_SHIFT)) & GPIO_ISFR_ISF19_MASK) + +#define GPIO_ISFR_ISF20_MASK (0x100000U) +#define GPIO_ISFR_ISF20_SHIFT (20U) +/*! ISF20 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF20_SHIFT)) & GPIO_ISFR_ISF20_MASK) + +#define GPIO_ISFR_ISF21_MASK (0x200000U) +#define GPIO_ISFR_ISF21_SHIFT (21U) +/*! ISF21 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF21_SHIFT)) & GPIO_ISFR_ISF21_MASK) + +#define GPIO_ISFR_ISF22_MASK (0x400000U) +#define GPIO_ISFR_ISF22_SHIFT (22U) +/*! ISF22 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF22_SHIFT)) & GPIO_ISFR_ISF22_MASK) + +#define GPIO_ISFR_ISF23_MASK (0x800000U) +#define GPIO_ISFR_ISF23_SHIFT (23U) +/*! ISF23 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF23_SHIFT)) & GPIO_ISFR_ISF23_MASK) + +#define GPIO_ISFR_ISF24_MASK (0x1000000U) +#define GPIO_ISFR_ISF24_SHIFT (24U) +/*! ISF24 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF24_SHIFT)) & GPIO_ISFR_ISF24_MASK) + +#define GPIO_ISFR_ISF25_MASK (0x2000000U) +#define GPIO_ISFR_ISF25_SHIFT (25U) +/*! ISF25 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF25_SHIFT)) & GPIO_ISFR_ISF25_MASK) + +#define GPIO_ISFR_ISF26_MASK (0x4000000U) +#define GPIO_ISFR_ISF26_SHIFT (26U) +/*! ISF26 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF26_SHIFT)) & GPIO_ISFR_ISF26_MASK) + +#define GPIO_ISFR_ISF27_MASK (0x8000000U) +#define GPIO_ISFR_ISF27_SHIFT (27U) +/*! ISF27 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF27_SHIFT)) & GPIO_ISFR_ISF27_MASK) + +#define GPIO_ISFR_ISF28_MASK (0x10000000U) +#define GPIO_ISFR_ISF28_SHIFT (28U) +/*! ISF28 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF28_SHIFT)) & GPIO_ISFR_ISF28_MASK) + +#define GPIO_ISFR_ISF29_MASK (0x20000000U) +#define GPIO_ISFR_ISF29_SHIFT (29U) +/*! ISF29 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF29_SHIFT)) & GPIO_ISFR_ISF29_MASK) + +#define GPIO_ISFR_ISF30_MASK (0x40000000U) +#define GPIO_ISFR_ISF30_SHIFT (30U) +/*! ISF30 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF30_SHIFT)) & GPIO_ISFR_ISF30_MASK) + +#define GPIO_ISFR_ISF31_MASK (0x80000000U) +#define GPIO_ISFR_ISF31_SHIFT (31U) +/*! ISF31 - Interrupt Status Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define GPIO_ISFR_ISF31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISFR_ISF31_SHIFT)) & GPIO_ISFR_ISF31_MASK) +/*! @} */ + +/* The count of GPIO_ISFR */ +#define GPIO_ISFR_COUNT (1U) + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO0 base address */ +#define GPIO0_BASE (0x40102000u) +/** Peripheral GPIO0 base pointer */ +#define GPIO0 ((GPIO_Type *)GPIO0_BASE) +/** Peripheral GPIO1 base address */ +#define GPIO1_BASE (0x40103000u) +/** Peripheral GPIO1 base pointer */ +#define GPIO1 ((GPIO_Type *)GPIO1_BASE) +/** Peripheral GPIO2 base address */ +#define GPIO2_BASE (0x40104000u) +/** Peripheral GPIO2 base pointer */ +#define GPIO2 ((GPIO_Type *)GPIO2_BASE) +/** Peripheral GPIO3 base address */ +#define GPIO3_BASE (0x40105000u) +/** Peripheral GPIO3 base pointer */ +#define GPIO3 ((GPIO_Type *)GPIO3_BASE) +/** Peripheral GPIO4 base address */ +#define GPIO4_BASE (0x40106000u) +/** Peripheral GPIO4 base pointer */ +#define GPIO4 ((GPIO_Type *)GPIO4_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { GPIO0_BASE, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { GPIO0, GPIO1, GPIO2, GPIO3, GPIO4 } +/** Interrupt vectors for the GPIO peripheral type */ +#define GPIO_IRQS { GPIO0_IRQn, GPIO1_IRQn, GPIO2_IRQn, GPIO3_IRQn, GPIO4_IRQn } + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I3C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I3C_Peripheral_Access_Layer I3C Peripheral Access Layer + * @{ + */ + +/** I3C - Register Layout Typedef */ +typedef struct { + __IO uint32_t MCONFIG; /**< Controller Configuration, offset: 0x0 */ + __IO uint32_t SCONFIG; /**< Target Configuration, offset: 0x4 */ + __IO uint32_t SSTATUS; /**< Target Status, offset: 0x8 */ + __IO uint32_t SCTRL; /**< Target Control, offset: 0xC */ + __IO uint32_t SINTSET; /**< Target Interrupt Set, offset: 0x10 */ + __IO uint32_t SINTCLR; /**< Target Interrupt Clear, offset: 0x14 */ + __I uint32_t SINTMASKED; /**< Target Interrupt Mask, offset: 0x18 */ + __IO uint32_t SERRWARN; /**< Target Errors and Warnings, offset: 0x1C */ + __IO uint32_t SDMACTRL; /**< Target DMA Control, offset: 0x20 */ + uint8_t RESERVED_0[8]; + __IO uint32_t SDATACTRL; /**< Target Data Control, offset: 0x2C */ + __O uint32_t SWDATAB; /**< Target Write Data Byte, offset: 0x30 */ + __O uint32_t SWDATABE; /**< Target Write Data Byte End, offset: 0x34 */ + __O uint32_t SWDATAH; /**< Target Write Data Halfword, offset: 0x38 */ + __O uint32_t SWDATAHE; /**< Target Write Data Halfword End, offset: 0x3C */ + __I uint32_t SRDATAB; /**< Target Read Data Byte, offset: 0x40 */ + uint8_t RESERVED_1[4]; + __I uint32_t SRDATAH; /**< Target Read Data Halfword, offset: 0x48 */ + uint8_t RESERVED_2[8]; + union { /* offset: 0x54 */ + __O uint32_t SWDATAB1; /**< Target Write Data Byte, offset: 0x54 */ + __O uint32_t SWDATAH1; /**< Target Write Data Halfword, offset: 0x54 */ + }; + uint8_t RESERVED_3[4]; + __I uint32_t SCAPABILITIES2; /**< Target Capabilities 2, offset: 0x5C */ + __I uint32_t SCAPABILITIES; /**< Target Capabilities, offset: 0x60 */ + __IO uint32_t SDYNADDR; /**< Target Dynamic Address, offset: 0x64 */ + __IO uint32_t SMAXLIMITS; /**< Target Maximum Limits, offset: 0x68 */ + __IO uint32_t SIDPARTNO; /**< Target ID Part Number, offset: 0x6C */ + __IO uint32_t SIDEXT; /**< Target ID Extension, offset: 0x70 */ + __IO uint32_t SVENDORID; /**< Target Vendor ID, offset: 0x74 */ + __IO uint32_t STCCLOCK; /**< Target Time Control Clock, offset: 0x78 */ + __I uint32_t SMSGMAPADDR; /**< Target Message Map Address, offset: 0x7C */ + __IO uint32_t MCONFIG_EXT; /**< Controller Extended Configuration, offset: 0x80 */ + __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ + __IO uint32_t MSTATUS; /**< Controller Status, offset: 0x88 */ + __IO uint32_t MIBIRULES; /**< Controller In-band Interrupt Registry and Rules, offset: 0x8C */ + __IO uint32_t MINTSET; /**< Controller Interrupt Set, offset: 0x90 */ + __IO uint32_t MINTCLR; /**< Controller Interrupt Clear, offset: 0x94 */ + __I uint32_t MINTMASKED; /**< Controller Interrupt Mask, offset: 0x98 */ + __IO uint32_t MERRWARN; /**< Controller Errors and Warnings, offset: 0x9C */ + __IO uint32_t MDMACTRL; /**< Controller DMA Control, offset: 0xA0 */ + uint8_t RESERVED_4[8]; + __IO uint32_t MDATACTRL; /**< Controller Data Control, offset: 0xAC */ + __O uint32_t MWDATAB; /**< Controller Write Data Byte, offset: 0xB0 */ + __O uint32_t MWDATABE; /**< Controller Write Data Byte End, offset: 0xB4 */ + __O uint32_t MWDATAH; /**< Controller Write Data Halfword, offset: 0xB8 */ + __O uint32_t MWDATAHE; /**< Controller Write Data Halfword End, offset: 0xBC */ + __I uint32_t MRDATAB; /**< Controller Read Data Byte, offset: 0xC0 */ + uint8_t RESERVED_5[4]; + __I uint32_t MRDATAH; /**< Controller Read Data Halfword, offset: 0xC8 */ + union { /* offset: 0xCC */ + __O uint32_t MWDATAB1; /**< Controller Write Byte Data 1 (to Bus), offset: 0xCC */ + __O uint32_t MWDATAH1; /**< Controller Write Halfword Data (to Bus), offset: 0xCC */ + }; + union { /* offset: 0xD0 */ + __O uint32_t MWMSG_SDR_CONTROL; /**< Controller Write Message Control in SDR mode, offset: 0xD0 */ + __O uint32_t MWMSG_SDR_DATA; /**< Controller Write Message Data in SDR mode, offset: 0xD0 */ + }; + __I uint32_t MRMSG_SDR; /**< Controller Read Message in SDR mode, offset: 0xD4 */ + union { /* offset: 0xD8 */ + __O uint32_t MWMSG_DDR_CONTROL; /**< Controller Write Message in DDR mode: First Control Word, offset: 0xD8 */ + __O uint32_t MWMSG_DDR_CONTROL2; /**< Controller Write Message in DDR Mode Control 2, offset: 0xD8 */ + __O uint32_t MWMSG_DDR_DATA; /**< Controller Write Message Data in DDR mode, offset: 0xD8 */ + }; + __I uint32_t MRMSG_DDR; /**< Controller Read Message in DDR mode, offset: 0xDC */ + uint8_t RESERVED_6[4]; + __IO uint32_t MDYNADDR; /**< Controller Dynamic Address, offset: 0xE4 */ + uint8_t RESERVED_7[52]; + __I uint32_t SMAPCTRL0; /**< Map Feature Control 0, offset: 0x11C */ + uint8_t RESERVED_8[32]; + __IO uint32_t IBIEXT1; /**< Extended IBI Data 1, offset: 0x140 */ + __IO uint32_t IBIEXT2; /**< Extended IBI Data 2, offset: 0x144 */ + uint8_t RESERVED_9[3764]; + __I uint32_t SID; /**< Target Module ID, offset: 0xFFC */ +} I3C_Type; + +/* ---------------------------------------------------------------------------- + -- I3C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I3C_Register_Masks I3C Register Masks + * @{ + */ + +/*! @name MCONFIG - Controller Configuration */ +/*! @{ */ + +#define I3C_MCONFIG_MSTENA_MASK (0x3U) +#define I3C_MCONFIG_MSTENA_SHIFT (0U) +/*! MSTENA - Controller Enable + * 0b00..CONTROLLER_OFF + * 0b01..CONTROLLER_ON + * 0b10..CONTROLLER_CAPABLE + * 0b11..I2C_CONTROLLER_MODE + */ +#define I3C_MCONFIG_MSTENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_MSTENA_SHIFT)) & I3C_MCONFIG_MSTENA_MASK) + +#define I3C_MCONFIG_DISTO_MASK (0x8U) +#define I3C_MCONFIG_DISTO_SHIFT (3U) +/*! DISTO - Disable Timeout + * 0b1..Disabled, if configured + * 0b0..Enabled + */ +#define I3C_MCONFIG_DISTO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_DISTO_SHIFT)) & I3C_MCONFIG_DISTO_MASK) + +#define I3C_MCONFIG_HKEEP_MASK (0x30U) +#define I3C_MCONFIG_HKEEP_SHIFT (4U) +/*! HKEEP - High-Keeper + * 0b00..None + * 0b01..WIRED_IN + * 0b10..PASSIVE_SDA + * 0b11..PASSIVE_ON_SDA_SCL + */ +#define I3C_MCONFIG_HKEEP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_HKEEP_SHIFT)) & I3C_MCONFIG_HKEEP_MASK) + +#define I3C_MCONFIG_ODSTOP_MASK (0x40U) +#define I3C_MCONFIG_ODSTOP_SHIFT (6U) +/*! ODSTOP - Open Drain Stop + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MCONFIG_ODSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODSTOP_SHIFT)) & I3C_MCONFIG_ODSTOP_MASK) + +#define I3C_MCONFIG_PPBAUD_MASK (0xF00U) +#define I3C_MCONFIG_PPBAUD_SHIFT (8U) +/*! PPBAUD - Push-Pull Baud Rate */ +#define I3C_MCONFIG_PPBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPBAUD_SHIFT)) & I3C_MCONFIG_PPBAUD_MASK) + +#define I3C_MCONFIG_PPLOW_MASK (0xF000U) +#define I3C_MCONFIG_PPLOW_SHIFT (12U) +/*! PPLOW - Push-Pull Low */ +#define I3C_MCONFIG_PPLOW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_PPLOW_SHIFT)) & I3C_MCONFIG_PPLOW_MASK) + +#define I3C_MCONFIG_ODBAUD_MASK (0xFF0000U) +#define I3C_MCONFIG_ODBAUD_SHIFT (16U) +/*! ODBAUD - Open Drain Baud Rate */ +#define I3C_MCONFIG_ODBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODBAUD_SHIFT)) & I3C_MCONFIG_ODBAUD_MASK) + +#define I3C_MCONFIG_ODHPP_MASK (0x1000000U) +#define I3C_MCONFIG_ODHPP_SHIFT (24U) +/*! ODHPP - Open Drain High Push-Pull + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MCONFIG_ODHPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_ODHPP_SHIFT)) & I3C_MCONFIG_ODHPP_MASK) + +#define I3C_MCONFIG_SKEW_MASK (0xE000000U) +#define I3C_MCONFIG_SKEW_SHIFT (25U) +/*! SKEW - Skew */ +#define I3C_MCONFIG_SKEW(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_SKEW_SHIFT)) & I3C_MCONFIG_SKEW_MASK) + +#define I3C_MCONFIG_I2CBAUD_MASK (0xF0000000U) +#define I3C_MCONFIG_I2CBAUD_SHIFT (28U) +/*! I2CBAUD - I2C Baud Rate */ +#define I3C_MCONFIG_I2CBAUD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_I2CBAUD_SHIFT)) & I3C_MCONFIG_I2CBAUD_MASK) +/*! @} */ + +/*! @name SCONFIG - Target Configuration */ +/*! @{ */ + +#define I3C_SCONFIG_SLVENA_MASK (0x1U) +#define I3C_SCONFIG_SLVENA_SHIFT (0U) +/*! SLVENA - Target Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SCONFIG_SLVENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SLVENA_SHIFT)) & I3C_SCONFIG_SLVENA_MASK) + +#define I3C_SCONFIG_NACK_MASK (0x2U) +#define I3C_SCONFIG_NACK_SHIFT (1U) +/*! NACK - Not Acknowledge + * 0b1..Always enable NACK mode (works normally) + * 0b0..Always disable NACK mode + */ +#define I3C_SCONFIG_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_NACK_SHIFT)) & I3C_SCONFIG_NACK_MASK) + +#define I3C_SCONFIG_MATCHSS_MASK (0x4U) +#define I3C_SCONFIG_MATCHSS_SHIFT (2U) +/*! MATCHSS - Match Start or Stop + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SCONFIG_MATCHSS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_MATCHSS_SHIFT)) & I3C_SCONFIG_MATCHSS_MASK) + +#define I3C_SCONFIG_S0IGNORE_MASK (0x8U) +#define I3C_SCONFIG_S0IGNORE_SHIFT (3U) +/*! S0IGNORE - Ignore TE0 or TE1 Errors + * 0b1..Ignore TE0 or TE1 errors + * 0b0..Do not ignore TE0 or TE1 errors + */ +#define I3C_SCONFIG_S0IGNORE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_S0IGNORE_SHIFT)) & I3C_SCONFIG_S0IGNORE_MASK) + +#define I3C_SCONFIG_HDROK_MASK (0x10U) +#define I3C_SCONFIG_HDROK_SHIFT (4U) +/*! HDROK - HDR OK + * 0b1..Enable HDR OK + * 0b0..Disable HDR OK + */ +#define I3C_SCONFIG_HDROK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_HDROK_SHIFT)) & I3C_SCONFIG_HDROK_MASK) + +#define I3C_SCONFIG_OFFLINE_MASK (0x200U) +#define I3C_SCONFIG_OFFLINE_SHIFT (9U) +/*! OFFLINE - Offline + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SCONFIG_OFFLINE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_OFFLINE_SHIFT)) & I3C_SCONFIG_OFFLINE_MASK) + +#define I3C_SCONFIG_BAMATCH_MASK (0xFF0000U) +#define I3C_SCONFIG_BAMATCH_SHIFT (16U) +/*! BAMATCH - Bus Available Match */ +#define I3C_SCONFIG_BAMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_BAMATCH_SHIFT)) & I3C_SCONFIG_BAMATCH_MASK) + +#define I3C_SCONFIG_SADDR_MASK (0xFE000000U) +#define I3C_SCONFIG_SADDR_SHIFT (25U) +/*! SADDR - Static Address */ +#define I3C_SCONFIG_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCONFIG_SADDR_SHIFT)) & I3C_SCONFIG_SADDR_MASK) +/*! @} */ + +/*! @name SSTATUS - Target Status */ +/*! @{ */ + +#define I3C_SSTATUS_STNOTSTOP_MASK (0x1U) +#define I3C_SSTATUS_STNOTSTOP_SHIFT (0U) +/*! STNOTSTOP - Status not Stop + * 0b1..Busy + * 0b0..In STOP condition + */ +#define I3C_SSTATUS_STNOTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STNOTSTOP_SHIFT)) & I3C_SSTATUS_STNOTSTOP_MASK) + +#define I3C_SSTATUS_STMSG_MASK (0x2U) +#define I3C_SSTATUS_STMSG_SHIFT (1U) +/*! STMSG - Status Message + * 0b1..Busy + * 0b0..Idle + */ +#define I3C_SSTATUS_STMSG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STMSG_SHIFT)) & I3C_SSTATUS_STMSG_MASK) + +#define I3C_SSTATUS_STCCCH_MASK (0x4U) +#define I3C_SSTATUS_STCCCH_SHIFT (2U) +/*! STCCCH - Status Common Command Code Handler + * 0b1..Handled automatically + * 0b0..No CCC message handled + */ +#define I3C_SSTATUS_STCCCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STCCCH_SHIFT)) & I3C_SSTATUS_STCCCH_MASK) + +#define I3C_SSTATUS_STREQRD_MASK (0x8U) +#define I3C_SSTATUS_STREQRD_SHIFT (3U) +/*! STREQRD - Status Request Read + * 0b1..SDR read from this target or an IBI is being pushed out + * 0b0..Not an SDR read + */ +#define I3C_SSTATUS_STREQRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQRD_SHIFT)) & I3C_SSTATUS_STREQRD_MASK) + +#define I3C_SSTATUS_STREQWR_MASK (0x10U) +#define I3C_SSTATUS_STREQWR_SHIFT (4U) +/*! STREQWR - Status Request Write + * 0b1..SDR write data from the controller, but not in ENTDAA mode + * 0b0..Not an SDR write + */ +#define I3C_SSTATUS_STREQWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STREQWR_SHIFT)) & I3C_SSTATUS_STREQWR_MASK) + +#define I3C_SSTATUS_STDAA_MASK (0x20U) +#define I3C_SSTATUS_STDAA_SHIFT (5U) +/*! STDAA - Status Dynamic Address Assignment + * 0b1..In ENTDAA mode + * 0b0..Not in ENTDAA mode + */ +#define I3C_SSTATUS_STDAA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STDAA_SHIFT)) & I3C_SSTATUS_STDAA_MASK) + +#define I3C_SSTATUS_STHDR_MASK (0x40U) +#define I3C_SSTATUS_STHDR_SHIFT (6U) +/*! STHDR - Status High Data Rate + * 0b1..I3C bus in HDR-DDR mode + * 0b0..I3C bus not in HDR-DDR mode + */ +#define I3C_SSTATUS_STHDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STHDR_SHIFT)) & I3C_SSTATUS_STHDR_MASK) + +#define I3C_SSTATUS_START_MASK (0x100U) +#define I3C_SSTATUS_START_SHIFT (8U) +/*! START - Start + * 0b1..Detected + * 0b0..Not detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_START_SHIFT)) & I3C_SSTATUS_START_MASK) + +#define I3C_SSTATUS_MATCHED_MASK (0x200U) +#define I3C_SSTATUS_MATCHED_SHIFT (9U) +/*! MATCHED - Matched + * 0b1..Header matched + * 0b0..Header not matched + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MATCHED_SHIFT)) & I3C_SSTATUS_MATCHED_MASK) + +#define I3C_SSTATUS_STOP_MASK (0x400U) +#define I3C_SSTATUS_STOP_SHIFT (10U) +/*! STOP - Stop + * 0b1..Stopped state detected + * 0b0..No Stopped state detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_STOP_SHIFT)) & I3C_SSTATUS_STOP_MASK) + +#define I3C_SSTATUS_RX_PEND_MASK (0x800U) +#define I3C_SSTATUS_RX_PEND_SHIFT (11U) +/*! RX_PEND - Received Message Pending + * 0b1..Received message pending + * 0b0..No received message pending + */ +#define I3C_SSTATUS_RX_PEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_RX_PEND_SHIFT)) & I3C_SSTATUS_RX_PEND_MASK) + +#define I3C_SSTATUS_TXNOTFULL_MASK (0x1000U) +#define I3C_SSTATUS_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - Transmit Buffer Not Full + * 0b1..Transmit buffer not full + * 0b0..Transmit buffer full + */ +#define I3C_SSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TXNOTFULL_SHIFT)) & I3C_SSTATUS_TXNOTFULL_MASK) + +#define I3C_SSTATUS_DACHG_MASK (0x2000U) +#define I3C_SSTATUS_DACHG_SHIFT (13U) +/*! DACHG - Dynamic Address Change + * 0b1..DA change detected + * 0b0..No DA change detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_DACHG_SHIFT)) & I3C_SSTATUS_DACHG_MASK) + +#define I3C_SSTATUS_CCC_MASK (0x4000U) +#define I3C_SSTATUS_CCC_SHIFT (14U) +/*! CCC - Common Command Code + * 0b1..CCC received + * 0b0..CCC not received + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CCC_SHIFT)) & I3C_SSTATUS_CCC_MASK) + +#define I3C_SSTATUS_ERRWARN_MASK (0x8000U) +#define I3C_SSTATUS_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error Warning */ +#define I3C_SSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ERRWARN_SHIFT)) & I3C_SSTATUS_ERRWARN_MASK) + +#define I3C_SSTATUS_HDRMATCH_MASK (0x10000U) +#define I3C_SSTATUS_HDRMATCH_SHIFT (16U) +/*! HDRMATCH - High Data Rate Command Match + * 0b1..Matched the I3C dynamic address + * 0b0..Did not match + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_HDRMATCH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HDRMATCH_SHIFT)) & I3C_SSTATUS_HDRMATCH_MASK) + +#define I3C_SSTATUS_CHANDLED_MASK (0x20000U) +#define I3C_SSTATUS_CHANDLED_SHIFT (17U) +/*! CHANDLED - Common Command Code Handled + * 0b1..CCC handling in progress + * 0b0..CCC handling not in progress + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_CHANDLED_SHIFT)) & I3C_SSTATUS_CHANDLED_MASK) + +#define I3C_SSTATUS_EVENT_MASK (0x40000U) +#define I3C_SSTATUS_EVENT_SHIFT (18U) +/*! EVENT - Event + * 0b1..IBI, CR, or HJ occurred + * 0b0..No event occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SSTATUS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVENT_SHIFT)) & I3C_SSTATUS_EVENT_MASK) + +#define I3C_SSTATUS_EVDET_MASK (0x300000U) +#define I3C_SSTATUS_EVDET_SHIFT (20U) +/*! EVDET - Event Details + * 0b00..NONE (no event or no pending event) + * 0b01..NO_REQUEST (request is not sent yet; either there is no START condition yet, or is waiting for Bus-Available or Bus-Idle (HJ)) + * 0b10..NACKed (not acknowledged, request sent and rejected); I3C tries again + * 0b11..ACKed (acknowledged; request sent and accepted), so done (unless the time control data is still being sent) + */ +#define I3C_SSTATUS_EVDET(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_EVDET_SHIFT)) & I3C_SSTATUS_EVDET_MASK) + +#define I3C_SSTATUS_IBIDIS_MASK (0x1000000U) +#define I3C_SSTATUS_IBIDIS_SHIFT (24U) +/*! IBIDIS - In-Band Interrupts Disable + * 0b1..Disabled + * 0b0..Enabled + */ +#define I3C_SSTATUS_IBIDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_IBIDIS_SHIFT)) & I3C_SSTATUS_IBIDIS_MASK) + +#define I3C_SSTATUS_MRDIS_MASK (0x2000000U) +#define I3C_SSTATUS_MRDIS_SHIFT (25U) +/*! MRDIS - Controller Requests Disable + * 0b1..Disabled + * 0b0..Enabled + */ +#define I3C_SSTATUS_MRDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_MRDIS_SHIFT)) & I3C_SSTATUS_MRDIS_MASK) + +#define I3C_SSTATUS_HJDIS_MASK (0x8000000U) +#define I3C_SSTATUS_HJDIS_SHIFT (27U) +/*! HJDIS - Hot-Join Disabled + * 0b1..Disabled + * 0b0..Enabled + */ +#define I3C_SSTATUS_HJDIS(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_HJDIS_SHIFT)) & I3C_SSTATUS_HJDIS_MASK) + +#define I3C_SSTATUS_ACTSTATE_MASK (0x30000000U) +#define I3C_SSTATUS_ACTSTATE_SHIFT (28U) +/*! ACTSTATE - Activity State from Common Command Codes (CCC) + * 0b00..NO_LATENCY (normal bus operations) + * 0b01..LATENCY_1MS (1 ms of latency) + * 0b10..LATENCY_100MS (100 ms of latency) + * 0b11..LATENCY_10S (10 seconds of latency) + */ +#define I3C_SSTATUS_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_ACTSTATE_SHIFT)) & I3C_SSTATUS_ACTSTATE_MASK) + +#define I3C_SSTATUS_TIMECTRL_MASK (0xC0000000U) +#define I3C_SSTATUS_TIMECTRL_SHIFT (30U) +/*! TIMECTRL - Time Control + * 0b00..NO_TIME_CONTROL (no time control is enabled) + * 0b01..SYNC_MODE (Synchronous mode is enabled) + * 0b10..ASYNC_MODE (Asynchronous standard mode (0 or 1) is enabled) + * 0b11..BOTHSYNCASYNC (both Synchronous and Asynchronous modes are enabled) + */ +#define I3C_SSTATUS_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SSTATUS_TIMECTRL_SHIFT)) & I3C_SSTATUS_TIMECTRL_MASK) +/*! @} */ + +/*! @name SCTRL - Target Control */ +/*! @{ */ + +#define I3C_SCTRL_EVENT_MASK (0x3U) +#define I3C_SCTRL_EVENT_SHIFT (0U) +/*! EVENT - Event + * 0b00..NORMAL_MODE + * 0b01..IBI + * 0b10..CONTROLLER_REQUEST + * 0b11..HOT_JOIN_REQUEST + */ +#define I3C_SCTRL_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EVENT_SHIFT)) & I3C_SCTRL_EVENT_MASK) + +#define I3C_SCTRL_EXTDATA_MASK (0x8U) +#define I3C_SCTRL_EXTDATA_SHIFT (3U) +/*! EXTDATA - Extended Data + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SCTRL_EXTDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_EXTDATA_SHIFT)) & I3C_SCTRL_EXTDATA_MASK) + +#define I3C_SCTRL_IBIDATA_MASK (0xFF00U) +#define I3C_SCTRL_IBIDATA_SHIFT (8U) +/*! IBIDATA - In-Band Interrupt Data */ +#define I3C_SCTRL_IBIDATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_IBIDATA_SHIFT)) & I3C_SCTRL_IBIDATA_MASK) + +#define I3C_SCTRL_PENDINT_MASK (0xF0000U) +#define I3C_SCTRL_PENDINT_SHIFT (16U) +/*! PENDINT - Pending Interrupt */ +#define I3C_SCTRL_PENDINT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_PENDINT_SHIFT)) & I3C_SCTRL_PENDINT_MASK) + +#define I3C_SCTRL_ACTSTATE_MASK (0x300000U) +#define I3C_SCTRL_ACTSTATE_SHIFT (20U) +/*! ACTSTATE - Activity State of Target */ +#define I3C_SCTRL_ACTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_ACTSTATE_SHIFT)) & I3C_SCTRL_ACTSTATE_MASK) + +#define I3C_SCTRL_VENDINFO_MASK (0xFF000000U) +#define I3C_SCTRL_VENDINFO_SHIFT (24U) +/*! VENDINFO - Vendor Information */ +#define I3C_SCTRL_VENDINFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCTRL_VENDINFO_SHIFT)) & I3C_SCTRL_VENDINFO_MASK) +/*! @} */ + +/*! @name SINTSET - Target Interrupt Set */ +/*! @{ */ + +#define I3C_SINTSET_START_MASK (0x100U) +#define I3C_SINTSET_START_SHIFT (8U) +/*! START - Start Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_START_SHIFT)) & I3C_SINTSET_START_MASK) + +#define I3C_SINTSET_MATCHED_MASK (0x200U) +#define I3C_SINTSET_MATCHED_SHIFT (9U) +/*! MATCHED - Match Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_MATCHED_SHIFT)) & I3C_SINTSET_MATCHED_MASK) + +#define I3C_SINTSET_STOP_MASK (0x400U) +#define I3C_SINTSET_STOP_SHIFT (10U) +/*! STOP - Stop Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_STOP_SHIFT)) & I3C_SINTSET_STOP_MASK) + +#define I3C_SINTSET_RXPEND_MASK (0x800U) +#define I3C_SINTSET_RXPEND_SHIFT (11U) +/*! RXPEND - Receive Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_RXPEND_SHIFT)) & I3C_SINTSET_RXPEND_MASK) + +#define I3C_SINTSET_TXSEND_MASK (0x1000U) +#define I3C_SINTSET_TXSEND_SHIFT (12U) +/*! TXSEND - Transmit Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_TXSEND_SHIFT)) & I3C_SINTSET_TXSEND_MASK) + +#define I3C_SINTSET_DACHG_MASK (0x2000U) +#define I3C_SINTSET_DACHG_SHIFT (13U) +/*! DACHG - Dynamic Address Change Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DACHG_SHIFT)) & I3C_SINTSET_DACHG_MASK) + +#define I3C_SINTSET_CCC_MASK (0x4000U) +#define I3C_SINTSET_CCC_SHIFT (14U) +/*! CCC - Common Command Code (CCC) Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CCC_SHIFT)) & I3C_SINTSET_CCC_MASK) + +#define I3C_SINTSET_ERRWARN_MASK (0x8000U) +#define I3C_SINTSET_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error or Warning Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_ERRWARN_SHIFT)) & I3C_SINTSET_ERRWARN_MASK) + +#define I3C_SINTSET_DDRMATCHED_MASK (0x10000U) +#define I3C_SINTSET_DDRMATCHED_SHIFT (16U) +/*! DDRMATCHED - Double Data Rate Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_DDRMATCHED_SHIFT)) & I3C_SINTSET_DDRMATCHED_MASK) + +#define I3C_SINTSET_CHANDLED_MASK (0x20000U) +#define I3C_SINTSET_CHANDLED_SHIFT (17U) +/*! CHANDLED - Common Command Code (CCC) Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_CHANDLED_SHIFT)) & I3C_SINTSET_CHANDLED_MASK) + +#define I3C_SINTSET_EVENT_MASK (0x40000U) +#define I3C_SINTSET_EVENT_SHIFT (18U) +/*! EVENT - Event Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_SINTSET_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTSET_EVENT_SHIFT)) & I3C_SINTSET_EVENT_MASK) +/*! @} */ + +/*! @name SINTCLR - Target Interrupt Clear */ +/*! @{ */ + +#define I3C_SINTCLR_START_MASK (0x100U) +#define I3C_SINTCLR_START_SHIFT (8U) +/*! START - START Interrupt Enable Clear */ +#define I3C_SINTCLR_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_START_SHIFT)) & I3C_SINTCLR_START_MASK) + +#define I3C_SINTCLR_MATCHED_MASK (0x200U) +#define I3C_SINTCLR_MATCHED_SHIFT (9U) +/*! MATCHED - Matched Interrupt Enable Clear */ +#define I3C_SINTCLR_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_MATCHED_SHIFT)) & I3C_SINTCLR_MATCHED_MASK) + +#define I3C_SINTCLR_STOP_MASK (0x400U) +#define I3C_SINTCLR_STOP_SHIFT (10U) +/*! STOP - STOP Interrupt Enable Clear */ +#define I3C_SINTCLR_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_STOP_SHIFT)) & I3C_SINTCLR_STOP_MASK) + +#define I3C_SINTCLR_RXPEND_MASK (0x800U) +#define I3C_SINTCLR_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Enable Clear */ +#define I3C_SINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_RXPEND_SHIFT)) & I3C_SINTCLR_RXPEND_MASK) + +#define I3C_SINTCLR_TXSEND_MASK (0x1000U) +#define I3C_SINTCLR_TXSEND_SHIFT (12U) +/*! TXSEND - TXSEND Interrupt Enable Clear */ +#define I3C_SINTCLR_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_TXSEND_SHIFT)) & I3C_SINTCLR_TXSEND_MASK) + +#define I3C_SINTCLR_DACHG_MASK (0x2000U) +#define I3C_SINTCLR_DACHG_SHIFT (13U) +/*! DACHG - DACHG Interrupt Enable Clear */ +#define I3C_SINTCLR_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DACHG_SHIFT)) & I3C_SINTCLR_DACHG_MASK) + +#define I3C_SINTCLR_CCC_MASK (0x4000U) +#define I3C_SINTCLR_CCC_SHIFT (14U) +/*! CCC - CCC Interrupt Enable Clear */ +#define I3C_SINTCLR_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CCC_SHIFT)) & I3C_SINTCLR_CCC_MASK) + +#define I3C_SINTCLR_ERRWARN_MASK (0x8000U) +#define I3C_SINTCLR_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Enable Clear */ +#define I3C_SINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_ERRWARN_SHIFT)) & I3C_SINTCLR_ERRWARN_MASK) + +#define I3C_SINTCLR_DDRMATCHED_MASK (0x10000U) +#define I3C_SINTCLR_DDRMATCHED_SHIFT (16U) +/*! DDRMATCHED - DDRMATCHED Interrupt Enable Clear */ +#define I3C_SINTCLR_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_DDRMATCHED_SHIFT)) & I3C_SINTCLR_DDRMATCHED_MASK) + +#define I3C_SINTCLR_CHANDLED_MASK (0x20000U) +#define I3C_SINTCLR_CHANDLED_SHIFT (17U) +/*! CHANDLED - CHANDLED Interrupt Enable Clear */ +#define I3C_SINTCLR_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_CHANDLED_SHIFT)) & I3C_SINTCLR_CHANDLED_MASK) + +#define I3C_SINTCLR_EVENT_MASK (0x40000U) +#define I3C_SINTCLR_EVENT_SHIFT (18U) +/*! EVENT - EVENT Interrupt Enable Clear */ +#define I3C_SINTCLR_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTCLR_EVENT_SHIFT)) & I3C_SINTCLR_EVENT_MASK) +/*! @} */ + +/*! @name SINTMASKED - Target Interrupt Mask */ +/*! @{ */ + +#define I3C_SINTMASKED_START_MASK (0x100U) +#define I3C_SINTMASKED_START_SHIFT (8U) +/*! START - START Interrupt Mask */ +#define I3C_SINTMASKED_START(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_START_SHIFT)) & I3C_SINTMASKED_START_MASK) + +#define I3C_SINTMASKED_MATCHED_MASK (0x200U) +#define I3C_SINTMASKED_MATCHED_SHIFT (9U) +/*! MATCHED - MATCHED Interrupt Mask */ +#define I3C_SINTMASKED_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_MATCHED_SHIFT)) & I3C_SINTMASKED_MATCHED_MASK) + +#define I3C_SINTMASKED_STOP_MASK (0x400U) +#define I3C_SINTMASKED_STOP_SHIFT (10U) +/*! STOP - STOP Interrupt Mask */ +#define I3C_SINTMASKED_STOP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_STOP_SHIFT)) & I3C_SINTMASKED_STOP_MASK) + +#define I3C_SINTMASKED_RXPEND_MASK (0x800U) +#define I3C_SINTMASKED_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Mask */ +#define I3C_SINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_RXPEND_SHIFT)) & I3C_SINTMASKED_RXPEND_MASK) + +#define I3C_SINTMASKED_TXSEND_MASK (0x1000U) +#define I3C_SINTMASKED_TXSEND_SHIFT (12U) +/*! TXSEND - TXSEND Interrupt Mask */ +#define I3C_SINTMASKED_TXSEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_TXSEND_SHIFT)) & I3C_SINTMASKED_TXSEND_MASK) + +#define I3C_SINTMASKED_DACHG_MASK (0x2000U) +#define I3C_SINTMASKED_DACHG_SHIFT (13U) +/*! DACHG - DACHG Interrupt Mask */ +#define I3C_SINTMASKED_DACHG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DACHG_SHIFT)) & I3C_SINTMASKED_DACHG_MASK) + +#define I3C_SINTMASKED_CCC_MASK (0x4000U) +#define I3C_SINTMASKED_CCC_SHIFT (14U) +/*! CCC - CCC Interrupt Mask */ +#define I3C_SINTMASKED_CCC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CCC_SHIFT)) & I3C_SINTMASKED_CCC_MASK) + +#define I3C_SINTMASKED_ERRWARN_MASK (0x8000U) +#define I3C_SINTMASKED_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Mask */ +#define I3C_SINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_ERRWARN_SHIFT)) & I3C_SINTMASKED_ERRWARN_MASK) + +#define I3C_SINTMASKED_DDRMATCHED_MASK (0x10000U) +#define I3C_SINTMASKED_DDRMATCHED_SHIFT (16U) +/*! DDRMATCHED - DDRMATCHED Interrupt Mask */ +#define I3C_SINTMASKED_DDRMATCHED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_DDRMATCHED_SHIFT)) & I3C_SINTMASKED_DDRMATCHED_MASK) + +#define I3C_SINTMASKED_CHANDLED_MASK (0x20000U) +#define I3C_SINTMASKED_CHANDLED_SHIFT (17U) +/*! CHANDLED - CHANDLED Interrupt Mask */ +#define I3C_SINTMASKED_CHANDLED(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_CHANDLED_SHIFT)) & I3C_SINTMASKED_CHANDLED_MASK) + +#define I3C_SINTMASKED_EVENT_MASK (0x40000U) +#define I3C_SINTMASKED_EVENT_SHIFT (18U) +/*! EVENT - EVENT Interrupt Mask */ +#define I3C_SINTMASKED_EVENT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SINTMASKED_EVENT_SHIFT)) & I3C_SINTMASKED_EVENT_MASK) +/*! @} */ + +/*! @name SERRWARN - Target Errors and Warnings */ +/*! @{ */ + +#define I3C_SERRWARN_ORUN_MASK (0x1U) +#define I3C_SERRWARN_ORUN_SHIFT (0U) +/*! ORUN - Overrun Error + * 0b1..Overrun error + * 0b0..No overrun error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_ORUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_ORUN_SHIFT)) & I3C_SERRWARN_ORUN_MASK) + +#define I3C_SERRWARN_URUN_MASK (0x2U) +#define I3C_SERRWARN_URUN_SHIFT (1U) +/*! URUN - Underrun Error + * 0b1..Underrun error + * 0b0..No underrun error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUN_SHIFT)) & I3C_SERRWARN_URUN_MASK) + +#define I3C_SERRWARN_URUNNACK_MASK (0x4U) +#define I3C_SERRWARN_URUNNACK_SHIFT (2U) +/*! URUNNACK - Underrun and Not Acknowledged (NACKed) Error + * 0b1..Underrun; not acknowledged error + * 0b0..No underrun; not acknowledged error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_URUNNACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_URUNNACK_SHIFT)) & I3C_SERRWARN_URUNNACK_MASK) + +#define I3C_SERRWARN_TERM_MASK (0x8U) +#define I3C_SERRWARN_TERM_SHIFT (3U) +/*! TERM - Terminated Error + * 0b1..Terminated error + * 0b0..No terminated error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_TERM_SHIFT)) & I3C_SERRWARN_TERM_MASK) + +#define I3C_SERRWARN_INVSTART_MASK (0x10U) +#define I3C_SERRWARN_INVSTART_SHIFT (4U) +/*! INVSTART - Invalid Start Error + * 0b1..Invalid start error + * 0b0..No invalid start error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_INVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_INVSTART_SHIFT)) & I3C_SERRWARN_INVSTART_MASK) + +#define I3C_SERRWARN_SPAR_MASK (0x100U) +#define I3C_SERRWARN_SPAR_SHIFT (8U) +/*! SPAR - SDR Parity Error + * 0b1..SDR parity error + * 0b0..No SDR parity error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_SPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_SPAR_SHIFT)) & I3C_SERRWARN_SPAR_MASK) + +#define I3C_SERRWARN_HPAR_MASK (0x200U) +#define I3C_SERRWARN_HPAR_SHIFT (9U) +/*! HPAR - HDR Parity Error + * 0b1..HDR parity error + * 0b0..No HDR parity error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HPAR_SHIFT)) & I3C_SERRWARN_HPAR_MASK) + +#define I3C_SERRWARN_HCRC_MASK (0x400U) +#define I3C_SERRWARN_HCRC_SHIFT (10U) +/*! HCRC - HDR-DDR CRC Error + * 0b1..HDR-DDR CRC error occurred + * 0b0..No HDR-DDR CRC error occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_HCRC_SHIFT)) & I3C_SERRWARN_HCRC_MASK) + +#define I3C_SERRWARN_S0S1_MASK (0x800U) +#define I3C_SERRWARN_S0S1_SHIFT (11U) +/*! S0S1 - TE0 or TE1 Error + * 0b1..TE0 or TE1 error occurred + * 0b0..No TE0 or TE1 error occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_S0S1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_S0S1_SHIFT)) & I3C_SERRWARN_S0S1_MASK) + +#define I3C_SERRWARN_OREAD_MASK (0x10000U) +#define I3C_SERRWARN_OREAD_SHIFT (16U) +/*! OREAD - Over-Read Error + * 0b1..Over-read error + * 0b0..No over-read error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OREAD_SHIFT)) & I3C_SERRWARN_OREAD_MASK) + +#define I3C_SERRWARN_OWRITE_MASK (0x20000U) +#define I3C_SERRWARN_OWRITE_SHIFT (17U) +/*! OWRITE - Over-Write Error + * 0b1..Overwrite error + * 0b0..No overwrite error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_SERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SERRWARN_OWRITE_SHIFT)) & I3C_SERRWARN_OWRITE_MASK) +/*! @} */ + +/*! @name SDMACTRL - Target DMA Control */ +/*! @{ */ + +#define I3C_SDMACTRL_DMAFB_MASK (0x3U) +#define I3C_SDMACTRL_DMAFB_SHIFT (0U) +/*! DMAFB - DMA Read (From-Bus) Trigger + * 0b00..DMA not used + * 0b01..DMA enabled for one frame + * 0b10..DMA enabled until turned off + * 0b11.. + */ +#define I3C_SDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAFB_SHIFT)) & I3C_SDMACTRL_DMAFB_MASK) + +#define I3C_SDMACTRL_DMATB_MASK (0xCU) +#define I3C_SDMACTRL_DMATB_SHIFT (2U) +/*! DMATB - DMA Write (To-Bus) Trigger + * 0b00..DMA not used + * 0b01..DMA enabled for one frame + * 0b10..DMA enabled until turned off + * 0b11.. + */ +#define I3C_SDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMATB_SHIFT)) & I3C_SDMACTRL_DMATB_MASK) + +#define I3C_SDMACTRL_DMAWIDTH_MASK (0x30U) +#define I3C_SDMACTRL_DMAWIDTH_SHIFT (4U) +/*! DMAWIDTH - Width of DMA Operations + * 0b00, 0b01..Byte + * 0b10..Halfword (16 bits) (this value ensures that two bytes are available in the FIFO) + * 0b11.. + */ +#define I3C_SDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDMACTRL_DMAWIDTH_SHIFT)) & I3C_SDMACTRL_DMAWIDTH_MASK) +/*! @} */ + +/*! @name SDATACTRL - Target Data Control */ +/*! @{ */ + +#define I3C_SDATACTRL_FLUSHTB_MASK (0x1U) +#define I3C_SDATACTRL_FLUSHTB_SHIFT (0U) +/*! FLUSHTB - Flush To-Bus Buffer or FIFO */ +#define I3C_SDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHTB_SHIFT)) & I3C_SDATACTRL_FLUSHTB_MASK) + +#define I3C_SDATACTRL_FLUSHFB_MASK (0x2U) +#define I3C_SDATACTRL_FLUSHFB_SHIFT (1U) +/*! FLUSHFB - Flush From-Bus Buffer or FIFO */ +#define I3C_SDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_FLUSHFB_SHIFT)) & I3C_SDATACTRL_FLUSHFB_MASK) + +#define I3C_SDATACTRL_UNLOCK_MASK (0x8U) +#define I3C_SDATACTRL_UNLOCK_SHIFT (3U) +/*! UNLOCK - Unlock + * 0b0..Cannot be changed + * 0b1..Can be changed + */ +#define I3C_SDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_UNLOCK_SHIFT)) & I3C_SDATACTRL_UNLOCK_MASK) + +#define I3C_SDATACTRL_TXTRIG_MASK (0x30U) +#define I3C_SDATACTRL_TXTRIG_SHIFT (4U) +/*! TXTRIG - Transmit Trigger Level + * 0b00..Trigger when empty + * 0b01..Trigger when 1/4 full or less + * 0b10..Trigger when 1/2 full or less + * 0b11..Default (trigger when 1 less than full or less) + */ +#define I3C_SDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXTRIG_SHIFT)) & I3C_SDATACTRL_TXTRIG_MASK) + +#define I3C_SDATACTRL_RXTRIG_MASK (0xC0U) +#define I3C_SDATACTRL_RXTRIG_SHIFT (6U) +/*! RXTRIG - Receive Trigger Level + * 0b00..Trigger when not empty + * 0b01..Trigger when 1/4 or more full + * 0b10..Trigger when 1/2 or more full + * 0b11..Trigger when 3/4 or more full + */ +#define I3C_SDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXTRIG_SHIFT)) & I3C_SDATACTRL_RXTRIG_MASK) + +#define I3C_SDATACTRL_TXCOUNT_MASK (0x1F0000U) +#define I3C_SDATACTRL_TXCOUNT_SHIFT (16U) +/*! TXCOUNT - Count of Bytes in Transmit */ +#define I3C_SDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXCOUNT_SHIFT)) & I3C_SDATACTRL_TXCOUNT_MASK) + +#define I3C_SDATACTRL_RXCOUNT_MASK (0x1F000000U) +#define I3C_SDATACTRL_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - Count of Bytes in Receive */ +#define I3C_SDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXCOUNT_SHIFT)) & I3C_SDATACTRL_RXCOUNT_MASK) + +#define I3C_SDATACTRL_TXFULL_MASK (0x40000000U) +#define I3C_SDATACTRL_TXFULL_SHIFT (30U) +/*! TXFULL - Transmit is Full + * 0b1..Full + * 0b0..Not full + */ +#define I3C_SDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_TXFULL_SHIFT)) & I3C_SDATACTRL_TXFULL_MASK) + +#define I3C_SDATACTRL_RXEMPTY_MASK (0x80000000U) +#define I3C_SDATACTRL_RXEMPTY_SHIFT (31U) +/*! RXEMPTY - Receive is Empty + * 0b1..Empty + * 0b0..Not empty + */ +#define I3C_SDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDATACTRL_RXEMPTY_SHIFT)) & I3C_SDATACTRL_RXEMPTY_MASK) +/*! @} */ + +/*! @name SWDATAB - Target Write Data Byte */ +/*! @{ */ + +#define I3C_SWDATAB_DATA_MASK (0xFFU) +#define I3C_SWDATAB_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATAB_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_DATA_SHIFT)) & I3C_SWDATAB_DATA_MASK) + +#define I3C_SWDATAB_END_MASK (0x100U) +#define I3C_SWDATAB_END_SHIFT (8U) +/*! END - End + * 0b1..End + * 0b0..Not the end + */ +#define I3C_SWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_SHIFT)) & I3C_SWDATAB_END_MASK) + +#define I3C_SWDATAB_END_ALSO_MASK (0x10000U) +#define I3C_SWDATAB_END_ALSO_SHIFT (16U) +/*! END_ALSO - End Also + * 0b1..End + * 0b0..Not the end + */ +#define I3C_SWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB_END_ALSO_SHIFT)) & I3C_SWDATAB_END_ALSO_MASK) +/*! @} */ + +/*! @name SWDATABE - Target Write Data Byte End */ +/*! @{ */ + +#define I3C_SWDATABE_DATA_MASK (0xFFU) +#define I3C_SWDATABE_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATABE_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATABE_DATA_SHIFT)) & I3C_SWDATABE_DATA_MASK) +/*! @} */ + +/*! @name SWDATAH - Target Write Data Halfword */ +/*! @{ */ + +#define I3C_SWDATAH_DATA0_MASK (0xFFU) +#define I3C_SWDATAH_DATA0_SHIFT (0U) +/*! DATA0 - Data 0 */ +#define I3C_SWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA0_SHIFT)) & I3C_SWDATAH_DATA0_MASK) + +#define I3C_SWDATAH_DATA1_MASK (0xFF00U) +#define I3C_SWDATAH_DATA1_SHIFT (8U) +/*! DATA1 - Data 1 */ +#define I3C_SWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_DATA1_SHIFT)) & I3C_SWDATAH_DATA1_MASK) + +#define I3C_SWDATAH_END_MASK (0x10000U) +#define I3C_SWDATAH_END_SHIFT (16U) +/*! END - End of Message + * 0b1..End + * 0b0..Not the end + */ +#define I3C_SWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH_END_SHIFT)) & I3C_SWDATAH_END_MASK) +/*! @} */ + +/*! @name SWDATAHE - Target Write Data Halfword End */ +/*! @{ */ + +#define I3C_SWDATAHE_DATA0_MASK (0xFFU) +#define I3C_SWDATAHE_DATA0_SHIFT (0U) +/*! DATA0 - Data 0 */ +#define I3C_SWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA0_SHIFT)) & I3C_SWDATAHE_DATA0_MASK) + +#define I3C_SWDATAHE_DATA1_MASK (0xFF00U) +#define I3C_SWDATAHE_DATA1_SHIFT (8U) +/*! DATA1 - Data 1 */ +#define I3C_SWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAHE_DATA1_SHIFT)) & I3C_SWDATAHE_DATA1_MASK) +/*! @} */ + +/*! @name SRDATAB - Target Read Data Byte */ +/*! @{ */ + +#define I3C_SRDATAB_DATA0_MASK (0xFFU) +#define I3C_SRDATAB_DATA0_SHIFT (0U) +/*! DATA0 - Data 0 */ +#define I3C_SRDATAB_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAB_DATA0_SHIFT)) & I3C_SRDATAB_DATA0_MASK) +/*! @} */ + +/*! @name SRDATAH - Target Read Data Halfword */ +/*! @{ */ + +#define I3C_SRDATAH_LSB_MASK (0xFFU) +#define I3C_SRDATAH_LSB_SHIFT (0U) +/*! LSB - Low Byte */ +#define I3C_SRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_LSB_SHIFT)) & I3C_SRDATAH_LSB_MASK) + +#define I3C_SRDATAH_MSB_MASK (0xFF00U) +#define I3C_SRDATAH_MSB_SHIFT (8U) +/*! MSB - High Byte */ +#define I3C_SRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SRDATAH_MSB_SHIFT)) & I3C_SRDATAH_MSB_MASK) +/*! @} */ + +/*! @name SWDATAB1 - Target Write Data Byte */ +/*! @{ */ + +#define I3C_SWDATAB1_DATA_MASK (0xFFU) +#define I3C_SWDATAB1_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATAB1_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAB1_DATA_SHIFT)) & I3C_SWDATAB1_DATA_MASK) +/*! @} */ + +/*! @name SWDATAH1 - Target Write Data Halfword */ +/*! @{ */ + +#define I3C_SWDATAH1_DATA_MASK (0xFFFFU) +#define I3C_SWDATAH1_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_SWDATAH1_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SWDATAH1_DATA_SHIFT)) & I3C_SWDATAH1_DATA_MASK) +/*! @} */ + +/*! @name SCAPABILITIES2 - Target Capabilities 2 */ +/*! @{ */ + +#define I3C_SCAPABILITIES2_MAPCNT_MASK (0xFU) +#define I3C_SCAPABILITIES2_MAPCNT_SHIFT (0U) +/*! MAPCNT - Map Count */ +#define I3C_SCAPABILITIES2_MAPCNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_MAPCNT_SHIFT)) & I3C_SCAPABILITIES2_MAPCNT_MASK) + +#define I3C_SCAPABILITIES2_I2C10B_MASK (0x10U) +#define I3C_SCAPABILITIES2_I2C10B_SHIFT (4U) +/*! I2C10B - I2C 10-bit Address + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_I2C10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2C10B_SHIFT)) & I3C_SCAPABILITIES2_I2C10B_MASK) + +#define I3C_SCAPABILITIES2_I2CRST_MASK (0x20U) +#define I3C_SCAPABILITIES2_I2CRST_SHIFT (5U) +/*! I2CRST - I2C Software Reset + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_I2CRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CRST_SHIFT)) & I3C_SCAPABILITIES2_I2CRST_MASK) + +#define I3C_SCAPABILITIES2_I2CDEVID_MASK (0x40U) +#define I3C_SCAPABILITIES2_I2CDEVID_SHIFT (6U) +/*! I2CDEVID - I2C Device ID + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_I2CDEVID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_I2CDEVID_SHIFT)) & I3C_SCAPABILITIES2_I2CDEVID_MASK) + +#define I3C_SCAPABILITIES2_IBIEXT_MASK (0x100U) +#define I3C_SCAPABILITIES2_IBIEXT_SHIFT (8U) +/*! IBIEXT - In-Band Interrupt EXTDATA + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_IBIEXT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIEXT_SHIFT)) & I3C_SCAPABILITIES2_IBIEXT_MASK) + +#define I3C_SCAPABILITIES2_IBIXREG_MASK (0x200U) +#define I3C_SCAPABILITIES2_IBIXREG_SHIFT (9U) +/*! IBIXREG - In-Band Interrupt Extended Register + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_IBIXREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_IBIXREG_SHIFT)) & I3C_SCAPABILITIES2_IBIXREG_MASK) + +#define I3C_SCAPABILITIES2_SLVRST_MASK (0x20000U) +#define I3C_SCAPABILITIES2_SLVRST_SHIFT (17U) +/*! SLVRST - Target Reset + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES2_SLVRST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SLVRST_SHIFT)) & I3C_SCAPABILITIES2_SLVRST_MASK) + +#define I3C_SCAPABILITIES2_GROUP_MASK (0xC0000U) +#define I3C_SCAPABILITIES2_GROUP_SHIFT (18U) +/*! GROUP - Group + * 0b00..v1.1 group addressing not supported + * 0b01..One group supported + * 0b10..Two groups supported + * 0b11..Three groups supported + */ +#define I3C_SCAPABILITIES2_GROUP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_GROUP_SHIFT)) & I3C_SCAPABILITIES2_GROUP_MASK) + +#define I3C_SCAPABILITIES2_AASA_MASK (0x200000U) +#define I3C_SCAPABILITIES2_AASA_SHIFT (21U) +/*! AASA - SETAASA + * 0b1..SETAASA supported + * 0b0..SETAASA not supported + */ +#define I3C_SCAPABILITIES2_AASA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_AASA_SHIFT)) & I3C_SCAPABILITIES2_AASA_MASK) + +#define I3C_SCAPABILITIES2_SSTSUB_MASK (0x400000U) +#define I3C_SCAPABILITIES2_SSTSUB_SHIFT (22U) +/*! SSTSUB - Target-Target(s)-Tunnel Subscriber Capable + * 0b1..Subscriber capable + * 0b0..Not subscriber capable + */ +#define I3C_SCAPABILITIES2_SSTSUB(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTSUB_SHIFT)) & I3C_SCAPABILITIES2_SSTSUB_MASK) + +#define I3C_SCAPABILITIES2_SSTWR_MASK (0x800000U) +#define I3C_SCAPABILITIES2_SSTWR_SHIFT (23U) +/*! SSTWR - Target-Target(s)-Tunnel Write Capable + * 0b1..Write capable + * 0b0..Not write capable + */ +#define I3C_SCAPABILITIES2_SSTWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES2_SSTWR_SHIFT)) & I3C_SCAPABILITIES2_SSTWR_MASK) +/*! @} */ + +/*! @name SCAPABILITIES - Target Capabilities */ +/*! @{ */ + +#define I3C_SCAPABILITIES_IDENA_MASK (0x3U) +#define I3C_SCAPABILITIES_IDENA_SHIFT (0U) +/*! IDENA - ID 48b Handler + * 0b00..Application + * 0b01..Hardware + * 0b10..Hardware, but the I3C module instance handles ID 48b + * 0b11..A part number register (PARTNO) + */ +#define I3C_SCAPABILITIES_IDENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDENA_SHIFT)) & I3C_SCAPABILITIES_IDENA_MASK) + +#define I3C_SCAPABILITIES_IDREG_MASK (0x3CU) +#define I3C_SCAPABILITIES_IDREG_SHIFT (2U) +/*! IDREG - ID Register + * 0b0000..All ID register features disabled + * 0bxxx1..ID Instance is a register; used if there is no PARTNO register + * 0bxx1x..An ID Random field is available + * 0bx1xx..A Device Characteristic Register (DCR) is available + * 0b1xxx..A Bus Characteristics Register (BCR) is available + */ +#define I3C_SCAPABILITIES_IDREG(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IDREG_SHIFT)) & I3C_SCAPABILITIES_IDREG_MASK) + +#define I3C_SCAPABILITIES_HDRSUPP_MASK (0xC0U) +#define I3C_SCAPABILITIES_HDRSUPP_SHIFT (6U) +/*! HDRSUPP - High Data Rate Support + * 0b00..No HDR modes supported + * 0b01..DDR mode supported + * *.. + */ +#define I3C_SCAPABILITIES_HDRSUPP(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_HDRSUPP_SHIFT)) & I3C_SCAPABILITIES_HDRSUPP_MASK) + +#define I3C_SCAPABILITIES_MASTER_MASK (0x200U) +#define I3C_SCAPABILITIES_MASTER_SHIFT (9U) +/*! MASTER - Controller + * 0b0..Not supported + * 0b1..Supported + */ +#define I3C_SCAPABILITIES_MASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_MASTER_SHIFT)) & I3C_SCAPABILITIES_MASTER_MASK) + +#define I3C_SCAPABILITIES_SADDR_MASK (0xC00U) +#define I3C_SCAPABILITIES_SADDR_SHIFT (10U) +/*! SADDR - Static Address + * 0b00..No static address + * 0b01..Static address is fixed in hardware + * 0b10..Hardware controls the static address dynamically (for example, from the pin strap) + * 0b11..SCONFIG register supplies the static address + */ +#define I3C_SCAPABILITIES_SADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_SADDR_SHIFT)) & I3C_SCAPABILITIES_SADDR_MASK) + +#define I3C_SCAPABILITIES_CCCHANDLE_MASK (0xF000U) +#define I3C_SCAPABILITIES_CCCHANDLE_SHIFT (12U) +/*! CCCHANDLE - Common Command Codes Handling + * 0b0000..All handling features disabled + * 0bxxx1..The I3C module manages events, activities, status, HDR, and if enabled for it, ID and static-address-related items + * 0bxx1x..The I3C module manages maximum read and write lengths, and max data speed + * 0bx1xx..GETSTATUS CCC returns the values of SCTRL[PENDINT] and SCTRL[ACTSTATE] + * 0b1xxx..GETSTATUS CCC returns the value of SCTRL[VENDINFO] + */ +#define I3C_SCAPABILITIES_CCCHANDLE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_CCCHANDLE_SHIFT)) & I3C_SCAPABILITIES_CCCHANDLE_MASK) + +#define I3C_SCAPABILITIES_IBI_MR_HJ_MASK (0x1F0000U) +#define I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT (16U) +/*! IBI_MR_HJ - In-Band Interrupts, Controller Requests, Hot-Join Events + * 0b00000..Application cannot generate IBI, CR, or HJ + * 0bxxxx1..Application can generate an IBI + * 0bxxx1x..When bit 0 = 1, the IBI has data from the SCTRL register + * 0bxx1xx..Application can generate a controller request for a secondary controller + * 0bx1xxx..Application can generate a Hot-Join event + * 0b1xxxx..Application can use SCONFIG[BAMATCH] for bus-available timing + */ +#define I3C_SCAPABILITIES_IBI_MR_HJ(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_IBI_MR_HJ_SHIFT)) & I3C_SCAPABILITIES_IBI_MR_HJ_MASK) + +#define I3C_SCAPABILITIES_TIMECTRL_MASK (0x200000U) +#define I3C_SCAPABILITIES_TIMECTRL_SHIFT (21U) +/*! TIMECTRL - Time Control + * 0b0..No time control supported + * 0b1..At least one time-control type supported + */ +#define I3C_SCAPABILITIES_TIMECTRL(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_TIMECTRL_SHIFT)) & I3C_SCAPABILITIES_TIMECTRL_MASK) + +#define I3C_SCAPABILITIES_EXTFIFO_MASK (0x3800000U) +#define I3C_SCAPABILITIES_EXTFIFO_SHIFT (23U) +/*! EXTFIFO - External FIFO + * 0b000..No external FIFO available + * 0b001..Standard available or free external FIFO + * 0b010..Request track external FIFO + * *.. + */ +#define I3C_SCAPABILITIES_EXTFIFO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_EXTFIFO_SHIFT)) & I3C_SCAPABILITIES_EXTFIFO_MASK) + +#define I3C_SCAPABILITIES_FIFOTX_MASK (0xC000000U) +#define I3C_SCAPABILITIES_FIFOTX_SHIFT (26U) +/*! FIFOTX - FIFO Transmit + * 0b00..Two + * 0b01..Four + * 0b10..Eight + * 0b11..16 or larger + */ +#define I3C_SCAPABILITIES_FIFOTX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFOTX_SHIFT)) & I3C_SCAPABILITIES_FIFOTX_MASK) + +#define I3C_SCAPABILITIES_FIFORX_MASK (0x30000000U) +#define I3C_SCAPABILITIES_FIFORX_SHIFT (28U) +/*! FIFORX - FIFO Receive + * 0b00..Two or three + * 0b01..Four + * 0b10..Eight + * 0b11..16 or larger + */ +#define I3C_SCAPABILITIES_FIFORX(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_FIFORX_SHIFT)) & I3C_SCAPABILITIES_FIFORX_MASK) + +#define I3C_SCAPABILITIES_INT_MASK (0x40000000U) +#define I3C_SCAPABILITIES_INT_SHIFT (30U) +/*! INT - Interrupts + * 0b1..Supported + * 0b0..Not supported + */ +#define I3C_SCAPABILITIES_INT(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_INT_SHIFT)) & I3C_SCAPABILITIES_INT_MASK) + +#define I3C_SCAPABILITIES_DMA_MASK (0x80000000U) +#define I3C_SCAPABILITIES_DMA_SHIFT (31U) +/*! DMA - Direct Memory Access + * 0b1..Supported + * 0b0..Not supported + */ +#define I3C_SCAPABILITIES_DMA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SCAPABILITIES_DMA_SHIFT)) & I3C_SCAPABILITIES_DMA_MASK) +/*! @} */ + +/*! @name SDYNADDR - Target Dynamic Address */ +/*! @{ */ + +#define I3C_SDYNADDR_DAVALID_MASK (0x1U) +#define I3C_SDYNADDR_DAVALID_SHIFT (0U) +/*! DAVALID - Dynamic Address Valid + * 0b0..DANOTASSIGNED: a dynamic address is not assigned + * 0b1..DAASSIGNED: a dynamic address is assigned + */ +#define I3C_SDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DAVALID_SHIFT)) & I3C_SDYNADDR_DAVALID_MASK) + +#define I3C_SDYNADDR_DADDR_MASK (0xFEU) +#define I3C_SDYNADDR_DADDR_SHIFT (1U) +/*! DADDR - Dynamic Address */ +#define I3C_SDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_DADDR_SHIFT)) & I3C_SDYNADDR_DADDR_MASK) + +#define I3C_SDYNADDR_MAPSA_MASK (0x1000U) +#define I3C_SDYNADDR_MAPSA_SHIFT (12U) +/*! MAPSA - Map a Static Address */ +#define I3C_SDYNADDR_MAPSA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_MAPSA_SHIFT)) & I3C_SDYNADDR_MAPSA_MASK) + +#define I3C_SDYNADDR_SA10B_MASK (0xE000U) +#define I3C_SDYNADDR_SA10B_SHIFT (13U) +/*! SA10B - 10-Bit Static Address */ +#define I3C_SDYNADDR_SA10B(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_SA10B_SHIFT)) & I3C_SDYNADDR_SA10B_MASK) + +#define I3C_SDYNADDR_KEY_MASK (0xFFFF0000U) +#define I3C_SDYNADDR_KEY_SHIFT (16U) +/*! KEY - Key */ +#define I3C_SDYNADDR_KEY(x) (((uint32_t)(((uint32_t)(x)) << I3C_SDYNADDR_KEY_SHIFT)) & I3C_SDYNADDR_KEY_MASK) +/*! @} */ + +/*! @name SMAXLIMITS - Target Maximum Limits */ +/*! @{ */ + +#define I3C_SMAXLIMITS_MAXRD_MASK (0xFFFU) +#define I3C_SMAXLIMITS_MAXRD_SHIFT (0U) +/*! MAXRD - Maximum Read Length */ +#define I3C_SMAXLIMITS_MAXRD(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXRD_SHIFT)) & I3C_SMAXLIMITS_MAXRD_MASK) + +#define I3C_SMAXLIMITS_MAXWR_MASK (0xFFF0000U) +#define I3C_SMAXLIMITS_MAXWR_SHIFT (16U) +/*! MAXWR - Maximum Write Length */ +#define I3C_SMAXLIMITS_MAXWR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAXLIMITS_MAXWR_SHIFT)) & I3C_SMAXLIMITS_MAXWR_MASK) +/*! @} */ + +/*! @name SIDPARTNO - Target ID Part Number */ +/*! @{ */ + +#define I3C_SIDPARTNO_PARTNO_MASK (0xFFFFFFFFU) +#define I3C_SIDPARTNO_PARTNO_SHIFT (0U) +/*! PARTNO - Part Number */ +#define I3C_SIDPARTNO_PARTNO(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDPARTNO_PARTNO_SHIFT)) & I3C_SIDPARTNO_PARTNO_MASK) +/*! @} */ + +/*! @name SIDEXT - Target ID Extension */ +/*! @{ */ + +#define I3C_SIDEXT_DCR_MASK (0xFF00U) +#define I3C_SIDEXT_DCR_SHIFT (8U) +/*! DCR - Device Characteristic Register */ +#define I3C_SIDEXT_DCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_DCR_SHIFT)) & I3C_SIDEXT_DCR_MASK) + +#define I3C_SIDEXT_BCR_MASK (0xFF0000U) +#define I3C_SIDEXT_BCR_SHIFT (16U) +/*! BCR - Bus Characteristics Register */ +#define I3C_SIDEXT_BCR(x) (((uint32_t)(((uint32_t)(x)) << I3C_SIDEXT_BCR_SHIFT)) & I3C_SIDEXT_BCR_MASK) +/*! @} */ + +/*! @name SVENDORID - Target Vendor ID */ +/*! @{ */ + +#define I3C_SVENDORID_VID_MASK (0x7FFFU) +#define I3C_SVENDORID_VID_SHIFT (0U) +/*! VID - Vendor ID */ +#define I3C_SVENDORID_VID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SVENDORID_VID_SHIFT)) & I3C_SVENDORID_VID_MASK) +/*! @} */ + +/*! @name STCCLOCK - Target Time Control Clock */ +/*! @{ */ + +#define I3C_STCCLOCK_ACCURACY_MASK (0xFFU) +#define I3C_STCCLOCK_ACCURACY_SHIFT (0U) +/*! ACCURACY - Clock Accuracy */ +#define I3C_STCCLOCK_ACCURACY(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_ACCURACY_SHIFT)) & I3C_STCCLOCK_ACCURACY_MASK) + +#define I3C_STCCLOCK_FREQ_MASK (0xFF00U) +#define I3C_STCCLOCK_FREQ_SHIFT (8U) +/*! FREQ - Clock Frequency */ +#define I3C_STCCLOCK_FREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_STCCLOCK_FREQ_SHIFT)) & I3C_STCCLOCK_FREQ_MASK) +/*! @} */ + +/*! @name SMSGMAPADDR - Target Message Map Address */ +/*! @{ */ + +#define I3C_SMSGMAPADDR_MAPLAST_MASK (0xFU) +#define I3C_SMSGMAPADDR_MAPLAST_SHIFT (0U) +/*! MAPLAST - Matched Address Index */ +#define I3C_SMSGMAPADDR_MAPLAST(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLAST_SHIFT)) & I3C_SMSGMAPADDR_MAPLAST_MASK) + +#define I3C_SMSGMAPADDR_LASTSTATIC_MASK (0x10U) +#define I3C_SMSGMAPADDR_LASTSTATIC_SHIFT (4U) +/*! LASTSTATIC - Last Static Address Matched + * 0b1..I2C static address + * 0b0..I3C dynamic address + */ +#define I3C_SMSGMAPADDR_LASTSTATIC(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_LASTSTATIC_SHIFT)) & I3C_SMSGMAPADDR_LASTSTATIC_MASK) + +#define I3C_SMSGMAPADDR_MAPLASTM1_MASK (0xF00U) +#define I3C_SMSGMAPADDR_MAPLASTM1_SHIFT (8U) +/*! MAPLASTM1 - Matched Previous Address Index 1 */ +#define I3C_SMSGMAPADDR_MAPLASTM1(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM1_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM1_MASK) + +#define I3C_SMSGMAPADDR_MAPLASTM2_MASK (0xF0000U) +#define I3C_SMSGMAPADDR_MAPLASTM2_SHIFT (16U) +/*! MAPLASTM2 - Matched Previous Index 2 */ +#define I3C_SMSGMAPADDR_MAPLASTM2(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMSGMAPADDR_MAPLASTM2_SHIFT)) & I3C_SMSGMAPADDR_MAPLASTM2_MASK) +/*! @} */ + +/*! @name MCONFIG_EXT - Controller Extended Configuration */ +/*! @{ */ + +#define I3C_MCONFIG_EXT_I3C_CAS_DEL_MASK (0x30000U) +#define I3C_MCONFIG_EXT_I3C_CAS_DEL_SHIFT (16U) +/*! I3C_CAS_DEL - I3C CAS Delay After START + * 0b00..No delay + * 0b01..Increases SCL clock period by 1/2 + * 0b10..Increases SCL clock period by 1 + * 0b11..Increases SCL clock period by 3/2 + */ +#define I3C_MCONFIG_EXT_I3C_CAS_DEL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I3C_CAS_DEL_SHIFT)) & I3C_MCONFIG_EXT_I3C_CAS_DEL_MASK) + +#define I3C_MCONFIG_EXT_I3C_CASR_DEL_MASK (0xC0000U) +#define I3C_MCONFIG_EXT_I3C_CASR_DEL_SHIFT (18U) +/*! I3C_CASR_DEL - I3C CAS Delay After Repeated START + * 0b00..No delay + * 0b01..Increases SCL clock period by 1/2 + * 0b10..Increases SCL clock period by 1 + * 0b11..Increases SCL clock period by 1 1/2 + */ +#define I3C_MCONFIG_EXT_I3C_CASR_DEL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCONFIG_EXT_I3C_CASR_DEL_SHIFT)) & I3C_MCONFIG_EXT_I3C_CASR_DEL_MASK) +/*! @} */ + +/*! @name MCTRL - Controller Control */ +/*! @{ */ + +#define I3C_MCTRL_REQUEST_MASK (0x7U) +#define I3C_MCTRL_REQUEST_SHIFT (0U) +/*! REQUEST - Request + * 0b000..NONE + * 0b001..EMITSTARTADDR + * 0b010..EMITSTOP + * 0b011..IBIACKNACK + * 0b100..PROCESSDAA + * 0b101.. + * 0b110..Force Exit and Target Reset + * 0b111..AUTOIBI + */ +#define I3C_MCTRL_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_REQUEST_SHIFT)) & I3C_MCTRL_REQUEST_MASK) + +#define I3C_MCTRL_TYPE_MASK (0x30U) +#define I3C_MCTRL_TYPE_SHIFT (4U) +/*! TYPE - Bus Type with EmitStartAddr + * 0b00..I3C + * 0b01..I2C + * 0b10..DDR + * 0b11.. + */ +#define I3C_MCTRL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_TYPE_SHIFT)) & I3C_MCTRL_TYPE_MASK) + +#define I3C_MCTRL_IBIRESP_MASK (0xC0U) +#define I3C_MCTRL_IBIRESP_SHIFT (6U) +/*! IBIRESP - In-Band Interrupt Response + * 0b00..ACK (acknowledge) + * 0b01..NACK (reject) + * 0b10..Acknowledge with mandatory byte + * 0b11..Manual + */ +#define I3C_MCTRL_IBIRESP(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_IBIRESP_SHIFT)) & I3C_MCTRL_IBIRESP_MASK) + +#define I3C_MCTRL_DIR_MASK (0x100U) +#define I3C_MCTRL_DIR_SHIFT (8U) +/*! DIR - Direction + * 0b0..Write + * 0b1..Read + */ +#define I3C_MCTRL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_DIR_SHIFT)) & I3C_MCTRL_DIR_MASK) + +#define I3C_MCTRL_ADDR_MASK (0xFE00U) +#define I3C_MCTRL_ADDR_SHIFT (9U) +/*! ADDR - Address */ +#define I3C_MCTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_ADDR_SHIFT)) & I3C_MCTRL_ADDR_MASK) + +#define I3C_MCTRL_RDTERM_MASK (0xFF0000U) +#define I3C_MCTRL_RDTERM_SHIFT (16U) +/*! RDTERM - Read Terminate Counter */ +#define I3C_MCTRL_RDTERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MCTRL_RDTERM_SHIFT)) & I3C_MCTRL_RDTERM_MASK) +/*! @} */ + +/*! @name MSTATUS - Controller Status */ +/*! @{ */ + +#define I3C_MSTATUS_STATE_MASK (0x7U) +#define I3C_MSTATUS_STATE_SHIFT (0U) +/*! STATE - State of the Controller + * 0b000..IDLE (bus has stopped) + * 0b001..SLVREQ (target request) + * 0b010..MSGSDR + * 0b011..NORMACT + * 0b100..MSGDDR + * 0b101..DAA + * 0b110..IBIACK + * 0b111..IBIRCV + */ +#define I3C_MSTATUS_STATE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_STATE_SHIFT)) & I3C_MSTATUS_STATE_MASK) + +#define I3C_MSTATUS_BETWEEN_MASK (0x10U) +#define I3C_MSTATUS_BETWEEN_SHIFT (4U) +/*! BETWEEN - Between + * 0b0..Inactive (for other cases) + * 0b1..Active + */ +#define I3C_MSTATUS_BETWEEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_BETWEEN_SHIFT)) & I3C_MSTATUS_BETWEEN_MASK) + +#define I3C_MSTATUS_NACKED_MASK (0x20U) +#define I3C_MSTATUS_NACKED_SHIFT (5U) +/*! NACKED - Not Acknowledged + * 0b1..NACKed (not acknowledged) + * 0b0..Not NACKed + */ +#define I3C_MSTATUS_NACKED(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NACKED_SHIFT)) & I3C_MSTATUS_NACKED_MASK) + +#define I3C_MSTATUS_IBITYPE_MASK (0xC0U) +#define I3C_MSTATUS_IBITYPE_SHIFT (6U) +/*! IBITYPE - In-Band Interrupt (IBI) Type + * 0b00..NONE (no IBI: this status occurs when MSTATUS[IBIWON] becomes 0) + * 0b01..IBI + * 0b10..CR + * 0b11..HJ + */ +#define I3C_MSTATUS_IBITYPE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBITYPE_SHIFT)) & I3C_MSTATUS_IBITYPE_MASK) + +#define I3C_MSTATUS_SLVSTART_MASK (0x100U) +#define I3C_MSTATUS_SLVSTART_SHIFT (8U) +/*! SLVSTART - Target Start + * 0b1..Target requesting START + * 0b0..Target not requesting START + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_SLVSTART_SHIFT)) & I3C_MSTATUS_SLVSTART_MASK) + +#define I3C_MSTATUS_MCTRLDONE_MASK (0x200U) +#define I3C_MSTATUS_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - Controller Control Done + * 0b1..Done + * 0b0..Not done + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_MCTRLDONE_SHIFT)) & I3C_MSTATUS_MCTRLDONE_MASK) + +#define I3C_MSTATUS_COMPLETE_MASK (0x400U) +#define I3C_MSTATUS_COMPLETE_SHIFT (10U) +/*! COMPLETE - Complete + * 0b1..Complete + * 0b0..Not complete + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_COMPLETE_SHIFT)) & I3C_MSTATUS_COMPLETE_MASK) + +#define I3C_MSTATUS_RXPEND_MASK (0x800U) +#define I3C_MSTATUS_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND + * 0b1..Receive message pending + * 0b0..No receive message pending + */ +#define I3C_MSTATUS_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_RXPEND_SHIFT)) & I3C_MSTATUS_RXPEND_MASK) + +#define I3C_MSTATUS_TXNOTFULL_MASK (0x1000U) +#define I3C_MSTATUS_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TX Buffer or FIFO Not Full + * 0b1..Receive buffer or FIFO not full + * 0b0..Receive buffer or FIFO full + */ +#define I3C_MSTATUS_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_TXNOTFULL_SHIFT)) & I3C_MSTATUS_TXNOTFULL_MASK) + +#define I3C_MSTATUS_IBIWON_MASK (0x2000U) +#define I3C_MSTATUS_IBIWON_SHIFT (13U) +/*! IBIWON - In-Band Interrupt (IBI) Won + * 0b1..IBI arbitration won + * 0b0..No IBI arbitration won + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIWON_SHIFT)) & I3C_MSTATUS_IBIWON_MASK) + +#define I3C_MSTATUS_ERRWARN_MASK (0x8000U) +#define I3C_MSTATUS_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error or Warning + * 0b1..Error or warning + * 0b0..No error or warning + */ +#define I3C_MSTATUS_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_ERRWARN_SHIFT)) & I3C_MSTATUS_ERRWARN_MASK) + +#define I3C_MSTATUS_NOWMASTER_MASK (0x80000U) +#define I3C_MSTATUS_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - Module is now Controller + * 0b1..Controller + * 0b0..Not a controller + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MSTATUS_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_NOWMASTER_SHIFT)) & I3C_MSTATUS_NOWMASTER_MASK) + +#define I3C_MSTATUS_IBIADDR_MASK (0x7F000000U) +#define I3C_MSTATUS_IBIADDR_SHIFT (24U) +/*! IBIADDR - IBI Address */ +#define I3C_MSTATUS_IBIADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MSTATUS_IBIADDR_SHIFT)) & I3C_MSTATUS_IBIADDR_MASK) +/*! @} */ + +/*! @name MIBIRULES - Controller In-band Interrupt Registry and Rules */ +/*! @{ */ + +#define I3C_MIBIRULES_ADDR0_MASK (0x3FU) +#define I3C_MIBIRULES_ADDR0_SHIFT (0U) +/*! ADDR0 - ADDR0 */ +#define I3C_MIBIRULES_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR0_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK) + +#define I3C_MIBIRULES_ADDR1_MASK (0xFC0U) +#define I3C_MIBIRULES_ADDR1_SHIFT (6U) +/*! ADDR1 - ADDR1 */ +#define I3C_MIBIRULES_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR1_MASK) + +#define I3C_MIBIRULES_ADDR2_MASK (0x3F000U) +#define I3C_MIBIRULES_ADDR2_SHIFT (12U) +/*! ADDR2 - ADDR2 */ +#define I3C_MIBIRULES_ADDR2(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR2_SHIFT)) & I3C_MIBIRULES_ADDR2_MASK) + +#define I3C_MIBIRULES_ADDR3_MASK (0xFC0000U) +#define I3C_MIBIRULES_ADDR3_SHIFT (18U) +/*! ADDR3 - ADDR3 */ +#define I3C_MIBIRULES_ADDR3(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR3_SHIFT)) & I3C_MIBIRULES_ADDR3_MASK) + +#define I3C_MIBIRULES_ADDR4_MASK (0x3F000000U) +#define I3C_MIBIRULES_ADDR4_SHIFT (24U) +/*! ADDR4 - ADDR4 */ +#define I3C_MIBIRULES_ADDR4(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_ADDR4_SHIFT)) & I3C_MIBIRULES_ADDR4_MASK) + +#define I3C_MIBIRULES_MSB0_MASK (0x40000000U) +#define I3C_MIBIRULES_MSB0_SHIFT (30U) +/*! MSB0 - Most Significant Address Bit is 0 + * 0b1..MSB is 0 + * 0b0..MSB is not 0 + */ +#define I3C_MIBIRULES_MSB0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_MSB0_SHIFT)) & I3C_MIBIRULES_MSB0_MASK) + +#define I3C_MIBIRULES_NOBYTE_MASK (0x80000000U) +#define I3C_MIBIRULES_NOBYTE_SHIFT (31U) +/*! NOBYTE - No IBI byte + * 0b1..Without mandatory IBI byte + * 0b0..With mandatory IBI byte + */ +#define I3C_MIBIRULES_NOBYTE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MIBIRULES_NOBYTE_SHIFT)) & I3C_MIBIRULES_NOBYTE_MASK) +/*! @} */ + +/*! @name MINTSET - Controller Interrupt Set */ +/*! @{ */ + +#define I3C_MINTSET_SLVSTART_MASK (0x100U) +#define I3C_MINTSET_SLVSTART_SHIFT (8U) +/*! SLVSTART - Target Start Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_SLVSTART_SHIFT)) & I3C_MINTSET_SLVSTART_MASK) + +#define I3C_MINTSET_MCTRLDONE_MASK (0x200U) +#define I3C_MINTSET_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - Controller Control Done Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_MCTRLDONE_SHIFT)) & I3C_MINTSET_MCTRLDONE_MASK) + +#define I3C_MINTSET_COMPLETE_MASK (0x400U) +#define I3C_MINTSET_COMPLETE_SHIFT (10U) +/*! COMPLETE - Completed Message Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_COMPLETE_SHIFT)) & I3C_MINTSET_COMPLETE_MASK) + +#define I3C_MINTSET_RXPEND_MASK (0x800U) +#define I3C_MINTSET_RXPEND_SHIFT (11U) +/*! RXPEND - Receive Pending Interrupt Enable */ +#define I3C_MINTSET_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_RXPEND_SHIFT)) & I3C_MINTSET_RXPEND_MASK) + +#define I3C_MINTSET_TXNOTFULL_MASK (0x1000U) +#define I3C_MINTSET_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - Transmit Buffer/FIFO Not Full Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_TXNOTFULL_SHIFT)) & I3C_MINTSET_TXNOTFULL_MASK) + +#define I3C_MINTSET_IBIWON_MASK (0x2000U) +#define I3C_MINTSET_IBIWON_SHIFT (13U) +/*! IBIWON - IBI Won Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_IBIWON_SHIFT)) & I3C_MINTSET_IBIWON_MASK) + +#define I3C_MINTSET_ERRWARN_MASK (0x8000U) +#define I3C_MINTSET_ERRWARN_SHIFT (15U) +/*! ERRWARN - Error or Warning (ERRWARN) Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_ERRWARN_SHIFT)) & I3C_MINTSET_ERRWARN_MASK) + +#define I3C_MINTSET_NOWMASTER_MASK (0x80000U) +#define I3C_MINTSET_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - Now Controller Interrupt Enable + * 0b1..Enable + * 0b0..Disable + */ +#define I3C_MINTSET_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTSET_NOWMASTER_SHIFT)) & I3C_MINTSET_NOWMASTER_MASK) +/*! @} */ + +/*! @name MINTCLR - Controller Interrupt Clear */ +/*! @{ */ + +#define I3C_MINTCLR_SLVSTART_MASK (0x100U) +#define I3C_MINTCLR_SLVSTART_SHIFT (8U) +/*! SLVSTART - SLVSTART Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_SLVSTART_SHIFT)) & I3C_MINTCLR_SLVSTART_MASK) + +#define I3C_MINTCLR_MCTRLDONE_MASK (0x200U) +#define I3C_MINTCLR_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - MCTRLDONE Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_MCTRLDONE_SHIFT)) & I3C_MINTCLR_MCTRLDONE_MASK) + +#define I3C_MINTCLR_COMPLETE_MASK (0x400U) +#define I3C_MINTCLR_COMPLETE_SHIFT (10U) +/*! COMPLETE - COMPLETE Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_COMPLETE_SHIFT)) & I3C_MINTCLR_COMPLETE_MASK) + +#define I3C_MINTCLR_RXPEND_MASK (0x800U) +#define I3C_MINTCLR_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_RXPEND_SHIFT)) & I3C_MINTCLR_RXPEND_MASK) + +#define I3C_MINTCLR_TXNOTFULL_MASK (0x1000U) +#define I3C_MINTCLR_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TXNOTFULL Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_TXNOTFULL_SHIFT)) & I3C_MINTCLR_TXNOTFULL_MASK) + +#define I3C_MINTCLR_IBIWON_MASK (0x2000U) +#define I3C_MINTCLR_IBIWON_SHIFT (13U) +/*! IBIWON - IBIWON Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_IBIWON_SHIFT)) & I3C_MINTCLR_IBIWON_MASK) + +#define I3C_MINTCLR_ERRWARN_MASK (0x8000U) +#define I3C_MINTCLR_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_ERRWARN_SHIFT)) & I3C_MINTCLR_ERRWARN_MASK) + +#define I3C_MINTCLR_NOWMASTER_MASK (0x80000U) +#define I3C_MINTCLR_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - NOWCONTROLLER Interrupt Enable Clear + * 0b1..Interrupt enable cleared + * 0b0..No effect + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MINTCLR_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTCLR_NOWMASTER_SHIFT)) & I3C_MINTCLR_NOWMASTER_MASK) +/*! @} */ + +/*! @name MINTMASKED - Controller Interrupt Mask */ +/*! @{ */ + +#define I3C_MINTMASKED_SLVSTART_MASK (0x100U) +#define I3C_MINTMASKED_SLVSTART_SHIFT (8U) +/*! SLVSTART - SLVSTART Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_SLVSTART(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_SLVSTART_SHIFT)) & I3C_MINTMASKED_SLVSTART_MASK) + +#define I3C_MINTMASKED_MCTRLDONE_MASK (0x200U) +#define I3C_MINTMASKED_MCTRLDONE_SHIFT (9U) +/*! MCTRLDONE - MCTRLDONE Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_MCTRLDONE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_MCTRLDONE_SHIFT)) & I3C_MINTMASKED_MCTRLDONE_MASK) + +#define I3C_MINTMASKED_COMPLETE_MASK (0x400U) +#define I3C_MINTMASKED_COMPLETE_SHIFT (10U) +/*! COMPLETE - COMPLETE Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_COMPLETE_SHIFT)) & I3C_MINTMASKED_COMPLETE_MASK) + +#define I3C_MINTMASKED_RXPEND_MASK (0x800U) +#define I3C_MINTMASKED_RXPEND_SHIFT (11U) +/*! RXPEND - RXPEND Interrupt Mask */ +#define I3C_MINTMASKED_RXPEND(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_RXPEND_SHIFT)) & I3C_MINTMASKED_RXPEND_MASK) + +#define I3C_MINTMASKED_TXNOTFULL_MASK (0x1000U) +#define I3C_MINTMASKED_TXNOTFULL_SHIFT (12U) +/*! TXNOTFULL - TXNOTFULL Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_TXNOTFULL_SHIFT)) & I3C_MINTMASKED_TXNOTFULL_MASK) + +#define I3C_MINTMASKED_IBIWON_MASK (0x2000U) +#define I3C_MINTMASKED_IBIWON_SHIFT (13U) +/*! IBIWON - IBIWON Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_IBIWON(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_IBIWON_SHIFT)) & I3C_MINTMASKED_IBIWON_MASK) + +#define I3C_MINTMASKED_ERRWARN_MASK (0x8000U) +#define I3C_MINTMASKED_ERRWARN_SHIFT (15U) +/*! ERRWARN - ERRWARN Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_ERRWARN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_ERRWARN_SHIFT)) & I3C_MINTMASKED_ERRWARN_MASK) + +#define I3C_MINTMASKED_NOWMASTER_MASK (0x80000U) +#define I3C_MINTMASKED_NOWMASTER_SHIFT (19U) +/*! NOWMASTER - NOWCONTROLLER Interrupt Mask + * 0b1..Enabled + * 0b0..Disabled + */ +#define I3C_MINTMASKED_NOWMASTER(x) (((uint32_t)(((uint32_t)(x)) << I3C_MINTMASKED_NOWMASTER_SHIFT)) & I3C_MINTMASKED_NOWMASTER_MASK) +/*! @} */ + +/*! @name MERRWARN - Controller Errors and Warnings */ +/*! @{ */ + +#define I3C_MERRWARN_URUN_MASK (0x2U) +#define I3C_MERRWARN_URUN_SHIFT (1U) +/*! URUN - Underrun Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_URUN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_URUN_SHIFT)) & I3C_MERRWARN_URUN_MASK) + +#define I3C_MERRWARN_NACK_MASK (0x4U) +#define I3C_MERRWARN_NACK_SHIFT (2U) +/*! NACK - Not Acknowledge Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_NACK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_NACK_SHIFT)) & I3C_MERRWARN_NACK_MASK) + +#define I3C_MERRWARN_WRABT_MASK (0x8U) +#define I3C_MERRWARN_WRABT_SHIFT (3U) +/*! WRABT - Write Abort Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_WRABT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_WRABT_SHIFT)) & I3C_MERRWARN_WRABT_MASK) + +#define I3C_MERRWARN_TERM_MASK (0x10U) +#define I3C_MERRWARN_TERM_SHIFT (4U) +/*! TERM - Terminate Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_TERM(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TERM_SHIFT)) & I3C_MERRWARN_TERM_MASK) + +#define I3C_MERRWARN_HPAR_MASK (0x200U) +#define I3C_MERRWARN_HPAR_SHIFT (9U) +/*! HPAR - High Data Rate Parity + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_HPAR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HPAR_SHIFT)) & I3C_MERRWARN_HPAR_MASK) + +#define I3C_MERRWARN_HCRC_MASK (0x400U) +#define I3C_MERRWARN_HCRC_SHIFT (10U) +/*! HCRC - High Data Rate CRC Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_HCRC(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_HCRC_SHIFT)) & I3C_MERRWARN_HCRC_MASK) + +#define I3C_MERRWARN_OREAD_MASK (0x10000U) +#define I3C_MERRWARN_OREAD_SHIFT (16U) +/*! OREAD - Overread Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_OREAD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OREAD_SHIFT)) & I3C_MERRWARN_OREAD_MASK) + +#define I3C_MERRWARN_OWRITE_MASK (0x20000U) +#define I3C_MERRWARN_OWRITE_SHIFT (17U) +/*! OWRITE - Overwrite Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_OWRITE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_OWRITE_SHIFT)) & I3C_MERRWARN_OWRITE_MASK) + +#define I3C_MERRWARN_MSGERR_MASK (0x40000U) +#define I3C_MERRWARN_MSGERR_SHIFT (18U) +/*! MSGERR - Message Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_MSGERR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_MSGERR_SHIFT)) & I3C_MERRWARN_MSGERR_MASK) + +#define I3C_MERRWARN_INVREQ_MASK (0x80000U) +#define I3C_MERRWARN_INVREQ_SHIFT (19U) +/*! INVREQ - Invalid Request Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_INVREQ(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_INVREQ_SHIFT)) & I3C_MERRWARN_INVREQ_MASK) + +#define I3C_MERRWARN_TIMEOUT_MASK (0x100000U) +#define I3C_MERRWARN_TIMEOUT_SHIFT (20U) +/*! TIMEOUT - Timeout Error + * 0b1..Error + * 0b0..No error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define I3C_MERRWARN_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MERRWARN_TIMEOUT_SHIFT)) & I3C_MERRWARN_TIMEOUT_MASK) +/*! @} */ + +/*! @name MDMACTRL - Controller DMA Control */ +/*! @{ */ + +#define I3C_MDMACTRL_DMAFB_MASK (0x3U) +#define I3C_MDMACTRL_DMAFB_SHIFT (0U) +/*! DMAFB - DMA from Bus + * 0b00..DMA not used + * 0b01..Enable DMA for one frame + * 0b10..Enable DMA until DMA is turned off + * 0b11.. + */ +#define I3C_MDMACTRL_DMAFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAFB_SHIFT)) & I3C_MDMACTRL_DMAFB_MASK) + +#define I3C_MDMACTRL_DMATB_MASK (0xCU) +#define I3C_MDMACTRL_DMATB_SHIFT (2U) +/*! DMATB - DMA to Bus + * 0b00..DMA not used + * 0b01..Enable DMA for one frame (ended by DMA or terminated) + * 0b10..Enable DMA until DMA is turned off + * 0b11.. + */ +#define I3C_MDMACTRL_DMATB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMATB_SHIFT)) & I3C_MDMACTRL_DMATB_MASK) + +#define I3C_MDMACTRL_DMAWIDTH_MASK (0x30U) +#define I3C_MDMACTRL_DMAWIDTH_SHIFT (4U) +/*! DMAWIDTH - DMA Width + * 0b00, 0b01..Byte + * 0b10..Halfword (16 bits) + * 0b11.. + */ +#define I3C_MDMACTRL_DMAWIDTH(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDMACTRL_DMAWIDTH_SHIFT)) & I3C_MDMACTRL_DMAWIDTH_MASK) +/*! @} */ + +/*! @name MDATACTRL - Controller Data Control */ +/*! @{ */ + +#define I3C_MDATACTRL_FLUSHTB_MASK (0x1U) +#define I3C_MDATACTRL_FLUSHTB_SHIFT (0U) +/*! FLUSHTB - Flush To-Bus Buffer or FIFO + * 0b1..Flush the buffer + * 0b0..No action + */ +#define I3C_MDATACTRL_FLUSHTB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHTB_SHIFT)) & I3C_MDATACTRL_FLUSHTB_MASK) + +#define I3C_MDATACTRL_FLUSHFB_MASK (0x2U) +#define I3C_MDATACTRL_FLUSHFB_SHIFT (1U) +/*! FLUSHFB - Flush From-Bus Buffer or FIFO + * 0b1..Flush the buffer + * 0b0..No action + */ +#define I3C_MDATACTRL_FLUSHFB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_FLUSHFB_SHIFT)) & I3C_MDATACTRL_FLUSHFB_MASK) + +#define I3C_MDATACTRL_UNLOCK_MASK (0x8U) +#define I3C_MDATACTRL_UNLOCK_SHIFT (3U) +/*! UNLOCK - Unlock + * 0b0..Locked + * 0b1..Unlocked + */ +#define I3C_MDATACTRL_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_UNLOCK_SHIFT)) & I3C_MDATACTRL_UNLOCK_MASK) + +#define I3C_MDATACTRL_TXTRIG_MASK (0x30U) +#define I3C_MDATACTRL_TXTRIG_SHIFT (4U) +/*! TXTRIG - Transmit Trigger Level + * 0b00..Trigger when empty + * 0b01..Trigger when 1/4 full or less + * 0b10..Trigger when 1/2 full or less + * 0b11..Trigger when 1 less than full or less (default) + */ +#define I3C_MDATACTRL_TXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXTRIG_SHIFT)) & I3C_MDATACTRL_TXTRIG_MASK) + +#define I3C_MDATACTRL_RXTRIG_MASK (0xC0U) +#define I3C_MDATACTRL_RXTRIG_SHIFT (6U) +/*! RXTRIG - Receive Trigger Level + * 0b00..Trigger when not empty + * 0b01..Trigger when 1/4 full or more + * 0b10..Trigger when 1/2 full or more + * 0b11..Trigger when 3/4 full or more + */ +#define I3C_MDATACTRL_RXTRIG(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXTRIG_SHIFT)) & I3C_MDATACTRL_RXTRIG_MASK) + +#define I3C_MDATACTRL_TXCOUNT_MASK (0x1F0000U) +#define I3C_MDATACTRL_TXCOUNT_SHIFT (16U) +/*! TXCOUNT - Transmit Byte Count */ +#define I3C_MDATACTRL_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXCOUNT_SHIFT)) & I3C_MDATACTRL_TXCOUNT_MASK) + +#define I3C_MDATACTRL_RXCOUNT_MASK (0x1F000000U) +#define I3C_MDATACTRL_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - Receive Byte Count */ +#define I3C_MDATACTRL_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXCOUNT_SHIFT)) & I3C_MDATACTRL_RXCOUNT_MASK) + +#define I3C_MDATACTRL_TXFULL_MASK (0x40000000U) +#define I3C_MDATACTRL_TXFULL_SHIFT (30U) +/*! TXFULL - Transmit is Full + * 0b0..Not full + * 0b1..Full + */ +#define I3C_MDATACTRL_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_TXFULL_SHIFT)) & I3C_MDATACTRL_TXFULL_MASK) + +#define I3C_MDATACTRL_RXEMPTY_MASK (0x80000000U) +#define I3C_MDATACTRL_RXEMPTY_SHIFT (31U) +/*! RXEMPTY - Receive is Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define I3C_MDATACTRL_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDATACTRL_RXEMPTY_SHIFT)) & I3C_MDATACTRL_RXEMPTY_MASK) +/*! @} */ + +/*! @name MWDATAB - Controller Write Data Byte */ +/*! @{ */ + +#define I3C_MWDATAB_VALUE_MASK (0xFFU) +#define I3C_MWDATAB_VALUE_SHIFT (0U) +/*! VALUE - Data Byte */ +#define I3C_MWDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_VALUE_SHIFT)) & I3C_MWDATAB_VALUE_MASK) + +#define I3C_MWDATAB_END_MASK (0x100U) +#define I3C_MWDATAB_END_SHIFT (8U) +/*! END - End of Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWDATAB_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_SHIFT)) & I3C_MWDATAB_END_MASK) + +#define I3C_MWDATAB_END_ALSO_MASK (0x10000U) +#define I3C_MWDATAB_END_ALSO_SHIFT (16U) +/*! END_ALSO - End of Message ALSO + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWDATAB_END_ALSO(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB_END_ALSO_SHIFT)) & I3C_MWDATAB_END_ALSO_MASK) +/*! @} */ + +/*! @name MWDATABE - Controller Write Data Byte End */ +/*! @{ */ + +#define I3C_MWDATABE_VALUE_MASK (0xFFU) +#define I3C_MWDATABE_VALUE_SHIFT (0U) +/*! VALUE - Data */ +#define I3C_MWDATABE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATABE_VALUE_SHIFT)) & I3C_MWDATABE_VALUE_MASK) +/*! @} */ + +/*! @name MWDATAH - Controller Write Data Halfword */ +/*! @{ */ + +#define I3C_MWDATAH_DATA0_MASK (0xFFU) +#define I3C_MWDATAH_DATA0_SHIFT (0U) +/*! DATA0 - Data Byte 0 */ +#define I3C_MWDATAH_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA0_SHIFT)) & I3C_MWDATAH_DATA0_MASK) + +#define I3C_MWDATAH_DATA1_MASK (0xFF00U) +#define I3C_MWDATAH_DATA1_SHIFT (8U) +/*! DATA1 - Data Byte 1 */ +#define I3C_MWDATAH_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_DATA1_SHIFT)) & I3C_MWDATAH_DATA1_MASK) + +#define I3C_MWDATAH_END_MASK (0x10000U) +#define I3C_MWDATAH_END_SHIFT (16U) +/*! END - End of Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWDATAH_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH_END_SHIFT)) & I3C_MWDATAH_END_MASK) +/*! @} */ + +/*! @name MWDATAHE - Controller Write Data Halfword End */ +/*! @{ */ + +#define I3C_MWDATAHE_DATA0_MASK (0xFFU) +#define I3C_MWDATAHE_DATA0_SHIFT (0U) +/*! DATA0 - Data Byte 0 */ +#define I3C_MWDATAHE_DATA0(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA0_SHIFT)) & I3C_MWDATAHE_DATA0_MASK) + +#define I3C_MWDATAHE_DATA1_MASK (0xFF00U) +#define I3C_MWDATAHE_DATA1_SHIFT (8U) +/*! DATA1 - Data Byte 1 */ +#define I3C_MWDATAHE_DATA1(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAHE_DATA1_SHIFT)) & I3C_MWDATAHE_DATA1_MASK) +/*! @} */ + +/*! @name MRDATAB - Controller Read Data Byte */ +/*! @{ */ + +#define I3C_MRDATAB_VALUE_MASK (0xFFU) +#define I3C_MRDATAB_VALUE_SHIFT (0U) +/*! VALUE - Value */ +#define I3C_MRDATAB_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAB_VALUE_SHIFT)) & I3C_MRDATAB_VALUE_MASK) +/*! @} */ + +/*! @name MRDATAH - Controller Read Data Halfword */ +/*! @{ */ + +#define I3C_MRDATAH_LSB_MASK (0xFFU) +#define I3C_MRDATAH_LSB_SHIFT (0U) +/*! LSB - Low Byte */ +#define I3C_MRDATAH_LSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_LSB_SHIFT)) & I3C_MRDATAH_LSB_MASK) + +#define I3C_MRDATAH_MSB_MASK (0xFF00U) +#define I3C_MRDATAH_MSB_SHIFT (8U) +/*! MSB - High Byte */ +#define I3C_MRDATAH_MSB(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRDATAH_MSB_SHIFT)) & I3C_MRDATAH_MSB_MASK) +/*! @} */ + +/*! @name MWDATAB1 - Controller Write Byte Data 1 (to Bus) */ +/*! @{ */ + +#define I3C_MWDATAB1_VALUE_MASK (0xFFU) +#define I3C_MWDATAB1_VALUE_SHIFT (0U) +/*! VALUE - Value */ +#define I3C_MWDATAB1_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAB1_VALUE_SHIFT)) & I3C_MWDATAB1_VALUE_MASK) +/*! @} */ + +/*! @name MWDATAH1 - Controller Write Halfword Data (to Bus) */ +/*! @{ */ + +#define I3C_MWDATAH1_VALUE_MASK (0xFFFFU) +#define I3C_MWDATAH1_VALUE_SHIFT (0U) +/*! VALUE - Value */ +#define I3C_MWDATAH1_VALUE(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWDATAH1_VALUE_SHIFT)) & I3C_MWDATAH1_VALUE_MASK) +/*! @} */ + +/*! @name MWMSG_SDR_CONTROL - Controller Write Message Control in SDR mode */ +/*! @{ */ + +#define I3C_MWMSG_SDR_CONTROL_DIR_MASK (0x1U) +#define I3C_MWMSG_SDR_CONTROL_DIR_SHIFT (0U) +/*! DIR - Direction + * 0b0..Write + * 0b1..Read + */ +#define I3C_MWMSG_SDR_CONTROL_DIR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_DIR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_DIR_MASK) + +#define I3C_MWMSG_SDR_CONTROL_ADDR_MASK (0xFEU) +#define I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT (1U) +/*! ADDR - Address */ +#define I3C_MWMSG_SDR_CONTROL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_ADDR_SHIFT)) & I3C_MWMSG_SDR_CONTROL_ADDR_MASK) + +#define I3C_MWMSG_SDR_CONTROL_END_MASK (0x100U) +#define I3C_MWMSG_SDR_CONTROL_END_SHIFT (8U) +/*! END - End of SDR Message + * 0b0..Not the end + * 0b1..End + */ +#define I3C_MWMSG_SDR_CONTROL_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_END_SHIFT)) & I3C_MWMSG_SDR_CONTROL_END_MASK) + +#define I3C_MWMSG_SDR_CONTROL_I2C_MASK (0x400U) +#define I3C_MWMSG_SDR_CONTROL_I2C_SHIFT (10U) +/*! I2C - I2C + * 0b0..I3C message + * 0b1..I2C message + */ +#define I3C_MWMSG_SDR_CONTROL_I2C(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_I2C_SHIFT)) & I3C_MWMSG_SDR_CONTROL_I2C_MASK) + +#define I3C_MWMSG_SDR_CONTROL_LEN_MASK (0xF800U) +#define I3C_MWMSG_SDR_CONTROL_LEN_SHIFT (11U) +/*! LEN - Length */ +#define I3C_MWMSG_SDR_CONTROL_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_CONTROL_LEN_SHIFT)) & I3C_MWMSG_SDR_CONTROL_LEN_MASK) +/*! @} */ + +/*! @name MWMSG_SDR_DATA - Controller Write Message Data in SDR mode */ +/*! @{ */ + +#define I3C_MWMSG_SDR_DATA_DATA16B_MASK (0xFFFFU) +#define I3C_MWMSG_SDR_DATA_DATA16B_SHIFT (0U) +/*! DATA16B - Data */ +#define I3C_MWMSG_SDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_SDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_SDR_DATA_DATA16B_MASK) +/*! @} */ + +/*! @name MRMSG_SDR - Controller Read Message in SDR mode */ +/*! @{ */ + +#define I3C_MRMSG_SDR_DATA_MASK (0xFFFFU) +#define I3C_MRMSG_SDR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_MRMSG_SDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_SDR_DATA_SHIFT)) & I3C_MRMSG_SDR_DATA_MASK) +/*! @} */ + +/*! @name MWMSG_DDR_CONTROL - Controller Write Message in DDR mode: First Control Word */ +/*! @{ */ + +#define I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK (0xFFFFU) +#define I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT (0U) +/*! ADDRCMD - Address Command */ +#define I3C_MWMSG_DDR_CONTROL_ADDRCMD(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL_ADDRCMD_SHIFT)) & I3C_MWMSG_DDR_CONTROL_ADDRCMD_MASK) +/*! @} */ + +/*! @name MWMSG_DDR_CONTROL2 - Controller Write Message in DDR Mode Control 2 */ +/*! @{ */ + +#define I3C_MWMSG_DDR_CONTROL2_LEN_MASK (0x3FFU) +#define I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT (0U) +/*! LEN - Length of Message */ +#define I3C_MWMSG_DDR_CONTROL2_LEN(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_LEN_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_LEN_MASK) + +#define I3C_MWMSG_DDR_CONTROL2_END_MASK (0x4000U) +#define I3C_MWMSG_DDR_CONTROL2_END_SHIFT (14U) +/*! END - End of Message + * 0b1..End + * 0b0..Not the end + */ +#define I3C_MWMSG_DDR_CONTROL2_END(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_CONTROL2_END_SHIFT)) & I3C_MWMSG_DDR_CONTROL2_END_MASK) +/*! @} */ + +/*! @name MWMSG_DDR_DATA - Controller Write Message Data in DDR mode */ +/*! @{ */ + +#define I3C_MWMSG_DDR_DATA_DATA16B_MASK (0xFFFFU) +#define I3C_MWMSG_DDR_DATA_DATA16B_SHIFT (0U) +/*! DATA16B - Data */ +#define I3C_MWMSG_DDR_DATA_DATA16B(x) (((uint32_t)(((uint32_t)(x)) << I3C_MWMSG_DDR_DATA_DATA16B_SHIFT)) & I3C_MWMSG_DDR_DATA_DATA16B_MASK) +/*! @} */ + +/*! @name MRMSG_DDR - Controller Read Message in DDR mode */ +/*! @{ */ + +#define I3C_MRMSG_DDR_DATA_MASK (0xFFFFU) +#define I3C_MRMSG_DDR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define I3C_MRMSG_DDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << I3C_MRMSG_DDR_DATA_SHIFT)) & I3C_MRMSG_DDR_DATA_MASK) +/*! @} */ + +/*! @name MDYNADDR - Controller Dynamic Address */ +/*! @{ */ + +#define I3C_MDYNADDR_DAVALID_MASK (0x1U) +#define I3C_MDYNADDR_DAVALID_SHIFT (0U) +/*! DAVALID - Dynamic Address Valid + * 0b1..Valid DA assigned + * 0b0..No valid DA assigned + */ +#define I3C_MDYNADDR_DAVALID(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DAVALID_SHIFT)) & I3C_MDYNADDR_DAVALID_MASK) + +#define I3C_MDYNADDR_DADDR_MASK (0xFEU) +#define I3C_MDYNADDR_DADDR_SHIFT (1U) +/*! DADDR - Dynamic Address */ +#define I3C_MDYNADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << I3C_MDYNADDR_DADDR_SHIFT)) & I3C_MDYNADDR_DADDR_MASK) +/*! @} */ + +/*! @name SMAPCTRL0 - Map Feature Control 0 */ +/*! @{ */ + +#define I3C_SMAPCTRL0_ENA_MASK (0x1U) +#define I3C_SMAPCTRL0_ENA_SHIFT (0U) +/*! ENA - Enable Primary Dynamic Address + * 0b0..Disabled + * 0b1..Enabled + */ +#define I3C_SMAPCTRL0_ENA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_ENA_SHIFT)) & I3C_SMAPCTRL0_ENA_MASK) + +#define I3C_SMAPCTRL0_DA_MASK (0xFEU) +#define I3C_SMAPCTRL0_DA_SHIFT (1U) +/*! DA - Dynamic Address */ +#define I3C_SMAPCTRL0_DA(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_DA_SHIFT)) & I3C_SMAPCTRL0_DA_MASK) + +#define I3C_SMAPCTRL0_CAUSE_MASK (0x700U) +#define I3C_SMAPCTRL0_CAUSE_SHIFT (8U) +/*! CAUSE - Cause + * 0b000..No information (this value occurs when not configured to write DA) + * 0b001..Set using ENTDAA + * 0b010..Set using SETDASA, SETAASA, or SETNEWDA + * 0b011..Cleared using RSTDAA + * 0b100..Auto MAP change happened last + * *.. + */ +#define I3C_SMAPCTRL0_CAUSE(x) (((uint32_t)(((uint32_t)(x)) << I3C_SMAPCTRL0_CAUSE_SHIFT)) & I3C_SMAPCTRL0_CAUSE_MASK) +/*! @} */ + +/*! @name IBIEXT1 - Extended IBI Data 1 */ +/*! @{ */ + +#define I3C_IBIEXT1_CNT_MASK (0x7U) +#define I3C_IBIEXT1_CNT_SHIFT (0U) +/*! CNT - Count */ +#define I3C_IBIEXT1_CNT(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_CNT_SHIFT)) & I3C_IBIEXT1_CNT_MASK) + +#define I3C_IBIEXT1_MAX_MASK (0x70U) +#define I3C_IBIEXT1_MAX_SHIFT (4U) +/*! MAX - Maximum */ +#define I3C_IBIEXT1_MAX(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_MAX_SHIFT)) & I3C_IBIEXT1_MAX_MASK) + +#define I3C_IBIEXT1_EXT1_MASK (0xFF00U) +#define I3C_IBIEXT1_EXT1_SHIFT (8U) +/*! EXT1 - Extra Byte 1 */ +#define I3C_IBIEXT1_EXT1(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT1_SHIFT)) & I3C_IBIEXT1_EXT1_MASK) + +#define I3C_IBIEXT1_EXT2_MASK (0xFF0000U) +#define I3C_IBIEXT1_EXT2_SHIFT (16U) +/*! EXT2 - Extra Byte 2 */ +#define I3C_IBIEXT1_EXT2(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT2_SHIFT)) & I3C_IBIEXT1_EXT2_MASK) + +#define I3C_IBIEXT1_EXT3_MASK (0xFF000000U) +#define I3C_IBIEXT1_EXT3_SHIFT (24U) +/*! EXT3 - Extra Byte 3 */ +#define I3C_IBIEXT1_EXT3(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT1_EXT3_SHIFT)) & I3C_IBIEXT1_EXT3_MASK) +/*! @} */ + +/*! @name IBIEXT2 - Extended IBI Data 2 */ +/*! @{ */ + +#define I3C_IBIEXT2_EXT4_MASK (0xFFU) +#define I3C_IBIEXT2_EXT4_SHIFT (0U) +/*! EXT4 - Extra Byte 4 */ +#define I3C_IBIEXT2_EXT4(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT4_SHIFT)) & I3C_IBIEXT2_EXT4_MASK) + +#define I3C_IBIEXT2_EXT5_MASK (0xFF00U) +#define I3C_IBIEXT2_EXT5_SHIFT (8U) +/*! EXT5 - Extra Byte 5 */ +#define I3C_IBIEXT2_EXT5(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT5_SHIFT)) & I3C_IBIEXT2_EXT5_MASK) + +#define I3C_IBIEXT2_EXT6_MASK (0xFF0000U) +#define I3C_IBIEXT2_EXT6_SHIFT (16U) +/*! EXT6 - Extra Byte 6 */ +#define I3C_IBIEXT2_EXT6(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT6_SHIFT)) & I3C_IBIEXT2_EXT6_MASK) + +#define I3C_IBIEXT2_EXT7_MASK (0xFF000000U) +#define I3C_IBIEXT2_EXT7_SHIFT (24U) +/*! EXT7 - Extra Byte 7 */ +#define I3C_IBIEXT2_EXT7(x) (((uint32_t)(((uint32_t)(x)) << I3C_IBIEXT2_EXT7_SHIFT)) & I3C_IBIEXT2_EXT7_MASK) +/*! @} */ + +/*! @name SID - Target Module ID */ +/*! @{ */ + +#define I3C_SID_ID_MASK (0xFFFFFFFFU) +#define I3C_SID_ID_SHIFT (0U) +/*! ID - ID */ +#define I3C_SID_ID(x) (((uint32_t)(((uint32_t)(x)) << I3C_SID_ID_SHIFT)) & I3C_SID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I3C_Register_Masks */ + + +/* I3C - Peripheral instance base addresses */ +/** Peripheral I3C0 base address */ +#define I3C0_BASE (0x40002000u) +/** Peripheral I3C0 base pointer */ +#define I3C0 ((I3C_Type *)I3C0_BASE) +/** Array initializer of I3C peripheral base addresses */ +#define I3C_BASE_ADDRS { I3C0_BASE } +/** Array initializer of I3C peripheral base pointers */ +#define I3C_BASE_PTRS { I3C0 } +/** Interrupt vectors for the I3C peripheral type */ +#define I3C_IRQS { I3C0_IRQn } + +/*! + * @} + */ /* end of group I3C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer + * @{ + */ + +/** INPUTMUX - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[32]; + __IO uint32_t CTIMER0CAP[4]; /**< Capture select register for CTIMER inputs, array offset: 0x20, array step: 0x4 */ + __IO uint32_t TIMER0TRIG; /**< Trigger register for TIMER0, offset: 0x30 */ + uint8_t RESERVED_1[12]; + __IO uint32_t CTIMER1CAP[4]; /**< Capture select register for CTIMER inputs, array offset: 0x40, array step: 0x4 */ + __IO uint32_t TIMER1TRIG; /**< Trigger register for TIMER1, offset: 0x50 */ + uint8_t RESERVED_2[12]; + __IO uint32_t CTIMER2CAP[4]; /**< Capture select register for CTIMER inputs, array offset: 0x60, array step: 0x4 */ + __IO uint32_t TIMER2TRIG; /**< Trigger register for TIMER2 inputs, offset: 0x70 */ + uint8_t RESERVED_3[268]; + __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ + __IO uint32_t FREQMEAS_TAR; /**< Selection for frequency measurement reference clock, offset: 0x184 */ + uint8_t RESERVED_4[24]; + __IO uint32_t CTIMER3CAP[4]; /**< Capture select register for CTIMER inputs, array offset: 0x1A0, array step: 0x4 */ + __IO uint32_t TIMER3TRIG; /**< Trigger register for TIMER3, offset: 0x1B0 */ + uint8_t RESERVED_5[12]; + __IO uint32_t CTIMER4CAP[4]; /**< Capture select register for CTIMER inputs, array offset: 0x1C0, array step: 0x4 */ + __IO uint32_t TIMER4TRIG; /**< Trigger register for TIMER4, offset: 0x1D0 */ + uint8_t RESERVED_6[44]; + __IO uint32_t AOI1_INPUT[16]; /**< AOI1 trigger input connections 0, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_7[32]; + __IO uint32_t CMP0_TRIG; /**< CMP0 input connections, offset: 0x260 */ + uint8_t RESERVED_8[28]; + __IO uint32_t ADC0_TRIG[4]; /**< ADC Trigger input connections, array offset: 0x280, array step: 0x4 */ + uint8_t RESERVED_9[48]; + __IO uint32_t ADC1_TRIG[4]; /**< ADC Trigger input connections, array offset: 0x2C0, array step: 0x4 */ + uint8_t RESERVED_10[48]; + __IO uint32_t DAC0_TRIG; /**< This register selects the DAC0 trigger inputs., offset: 0x300 */ + uint8_t RESERVED_11[92]; + __IO uint32_t QDC0_TRIG; /**< QDC0 Trigger Input Connections, offset: 0x360 */ + __IO uint32_t QDC0_HOME; /**< QDC0 Trigger Input Connections, offset: 0x364 */ + __IO uint32_t QDC0_INDEX; /**< QDC0 Trigger Input Connections, offset: 0x368 */ + __IO uint32_t QDC0_PHASEB; /**< QDC0 Trigger Input Connections, offset: 0x36C */ + __IO uint32_t QDC0_PHASEA; /**< QDC0 Trigger Input Connections, offset: 0x370 */ + __IO uint32_t QDC0_ICAP1; /**< QDC0 Trigger Input Connections, offset: 0x374 */ + __IO uint32_t QDC0_ICAP2; /**< QDC0 Trigger Input Connections, offset: 0x378 */ + __IO uint32_t QDC0_ICAP3; /**< QDC0 Trigger Input Connections, offset: 0x37C */ + __IO uint32_t QDC1_TRIG; /**< QDC1 Trigger Input Connections, offset: 0x380 */ + __IO uint32_t QDC1_HOME; /**< QDC1 Trigger Input Connections, offset: 0x384 */ + __IO uint32_t QDC1_INDEX; /**< QDC1 Trigger Input Connections, offset: 0x388 */ + __IO uint32_t QDC1_PHASEB; /**< QDC1 Trigger Input Connections, offset: 0x38C */ + __IO uint32_t QDC1_PHASEA; /**< QDC1 Trigger Input Connections, offset: 0x390 */ + __IO uint32_t QDC1_ICAP1; /**< QDC1 Trigger Input Connections, offset: 0x394 */ + __IO uint32_t QDC1_ICAP2; /**< QDC1 Trigger Input Connections, offset: 0x398 */ + __IO uint32_t QDC1_ICAP3; /**< QDC1 Trigger Input Connections, offset: 0x39C */ + __IO uint32_t FLEXPWM0_SM0_EXTA0; /**< PWM0 input trigger connections, offset: 0x3A0 */ + __IO uint32_t FLEXPWM0_SM0_EXTSYNC; /**< PWM0 input trigger connections, offset: 0x3A4 */ + __IO uint32_t FLEXPWM0_SM1_EXTA; /**< PWM0 input trigger connections, offset: 0x3A8 */ + __IO uint32_t FLEXPWM0_SM1_EXTSYNC; /**< PWM0 input trigger connections, offset: 0x3AC */ + __IO uint32_t FLEXPWM0_SM2_EXTA; /**< PWM0 input trigger connections, offset: 0x3B0 */ + __IO uint32_t FLEXPWM0_SM2_EXTSYNC; /**< PWM0 input trigger connections, offset: 0x3B4 */ + uint8_t RESERVED_12[8]; + __IO uint32_t FLEXPWM0_FAULT[4]; /**< PWM0 Fault Input Trigger Connections, array offset: 0x3C0, array step: 0x4 */ + __IO uint32_t FLEXPWM0_FORCE; /**< PWM0 input trigger connections, offset: 0x3D0 */ + uint8_t RESERVED_13[12]; + __IO uint32_t FLEXPWM1_SM0_EXTA0; /**< PWM1 input trigger connections, offset: 0x3E0 */ + __IO uint32_t FLEXPWM1_SM0_EXTSYNC; /**< PWM1 input trigger connections, offset: 0x3E4 */ + __IO uint32_t FLEXPWM1_SM1_EXTA; /**< PWM1 input trigger connections, offset: 0x3E8 */ + __IO uint32_t FLEXPWM1_SM1_EXTSYNC; /**< PWM1 input trigger connections, offset: 0x3EC */ + __IO uint32_t FLEXPWM1_SM2_EXTA; /**< PWM1 input trigger connections, offset: 0x3F0 */ + __IO uint32_t FLEXPWM1_SM2_EXTSYNC; /**< PWM1 input trigger connections, offset: 0x3F4 */ + uint8_t RESERVED_14[8]; + __IO uint32_t FLEXPWM1_FAULT[4]; /**< PWM1 Fault Input Trigger Connections, array offset: 0x400, array step: 0x4 */ + __IO uint32_t FLEXPWM1_FORCE; /**< PWM1 input trigger connections, offset: 0x410 */ + uint8_t RESERVED_15[12]; + __IO uint32_t PWM0_EXT_CLK; /**< PWM0 external clock trigger, offset: 0x420 */ + __IO uint32_t PWM1_EXT_CLK; /**< PWM1 external clock trigger, offset: 0x424 */ + uint8_t RESERVED_16[24]; + __IO uint32_t AOI0_INPUT[16]; /**< AOI0 trigger input connections 0, array offset: 0x440, array step: 0x4 */ + __IO uint32_t USBFS_TRIG; /**< USB-FS trigger input connections, offset: 0x480 */ + uint8_t RESERVED_17[60]; + __IO uint32_t EXT_TRIG0; /**< EXT trigger connections 0, offset: 0x4C0 */ + uint8_t RESERVED_18[28]; + __IO uint32_t CMP1_TRIG; /**< CMP1 input connections, offset: 0x4E0 */ + uint8_t RESERVED_19[92]; + __IO uint32_t LPI2C2_TRIG; /**< LPI2C2 trigger input connections, offset: 0x540 */ + uint8_t RESERVED_20[60]; + __IO uint32_t OPAMP0_TRIG; /**< OPAMP0 Trigger Input Connections, offset: 0x580 */ + uint8_t RESERVED_21[28]; + __IO uint32_t LPI2C0_TRIG; /**< LPI2C0 trigger input connections, offset: 0x5A0 */ + uint8_t RESERVED_22[28]; + __IO uint32_t LPI2C1_TRIG; /**< LPI2C1 trigger input connections, offset: 0x5C0 */ + uint8_t RESERVED_23[28]; + __IO uint32_t LPSPI0_TRIG; /**< LPSPI0 trigger input connections, offset: 0x5E0 */ + uint8_t RESERVED_24[28]; + __IO uint32_t LPSPI1_TRIG; /**< LPSPI1 trigger input connections, offset: 0x600 */ + uint8_t RESERVED_25[28]; + __IO uint32_t LPUART0r; /**< LPUART0 trigger input connections, offset: 0x620, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART0' */ + uint8_t RESERVED_26[28]; + __IO uint32_t LPUART1r; /**< LPUART1 trigger input connections, offset: 0x640, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART1' */ + uint8_t RESERVED_27[28]; + __IO uint32_t LPUART2r; /**< LPUART2 trigger input connections, offset: 0x660, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART2' */ + uint8_t RESERVED_28[28]; + __IO uint32_t LPUART3r; /**< LPUART3 trigger input connections, offset: 0x680, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART3' */ + uint8_t RESERVED_29[28]; + __IO uint32_t LPUART4r; /**< LPUART4 trigger input connections, offset: 0x6A0, 'r' suffix has been added to avoid a clash with peripheral base pointer macro 'LPUART4' */ + uint8_t RESERVED_30[60]; + __IO uint32_t FLEXIO_TRIG[4]; /**< FlexIO Trigger Input Connections, array offset: 0x6E0, array step: 0x4 */ +} INPUTMUX_Type; + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks + * @{ + */ + +/*! @name CTIMERA_CTIMER0CAP - Capture select register for CTIMER inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMERA_CTIMER0CAP_INP_MASK (0x7FU) +#define INPUTMUX_CTIMERA_CTIMER0CAP_INP_SHIFT (0U) +/*! INP - Input number for CTIMER0 + * 0b0000000..Reserved + * 0b0000001..CT_IPN0 input is selected + * 0b0000010..CT_IPN1 input is selected + * 0b0000011..CT_IPN2 input is selected + * 0b0000100..CT_IPN3 input is selected + * 0b0000101..CT_IPN4 input is selected + * 0b0000110..CT_IPN5 input is selected + * 0b0000111..CT_IPN6 input is selected + * 0b0001000..CT_IPN7 input is selected + * 0b0001001..CT_IPN8 input is selected + * 0b0001010..CT_IPN9 input is selected + * 0b0001011..CT_IPN10 input is selected + * 0b0001100..CT_IPN11 input is selected + * 0b0001101..CT_IPN12 input is selected + * 0b0001110..CT_IPN13 input is selected + * 0b0001111..CT_IPN14 input is selected + * 0b0010000..CT_IPN15 input is selected + * 0b0010001..CT_IPN16 input is selected + * 0b0010010..CT_IPN17 input is selected + * 0b0010011..CT_IPN18 input is selected + * 0b0010100..CT_IPN19 input is selected + * 0b0010101..USB0 usb0 start of frame input is selected + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..Reserved + * 0b0100001..CTimer1_MAT1 input is selected + * 0b0100010..CTimer1_MAT2 input is selected + * 0b0100011..CTimer1_MAT3 input is selected + * 0b0100100..CTimer2_MAT1 input is selected + * 0b0100101..CTimer2_MAT2 input is selected + * 0b0100110..CTimer2_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..Reserved + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..LPUART4 Received Data Word input is selected + * 0b1000101..LPUART4 Transmitted Data Word input is selected + * 0b1000110..LPUART4 Receive Line Idle input is selected + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..CTimer3_MAT1 input is selected + * 0b1010000..CTimer3_MAT2 input is selected + * 0b1010001..CTimer3_MAT3 input is selected + * 0b1010010..CTimer4_MAT1 input is selected + * 0b1010011..CTimer4_MAT2 input is selected + * 0b1010100..CTimer4_MAT3 input is selected + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..Reserved + * 0b1011110..LPI2C2 Master End of Packet input is selected + * 0b1011111..LPI2C2 Slave End of Packet input is selected + * 0b1100000..LPI2C3 Master End of Packet input is selected + * 0b1100001..LPI2C3 Slave End of Packet input is selected + * *.. + */ +#define INPUTMUX_CTIMERA_CTIMER0CAP_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMERA_CTIMER0CAP_INP_SHIFT)) & INPUTMUX_CTIMERA_CTIMER0CAP_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_CTIMERA_CTIMER0CAP */ +#define INPUTMUX_CTIMERA_CTIMER0CAP_COUNT (4U) + +/*! @name TIMER0TRIG - Trigger register for TIMER0 */ +/*! @{ */ + +#define INPUTMUX_TIMER0TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER0TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER0 + * 0b0000000..Reserved + * 0b0000001..CT_IPN0 input is selected + * 0b0000010..CT_IPN1 input is selected + * 0b0000011..CT_IPN2 input is selected + * 0b0000100..CT_IPN3 input is selected + * 0b0000101..CT_IPN4 input is selected + * 0b0000110..CT_IPN5 input is selected + * 0b0000111..CT_IPN6 input is selected + * 0b0001000..CT_IPN7 input is selected + * 0b0001001..CT_IPN8 input is selected + * 0b0001010..CT_IPN9 input is selected + * 0b0001011..CT_IPN10 input is selected + * 0b0001100..CT_IPN11 input is selected + * 0b0001101..CT_IPN12 input is selected + * 0b0001110..CT_IPN13 input is selected + * 0b0001111..CT_IPN14 input is selected + * 0b0010000..CT_IPN15 input is selected + * 0b0010001..CT_IPN16 input is selected + * 0b0010010..CT_IPN17 input is selected + * 0b0010011..CT_IPN18 input is selected + * 0b0010100..CT_IPN19 input is selected + * 0b0010101..USB0 usb0 start of frame input is selected + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..Reserved + * 0b0100001..CTimer1_MAT1 input is selected + * 0b0100010..CTimer1_MAT2 input is selected + * 0b0100011..CTimer1_MAT3 input is selected + * 0b0100100..CTimer2_MAT1 input is selected + * 0b0100101..CTimer2_MAT2 input is selected + * 0b0100110..CTimer2_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..Reserved + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..LPUART4 Received Data Word input is selected + * 0b1000101..LPUART4 Transmitted Data Word input is selected + * 0b1000110..LPUART4 Receive Line Idle input is selected + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..CTimer3_MAT1 input is selected + * 0b1010000..CTimer3_MAT2 input is selected + * 0b1010001..CTimer3_MAT3 input is selected + * 0b1010010..CTimer4_MAT1 input is selected + * 0b1010011..CTimer4_MAT2 input is selected + * 0b1010100..CTimer4_MAT3 input is selected + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..Reserved + * 0b1011110..LPI2C2 Master End of Packet input is selected + * 0b1011111..LPI2C2 Slave End of Packet input is selected + * 0b1100000..LPI2C3 Master End of Packet input is selected + * 0b1100001..LPI2C3 Slave End of Packet input is selected + * *.. + */ +#define INPUTMUX_TIMER0TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER0TRIG_INP_SHIFT)) & INPUTMUX_TIMER0TRIG_INP_MASK) +/*! @} */ + +/*! @name CTIMERB_CTIMER1CAP - Capture select register for CTIMER inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMERB_CTIMER1CAP_INP_MASK (0x7FU) +#define INPUTMUX_CTIMERB_CTIMER1CAP_INP_SHIFT (0U) +/*! INP - Input number for CTIMER1 + * 0b0000000..Reserved + * 0b0000001..CT_IPN0 input is selected + * 0b0000010..CT_IPN1 input is selected + * 0b0000011..CT_IPN2 input is selected + * 0b0000100..CT_IPN3 input is selected + * 0b0000101..CT_IPN4 input is selected + * 0b0000110..CT_IPN5 input is selected + * 0b0000111..CT_IPN6 input is selected + * 0b0001000..CT_IPN7 input is selected + * 0b0001001..CT_IPN8 input is selected + * 0b0001010..CT_IPN9 input is selected + * 0b0001011..CT_IPN10 input is selected + * 0b0001100..CT_IPN11 input is selected + * 0b0001101..CT_IPN12 input is selected + * 0b0001110..CT_IPN13 input is selected + * 0b0001111..CT_IPN14 input is selected + * 0b0010000..CT_IPN15 input is selected + * 0b0010001..CT_IPN16 input is selected + * 0b0010010..CT_IPN17 input is selected + * 0b0010011..CT_IPN18 input is selected + * 0b0010100..CT_IPN19 input is selected + * 0b0010101..USB0 usb0 start of frame input is selected + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..Reserved + * 0b0100001..CTimer0_MAT1 input is selected + * 0b0100010..CTimer0_MAT2 input is selected + * 0b0100011..CTimer0_MAT3 input is selected + * 0b0100100..CTimer2_MAT1 input is selected + * 0b0100101..CTimer2_MAT2 input is selected + * 0b0100110..CTimer2_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..Reserved + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..LPUART4 Received Data Word input is selected + * 0b1000101..LPUART4 Transmitted Data Word input is selected + * 0b1000110..LPUART4 Receive Line Idle input is selected + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..CTimer3_MAT1 input is selected + * 0b1010000..CTimer3_MAT2 input is selected + * 0b1010001..CTimer3_MAT3 input is selected + * 0b1010010..CTimer4_MAT1 input is selected + * 0b1010011..CTimer4_MAT2 input is selected + * 0b1010100..CTimer4_MAT3 input is selected + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..Reserved + * 0b1011110..LPI2C2 Master End of Packet input is selected + * 0b1011111..LPI2C2 Slave End of Packet input is selected + * 0b1100000..LPI2C3 Master End of Packet input is selected + * 0b1100001..LPI2C3 Slave End of Packet input is selected + * *.. + */ +#define INPUTMUX_CTIMERB_CTIMER1CAP_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMERB_CTIMER1CAP_INP_SHIFT)) & INPUTMUX_CTIMERB_CTIMER1CAP_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_CTIMERB_CTIMER1CAP */ +#define INPUTMUX_CTIMERB_CTIMER1CAP_COUNT (4U) + +/*! @name TIMER1TRIG - Trigger register for TIMER1 */ +/*! @{ */ + +#define INPUTMUX_TIMER1TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER1TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER1 + * 0b0000000..Reserved + * 0b0000001..CT_IPN0 input is selected + * 0b0000010..CT_IPN1 input is selected + * 0b0000011..CT_IPN2 input is selected + * 0b0000100..CT_IPN3 input is selected + * 0b0000101..CT_IPN4 input is selected + * 0b0000110..CT_IPN5 input is selected + * 0b0000111..CT_IPN6 input is selected + * 0b0001000..CT_IPN7 input is selected + * 0b0001001..CT_IPN8 input is selected + * 0b0001010..CT_IPN9 input is selected + * 0b0001011..CT_IPN10 input is selected + * 0b0001100..CT_IPN11 input is selected + * 0b0001101..CT_IPN12 input is selected + * 0b0001110..CT_IPN13 input is selected + * 0b0001111..CT_IPN14 input is selected + * 0b0010000..CT_IPN15 input is selected + * 0b0010001..CT_IPN16 input is selected + * 0b0010010..CT_IPN17 input is selected + * 0b0010011..CT_IPN18 input is selected + * 0b0010100..CT_IPN19 input is selected + * 0b0010101..USB0 usb0 start of frame input is selected + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..Reserved + * 0b0100001..CTimer0_MAT1 input is selected + * 0b0100010..CTimer0_MAT2 input is selected + * 0b0100011..CTimer0_MAT3 input is selected + * 0b0100100..CTimer2_MAT1 input is selected + * 0b0100101..CTimer2_MAT2 input is selected + * 0b0100110..CTimer2_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..Reserved + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..LPUART4 Received Data Word input is selected + * 0b1000101..LPUART4 Transmitted Data Word input is selected + * 0b1000110..LPUART4 Receive Line Idle input is selected + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..CTimer3_MAT1 input is selected + * 0b1010000..CTimer3_MAT2 input is selected + * 0b1010001..CTimer3_MAT3 input is selected + * 0b1010010..CTimer4_MAT1 input is selected + * 0b1010011..CTimer4_MAT2 input is selected + * 0b1010100..CTimer4_MAT3 input is selected + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..Reserved + * 0b1011110..LPI2C2 Master End of Packet input is selected + * 0b1011111..LPI2C2 Slave End of Packet input is selected + * 0b1100000..LPI2C3 Master End of Packet input is selected + * 0b1100001..LPI2C3 Slave End of Packet input is selected + * *.. + */ +#define INPUTMUX_TIMER1TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER1TRIG_INP_SHIFT)) & INPUTMUX_TIMER1TRIG_INP_MASK) +/*! @} */ + +/*! @name CTIMERC_CTIMER2CAP - Capture select register for CTIMER inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMERC_CTIMER2CAP_INP_MASK (0x7FU) +#define INPUTMUX_CTIMERC_CTIMER2CAP_INP_SHIFT (0U) +/*! INP - Input number for CTIMER2 + * 0b0000000..Reserved + * 0b0000001..CT_IPN0 input is selected + * 0b0000010..CT_IPN1 input is selected + * 0b0000011..CT_IPN2 input is selected + * 0b0000100..CT_IPN3 input is selected + * 0b0000101..CT_IPN4 input is selected + * 0b0000110..CT_IPN5 input is selected + * 0b0000111..CT_IPN6 input is selected + * 0b0001000..CT_IPN7 input is selected + * 0b0001001..CT_IPN8 input is selected + * 0b0001010..CT_IPN9 input is selected + * 0b0001011..CT_IPN10 input is selected + * 0b0001100..CT_IPN11 input is selected + * 0b0001101..CT_IPN12 input is selected + * 0b0001110..CT_IPN13 input is selected + * 0b0001111..CT_IPN14 input is selected + * 0b0010000..CT_IPN15 input is selected + * 0b0010001..CT_IPN16 input is selected + * 0b0010010..CT_IPN17 input is selected + * 0b0010011..CT_IPN18 input is selected + * 0b0010100..CT_IPN19 input is selected + * 0b0010101..USB0 usb0 start of frame input is selected + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..Reserved + * 0b0100001..CTimer0_MAT1 input is selected + * 0b0100010..CTimer0_MAT2 input is selected + * 0b0100011..CTimer0_MAT3 input is selected + * 0b0100100..CTimer1_MAT1 input is selected + * 0b0100101..CTimer1_MAT2 input is selected + * 0b0100110..CTimer1_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..Reserved + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..LPUART4 Received Data Word input is selected + * 0b1000101..LPUART4 Transmitted Data Word input is selected + * 0b1000110..LPUART4 Receive Line Idle input is selected + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..CTimer3_MAT1 input is selected + * 0b1010000..CTimer3_MAT2 input is selected + * 0b1010001..CTimer3_MAT3 input is selected + * 0b1010010..CTimer4_MAT1 input is selected + * 0b1010011..CTimer4_MAT2 input is selected + * 0b1010100..CTimer4_MAT3 input is selected + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..Reserved + * 0b1011110..LPI2C2 Master End of Packet input is selected + * 0b1011111..LPI2C2 Slave End of Packet input is selected + * 0b1100000..LPI2C3 Master End of Packet input is selected + * 0b1100001..LPI2C3 Slave End of Packet input is selected + * *.. + */ +#define INPUTMUX_CTIMERC_CTIMER2CAP_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMERC_CTIMER2CAP_INP_SHIFT)) & INPUTMUX_CTIMERC_CTIMER2CAP_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_CTIMERC_CTIMER2CAP */ +#define INPUTMUX_CTIMERC_CTIMER2CAP_COUNT (4U) + +/*! @name TIMER2TRIG - Trigger register for TIMER2 inputs */ +/*! @{ */ + +#define INPUTMUX_TIMER2TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER2TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER2 + * 0b0000000..Reserved + * 0b0000001..CT_IPN0 input is selected + * 0b0000010..CT_IPN1 input is selected + * 0b0000011..CT_IPN2 input is selected + * 0b0000100..CT_IPN3 input is selected + * 0b0000101..CT_IPN4 input is selected + * 0b0000110..CT_IPN5 input is selected + * 0b0000111..CT_IPN6 input is selected + * 0b0001000..CT_IPN7 input is selected + * 0b0001001..CT_IPN8 input is selected + * 0b0001010..CT_IPN9 input is selected + * 0b0001011..CT_IPN10 input is selected + * 0b0001100..CT_IPN11 input is selected + * 0b0001101..CT_IPN12 input is selected + * 0b0001110..CT_IPN13 input is selected + * 0b0001111..CT_IPN14 input is selected + * 0b0010000..CT_IPN15 input is selected + * 0b0010001..CT_IPN16 input is selected + * 0b0010010..CT_IPN17 input is selected + * 0b0010011..CT_IPN18 input is selected + * 0b0010100..CT_IPN19 input is selected + * 0b0010101..USB0 usb0 start of frame input is selected + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..Reserved + * 0b0100001..CTimer0_MAT1 input is selected + * 0b0100010..CTimer0_MAT2 input is selected + * 0b0100011..CTimer0_MAT3 input is selected + * 0b0100100..CTimer1_MAT1 input is selected + * 0b0100101..CTimer1_MAT2 input is selected + * 0b0100110..CTimer1_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..Reserved + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..LPUART4 Received Data Word input is selected + * 0b1000101..LPUART4 Transmitted Data Word input is selected + * 0b1000110..LPUART4 Receive Line Idle input is selected + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..CTimer3_MAT1 input is selected + * 0b1010000..CTimer3_MAT2 input is selected + * 0b1010001..CTimer3_MAT3 input is selected + * 0b1010010..CTimer4_MAT1 input is selected + * 0b1010011..CTimer4_MAT2 input is selected + * 0b1010100..CTimer4_MAT3 input is selected + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..Reserved + * 0b1011110..LPI2C2 Master End of Packet input is selected + * 0b1011111..LPI2C2 Slave End of Packet input is selected + * 0b1100000..LPI2C3 Master End of Packet input is selected + * 0b1100001..LPI2C3 Slave End of Packet input is selected + * *.. + */ +#define INPUTMUX_TIMER2TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER2TRIG_INP_SHIFT)) & INPUTMUX_TIMER2TRIG_INP_MASK) +/*! @} */ + +/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ +/*! @{ */ + +#define INPUTMUX_FREQMEAS_REF_INP_MASK (0x7FU) +#define INPUTMUX_FREQMEAS_REF_INP_SHIFT (0U) +/*! INP - Clock source number (binary value) for frequency measure function target clock. + * 0b0000000..Reserved + * 0b0000001..clk_in input is selected + * 0b0000010..FRO_OSC_12M input is selected + * 0b0000011..fro_hf_div input is selected + * 0b0000100..Reserved + * 0b0000101..clk_16k[1] input is selected + * 0b0000110..SLOW_CLK input is selected + * 0b0000111..FREQME_CLK_IN0 input is selected + * 0b0001000..FREQME_CLK_IN1 input is selected input is selected + * 0b0001001..AOI0_OUT0 input is selected + * 0b0001010..AOI0_OUT1 + * 0b0001011..PWM0_SM0_MUX_TRIG0 + * 0b0001100..PWM0_SM0_MUX_TRIG1 + * 0b0001101..PWM0_SM1_MUX_TRIG0 + * 0b0001110..PWM0_SM1_MUX_TRIG1 + * 0b0001111..PWM0_SM2_MUX_TRIG0 + * 0b0010000..PWM0_SM2_MUX_TRIG1 + * 0b0010001..Reserved + * 0b0010010..Reserved + * 0b0010011..Reserved + * 0b0010100..Reserved + * 0b0010101..Reserved + * 0b0010110..Reserved + * 0b0010111..Reserved + * 0b0011000..Reserved + * 0b0011001..Reserved + * 0b0011010..Reserved + * 0b0011011..Reserved + * 0b0011100..Reserved + * 0b0011101..Reserved + * 0b0011110..Reserved + * 0b0011111..Reserved + * 0b0100000..AOI1_OUT0 input is selected + * 0b0100001..AOI1_OUT1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b0100011..PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM1_MUX_TRIG0 input is selected + * 0b0100101..PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100110..PWM1_SM2_MUX_TRIG0 input is selected + * 0b0100111..PWM1_SM2_MUX_TRIG1 input is selected + * 0b0101000..Reserved + * 0b0101001..Reserved + * *.. + */ +#define INPUTMUX_FREQMEAS_REF_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_INP_SHIFT)) & INPUTMUX_FREQMEAS_REF_INP_MASK) +/*! @} */ + +/*! @name FREQMEAS_TAR - Selection for frequency measurement reference clock */ +/*! @{ */ + +#define INPUTMUX_FREQMEAS_TAR_INP_MASK (0x7FU) +#define INPUTMUX_FREQMEAS_TAR_INP_SHIFT (0U) +/*! INP - Clock source number (binary value) for frequency measure function target clock. + * 0b0000000..Reserved + * 0b0000001..clk_in input is selected + * 0b0000010..FRO_OSC_12M input is selected + * 0b0000011..fro_hf_div input is selected + * 0b0000100..Reserved + * 0b0000101..clk_16k[1] input is selected + * 0b0000110..SLOW_CLK input is selected + * 0b0000111..FREQME_CLK_IN0 input is selected + * 0b0001000..FREQME_CLK_IN1 input is selected input is selected + * 0b0001001..AOI0_OUT0 input is selected + * 0b0001010..AOI0_OUT1 + * 0b0001011..PWM0_SM0_MUX_TRIG0 + * 0b0001100..PWM0_SM0_MUX_TRIG1 + * 0b0001101..PWM0_SM1_MUX_TRIG0 + * 0b0001110..PWM0_SM1_MUX_TRIG1 + * 0b0001111..PWM0_SM2_MUX_TRIG0 + * 0b0010000..PWM0_SM2_MUX_TRIG1 + * 0b0010001..Reserved + * 0b0010010..Reserved + * 0b0010011..Reserved + * 0b0010100..Reserved + * 0b0010101..Reserved + * 0b0010110..Reserved + * 0b0010111..Reserved + * 0b0011000..Reserved + * 0b0011001..Reserved + * 0b0011010..Reserved + * 0b0011011..Reserved + * 0b0011100..Reserved + * 0b0011101..Reserved + * 0b0011110..Reserved + * 0b0011111..Reserved + * 0b0100000..AOI1_OUT0 input is selected + * 0b0100001..AOI1_OUT1 input is selected + * 0b0100010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b0100011..PWM1_SM0_MUX_TRIG1 input is selected + * 0b0100100..PWM1_SM1_MUX_TRIG0 input is selected + * 0b0100101..PWM1_SM1_MUX_TRIG1 input is selected + * 0b0100110..PWM1_SM2_MUX_TRIG0 input is selected + * 0b0100111..PWM1_SM2_MUX_TRIG1 input is selected + * 0b0101000..Reserved + * 0b0101001..Reserved + * *.. + */ +#define INPUTMUX_FREQMEAS_TAR_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TAR_INP_SHIFT)) & INPUTMUX_FREQMEAS_TAR_INP_MASK) +/*! @} */ + +/*! @name CTIMERD_CTIMER3CAP - Capture select register for CTIMER inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMERD_CTIMER3CAP_INP_MASK (0x7FU) +#define INPUTMUX_CTIMERD_CTIMER3CAP_INP_SHIFT (0U) +/*! INP - Input number for CTIMER3 + * 0b0000000..Reserved + * 0b0000001..CT_IPN0 input is selected + * 0b0000010..CT_IPN1 input is selected + * 0b0000011..CT_IPN2 input is selected + * 0b0000100..CT_IPN3 input is selected + * 0b0000101..CT_IPN4 input is selected + * 0b0000110..CT_IPN5 input is selected + * 0b0000111..CT_IPN6 input is selected + * 0b0001000..CT_IPN7 input is selected + * 0b0001001..CT_IPN8 input is selected + * 0b0001010..CT_IPN9 input is selected + * 0b0001011..CT_IPN10 input is selected + * 0b0001100..CT_IPN11 input is selected + * 0b0001101..CT_IPN12 input is selected + * 0b0001110..CT_IPN13 input is selected + * 0b0001111..CT_IPN14 input is selected + * 0b0010000..CT_IPN15 input is selected + * 0b0010001..CT_IPN16 input is selected + * 0b0010010..CT_IPN17 input is selected + * 0b0010011..CT_IPN18 input is selected + * 0b0010100..CT_IPN19 input is selected + * 0b0010101..USB0 usb0 start of frame input is selected + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..Reserved + * 0b0100001..CTimer0_MAT1 input is selected + * 0b0100010..CTimer0_MAT2 input is selected + * 0b0100011..CTimer0_MAT3 input is selected + * 0b0100100..CTimer1_MAT1 input is selected + * 0b0100101..CTimer1_MAT2 input is selected + * 0b0100110..CTimer1_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..Reserved + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..LPUART4 Received Data Word input is selected + * 0b1000101..LPUART4 Transmitted Data Word input is selected + * 0b1000110..LPUART4 Receive Line Idle input is selected + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..CTimer2_MAT1 input is selected + * 0b1010000..CTimer2_MAT2 input is selected + * 0b1010001..CTimer2_MAT3 input is selected + * 0b1010010..CTimer4_MAT1 input is selected + * 0b1010011..CTimer4_MAT2 input is selected + * 0b1010100..CTimer4_MAT3 input is selected + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..Reserved + * 0b1011110..LPI2C2 Master End of Packet input is selected + * 0b1011111..LPI2C2 Slave End of Packet input is selected + * 0b1100000..LPI2C3 Master End of Packet input is selected + * 0b1100001..LPI2C3 Slave End of Packet input is selected + * *.. + */ +#define INPUTMUX_CTIMERD_CTIMER3CAP_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMERD_CTIMER3CAP_INP_SHIFT)) & INPUTMUX_CTIMERD_CTIMER3CAP_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_CTIMERD_CTIMER3CAP */ +#define INPUTMUX_CTIMERD_CTIMER3CAP_COUNT (4U) + +/*! @name TIMER3TRIG - Trigger register for TIMER3 */ +/*! @{ */ + +#define INPUTMUX_TIMER3TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER3TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER3 + * 0b0000000..Reserved + * 0b0000001..CT_IPN0 input is selected + * 0b0000010..CT_IPN1 input is selected + * 0b0000011..CT_IPN2 input is selected + * 0b0000100..CT_IPN3 input is selected + * 0b0000101..CT_IPN4 input is selected + * 0b0000110..CT_IPN5 input is selected + * 0b0000111..CT_IPN6 input is selected + * 0b0001000..CT_IPN7 input is selected + * 0b0001001..CT_IPN8 input is selected + * 0b0001010..CT_IPN9 input is selected + * 0b0001011..CT_IPN10 input is selected + * 0b0001100..CT_IPN11 input is selected + * 0b0001101..CT_IPN12 input is selected + * 0b0001110..CT_IPN13 input is selected + * 0b0001111..CT_IPN14 input is selected + * 0b0010000..CT_IPN15 input is selected + * 0b0010001..CT_IPN16 input is selected + * 0b0010010..CT_IPN17 input is selected + * 0b0010011..CT_IPN18 input is selected + * 0b0010100..CT_IPN19 input is selected + * 0b0010101..USB0 usb0 start of frame input is selected + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..Reserved + * 0b0100001..CTimer0_MAT1 input is selected + * 0b0100010..CTimer0_MAT2 input is selected + * 0b0100011..CTimer0_MAT3 input is selected + * 0b0100100..CTimer1_MAT1 input is selected + * 0b0100101..CTimer1_MAT2 input is selected + * 0b0100110..CTimer1_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..Reserved + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..LPUART4 Received Data Word input is selected + * 0b1000101..LPUART4 Transmitted Data Word input is selected + * 0b1000110..LPUART4 Receive Line Idle input is selected + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..CTimer2_MAT1 input is selected + * 0b1010000..CTimer2_MAT2 input is selected + * 0b1010001..CTimer2_MAT3 input is selected + * 0b1010010..CTimer4_MAT1 input is selected + * 0b1010011..CTimer4_MAT2 input is selected + * 0b1010100..CTimer4_MAT3 input is selected + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..Reserved + * 0b1011110..LPI2C2 Master End of Packet input is selected + * 0b1011111..LPI2C2 Slave End of Packet input is selected + * 0b1100000..LPI2C3 Master End of Packet input is selected + * 0b1100001..LPI2C3 Slave End of Packet input is selected + * *.. + */ +#define INPUTMUX_TIMER3TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER3TRIG_INP_SHIFT)) & INPUTMUX_TIMER3TRIG_INP_MASK) +/*! @} */ + +/*! @name CTIMERE_CTIMER4CAP - Capture select register for CTIMER inputs */ +/*! @{ */ + +#define INPUTMUX_CTIMERE_CTIMER4CAP_INP_MASK (0x7FU) +#define INPUTMUX_CTIMERE_CTIMER4CAP_INP_SHIFT (0U) +/*! INP - Input number for CTIMER4 + * 0b0000000..Reserved + * 0b0000001..CT_IPN0 input is selected + * 0b0000010..CT_IPN1 input is selected + * 0b0000011..CT_IPN2 input is selected + * 0b0000100..CT_IPN3 input is selected + * 0b0000101..CT_IPN4 input is selected + * 0b0000110..CT_IPN5 input is selected + * 0b0000111..CT_IPN6 input is selected + * 0b0001000..CT_IPN7 input is selected + * 0b0001001..CT_IPN8 input is selected + * 0b0001010..CT_IPN9 input is selected + * 0b0001011..CT_IPN10 input is selected + * 0b0001100..CT_IPN11 input is selected + * 0b0001101..CT_IPN12 input is selected + * 0b0001110..CT_IPN13 input is selected + * 0b0001111..CT_IPN14 input is selected + * 0b0010000..CT_IPN15 input is selected + * 0b0010001..CT_IPN16 input is selected + * 0b0010010..CT_IPN17 input is selected + * 0b0010011..CT_IPN18 input is selected + * 0b0010100..CT_IPN19 input is selected + * 0b0010101..USB0 usb0 start of frame input is selected + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..Reserved + * 0b0100001..CTimer0_MAT1 input is selected + * 0b0100010..CTimer0_MAT2 input is selected + * 0b0100011..CTimer0_MAT3 input is selected + * 0b0100100..CTimer1_MAT1 input is selected + * 0b0100101..CTimer1_MAT2 input is selected + * 0b0100110..CTimer1_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..Reserved + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..LPUART4 Received Data Word input is selected + * 0b1000101..LPUART4 Transmitted Data Word input is selected + * 0b1000110..LPUART4 Receive Line Idle input is selected + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..CTimer2_MAT1 input is selected + * 0b1010000..CTimer2_MAT2 input is selected + * 0b1010001..CTimer2_MAT3 input is selected + * 0b1010010..CTimer3_MAT1 input is selected + * 0b1010011..CTimer3_MAT2 input is selected + * 0b1010100..CTimer3_MAT3 input is selected + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..Reserved + * 0b1011110..LPI2C2 Master End of Packet input is selected + * 0b1011111..LPI2C2 Slave End of Packet input is selected + * 0b1100000..LPI2C3 Master End of Packet input is selected + * 0b1100001..LPI2C3 Slave End of Packet input is selected + * *.. + */ +#define INPUTMUX_CTIMERE_CTIMER4CAP_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CTIMERE_CTIMER4CAP_INP_SHIFT)) & INPUTMUX_CTIMERE_CTIMER4CAP_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_CTIMERE_CTIMER4CAP */ +#define INPUTMUX_CTIMERE_CTIMER4CAP_COUNT (4U) + +/*! @name TIMER4TRIG - Trigger register for TIMER4 */ +/*! @{ */ + +#define INPUTMUX_TIMER4TRIG_INP_MASK (0x7FU) +#define INPUTMUX_TIMER4TRIG_INP_SHIFT (0U) +/*! INP - Input number for CTIMER4 + * 0b0000000..Reserved + * 0b0000001..CT_IPN0 input is selected + * 0b0000010..CT_IPN1 input is selected + * 0b0000011..CT_IPN2 input is selected + * 0b0000100..CT_IPN3 input is selected + * 0b0000101..CT_IPN4 input is selected + * 0b0000110..CT_IPN5 input is selected + * 0b0000111..CT_IPN6 input is selected + * 0b0001000..CT_IPN7 input is selected + * 0b0001001..CT_IPN8 input is selected + * 0b0001010..CT_IPN9 input is selected + * 0b0001011..CT_IPN10 input is selected + * 0b0001100..CT_IPN11 input is selected + * 0b0001101..CT_IPN12 input is selected + * 0b0001110..CT_IPN13 input is selected + * 0b0001111..CT_IPN14 input is selected + * 0b0010000..CT_IPN15 input is selected + * 0b0010001..CT_IPN16 input is selected + * 0b0010010..CT_IPN17 input is selected + * 0b0010011..CT_IPN18 input is selected + * 0b0010100..CT_IPN19 input is selected + * 0b0010101..USB0 usb0 start of frame input is selected + * 0b0010110..AOI0_OUT0 input is selected + * 0b0010111..AOI0_OUT1 input is selected + * 0b0011000..AOI0_OUT2 input is selected + * 0b0011001..AOI0_OUT3 input is selected + * 0b0011010..ADC0_tcomp[0] + * 0b0011011..ADC0_tcomp[1] + * 0b0011100..ADC0_tcomp[2] + * 0b0011101..ADC0_tcomp[3] input is selected + * 0b0011110..CMP0_OUT is selected + * 0b0011111..CMP1_OUT is selected + * 0b0100000..Reserved + * 0b0100001..CTimer0_MAT1 input is selected + * 0b0100010..CTimer0_MAT2 input is selected + * 0b0100011..CTimer0_MAT3 input is selected + * 0b0100100..CTimer1_MAT1 input is selected + * 0b0100101..CTimer1_MAT2 input is selected + * 0b0100110..CTimer1_MAT3 input is selected + * 0b0100111..QDC0_CMP_FLAG0 is selected + * 0b0101000..QDC0_CMP_FLAG1 input is selected + * 0b0101001..QDC0_CMP_FLAG2 input is selected + * 0b0101010..QDC0_CMP_FLAG3 input is selected + * 0b0101011..QDC0_POS_MATCH0 input is selected + * 0b0101100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0101101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0101110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0101111..Reserved + * 0b0110000..LPI2C0 Master End of Packet input is selected + * 0b0110001..LPI2C0 Slave End of Packet input is selected + * 0b0110010..LPI2C1 Master End of Packet input is selected + * 0b0110011..LPI2C1 Slave End of Packet input is selected + * 0b0110100..LPSPI0 End of Frame input is selected + * 0b0110101..LPSPI0 Received Data Word input is selected + * 0b0110110..LPSPI1 End of Frame input is selected + * 0b0110111..LPSPI1 Received Data Word input is selected + * 0b0111000..LPUART0 Received Data Word input is selected + * 0b0111001..LPUART0 Transmitted Data Word input is selected + * 0b0111010..LPUART0 Receive Line Idle input is selected + * 0b0111011..LPUART1 Received Data Word input is selected + * 0b0111100..LPUART1 Transmitted Data Word input is selected + * 0b0111101..LPUART1 Receive Line Idle input is selected + * 0b0111110..LPUART2 Received Data Word input is selected + * 0b0111111..LPUART2 Transmitted Data Word input is selected + * 0b1000000..LPUART2 Receive Line Idle input is selected + * 0b1000001..LPUART3 Received Data Word input is selected + * 0b1000010..LPUART3 Transmitted Data Word input is selected + * 0b1000011..LPUART3 Receive Line Idle input is selected + * 0b1000100..LPUART4 Received Data Word input is selected + * 0b1000101..LPUART4 Transmitted Data Word input is selected + * 0b1000110..LPUART4 Receive Line Idle input is selected + * 0b1000111..AOI1_OUT0 input is selected + * 0b1001000..AOI1_OUT1 input is selected + * 0b1001001..AOI1_OUT2 input is selected + * 0b1001010..AOI1_OUT3 input is selected + * 0b1001011..ADC1_tcomp[0] input is selected + * 0b1001100..ADC1_tcomp[1] input is selected + * 0b1001101..ADC1_tcomp[2] input is selected + * 0b1001110..ADC1_tcomp[3] input is selected + * 0b1001111..CTimer2_MAT1 input is selected + * 0b1010000..CTimer2_MAT2 input is selected + * 0b1010001..CTimer2_MAT3 input is selected + * 0b1010010..CTimer3_MAT1 input is selected + * 0b1010011..CTimer3_MAT2 input is selected + * 0b1010100..CTimer3_MAT3 input is selected + * 0b1010101..QDC1_CMP_FLAG0 input is selected + * 0b1010110..QDC1_CMP_FLAG1 input is selected + * 0b1010111..QDC1_CMP_FLAG2 input is selected + * 0b1011000..QDC1_CMP_FLAG3 input is selected + * 0b1011001..QDC1_POS_MATCH0 input is selected + * 0b1011010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1011011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1011100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1011101..Reserved + * 0b1011110..LPI2C2 Master End of Packet input is selected + * 0b1011111..LPI2C2 Slave End of Packet input is selected + * 0b1100000..LPI2C3 Master End of Packet input is selected + * 0b1100001..LPI2C3 Slave End of Packet input is selected + * *.. + */ +#define INPUTMUX_TIMER4TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_TIMER4TRIG_INP_SHIFT)) & INPUTMUX_TIMER4TRIG_INP_MASK) +/*! @} */ + +/*! @name AOI1_INPUTM_AOI1_INPUT - AOI1 trigger input connections 0 */ +/*! @{ */ + +#define INPUTMUX_AOI1_INPUTM_AOI1_INPUT_INP_MASK (0x7FU) +#define INPUTMUX_AOI1_INPUTM_AOI1_INPUT_INP_SHIFT (0U) +/*! INP - AOI0 trigger input connections + * 0b0000000..Reserved + * 0b0000001..ADC0_tcomp[0] input is selected + * 0b0000010..ADC0_tcomp[1] input is selected + * 0b0000011..ADC0_tcomp[2] input is selected + * 0b0000100..ADC0_tcomp[3] input is selected + * 0b0000101..CMP0_OUT input is selected + * 0b0000110..CMP1_OUT input is selected + * 0b0000111..Reserved + * 0b0001000..CTimer0_MAT0 input is selected + * 0b0001001..CTimer0_MAT1 input is selected + * 0b0001010..CTimer0_MAT2 input is selected + * 0b0001011..CTimer0_MAT3 input is selected + * 0b0001100..CTimer1_MAT0 + * 0b0001101..CTimer1_MAT1 input is selected + * 0b0001110..CTimer1_MAT2 input is selected + * 0b0001111..CTimer1_MAT3 input is selected + * 0b0010000..CTimer2_MAT0 input is selected + * 0b0010001..CTimer2_MAT1 input is selected + * 0b0010010..CTimer2_MAT2 input is selected + * 0b0010011..CTimer2_MAT3 input is selected + * 0b0010100..LPTMR0 input is selected + * 0b0010101..Reserved + * 0b0010110..QDC0_CMP_FLAG0 input is selected + * 0b0010111..QDC0_CMP_FLAG1 input is selected + * 0b0011000..QDC0_CMP_FLAG2 input is selected + * 0b0011001..QDC0_CMP_FLAG3 input is selected + * 0b0011010..QDC0_POS_MATCH input is selected + * 0b0011011..PWM0_SM0_MUX_TRIG0 0 input is selected + * 0b0011100..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0011110..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..Reserved + * 0b0100010..Reserved + * 0b0100011..TRIG_IN0 input is selected + * 0b0100100..TRIG_IN1 input is selected + * 0b0100101..TRIG_IN2 input is selected + * 0b0100110..TRIG_IN3 input is selected + * 0b0100111..TRIG_IN4 input is selected + * 0b0101000..TRIG_IN5 input is selected + * 0b0101001..TRIG_IN6 input is selected + * 0b0101010..TRIG_IN7 input is selected + * 0b0101011..TRIG_IN8 input is selected + * 0b0101100..TRIG_IN9 input is selected + * 0b0101101..TRIG_IN10 input is selected + * 0b0101110..TRIG_IN11 input is selected + * 0b0101111..GPIO0 Pin Event Trig 0 input is selected + * 0b0110000..GPIO1 Pin Event Trig 0 input is selected + * 0b0110001..GPIO2 Pin Event Trig 0 input is selected + * 0b0110010..GPIO3 Pin Event Trig 0 input is selected + * 0b0110011..GPIO4 Pin Event Trig 0 input is selected + * 0b0110100..ADC1_tcomp[0] input is selected + * 0b0110101..ADC1_tcomp[1] input is selected + * 0b0110110..ADC1_tcomp[2] input is selected + * 0b0110111..ADC1_tcomp[3] input is selected + * 0b0111000..CTimer3_MAT0 input is selected + * 0b0111001..CTimer3_MAT1 input is selected + * 0b0111010..CTimer3_MAT2 input is selected + * 0b0111011..CTimer3_MAT3 input is selected + * 0b0111100..CTimer4_MAT0 input is selected + * 0b0111101..CTimer4_MAT1 input is selected + * 0b0111110..CTimer4_MAT2 input is selected + * 0b0111111..CTimer4_MAT3 input is selected + * 0b1000000..FlexIO CH0 input is selected + * 0b1000001..FlexIO CH1 input is selected + * 0b1000010..FlexIO CH2 input is selected + * 0b1000011..FlexIO CH3 input is selected + * 0b1000100..QDC1_CMP_FLAG0 input is selected + * 0b1000101..QDC1_CMP_FLAG1 input is selected + * 0b1000110..QDC1_CMP_FLAG2 input is selected + * 0b1000111..QDC1_CMP_FLAG3 input is selected + * 0b1001000..QDC1_POS_MATCH0 input is selected + * 0b1001001..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1001010..PWM1_SM0_MUX_TRIG1 input is selected + * 0b1001011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1001100..PWM1_SM1_MUX_TRIG1 input is selected + * 0b1001101..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1001110..PWM1_SM2_MUX_TRIG1 input is selected + * 0b1001111..Reserved + * 0b1010000..Reserved + * *.. + */ +#define INPUTMUX_AOI1_INPUTM_AOI1_INPUT_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AOI1_INPUTM_AOI1_INPUT_INP_SHIFT)) & INPUTMUX_AOI1_INPUTM_AOI1_INPUT_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_AOI1_INPUTM_AOI1_INPUT */ +#define INPUTMUX_AOI1_INPUTM_AOI1_INPUT_COUNT (16U) + +/*! @name CMP0_TRIG - CMP0 input connections */ +/*! @{ */ + +#define INPUTMUX_CMP0_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_CMP0_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - CMP0 input trigger + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP1_OUT input is selected + * 0b000111..Reserved + * 0b001000..CTimer0_MAT0 input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer1_MAT0 + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer2_MAT0 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..LPTMR0 input is selected + * 0b001111..Reserved + * 0b010000..QDC0_POS_MATCH0 + * 0b010001..PWM0_SM0_MUX_TRIG0 input is selected + * 0b010010..PWM0_SM0_MUX_TRIG1 input is selected + * 0b010011..PWM0_SM1_MUX_TRIG0 input is selected + * 0b010100..PWM0_SM1_MUX_TRIG1 input is selected + * 0b010101..PWM0_SM2_MUX_TRIG0 input is selected + * 0b010110..PWM0_SM2_MUX_TRIG1 input is selected + * 0b010111..Reserved + * 0b011000..Reserved + * 0b011001..GPIO0 Pin Event Trig 0 input is selected + * 0b011010..GPIO1 Pin Event Trig 0 input is selected + * 0b011011..GPIO2 Pin Event Trig 0 input is selected + * 0b011100..GPIO3 Pin Event Trig 0 input is selected + * 0b011101..GPIO4 Pin Event Trig 0 input is selected + * 0b011110..WUU input is selected + * 0b011111..AOI1_OUT0 input is selected + * 0b100000..AOI1_OUT1 input is selected + * 0b100001..AOI1_OUT2 input is selected + * 0b100010..AOI1_OUT3 input is selected + * 0b100011..Reserved + * 0b100100..Reserved + * 0b100101..Reserved + * 0b100110..Reserved + * 0b100111..CTimer3_MAT0 + * 0b101000..CTimer3_MAT1 + * 0b101001..CTimer4_MAT0 input is selected + * 0b101010..CTimer4_MAT1 input is selected + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..QDC1_POS_MATCH0 input is selected + * 0b110000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b110010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b110011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b110100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b110101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b110110..Reserved + * 0b110111..Reserved + * *.. + */ +#define INPUTMUX_CMP0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP0_TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name ADC0_TRIGM_ADC0_TRIG - ADC Trigger input connections */ +/*! @{ */ + +#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - ADC0 trigger inputs + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT0 input is selected + * 0b001010..CTimer0_MAT1 input is selected + * 0b001011..CTimer1_MAT0 input is selected + * 0b001100..CTimer1_MAT1 input is selected + * 0b001101..CTimer2_MAT0 input is selected + * 0b001110..CTimer2_MAT1 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..QDC0_POS_MATCH0 input is selected + * 0b010010..PWM0_SM0_OUT_TRIG0 input is selected + * 0b010011..PWM0_SM0_OUT_TRIG1 input is selected + * 0b010100..PWM0_SM1_OUT_TRIG0 input is selected + * 0b010101..PWM0_SM1_OUT_TRIG1 input is selected + * 0b010110..PWM0_SM2_OUT_TRIG0 input is selected + * 0b010111..PWM0_SM2_OUT_TRIG1 input is selected + * 0b011000..Reserved + * 0b011001..Reserved + * 0b011010..GPIO0 Pin Event Trig 0 input is selected + * 0b011011..GPIO1 Pin Event Trig 0 input is selected + * 0b011100..GPIO2 Pin Event Trig 0 input is selected + * 0b011101..GPIO3 Pin Event Trig 0 input is selected + * 0b011110..GPIO4 Pin Event Trig 0 input is selected + * 0b011111..WUU + * 0b100000..Reserved + * 0b100001..AOI1_OUT0 input is selected + * 0b100010..AOI1_OUT1 input is selected + * 0b100011..AOI1_OUT2 input is selected + * 0b100100..AOI1_OUT3 input is selected + * 0b100101..ADC1_tcomp[0] input is selected + * 0b100110..ADC1_tcomp[1] input is selected + * 0b100111..ADC1_tcomp[2] input is selected + * 0b101000..ADC1_tcomp[3] input is selected + * 0b101001..CTimer3_MAT0 input is selected + * 0b101010..CTimer3_MAT1 input is selected + * 0b101011..CTimer4_MAT0 input is selected + * 0b101100..CTimer4_MAT1 input is selected + * 0b101101..FlexIO CH0 input is selected + * 0b101110..FlexIO CH1 input is selected + * 0b101111..FlexIO CH2 input is selected + * 0b110000..FlexIO CH3 input is selected + * 0b110001..QDC1_POS_MATCH0 input is selected + * 0b110010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110011..PWM1_SM0_MUX_TRIG1 input is selected + * 0b110100..PWM1_SM1_MUX_TRIG0 input is selected + * 0b110101..PWM1_SM1_MUX_TRIG1 input is selected + * 0b110110..PWM1_SM2_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111000..Reserved + * 0b111001..Reserved + * *.. + */ +#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC0_TRIGM_ADC0_TRIG_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_ADC0_TRIGM_ADC0_TRIG */ +#define INPUTMUX_ADC0_TRIGM_ADC0_TRIG_COUNT (4U) + +/*! @name ADC1_TRIGM_ADC1_TRIG - ADC Trigger input connections */ +/*! @{ */ + +#define INPUTMUX_ADC1_TRIGM_ADC1_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_ADC1_TRIGM_ADC1_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - ADC0 trigger inputs + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT0 input is selected + * 0b001010..CTimer0_MAT1 input is selected + * 0b001011..CTimer1_MAT0 input is selected + * 0b001100..CTimer1_MAT1 input is selected + * 0b001101..CTimer2_MAT0 input is selected + * 0b001110..CTimer2_MAT1 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..QDC0_POS_MATCH0 input is selected + * 0b010010..PWM0_SM0_OUT_TRIG0 input is selected + * 0b010011..PWM0_SM0_OUT_TRIG1 input is selected + * 0b010100..PWM0_SM1_OUT_TRIG0 input is selected + * 0b010101..PWM0_SM1_OUT_TRIG1 input is selected + * 0b010110..PWM0_SM2_OUT_TRIG0 input is selected + * 0b010111..PWM0_SM2_OUT_TRIG1 input is selected + * 0b011000..Reserved + * 0b011001..Reserved + * 0b011010..GPIO0 Pin Event Trig 0 input is selected + * 0b011011..GPIO1 Pin Event Trig 0 input is selected + * 0b011100..GPIO2 Pin Event Trig 0 input is selected + * 0b011101..GPIO3 Pin Event Trig 0 input is selected + * 0b011110..GPIO4 Pin Event Trig 0 input is selected + * 0b011111..WUU + * 0b100000..Reserved + * 0b100001..AOI1_OUT0 input is selected + * 0b100010..AOI1_OUT1 input is selected + * 0b100011..AOI1_OUT2 input is selected + * 0b100100..AOI1_OUT3 input is selected + * 0b100101..ADC0_tcomp[0] input is selected + * 0b100110..ADC0_tcomp[1] input is selected + * 0b100111..ADC0_tcomp[2] input is selected + * 0b101000..ADC0_tcomp[3] input is selected + * 0b101001..CTimer3_MAT0 input is selected + * 0b101010..CTimer3_MAT1 input is selected + * 0b101011..CTimer4_MAT0 input is selected + * 0b101100..CTimer4_MAT1 input is selected + * 0b101101..FlexIO CH0 input is selected + * 0b101110..FlexIO CH1 input is selected + * 0b101111..FlexIO CH2 input is selected + * 0b110000..FlexIO CH3 input is selected + * 0b110001..QDC1_POS_MATCH0 input is selected + * 0b110010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110011..PWM1_SM0_MUX_TRIG1 input is selected + * 0b110100..PWM1_SM1_MUX_TRIG0 input is selected + * 0b110101..PWM1_SM1_MUX_TRIG1 input is selected + * 0b110110..PWM1_SM2_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111000..Reserved + * 0b111001..Reserved + * *.. + */ +#define INPUTMUX_ADC1_TRIGM_ADC1_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_ADC1_TRIGM_ADC1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_ADC1_TRIGM_ADC1_TRIG_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_ADC1_TRIGM_ADC1_TRIG */ +#define INPUTMUX_ADC1_TRIGM_ADC1_TRIG_COUNT (4U) + +/*! @name DAC0_TRIG - This register selects the DAC0 trigger inputs. */ +/*! @{ */ + +#define INPUTMUX_DAC0_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_DAC0_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - DAC0 trigger input + * 0b000000..Reserved + * 0b000001..ARM_TXEV + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT0 input is selected + * 0b001010..CTimer0_MAT1 input is selected + * 0b001011..CTimer1_MAT0 input is selected + * 0b001100..CTimer1_MAT1 input is selected + * 0b001101..CTimer2_MAT0 input is selected + * 0b001110..CTimer2_MAT1 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..Reserved + * 0b010010..Reserved + * 0b010011..Reserved + * 0b010100..Reserved + * 0b010101..Reserved + * 0b010110..Reserved + * 0b010111..Reserved + * 0b011000..Reserved + * 0b011001..Reserved + * 0b011010..GPIO0 Pin Event Trig 0 input is selected + * 0b011011..GPIO1 Pin Event Trig 0 input is selected + * 0b011100..GPIO2 Pin Event Trig 0 input is selected + * 0b011101..GPIO3 Pin Event Trig 0 input is selected + * 0b011110..GPIO4 Pin Event Trig 0 input is selected + * 0b011111..WUU input is selected + * 0b100000..Reserved + * 0b100001..AOI1_OUT0 input is selected + * 0b100010..AOI1_OUT1 input is selected + * 0b100011..AOI1_OUT2 input is selected + * 0b100100..AOI1_OUT3 input is selected + * 0b100101..ADC0_tcomp[0] input is selected + * 0b100110..ADC0_tcomp[1] input is selected + * 0b100111..ADC1_tcomp[0] input is selected + * 0b101000..ADC1_tcomp[1] input is selected + * 0b101001..CTimer3_MAT0 input is selected + * 0b101010..CTimer3_MAT1 input is selected + * 0b101011..CTimer4_MAT0 input is selected + * 0b101100..CTimer4_MAT1 input is selected + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..Reserved + * 0b110000..Reserved + * 0b110001..Reserved + * 0b110010..Reserved + * 0b110011..Reserved + * 0b110100..Reserved + * 0b110101..Reserved + * 0b110110..Reserved + * 0b110111..Reserved + * 0b111000..Reserved + * 0b111001..Reserved + * *.. + */ +#define INPUTMUX_DAC0_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DAC0_TRIG_TRIGIN_SHIFT)) & INPUTMUX_DAC0_TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name QDC0_TRIG - QDC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC0_TRIG_INP_MASK (0x7FU) +#define INPUTMUX_QDC0_TRIG_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..Reserved + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..Reserved + * 0b0010111..Reserved + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 End of Frame input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..Reserved + * 0b1000101..Reserved + * *.. + */ +#define INPUTMUX_QDC0_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_TRIG_INP_SHIFT)) & INPUTMUX_QDC0_TRIG_INP_MASK) +/*! @} */ + +/*! @name QDC0_HOME - QDC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC0_HOME_INP_MASK (0x7FU) +#define INPUTMUX_QDC0_HOME_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..Reserved + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..Reserved + * 0b0010111..Reserved + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 End of Frame input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..Reserved + * 0b1000101..Reserved + * *.. + */ +#define INPUTMUX_QDC0_HOME_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_HOME_INP_SHIFT)) & INPUTMUX_QDC0_HOME_INP_MASK) +/*! @} */ + +/*! @name QDC0_INDEX - QDC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC0_INDEX_INP_MASK (0x7FU) +#define INPUTMUX_QDC0_INDEX_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..Reserved + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..Reserved + * 0b0010111..Reserved + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 End of Frame input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..Reserved + * 0b1000101..Reserved + * *.. + */ +#define INPUTMUX_QDC0_INDEX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_INDEX_INP_SHIFT)) & INPUTMUX_QDC0_INDEX_INP_MASK) +/*! @} */ + +/*! @name QDC0_PHASEB - QDC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC0_PHASEB_INP_MASK (0x7FU) +#define INPUTMUX_QDC0_PHASEB_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..Reserved + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..Reserved + * 0b0010111..Reserved + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 End of Frame input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..Reserved + * 0b1000101..Reserved + * *.. + */ +#define INPUTMUX_QDC0_PHASEB_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_PHASEB_INP_SHIFT)) & INPUTMUX_QDC0_PHASEB_INP_MASK) +/*! @} */ + +/*! @name QDC0_PHASEA - QDC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC0_PHASEA_INP_MASK (0x7FU) +#define INPUTMUX_QDC0_PHASEA_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..Reserved + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..Reserved + * 0b0010111..Reserved + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 End of Frame input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..Reserved + * 0b1000101..Reserved + * *.. + */ +#define INPUTMUX_QDC0_PHASEA_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_PHASEA_INP_SHIFT)) & INPUTMUX_QDC0_PHASEA_INP_MASK) +/*! @} */ + +/*! @name QDC0_ICAP1 - QDC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC0_ICAP1_INP_MASK (0x7FU) +#define INPUTMUX_QDC0_ICAP1_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..Reserved + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..Reserved + * 0b0010111..Reserved + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 End of Frame input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..Reserved + * 0b1000101..Reserved + * *.. + */ +#define INPUTMUX_QDC0_ICAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_ICAP1_INP_SHIFT)) & INPUTMUX_QDC0_ICAP1_INP_MASK) +/*! @} */ + +/*! @name QDC0_ICAP2 - QDC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC0_ICAP2_INP_MASK (0x7FU) +#define INPUTMUX_QDC0_ICAP2_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..Reserved + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..Reserved + * 0b0010111..Reserved + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 End of Frame input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..Reserved + * 0b1000101..Reserved + * *.. + */ +#define INPUTMUX_QDC0_ICAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_ICAP2_INP_SHIFT)) & INPUTMUX_QDC0_ICAP2_INP_MASK) +/*! @} */ + +/*! @name QDC0_ICAP3 - QDC0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC0_ICAP3_INP_MASK (0x7FU) +#define INPUTMUX_QDC0_ICAP3_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..Reserved + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..Reserved + * 0b0010111..Reserved + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 End of Frame input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..Reserved + * 0b1000101..Reserved + * *.. + */ +#define INPUTMUX_QDC0_ICAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC0_ICAP3_INP_SHIFT)) & INPUTMUX_QDC0_ICAP3_INP_MASK) +/*! @} */ + +/*! @name QDC1_TRIG - QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC1_TRIG_INP_MASK (0x7FU) +#define INPUTMUX_QDC1_TRIG_INP_SHIFT (0U) +/*! INP - QDC1 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..Reserved + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..Reserved + * 0b0010111..Reserved + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 End of Frame input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..Reserved + * 0b1000101..Reserved + * *.. + */ +#define INPUTMUX_QDC1_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_TRIG_INP_SHIFT)) & INPUTMUX_QDC1_TRIG_INP_MASK) +/*! @} */ + +/*! @name QDC1_HOME - QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC1_HOME_INP_MASK (0x7FU) +#define INPUTMUX_QDC1_HOME_INP_SHIFT (0U) +/*! INP - QDC1 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..Reserved + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..Reserved + * 0b0010111..Reserved + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 End of Frame input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..Reserved + * 0b1000101..Reserved + * *.. + */ +#define INPUTMUX_QDC1_HOME_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_HOME_INP_SHIFT)) & INPUTMUX_QDC1_HOME_INP_MASK) +/*! @} */ + +/*! @name QDC1_INDEX - QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC1_INDEX_INP_MASK (0x7FU) +#define INPUTMUX_QDC1_INDEX_INP_SHIFT (0U) +/*! INP - QDC1 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..Reserved + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..Reserved + * 0b0010111..Reserved + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 End of Frame input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..Reserved + * 0b1000101..Reserved + * *.. + */ +#define INPUTMUX_QDC1_INDEX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_INDEX_INP_SHIFT)) & INPUTMUX_QDC1_INDEX_INP_MASK) +/*! @} */ + +/*! @name QDC1_PHASEB - QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC1_PHASEB_INP_MASK (0x7FU) +#define INPUTMUX_QDC1_PHASEB_INP_SHIFT (0U) +/*! INP - QDC1 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..Reserved + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..Reserved + * 0b0010111..Reserved + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 End of Frame input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..Reserved + * 0b1000101..Reserved + * *.. + */ +#define INPUTMUX_QDC1_PHASEB_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_PHASEB_INP_SHIFT)) & INPUTMUX_QDC1_PHASEB_INP_MASK) +/*! @} */ + +/*! @name QDC1_PHASEA - QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC1_PHASEA_INP_MASK (0x7FU) +#define INPUTMUX_QDC1_PHASEA_INP_SHIFT (0U) +/*! INP - QDC0 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..Reserved + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..Reserved + * 0b0010111..Reserved + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 End of Frame input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..Reserved + * 0b1000101..Reserved + * *.. + */ +#define INPUTMUX_QDC1_PHASEA_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_PHASEA_INP_SHIFT)) & INPUTMUX_QDC1_PHASEA_INP_MASK) +/*! @} */ + +/*! @name QDC1_ICAP1 - QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC1_ICAP1_INP_MASK (0x7FU) +#define INPUTMUX_QDC1_ICAP1_INP_SHIFT (0U) +/*! INP - QDC1 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..Reserved + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..Reserved + * 0b0010111..Reserved + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 End of Frame input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..Reserved + * 0b1000101..Reserved + * *.. + */ +#define INPUTMUX_QDC1_ICAP1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_ICAP1_INP_SHIFT)) & INPUTMUX_QDC1_ICAP1_INP_MASK) +/*! @} */ + +/*! @name QDC1_ICAP2 - QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC1_ICAP2_INP_MASK (0x7FU) +#define INPUTMUX_QDC1_ICAP2_INP_SHIFT (0U) +/*! INP - QDC1 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..Reserved + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..Reserved + * 0b0010111..Reserved + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 End of Frame input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..Reserved + * 0b1000101..Reserved + * *.. + */ +#define INPUTMUX_QDC1_ICAP2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_ICAP2_INP_SHIFT)) & INPUTMUX_QDC1_ICAP2_INP_MASK) +/*! @} */ + +/*! @name QDC1_ICAP3 - QDC1 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_QDC1_ICAP3_INP_MASK (0x7FU) +#define INPUTMUX_QDC1_ICAP3_INP_SHIFT (0U) +/*! INP - QDC1 input connections + * 0b0000000..Reserved + * 0b0000001..ARM_TXEV input is selected + * 0b0000010..AOI0_OUT0 input is selected + * 0b0000011..AOI0_OUT1 input is selected + * 0b0000100..AOI0_OUT2 input is selected + * 0b0000101..AOI0_OUT3 input is selected + * 0b0000110..CMP0_OUT input is selected + * 0b0000111..CMP1_OUT input is selected + * 0b0001000..Reserved + * 0b0001001..CTimer0_MAT2 input is selected + * 0b0001010..CTimer0_MAT3 + * 0b0001011..CTimer1_MAT2 input is selected + * 0b0001100..CTimer1_MAT3 input is selected + * 0b0001101..CTimer2_MAT2 input is selected + * 0b0001110..CTimer2_MAT3 input is selected + * 0b0001111..Reserved + * 0b0010000..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010001..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0010010..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010011..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0010100..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0010110..Reserved + * 0b0010111..Reserved + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..TRIG_IN8 input is selected + * 0b0100001..TRIG_IN9 input is selected + * 0b0100010..TRIG_IN10 input is selected + * 0b0100011..TRIG_IN11 input is selected + * 0b0100100..GPIO0 Pin Event Trig 0 is selected + * 0b0100101..GPIO1 Pin Event Trig 0 input is selected + * 0b0100110..GPIO2 Pin Event Trig 0 input is selected + * 0b0100111..GPIO3 Pin Event Trig 0 input is selected + * 0b0101000..GPIO4 Pin Event Trig 0 input is selected + * 0b0101001..AOI1_OUT0 input is selected + * 0b0101010..AOI1_OUT1 input is selected + * 0b0101011..AOI1_OUT2 input is selected + * 0b0101100..AOI1_OUT3 input is selected + * 0b0101101..Reserved + * 0b0101110..Reserved + * 0b0101111..Reserved + * 0b0110000..Reserved + * 0b0110001..CTimer3_MAT2 input is selected + * 0b0110010..CTimer3_MAT3 input is selected + * 0b0110011..CTimer4_MAT2 input is selected + * 0b0110100..CTimer4_MAT3 End of Frame input is selected + * 0b0110101..Reserved + * 0b0110110..Reserved + * 0b0110111..Reserved + * 0b0111000..Reserved + * 0b0111001..Reserved + * 0b0111010..Reserved + * 0b0111011..Reserved + * 0b0111100..Reserved + * 0b0111101..Reserved + * 0b0111110..PWM1_SM0_OUT_TRIG0 input is selected + * 0b0111111..PWM1_SM0_OUT_TRIG1 input is selected + * 0b1000000..PWM1_SM1_OUT_TRIG0 input is selected + * 0b1000001..PWM1_SM1_OUT_TRIG1 input is selected + * 0b1000010..PWM1_SM2_OUT_TRIG0 input is selected + * 0b1000011..PWM1_SM2_OUT_TRIG1 input is selected + * 0b1000100..Reserved + * 0b1000101..Reserved + * *.. + */ +#define INPUTMUX_QDC1_ICAP3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_QDC1_ICAP3_INP_SHIFT)) & INPUTMUX_QDC1_ICAP3_INP_MASK) +/*! @} */ + +/*! @name FLEXPWM0_SM0_EXTA0 - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..Reserved + * 0b111101..Reserved + * *.. + */ +#define INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM0_EXTA0_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM0_SM0_EXTSYNC - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_SM0_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_SM0_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..Reserved + * 0b111101..Reserved + * *.. + */ +#define INPUTMUX_FLEXPWM0_SM0_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM0_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM0_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM0_SM1_EXTA - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_SM1_EXTA_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_SM1_EXTA_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..Reserved + * 0b111101..Reserved + * *.. + */ +#define INPUTMUX_FLEXPWM0_SM1_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM1_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM1_EXTA_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM0_SM1_EXTSYNC - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_SM1_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_SM1_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..Reserved + * 0b111101..Reserved + * *.. + */ +#define INPUTMUX_FLEXPWM0_SM1_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM1_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM1_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM0_SM2_EXTA - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_SM2_EXTA_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_SM2_EXTA_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..Reserved + * 0b111101..Reserved + * *.. + */ +#define INPUTMUX_FLEXPWM0_SM2_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM2_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM2_EXTA_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM0_SM2_EXTSYNC - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_SM2_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_SM2_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..Reserved + * 0b111101..Reserved + * *.. + */ +#define INPUTMUX_FLEXPWM0_SM2_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_SM2_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_SM2_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM0_FAULT - PWM0 Fault Input Trigger Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_FAULT_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_FAULT_TRIGIN_SHIFT (0U) +/*! TRIGIN - FAULT input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..Reserved + * 0b111101..Reserved + * *.. + */ +#define INPUTMUX_FLEXPWM0_FAULT_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_FAULT_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_FAULT_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXPWM0_FAULT */ +#define INPUTMUX_FLEXPWM0_FAULT_COUNT (4U) + +/*! @name FLEXPWM0_FORCE - PWM0 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM0_FORCE_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM0_FORCE_TRIGIN_SHIFT (0U) +/*! TRIGIN - Trigger input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM1_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM1_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM1_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111100..Reserved + * 0b111101..Reserved + * *.. + */ +#define INPUTMUX_FLEXPWM0_FORCE_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM0_FORCE_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM0_FORCE_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_SM0_EXTA0 - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM0_EXTA0_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM0_EXTA0_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..Reserved + * 0b111101..Reserved + * *.. + */ +#define INPUTMUX_FLEXPWM1_SM0_EXTA0_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM0_EXTA0_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM0_EXTA0_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_SM0_EXTSYNC - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM0_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM0_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..Reserved + * 0b111101..Reserved + * *.. + */ +#define INPUTMUX_FLEXPWM1_SM0_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM0_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM0_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_SM1_EXTA - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM1_EXTA_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM1_EXTA_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..Reserved + * 0b111101..Reserved + * *.. + */ +#define INPUTMUX_FLEXPWM1_SM1_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM1_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM1_EXTA_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_SM1_EXTSYNC - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM1_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM1_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..Reserved + * 0b111101..Reserved + * *.. + */ +#define INPUTMUX_FLEXPWM1_SM1_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM1_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM1_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_SM2_EXTA - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM2_EXTA_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM2_EXTA_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTA input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..Reserved + * 0b111101..Reserved + * *.. + */ +#define INPUTMUX_FLEXPWM1_SM2_EXTA_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM2_EXTA_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM2_EXTA_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_SM2_EXTSYNC - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_SM2_EXTSYNC_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_SM2_EXTSYNC_TRIGIN_SHIFT (0U) +/*! TRIGIN - EXTSYNC input connections for PWM0 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..Reserved + * 0b111101..Reserved + * *.. + */ +#define INPUTMUX_FLEXPWM1_SM2_EXTSYNC_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_SM2_EXTSYNC_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_SM2_EXTSYNC_TRIGIN_MASK) +/*! @} */ + +/*! @name FLEXPWM1_FAULT - PWM1 Fault Input Trigger Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_FAULT_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_FAULT_TRIGIN_SHIFT (0U) +/*! TRIGIN - FAULT input connections for PWM1 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..Reserved + * 0b111101..Reserved + * *.. + */ +#define INPUTMUX_FLEXPWM1_FAULT_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_FAULT_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_FAULT_TRIGIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXPWM1_FAULT */ +#define INPUTMUX_FLEXPWM1_FAULT_COUNT (4U) + +/*! @name FLEXPWM1_FORCE - PWM1 input trigger connections */ +/*! @{ */ + +#define INPUTMUX_FLEXPWM1_FORCE_TRIGIN_MASK (0x3FU) +#define INPUTMUX_FLEXPWM1_FORCE_TRIGIN_SHIFT (0U) +/*! TRIGIN - Trigger input connections for PWM1 + * 0b000000..Reserved + * 0b000001..ARM_TXEV input is selected + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..QDC0_CMP_FLAG0 input is selected + * 0b010000..QDC0_CMP_FLAG1 input is selected + * 0b010001..QDC0_CMP_FLAG2 input is selected + * 0b010010..QDC0_CMP_FLAG3 input is selected + * 0b010011..QDC0_POS_MATCH0 input is selected + * 0b010100..TRIG_IN0 input is selected + * 0b010101..TRIG_IN1 input is selected + * 0b010110..TRIG_IN2 input is selected + * 0b010111..TRIG_IN3 input is selected + * 0b011000..TRIG_IN4 input is selected + * 0b011001..TRIG_IN5 input is selected + * 0b011010..TRIG_IN6 input is selected + * 0b011011..TRIG_IN7 input is selected + * 0b011100..TRIG_IN8 input is selected + * 0b011101..TRIG_IN9 input is selected + * 0b011110..TRIG_IN10 input is selected + * 0b011111..TRIG_IN11 input is selected + * 0b100000..GPIO0 Pin Event Trig 0 input is selected + * 0b100001..GPIO1 Pin Event Trig 0 input is selected + * 0b100010..GPIO2 Pin Event Trig 0 input is selected + * 0b100011..GPIO3 Pin Event Trig 0 input is selected + * 0b100100..GPIO4 Pin Event Trig 0 input is selected + * 0b100101..AOI1_OUT0 input is selected + * 0b100110..AOI1_OUT1 input is selected + * 0b100111..AOI1_OUT2 input is selected + * 0b101000..AOI1_OUT3 input is selected + * 0b101001..Reserved + * 0b101010..Reserved + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..CTimer3_MAT2 input is selected + * 0b101110..CTimer3_MAT3 input is selected + * 0b101111..CTimer4_MAT2 input is selected + * 0b110000..CTimer4_MAT3 input is selected + * 0b110001..QDC1_CMP_FLAG0 input is selected + * 0b110010..QDC1_CMP_FLAG1 input is selected + * 0b110011..QDC1_CMP_FLAG2 input is selected + * 0b110100..QDC1_CMP_FLAG3 input is selected + * 0b110101..QDC1_POS_MATCH0 input is selected + * 0b110110..PWM0_SM0_MUX_TRIG0 input is selected + * 0b110111..PWM0_SM0_MUX_TRIG1 input is selected + * 0b111000..PWM0_SM1_MUX_TRIG0 input is selected + * 0b111001..PWM0_SM1_MUX_TRIG1 input is selected + * 0b111010..PWM0_SM2_MUX_TRIG0 input is selected + * 0b111011..PWM0_SM2_MUX_TRIG1 input is selected + * 0b111100..Reserved + * 0b111101..Reserved + * *.. + */ +#define INPUTMUX_FLEXPWM1_FORCE_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXPWM1_FORCE_TRIGIN_SHIFT)) & INPUTMUX_FLEXPWM1_FORCE_TRIGIN_MASK) +/*! @} */ + +/*! @name PWM0_EXT_CLK - PWM0 external clock trigger */ +/*! @{ */ + +#define INPUTMUX_PWM0_EXT_CLK_TRIGIN_MASK (0xFU) +#define INPUTMUX_PWM0_EXT_CLK_TRIGIN_SHIFT (0U) +/*! TRIGIN - Trigger input connections for PWM + * 0b0000..Reserved + * 0b0001..clk_16k[1] input is selected + * 0b0010..clk_in input is selected + * 0b0011..AOI0_OUT0 input is selected + * 0b0100..AOI0_OUT1 input is selected + * 0b0101..EXTTRIG_IN0 input is selected + * 0b0110..EXTTRIG_IN7 input is selected + * 0b0111..AOI1_OUT0 input is selected + * 0b1000..AOI1_OUT1 input is selected + * *.. + */ +#define INPUTMUX_PWM0_EXT_CLK_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM0_EXT_CLK_TRIGIN_SHIFT)) & INPUTMUX_PWM0_EXT_CLK_TRIGIN_MASK) +/*! @} */ + +/*! @name PWM1_EXT_CLK - PWM1 external clock trigger */ +/*! @{ */ + +#define INPUTMUX_PWM1_EXT_CLK_TRIGIN_MASK (0xFU) +#define INPUTMUX_PWM1_EXT_CLK_TRIGIN_SHIFT (0U) +/*! TRIGIN - Trigger input connections for PWM + * 0b0000..Reserved + * 0b0001..clk_16k[1] input is selected + * 0b0010..clk_in input is selected + * 0b0011..AOI0_OUT0 input is selected + * 0b0100..AOI0_OUT1 input is selected + * 0b0101..EXTTRIG_IN0 input is selected + * 0b0110..EXTTRIG_IN7 input is selected + * 0b0111..AOI1_OUT0 input is selected + * 0b1000..AOI1_OUT1 input is selected + * *.. + */ +#define INPUTMUX_PWM1_EXT_CLK_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PWM1_EXT_CLK_TRIGIN_SHIFT)) & INPUTMUX_PWM1_EXT_CLK_TRIGIN_MASK) +/*! @} */ + +/*! @name AOI0_INPUTK_AOI0_INPUT - AOI0 trigger input connections 0 */ +/*! @{ */ + +#define INPUTMUX_AOI0_INPUTK_AOI0_INPUT_INP_MASK (0x7FU) +#define INPUTMUX_AOI0_INPUTK_AOI0_INPUT_INP_SHIFT (0U) +/*! INP - AOI0 trigger input connections + * 0b0000000..Reserved + * 0b0000001..ADC0_tcomp[0] input is selected + * 0b0000010..ADC0_tcomp[1] input is selected + * 0b0000011..ADC0_tcomp[2] input is selected + * 0b0000100..ADC0_tcomp[3] input is selected + * 0b0000101..CMP0_OUT input is selected + * 0b0000110..CMP1_OUT input is selected + * 0b0000111..Reserved + * 0b0001000..CTimer0_MAT0 input is selected + * 0b0001001..CTimer0_MAT1 input is selected + * 0b0001010..CTimer0_MAT2 input is selected + * 0b0001011..CTimer0_MAT3 input is selected + * 0b0001100..CTimer1_MAT0 + * 0b0001101..CTimer1_MAT1 input is selected + * 0b0001110..CTimer1_MAT2 input is selected + * 0b0001111..CTimer1_MAT3 input is selected + * 0b0010000..CTimer2_MAT0 input is selected + * 0b0010001..CTimer2_MAT1 input is selected + * 0b0010010..CTimer2_MAT2 input is selected + * 0b0010011..CTimer2_MAT3 input is selected + * 0b0010100..LPTMR0 input is selected + * 0b0010101..Reserved + * 0b0010110..QDC0_CMP_FLAG0 input is selected + * 0b0010111..QDC0_CMP_FLAG1 input is selected + * 0b0011000..QDC0_CMP_FLAG2 input is selected + * 0b0011001..QDC0_CMP_FLAG3 input is selected + * 0b0011010..QDC0_POS_MATCH input is selected + * 0b0011011..PWM0_SM0_MUX_TRIG0 0 input is selected + * 0b0011100..PWM0_SM0_MUX_TRIG1 input is selected + * 0b0011101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0011110..PWM0_SM1_MUX_TRIG1 input is selected + * 0b0011111..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0100000..PWM0_SM2_MUX_TRIG1 input is selected + * 0b0100001..Reserved + * 0b0100010..Reserved + * 0b0100011..TRIG_IN0 input is selected + * 0b0100100..TRIG_IN1 input is selected + * 0b0100101..TRIG_IN2 input is selected + * 0b0100110..TRIG_IN3 input is selected + * 0b0100111..TRIG_IN4 input is selected + * 0b0101000..TRIG_IN5 input is selected + * 0b0101001..TRIG_IN6 input is selected + * 0b0101010..TRIG_IN7 input is selected + * 0b0101011..TRIG_IN8 input is selected + * 0b0101100..TRIG_IN9 input is selected + * 0b0101101..TRIG_IN10 input is selected + * 0b0101110..TRIG_IN11 input is selected + * 0b0101111..GPIO0 Pin Event Trig 0 input is selected + * 0b0110000..GPIO1 Pin Event Trig 0 input is selected + * 0b0110001..GPIO2 Pin Event Trig 0 input is selected + * 0b0110010..GPIO3 Pin Event Trig 0 input is selected + * 0b0110011..GPIO4 Pin Event Trig 0 input is selected + * 0b0110100..ADC1_tcomp[0] input is selected + * 0b0110101..ADC1_tcomp[1] input is selected + * 0b0110110..ADC1_tcomp[2] input is selected + * 0b0110111..ADC1_tcomp[3] input is selected + * 0b0111000..CTimer3_MAT0 input is selected + * 0b0111001..CTimer3_MAT1 input is selected + * 0b0111010..CTimer3_MAT2 input is selected + * 0b0111011..CTimer3_MAT3 input is selected + * 0b0111100..CTimer4_MAT0 input is selected + * 0b0111101..CTimer4_MAT1 input is selected + * 0b0111110..CTimer4_MAT2 input is selected + * 0b0111111..CTimer4_MAT3 input is selected + * 0b1000000..FlexIO CH0 input is selected + * 0b1000001..FlexIO CH1 input is selected + * 0b1000010..FlexIO CH2 input is selected + * 0b1000011..FlexIO CH3 input is selected + * 0b1000100..QDC1_CMP_FLAG0 input is selected + * 0b1000101..QDC1_CMP_FLAG1 input is selected + * 0b1000110..QDC1_CMP_FLAG2 input is selected + * 0b1000111..QDC1_CMP_FLAG3 input is selected + * 0b1001000..QDC1_POS_MATCH0 input is selected + * 0b1001001..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1001010..PWM1_SM0_MUX_TRIG1 input is selected + * 0b1001011..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1001100..PWM1_SM1_MUX_TRIG1 input is selected + * 0b1001101..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1001110..PWM1_SM2_MUX_TRIG1 input is selected + * 0b1001111..Reserved + * 0b1010000..Reserved + * *.. + */ +#define INPUTMUX_AOI0_INPUTK_AOI0_INPUT_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_AOI0_INPUTK_AOI0_INPUT_INP_SHIFT)) & INPUTMUX_AOI0_INPUTK_AOI0_INPUT_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_AOI0_INPUTK_AOI0_INPUT */ +#define INPUTMUX_AOI0_INPUTK_AOI0_INPUT_COUNT (16U) + +/*! @name USBFS_TRIG - USB-FS trigger input connections */ +/*! @{ */ + +#define INPUTMUX_USBFS_TRIG_INP_MASK (0xFU) +#define INPUTMUX_USBFS_TRIG_INP_SHIFT (0U) +/*! INP - USB-FS trigger input connections. + * 0b0000..Reserved + * 0b0001..LPUART0 lpuart_trg_txdata input is selected + * 0b0010..LPUART1 lpuart_trg_txdata input is selected + * 0b0011..LPUART2 lpuart_trg_txdata input is selected + * 0b0100..LPUART3 lpuart_trg_txdata input is selected + * 0b0101..LPUART4 lpuart_trg_txda input is selected + * *.. + */ +#define INPUTMUX_USBFS_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_USBFS_TRIG_INP_SHIFT)) & INPUTMUX_USBFS_TRIG_INP_MASK) +/*! @} */ + +/*! @name EXT_TRIG0 - EXT trigger connections 0 */ +/*! @{ */ + +#define INPUTMUX_EXT_TRIG0_INP_MASK (0x1FU) +#define INPUTMUX_EXT_TRIG0_INP_SHIFT (0U) +/*! INP - EXT trigger input connections + * 0b00000..Reserved + * 0b00001..Reserved + * 0b00010..AOI0_OUT0 input is selected + * 0b00011..AOI0_OUT1 input is selected + * 0b00100..AOI0_OUT2 input is selected + * 0b00101..AOI0_OUT3 input is selected + * 0b00110..CMP0_OUT input is selected + * 0b00111..CMP1_OUT input is selected + * 0b01000..Reserved + * 0b01001..LPUART0 input is selected + * 0b01010..LPUART1 input is selected + * 0b01011..LPUART2 input is selected + * 0b01100..LPUART3 input is selected + * 0b01101..LPUART4 input is selected + * 0b01110..AOI1_OUT0 input is selected + * 0b01111..AOI1_OUT1 input is selected + * 0b10000..AOI1_OUT2 input is selected + * 0b10001..AOI1_OUT3 input is selected + * *.. + */ +#define INPUTMUX_EXT_TRIG0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_EXT_TRIG0_INP_SHIFT)) & INPUTMUX_EXT_TRIG0_INP_MASK) +/*! @} */ + +/*! @name CMP1_TRIG - CMP1 input connections */ +/*! @{ */ + +#define INPUTMUX_CMP1_TRIG_TRIGIN_MASK (0x3FU) +#define INPUTMUX_CMP1_TRIG_TRIGIN_SHIFT (0U) +/*! TRIGIN - CMP0 input trigger + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..Reserved + * 0b001000..CTimer0_MAT0 input is selected + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer1_MAT0 + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer2_MAT0 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..LPTMR0 input is selected + * 0b001111..Reserved + * 0b010000..QDC0_POS_MATCH0 + * 0b010001..PWM0_SM0_MUX_TRIG0 input is selected + * 0b010010..PWM0_SM0_MUX_TRIG1 input is selected + * 0b010011..PWM0_SM1_MUX_TRIG0 input is selected + * 0b010100..PWM0_SM1_MUX_TRIG1 input is selected + * 0b010101..PWM0_SM2_MUX_TRIG0 input is selected + * 0b010110..PWM0_SM2_MUX_TRIG1 input is selected + * 0b010111..Reserved + * 0b011000..Reserved + * 0b011001..GPIO0 Pin Event Trig 0 input is selected + * 0b011010..GPIO1 Pin Event Trig 0 input is selected + * 0b011011..GPIO2 Pin Event Trig 0 input is selected + * 0b011100..GPIO3 Pin Event Trig 0 input is selected + * 0b011101..GPIO4 Pin Event Trig 0 input is selected + * 0b011110..WUU input is selected + * 0b011111..AOI1_OUT0 input is selected + * 0b100000..AOI1_OUT1 input is selected + * 0b100001..AOI1_OUT2 input is selected + * 0b100010..AOI1_OUT3 input is selected + * 0b100011..Reserved + * 0b100100..Reserved + * 0b100101..Reserved + * 0b100110..Reserved + * 0b100111..CTimer3_MAT0 + * 0b101000..CTimer3_MAT1 + * 0b101001..CTimer4_MAT0 input is selected + * 0b101010..CTimer4_MAT1 input is selected + * 0b101011..Reserved + * 0b101100..Reserved + * 0b101101..Reserved + * 0b101110..Reserved + * 0b101111..QDC1_POS_MATCH0 input is selected + * 0b110000..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110001..PWM1_SM0_MUX_TRIG1 input is selected + * 0b110010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b110011..PWM1_SM1_MUX_TRIG1 input is selected + * 0b110100..PWM1_SM2_MUX_TRIG0 input is selected + * 0b110101..PWM1_SM2_MUX_TRIG1 input is selected + * 0b110110..Reserved + * 0b110111..Reserved + * *.. + */ +#define INPUTMUX_CMP1_TRIG_TRIGIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_CMP1_TRIG_TRIGIN_SHIFT)) & INPUTMUX_CMP1_TRIG_TRIGIN_MASK) +/*! @} */ + +/*! @name LPI2C2_TRIG - LPI2C2 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPI2C2_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_LPI2C2_TRIG_INP_SHIFT (0U) +/*! INP - LPI2C2 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT0 input is selected + * 0b001010..CTimer0_MAT1 input is selected + * 0b001011..CTimer1_MAT0 input is selected + * 0b001100..CTimer1_MAT1 input is selected + * 0b001101..CTimer2_MAT0 input is selected + * 0b001110..CTimer2_MAT1 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..GPIO0 Pin Event Trig 0 input is selected + * 0b011010..GPIO1 Pin Event Trig 0 input is selected + * 0b011011..GPIO2 Pin Event Trig 0 input is selected + * 0b011100..GPIO3 Pin Event Trig 0 input is selected + * 0b011101..GPIO4 Pin Event Trig 0 input is selected + * 0b011110..WUU input is selected + * 0b011111..AOI1_OUT0 input is selected + * 0b100000..AOI1_OUT1 input is selected + * 0b100001..AOI1_OUT2 input is selected + * 0b100010..AOI1_OUT3 input is selected + * 0b100011..CTimer3_MAT2 input is selected + * 0b100100..CTimer3_MAT3 input is selected + * 0b100101..CTimer4_MAT2 input is selected + * 0b100110..CTimer4_MAT3 input is selected + * 0b100111..FlexIO CH0 input is selected + * 0b101000..FlexIO CH1 input is selected + * 0b101001..FlexIO CH2 input is selected + * 0b101010..FlexIO CH3 input is selected + * *.. + */ +#define INPUTMUX_LPI2C2_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPI2C2_TRIG_INP_SHIFT)) & INPUTMUX_LPI2C2_TRIG_INP_MASK) +/*! @} */ + +/*! @name OPAMP0_TRIG - OPAMP0 Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_OPAMP0_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_OPAMP0_TRIG_INP_SHIFT (0U) +/*! INP - DAC0 trigger input + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT0 input is selected + * 0b001010..CTimer0_MAT1 input is selected + * 0b001011..CTimer1_MAT0 input is selected + * 0b001100..CTimer1_MAT1 input is selected + * 0b001101..CTimer2_MAT0 input is selected + * 0b001110..CTimer2_MAT1 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..Reserved + * 0b010010..PWM0_SM0_MUX_TRIG0 input is selected + * 0b010011..PWM0_SM0_MUX_TRIG1 input is selected + * 0b010100..PWM0_SM1_MUX_TRIG0 input is selected + * 0b010101..PWM0_SM1_MUX_TRIG1 input is selected + * 0b010110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b010111..PWM0_SM2_MUX_TRIG1 input is selected + * 0b011000..Reserved + * 0b011001..Reserved + * 0b011010..GPIO0 Pin Event Trig 0 input is selected + * 0b011011..GPIO1 Pin Event Trig 0 input is selected + * 0b011100..GPIO2 Pin Event Trig 0 input is selected + * 0b011101..GPIO3 Pin Event Trig 0 input is selected + * 0b011110..GPIO4 Pin Event Trig 0 input is selected + * 0b011111..WUU input is selected + * 0b100000..Reserved + * 0b100001..AOI1_OUT0 input is selected + * 0b100010..AOI1_OUT1 input is selected + * 0b100011..AOI1_OUT2 input is selected + * 0b100100..AOI1_OUT3 input is selected + * 0b100101..ADC0_tcomp[0] input is selected + * 0b100110..ADC0_tcomp[1] input is selected + * 0b100111..ADC1_tcomp[0] input is selected + * 0b101000..ADC1_tcomp[1] input is selected + * 0b101001..CTimer3_MAT0 input is selected + * 0b101010..CTimer3_MAT1 input is selected + * 0b101011..CTimer4_MAT0 input is selected + * 0b101100..CTimer4_MAT1 input is selected + * 0b101101..FlexIO CH0 input is selected + * 0b101110..FlexIO CH1 input is selected + * 0b101111..FlexIO CH2 input is selected + * 0b110000..FlexIO CH3 input is selected + * 0b110001..Reserved + * 0b110010..PWM1_SM0_MUX_TRIG0 input is selected + * 0b110011..PWM1_SM0_MUX_TRIG1 input is selected + * 0b110100..PWM1_SM1_MUX_TRIG0 input is selected + * 0b110101..PWM1_SM1_MUX_TRIG1 input is selected + * 0b110110..PWM1_SM2_MUX_TRIG0 input is selected + * 0b110111..PWM1_SM2_MUX_TRIG1 input is selected + * 0b111000..Reserved + * 0b111001..Reserved + * *.. + */ +#define INPUTMUX_OPAMP0_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_OPAMP0_TRIG_INP_SHIFT)) & INPUTMUX_OPAMP0_TRIG_INP_MASK) +/*! @} */ + +/*! @name LPI2C0_TRIG - LPI2C0 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPI2C0_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_LPI2C0_TRIG_INP_SHIFT (0U) +/*! INP - LPI2C0 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT0 input is selected + * 0b001010..CTimer0_MAT1 input is selected + * 0b001011..CTimer1_MAT0 input is selected + * 0b001100..CTimer1_MAT1 input is selected + * 0b001101..CTimer2_MAT0 input is selected + * 0b001110..CTimer2_MAT1 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..GPIO0 Pin Event Trig 0 input is selected + * 0b011010..GPIO1 Pin Event Trig 0 input is selected + * 0b011011..GPIO2 Pin Event Trig 0 input is selected + * 0b011100..GPIO3 Pin Event Trig 0 input is selected + * 0b011101..GPIO4 Pin Event Trig 0 input is selected + * 0b011110..WUU input is selected + * 0b011111..AOI1_OUT0 input is selected + * 0b100000..AOI1_OUT1 input is selected + * 0b100001..AOI1_OUT2 input is selected + * 0b100010..AOI1_OUT3 input is selected + * 0b100011..CTimer3_MAT2 input is selected + * 0b100100..CTimer3_MAT3 input is selected + * 0b100101..CTimer4_MAT2 input is selected + * 0b100110..CTimer4_MAT3 input is selected + * 0b100111..FlexIO CH0 input is selected + * 0b101000..FlexIO CH1 input is selected + * 0b101001..FlexIO CH2 input is selected + * 0b101010..FlexIO CH3 input is selected + * *.. + */ +#define INPUTMUX_LPI2C0_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPI2C0_TRIG_INP_SHIFT)) & INPUTMUX_LPI2C0_TRIG_INP_MASK) +/*! @} */ + +/*! @name LPI2C1_TRIG - LPI2C1 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPI2C1_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_LPI2C1_TRIG_INP_SHIFT (0U) +/*! INP - LPI2C1 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT0 input is selected + * 0b001010..CTimer0_MAT1 input is selected + * 0b001011..CTimer1_MAT0 input is selected + * 0b001100..CTimer1_MAT1 input is selected + * 0b001101..CTimer2_MAT0 input is selected + * 0b001110..CTimer2_MAT1 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..GPIO0 Pin Event Trig 0 input is selected + * 0b011010..GPIO1 Pin Event Trig 0 input is selected + * 0b011011..GPIO2 Pin Event Trig 0 input is selected + * 0b011100..GPIO3 Pin Event Trig 0 input is selected + * 0b011101..GPIO4 Pin Event Trig 0 input is selected + * 0b011110..WUU input is selected + * 0b011111..AOI1_OUT0 input is selected + * 0b100000..AOI1_OUT1 input is selected + * 0b100001..AOI1_OUT2 input is selected + * 0b100010..AOI1_OUT3 input is selected + * 0b100011..CTimer3_MAT2 input is selected + * 0b100100..CTimer3_MAT3 input is selected + * 0b100101..CTimer4_MAT2 input is selected + * 0b100110..CTimer4_MAT3 input is selected + * 0b100111..FlexIO CH0 input is selected + * 0b101000..FlexIO CH1 input is selected + * 0b101001..FlexIO CH2 input is selected + * 0b101010..FlexIO CH3 input is selected + * *.. + */ +#define INPUTMUX_LPI2C1_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPI2C1_TRIG_INP_SHIFT)) & INPUTMUX_LPI2C1_TRIG_INP_MASK) +/*! @} */ + +/*! @name LPSPI0_TRIG - LPSPI0 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPSPI0_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_LPSPI0_TRIG_INP_SHIFT (0U) +/*! INP - LPSPI0 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT1 input is selected + * 0b001010..CTimer0_MAT2 input is selected + * 0b001011..CTimer1_MAT1 input is selected + * 0b001100..CTimer1_MAT2 input is selected + * 0b001101..CTimer2_MAT1 input is selected + * 0b001110..CTimer2_MAT2 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..GPIO0 Pin Event Trig 0 input is selected + * 0b011010..GPIO1 Pin Event Trig 0 input is selected + * 0b011011..GPIO2 Pin Event Trig 0 input is selected + * 0b011100..GPIO3 Pin Event Trig 0 input is selected + * 0b011101..GPIO4 Pin Event Trig 0 input is selected + * 0b011110..WUU input is selected + * 0b011111..AOI1_OUT0 input is selected + * 0b100000..AOI1_OUT1 input is selected + * 0b100001..AOI1_OUT2 input is selected + * 0b100010..AOI1_OUT3 input is selected + * 0b100011..CTimer3_MAT2 input is selected + * 0b100100..CTimer3_MAT3 input is selected + * 0b100101..CTimer4_MAT2 input is selected + * 0b100110..CTimer4_MAT3 input is selected + * 0b100111..FlexIO CH0 input is selected + * 0b101000..FlexIO CH1 input is selected + * 0b101001..FlexIO CH2 input is selected + * 0b101010..FlexIO CH3 input is selected + * *.. + */ +#define INPUTMUX_LPSPI0_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPSPI0_TRIG_INP_SHIFT)) & INPUTMUX_LPSPI0_TRIG_INP_MASK) +/*! @} */ + +/*! @name LPSPI1_TRIG - LPSPI1 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPSPI1_TRIG_INP_MASK (0x3FU) +#define INPUTMUX_LPSPI1_TRIG_INP_SHIFT (0U) +/*! INP - LPSPI1 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT1 input is selected + * 0b001010..CTimer0_MAT2 input is selected + * 0b001011..CTimer1_MAT1 input is selected + * 0b001100..CTimer1_MAT2 input is selected + * 0b001101..CTimer2_MAT1 input is selected + * 0b001110..CTimer2_MAT2 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..GPIO0 Pin Event Trig 0 input is selected + * 0b011010..GPIO1 Pin Event Trig 0 input is selected + * 0b011011..GPIO2 Pin Event Trig 0 input is selected + * 0b011100..GPIO3 Pin Event Trig 0 input is selected + * 0b011101..GPIO4 Pin Event Trig 0 input is selected + * 0b011110..WUU input is selected + * 0b011111..AOI1_OUT0 input is selected + * 0b100000..AOI1_OUT1 input is selected + * 0b100001..AOI1_OUT2 input is selected + * 0b100010..AOI1_OUT3 input is selected + * 0b100011..CTimer3_MAT2 input is selected + * 0b100100..CTimer3_MAT3 input is selected + * 0b100101..CTimer4_MAT2 input is selected + * 0b100110..CTimer4_MAT3 input is selected + * 0b100111..FlexIO CH0 input is selected + * 0b101000..FlexIO CH1 input is selected + * 0b101001..FlexIO CH2 input is selected + * 0b101010..FlexIO CH3 input is selected + * *.. + */ +#define INPUTMUX_LPSPI1_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPSPI1_TRIG_INP_SHIFT)) & INPUTMUX_LPSPI1_TRIG_INP_MASK) +/*! @} */ + +/*! @name LPUART0 - LPUART0 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPUART0_INP_MASK (0x3FU) +#define INPUTMUX_LPUART0_INP_SHIFT (0U) +/*! INP - LPUART0 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..TRIG_IN8 input is selected + * 0b011010..TRIG_IN9 input is selected + * 0b011011..TRIG_IN10 input is selected + * 0b011100..TRIG_IN11 input is selected + * 0b011101..GPIO0 Pin Event Trig 0 input is selected + * 0b011110..GPIO1 Pin Event Trig 0 input is selected + * 0b011111..GPIO2 Pin Event Trig 0 input is selected + * 0b100000..GPIO3 Pin Event Trig 0 input is selected + * 0b100001..GPIO4 Pin Event Trig 0 input is selected + * 0b100010..WUU selected + * 0b100011..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100100..AOI1_OUT0 input is selected + * 0b100101..AOI1_OUT1 input is selected + * 0b100110..AOI1_OUT2 input is selected + * 0b100111..AOI1_OUT3 input is selected + * 0b101000..CTimer3_MAT2 input is selected + * 0b101001..CTimer3_MAT3 input is selected + * 0b101010..CTimer4_MAT2 input is selected + * 0b101011..CTimer4_MAT3 input is selected + * 0b101100..FlexIO CH0 input is selected + * 0b101101..FlexIO CH1 input is selected + * 0b101110..FlexIO CH2 input is selected + * 0b101111..FlexIO CH3 input is selected + * *.. + */ +#define INPUTMUX_LPUART0_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPUART0_INP_SHIFT)) & INPUTMUX_LPUART0_INP_MASK) +/*! @} */ + +/*! @name LPUART1 - LPUART1 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPUART1_INP_MASK (0x3FU) +#define INPUTMUX_LPUART1_INP_SHIFT (0U) +/*! INP - LPUART1 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..TRIG_IN8 input is selected + * 0b011010..TRIG_IN9 input is selected + * 0b011011..TRIG_IN10 input is selected + * 0b011100..TRIG_IN11 input is selected + * 0b011101..GPIO0 Pin Event Trig 0 input is selected + * 0b011110..GPIO1 Pin Event Trig 0 input is selected + * 0b011111..GPIO2 Pin Event Trig 0 input is selected + * 0b100000..GPIO3 Pin Event Trig 0 input is selected + * 0b100001..GPIO4 Pin Event Trig 0 input is selected + * 0b100010..WUU selected + * 0b100011..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100100..AOI1_OUT0 input is selected + * 0b100101..AOI1_OUT1 input is selected + * 0b100110..AOI1_OUT2 input is selected + * 0b100111..AOI1_OUT3 input is selected + * 0b101000..CTimer3_MAT2 input is selected + * 0b101001..CTimer3_MAT3 input is selected + * 0b101010..CTimer4_MAT2 input is selected + * 0b101011..CTimer4_MAT3 input is selected + * 0b101100..FlexIO CH0 input is selected + * 0b101101..FlexIO CH1 input is selected + * 0b101110..FlexIO CH2 input is selected + * 0b101111..FlexIO CH3 input is selected + * *.. + */ +#define INPUTMUX_LPUART1_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPUART1_INP_SHIFT)) & INPUTMUX_LPUART1_INP_MASK) +/*! @} */ + +/*! @name LPUART2 - LPUART2 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPUART2_INP_MASK (0x3FU) +#define INPUTMUX_LPUART2_INP_SHIFT (0U) +/*! INP - LPUART2 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..TRIG_IN8 input is selected + * 0b011010..TRIG_IN9 input is selected + * 0b011011..TRIG_IN10 input is selected + * 0b011100..TRIG_IN11 input is selected + * 0b011101..GPIO0 Pin Event Trig 0 input is selected + * 0b011110..GPIO1 Pin Event Trig 0 input is selected + * 0b011111..GPIO2 Pin Event Trig 0 input is selected + * 0b100000..GPIO3 Pin Event Trig 0 input is selected + * 0b100001..GPIO4 Pin Event Trig 0 input is selected + * 0b100010..WUU selected + * 0b100011..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100100..AOI1_OUT0 input is selected + * 0b100101..AOI1_OUT1 input is selected + * 0b100110..AOI1_OUT2 input is selected + * 0b100111..AOI1_OUT3 input is selected + * 0b101000..CTimer3_MAT2 input is selected + * 0b101001..CTimer3_MAT3 input is selected + * 0b101010..CTimer4_MAT2 input is selected + * 0b101011..CTimer4_MAT3 input is selected + * 0b101100..FlexIO CH0 input is selected + * 0b101101..FlexIO CH1 input is selected + * 0b101110..FlexIO CH2 input is selected + * 0b101111..FlexIO CH3 input is selected + * *.. + */ +#define INPUTMUX_LPUART2_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPUART2_INP_SHIFT)) & INPUTMUX_LPUART2_INP_MASK) +/*! @} */ + +/*! @name LPUART3 - LPUART3 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPUART3_INP_MASK (0x3FU) +#define INPUTMUX_LPUART3_INP_SHIFT (0U) +/*! INP - LPUART3 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..TRIG_IN8 input is selected + * 0b011010..TRIG_IN9 input is selected + * 0b011011..TRIG_IN10 input is selected + * 0b011100..TRIG_IN11 input is selected + * 0b011101..GPIO0 Pin Event Trig 0 input is selected + * 0b011110..GPIO1 Pin Event Trig 0 input is selected + * 0b011111..GPIO2 Pin Event Trig 0 input is selected + * 0b100000..GPIO3 Pin Event Trig 0 input is selected + * 0b100001..GPIO4 Pin Event Trig 0 input is selected + * 0b100010..WUU selected + * 0b100011..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100100..AOI1_OUT0 input is selected + * 0b100101..AOI1_OUT1 input is selected + * 0b100110..AOI1_OUT2 input is selected + * 0b100111..AOI1_OUT3 input is selected + * 0b101000..CTimer3_MAT2 input is selected + * 0b101001..CTimer3_MAT3 input is selected + * 0b101010..CTimer4_MAT2 input is selected + * 0b101011..CTimer4_MAT3 input is selected + * 0b101100..FlexIO CH0 input is selected + * 0b101101..FlexIO CH1 input is selected + * 0b101110..FlexIO CH2 input is selected + * 0b101111..FlexIO CH3 input is selected + * *.. + */ +#define INPUTMUX_LPUART3_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPUART3_INP_SHIFT)) & INPUTMUX_LPUART3_INP_MASK) +/*! @} */ + +/*! @name LPUART4 - LPUART4 trigger input connections */ +/*! @{ */ + +#define INPUTMUX_LPUART4_INP_MASK (0x3FU) +#define INPUTMUX_LPUART4_INP_SHIFT (0U) +/*! INP - LPUART4 trigger input connections + * 0b000000..Reserved + * 0b000001..Reserved + * 0b000010..AOI0_OUT0 input is selected + * 0b000011..AOI0_OUT1 input is selected + * 0b000100..AOI0_OUT2 input is selected + * 0b000101..AOI0_OUT3 input is selected + * 0b000110..CMP0_OUT input is selected + * 0b000111..CMP1_OUT input is selected + * 0b001000..Reserved + * 0b001001..CTimer0_MAT2 input is selected + * 0b001010..CTimer0_MAT3 input is selected + * 0b001011..CTimer1_MAT2 input is selected + * 0b001100..CTimer1_MAT3 input is selected + * 0b001101..CTimer2_MAT2 input is selected + * 0b001110..CTimer2_MAT3 input is selected + * 0b001111..LPTMR0 input is selected + * 0b010000..Reserved + * 0b010001..TRIG_IN0 input is selected + * 0b010010..TRIG_IN1 input is selected + * 0b010011..TRIG_IN2 input is selected + * 0b010100..TRIG_IN3 input is selected + * 0b010101..TRIG_IN4 input is selected + * 0b010110..TRIG_IN5 input is selected + * 0b010111..TRIG_IN6 input is selected + * 0b011000..TRIG_IN7 input is selected + * 0b011001..TRIG_IN8 input is selected + * 0b011010..TRIG_IN9 input is selected + * 0b011011..TRIG_IN10 input is selected + * 0b011100..TRIG_IN11 input is selected + * 0b011101..GPIO0 Pin Event Trig 0 input is selected + * 0b011110..GPIO1 Pin Event Trig 0 input is selected + * 0b011111..GPIO2 Pin Event Trig 0 input is selected + * 0b100000..GPIO3 Pin Event Trig 0 input is selected + * 0b100001..GPIO4 Pin Event Trig 0 input is selected + * 0b100010..WUU selected + * 0b100011..USB0 ipp_ind_uart_rxd_usbmux input is selected + * 0b100100..AOI1_OUT0 input is selected + * 0b100101..AOI1_OUT1 input is selected + * 0b100110..AOI1_OUT2 input is selected + * 0b100111..AOI1_OUT3 input is selected + * 0b101000..CTimer3_MAT2 input is selected + * 0b101001..CTimer3_MAT3 input is selected + * 0b101010..CTimer4_MAT2 input is selected + * 0b101011..CTimer4_MAT3 input is selected + * 0b101100..FlexIO CH0 input is selected + * 0b101101..FlexIO CH1 input is selected + * 0b101110..FlexIO CH2 input is selected + * 0b101111..FlexIO CH3 input is selected + * *.. + */ +#define INPUTMUX_LPUART4_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_LPUART4_INP_SHIFT)) & INPUTMUX_LPUART4_INP_MASK) +/*! @} */ + +/*! @name FLEXIO_TRIGN_FLEXIO_TRIG - FlexIO Trigger Input Connections */ +/*! @{ */ + +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_MASK (0x7FU) +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_SHIFT (0U) +/*! INP - Input number for FlexIO0. + * 0b0000000..Reserved + * 0b0000001..AOI0_OUT0 input is selected + * 0b0000010..AOI0_OUT1 input is selected + * 0b0000011..AOI0_OUT2 input is selected + * 0b0000100..AOI0_OUT3 input is selected + * 0b0000101..ADC0_tcomp[0] input is selected + * 0b0000110..ADC0_tcomp[1] input is selected + * 0b0000111..ADC0_tcomp[2] input is selected + * 0b0001000..ADC0_tcomp[3] input is selected + * 0b0001001..CMP0_OUT input is selected + * 0b0001010..CMP1_OUT input is selected + * 0b0001011..Reserved + * 0b0001100..CTimer0_MAT1 input is selected + * 0b0001101..CTimer0_MAT2 input is selected + * 0b0001110..CTimer1_MAT1 input is selected + * 0b0001111..CTimer1_MAT2 input is selected + * 0b0010000..CTimer2_MAT1 input is selected + * 0b0010001..CTimer2_MAT2 input is selected + * 0b0010010..LPTMR0 input is selected + * 0b0010011..Reserved (LPTMR1) input is selected + * 0b0010100..PWM0_SM0_MUX_TRIG0 input is selected + * 0b0010101..PWM0_SM1_MUX_TRIG0 input is selected + * 0b0010110..PWM0_SM2_MUX_TRIG0 input is selected + * 0b0010111..Reserved + * 0b0011000..TRIG_IN0 input is selected + * 0b0011001..TRIG_IN1 input is selected + * 0b0011010..TRIG_IN2 input is selected + * 0b0011011..TRIG_IN3 input is selected + * 0b0011100..TRIG_IN4 input is selected + * 0b0011101..TRIG_IN5 input is selected + * 0b0011110..TRIG_IN6 input is selected + * 0b0011111..TRIG_IN7 input is selected + * 0b0100000..GPIO0 Pin Event Trig 0 input is selected + * 0b0100001..GPIO2 Pin Event Trig 0 input is selected + * 0b0100010..GPIO3 Pin Event Trig 0 input is selected + * 0b0100011..GPIO4 Pin Event Trig 0 input is selected + * 0b0100100..WUU input is selected + * 0b0100101..PWM1_A0_TRIG0 input is selected + * 0b0100110..LPI2C0 Master End of Packet + * 0b0100111..LPI2C0 Slave End of Packet + * 0b0101000..LPI2C1 Master End of Packet + * 0b0101001..LPI2C1 Slave End of Packet + * 0b0101010..LPSPI0 End of Frame + * 0b0101011..LPSPI0 Received Data Word + * 0b0101100..LPSPI1 End of Frame + * 0b0101101..LPSPI1 Received Data Word + * 0b0101110..LPUART0 Received Data Word + * 0b0101111..LPUART0 Transmitted Data Word + * 0b0110000..LPUART0 Receive Line Idle + * 0b0110001..LPUART1 Received Data Word + * 0b0110010..LPUART1 Transmitted Data Word + * 0b0110011..LPUART1 Receive Line Idle + * 0b0110100..LPUART2 Received Data Word + * 0b0110101..LPUART2 Transmitted Data Word + * 0b0110110..LPUART2 Receive Line Idle + * 0b0110111..LPUART3 Received Data Word + * 0b0111000..LPUART3 Transmitted Data Word + * 0b0111001..LPUART3 Receive Line Idle + * 0b0111010..LPUART4 Received Data Word + * 0b0111011..LPUART4 Transmitted Data Word + * 0b0111100..LPUART4 Receive Line Idle + * 0b0111101..AOI1_OUT0 input is selected + * 0b0111110..AOI1_OUT1 input is selected + * 0b0111111..AOI1_OUT2 input is selected + * 0b1000000..AOI1_OUT3 input is selected + * 0b1000001..ADC1_tcomp[0] input is selected + * 0b1000010..ADC1_tcomp[1] input is selected + * 0b1000011..ADC1_tcomp[2] input is selected + * 0b1000100..ADC1_tcomp[3] input is selected + * 0b1000101..CTimer3_MAT2 input is selected + * 0b1000110..CTimer3_MAT3 input is selected + * 0b1000111..CTimer4_MAT2 input is selected + * 0b1001000..CTimer4_MAT3 input is selected + * 0b1001001..PWM1_SM0_MUX_TRIG0 input is selected + * 0b1001010..PWM1_SM1_MUX_TRIG0 input is selected + * 0b1001011..PWM1_SM2_MUX_TRIG0 input is selected + * 0b1001100..Reserved + * 0b1001101..LPI2C2 Master End of Packet + * 0b1001110..LPI2C2 Slave End of Packet + * 0b1001111..LPI2C3 Master End of Packet + * 0b1010000..LPI2C3 Slave End of Packet + * *.. + */ +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_SHIFT)) & INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG */ +#define INPUTMUX_FLEXIO_TRIGN_FLEXIO_TRIG_COUNT (4U) + + +/*! + * @} + */ /* end of group INPUTMUX_Register_Masks */ + + +/* INPUTMUX - Peripheral instance base addresses */ +/** Peripheral INPUTMUX0 base address */ +#define INPUTMUX0_BASE (0x40001000u) +/** Peripheral INPUTMUX0 base pointer */ +#define INPUTMUX0 ((INPUTMUX_Type *)INPUTMUX0_BASE) +/** Array initializer of INPUTMUX peripheral base addresses */ +#define INPUTMUX_BASE_ADDRS { INPUTMUX0_BASE } +/** Array initializer of INPUTMUX peripheral base pointers */ +#define INPUTMUX_BASE_PTRS { INPUTMUX0 } + +/*! + * @} + */ /* end of group INPUTMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPCMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPCMP_Peripheral_Access_Layer LPCMP Peripheral Access Layer + * @{ + */ + +/** LPCMP - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t CCR0; /**< Comparator Control Register 0, offset: 0x8 */ + __IO uint32_t CCR1; /**< Comparator Control Register 1, offset: 0xC */ + __IO uint32_t CCR2; /**< Comparator Control Register 2, offset: 0x10 */ + uint8_t RESERVED_0[4]; + __IO uint32_t DCR; /**< DAC Control, offset: 0x18 */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x1C */ + __IO uint32_t CSR; /**< Comparator Status, offset: 0x20 */ + __IO uint32_t RRCR0; /**< Round Robin Control Register 0, offset: 0x24 */ + __IO uint32_t RRCR1; /**< Round Robin Control Register 1, offset: 0x28 */ + __IO uint32_t RRCSR; /**< Round Robin Control and Status, offset: 0x2C */ + __IO uint32_t RRSR; /**< Round Robin Status, offset: 0x30 */ + uint8_t RESERVED_1[4]; + __IO uint32_t RRCR2; /**< Round Robin Control Register 2, offset: 0x38 */ +} LPCMP_Type; + +/* ---------------------------------------------------------------------------- + -- LPCMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPCMP_Register_Masks LPCMP Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPCMP_VERID_FEATURE_MASK (0xFFFFU) +#define LPCMP_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000001..Round robin feature + */ +#define LPCMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_FEATURE_SHIFT)) & LPCMP_VERID_FEATURE_MASK) + +#define LPCMP_VERID_MINOR_MASK (0xFF0000U) +#define LPCMP_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPCMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MINOR_SHIFT)) & LPCMP_VERID_MINOR_MASK) + +#define LPCMP_VERID_MAJOR_MASK (0xFF000000U) +#define LPCMP_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPCMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MAJOR_SHIFT)) & LPCMP_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPCMP_PARAM_DAC_RES_MASK (0xFU) +#define LPCMP_PARAM_DAC_RES_SHIFT (0U) +/*! DAC_RES - DAC Resolution + * 0b0000..4-bit DAC + * 0b0001..6-bit DAC + * 0b0010..8-bit DAC + * 0b0011..10-bit DAC + * 0b0100..12-bit DAC + * 0b0101..14-bit DAC + * 0b0110..16-bit DAC + */ +#define LPCMP_PARAM_DAC_RES(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_PARAM_DAC_RES_SHIFT)) & LPCMP_PARAM_DAC_RES_MASK) +/*! @} */ + +/*! @name CCR0 - Comparator Control Register 0 */ +/*! @{ */ + +#define LPCMP_CCR0_CMP_EN_MASK (0x1U) +#define LPCMP_CCR0_CMP_EN_SHIFT (0U) +/*! CMP_EN - Comparator Enable + * 0b0..Disable (The analog logic remains off and consumes no power.) + * 0b1..Enable + */ +#define LPCMP_CCR0_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_EN_SHIFT)) & LPCMP_CCR0_CMP_EN_MASK) + +#define LPCMP_CCR0_CMP_STOP_EN_MASK (0x2U) +#define LPCMP_CCR0_CMP_STOP_EN_SHIFT (1U) +/*! CMP_STOP_EN - Comparator Deep sleep Mode Enable + * 0b0..Disables the analog comparator regardless of CMP_EN. + * 0b1..Allows CMP_EN to enable the analog comparator. + */ +#define LPCMP_CCR0_CMP_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_STOP_EN_SHIFT)) & LPCMP_CCR0_CMP_STOP_EN_MASK) +/*! @} */ + +/*! @name CCR1 - Comparator Control Register 1 */ +/*! @{ */ + +#define LPCMP_CCR1_WINDOW_EN_MASK (0x1U) +#define LPCMP_CCR1_WINDOW_EN_SHIFT (0U) +/*! WINDOW_EN - Windowing Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_CCR1_WINDOW_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_EN_SHIFT)) & LPCMP_CCR1_WINDOW_EN_MASK) + +#define LPCMP_CCR1_SAMPLE_EN_MASK (0x2U) +#define LPCMP_CCR1_SAMPLE_EN_SHIFT (1U) +/*! SAMPLE_EN - Sampling Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_CCR1_SAMPLE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_SAMPLE_EN_SHIFT)) & LPCMP_CCR1_SAMPLE_EN_MASK) + +#define LPCMP_CCR1_DMA_EN_MASK (0x4U) +#define LPCMP_CCR1_DMA_EN_SHIFT (2U) +/*! DMA_EN - DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_CCR1_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_DMA_EN_SHIFT)) & LPCMP_CCR1_DMA_EN_MASK) + +#define LPCMP_CCR1_COUT_INV_MASK (0x8U) +#define LPCMP_CCR1_COUT_INV_SHIFT (3U) +/*! COUT_INV - Comparator Invert + * 0b0..Do not invert + * 0b1..Invert + */ +#define LPCMP_CCR1_COUT_INV(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_INV_SHIFT)) & LPCMP_CCR1_COUT_INV_MASK) + +#define LPCMP_CCR1_COUT_SEL_MASK (0x10U) +#define LPCMP_CCR1_COUT_SEL_SHIFT (4U) +/*! COUT_SEL - Comparator Output Select + * 0b0..Use COUT (filtered) + * 0b1..Use COUTA (unfiltered) + */ +#define LPCMP_CCR1_COUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_SEL_SHIFT)) & LPCMP_CCR1_COUT_SEL_MASK) + +#define LPCMP_CCR1_COUT_PEN_MASK (0x20U) +#define LPCMP_CCR1_COUT_PEN_SHIFT (5U) +/*! COUT_PEN - Comparator Output Pin Enable + * 0b0..Not available + * 0b1..Available + */ +#define LPCMP_CCR1_COUT_PEN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_PEN_SHIFT)) & LPCMP_CCR1_COUT_PEN_MASK) + +#define LPCMP_CCR1_COUTA_OWEN_MASK (0x40U) +#define LPCMP_CCR1_COUTA_OWEN_SHIFT (6U) +/*! COUTA_OWEN - COUTA_OW Enable + * 0b0..COUTA holds the last sampled value. + * 0b1..Enables the COUTA signal value to be defined by COUTA_OW. + */ +#define LPCMP_CCR1_COUTA_OWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_OWEN_SHIFT)) & LPCMP_CCR1_COUTA_OWEN_MASK) + +#define LPCMP_CCR1_COUTA_OW_MASK (0x80U) +#define LPCMP_CCR1_COUTA_OW_SHIFT (7U) +/*! COUTA_OW - COUTA Output Level for Closed Window + * 0b0..COUTA is 0 + * 0b1..COUTA is 1 + */ +#define LPCMP_CCR1_COUTA_OW(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_OW_SHIFT)) & LPCMP_CCR1_COUTA_OW_MASK) + +#define LPCMP_CCR1_WINDOW_INV_MASK (0x100U) +#define LPCMP_CCR1_WINDOW_INV_SHIFT (8U) +/*! WINDOW_INV - WINDOW/SAMPLE Signal Invert + * 0b0..Do not invert + * 0b1..Invert + */ +#define LPCMP_CCR1_WINDOW_INV(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_INV_SHIFT)) & LPCMP_CCR1_WINDOW_INV_MASK) + +#define LPCMP_CCR1_WINDOW_CLS_MASK (0x200U) +#define LPCMP_CCR1_WINDOW_CLS_SHIFT (9U) +/*! WINDOW_CLS - COUT Event Window Close + * 0b0..COUT event cannot close the window + * 0b1..COUT event can close the window + */ +#define LPCMP_CCR1_WINDOW_CLS(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_CLS_SHIFT)) & LPCMP_CCR1_WINDOW_CLS_MASK) + +#define LPCMP_CCR1_EVT_SEL_MASK (0xC00U) +#define LPCMP_CCR1_EVT_SEL_SHIFT (10U) +/*! EVT_SEL - COUT Event Select + * 0b00..Rising edge + * 0b01..Falling edge + * 0b1x..Both edges + */ +#define LPCMP_CCR1_EVT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_EVT_SEL_SHIFT)) & LPCMP_CCR1_EVT_SEL_MASK) + +#define LPCMP_CCR1_FUNC_CLK_SEL_MASK (0x3000U) +#define LPCMP_CCR1_FUNC_CLK_SEL_SHIFT (12U) +/*! FUNC_CLK_SEL - Functional Clock Source Select + * 0b00..Select functional clock source 0 + * 0b01..Select functional clock source 1 + * 0b10..Select functional clock source 2 + * 0b11..Select functional clock source 3 + */ +#define LPCMP_CCR1_FUNC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FUNC_CLK_SEL_SHIFT)) & LPCMP_CCR1_FUNC_CLK_SEL_MASK) + +#define LPCMP_CCR1_FILT_CNT_MASK (0x70000U) +#define LPCMP_CCR1_FILT_CNT_SHIFT (16U) +/*! FILT_CNT - Filter Sample Count + * 0b000..Filter is bypassed: COUT = COUTA + * 0b001..1 consecutive sample (Comparator output is simply sampled.) + * 0b010..2 consecutive samples + * 0b011..3 consecutive samples + * 0b100..4 consecutive samples + * 0b101..5 consecutive samples + * 0b110..6 consecutive samples + * 0b111..7 consecutive samples + */ +#define LPCMP_CCR1_FILT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_CNT_SHIFT)) & LPCMP_CCR1_FILT_CNT_MASK) + +#define LPCMP_CCR1_FILT_PER_MASK (0xFF000000U) +#define LPCMP_CCR1_FILT_PER_SHIFT (24U) +/*! FILT_PER - Filter Sample Period */ +#define LPCMP_CCR1_FILT_PER(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_PER_SHIFT)) & LPCMP_CCR1_FILT_PER_MASK) +/*! @} */ + +/*! @name CCR2 - Comparator Control Register 2 */ +/*! @{ */ + +#define LPCMP_CCR2_CMP_HPMD_MASK (0x1U) +#define LPCMP_CCR2_CMP_HPMD_SHIFT (0U) +/*! CMP_HPMD - CMP High Power Mode Select + * 0b0..Low power (speed) comparison mode + * 0b1..High power (speed) comparison mode + */ +#define LPCMP_CCR2_CMP_HPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_HPMD_SHIFT)) & LPCMP_CCR2_CMP_HPMD_MASK) + +#define LPCMP_CCR2_CMP_NPMD_MASK (0x2U) +#define LPCMP_CCR2_CMP_NPMD_SHIFT (1U) +/*! CMP_NPMD - CMP Nano Power Mode Select + * 0b0..Disables CMP Nano power mode. CCR2[CMP_HPMD] determines the mode for the comparator. + * 0b1..Enables CMP Nano power mode. + */ +#define LPCMP_CCR2_CMP_NPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_NPMD_SHIFT)) & LPCMP_CCR2_CMP_NPMD_MASK) + +#define LPCMP_CCR2_HYSTCTR_MASK (0x30U) +#define LPCMP_CCR2_HYSTCTR_SHIFT (4U) +/*! HYSTCTR - Comparator Hysteresis Control + * 0b00..Level 0: Analog comparator hysteresis 0 mV. + * 0b01..Level 1: Analog comparator hysteresis 10 mV. + * 0b10..Level 2: Analog comparator hysteresis 20 mV. + * 0b11..Level 3: Analog comparator hysteresis 30 mV. + */ +#define LPCMP_CCR2_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_HYSTCTR_SHIFT)) & LPCMP_CCR2_HYSTCTR_MASK) + +#define LPCMP_CCR2_PSEL_MASK (0x70000U) +#define LPCMP_CCR2_PSEL_SHIFT (16U) +/*! PSEL - Plus Input MUX Select + * 0b000..Input 0p + * 0b001..Input 1p + * 0b010..Input 2p + * 0b011..Input 3p + * 0b100..Input 4p + * 0b101..Input 5p + * 0b110..Reserved + * 0b111..Internal DAC output + */ +#define LPCMP_CCR2_PSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_PSEL_SHIFT)) & LPCMP_CCR2_PSEL_MASK) + +#define LPCMP_CCR2_MSEL_MASK (0x700000U) +#define LPCMP_CCR2_MSEL_SHIFT (20U) +/*! MSEL - Minus Input MUX Select + * 0b000..Input 0m + * 0b001..Input 1m + * 0b010..Input 2m + * 0b011..Input 3m + * 0b100..Input 4m + * 0b101..Input 5m + * 0b110..Reserved + * 0b111..Internal DAC output + */ +#define LPCMP_CCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_MSEL_SHIFT)) & LPCMP_CCR2_MSEL_MASK) +/*! @} */ + +/*! @name DCR - DAC Control */ +/*! @{ */ + +#define LPCMP_DCR_DAC_EN_MASK (0x1U) +#define LPCMP_DCR_DAC_EN_SHIFT (0U) +/*! DAC_EN - DAC Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_DCR_DAC_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_EN_SHIFT)) & LPCMP_DCR_DAC_EN_MASK) + +#define LPCMP_DCR_DAC_HPMD_MASK (0x2U) +#define LPCMP_DCR_DAC_HPMD_SHIFT (1U) +/*! DAC_HPMD - DAC High Power Mode + * 0b0..Disable + * 0b1..Enable + */ +#define LPCMP_DCR_DAC_HPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_HPMD_SHIFT)) & LPCMP_DCR_DAC_HPMD_MASK) + +#define LPCMP_DCR_VRSEL_MASK (0x100U) +#define LPCMP_DCR_VRSEL_SHIFT (8U) +/*! VRSEL - DAC Reference High Voltage Source Select + * 0b0..VREFH0 + * 0b1..VREFH1 + */ +#define LPCMP_DCR_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_VRSEL_SHIFT)) & LPCMP_DCR_VRSEL_MASK) + +#define LPCMP_DCR_DAC_DATA_MASK (0xFF0000U) +#define LPCMP_DCR_DAC_DATA_SHIFT (16U) +/*! DAC_DATA - DAC Output Voltage Select */ +#define LPCMP_DCR_DAC_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_DATA_SHIFT)) & LPCMP_DCR_DAC_DATA_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define LPCMP_IER_CFR_IE_MASK (0x1U) +#define LPCMP_IER_CFR_IE_SHIFT (0U) +/*! CFR_IE - Comparator Flag Rising Interrupt Enable + * 0b0..Disables the comparator flag rising interrupt. + * 0b1..Enables the comparator flag rising interrupt when CFR is set. + */ +#define LPCMP_IER_CFR_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFR_IE_SHIFT)) & LPCMP_IER_CFR_IE_MASK) + +#define LPCMP_IER_CFF_IE_MASK (0x2U) +#define LPCMP_IER_CFF_IE_SHIFT (1U) +/*! CFF_IE - Comparator Flag Falling Interrupt Enable + * 0b0..Disables the comparator flag falling interrupt. + * 0b1..Enables the comparator flag falling interrupt when CFF is set. + */ +#define LPCMP_IER_CFF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFF_IE_SHIFT)) & LPCMP_IER_CFF_IE_MASK) + +#define LPCMP_IER_RRF_IE_MASK (0x4U) +#define LPCMP_IER_RRF_IE_SHIFT (2U) +/*! RRF_IE - Round-Robin Flag Interrupt Enable + * 0b0..Disables the round-robin flag interrupt. + * 0b1..Enables the round-robin flag interrupt when the comparison result changes for a given channel. + */ +#define LPCMP_IER_RRF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_RRF_IE_SHIFT)) & LPCMP_IER_RRF_IE_MASK) +/*! @} */ + +/*! @name CSR - Comparator Status */ +/*! @{ */ + +#define LPCMP_CSR_CFR_MASK (0x1U) +#define LPCMP_CSR_CFR_SHIFT (0U) +/*! CFR - Analog Comparator Flag Rising + * 0b0..Not detected + * 0b1..Detected + */ +#define LPCMP_CSR_CFR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFR_SHIFT)) & LPCMP_CSR_CFR_MASK) + +#define LPCMP_CSR_CFF_MASK (0x2U) +#define LPCMP_CSR_CFF_SHIFT (1U) +/*! CFF - Analog Comparator Flag Falling + * 0b0..Not detected + * 0b1..Detected + */ +#define LPCMP_CSR_CFF(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFF_SHIFT)) & LPCMP_CSR_CFF_MASK) + +#define LPCMP_CSR_RRF_MASK (0x4U) +#define LPCMP_CSR_RRF_SHIFT (2U) +/*! RRF - Round-Robin Flag + * 0b0..Not detected + * 0b1..Detected + */ +#define LPCMP_CSR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_RRF_SHIFT)) & LPCMP_CSR_RRF_MASK) + +#define LPCMP_CSR_COUT_MASK (0x100U) +#define LPCMP_CSR_COUT_SHIFT (8U) +/*! COUT - Analog Comparator Output */ +#define LPCMP_CSR_COUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_COUT_SHIFT)) & LPCMP_CSR_COUT_MASK) +/*! @} */ + +/*! @name RRCR0 - Round Robin Control Register 0 */ +/*! @{ */ + +#define LPCMP_RRCR0_RR_EN_MASK (0x1U) +#define LPCMP_RRCR0_RR_EN_SHIFT (0U) +/*! RR_EN - Round-Robin Enable + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR0_RR_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK) + +#define LPCMP_RRCR0_RR_TRG_SEL_MASK (0x2U) +#define LPCMP_RRCR0_RR_TRG_SEL_SHIFT (1U) +/*! RR_TRG_SEL - Round-Robin Trigger Select + * 0b0..External trigger + * 0b1..Internal trigger + */ +#define LPCMP_RRCR0_RR_TRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_TRG_SEL_SHIFT)) & LPCMP_RRCR0_RR_TRG_SEL_MASK) + +#define LPCMP_RRCR0_RR_EXTTRG_SEL_MASK (0x3CU) +#define LPCMP_RRCR0_RR_EXTTRG_SEL_SHIFT (2U) +/*! RR_EXTTRG_SEL - External Trigger Source Select + * 0b0000..Select external trigger source 0 + * 0b0001..Select external trigger source 1 + * 0b0010..Select external trigger source 2 + * 0b0011..Select external trigger source 3 + * 0b0100..Select external trigger source 4 + * 0b0101..Select external trigger source 5 + * 0b0110..Select external trigger source 6 + * 0b0111..Select external trigger source 7 + * 0b1000..Select external trigger source 8 + * 0b1001..Select external trigger source 9 + * 0b1010..Select external trigger source 10 + * 0b1011..Select external trigger source 11 + * 0b1100..Select external trigger source 12 + * 0b1101..Select external trigger source 13 + * 0b1110..Select external trigger source 14 + * 0b1111..Select external trigger source 15 + */ +#define LPCMP_RRCR0_RR_EXTTRG_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EXTTRG_SEL_SHIFT)) & LPCMP_RRCR0_RR_EXTTRG_SEL_MASK) + +#define LPCMP_RRCR0_RR_NSAM_MASK (0x300U) +#define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) +/*! RR_NSAM - Number of Sample Clocks + * 0b00..0 clock + * 0b01..1 clock + * 0b10..2 clocks + * 0b11..3 clocks + */ +#define LPCMP_RRCR0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCMP_RRCR0_RR_NSAM_MASK) + +#define LPCMP_RRCR0_RR_CLK_SEL_MASK (0x3000U) +#define LPCMP_RRCR0_RR_CLK_SEL_SHIFT (12U) +/*! RR_CLK_SEL - Round Robin Clock Source Select + * 0b00..Select Round Robin clock Source 0 + * 0b01..Select Round Robin clock Source 1 + * 0b10..Select Round Robin clock Source 2 + * 0b11..Select Round Robin clock Source 3 + */ +#define LPCMP_RRCR0_RR_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_CLK_SEL_SHIFT)) & LPCMP_RRCR0_RR_CLK_SEL_MASK) + +#define LPCMP_RRCR0_RR_INITMOD_MASK (0x3F0000U) +#define LPCMP_RRCR0_RR_INITMOD_SHIFT (16U) +/*! RR_INITMOD - Initialization Delay Modulus + * 0b000000..63 cycles (same as 111111b) + * 0b000001-0b111111..1 to 63 cycles + */ +#define LPCMP_RRCR0_RR_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_INITMOD_SHIFT)) & LPCMP_RRCR0_RR_INITMOD_MASK) + +#define LPCMP_RRCR0_RR_SAMPLE_CNT_MASK (0xF000000U) +#define LPCMP_RRCR0_RR_SAMPLE_CNT_SHIFT (24U) +/*! RR_SAMPLE_CNT - Number of Sample for One Channel + * 0b0000..1 samples + * 0b0001..2 samples + * 0b0010..3 samples + * 0b0011..4 samples + * 0b0100..5 samples + * 0b0101..6 samples + * 0b0110..7 samples + * 0b0111..8 samples + * 0b1000..9 samples + * 0b1001..10 samples + * 0b1010..11 samples + * 0b1011..12 samples + * 0b1100..13 samples + * 0b1101..14 samples + * 0b1110..15 samples + * 0b1111..16 samples + */ +#define LPCMP_RRCR0_RR_SAMPLE_CNT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_SAMPLE_CNT_SHIFT)) & LPCMP_RRCR0_RR_SAMPLE_CNT_MASK) + +#define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK (0xF0000000U) +#define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_SHIFT (28U) +/*! RR_SAMPLE_THRESHOLD - Sample Time Threshold + * 0b0000..At least 1 sampled "1", the final result is "1" + * 0b0001..At least 2 sampled "1", the final result is "1" + * 0b0010..At least 3 sampled "1", the final result is "1" + * 0b0011..At least 4 sampled "1", the final result is "1" + * 0b0100..At least 5 sampled "1", the final result is "1" + * 0b0101..At least 6 sampled "1", the final result is "1" + * 0b0110..At least 7 sampled "1", the final result is "1" + * 0b0111..At least 8 sampled "1", the final result is "1" + * 0b1000..At least 9 sampled "1", the final result is "1" + * 0b1001..At least 10 sampled "1", the final result is "1" + * 0b1010..At least 11 sampled "1", the final result is "1" + * 0b1011..At least 12 sampled "1", the final result is "1" + * 0b1100..At least 13 sampled "1", the final result is "1" + * 0b1101..At least 14 sampled "1", the final result is "1" + * 0b1110..At least 15 sampled "1", the final result is "1" + * 0b1111..At least 16 sampled "1", the final result is "1" + */ +#define LPCMP_RRCR0_RR_SAMPLE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_SHIFT)) & LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK) +/*! @} */ + +/*! @name RRCR1 - Round Robin Control Register 1 */ +/*! @{ */ + +#define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) +#define LPCMP_RRCR1_RR_CH0EN_SHIFT (0U) +/*! RR_CH0EN - Channel 0 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK) + +#define LPCMP_RRCR1_RR_CH1EN_MASK (0x2U) +#define LPCMP_RRCR1_RR_CH1EN_SHIFT (1U) +/*! RR_CH1EN - Channel 1 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH1EN_SHIFT)) & LPCMP_RRCR1_RR_CH1EN_MASK) + +#define LPCMP_RRCR1_RR_CH2EN_MASK (0x4U) +#define LPCMP_RRCR1_RR_CH2EN_SHIFT (2U) +/*! RR_CH2EN - Channel 2 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH2EN_SHIFT)) & LPCMP_RRCR1_RR_CH2EN_MASK) + +#define LPCMP_RRCR1_RR_CH3EN_MASK (0x8U) +#define LPCMP_RRCR1_RR_CH3EN_SHIFT (3U) +/*! RR_CH3EN - Channel 3 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH3EN_SHIFT)) & LPCMP_RRCR1_RR_CH3EN_MASK) + +#define LPCMP_RRCR1_RR_CH4EN_MASK (0x10U) +#define LPCMP_RRCR1_RR_CH4EN_SHIFT (4U) +/*! RR_CH4EN - Channel 4 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH4EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH4EN_SHIFT)) & LPCMP_RRCR1_RR_CH4EN_MASK) + +#define LPCMP_RRCR1_RR_CH5EN_MASK (0x20U) +#define LPCMP_RRCR1_RR_CH5EN_SHIFT (5U) +/*! RR_CH5EN - Channel 5 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH5EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH5EN_SHIFT)) & LPCMP_RRCR1_RR_CH5EN_MASK) + +#define LPCMP_RRCR1_RR_CH6EN_MASK (0x40U) +#define LPCMP_RRCR1_RR_CH6EN_SHIFT (6U) +/*! RR_CH6EN - Channel 6 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH6EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH6EN_SHIFT)) & LPCMP_RRCR1_RR_CH6EN_MASK) + +#define LPCMP_RRCR1_RR_CH7EN_MASK (0x80U) +#define LPCMP_RRCR1_RR_CH7EN_SHIFT (7U) +/*! RR_CH7EN - Channel 7 Input Enable in Trigger Mode + * 0b1..Enable + * 0b0..Disable + */ +#define LPCMP_RRCR1_RR_CH7EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH7EN_SHIFT)) & LPCMP_RRCR1_RR_CH7EN_MASK) + +#define LPCMP_RRCR1_FIXP_MASK (0x10000U) +#define LPCMP_RRCR1_FIXP_SHIFT (16U) +/*! FIXP - Fixed Port + * 0b0..Fix the plus port. Sweep only the inputs to the minus port. + * 0b1..Fix the minus port. Sweep only the inputs to the plus port. + */ +#define LPCMP_RRCR1_FIXP(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_FIXP_SHIFT)) & LPCMP_RRCR1_FIXP_MASK) + +#define LPCMP_RRCR1_FIXCH_MASK (0x700000U) +#define LPCMP_RRCR1_FIXCH_SHIFT (20U) +/*! FIXCH - Fixed Channel Select + * 0b000..Channel 0 + * 0b001..Channel 1 + * 0b010..Channel 2 + * 0b011..Channel 3 + * 0b100..Channel 4 + * 0b101..Channel 5 + * 0b110..Channel 6 + * 0b111..Channel 7 + */ +#define LPCMP_RRCR1_FIXCH(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_FIXCH_SHIFT)) & LPCMP_RRCR1_FIXCH_MASK) +/*! @} */ + +/*! @name RRCSR - Round Robin Control and Status */ +/*! @{ */ + +#define LPCMP_RRCSR_RR_CH0OUT_MASK (0x1U) +#define LPCMP_RRCSR_RR_CH0OUT_SHIFT (0U) +/*! RR_CH0OUT - Comparison Result for Channel 0 */ +#define LPCMP_RRCSR_RR_CH0OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH0OUT_SHIFT)) & LPCMP_RRCSR_RR_CH0OUT_MASK) + +#define LPCMP_RRCSR_RR_CH1OUT_MASK (0x2U) +#define LPCMP_RRCSR_RR_CH1OUT_SHIFT (1U) +/*! RR_CH1OUT - Comparison Result for Channel 1 */ +#define LPCMP_RRCSR_RR_CH1OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH1OUT_SHIFT)) & LPCMP_RRCSR_RR_CH1OUT_MASK) + +#define LPCMP_RRCSR_RR_CH2OUT_MASK (0x4U) +#define LPCMP_RRCSR_RR_CH2OUT_SHIFT (2U) +/*! RR_CH2OUT - Comparison Result for Channel 2 */ +#define LPCMP_RRCSR_RR_CH2OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH2OUT_SHIFT)) & LPCMP_RRCSR_RR_CH2OUT_MASK) + +#define LPCMP_RRCSR_RR_CH3OUT_MASK (0x8U) +#define LPCMP_RRCSR_RR_CH3OUT_SHIFT (3U) +/*! RR_CH3OUT - Comparison Result for Channel 3 */ +#define LPCMP_RRCSR_RR_CH3OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH3OUT_SHIFT)) & LPCMP_RRCSR_RR_CH3OUT_MASK) + +#define LPCMP_RRCSR_RR_CH4OUT_MASK (0x10U) +#define LPCMP_RRCSR_RR_CH4OUT_SHIFT (4U) +/*! RR_CH4OUT - Comparison Result for Channel 4 */ +#define LPCMP_RRCSR_RR_CH4OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH4OUT_SHIFT)) & LPCMP_RRCSR_RR_CH4OUT_MASK) + +#define LPCMP_RRCSR_RR_CH5OUT_MASK (0x20U) +#define LPCMP_RRCSR_RR_CH5OUT_SHIFT (5U) +/*! RR_CH5OUT - Comparison Result for Channel 5 */ +#define LPCMP_RRCSR_RR_CH5OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH5OUT_SHIFT)) & LPCMP_RRCSR_RR_CH5OUT_MASK) + +#define LPCMP_RRCSR_RR_CH6OUT_MASK (0x40U) +#define LPCMP_RRCSR_RR_CH6OUT_SHIFT (6U) +/*! RR_CH6OUT - Comparison Result for Channel 6 */ +#define LPCMP_RRCSR_RR_CH6OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH6OUT_SHIFT)) & LPCMP_RRCSR_RR_CH6OUT_MASK) + +#define LPCMP_RRCSR_RR_CH7OUT_MASK (0x80U) +#define LPCMP_RRCSR_RR_CH7OUT_SHIFT (7U) +/*! RR_CH7OUT - Comparison Result for Channel 7 */ +#define LPCMP_RRCSR_RR_CH7OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH7OUT_SHIFT)) & LPCMP_RRCSR_RR_CH7OUT_MASK) +/*! @} */ + +/*! @name RRSR - Round Robin Status */ +/*! @{ */ + +#define LPCMP_RRSR_RR_CH0F_MASK (0x1U) +#define LPCMP_RRSR_RR_CH0F_SHIFT (0U) +/*! RR_CH0F - Channel 0 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH0F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH0F_SHIFT)) & LPCMP_RRSR_RR_CH0F_MASK) + +#define LPCMP_RRSR_RR_CH1F_MASK (0x2U) +#define LPCMP_RRSR_RR_CH1F_SHIFT (1U) +/*! RR_CH1F - Channel 1 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH1F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH1F_SHIFT)) & LPCMP_RRSR_RR_CH1F_MASK) + +#define LPCMP_RRSR_RR_CH2F_MASK (0x4U) +#define LPCMP_RRSR_RR_CH2F_SHIFT (2U) +/*! RR_CH2F - Channel 2 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH2F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH2F_SHIFT)) & LPCMP_RRSR_RR_CH2F_MASK) + +#define LPCMP_RRSR_RR_CH3F_MASK (0x8U) +#define LPCMP_RRSR_RR_CH3F_SHIFT (3U) +/*! RR_CH3F - Channel 3 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH3F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH3F_SHIFT)) & LPCMP_RRSR_RR_CH3F_MASK) + +#define LPCMP_RRSR_RR_CH4F_MASK (0x10U) +#define LPCMP_RRSR_RR_CH4F_SHIFT (4U) +/*! RR_CH4F - Channel 4 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH4F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH4F_SHIFT)) & LPCMP_RRSR_RR_CH4F_MASK) + +#define LPCMP_RRSR_RR_CH5F_MASK (0x20U) +#define LPCMP_RRSR_RR_CH5F_SHIFT (5U) +/*! RR_CH5F - Channel 5 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH5F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH5F_SHIFT)) & LPCMP_RRSR_RR_CH5F_MASK) + +#define LPCMP_RRSR_RR_CH6F_MASK (0x40U) +#define LPCMP_RRSR_RR_CH6F_SHIFT (6U) +/*! RR_CH6F - Channel 6 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH6F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH6F_SHIFT)) & LPCMP_RRSR_RR_CH6F_MASK) + +#define LPCMP_RRSR_RR_CH7F_MASK (0x80U) +#define LPCMP_RRSR_RR_CH7F_SHIFT (7U) +/*! RR_CH7F - Channel 7 Input Changed Flag + * 0b0..No different + * 0b1..Different + */ +#define LPCMP_RRSR_RR_CH7F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH7F_SHIFT)) & LPCMP_RRSR_RR_CH7F_MASK) +/*! @} */ + +/*! @name RRCR2 - Round Robin Control Register 2 */ +/*! @{ */ + +#define LPCMP_RRCR2_RR_TIMER_RELOAD_MASK (0xFFFFFFFU) +#define LPCMP_RRCR2_RR_TIMER_RELOAD_SHIFT (0U) +/*! RR_TIMER_RELOAD - Number of Sample Clocks */ +#define LPCMP_RRCR2_RR_TIMER_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR2_RR_TIMER_RELOAD_SHIFT)) & LPCMP_RRCR2_RR_TIMER_RELOAD_MASK) + +#define LPCMP_RRCR2_RR_TIMER_EN_MASK (0x80000000U) +#define LPCMP_RRCR2_RR_TIMER_EN_SHIFT (31U) +/*! RR_TIMER_EN - Round-Robin Internal Timer Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPCMP_RRCR2_RR_TIMER_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR2_RR_TIMER_EN_SHIFT)) & LPCMP_RRCR2_RR_TIMER_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPCMP_Register_Masks */ + + +/* LPCMP - Peripheral instance base addresses */ +/** Peripheral CMP0 base address */ +#define CMP0_BASE (0x400B1000u) +/** Peripheral CMP0 base pointer */ +#define CMP0 ((LPCMP_Type *)CMP0_BASE) +/** Peripheral CMP1 base address */ +#define CMP1_BASE (0x400B2000u) +/** Peripheral CMP1 base pointer */ +#define CMP1 ((LPCMP_Type *)CMP1_BASE) +/** Array initializer of LPCMP peripheral base addresses */ +#define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } +/** Array initializer of LPCMP peripheral base pointers */ +#define LPCMP_BASE_PTRS { CMP0, CMP1 } + +/*! + * @} + */ /* end of group LPCMP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPDAC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPDAC_Peripheral_Access_Layer LPDAC Peripheral Access Layer + * @{ + */ + +/** LPDAC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version Identifier, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __O uint32_t DATA; /**< Data, offset: 0x8 */ + __IO uint32_t GCR; /**< Global Control, offset: 0xC */ + __IO uint32_t FCR; /**< DAC FIFO Control, offset: 0x10 */ + __I uint32_t FPR; /**< DAC FIFO Pointer, offset: 0x14 */ + __IO uint32_t FSR; /**< FIFO Status, offset: 0x18 */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x1C */ + __IO uint32_t DER; /**< DMA Enable, offset: 0x20 */ + __IO uint32_t RCR; /**< Reset Control, offset: 0x24 */ + __O uint32_t TCR; /**< Trigger Control, offset: 0x28 */ + __IO uint32_t PCR; /**< Periodic Trigger Control, offset: 0x2C */ +} LPDAC_Type; + +/* ---------------------------------------------------------------------------- + -- LPDAC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPDAC_Register_Masks LPDAC Register Masks + * @{ + */ + +/*! @name VERID - Version Identifier */ +/*! @{ */ + +#define LPDAC_VERID_FEATURE_MASK (0xFFFFU) +#define LPDAC_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Identification Number */ +#define LPDAC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_FEATURE_SHIFT)) & LPDAC_VERID_FEATURE_MASK) + +#define LPDAC_VERID_MINOR_MASK (0xFF0000U) +#define LPDAC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPDAC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_MINOR_SHIFT)) & LPDAC_VERID_MINOR_MASK) + +#define LPDAC_VERID_MAJOR_MASK (0xFF000000U) +#define LPDAC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPDAC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_VERID_MAJOR_SHIFT)) & LPDAC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPDAC_PARAM_FIFOSZ_MASK (0x7U) +#define LPDAC_PARAM_FIFOSZ_SHIFT (0U) +/*! FIFOSZ - FIFO Size + * 0b000..Reserved + * 0b001..FIFO depth is 4 + * 0b010..FIFO depth is 8 + * 0b011..FIFO depth is 16 + * 0b100..FIFO depth is 32 + * 0b101..FIFO depth is 64 + * 0b110..FIFO depth is 128 + * 0b111..FIFO depth is 256 + */ +#define LPDAC_PARAM_FIFOSZ(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_PARAM_FIFOSZ_SHIFT)) & LPDAC_PARAM_FIFOSZ_MASK) +/*! @} */ + +/*! @name DATA - Data */ +/*! @{ */ + +#define LPDAC_DATA_DATA_MASK (0xFFFU) +#define LPDAC_DATA_DATA_SHIFT (0U) +/*! DATA - FIFO Entry or Buffer Entry */ +#define LPDAC_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_DATA_DATA_SHIFT)) & LPDAC_DATA_DATA_MASK) +/*! @} */ + +/*! @name GCR - Global Control */ +/*! @{ */ + +#define LPDAC_GCR_DACEN_MASK (0x1U) +#define LPDAC_GCR_DACEN_SHIFT (0U) +/*! DACEN - DAC Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPDAC_GCR_DACEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_DACEN_SHIFT)) & LPDAC_GCR_DACEN_MASK) + +#define LPDAC_GCR_DACRFS_MASK (0x6U) +#define LPDAC_GCR_DACRFS_SHIFT (1U) +/*! DACRFS - DAC Reference Select + * 0b00..Selects VREFH0 as the reference voltage. + * 0b01..Selects VREFH1 as the reference voltage. + * 0b10..Selects VREFH2 as the reference voltage. + * 0b11..Reserved. + */ +#define LPDAC_GCR_DACRFS(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_DACRFS_SHIFT)) & LPDAC_GCR_DACRFS_MASK) + +#define LPDAC_GCR_FIFOEN_MASK (0x8U) +#define LPDAC_GCR_FIFOEN_SHIFT (3U) +/*! FIFOEN - FIFO Enable + * 0b0..Enables FIFO mode and disables Buffer mode. Any data written to DATA[DATA] goes to buffer then goes to conversion. + * 0b1..Enables FIFO mode. Data will be first read from FIFO to buffer and then goes to conversion. + */ +#define LPDAC_GCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_FIFOEN_SHIFT)) & LPDAC_GCR_FIFOEN_MASK) + +#define LPDAC_GCR_SWMD_MASK (0x10U) +#define LPDAC_GCR_SWMD_SHIFT (4U) +/*! SWMD - Swing Back Mode + * 0b0..Disables + * 0b1..Enables + */ +#define LPDAC_GCR_SWMD(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_SWMD_SHIFT)) & LPDAC_GCR_SWMD_MASK) + +#define LPDAC_GCR_TRGSEL_MASK (0x20U) +#define LPDAC_GCR_TRGSEL_SHIFT (5U) +/*! TRGSEL - DAC Trigger Select + * 0b0..Hardware trigger + * 0b1..Software trigger + */ +#define LPDAC_GCR_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_TRGSEL_SHIFT)) & LPDAC_GCR_TRGSEL_MASK) + +#define LPDAC_GCR_PTGEN_MASK (0x40U) +#define LPDAC_GCR_PTGEN_SHIFT (6U) +/*! PTGEN - DAC Periodic Trigger Mode Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPDAC_GCR_PTGEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_PTGEN_SHIFT)) & LPDAC_GCR_PTGEN_MASK) + +#define LPDAC_GCR_LATCH_CYC_MASK (0xF00U) +#define LPDAC_GCR_LATCH_CYC_SHIFT (8U) +/*! LATCH_CYC - RCLK Cycles Before Data Latch */ +#define LPDAC_GCR_LATCH_CYC(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_LATCH_CYC_SHIFT)) & LPDAC_GCR_LATCH_CYC_MASK) + +#define LPDAC_GCR_BUF_EN_MASK (0x20000U) +#define LPDAC_GCR_BUF_EN_SHIFT (17U) +/*! BUF_EN - Buffer Enable + * 0b0..Not used + * 0b1..Used + */ +#define LPDAC_GCR_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_BUF_EN_SHIFT)) & LPDAC_GCR_BUF_EN_MASK) + +#define LPDAC_GCR_IREF_PTAT_EXT_SEL_MASK (0x100000U) +#define LPDAC_GCR_IREF_PTAT_EXT_SEL_SHIFT (20U) +/*! IREF_PTAT_EXT_SEL - External On-Chip PTAT Current Reference Select + * 0b0..Not selected + * 0b1..Selected + */ +#define LPDAC_GCR_IREF_PTAT_EXT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_IREF_PTAT_EXT_SEL_SHIFT)) & LPDAC_GCR_IREF_PTAT_EXT_SEL_MASK) + +#define LPDAC_GCR_IREF_ZTC_EXT_SEL_MASK (0x200000U) +#define LPDAC_GCR_IREF_ZTC_EXT_SEL_SHIFT (21U) +/*! IREF_ZTC_EXT_SEL - External On-Chip ZTC Current Reference Select + * 0b0..Not selected + * 0b1..Selected + */ +#define LPDAC_GCR_IREF_ZTC_EXT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_IREF_ZTC_EXT_SEL_SHIFT)) & LPDAC_GCR_IREF_ZTC_EXT_SEL_MASK) + +#define LPDAC_GCR_BUF_SPD_CTRL_MASK (0x800000U) +#define LPDAC_GCR_BUF_SPD_CTRL_SHIFT (23U) +/*! BUF_SPD_CTRL - OPAMP as Buffer, Speed Control Signal + * 0b0..Lower Low-Power mode + * 0b1..Low-Power mode + */ +#define LPDAC_GCR_BUF_SPD_CTRL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_GCR_BUF_SPD_CTRL_SHIFT)) & LPDAC_GCR_BUF_SPD_CTRL_MASK) +/*! @} */ + +/*! @name FCR - DAC FIFO Control */ +/*! @{ */ + +#define LPDAC_FCR_WML_MASK (0xFU) +#define LPDAC_FCR_WML_SHIFT (0U) +/*! WML - Watermark Level */ +#define LPDAC_FCR_WML(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FCR_WML_SHIFT)) & LPDAC_FCR_WML_MASK) +/*! @} */ + +/*! @name FPR - DAC FIFO Pointer */ +/*! @{ */ + +#define LPDAC_FPR_FIFO_RPT_MASK (0xFU) +#define LPDAC_FPR_FIFO_RPT_SHIFT (0U) +/*! FIFO_RPT - FIFO Read Pointer */ +#define LPDAC_FPR_FIFO_RPT(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FPR_FIFO_RPT_SHIFT)) & LPDAC_FPR_FIFO_RPT_MASK) + +#define LPDAC_FPR_FIFO_WPT_MASK (0xF0000U) +#define LPDAC_FPR_FIFO_WPT_SHIFT (16U) +/*! FIFO_WPT - FIFO Write Pointer */ +#define LPDAC_FPR_FIFO_WPT(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FPR_FIFO_WPT_SHIFT)) & LPDAC_FPR_FIFO_WPT_MASK) +/*! @} */ + +/*! @name FSR - FIFO Status */ +/*! @{ */ + +#define LPDAC_FSR_FULL_MASK (0x1U) +#define LPDAC_FSR_FULL_SHIFT (0U) +/*! FULL - FIFO Full Flag + * 0b0..Not full + * 0b1..Full + */ +#define LPDAC_FSR_FULL(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_FULL_SHIFT)) & LPDAC_FSR_FULL_MASK) + +#define LPDAC_FSR_EMPTY_MASK (0x2U) +#define LPDAC_FSR_EMPTY_SHIFT (1U) +/*! EMPTY - FIFO Empty Flag + * 0b0..Not empty + * 0b1..Empty + */ +#define LPDAC_FSR_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_EMPTY_SHIFT)) & LPDAC_FSR_EMPTY_MASK) + +#define LPDAC_FSR_WM_MASK (0x4U) +#define LPDAC_FSR_WM_SHIFT (2U) +/*! WM - FIFO Watermark Status Flag + * 0b0..Data in FIFO is more than watermark level + * 0b1..Data in FIFO is less than or equal to watermark level + */ +#define LPDAC_FSR_WM(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_WM_SHIFT)) & LPDAC_FSR_WM_MASK) + +#define LPDAC_FSR_SWBK_MASK (0x8U) +#define LPDAC_FSR_SWBK_SHIFT (3U) +/*! SWBK - Swing Back One Cycle Complete Flag + * 0b0..No swing back cycle has completed since the last time the flag was cleared + * 0b1..At least one swing back cycle has occurred since the last time the flag was cleared + */ +#define LPDAC_FSR_SWBK(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_SWBK_SHIFT)) & LPDAC_FSR_SWBK_MASK) + +#define LPDAC_FSR_OF_MASK (0x40U) +#define LPDAC_FSR_OF_SHIFT (6U) +/*! OF - FIFO Overflow Flag + * 0b0..No overflow has occurred since the last time the flag was cleared + * 0b1..At least one FIFO overflow has occurred since the last time the flag was cleared + */ +#define LPDAC_FSR_OF(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_OF_SHIFT)) & LPDAC_FSR_OF_MASK) + +#define LPDAC_FSR_UF_MASK (0x80U) +#define LPDAC_FSR_UF_SHIFT (7U) +/*! UF - FIFO Underflow Flag + * 0b0..No underflow has occurred since the last time the flag was cleared + * 0b1..At least one trigger underflow has occurred since the last time the flag was cleared + */ +#define LPDAC_FSR_UF(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_UF_SHIFT)) & LPDAC_FSR_UF_MASK) + +#define LPDAC_FSR_PTGCOCO_MASK (0x100U) +#define LPDAC_FSR_PTGCOCO_SHIFT (8U) +/*! PTGCOCO - Period Trigger Mode Conversion Complete Flag + * 0b0..Not completed or not started + * 0b1..Completed + */ +#define LPDAC_FSR_PTGCOCO(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_FSR_PTGCOCO_SHIFT)) & LPDAC_FSR_PTGCOCO_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define LPDAC_IER_FULL_IE_MASK (0x1U) +#define LPDAC_IER_FULL_IE_SHIFT (0U) +/*! FULL_IE - FIFO Full Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPDAC_IER_FULL_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_FULL_IE_SHIFT)) & LPDAC_IER_FULL_IE_MASK) + +#define LPDAC_IER_EMPTY_IE_MASK (0x2U) +#define LPDAC_IER_EMPTY_IE_SHIFT (1U) +/*! EMPTY_IE - FIFO Empty Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPDAC_IER_EMPTY_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_EMPTY_IE_SHIFT)) & LPDAC_IER_EMPTY_IE_MASK) + +#define LPDAC_IER_WM_IE_MASK (0x4U) +#define LPDAC_IER_WM_IE_SHIFT (2U) +/*! WM_IE - FIFO Watermark Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPDAC_IER_WM_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_WM_IE_SHIFT)) & LPDAC_IER_WM_IE_MASK) + +#define LPDAC_IER_SWBK_IE_MASK (0x8U) +#define LPDAC_IER_SWBK_IE_SHIFT (3U) +/*! SWBK_IE - Swing Back One Cycle Complete Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPDAC_IER_SWBK_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_SWBK_IE_SHIFT)) & LPDAC_IER_SWBK_IE_MASK) + +#define LPDAC_IER_OF_IE_MASK (0x40U) +#define LPDAC_IER_OF_IE_SHIFT (6U) +/*! OF_IE - FIFO Overflow Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPDAC_IER_OF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_OF_IE_SHIFT)) & LPDAC_IER_OF_IE_MASK) + +#define LPDAC_IER_UF_IE_MASK (0x80U) +#define LPDAC_IER_UF_IE_SHIFT (7U) +/*! UF_IE - FIFO Underflow Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPDAC_IER_UF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_UF_IE_SHIFT)) & LPDAC_IER_UF_IE_MASK) + +#define LPDAC_IER_PTGCOCO_IE_MASK (0x100U) +#define LPDAC_IER_PTGCOCO_IE_SHIFT (8U) +/*! PTGCOCO_IE - PTG Mode Conversion Complete Interrupt Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPDAC_IER_PTGCOCO_IE(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_IER_PTGCOCO_IE_SHIFT)) & LPDAC_IER_PTGCOCO_IE_MASK) +/*! @} */ + +/*! @name DER - DMA Enable */ +/*! @{ */ + +#define LPDAC_DER_EMPTY_DMAEN_MASK (0x2U) +#define LPDAC_DER_EMPTY_DMAEN_SHIFT (1U) +/*! EMPTY_DMAEN - FIFO Empty DMA Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPDAC_DER_EMPTY_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_DER_EMPTY_DMAEN_SHIFT)) & LPDAC_DER_EMPTY_DMAEN_MASK) + +#define LPDAC_DER_WM_DMAEN_MASK (0x4U) +#define LPDAC_DER_WM_DMAEN_SHIFT (2U) +/*! WM_DMAEN - FIFO Watermark DMA Enable + * 0b0..Disables + * 0b1..Enables + */ +#define LPDAC_DER_WM_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_DER_WM_DMAEN_SHIFT)) & LPDAC_DER_WM_DMAEN_MASK) +/*! @} */ + +/*! @name RCR - Reset Control */ +/*! @{ */ + +#define LPDAC_RCR_SWRST_MASK (0x1U) +#define LPDAC_RCR_SWRST_SHIFT (0U) +/*! SWRST - Software Reset + * 0b0..No effect + * 0b1..Software reset + */ +#define LPDAC_RCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_RCR_SWRST_SHIFT)) & LPDAC_RCR_SWRST_MASK) + +#define LPDAC_RCR_FIFORST_MASK (0x2U) +#define LPDAC_RCR_FIFORST_SHIFT (1U) +/*! FIFORST - FIFO Reset + * 0b0..No effect + * 0b1..FIFO reset + */ +#define LPDAC_RCR_FIFORST(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_RCR_FIFORST_SHIFT)) & LPDAC_RCR_FIFORST_MASK) +/*! @} */ + +/*! @name TCR - Trigger Control */ +/*! @{ */ + +#define LPDAC_TCR_SWTRG_MASK (0x1U) +#define LPDAC_TCR_SWTRG_SHIFT (0U) +/*! SWTRG - Software Trigger + * 0b0..Not valid + * 0b1..Valid + */ +#define LPDAC_TCR_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_TCR_SWTRG_SHIFT)) & LPDAC_TCR_SWTRG_MASK) +/*! @} */ + +/*! @name PCR - Periodic Trigger Control */ +/*! @{ */ + +#define LPDAC_PCR_PTG_NUM_MASK (0xFFFFU) +#define LPDAC_PCR_PTG_NUM_SHIFT (0U) +/*! PTG_NUM - Periodic Trigger Number */ +#define LPDAC_PCR_PTG_NUM(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_PCR_PTG_NUM_SHIFT)) & LPDAC_PCR_PTG_NUM_MASK) + +#define LPDAC_PCR_PTG_PERIOD_MASK (0xFFFF0000U) +#define LPDAC_PCR_PTG_PERIOD_SHIFT (16U) +/*! PTG_PERIOD - Periodic Trigger Period Width */ +#define LPDAC_PCR_PTG_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LPDAC_PCR_PTG_PERIOD_SHIFT)) & LPDAC_PCR_PTG_PERIOD_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPDAC_Register_Masks */ + + +/* LPDAC - Peripheral instance base addresses */ +/** Peripheral DAC0 base address */ +#define DAC0_BASE (0x400B4000u) +/** Peripheral DAC0 base pointer */ +#define DAC0 ((LPDAC_Type *)DAC0_BASE) +/** Array initializer of LPDAC peripheral base addresses */ +#define LPDAC_BASE_ADDRS { DAC0_BASE } +/** Array initializer of LPDAC peripheral base pointers */ +#define LPDAC_BASE_PTRS { DAC0 } +/** Interrupt vectors for the LPDAC peripheral type */ +#define LPDAC_IRQS { DAC0_IRQn } + +/*! + * @} + */ /* end of group LPDAC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPI2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer + * @{ + */ + +/** LPI2C - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t MCR; /**< Controller Control, offset: 0x10 */ + __IO uint32_t MSR; /**< Controller Status, offset: 0x14 */ + __IO uint32_t MIER; /**< Controller Interrupt Enable, offset: 0x18 */ + __IO uint32_t MDER; /**< Controller DMA Enable, offset: 0x1C */ + __IO uint32_t MCFGR0; /**< Controller Configuration 0, offset: 0x20 */ + __IO uint32_t MCFGR1; /**< Controller Configuration 1, offset: 0x24 */ + __IO uint32_t MCFGR2; /**< Controller Configuration 2, offset: 0x28 */ + __IO uint32_t MCFGR3; /**< Controller Configuration 3, offset: 0x2C */ + uint8_t RESERVED_1[16]; + __IO uint32_t MDMR; /**< Controller Data Match, offset: 0x40 */ + uint8_t RESERVED_2[4]; + __IO uint32_t MCCR0; /**< Controller Clock Configuration 0, offset: 0x48 */ + uint8_t RESERVED_3[4]; + __IO uint32_t MCCR1; /**< Controller Clock Configuration 1, offset: 0x50 */ + uint8_t RESERVED_4[4]; + __IO uint32_t MFCR; /**< Controller FIFO Control, offset: 0x58 */ + __I uint32_t MFSR; /**< Controller FIFO Status, offset: 0x5C */ + __O uint32_t MTDR; /**< Controller Transmit Data, offset: 0x60 */ + uint8_t RESERVED_5[12]; + __I uint32_t MRDR; /**< Controller Receive Data, offset: 0x70 */ + uint8_t RESERVED_6[4]; + __I uint32_t MRDROR; /**< Controller Receive Data Read Only, offset: 0x78 */ + uint8_t RESERVED_7[148]; + __IO uint32_t SCR; /**< Target Control, offset: 0x110 */ + __IO uint32_t SSR; /**< Target Status, offset: 0x114 */ + __IO uint32_t SIER; /**< Target Interrupt Enable, offset: 0x118 */ + __IO uint32_t SDER; /**< Target DMA Enable, offset: 0x11C */ + __IO uint32_t SCFGR0; /**< Target Configuration 0, offset: 0x120 */ + __IO uint32_t SCFGR1; /**< Target Configuration 1, offset: 0x124 */ + __IO uint32_t SCFGR2; /**< Target Configuration 2, offset: 0x128 */ + uint8_t RESERVED_8[20]; + __IO uint32_t SAMR; /**< Target Address Match, offset: 0x140 */ + uint8_t RESERVED_9[12]; + __I uint32_t SASR; /**< Target Address Status, offset: 0x150 */ + __IO uint32_t STAR; /**< Target Transmit ACK, offset: 0x154 */ + uint8_t RESERVED_10[8]; + __O uint32_t STDR; /**< Target Transmit Data, offset: 0x160 */ + uint8_t RESERVED_11[12]; + __I uint32_t SRDR; /**< Target Receive Data, offset: 0x170 */ + uint8_t RESERVED_12[4]; + __I uint32_t SRDROR; /**< Target Receive Data Read Only, offset: 0x178 */ +} LPI2C_Type; + +/* ---------------------------------------------------------------------------- + -- LPI2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPI2C_Register_Masks LPI2C Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPI2C_VERID_FEATURE_MASK (0xFFFFU) +#define LPI2C_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000010..Controller only, with standard feature set + * 0b0000000000000011..Controller and target, with standard feature set + */ +#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) + +#define LPI2C_VERID_MINOR_MASK (0xFF0000U) +#define LPI2C_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) + +#define LPI2C_VERID_MAJOR_MASK (0xFF000000U) +#define LPI2C_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPI2C_PARAM_MTXFIFO_MASK (0xFU) +#define LPI2C_PARAM_MTXFIFO_SHIFT (0U) +/*! MTXFIFO - Controller Transmit FIFO Size */ +#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) + +#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) +#define LPI2C_PARAM_MRXFIFO_SHIFT (8U) +/*! MRXFIFO - Controller Receive FIFO Size */ +#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) +/*! @} */ + +/*! @name MCR - Controller Control */ +/*! @{ */ + +#define LPI2C_MCR_MEN_MASK (0x1U) +#define LPI2C_MCR_MEN_SHIFT (0U) +/*! MEN - Controller Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) + +#define LPI2C_MCR_RST_MASK (0x2U) +#define LPI2C_MCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..No effect + * 0b1..Reset + */ +#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) + +#define LPI2C_MCR_DOZEN_MASK (0x4U) +#define LPI2C_MCR_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Mode Enable + * 0b0..Enable + * 0b1..Disable + */ +#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) + +#define LPI2C_MCR_DBGEN_MASK (0x8U) +#define LPI2C_MCR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) + +#define LPI2C_MCR_RTF_MASK (0x100U) +#define LPI2C_MCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Reset transmit FIFO + */ +#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) + +#define LPI2C_MCR_RRF_MASK (0x200U) +#define LPI2C_MCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Reset receive FIFO + */ +#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) +/*! @} */ + +/*! @name MSR - Controller Status */ +/*! @{ */ + +#define LPI2C_MSR_TDF_MASK (0x1U) +#define LPI2C_MSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data requested + */ +#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) + +#define LPI2C_MSR_RDF_MASK (0x2U) +#define LPI2C_MSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive data not ready + * 0b1..Receive data ready + */ +#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) + +#define LPI2C_MSR_EPF_MASK (0x100U) +#define LPI2C_MSR_EPF_SHIFT (8U) +/*! EPF - End Packet Flag + * 0b0..No Stop or repeated Start generated + * 0b1..Stop or repeated Start generated + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) + +#define LPI2C_MSR_SDF_MASK (0x200U) +#define LPI2C_MSR_SDF_SHIFT (9U) +/*! SDF - Stop Detect Flag + * 0b0..No Stop condition generated + * 0b1..Stop condition generated + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) + +#define LPI2C_MSR_NDF_MASK (0x400U) +#define LPI2C_MSR_NDF_SHIFT (10U) +/*! NDF - NACK Detect Flag + * 0b0..No unexpected NACK detected + * 0b1..Unexpected NACK detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) + +#define LPI2C_MSR_ALF_MASK (0x800U) +#define LPI2C_MSR_ALF_SHIFT (11U) +/*! ALF - Arbitration Lost Flag + * 0b0..Controller did not lose arbitration + * 0b1..Controller lost arbitration + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) + +#define LPI2C_MSR_FEF_MASK (0x1000U) +#define LPI2C_MSR_FEF_SHIFT (12U) +/*! FEF - FIFO Error Flag + * 0b0..No FIFO error + * 0b1..FIFO error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) + +#define LPI2C_MSR_PLTF_MASK (0x2000U) +#define LPI2C_MSR_PLTF_SHIFT (13U) +/*! PLTF - Pin Low Timeout Flag + * 0b0..Pin low timeout did not occur + * 0b1..Pin low timeout occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) + +#define LPI2C_MSR_DMF_MASK (0x4000U) +#define LPI2C_MSR_DMF_SHIFT (14U) +/*! DMF - Data Match Flag + * 0b0..Matching data not received + * 0b1..Matching data received + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) + +#define LPI2C_MSR_STF_MASK (0x8000U) +#define LPI2C_MSR_STF_SHIFT (15U) +/*! STF - Start Flag + * 0b0..Start condition not detected + * 0b1..Start condition detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_MSR_STF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_STF_SHIFT)) & LPI2C_MSR_STF_MASK) + +#define LPI2C_MSR_MBF_MASK (0x1000000U) +#define LPI2C_MSR_MBF_SHIFT (24U) +/*! MBF - Controller Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) + +#define LPI2C_MSR_BBF_MASK (0x2000000U) +#define LPI2C_MSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) +/*! @} */ + +/*! @name MIER - Controller Interrupt Enable */ +/*! @{ */ + +#define LPI2C_MIER_TDIE_MASK (0x1U) +#define LPI2C_MIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) + +#define LPI2C_MIER_RDIE_MASK (0x2U) +#define LPI2C_MIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) + +#define LPI2C_MIER_EPIE_MASK (0x100U) +#define LPI2C_MIER_EPIE_SHIFT (8U) +/*! EPIE - End Packet Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) + +#define LPI2C_MIER_SDIE_MASK (0x200U) +#define LPI2C_MIER_SDIE_SHIFT (9U) +/*! SDIE - Stop Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) + +#define LPI2C_MIER_NDIE_MASK (0x400U) +#define LPI2C_MIER_NDIE_SHIFT (10U) +/*! NDIE - NACK Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) + +#define LPI2C_MIER_ALIE_MASK (0x800U) +#define LPI2C_MIER_ALIE_SHIFT (11U) +/*! ALIE - Arbitration Lost Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) + +#define LPI2C_MIER_FEIE_MASK (0x1000U) +#define LPI2C_MIER_FEIE_SHIFT (12U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) + +#define LPI2C_MIER_PLTIE_MASK (0x2000U) +#define LPI2C_MIER_PLTIE_SHIFT (13U) +/*! PLTIE - Pin Low Timeout Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) + +#define LPI2C_MIER_DMIE_MASK (0x4000U) +#define LPI2C_MIER_DMIE_SHIFT (14U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) + +#define LPI2C_MIER_STIE_MASK (0x8000U) +#define LPI2C_MIER_STIE_SHIFT (15U) +/*! STIE - Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MIER_STIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_STIE_SHIFT)) & LPI2C_MIER_STIE_MASK) +/*! @} */ + +/*! @name MDER - Controller DMA Enable */ +/*! @{ */ + +#define LPI2C_MDER_TDDE_MASK (0x1U) +#define LPI2C_MDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) + +#define LPI2C_MDER_RDDE_MASK (0x2U) +#define LPI2C_MDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) +/*! @} */ + +/*! @name MCFGR0 - Controller Configuration 0 */ +/*! @{ */ + +#define LPI2C_MCFGR0_HREN_MASK (0x1U) +#define LPI2C_MCFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) + +#define LPI2C_MCFGR0_HRPOL_MASK (0x2U) +#define LPI2C_MCFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active low + * 0b1..Active high + */ +#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) + +#define LPI2C_MCFGR0_HRSEL_MASK (0x4U) +#define LPI2C_MCFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..Host request input is pin HREQ + * 0b1..Host request input is input trigger + */ +#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) + +#define LPI2C_MCFGR0_HRDIR_MASK (0x8U) +#define LPI2C_MCFGR0_HRDIR_SHIFT (3U) +/*! HRDIR - Host Request Direction + * 0b0..HREQ pin is input (for LPI2C controller) + * 0b1..HREQ pin is output (for LPI2C target) + */ +#define LPI2C_MCFGR0_HRDIR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRDIR_SHIFT)) & LPI2C_MCFGR0_HRDIR_MASK) + +#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) +#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) + +#define LPI2C_MCFGR0_RDMO_MASK (0x200U) +#define LPI2C_MCFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Received data is stored in the receive FIFO + * 0b1..Received data is discarded unless MSR[DMF] is set + */ +#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) + +#define LPI2C_MCFGR0_RELAX_MASK (0x10000U) +#define LPI2C_MCFGR0_RELAX_SHIFT (16U) +/*! RELAX - Relaxed Mode + * 0b0..Normal transfer + * 0b1..Relaxed transfer + */ +#define LPI2C_MCFGR0_RELAX(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RELAX_SHIFT)) & LPI2C_MCFGR0_RELAX_MASK) + +#define LPI2C_MCFGR0_ABORT_MASK (0x20000U) +#define LPI2C_MCFGR0_ABORT_SHIFT (17U) +/*! ABORT - Abort Transfer + * 0b0..Normal transfer + * 0b1..Abort existing transfer and do not start a new one + */ +#define LPI2C_MCFGR0_ABORT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_ABORT_SHIFT)) & LPI2C_MCFGR0_ABORT_MASK) +/*! @} */ + +/*! @name MCFGR1 - Controller Configuration 1 */ +/*! @{ */ + +#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) +#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) +/*! PRESCALE - Prescaler + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) + +#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) +#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) +/*! AUTOSTOP - Automatic Stop Generation + * 0b0..No effect + * 0b1..Stop automatically generated + */ +#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) + +#define LPI2C_MCFGR1_IGNACK_MASK (0x200U) +#define LPI2C_MCFGR1_IGNACK_SHIFT (9U) +/*! IGNACK - Ignore NACK + * 0b0..No effect + * 0b1..Treat a received NACK as an ACK + */ +#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) + +#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) +#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) +/*! TIMECFG - Timeout Configuration + * 0b0..SCL + * 0b1..SCL or SDA + */ +#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) + +#define LPI2C_MCFGR1_STOPCFG_MASK (0x800U) +#define LPI2C_MCFGR1_STOPCFG_SHIFT (11U) +/*! STOPCFG - Stop Configuration + * 0b0..Any Stop condition + * 0b1..Last Stop condition + */ +#define LPI2C_MCFGR1_STOPCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STOPCFG_SHIFT)) & LPI2C_MCFGR1_STOPCFG_MASK) + +#define LPI2C_MCFGR1_STARTCFG_MASK (0x1000U) +#define LPI2C_MCFGR1_STARTCFG_SHIFT (12U) +/*! STARTCFG - Start Configuration + * 0b0..Sets when both I2C bus and LPI2C controller are idle + * 0b1..Sets when I2C bus is idle + */ +#define LPI2C_MCFGR1_STARTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STARTCFG_SHIFT)) & LPI2C_MCFGR1_STARTCFG_MASK) + +#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) +#define LPI2C_MCFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001..Reserved + * 0b010..Match is enabled: first data word equals MDMR[MATCH0] OR MDMR[MATCH1] + * 0b011..Match is enabled: any data word equals MDMR[MATCH0] OR MDMR[MATCH1] + * 0b100..Match is enabled: (first data word equals MDMR[MATCH0]) AND (second data word equals MDMR[MATCH1) + * 0b101..Match is enabled: (any data word equals MDMR[MATCH0]) AND (next data word equals MDMR[MATCH1) + * 0b110..Match is enabled: (first data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) + * 0b111..Match is enabled: (any data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) + */ +#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) + +#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) +#define LPI2C_MCFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b000..Two-pin open drain mode + * 0b001..Two-pin output only mode (Ultra-Fast mode) + * 0b010..Two-pin push-pull mode + * 0b011..Four-pin push-pull mode + * 0b100..Two-pin open-drain mode with separate LPI2C target + * 0b101..Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target + * 0b110..Two-pin push-pull mode with separate LPI2C target + * 0b111..Four-pin push-pull mode (inverted outputs) + */ +#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) +/*! @} */ + +/*! @name MCFGR2 - Controller Configuration 2 */ +/*! @{ */ + +#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) +#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) +/*! BUSIDLE - Bus Idle Timeout */ +#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) + +#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) +/*! FILTSCL - Glitch Filter SCL */ +#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) + +#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) +/*! FILTSDA - Glitch Filter SDA */ +#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name MCFGR3 - Controller Configuration 3 */ +/*! @{ */ + +#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) +#define LPI2C_MCFGR3_PINLOW_SHIFT (8U) +/*! PINLOW - Pin Low Timeout */ +#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) +/*! @} */ + +/*! @name MDMR - Controller Data Match */ +/*! @{ */ + +#define LPI2C_MDMR_MATCH0_MASK (0xFFU) +#define LPI2C_MDMR_MATCH0_SHIFT (0U) +/*! MATCH0 - Match 0 Value */ +#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) + +#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) +#define LPI2C_MDMR_MATCH1_SHIFT (16U) +/*! MATCH1 - Match 1 Value */ +#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) +/*! @} */ + +/*! @name MCCR0 - Controller Clock Configuration 0 */ +/*! @{ */ + +#define LPI2C_MCCR0_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR0_CLKLO_SHIFT (0U) +/*! CLKLO - Clock Low Period */ +#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) + +#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR0_CLKHI_SHIFT (8U) +/*! CLKHI - Clock High Period */ +#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) + +#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR0_SETHOLD_SHIFT (16U) +/*! SETHOLD - Setup Hold Delay */ +#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) + +#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR0_DATAVD_SHIFT (24U) +/*! DATAVD - Data Valid Delay */ +#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) +/*! @} */ + +/*! @name MCCR1 - Controller Clock Configuration 1 */ +/*! @{ */ + +#define LPI2C_MCCR1_CLKLO_MASK (0x3FU) +#define LPI2C_MCCR1_CLKLO_SHIFT (0U) +/*! CLKLO - Clock Low Period */ +#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) + +#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) +#define LPI2C_MCCR1_CLKHI_SHIFT (8U) +/*! CLKHI - Clock High Period */ +#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) + +#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) +#define LPI2C_MCCR1_SETHOLD_SHIFT (16U) +/*! SETHOLD - Setup Hold Delay */ +#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) + +#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) +#define LPI2C_MCCR1_DATAVD_SHIFT (24U) +/*! DATAVD - Data Valid Delay */ +#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) +/*! @} */ + +/*! @name MFCR - Controller FIFO Control */ +/*! @{ */ + +#define LPI2C_MFCR_TXWATER_MASK (0x3U) +#define LPI2C_MFCR_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit FIFO Watermark */ +#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) + +#define LPI2C_MFCR_RXWATER_MASK (0x30000U) +#define LPI2C_MFCR_RXWATER_SHIFT (16U) +/*! RXWATER - Receive FIFO Watermark */ +#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) +/*! @} */ + +/*! @name MFSR - Controller FIFO Status */ +/*! @{ */ + +#define LPI2C_MFSR_TXCOUNT_MASK (0x7U) +#define LPI2C_MFSR_TXCOUNT_SHIFT (0U) +/*! TXCOUNT - Transmit FIFO Count */ +#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) + +#define LPI2C_MFSR_RXCOUNT_MASK (0x70000U) +#define LPI2C_MFSR_RXCOUNT_SHIFT (16U) +/*! RXCOUNT - Receive FIFO Count */ +#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name MTDR - Controller Transmit Data */ +/*! @{ */ + +#define LPI2C_MTDR_DATA_MASK (0xFFU) +#define LPI2C_MTDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data */ +#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) + +#define LPI2C_MTDR_CMD_MASK (0x700U) +#define LPI2C_MTDR_CMD_SHIFT (8U) +/*! CMD - Command Data + * 0b000..Transmit the value in DATA[7:0] + * 0b001..Receive (DATA[7:0] + 1) bytes + * 0b010..Generate Stop condition on I2C bus + * 0b011..Receive and discard (DATA[7:0] + 1) bytes + * 0b100..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] + * 0b101..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] (this transfer expects a NACK to be returned) + * 0b110..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode + * 0b111..Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode (this transfer expects a NACK to be returned) + */ +#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) +/*! @} */ + +/*! @name MRDR - Controller Receive Data */ +/*! @{ */ + +#define LPI2C_MRDR_DATA_MASK (0xFFU) +#define LPI2C_MRDR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) + +#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_MRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) +/*! @} */ + +/*! @name MRDROR - Controller Receive Data Read Only */ +/*! @{ */ + +#define LPI2C_MRDROR_DATA_MASK (0xFFU) +#define LPI2C_MRDROR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPI2C_MRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_DATA_SHIFT)) & LPI2C_MRDROR_DATA_MASK) + +#define LPI2C_MRDROR_RXEMPTY_MASK (0x4000U) +#define LPI2C_MRDROR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - RX Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_MRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_RXEMPTY_SHIFT)) & LPI2C_MRDROR_RXEMPTY_MASK) +/*! @} */ + +/*! @name SCR - Target Control */ +/*! @{ */ + +#define LPI2C_SCR_SEN_MASK (0x1U) +#define LPI2C_SCR_SEN_SHIFT (0U) +/*! SEN - Target Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) + +#define LPI2C_SCR_RST_MASK (0x2U) +#define LPI2C_SCR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset + */ +#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) + +#define LPI2C_SCR_FILTEN_MASK (0x10U) +#define LPI2C_SCR_FILTEN_SHIFT (4U) +/*! FILTEN - Filter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) + +#define LPI2C_SCR_FILTDZ_MASK (0x20U) +#define LPI2C_SCR_FILTDZ_SHIFT (5U) +/*! FILTDZ - Filter Doze Enable + * 0b0..Enable + * 0b1..Disable + */ +#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) + +#define LPI2C_SCR_RTF_MASK (0x100U) +#define LPI2C_SCR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..STDR is now empty + */ +#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) + +#define LPI2C_SCR_RRF_MASK (0x200U) +#define LPI2C_SCR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..SRDR is now empty + */ +#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) +/*! @} */ + +/*! @name SSR - Target Status */ +/*! @{ */ + +#define LPI2C_SSR_TDF_MASK (0x1U) +#define LPI2C_SSR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data is requested + */ +#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) + +#define LPI2C_SSR_RDF_MASK (0x2U) +#define LPI2C_SSR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Not ready + * 0b1..Ready + */ +#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) + +#define LPI2C_SSR_AVF_MASK (0x4U) +#define LPI2C_SSR_AVF_SHIFT (2U) +/*! AVF - Address Valid Flag + * 0b0..Not valid + * 0b1..Valid + */ +#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) + +#define LPI2C_SSR_TAF_MASK (0x8U) +#define LPI2C_SSR_TAF_SHIFT (3U) +/*! TAF - Transmit ACK Flag + * 0b0..Not required + * 0b1..Required + */ +#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) + +#define LPI2C_SSR_RSF_MASK (0x100U) +#define LPI2C_SSR_RSF_SHIFT (8U) +/*! RSF - Repeated Start Flag + * 0b0..No repeated Start detected + * 0b1..Repeated Start detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) + +#define LPI2C_SSR_SDF_MASK (0x200U) +#define LPI2C_SSR_SDF_SHIFT (9U) +/*! SDF - Stop Detect Flag + * 0b0..No Stop detected + * 0b1..Stop detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) + +#define LPI2C_SSR_BEF_MASK (0x400U) +#define LPI2C_SSR_BEF_SHIFT (10U) +/*! BEF - Bit Error Flag + * 0b0..No bit error occurred + * 0b1..Bit error occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) + +#define LPI2C_SSR_FEF_MASK (0x800U) +#define LPI2C_SSR_FEF_SHIFT (11U) +/*! FEF - FIFO Error Flag + * 0b0..No FIFO error + * 0b1..FIFO error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) + +#define LPI2C_SSR_AM0F_MASK (0x1000U) +#define LPI2C_SSR_AM0F_SHIFT (12U) +/*! AM0F - Address Match 0 Flag + * 0b0..ADDR0 matching address not received + * 0b1..ADDR0 matching address received + */ +#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) + +#define LPI2C_SSR_AM1F_MASK (0x2000U) +#define LPI2C_SSR_AM1F_SHIFT (13U) +/*! AM1F - Address Match 1 Flag + * 0b0..Matching address not received + * 0b1..Matching address received + */ +#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) + +#define LPI2C_SSR_GCF_MASK (0x4000U) +#define LPI2C_SSR_GCF_SHIFT (14U) +/*! GCF - General Call Flag + * 0b0..General call address disabled or not detected + * 0b1..General call address detected + */ +#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) + +#define LPI2C_SSR_SARF_MASK (0x8000U) +#define LPI2C_SSR_SARF_SHIFT (15U) +/*! SARF - SMBus Alert Response Flag + * 0b0..Disabled or not detected + * 0b1..Enabled and detected + */ +#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) + +#define LPI2C_SSR_SBF_MASK (0x1000000U) +#define LPI2C_SSR_SBF_SHIFT (24U) +/*! SBF - Target Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) + +#define LPI2C_SSR_BBF_MASK (0x2000000U) +#define LPI2C_SSR_BBF_SHIFT (25U) +/*! BBF - Bus Busy Flag + * 0b0..Idle + * 0b1..Busy + */ +#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) +/*! @} */ + +/*! @name SIER - Target Interrupt Enable */ +/*! @{ */ + +#define LPI2C_SIER_TDIE_MASK (0x1U) +#define LPI2C_SIER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) + +#define LPI2C_SIER_RDIE_MASK (0x2U) +#define LPI2C_SIER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) + +#define LPI2C_SIER_AVIE_MASK (0x4U) +#define LPI2C_SIER_AVIE_SHIFT (2U) +/*! AVIE - Address Valid Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) + +#define LPI2C_SIER_TAIE_MASK (0x8U) +#define LPI2C_SIER_TAIE_SHIFT (3U) +/*! TAIE - Transmit ACK Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) + +#define LPI2C_SIER_RSIE_MASK (0x100U) +#define LPI2C_SIER_RSIE_SHIFT (8U) +/*! RSIE - Repeated Start Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) + +#define LPI2C_SIER_SDIE_MASK (0x200U) +#define LPI2C_SIER_SDIE_SHIFT (9U) +/*! SDIE - Stop Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) + +#define LPI2C_SIER_BEIE_MASK (0x400U) +#define LPI2C_SIER_BEIE_SHIFT (10U) +/*! BEIE - Bit Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) + +#define LPI2C_SIER_FEIE_MASK (0x800U) +#define LPI2C_SIER_FEIE_SHIFT (11U) +/*! FEIE - FIFO Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) + +#define LPI2C_SIER_AM0IE_MASK (0x1000U) +#define LPI2C_SIER_AM0IE_SHIFT (12U) +/*! AM0IE - Address Match 0 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) + +#define LPI2C_SIER_AM1IE_MASK (0x2000U) +#define LPI2C_SIER_AM1IE_SHIFT (13U) +/*! AM1IE - Address Match 1 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_AM1IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK) + +#define LPI2C_SIER_GCIE_MASK (0x4000U) +#define LPI2C_SIER_GCIE_SHIFT (14U) +/*! GCIE - General Call Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) + +#define LPI2C_SIER_SARIE_MASK (0x8000U) +#define LPI2C_SIER_SARIE_SHIFT (15U) +/*! SARIE - SMBus Alert Response Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) +/*! @} */ + +/*! @name SDER - Target DMA Enable */ +/*! @{ */ + +#define LPI2C_SDER_TDDE_MASK (0x1U) +#define LPI2C_SDER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) + +#define LPI2C_SDER_RDDE_MASK (0x2U) +#define LPI2C_SDER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable DMA request + * 0b1..Enable DMA request + */ +#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) + +#define LPI2C_SDER_AVDE_MASK (0x4U) +#define LPI2C_SDER_AVDE_SHIFT (2U) +/*! AVDE - Address Valid DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) + +#define LPI2C_SDER_RSDE_MASK (0x100U) +#define LPI2C_SDER_RSDE_SHIFT (8U) +/*! RSDE - Repeated Start DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_RSDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RSDE_SHIFT)) & LPI2C_SDER_RSDE_MASK) + +#define LPI2C_SDER_SDDE_MASK (0x200U) +#define LPI2C_SDER_SDDE_SHIFT (9U) +/*! SDDE - Stop Detect DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SDER_SDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_SDDE_SHIFT)) & LPI2C_SDER_SDDE_MASK) +/*! @} */ + +/*! @name SCFGR0 - Target Configuration 0 */ +/*! @{ */ + +#define LPI2C_SCFGR0_RDREQ_MASK (0x1U) +#define LPI2C_SCFGR0_RDREQ_SHIFT (0U) +/*! RDREQ - Read Request + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR0_RDREQ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDREQ_SHIFT)) & LPI2C_SCFGR0_RDREQ_MASK) + +#define LPI2C_SCFGR0_RDACK_MASK (0x2U) +#define LPI2C_SCFGR0_RDACK_SHIFT (1U) +/*! RDACK - Read Acknowledge Flag + * 0b0..Read Request not acknowledged + * 0b1..Read Request acknowledged + */ +#define LPI2C_SCFGR0_RDACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDACK_SHIFT)) & LPI2C_SCFGR0_RDACK_MASK) +/*! @} */ + +/*! @name SCFGR1 - Target Configuration 1 */ +/*! @{ */ + +#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) +#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) +/*! ADRSTALL - Address SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) + +#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) +#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) +/*! RXSTALL - RX SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) + +#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) +#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) +/*! TXDSTALL - Transmit Data SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) + +#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) +#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) +/*! ACKSTALL - ACK SCL Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) + +#define LPI2C_SCFGR1_RXNACK_MASK (0x10U) +#define LPI2C_SCFGR1_RXNACK_SHIFT (4U) +/*! RXNACK - Receive NACK + * 0b0..ACK or NACK always determined by STAR[TXNACK] + * 0b1..NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR[TXNACK] + */ +#define LPI2C_SCFGR1_RXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXNACK_SHIFT)) & LPI2C_SCFGR1_RXNACK_MASK) + +#define LPI2C_SCFGR1_GCEN_MASK (0x100U) +#define LPI2C_SCFGR1_GCEN_SHIFT (8U) +/*! GCEN - General Call Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) + +#define LPI2C_SCFGR1_SAEN_MASK (0x200U) +#define LPI2C_SCFGR1_SAEN_SHIFT (9U) +/*! SAEN - SMBus Alert Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) + +#define LPI2C_SCFGR1_TXCFG_MASK (0x400U) +#define LPI2C_SCFGR1_TXCFG_SHIFT (10U) +/*! TXCFG - Transmit Flag Configuration + * 0b0..MSR[TDF] is set only during a target-transmit transfer when STDR is empty + * 0b1..MSR[TDF] is set whenever STDR is empty + */ +#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) + +#define LPI2C_SCFGR1_RXCFG_MASK (0x800U) +#define LPI2C_SCFGR1_RXCFG_SHIFT (11U) +/*! RXCFG - Receive Data Configuration + * 0b0..Return received data, clear MSR[RDF] + * 0b1..Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear MSR[RDF] when SSR[AFV] is not set + */ +#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) + +#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) +#define LPI2C_SCFGR1_IGNACK_SHIFT (12U) +/*! IGNACK - Ignore NACK + * 0b0..End transfer on NACK + * 0b1..Do not end transfer on NACK + */ +#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) + +#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) +#define LPI2C_SCFGR1_HSMEN_SHIFT (13U) +/*! HSMEN - HS Mode Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) + +#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) +#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) +/*! ADDRCFG - Address Configuration + * 0b000..Address match 0 (7-bit) + * 0b001..Address match 0 (10-bit) + * 0b010..Address match 0 (7-bit) or address match 1 (7-bit) + * 0b011..Address match 0 (10-bit) or address match 1 (10-bit) + * 0b100..Address match 0 (7-bit) or address match 1 (10-bit) + * 0b101..Address match 0 (10-bit) or address match 1 (7-bit) + * 0b110..From address match 0 (7-bit) to address match 1 (7-bit) + * 0b111..From address match 0 (10-bit) to address match 1 (10-bit) + */ +#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) + +#define LPI2C_SCFGR1_RXALL_MASK (0x1000000U) +#define LPI2C_SCFGR1_RXALL_SHIFT (24U) +/*! RXALL - Receive All + * 0b0..Disable + * 0b1..Enable + */ +#define LPI2C_SCFGR1_RXALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXALL_SHIFT)) & LPI2C_SCFGR1_RXALL_MASK) + +#define LPI2C_SCFGR1_RSCFG_MASK (0x2000000U) +#define LPI2C_SCFGR1_RSCFG_SHIFT (25U) +/*! RSCFG - Repeated Start Configuration + * 0b0..Any repeated Start condition following an address match + * 0b1..Any repeated Start condition + */ +#define LPI2C_SCFGR1_RSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RSCFG_SHIFT)) & LPI2C_SCFGR1_RSCFG_MASK) + +#define LPI2C_SCFGR1_SDCFG_MASK (0x4000000U) +#define LPI2C_SCFGR1_SDCFG_SHIFT (26U) +/*! SDCFG - Stop Detect Configuration + * 0b0..Any Stop condition following an address match + * 0b1..Any Stop condition + */ +#define LPI2C_SCFGR1_SDCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SDCFG_SHIFT)) & LPI2C_SCFGR1_SDCFG_MASK) +/*! @} */ + +/*! @name SCFGR2 - Target Configuration 2 */ +/*! @{ */ + +#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) +#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) +/*! CLKHOLD - Clock Hold Time */ +#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) + +#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) +#define LPI2C_SCFGR2_DATAVD_SHIFT (8U) +/*! DATAVD - Data Valid Delay */ +#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) + +#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) +#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) +/*! FILTSCL - Glitch Filter SCL */ +#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) + +#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) +#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) +/*! FILTSDA - Glitch Filter SDA */ +#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) +/*! @} */ + +/*! @name SAMR - Target Address Match */ +/*! @{ */ + +#define LPI2C_SAMR_ADDR0_MASK (0x7FEU) +#define LPI2C_SAMR_ADDR0_SHIFT (1U) +/*! ADDR0 - Address 0 Value */ +#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) + +#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) +#define LPI2C_SAMR_ADDR1_SHIFT (17U) +/*! ADDR1 - Address 1 Value */ +#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) +/*! @} */ + +/*! @name SASR - Target Address Status */ +/*! @{ */ + +#define LPI2C_SASR_RADDR_MASK (0x7FFU) +#define LPI2C_SASR_RADDR_SHIFT (0U) +/*! RADDR - Received Address */ +#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) + +#define LPI2C_SASR_ANV_MASK (0x4000U) +#define LPI2C_SASR_ANV_SHIFT (14U) +/*! ANV - Address Not Valid + * 0b0..Valid + * 0b1..Not valid + */ +#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) +/*! @} */ + +/*! @name STAR - Target Transmit ACK */ +/*! @{ */ + +#define LPI2C_STAR_TXNACK_MASK (0x1U) +#define LPI2C_STAR_TXNACK_SHIFT (0U) +/*! TXNACK - Transmit NACK + * 0b0..Transmit ACK + * 0b1..Transmit NACK + */ +#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) +/*! @} */ + +/*! @name STDR - Target Transmit Data */ +/*! @{ */ + +#define LPI2C_STDR_DATA_MASK (0xFFU) +#define LPI2C_STDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data */ +#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) +/*! @} */ + +/*! @name SRDR - Target Receive Data */ +/*! @{ */ + +#define LPI2C_SRDR_DATA_MASK (0xFFU) +#define LPI2C_SRDR_DATA_SHIFT (0U) +/*! DATA - Received Data */ +#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) + +#define LPI2C_SRDR_RADDR_MASK (0x700U) +#define LPI2C_SRDR_RADDR_SHIFT (8U) +/*! RADDR - Received Address */ +#define LPI2C_SRDR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RADDR_SHIFT)) & LPI2C_SRDR_RADDR_MASK) + +#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) +#define LPI2C_SRDR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) + +#define LPI2C_SRDR_SOF_MASK (0x8000U) +#define LPI2C_SRDR_SOF_SHIFT (15U) +/*! SOF - Start of Frame + * 0b0..Not first + * 0b1..First + */ +#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) +/*! @} */ + +/*! @name SRDROR - Target Receive Data Read Only */ +/*! @{ */ + +#define LPI2C_SRDROR_DATA_MASK (0xFFU) +#define LPI2C_SRDROR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPI2C_SRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_DATA_SHIFT)) & LPI2C_SRDROR_DATA_MASK) + +#define LPI2C_SRDROR_RADDR_MASK (0x700U) +#define LPI2C_SRDROR_RADDR_SHIFT (8U) +/*! RADDR - Received Address */ +#define LPI2C_SRDROR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RADDR_SHIFT)) & LPI2C_SRDROR_RADDR_MASK) + +#define LPI2C_SRDROR_RXEMPTY_MASK (0x4000U) +#define LPI2C_SRDROR_RXEMPTY_SHIFT (14U) +/*! RXEMPTY - Receive Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPI2C_SRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RXEMPTY_SHIFT)) & LPI2C_SRDROR_RXEMPTY_MASK) + +#define LPI2C_SRDROR_SOF_MASK (0x8000U) +#define LPI2C_SRDROR_SOF_SHIFT (15U) +/*! SOF - Start of Frame + * 0b0..Not the first + * 0b1..First + */ +#define LPI2C_SRDROR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_SOF_SHIFT)) & LPI2C_SRDROR_SOF_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPI2C_Register_Masks */ + + +/* LPI2C - Peripheral instance base addresses */ +/** Peripheral LPI2C0 base address */ +#define LPI2C0_BASE (0x4009A000u) +/** Peripheral LPI2C0 base pointer */ +#define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE) +/** Peripheral LPI2C1 base address */ +#define LPI2C1_BASE (0x4009B000u) +/** Peripheral LPI2C1 base pointer */ +#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE) +/** Peripheral LPI2C2 base address */ +#define LPI2C2_BASE (0x400D4000u) +/** Peripheral LPI2C2 base pointer */ +#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE) +/** Peripheral LPI2C3 base address */ +#define LPI2C3_BASE (0x400D5000u) +/** Peripheral LPI2C3 base pointer */ +#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE) +/** Array initializer of LPI2C peripheral base addresses */ +#define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE } +/** Array initializer of LPI2C peripheral base pointers */ +#define LPI2C_BASE_PTRS { LPI2C0, LPI2C1, LPI2C2, LPI2C3 } +/** Interrupt vectors for the LPI2C peripheral type */ +#define LPI2C_IRQS { LPI2C0_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn } + +/*! + * @} + */ /* end of group LPI2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer + * @{ + */ + +/** LPSPI - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t CR; /**< Control, offset: 0x10 */ + __IO uint32_t SR; /**< Status, offset: 0x14 */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x18 */ + __IO uint32_t DER; /**< DMA Enable, offset: 0x1C */ + __IO uint32_t CFGR0; /**< Configuration 0, offset: 0x20 */ + __IO uint32_t CFGR1; /**< Configuration 1, offset: 0x24 */ + uint8_t RESERVED_1[8]; + __IO uint32_t DMR0; /**< Data Match 0, offset: 0x30 */ + __IO uint32_t DMR1; /**< Data Match 1, offset: 0x34 */ + uint8_t RESERVED_2[8]; + __IO uint32_t CCR; /**< Clock Configuration, offset: 0x40 */ + __IO uint32_t CCR1; /**< Clock Configuration 1, offset: 0x44 */ + uint8_t RESERVED_3[16]; + __IO uint32_t FCR; /**< FIFO Control, offset: 0x58 */ + __I uint32_t FSR; /**< FIFO Status, offset: 0x5C */ + __IO uint32_t TCR; /**< Transmit Command, offset: 0x60 */ + __O uint32_t TDR; /**< Transmit Data, offset: 0x64 */ + uint8_t RESERVED_4[8]; + __I uint32_t RSR; /**< Receive Status, offset: 0x70 */ + __I uint32_t RDR; /**< Receive Data, offset: 0x74 */ + __I uint32_t RDROR; /**< Receive Data Read Only, offset: 0x78 */ + uint8_t RESERVED_5[896]; + __O uint32_t TCBR; /**< Transmit Command Burst, offset: 0x3FC */ + __O uint32_t TDBR[128]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ + __I uint32_t RDBR[128]; /**< Receive Data Burst, array offset: 0x600, array step: 0x4 */ +} LPSPI_Type; + +/* ---------------------------------------------------------------------------- + -- LPSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPSPI_Register_Masks LPSPI Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPSPI_VERID_FEATURE_MASK (0xFFFFU) +#define LPSPI_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Module Identification Number + * 0b0000000000000100..Standard feature set supporting a 32-bit shift register. + * *.. + */ +#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) + +#define LPSPI_VERID_MINOR_MASK (0xFF0000U) +#define LPSPI_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) + +#define LPSPI_VERID_MAJOR_MASK (0xFF000000U) +#define LPSPI_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPSPI_PARAM_TXFIFO_MASK (0xFFU) +#define LPSPI_PARAM_TXFIFO_SHIFT (0U) +/*! TXFIFO - Transmit FIFO Size */ +#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) + +#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) +#define LPSPI_PARAM_RXFIFO_SHIFT (8U) +/*! RXFIFO - Receive FIFO Size */ +#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) + +#define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U) +#define LPSPI_PARAM_PCSNUM_SHIFT (16U) +/*! PCSNUM - PCS Number */ +#define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK) +/*! @} */ + +/*! @name CR - Control */ +/*! @{ */ + +#define LPSPI_CR_MEN_MASK (0x1U) +#define LPSPI_CR_MEN_SHIFT (0U) +/*! MEN - Module Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) + +#define LPSPI_CR_RST_MASK (0x2U) +#define LPSPI_CR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset + */ +#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) + +#define LPSPI_CR_DBGEN_MASK (0x8U) +#define LPSPI_CR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) + +#define LPSPI_CR_RTF_MASK (0x100U) +#define LPSPI_CR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Reset + */ +#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) + +#define LPSPI_CR_RRF_MASK (0x200U) +#define LPSPI_CR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Reset + */ +#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) +/*! @} */ + +/*! @name SR - Status */ +/*! @{ */ + +#define LPSPI_SR_TDF_MASK (0x1U) +#define LPSPI_SR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data requested + */ +#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) + +#define LPSPI_SR_RDF_MASK (0x2U) +#define LPSPI_SR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive data not ready + * 0b1..Receive data ready + */ +#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) + +#define LPSPI_SR_WCF_MASK (0x100U) +#define LPSPI_SR_WCF_SHIFT (8U) +/*! WCF - Word Complete Flag + * 0b0..Not complete + * 0b1..Complete + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) + +#define LPSPI_SR_FCF_MASK (0x200U) +#define LPSPI_SR_FCF_SHIFT (9U) +/*! FCF - Frame Complete Flag + * 0b0..Not complete + * 0b1..Complete + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) + +#define LPSPI_SR_TCF_MASK (0x400U) +#define LPSPI_SR_TCF_SHIFT (10U) +/*! TCF - Transfer Complete Flag + * 0b0..Not complete + * 0b1..Complete + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) + +#define LPSPI_SR_TEF_MASK (0x800U) +#define LPSPI_SR_TEF_SHIFT (11U) +/*! TEF - Transmit Error Flag + * 0b0..No underrun + * 0b1..Underrun + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) + +#define LPSPI_SR_REF_MASK (0x1000U) +#define LPSPI_SR_REF_SHIFT (12U) +/*! REF - Receive Error Flag + * 0b0..No overflow + * 0b1..Overflow + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) + +#define LPSPI_SR_DMF_MASK (0x2000U) +#define LPSPI_SR_DMF_SHIFT (13U) +/*! DMF - Data Match Flag + * 0b0..No match + * 0b1..Match + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) + +#define LPSPI_SR_MBF_MASK (0x1000000U) +#define LPSPI_SR_MBF_SHIFT (24U) +/*! MBF - Module Busy Flag + * 0b0..LPSPI is idle + * 0b1..LPSPI is busy + */ +#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) +/*! @} */ + +/*! @name IER - Interrupt Enable */ +/*! @{ */ + +#define LPSPI_IER_TDIE_MASK (0x1U) +#define LPSPI_IER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) + +#define LPSPI_IER_RDIE_MASK (0x2U) +#define LPSPI_IER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) + +#define LPSPI_IER_WCIE_MASK (0x100U) +#define LPSPI_IER_WCIE_SHIFT (8U) +/*! WCIE - Word Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) + +#define LPSPI_IER_FCIE_MASK (0x200U) +#define LPSPI_IER_FCIE_SHIFT (9U) +/*! FCIE - Frame Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) + +#define LPSPI_IER_TCIE_MASK (0x400U) +#define LPSPI_IER_TCIE_SHIFT (10U) +/*! TCIE - Transfer Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) + +#define LPSPI_IER_TEIE_MASK (0x800U) +#define LPSPI_IER_TEIE_SHIFT (11U) +/*! TEIE - Transmit Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) + +#define LPSPI_IER_REIE_MASK (0x1000U) +#define LPSPI_IER_REIE_SHIFT (12U) +/*! REIE - Receive Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) + +#define LPSPI_IER_DMIE_MASK (0x2000U) +#define LPSPI_IER_DMIE_SHIFT (13U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) +/*! @} */ + +/*! @name DER - DMA Enable */ +/*! @{ */ + +#define LPSPI_DER_TDDE_MASK (0x1U) +#define LPSPI_DER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) + +#define LPSPI_DER_RDDE_MASK (0x2U) +#define LPSPI_DER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) + +#define LPSPI_DER_FCDE_MASK (0x200U) +#define LPSPI_DER_FCDE_SHIFT (9U) +/*! FCDE - Frame Complete DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_DER_FCDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_FCDE_SHIFT)) & LPSPI_DER_FCDE_MASK) +/*! @} */ + +/*! @name CFGR0 - Configuration 0 */ +/*! @{ */ + +#define LPSPI_CFGR0_HREN_MASK (0x1U) +#define LPSPI_CFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) + +#define LPSPI_CFGR0_HRPOL_MASK (0x2U) +#define LPSPI_CFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..Active high + * 0b1..Active low + */ +#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) + +#define LPSPI_CFGR0_HRSEL_MASK (0x4U) +#define LPSPI_CFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..HREQ pin + * 0b1..Input trigger + */ +#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) + +#define LPSPI_CFGR0_HRDIR_MASK (0x8U) +#define LPSPI_CFGR0_HRDIR_SHIFT (3U) +/*! HRDIR - Host Request Direction + * 0b0..Input + * 0b1..Output + */ +#define LPSPI_CFGR0_HRDIR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRDIR_SHIFT)) & LPSPI_CFGR0_HRDIR_MASK) + +#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) +#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) + +#define LPSPI_CFGR0_RDMO_MASK (0x200U) +#define LPSPI_CFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) +/*! @} */ + +/*! @name CFGR1 - Configuration 1 */ +/*! @{ */ + +#define LPSPI_CFGR1_MASTER_MASK (0x1U) +#define LPSPI_CFGR1_MASTER_SHIFT (0U) +/*! MASTER - Master Mode + * 0b0..Slave mode + * 0b1..Master mode + */ +#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) + +#define LPSPI_CFGR1_SAMPLE_MASK (0x2U) +#define LPSPI_CFGR1_SAMPLE_SHIFT (1U) +/*! SAMPLE - Sample Point + * 0b0..SCK edge + * 0b1..Delayed SCK edge + */ +#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) + +#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) +#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) +/*! AUTOPCS - Automatic PCS + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) + +#define LPSPI_CFGR1_NOSTALL_MASK (0x8U) +#define LPSPI_CFGR1_NOSTALL_SHIFT (3U) +/*! NOSTALL - No Stall + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) + +#define LPSPI_CFGR1_PARTIAL_MASK (0x10U) +#define LPSPI_CFGR1_PARTIAL_SHIFT (4U) +/*! PARTIAL - Partial Enable + * 0b0..Discard + * 0b1..Store + */ +#define LPSPI_CFGR1_PARTIAL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PARTIAL_SHIFT)) & LPSPI_CFGR1_PARTIAL_MASK) + +#define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) +#define LPSPI_CFGR1_PCSPOL_SHIFT (8U) +/*! PCSPOL - Peripheral Chip Select Polarity + * 0b0000..Active low + * 0b0001..Active high + */ +#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) + +#define LPSPI_CFGR1_MATCFG_MASK (0x70000U) +#define LPSPI_CFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001.. + * 0b010..Match first data word with compare word + * 0b011..Match any data word with compare word + * 0b100..Sequential match, first data word + * 0b101..Sequential match, any data word + * 0b110..Match first data word (masked) with compare word (masked) + * 0b111..Match any data word (masked) with compare word (masked) + */ +#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) + +#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) +#define LPSPI_CFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b00..SIN is used for input data; SOUT is used for output data + * 0b01..SIN is used for both input and output data; only half-duplex serial transfers are supported + * 0b10..SOUT is used for both input and output data; only half-duplex serial transfers are supported + * 0b11..SOUT is used for input data; SIN is used for output data + */ +#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) + +#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) +#define LPSPI_CFGR1_OUTCFG_SHIFT (26U) +/*! OUTCFG - Output Configuration + * 0b0..Retain last value + * 0b1..3-stated + */ +#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) + +#define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) +#define LPSPI_CFGR1_PCSCFG_SHIFT (27U) +/*! PCSCFG - Peripheral Chip Select Configuration + * 0b0..PCS[3:2] configured for chip select function + * 0b1..PCS[3:2] configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2]) + */ +#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) +/*! @} */ + +/*! @name DMR0 - Data Match 0 */ +/*! @{ */ + +#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) +#define LPSPI_DMR0_MATCH0_SHIFT (0U) +/*! MATCH0 - Match 0 Value */ +#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) +/*! @} */ + +/*! @name DMR1 - Data Match 1 */ +/*! @{ */ + +#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) +#define LPSPI_DMR1_MATCH1_SHIFT (0U) +/*! MATCH1 - Match 1 Value */ +#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) +/*! @} */ + +/*! @name CCR - Clock Configuration */ +/*! @{ */ + +#define LPSPI_CCR_SCKDIV_MASK (0xFFU) +#define LPSPI_CCR_SCKDIV_SHIFT (0U) +/*! SCKDIV - SCK Divider */ +#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) + +#define LPSPI_CCR_DBT_MASK (0xFF00U) +#define LPSPI_CCR_DBT_SHIFT (8U) +/*! DBT - Delay Between Transfers */ +#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) + +#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) +#define LPSPI_CCR_PCSSCK_SHIFT (16U) +/*! PCSSCK - PCS-to-SCK Delay */ +#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) + +#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) +#define LPSPI_CCR_SCKPCS_SHIFT (24U) +/*! SCKPCS - SCK-to-PCS Delay */ +#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) +/*! @} */ + +/*! @name CCR1 - Clock Configuration 1 */ +/*! @{ */ + +#define LPSPI_CCR1_SCKSET_MASK (0xFFU) +#define LPSPI_CCR1_SCKSET_SHIFT (0U) +/*! SCKSET - SCK Setup */ +#define LPSPI_CCR1_SCKSET(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSET_SHIFT)) & LPSPI_CCR1_SCKSET_MASK) + +#define LPSPI_CCR1_SCKHLD_MASK (0xFF00U) +#define LPSPI_CCR1_SCKHLD_SHIFT (8U) +/*! SCKHLD - SCK Hold */ +#define LPSPI_CCR1_SCKHLD(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKHLD_SHIFT)) & LPSPI_CCR1_SCKHLD_MASK) + +#define LPSPI_CCR1_PCSPCS_MASK (0xFF0000U) +#define LPSPI_CCR1_PCSPCS_SHIFT (16U) +/*! PCSPCS - PCS to PCS Delay */ +#define LPSPI_CCR1_PCSPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_PCSPCS_SHIFT)) & LPSPI_CCR1_PCSPCS_MASK) + +#define LPSPI_CCR1_SCKSCK_MASK (0xFF000000U) +#define LPSPI_CCR1_SCKSCK_SHIFT (24U) +/*! SCKSCK - SCK Inter-Frame Delay */ +#define LPSPI_CCR1_SCKSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR1_SCKSCK_SHIFT)) & LPSPI_CCR1_SCKSCK_MASK) +/*! @} */ + +/*! @name FCR - FIFO Control */ +/*! @{ */ + +#define LPSPI_FCR_TXWATER_MASK (0x3U) +#define LPSPI_FCR_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit FIFO Watermark */ +#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) + +#define LPSPI_FCR_RXWATER_MASK (0x30000U) +#define LPSPI_FCR_RXWATER_SHIFT (16U) +/*! RXWATER - Receive FIFO Watermark */ +#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) +/*! @} */ + +/*! @name FSR - FIFO Status */ +/*! @{ */ + +#define LPSPI_FSR_TXCOUNT_MASK (0x7U) +#define LPSPI_FSR_TXCOUNT_SHIFT (0U) +/*! TXCOUNT - Transmit FIFO Count */ +#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) + +#define LPSPI_FSR_RXCOUNT_MASK (0x70000U) +#define LPSPI_FSR_RXCOUNT_SHIFT (16U) +/*! RXCOUNT - Receive FIFO Count */ +#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) +/*! @} */ + +/*! @name TCR - Transmit Command */ +/*! @{ */ + +#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) +#define LPSPI_TCR_FRAMESZ_SHIFT (0U) +/*! FRAMESZ - Frame Size */ +#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) + +#define LPSPI_TCR_WIDTH_MASK (0x30000U) +#define LPSPI_TCR_WIDTH_SHIFT (16U) +/*! WIDTH - Transfer Width + * 0b00..1-bit transfer + * 0b01..2-bit transfer + * 0b10..4-bit transfer + * 0b11..Reserved + */ +#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) + +#define LPSPI_TCR_TXMSK_MASK (0x40000U) +#define LPSPI_TCR_TXMSK_SHIFT (18U) +/*! TXMSK - Transmit Data Mask + * 0b0..Normal transfer + * 0b1..Mask transmit data + */ +#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) + +#define LPSPI_TCR_RXMSK_MASK (0x80000U) +#define LPSPI_TCR_RXMSK_SHIFT (19U) +/*! RXMSK - Receive Data Mask + * 0b0..Normal transfer + * 0b1..Mask receive data + */ +#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) + +#define LPSPI_TCR_CONTC_MASK (0x100000U) +#define LPSPI_TCR_CONTC_SHIFT (20U) +/*! CONTC - Continuing Command + * 0b0..Command word for start of new transfer + * 0b1..Command word for continuing transfer + */ +#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) + +#define LPSPI_TCR_CONT_MASK (0x200000U) +#define LPSPI_TCR_CONT_SHIFT (21U) +/*! CONT - Continuous Transfer + * 0b0..Disable + * 0b1..Enable + */ +#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) + +#define LPSPI_TCR_BYSW_MASK (0x400000U) +#define LPSPI_TCR_BYSW_SHIFT (22U) +/*! BYSW - Byte Swap + * 0b0..Disable byte swap + * 0b1..Enable byte swap + */ +#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) + +#define LPSPI_TCR_LSBF_MASK (0x800000U) +#define LPSPI_TCR_LSBF_SHIFT (23U) +/*! LSBF - LSB First + * 0b0..MSB first + * 0b1..LSB first + */ +#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) + +#define LPSPI_TCR_PCS_MASK (0x3000000U) +#define LPSPI_TCR_PCS_SHIFT (24U) +/*! PCS - Peripheral Chip Select + * 0b00..Transfer using PCS[0] + * 0b01..Transfer using PCS[1] + * 0b10..Transfer using PCS[2] + * 0b11..Transfer using PCS[3] + */ +#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) + +#define LPSPI_TCR_PRESCALE_MASK (0x38000000U) +#define LPSPI_TCR_PRESCALE_SHIFT (27U) +/*! PRESCALE - Prescaler Value + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) + +#define LPSPI_TCR_CPHA_MASK (0x40000000U) +#define LPSPI_TCR_CPHA_SHIFT (30U) +/*! CPHA - Clock Phase + * 0b0..Captured + * 0b1..Changed + */ +#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) + +#define LPSPI_TCR_CPOL_MASK (0x80000000U) +#define LPSPI_TCR_CPOL_SHIFT (31U) +/*! CPOL - Clock Polarity + * 0b0..Inactive low + * 0b1..Inactive high + */ +#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) +/*! @} */ + +/*! @name TDR - Transmit Data */ +/*! @{ */ + +#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TDR_DATA_SHIFT (0U) +/*! DATA - Transmit Data */ +#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) +/*! @} */ + +/*! @name RSR - Receive Status */ +/*! @{ */ + +#define LPSPI_RSR_SOF_MASK (0x1U) +#define LPSPI_RSR_SOF_SHIFT (0U) +/*! SOF - Start of Frame + * 0b0..Subsequent data word + * 0b1..First data word + */ +#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) + +#define LPSPI_RSR_RXEMPTY_MASK (0x2U) +#define LPSPI_RSR_RXEMPTY_SHIFT (1U) +/*! RXEMPTY - RX FIFO Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) +/*! @} */ + +/*! @name RDR - Receive Data */ +/*! @{ */ + +#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) +/*! @} */ + +/*! @name RDROR - Receive Data Read Only */ +/*! @{ */ + +#define LPSPI_RDROR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDROR_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPSPI_RDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDROR_DATA_SHIFT)) & LPSPI_RDROR_DATA_MASK) +/*! @} */ + +/*! @name TCBR - Transmit Command Burst */ +/*! @{ */ + +#define LPSPI_TCBR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TCBR_DATA_SHIFT (0U) +/*! DATA - Command Data */ +#define LPSPI_TCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCBR_DATA_SHIFT)) & LPSPI_TCBR_DATA_MASK) +/*! @} */ + +/*! @name TDBR - Transmit Data Burst */ +/*! @{ */ + +#define LPSPI_TDBR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TDBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPSPI_TDBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDBR_DATA_SHIFT)) & LPSPI_TDBR_DATA_MASK) +/*! @} */ + +/* The count of LPSPI_TDBR */ +#define LPSPI_TDBR_COUNT (128U) + +/*! @name RDBR - Receive Data Burst */ +/*! @{ */ + +#define LPSPI_RDBR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDBR_DATA_SHIFT (0U) +/*! DATA - Data */ +#define LPSPI_RDBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDBR_DATA_SHIFT)) & LPSPI_RDBR_DATA_MASK) +/*! @} */ + +/* The count of LPSPI_RDBR */ +#define LPSPI_RDBR_COUNT (128U) + + +/*! + * @} + */ /* end of group LPSPI_Register_Masks */ + + +/* LPSPI - Peripheral instance base addresses */ +/** Peripheral LPSPI0 base address */ +#define LPSPI0_BASE (0x4009C000u) +/** Peripheral LPSPI0 base pointer */ +#define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE) +/** Peripheral LPSPI1 base address */ +#define LPSPI1_BASE (0x4009D000u) +/** Peripheral LPSPI1 base pointer */ +#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE) +/** Array initializer of LPSPI peripheral base addresses */ +#define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE } +/** Array initializer of LPSPI peripheral base pointers */ +#define LPSPI_BASE_PTRS { LPSPI0, LPSPI1 } +/** Interrupt vectors for the LPSPI peripheral type */ +#define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn } + +/*! + * @} + */ /* end of group LPSPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPTMR Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer + * @{ + */ + +/** LPTMR - Register Layout Typedef */ +typedef struct { + __IO uint32_t CSR; /**< Control Status, offset: 0x0 */ + __IO uint32_t PSR; /**< Prescaler and Glitch Filter, offset: 0x4 */ + __IO uint32_t CMR; /**< Compare, offset: 0x8 */ + __IO uint32_t CNR; /**< Counter, offset: 0xC */ +} LPTMR_Type; + +/* ---------------------------------------------------------------------------- + -- LPTMR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPTMR_Register_Masks LPTMR Register Masks + * @{ + */ + +/*! @name CSR - Control Status */ +/*! @{ */ + +#define LPTMR_CSR_TEN_MASK (0x1U) +#define LPTMR_CSR_TEN_SHIFT (0U) +/*! TEN - Timer Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) + +#define LPTMR_CSR_TMS_MASK (0x2U) +#define LPTMR_CSR_TMS_SHIFT (1U) +/*! TMS - Timer Mode Select + * 0b0..Time Counter + * 0b1..Pulse Counter + */ +#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) + +#define LPTMR_CSR_TFC_MASK (0x4U) +#define LPTMR_CSR_TFC_SHIFT (2U) +/*! TFC - Timer Free-Running Counter + * 0b0..Reset when TCF asserts + * 0b1..Reset on overflow + */ +#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) + +#define LPTMR_CSR_TPP_MASK (0x8U) +#define LPTMR_CSR_TPP_SHIFT (3U) +/*! TPP - Timer Pin Polarity + * 0b0..Active-high + * 0b1..Active-low + */ +#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) + +#define LPTMR_CSR_TPS_MASK (0x30U) +#define LPTMR_CSR_TPS_SHIFT (4U) +/*! TPS - Timer Pin Select + * 0b00..Input 0 + * 0b01..Input 1 + * 0b10..Input 2 + * 0b11..Input 3 + */ +#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) + +#define LPTMR_CSR_TIE_MASK (0x40U) +#define LPTMR_CSR_TIE_SHIFT (6U) +/*! TIE - Timer Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) + +#define LPTMR_CSR_TCF_MASK (0x80U) +#define LPTMR_CSR_TCF_SHIFT (7U) +/*! TCF - Timer Compare Flag + * 0b0..CNR != (CMR + 1) + * 0b1..CNR = (CMR + 1) + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) + +#define LPTMR_CSR_TDRE_MASK (0x100U) +#define LPTMR_CSR_TDRE_SHIFT (8U) +/*! TDRE - Timer DMA Request Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TDRE_SHIFT)) & LPTMR_CSR_TDRE_MASK) +/*! @} */ + +/*! @name PSR - Prescaler and Glitch Filter */ +/*! @{ */ + +#define LPTMR_PSR_PCS_MASK (0x3U) +#define LPTMR_PSR_PCS_SHIFT (0U) +/*! PCS - Prescaler and Glitch Filter Clock Select + * 0b00..Clock 0 + * 0b01..Clock 1 + * 0b10..Clock 2 + * 0b11..Clock 3 + */ +#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) + +#define LPTMR_PSR_PBYP_MASK (0x4U) +#define LPTMR_PSR_PBYP_SHIFT (2U) +/*! PBYP - Prescaler and Glitch Filter Bypass + * 0b0..Prescaler and glitch filter enable + * 0b1..Prescaler and glitch filter bypass + */ +#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) + +#define LPTMR_PSR_PRESCALE_MASK (0x78U) +#define LPTMR_PSR_PRESCALE_SHIFT (3U) +/*! PRESCALE - Prescaler and Glitch Filter Value + * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration + * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after two rising clock edges + * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after four rising clock edges + * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after eight rising clock edges + * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges + * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges + * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges + * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges + * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges + * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges + * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges + * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges + * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges + * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges + * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges + * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges + */ +#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) +/*! @} */ + +/*! @name CMR - Compare */ +/*! @{ */ + +#define LPTMR_CMR_COMPARE_MASK (0xFFFFFFFFU) +#define LPTMR_CMR_COMPARE_SHIFT (0U) +/*! COMPARE - Compare Value */ +#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) +/*! @} */ + +/*! @name CNR - Counter */ +/*! @{ */ + +#define LPTMR_CNR_COUNTER_MASK (0xFFFFFFFFU) +#define LPTMR_CNR_COUNTER_SHIFT (0U) +/*! COUNTER - Counter Value */ +#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPTMR_Register_Masks */ + + +/* LPTMR - Peripheral instance base addresses */ +/** Peripheral LPTMR0 base address */ +#define LPTMR0_BASE (0x400AB000u) +/** Peripheral LPTMR0 base pointer */ +#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) +/** Array initializer of LPTMR peripheral base addresses */ +#define LPTMR_BASE_ADDRS { LPTMR0_BASE } +/** Array initializer of LPTMR peripheral base pointers */ +#define LPTMR_BASE_PTRS { LPTMR0 } +/** Interrupt vectors for the LPTMR peripheral type */ +#define LPTMR_IRQS { LPTMR0_IRQn } + +/*! + * @} + */ /* end of group LPTMR_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- LPUART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer + * @{ + */ + +/** LPUART - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t GLOBAL; /**< Global, offset: 0x8 */ + __IO uint32_t PINCFG; /**< Pin Configuration, offset: 0xC */ + __IO uint32_t BAUD; /**< Baud Rate, offset: 0x10 */ + __IO uint32_t STAT; /**< Status, offset: 0x14 */ + __IO uint32_t CTRL; /**< Control, offset: 0x18 */ + __IO uint32_t DATA; /**< Data, offset: 0x1C */ + __IO uint32_t MATCH; /**< Match Address, offset: 0x20 */ + __IO uint32_t MODIR; /**< MODEM IrDA, offset: 0x24 */ + __IO uint32_t FIFO; /**< FIFO, offset: 0x28 */ + __IO uint32_t WATER; /**< Watermark, offset: 0x2C */ + __I uint32_t DATARO; /**< Data Read-Only, offset: 0x30 */ +} LPUART_Type; + +/* ---------------------------------------------------------------------------- + -- LPUART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LPUART_Register_Masks LPUART Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define LPUART_VERID_FEATURE_MASK (0xFFFFU) +#define LPUART_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Identification Number + * 0b0000000000000001..Standard feature set + * 0b0000000000000011..Standard feature set with MODEM and IrDA support + */ +#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) + +#define LPUART_VERID_MINOR_MASK (0xFF0000U) +#define LPUART_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) + +#define LPUART_VERID_MAJOR_MASK (0xFF000000U) +#define LPUART_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define LPUART_PARAM_TXFIFO_MASK (0xFFU) +#define LPUART_PARAM_TXFIFO_SHIFT (0U) +/*! TXFIFO - Transmit FIFO Size */ +#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) + +#define LPUART_PARAM_RXFIFO_MASK (0xFF00U) +#define LPUART_PARAM_RXFIFO_SHIFT (8U) +/*! RXFIFO - Receive FIFO Size */ +#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK) +/*! @} */ + +/*! @name GLOBAL - Global */ +/*! @{ */ + +#define LPUART_GLOBAL_RST_MASK (0x2U) +#define LPUART_GLOBAL_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Not reset + * 0b1..Reset + */ +#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK) +/*! @} */ + +/*! @name PINCFG - Pin Configuration */ +/*! @{ */ + +#define LPUART_PINCFG_TRGSEL_MASK (0x3U) +#define LPUART_PINCFG_TRGSEL_SHIFT (0U) +/*! TRGSEL - Trigger Select + * 0b00..Input trigger disabled + * 0b01..Input trigger used instead of the RXD pin input + * 0b10..Input trigger used instead of the CTS_B pin input + * 0b11..Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger + */ +#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) +/*! @} */ + +/*! @name BAUD - Baud Rate */ +/*! @{ */ + +#define LPUART_BAUD_SBR_MASK (0x1FFFU) +#define LPUART_BAUD_SBR_SHIFT (0U) +/*! SBR - Baud Rate Modulo Divisor */ +#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) + +#define LPUART_BAUD_SBNS_MASK (0x2000U) +#define LPUART_BAUD_SBNS_SHIFT (13U) +/*! SBNS - Stop Bit Number Select + * 0b0..One stop bit + * 0b1..Two stop bits + */ +#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) + +#define LPUART_BAUD_RXEDGIE_MASK (0x4000U) +#define LPUART_BAUD_RXEDGIE_SHIFT (14U) +/*! RXEDGIE - RX Input Active Edge Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) + +#define LPUART_BAUD_LBKDIE_MASK (0x8000U) +#define LPUART_BAUD_LBKDIE_SHIFT (15U) +/*! LBKDIE - LIN Break Detect Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) + +#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) +#define LPUART_BAUD_RESYNCDIS_SHIFT (16U) +/*! RESYNCDIS - Resynchronization Disable + * 0b0..Enable + * 0b1..Disable + */ +#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) + +#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) +#define LPUART_BAUD_BOTHEDGE_SHIFT (17U) +/*! BOTHEDGE - Both Edge Sampling + * 0b0..Rising edge + * 0b1..Both rising and falling edges + */ +#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) + +#define LPUART_BAUD_MATCFG_MASK (0xC0000U) +#define LPUART_BAUD_MATCFG_SHIFT (18U) +/*! MATCFG - Match Configuration + * 0b00..Address match wake-up + * 0b01..Idle match wake-up + * 0b10..Match on and match off + * 0b11..Enables RWU on data match and match on or off for the transmitter CTS input + */ +#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) + +#define LPUART_BAUD_RIDMAE_MASK (0x100000U) +#define LPUART_BAUD_RIDMAE_SHIFT (20U) +/*! RIDMAE - Receiver Idle DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) + +#define LPUART_BAUD_RDMAE_MASK (0x200000U) +#define LPUART_BAUD_RDMAE_SHIFT (21U) +/*! RDMAE - Receiver Full DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) + +#define LPUART_BAUD_TDMAE_MASK (0x800000U) +#define LPUART_BAUD_TDMAE_SHIFT (23U) +/*! TDMAE - Transmitter DMA Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) + +#define LPUART_BAUD_OSR_MASK (0x1F000000U) +#define LPUART_BAUD_OSR_SHIFT (24U) +/*! OSR - Oversampling Ratio + * 0b00000..Results in an OSR of 16 + * 0b00001..Reserved + * 0b00010..Reserved + * 0b00011..Results in an OSR of 4 (requires BAUD[BOTHEDGE] to be 1) + * 0b00100..Results in an OSR of 5 (requires BAUD[BOTHEDGE] to be 1) + * 0b00101..Results in an OSR of 6 (requires BAUD[BOTHEDGE] to be 1) + * 0b00110..Results in an OSR of 7 (requires BAUD[BOTHEDGE] to be 1) + * 0b00111..Results in an OSR of 8 + * 0b01000..Results in an OSR of 9 + * 0b01001..Results in an OSR of 10 + * 0b01010..Results in an OSR of 11 + * 0b01011..Results in an OSR of 12 + * 0b01100..Results in an OSR of 13 + * 0b01101..Results in an OSR of 14 + * 0b01110..Results in an OSR of 15 + * 0b01111..Results in an OSR of 16 + * 0b10000..Results in an OSR of 17 + * 0b10001..Results in an OSR of 18 + * 0b10010..Results in an OSR of 19 + * 0b10011..Results in an OSR of 20 + * 0b10100..Results in an OSR of 21 + * 0b10101..Results in an OSR of 22 + * 0b10110..Results in an OSR of 23 + * 0b10111..Results in an OSR of 24 + * 0b11000..Results in an OSR of 25 + * 0b11001..Results in an OSR of 26 + * 0b11010..Results in an OSR of 27 + * 0b11011..Results in an OSR of 28 + * 0b11100..Results in an OSR of 29 + * 0b11101..Results in an OSR of 30 + * 0b11110..Results in an OSR of 31 + * 0b11111..Results in an OSR of 32 + */ +#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) + +#define LPUART_BAUD_M10_MASK (0x20000000U) +#define LPUART_BAUD_M10_SHIFT (29U) +/*! M10 - 10-Bit Mode Select + * 0b0..Receiver and transmitter use 7-bit to 9-bit data characters + * 0b1..Receiver and transmitter use 10-bit data characters + */ +#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) + +#define LPUART_BAUD_MAEN2_MASK (0x40000000U) +#define LPUART_BAUD_MAEN2_SHIFT (30U) +/*! MAEN2 - Match Address Mode Enable 2 + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) + +#define LPUART_BAUD_MAEN1_MASK (0x80000000U) +#define LPUART_BAUD_MAEN1_SHIFT (31U) +/*! MAEN1 - Match Address Mode Enable 1 + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) +/*! @} */ + +/*! @name STAT - Status */ +/*! @{ */ + +#define LPUART_STAT_LBKFE_MASK (0x1U) +#define LPUART_STAT_LBKFE_SHIFT (0U) +/*! LBKFE - LIN Break Flag Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_STAT_LBKFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKFE_SHIFT)) & LPUART_STAT_LBKFE_MASK) + +#define LPUART_STAT_AME_MASK (0x2U) +#define LPUART_STAT_AME_SHIFT (1U) +/*! AME - Address Mark Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_STAT_AME(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_AME_SHIFT)) & LPUART_STAT_AME_MASK) + +#define LPUART_STAT_MA2F_MASK (0x4000U) +#define LPUART_STAT_MA2F_SHIFT (14U) +/*! MA2F - Match 2 Flag + * 0b0..Not equal to MA2 + * 0b1..Equal to MA2 + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) + +#define LPUART_STAT_MA1F_MASK (0x8000U) +#define LPUART_STAT_MA1F_SHIFT (15U) +/*! MA1F - Match 1 Flag + * 0b0..Not equal to MA1 + * 0b1..Equal to MA1 + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) + +#define LPUART_STAT_PF_MASK (0x10000U) +#define LPUART_STAT_PF_SHIFT (16U) +/*! PF - Parity Error Flag + * 0b0..No parity error detected + * 0b1..Parity error detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) + +#define LPUART_STAT_FE_MASK (0x20000U) +#define LPUART_STAT_FE_SHIFT (17U) +/*! FE - Framing Error Flag + * 0b0..No framing error detected (this does not guarantee that the framing is correct) + * 0b1..Framing error detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) + +#define LPUART_STAT_NF_MASK (0x40000U) +#define LPUART_STAT_NF_SHIFT (18U) +/*! NF - Noise Flag + * 0b0..No noise detected + * 0b1..Noise detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) + +#define LPUART_STAT_OR_MASK (0x80000U) +#define LPUART_STAT_OR_SHIFT (19U) +/*! OR - Receiver Overrun Flag + * 0b0..No overrun + * 0b1..Receive overrun (new LPUART data is lost) + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) + +#define LPUART_STAT_IDLE_MASK (0x100000U) +#define LPUART_STAT_IDLE_SHIFT (20U) +/*! IDLE - Idle Line Flag + * 0b0..Idle line detected + * 0b1..Idle line not detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) + +#define LPUART_STAT_RDRF_MASK (0x200000U) +#define LPUART_STAT_RDRF_SHIFT (21U) +/*! RDRF - Receive Data Register Full Flag + * 0b0..Equal to or less than watermark + * 0b1..Greater than watermark + */ +#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) + +#define LPUART_STAT_TC_MASK (0x400000U) +#define LPUART_STAT_TC_SHIFT (22U) +/*! TC - Transmission Complete Flag + * 0b0..Transmitter active + * 0b1..Transmitter idle + */ +#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) + +#define LPUART_STAT_TDRE_MASK (0x800000U) +#define LPUART_STAT_TDRE_SHIFT (23U) +/*! TDRE - Transmit Data Register Empty Flag + * 0b0..Greater than watermark + * 0b1..Equal to or less than watermark + */ +#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) + +#define LPUART_STAT_RAF_MASK (0x1000000U) +#define LPUART_STAT_RAF_SHIFT (24U) +/*! RAF - Receiver Active Flag + * 0b0..Idle, waiting for a start bit + * 0b1..Receiver active (RXD pin input not idle) + */ +#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) + +#define LPUART_STAT_LBKDE_MASK (0x2000000U) +#define LPUART_STAT_LBKDE_SHIFT (25U) +/*! LBKDE - LIN Break Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) + +#define LPUART_STAT_BRK13_MASK (0x4000000U) +#define LPUART_STAT_BRK13_SHIFT (26U) +/*! BRK13 - Break Character Generation Length + * 0b0..9 to 13 bit times + * 0b1..12 to 15 bit times + */ +#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) + +#define LPUART_STAT_RWUID_MASK (0x8000000U) +#define LPUART_STAT_RWUID_SHIFT (27U) +/*! RWUID - Receive Wake Up Idle Detect + * 0b0..STAT[IDLE] does not become 1 + * 0b1..STAT[IDLE] becomes 1 + */ +#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) + +#define LPUART_STAT_RXINV_MASK (0x10000000U) +#define LPUART_STAT_RXINV_SHIFT (28U) +/*! RXINV - Receive Data Inversion + * 0b0..Inverted + * 0b1..Not inverted + */ +#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) + +#define LPUART_STAT_MSBF_MASK (0x20000000U) +#define LPUART_STAT_MSBF_SHIFT (29U) +/*! MSBF - MSB First + * 0b0..LSB + * 0b1..MSB + */ +#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) + +#define LPUART_STAT_RXEDGIF_MASK (0x40000000U) +#define LPUART_STAT_RXEDGIF_SHIFT (30U) +/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag + * 0b0..Not occurred + * 0b1..Occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) + +#define LPUART_STAT_LBKDIF_MASK (0x80000000U) +#define LPUART_STAT_LBKDIF_SHIFT (31U) +/*! LBKDIF - LIN Break Detect Interrupt Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) +/*! @} */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define LPUART_CTRL_PT_MASK (0x1U) +#define LPUART_CTRL_PT_SHIFT (0U) +/*! PT - Parity Type + * 0b0..Even parity + * 0b1..Odd parity + */ +#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) + +#define LPUART_CTRL_PE_MASK (0x2U) +#define LPUART_CTRL_PE_SHIFT (1U) +/*! PE - Parity Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) + +#define LPUART_CTRL_ILT_MASK (0x4U) +#define LPUART_CTRL_ILT_SHIFT (2U) +/*! ILT - Idle Line Type Select + * 0b0..After the start bit + * 0b1..After the stop bit + */ +#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) + +#define LPUART_CTRL_WAKE_MASK (0x8U) +#define LPUART_CTRL_WAKE_SHIFT (3U) +/*! WAKE - Receiver Wake-Up Method Select + * 0b0..Idle + * 0b1..Mark + */ +#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) + +#define LPUART_CTRL_M_MASK (0x10U) +#define LPUART_CTRL_M_SHIFT (4U) +/*! M - 9-Bit Or 8-Bit Mode Select + * 0b0..8-bit + * 0b1..9-bit + */ +#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) + +#define LPUART_CTRL_RSRC_MASK (0x20U) +#define LPUART_CTRL_RSRC_SHIFT (5U) +/*! RSRC - Receiver Source Select + * 0b0..Internal Loopback mode + * 0b1..Single-wire mode + */ +#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) + +#define LPUART_CTRL_DOZEEN_MASK (0x40U) +#define LPUART_CTRL_DOZEEN_SHIFT (6U) +/*! DOZEEN - Doze Mode + * 0b0..Enable + * 0b1..Disable + */ +#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) + +#define LPUART_CTRL_LOOPS_MASK (0x80U) +#define LPUART_CTRL_LOOPS_SHIFT (7U) +/*! LOOPS - Loop Mode Select + * 0b0..Normal operation: RXD and TXD use separate pins + * 0b1..Loop mode or Single-Wire mode + */ +#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) + +#define LPUART_CTRL_IDLECFG_MASK (0x700U) +#define LPUART_CTRL_IDLECFG_SHIFT (8U) +/*! IDLECFG - Idle Configuration + * 0b000..1 + * 0b001..2 + * 0b010..4 + * 0b011..8 + * 0b100..16 + * 0b101..32 + * 0b110..64 + * 0b111..128 + */ +#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) + +#define LPUART_CTRL_M7_MASK (0x800U) +#define LPUART_CTRL_M7_SHIFT (11U) +/*! M7 - 7-Bit Mode Select + * 0b0..8-bit to 10-bit + * 0b1..7-bit + */ +#define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) + +#define LPUART_CTRL_MA2IE_MASK (0x4000U) +#define LPUART_CTRL_MA2IE_SHIFT (14U) +/*! MA2IE - Match 2 (MA2F) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) + +#define LPUART_CTRL_MA1IE_MASK (0x8000U) +#define LPUART_CTRL_MA1IE_SHIFT (15U) +/*! MA1IE - Match 1 (MA1F) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) + +#define LPUART_CTRL_SBK_MASK (0x10000U) +#define LPUART_CTRL_SBK_SHIFT (16U) +/*! SBK - Send Break + * 0b0..Normal transmitter operation + * 0b1..Queue break character(s) to be sent + */ +#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) + +#define LPUART_CTRL_RWU_MASK (0x20000U) +#define LPUART_CTRL_RWU_SHIFT (17U) +/*! RWU - Receiver Wake-Up Control + * 0b0..Normal receiver operation + * 0b1..LPUART receiver in standby, waiting for a wake-up condition + */ +#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) + +#define LPUART_CTRL_RE_MASK (0x40000U) +#define LPUART_CTRL_RE_SHIFT (18U) +/*! RE - Receiver Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) + +#define LPUART_CTRL_TE_MASK (0x80000U) +#define LPUART_CTRL_TE_SHIFT (19U) +/*! TE - Transmitter Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) + +#define LPUART_CTRL_ILIE_MASK (0x100000U) +#define LPUART_CTRL_ILIE_SHIFT (20U) +/*! ILIE - Idle Line Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) + +#define LPUART_CTRL_RIE_MASK (0x200000U) +#define LPUART_CTRL_RIE_SHIFT (21U) +/*! RIE - Receiver Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) + +#define LPUART_CTRL_TCIE_MASK (0x400000U) +#define LPUART_CTRL_TCIE_SHIFT (22U) +/*! TCIE - Transmission Complete Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) + +#define LPUART_CTRL_TIE_MASK (0x800000U) +#define LPUART_CTRL_TIE_SHIFT (23U) +/*! TIE - Transmit Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) + +#define LPUART_CTRL_PEIE_MASK (0x1000000U) +#define LPUART_CTRL_PEIE_SHIFT (24U) +/*! PEIE - Parity Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) + +#define LPUART_CTRL_FEIE_MASK (0x2000000U) +#define LPUART_CTRL_FEIE_SHIFT (25U) +/*! FEIE - Framing Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) + +#define LPUART_CTRL_NEIE_MASK (0x4000000U) +#define LPUART_CTRL_NEIE_SHIFT (26U) +/*! NEIE - Noise Error Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) + +#define LPUART_CTRL_ORIE_MASK (0x8000000U) +#define LPUART_CTRL_ORIE_SHIFT (27U) +/*! ORIE - Overrun Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) + +#define LPUART_CTRL_TXINV_MASK (0x10000000U) +#define LPUART_CTRL_TXINV_SHIFT (28U) +/*! TXINV - Transmit Data Inversion + * 0b0..Not inverted + * 0b1..Inverted + */ +#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) + +#define LPUART_CTRL_TXDIR_MASK (0x20000000U) +#define LPUART_CTRL_TXDIR_SHIFT (29U) +/*! TXDIR - TXD Pin Direction in Single-Wire Mode + * 0b0..Input + * 0b1..Output + */ +#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) + +#define LPUART_CTRL_R9T8_MASK (0x40000000U) +#define LPUART_CTRL_R9T8_SHIFT (30U) +/*! R9T8 - Receive Bit 9 Transmit Bit 8 */ +#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) + +#define LPUART_CTRL_R8T9_MASK (0x80000000U) +#define LPUART_CTRL_R8T9_SHIFT (31U) +/*! R8T9 - Receive Bit 8 Transmit Bit 9 */ +#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) +/*! @} */ + +/*! @name DATA - Data */ +/*! @{ */ + +#define LPUART_DATA_R0T0_MASK (0x1U) +#define LPUART_DATA_R0T0_SHIFT (0U) +/*! R0T0 - Read receive FIFO bit 0 or write transmit FIFO bit 0 */ +#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) + +#define LPUART_DATA_R1T1_MASK (0x2U) +#define LPUART_DATA_R1T1_SHIFT (1U) +/*! R1T1 - Read receive FIFO bit 1 or write transmit FIFO bit 1 */ +#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) + +#define LPUART_DATA_R2T2_MASK (0x4U) +#define LPUART_DATA_R2T2_SHIFT (2U) +/*! R2T2 - Read receive FIFO bit 2 or write transmit FIFO bit 2 */ +#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) + +#define LPUART_DATA_R3T3_MASK (0x8U) +#define LPUART_DATA_R3T3_SHIFT (3U) +/*! R3T3 - Read receive FIFO bit 3 or write transmit FIFO bit 3 */ +#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) + +#define LPUART_DATA_R4T4_MASK (0x10U) +#define LPUART_DATA_R4T4_SHIFT (4U) +/*! R4T4 - Read receive FIFO bit 4 or write transmit FIFO bit 4 */ +#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) + +#define LPUART_DATA_R5T5_MASK (0x20U) +#define LPUART_DATA_R5T5_SHIFT (5U) +/*! R5T5 - Read receive FIFO bit 5 or write transmit FIFO bit 5 */ +#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) + +#define LPUART_DATA_R6T6_MASK (0x40U) +#define LPUART_DATA_R6T6_SHIFT (6U) +/*! R6T6 - Read receive FIFO bit 6 or write transmit FIFO bit 6 */ +#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) + +#define LPUART_DATA_R7T7_MASK (0x80U) +#define LPUART_DATA_R7T7_SHIFT (7U) +/*! R7T7 - Read receive FIFO bit 7 or write transmit FIFO bit 7 */ +#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) + +#define LPUART_DATA_R8T8_MASK (0x100U) +#define LPUART_DATA_R8T8_SHIFT (8U) +/*! R8T8 - Read receive FIFO bit 8 or write transmit FIFO bit 8 */ +#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) + +#define LPUART_DATA_R9T9_MASK (0x200U) +#define LPUART_DATA_R9T9_SHIFT (9U) +/*! R9T9 - Read receive FIFO bit 9 or write transmit FIFO bit 9 */ +#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) + +#define LPUART_DATA_LINBRK_MASK (0x400U) +#define LPUART_DATA_LINBRK_SHIFT (10U) +/*! LINBRK - LIN Break + * 0b0..Not detected + * 0b1..Detected + */ +#define LPUART_DATA_LINBRK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_LINBRK_SHIFT)) & LPUART_DATA_LINBRK_MASK) + +#define LPUART_DATA_IDLINE_MASK (0x800U) +#define LPUART_DATA_IDLINE_SHIFT (11U) +/*! IDLINE - Idle Line + * 0b0..Not idle + * 0b1..Idle + */ +#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) + +#define LPUART_DATA_RXEMPT_MASK (0x1000U) +#define LPUART_DATA_RXEMPT_SHIFT (12U) +/*! RXEMPT - Receive Buffer Empty + * 0b0..Valid data + * 0b1..Invalid data and empty + */ +#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) + +#define LPUART_DATA_FRETSC_MASK (0x2000U) +#define LPUART_DATA_FRETSC_SHIFT (13U) +/*! FRETSC - Frame Error Transmit Special Character + * 0b0..Received without a frame error on reads or transmits a normal character on writes + * 0b1..Received with a frame error on reads or transmits an idle or break character on writes + */ +#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) + +#define LPUART_DATA_PARITYE_MASK (0x4000U) +#define LPUART_DATA_PARITYE_SHIFT (14U) +/*! PARITYE - Parity Error + * 0b0..Received without a parity error + * 0b1..Received with a parity error + */ +#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) + +#define LPUART_DATA_NOISY_MASK (0x8000U) +#define LPUART_DATA_NOISY_SHIFT (15U) +/*! NOISY - Noisy Data Received + * 0b0..Received without noise + * 0b1..Received with noise + */ +#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) +/*! @} */ + +/*! @name MATCH - Match Address */ +/*! @{ */ + +#define LPUART_MATCH_MA1_MASK (0x3FFU) +#define LPUART_MATCH_MA1_SHIFT (0U) +/*! MA1 - Match Address 1 */ +#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) + +#define LPUART_MATCH_MA2_MASK (0x3FF0000U) +#define LPUART_MATCH_MA2_SHIFT (16U) +/*! MA2 - Match Address 2 */ +#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) +/*! @} */ + +/*! @name MODIR - MODEM IrDA */ +/*! @{ */ + +#define LPUART_MODIR_TXCTSE_MASK (0x1U) +#define LPUART_MODIR_TXCTSE_SHIFT (0U) +/*! TXCTSE - Transmitter CTS Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) + +#define LPUART_MODIR_TXRTSE_MASK (0x2U) +#define LPUART_MODIR_TXRTSE_SHIFT (1U) +/*! TXRTSE - Transmitter RTS Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) + +#define LPUART_MODIR_TXRTSPOL_MASK (0x4U) +#define LPUART_MODIR_TXRTSPOL_SHIFT (2U) +/*! TXRTSPOL - Transmitter RTS Polarity + * 0b0..Active low + * 0b1..Active high + */ +#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) + +#define LPUART_MODIR_RXRTSE_MASK (0x8U) +#define LPUART_MODIR_RXRTSE_SHIFT (3U) +/*! RXRTSE - Receiver RTS Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) + +#define LPUART_MODIR_TXCTSC_MASK (0x10U) +#define LPUART_MODIR_TXCTSC_SHIFT (4U) +/*! TXCTSC - Transmit CTS Configuration + * 0b0..Sampled at the start of each character + * 0b1..Sampled when the transmitter is idle + */ +#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) + +#define LPUART_MODIR_TXCTSSRC_MASK (0x20U) +#define LPUART_MODIR_TXCTSSRC_SHIFT (5U) +/*! TXCTSSRC - Transmit CTS Source + * 0b0..The CTS_B pin + * 0b1..An internal connection to the receiver address match result + */ +#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) + +#define LPUART_MODIR_RTSWATER_MASK (0x300U) +#define LPUART_MODIR_RTSWATER_SHIFT (8U) +/*! RTSWATER - Receive RTS Configuration */ +#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) + +#define LPUART_MODIR_TNP_MASK (0x30000U) +#define LPUART_MODIR_TNP_SHIFT (16U) +/*! TNP - Transmitter Narrow Pulse + * 0b00..1 / OSR + * 0b01..2 / OSR + * 0b10..3 / OSR + * 0b11..4 / OSR + */ +#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) + +#define LPUART_MODIR_IREN_MASK (0x40000U) +#define LPUART_MODIR_IREN_SHIFT (18U) +/*! IREN - IR Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) +/*! @} */ + +/*! @name FIFO - FIFO */ +/*! @{ */ + +#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) +#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) +/*! RXFIFOSIZE - Receive FIFO Buffer Depth + * 0b000..1 + * 0b001..4 + * 0b010..8 + * 0b011..16 + * 0b100..32 + * 0b101..64 + * 0b110..128 + * 0b111..256 + */ +#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) + +#define LPUART_FIFO_RXFE_MASK (0x8U) +#define LPUART_FIFO_RXFE_SHIFT (3U) +/*! RXFE - Receive FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) + +#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) +#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) +/*! TXFIFOSIZE - Transmit FIFO Buffer Depth + * 0b000..1 + * 0b001..4 + * 0b010..8 + * 0b011..16 + * 0b100..32 + * 0b101..64 + * 0b110..128 + * 0b111..256 + */ +#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) + +#define LPUART_FIFO_TXFE_MASK (0x80U) +#define LPUART_FIFO_TXFE_SHIFT (7U) +/*! TXFE - Transmit FIFO Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) + +#define LPUART_FIFO_RXUFE_MASK (0x100U) +#define LPUART_FIFO_RXUFE_SHIFT (8U) +/*! RXUFE - Receive FIFO Underflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) + +#define LPUART_FIFO_TXOFE_MASK (0x200U) +#define LPUART_FIFO_TXOFE_SHIFT (9U) +/*! TXOFE - Transmit FIFO Overflow Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) + +#define LPUART_FIFO_RXIDEN_MASK (0x1C00U) +#define LPUART_FIFO_RXIDEN_SHIFT (10U) +/*! RXIDEN - Receiver Idle Empty Enable + * 0b000..Disable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle + * 0b001..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character + * 0b010..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters + * 0b011..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters + * 0b100..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters + * 0b101..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters + * 0b110..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters + * 0b111..Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters + */ +#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) + +#define LPUART_FIFO_RXFLUSH_MASK (0x4000U) +#define LPUART_FIFO_RXFLUSH_SHIFT (14U) +/*! RXFLUSH - Receive FIFO Flush + * 0b0..No effect + * 0b1..All data flushed out + */ +#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) + +#define LPUART_FIFO_TXFLUSH_MASK (0x8000U) +#define LPUART_FIFO_TXFLUSH_SHIFT (15U) +/*! TXFLUSH - Transmit FIFO Flush + * 0b0..No effect + * 0b1..All data flushed out + */ +#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) + +#define LPUART_FIFO_RXUF_MASK (0x10000U) +#define LPUART_FIFO_RXUF_SHIFT (16U) +/*! RXUF - Receiver FIFO Underflow Flag + * 0b0..No underflow + * 0b1..Underflow + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) + +#define LPUART_FIFO_TXOF_MASK (0x20000U) +#define LPUART_FIFO_TXOF_SHIFT (17U) +/*! TXOF - Transmitter FIFO Overflow Flag + * 0b0..No overflow + * 0b1..Overflow + * 0b0..No effect + * 0b1..Clear the flag + */ +#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) + +#define LPUART_FIFO_RXEMPT_MASK (0x400000U) +#define LPUART_FIFO_RXEMPT_SHIFT (22U) +/*! RXEMPT - Receive FIFO Or Buffer Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) + +#define LPUART_FIFO_TXEMPT_MASK (0x800000U) +#define LPUART_FIFO_TXEMPT_SHIFT (23U) +/*! TXEMPT - Transmit FIFO Or Buffer Empty + * 0b0..Not empty + * 0b1..Empty + */ +#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) +/*! @} */ + +/*! @name WATER - Watermark */ +/*! @{ */ + +#define LPUART_WATER_TXWATER_MASK (0x3U) +#define LPUART_WATER_TXWATER_SHIFT (0U) +/*! TXWATER - Transmit Watermark */ +#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) + +#define LPUART_WATER_TXCOUNT_MASK (0x700U) +#define LPUART_WATER_TXCOUNT_SHIFT (8U) +/*! TXCOUNT - Transmit Counter */ +#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) + +#define LPUART_WATER_RXWATER_MASK (0x30000U) +#define LPUART_WATER_RXWATER_SHIFT (16U) +/*! RXWATER - Receive Watermark */ +#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) + +#define LPUART_WATER_RXCOUNT_MASK (0x7000000U) +#define LPUART_WATER_RXCOUNT_SHIFT (24U) +/*! RXCOUNT - Receive Counter */ +#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) +/*! @} */ + +/*! @name DATARO - Data Read-Only */ +/*! @{ */ + +#define LPUART_DATARO_DATA_MASK (0xFFFFU) +#define LPUART_DATARO_DATA_SHIFT (0U) +/*! DATA - Receive Data */ +#define LPUART_DATARO_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATARO_DATA_SHIFT)) & LPUART_DATARO_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group LPUART_Register_Masks */ + + +/* LPUART - Peripheral instance base addresses */ +/** Peripheral LPUART0 base address */ +#define LPUART0_BASE (0x4009F000u) +/** Peripheral LPUART0 base pointer */ +#define LPUART0 ((LPUART_Type *)LPUART0_BASE) +/** Peripheral LPUART1 base address */ +#define LPUART1_BASE (0x400A0000u) +/** Peripheral LPUART1 base pointer */ +#define LPUART1 ((LPUART_Type *)LPUART1_BASE) +/** Peripheral LPUART2 base address */ +#define LPUART2_BASE (0x400A1000u) +/** Peripheral LPUART2 base pointer */ +#define LPUART2 ((LPUART_Type *)LPUART2_BASE) +/** Peripheral LPUART3 base address */ +#define LPUART3_BASE (0x400A2000u) +/** Peripheral LPUART3 base pointer */ +#define LPUART3 ((LPUART_Type *)LPUART3_BASE) +/** Peripheral LPUART4 base address */ +#define LPUART4_BASE (0x400A3000u) +/** Peripheral LPUART4 base pointer */ +#define LPUART4 ((LPUART_Type *)LPUART4_BASE) +/** Array initializer of LPUART peripheral base addresses */ +#define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE } +/** Array initializer of LPUART peripheral base pointers */ +#define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2, LPUART3, LPUART4 } +/** Interrupt vectors for the LPUART peripheral type */ +#define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn } +#define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn } + +/*! + * @} + */ /* end of group LPUART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MRCC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRCC_Peripheral_Access_Layer MRCC Peripheral Access Layer + * @{ + */ + +/** MRCC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MRCC_GLB_RST0; /**< Peripheral Reset Control 0, offset: 0x0 */ + __O uint32_t MRCC_GLB_RST0_SET; /**< Peripheral Reset Control Set 0, offset: 0x4 */ + __O uint32_t MRCC_GLB_RST0_CLR; /**< Peripheral Reset Control Clear 0, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t MRCC_GLB_RST1; /**< Peripheral Reset Control 1, offset: 0x10 */ + __O uint32_t MRCC_GLB_RST1_SET; /**< Peripheral Reset Control Set 1, offset: 0x14 */ + __O uint32_t MRCC_GLB_RST1_CLR; /**< Peripheral Reset Control Clear 1, offset: 0x18 */ + uint8_t RESERVED_1[36]; + __IO uint32_t MRCC_GLB_CC0; /**< AHB Clock Control 0, offset: 0x40 */ + __O uint32_t MRCC_GLB_CC0_SET; /**< AHB Clock Control Set 0, offset: 0x44 */ + __O uint32_t MRCC_GLB_CC0_CLR; /**< AHB Clock Control Clear 0, offset: 0x48 */ + uint8_t RESERVED_2[4]; + __IO uint32_t MRCC_GLB_CC1; /**< AHB Clock Control 1, offset: 0x50 */ + __O uint32_t MRCC_GLB_CC_SET[1]; /**< AHB Clock Control Set 1, array offset: 0x54, array step: 0x4 */ + __O uint32_t MRCC_GLB_CC_CLR[1]; /**< AHB Clock Control Clear 1, array offset: 0x58, array step: 0x4 */ + uint8_t RESERVED_3[36]; + __IO uint32_t MRCC_GLB_ACC0; /**< Control Automatic Clock Gating 0, offset: 0x80 */ + __IO uint32_t MRCC_GLB_ACC1; /**< Control Automatic Clock Gating 1, offset: 0x84 */ + uint8_t RESERVED_4[24]; + __IO uint32_t MRCC_I3C0_FCLK_CLKSEL; /**< I3C0_FCLK clock selection control, offset: 0xA0 */ + __IO uint32_t MRCC_I3C0_FCLK_CLKDIV; /**< I3C0_FCLK clock divider control, offset: 0xA4 */ + __IO uint32_t MRCC_CTIMER0_CLKSEL; /**< CTIMER0 clock selection control, offset: 0xA8 */ + __IO uint32_t MRCC_CTIMER0_CLKDIV; /**< CTIMER0 clock divider control, offset: 0xAC */ + __IO uint32_t MRCC_CTIMER1_CLKSEL; /**< CTIMER1 clock selection control, offset: 0xB0 */ + __IO uint32_t MRCC_CTIMER1_CLKDIV; /**< CTIMER1 clock divider control, offset: 0xB4 */ + __IO uint32_t MRCC_CTIMER2_CLKSEL; /**< CTIMER2 clock selection control, offset: 0xB8 */ + __IO uint32_t MRCC_CTIMER2_CLKDIV; /**< CTIMER2 clock divider control, offset: 0xBC */ + __IO uint32_t MRCC_CTIMER3_CLKSEL; /**< CTIMER3 clock selection control, offset: 0xC0 */ + __IO uint32_t MRCC_CTIMER3_CLKDIV; /**< CTIMER3 clock divider control, offset: 0xC4 */ + __IO uint32_t MRCC_CTIMER4_CLKSEL; /**< CTIMER4 clock selection control, offset: 0xC8 */ + __IO uint32_t MRCC_CTIMER4_CLKDIV; /**< CTIMER4 clock divider control, offset: 0xCC */ + uint8_t RESERVED_5[4]; + __IO uint32_t MRCC_WWDT0_CLKDIV; /**< WWDT0 clock divider control, offset: 0xD4 */ + __IO uint32_t MRCC_FLEXIO0_CLKSEL; /**< FLEXIO0 clock selection control, offset: 0xD8 */ + __IO uint32_t MRCC_FLEXIO0_CLKDIV; /**< FLEXIO0 clock divider control, offset: 0xDC */ + __IO uint32_t MRCC_LPI2C0_CLKSEL; /**< LPI2C0 clock selection control, offset: 0xE0 */ + __IO uint32_t MRCC_LPI2C0_CLKDIV; /**< LPI2C0 clock divider control, offset: 0xE4 */ + __IO uint32_t MRCC_LPI2C1_CLKSEL; /**< LPI2C1 clock selection control, offset: 0xE8 */ + __IO uint32_t MRCC_LPI2C1_CLKDIV; /**< LPI2C1 clock divider control, offset: 0xEC */ + __IO uint32_t MRCC_LPSPI0_CLKSEL; /**< LPSPI0 clock selection control, offset: 0xF0 */ + __IO uint32_t MRCC_LPSPI0_CLKDIV; /**< LPSPI0 clock divider control, offset: 0xF4 */ + __IO uint32_t MRCC_LPSPI1_CLKSEL; /**< LPSPI1 clock selection control, offset: 0xF8 */ + __IO uint32_t MRCC_LPSPI1_CLKDIV; /**< LPSPI1 clock divider control, offset: 0xFC */ + __IO uint32_t MRCC_LPUART0_CLKSEL; /**< LPUART0 clock selection control, offset: 0x100 */ + __IO uint32_t MRCC_LPUART0_CLKDIV; /**< LPUART0 clock divider control, offset: 0x104 */ + __IO uint32_t MRCC_LPUART1_CLKSEL; /**< LPUART1 clock selection control, offset: 0x108 */ + __IO uint32_t MRCC_LPUART1_CLKDIV; /**< LPUART1 clock divider control, offset: 0x10C */ + __IO uint32_t MRCC_LPUART2_CLKSEL; /**< LPUART2 clock selection control, offset: 0x110 */ + __IO uint32_t MRCC_LPUART2_CLKDIV; /**< LPUART2 clock divider control, offset: 0x114 */ + __IO uint32_t MRCC_LPUART3_CLKSEL; /**< LPUART3 clock selection control, offset: 0x118 */ + __IO uint32_t MRCC_LPUART3_CLKDIV; /**< LPUART3 clock divider control, offset: 0x11C */ + __IO uint32_t MRCC_LPUART4_CLKSEL; /**< LPUART4 clock selection control, offset: 0x120 */ + __IO uint32_t MRCC_LPUART4_CLKDIV; /**< LPUART4 clock divider control, offset: 0x124 */ + __IO uint32_t MRCC_USB0_CLKSEL; /**< USB0 clock selection control, offset: 0x128 */ + uint8_t RESERVED_6[4]; + __IO uint32_t MRCC_LPTMR0_CLKSEL; /**< LPTMR0 clock selection control, offset: 0x130 */ + __IO uint32_t MRCC_LPTMR0_CLKDIV; /**< LPTMR0 clock divider control, offset: 0x134 */ + __IO uint32_t MRCC_OSTIMER0_CLKSEL; /**< OSTIMER0 clock selection control, offset: 0x138 */ + uint8_t RESERVED_7[4]; + __IO uint32_t MRCC_ADC0_CLKSEL; /**< ADC0 clock selection control, offset: 0x140 */ + __IO uint32_t MRCC_ADC0_CLKDIV; /**< ADC0 clock divider control, offset: 0x144 */ + __IO uint32_t MRCC_ADC1_CLKSEL; /**< ADC1 clock selection control, offset: 0x148 */ + __IO uint32_t MRCC_ADC1_CLKDIV; /**< ADC1 clock divider control, offset: 0x14C */ + uint8_t RESERVED_8[4]; + __IO uint32_t MRCC_CMP0_FUNC_CLKDIV; /**< CMP0_FUNC clock divider control, offset: 0x154 */ + __IO uint32_t MRCC_CMP0_RR_CLKSEL; /**< CMP0_RR clock selection control, offset: 0x158 */ + __IO uint32_t MRCC_CMP0_RR_CLKDIV; /**< CMP0_RR clock divider control, offset: 0x15C */ + uint8_t RESERVED_9[4]; + __IO uint32_t MRCC_CMP1_FUNC_CLKDIV; /**< CMP1_FUNC clock divider control, offset: 0x164 */ + __IO uint32_t MRCC_CMP1_RR_CLKSEL; /**< CMP1_RR clock selection control, offset: 0x168 */ + __IO uint32_t MRCC_CMP1_RR_CLKDIV; /**< CMP1_RR clock divider control, offset: 0x16C */ + __IO uint32_t MRCC_DAC0_CLKSEL; /**< DAC0 clock selection control, offset: 0x170 */ + __IO uint32_t MRCC_DAC0_CLKDIV; /**< DAC0 clock divider control, offset: 0x174 */ + __IO uint32_t MRCC_FLEXCAN0_CLKSEL; /**< FLEXCAN0 clock selection control, offset: 0x178 */ + __IO uint32_t MRCC_FLEXCAN0_CLKDIV; /**< FLEXCAN0 clock divider control, offset: 0x17C */ + __IO uint32_t MRCC_LPI2C2_CLKSEL; /**< LPI2C2 clock selection control, offset: 0x180 */ + __IO uint32_t MRCC_LPI2C2_CLKDIV; /**< LPI2C2 clock divider control, offset: 0x184 */ + __IO uint32_t MRCC_LPI2C3_CLKSEL; /**< LPI2C3 clock selection control, offset: 0x188 */ + __IO uint32_t MRCC_LPI2C3_CLKDIV; /**< LPI2C3 clock divider control, offset: 0x18C */ + __IO uint32_t MRCC_DBG_TRACE_CLKSEL; /**< DBG_TRACE clock selection control, offset: 0x190 */ + __IO uint32_t MRCC_DBG_TRACE_CLKDIV; /**< DBG_TRACE clock divider control, offset: 0x194 */ + __IO uint32_t MRCC_CLKOUT_CLKSEL; /**< CLKOUT clock selection control, offset: 0x198 */ + __IO uint32_t MRCC_CLKOUT_CLKDIV; /**< CLKOUT clock divider control, offset: 0x19C */ + __IO uint32_t MRCC_SYSTICK_CLKSEL; /**< SYSTICK clock selection control, offset: 0x1A0 */ + __IO uint32_t MRCC_SYSTICK_CLKDIV; /**< SYSTICK clock divider control, offset: 0x1A4 */ + uint8_t RESERVED_10[4]; + __IO uint32_t MRCC_FRO_HF_DIV_CLKDIV; /**< FRO_HF_DIV clock divider control, offset: 0x1AC */ +} MRCC_Type; + +/* ---------------------------------------------------------------------------- + -- MRCC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRCC_Register_Masks MRCC Register Masks + * @{ + */ + +/*! @name MRCC_GLB_RST0 - Peripheral Reset Control 0 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_RST0_INPUTMUX0_MASK (0x1U) +#define MRCC_MRCC_GLB_RST0_INPUTMUX0_SHIFT (0U) +/*! INPUTMUX0 - INPUTMUX0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_INPUTMUX0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_INPUTMUX0_SHIFT)) & MRCC_MRCC_GLB_RST0_INPUTMUX0_MASK) + +#define MRCC_MRCC_GLB_RST0_I3C0_MASK (0x2U) +#define MRCC_MRCC_GLB_RST0_I3C0_SHIFT (1U) +/*! I3C0 - I3C0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_I3C0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_I3C0_SHIFT)) & MRCC_MRCC_GLB_RST0_I3C0_MASK) + +#define MRCC_MRCC_GLB_RST0_CTIMER0_MASK (0x4U) +#define MRCC_MRCC_GLB_RST0_CTIMER0_SHIFT (2U) +/*! CTIMER0 - CTIMER0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CTIMER0_SHIFT)) & MRCC_MRCC_GLB_RST0_CTIMER0_MASK) + +#define MRCC_MRCC_GLB_RST0_CTIMER1_MASK (0x8U) +#define MRCC_MRCC_GLB_RST0_CTIMER1_SHIFT (3U) +/*! CTIMER1 - CTIMER1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CTIMER1_SHIFT)) & MRCC_MRCC_GLB_RST0_CTIMER1_MASK) + +#define MRCC_MRCC_GLB_RST0_CTIMER2_MASK (0x10U) +#define MRCC_MRCC_GLB_RST0_CTIMER2_SHIFT (4U) +/*! CTIMER2 - CTIMER2 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CTIMER2_SHIFT)) & MRCC_MRCC_GLB_RST0_CTIMER2_MASK) + +#define MRCC_MRCC_GLB_RST0_CTIMER3_MASK (0x20U) +#define MRCC_MRCC_GLB_RST0_CTIMER3_SHIFT (5U) +/*! CTIMER3 - CTIMER3 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CTIMER3_SHIFT)) & MRCC_MRCC_GLB_RST0_CTIMER3_MASK) + +#define MRCC_MRCC_GLB_RST0_CTIMER4_MASK (0x40U) +#define MRCC_MRCC_GLB_RST0_CTIMER4_SHIFT (6U) +/*! CTIMER4 - CTIMER4 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CTIMER4_SHIFT)) & MRCC_MRCC_GLB_RST0_CTIMER4_MASK) + +#define MRCC_MRCC_GLB_RST0_FREQME_MASK (0x80U) +#define MRCC_MRCC_GLB_RST0_FREQME_SHIFT (7U) +/*! FREQME - FREQME + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_FREQME(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_FREQME_SHIFT)) & MRCC_MRCC_GLB_RST0_FREQME_MASK) + +#define MRCC_MRCC_GLB_RST0_UTICK0_MASK (0x100U) +#define MRCC_MRCC_GLB_RST0_UTICK0_SHIFT (8U) +/*! UTICK0 - UTICK0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_UTICK0_SHIFT)) & MRCC_MRCC_GLB_RST0_UTICK0_MASK) + +#define MRCC_MRCC_GLB_RST0_DMA_MASK (0x400U) +#define MRCC_MRCC_GLB_RST0_DMA_SHIFT (10U) +/*! DMA - DMA + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_DMA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_DMA_SHIFT)) & MRCC_MRCC_GLB_RST0_DMA_MASK) + +#define MRCC_MRCC_GLB_RST0_AOI0_MASK (0x800U) +#define MRCC_MRCC_GLB_RST0_AOI0_SHIFT (11U) +/*! AOI0 - AOI0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_AOI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_AOI0_SHIFT)) & MRCC_MRCC_GLB_RST0_AOI0_MASK) + +#define MRCC_MRCC_GLB_RST0_CRC0_MASK (0x1000U) +#define MRCC_MRCC_GLB_RST0_CRC0_SHIFT (12U) +/*! CRC0 - CRC0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_CRC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CRC0_SHIFT)) & MRCC_MRCC_GLB_RST0_CRC0_MASK) + +#define MRCC_MRCC_GLB_RST0_EIM0_MASK (0x2000U) +#define MRCC_MRCC_GLB_RST0_EIM0_SHIFT (13U) +/*! EIM0 - EIM0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_EIM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_EIM0_SHIFT)) & MRCC_MRCC_GLB_RST0_EIM0_MASK) + +#define MRCC_MRCC_GLB_RST0_ERM0_MASK (0x4000U) +#define MRCC_MRCC_GLB_RST0_ERM0_SHIFT (14U) +/*! ERM0 - ERM0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_ERM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_ERM0_SHIFT)) & MRCC_MRCC_GLB_RST0_ERM0_MASK) + +#define MRCC_MRCC_GLB_RST0_AOI1_MASK (0x10000U) +#define MRCC_MRCC_GLB_RST0_AOI1_SHIFT (16U) +/*! AOI1 - AOI1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_AOI1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_AOI1_SHIFT)) & MRCC_MRCC_GLB_RST0_AOI1_MASK) + +#define MRCC_MRCC_GLB_RST0_FLEXIO0_MASK (0x20000U) +#define MRCC_MRCC_GLB_RST0_FLEXIO0_SHIFT (17U) +/*! FLEXIO0 - FLEXIO0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_FLEXIO0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_FLEXIO0_SHIFT)) & MRCC_MRCC_GLB_RST0_FLEXIO0_MASK) + +#define MRCC_MRCC_GLB_RST0_LPI2C0_MASK (0x40000U) +#define MRCC_MRCC_GLB_RST0_LPI2C0_SHIFT (18U) +/*! LPI2C0 - LPI2C0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPI2C0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPI2C0_SHIFT)) & MRCC_MRCC_GLB_RST0_LPI2C0_MASK) + +#define MRCC_MRCC_GLB_RST0_LPI2C1_MASK (0x80000U) +#define MRCC_MRCC_GLB_RST0_LPI2C1_SHIFT (19U) +/*! LPI2C1 - LPI2C1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPI2C1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPI2C1_SHIFT)) & MRCC_MRCC_GLB_RST0_LPI2C1_MASK) + +#define MRCC_MRCC_GLB_RST0_LPSPI0_MASK (0x100000U) +#define MRCC_MRCC_GLB_RST0_LPSPI0_SHIFT (20U) +/*! LPSPI0 - LPSPI0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPSPI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPSPI0_SHIFT)) & MRCC_MRCC_GLB_RST0_LPSPI0_MASK) + +#define MRCC_MRCC_GLB_RST0_LPSPI1_MASK (0x200000U) +#define MRCC_MRCC_GLB_RST0_LPSPI1_SHIFT (21U) +/*! LPSPI1 - LPSPI1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPSPI1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPSPI1_SHIFT)) & MRCC_MRCC_GLB_RST0_LPSPI1_MASK) + +#define MRCC_MRCC_GLB_RST0_LPUART0_MASK (0x400000U) +#define MRCC_MRCC_GLB_RST0_LPUART0_SHIFT (22U) +/*! LPUART0 - LPUART0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPUART0_SHIFT)) & MRCC_MRCC_GLB_RST0_LPUART0_MASK) + +#define MRCC_MRCC_GLB_RST0_LPUART1_MASK (0x800000U) +#define MRCC_MRCC_GLB_RST0_LPUART1_SHIFT (23U) +/*! LPUART1 - LPUART1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPUART1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPUART1_SHIFT)) & MRCC_MRCC_GLB_RST0_LPUART1_MASK) + +#define MRCC_MRCC_GLB_RST0_LPUART2_MASK (0x1000000U) +#define MRCC_MRCC_GLB_RST0_LPUART2_SHIFT (24U) +/*! LPUART2 - LPUART2 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPUART2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPUART2_SHIFT)) & MRCC_MRCC_GLB_RST0_LPUART2_MASK) + +#define MRCC_MRCC_GLB_RST0_LPUART3_MASK (0x2000000U) +#define MRCC_MRCC_GLB_RST0_LPUART3_SHIFT (25U) +/*! LPUART3 - LPUART3 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPUART3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPUART3_SHIFT)) & MRCC_MRCC_GLB_RST0_LPUART3_MASK) + +#define MRCC_MRCC_GLB_RST0_LPUART4_MASK (0x4000000U) +#define MRCC_MRCC_GLB_RST0_LPUART4_SHIFT (26U) +/*! LPUART4 - LPUART4 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_LPUART4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_LPUART4_SHIFT)) & MRCC_MRCC_GLB_RST0_LPUART4_MASK) + +#define MRCC_MRCC_GLB_RST0_USB0_MASK (0x8000000U) +#define MRCC_MRCC_GLB_RST0_USB0_SHIFT (27U) +/*! USB0 - USB0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_USB0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_USB0_SHIFT)) & MRCC_MRCC_GLB_RST0_USB0_MASK) + +#define MRCC_MRCC_GLB_RST0_QDC0_MASK (0x10000000U) +#define MRCC_MRCC_GLB_RST0_QDC0_SHIFT (28U) +/*! QDC0 - QDC0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_QDC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_QDC0_SHIFT)) & MRCC_MRCC_GLB_RST0_QDC0_MASK) + +#define MRCC_MRCC_GLB_RST0_QDC1_MASK (0x20000000U) +#define MRCC_MRCC_GLB_RST0_QDC1_SHIFT (29U) +/*! QDC1 - QDC1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_QDC1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_QDC1_SHIFT)) & MRCC_MRCC_GLB_RST0_QDC1_MASK) + +#define MRCC_MRCC_GLB_RST0_FLEXPWM0_MASK (0x40000000U) +#define MRCC_MRCC_GLB_RST0_FLEXPWM0_SHIFT (30U) +/*! FLEXPWM0 - FLEXPWM0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_FLEXPWM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_FLEXPWM0_SHIFT)) & MRCC_MRCC_GLB_RST0_FLEXPWM0_MASK) + +#define MRCC_MRCC_GLB_RST0_FLEXPWM1_MASK (0x80000000U) +#define MRCC_MRCC_GLB_RST0_FLEXPWM1_SHIFT (31U) +/*! FLEXPWM1 - FLEXPWM1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST0_FLEXPWM1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_FLEXPWM1_SHIFT)) & MRCC_MRCC_GLB_RST0_FLEXPWM1_MASK) +/*! @} */ + +/*! @name MRCC_GLB_RST0_SET - Peripheral Reset Control Set 0 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_RST0_SET_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_RST0_SET_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */ +#define MRCC_MRCC_GLB_RST0_SET_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_RST0_SET_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_RST0_CLR - Peripheral Reset Control Clear 0 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_RST0_CLR_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_RST0_CLR_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */ +#define MRCC_MRCC_GLB_RST0_CLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST0_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_RST0_CLR_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_RST1 - Peripheral Reset Control 1 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_RST1_OSTIMER0_MASK (0x1U) +#define MRCC_MRCC_GLB_RST1_OSTIMER0_SHIFT (0U) +/*! OSTIMER0 - OSTIMER0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_OSTIMER0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_OSTIMER0_SHIFT)) & MRCC_MRCC_GLB_RST1_OSTIMER0_MASK) + +#define MRCC_MRCC_GLB_RST1_ADC0_MASK (0x2U) +#define MRCC_MRCC_GLB_RST1_ADC0_SHIFT (1U) +/*! ADC0 - ADC0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_ADC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_ADC0_SHIFT)) & MRCC_MRCC_GLB_RST1_ADC0_MASK) + +#define MRCC_MRCC_GLB_RST1_ADC1_MASK (0x4U) +#define MRCC_MRCC_GLB_RST1_ADC1_SHIFT (2U) +/*! ADC1 - ADC1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_ADC1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_ADC1_SHIFT)) & MRCC_MRCC_GLB_RST1_ADC1_MASK) + +#define MRCC_MRCC_GLB_RST1_CMP1_MASK (0x10U) +#define MRCC_MRCC_GLB_RST1_CMP1_SHIFT (4U) +/*! CMP1 - CMP1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_CMP1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_CMP1_SHIFT)) & MRCC_MRCC_GLB_RST1_CMP1_MASK) + +#define MRCC_MRCC_GLB_RST1_DAC0_MASK (0x20U) +#define MRCC_MRCC_GLB_RST1_DAC0_SHIFT (5U) +/*! DAC0 - DAC0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_DAC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_DAC0_SHIFT)) & MRCC_MRCC_GLB_RST1_DAC0_MASK) + +#define MRCC_MRCC_GLB_RST1_OPAMP0_MASK (0x40U) +#define MRCC_MRCC_GLB_RST1_OPAMP0_SHIFT (6U) +/*! OPAMP0 - OPAMP0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_OPAMP0_SHIFT)) & MRCC_MRCC_GLB_RST1_OPAMP0_MASK) + +#define MRCC_MRCC_GLB_RST1_PORT0_MASK (0x80U) +#define MRCC_MRCC_GLB_RST1_PORT0_SHIFT (7U) +/*! PORT0 - PORT0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_PORT0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_PORT0_SHIFT)) & MRCC_MRCC_GLB_RST1_PORT0_MASK) + +#define MRCC_MRCC_GLB_RST1_PORT1_MASK (0x100U) +#define MRCC_MRCC_GLB_RST1_PORT1_SHIFT (8U) +/*! PORT1 - PORT1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_PORT1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_PORT1_SHIFT)) & MRCC_MRCC_GLB_RST1_PORT1_MASK) + +#define MRCC_MRCC_GLB_RST1_PORT2_MASK (0x200U) +#define MRCC_MRCC_GLB_RST1_PORT2_SHIFT (9U) +/*! PORT2 - PORT2 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_PORT2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_PORT2_SHIFT)) & MRCC_MRCC_GLB_RST1_PORT2_MASK) + +#define MRCC_MRCC_GLB_RST1_PORT3_MASK (0x400U) +#define MRCC_MRCC_GLB_RST1_PORT3_SHIFT (10U) +/*! PORT3 - PORT3 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_PORT3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_PORT3_SHIFT)) & MRCC_MRCC_GLB_RST1_PORT3_MASK) + +#define MRCC_MRCC_GLB_RST1_PORT4_MASK (0x800U) +#define MRCC_MRCC_GLB_RST1_PORT4_SHIFT (11U) +/*! PORT4 - PORT4 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_PORT4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_PORT4_SHIFT)) & MRCC_MRCC_GLB_RST1_PORT4_MASK) + +#define MRCC_MRCC_GLB_RST1_FLEXCAN0_MASK (0x1000U) +#define MRCC_MRCC_GLB_RST1_FLEXCAN0_SHIFT (12U) +/*! FLEXCAN0 - FLEXCAN0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_FLEXCAN0_SHIFT)) & MRCC_MRCC_GLB_RST1_FLEXCAN0_MASK) + +#define MRCC_MRCC_GLB_RST1_LPI2C2_MASK (0x2000U) +#define MRCC_MRCC_GLB_RST1_LPI2C2_SHIFT (13U) +/*! LPI2C2 - LPI2C2 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_LPI2C2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_LPI2C2_SHIFT)) & MRCC_MRCC_GLB_RST1_LPI2C2_MASK) + +#define MRCC_MRCC_GLB_RST1_LPI2C3_MASK (0x4000U) +#define MRCC_MRCC_GLB_RST1_LPI2C3_SHIFT (14U) +/*! LPI2C3 - LPI2C3 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_LPI2C3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_LPI2C3_SHIFT)) & MRCC_MRCC_GLB_RST1_LPI2C3_MASK) + +#define MRCC_MRCC_GLB_RST1_GPIO0_MASK (0x100000U) +#define MRCC_MRCC_GLB_RST1_GPIO0_SHIFT (20U) +/*! GPIO0 - GPIO0 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_GPIO0_SHIFT)) & MRCC_MRCC_GLB_RST1_GPIO0_MASK) + +#define MRCC_MRCC_GLB_RST1_GPIO1_MASK (0x200000U) +#define MRCC_MRCC_GLB_RST1_GPIO1_SHIFT (21U) +/*! GPIO1 - GPIO1 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_GPIO1_SHIFT)) & MRCC_MRCC_GLB_RST1_GPIO1_MASK) + +#define MRCC_MRCC_GLB_RST1_GPIO2_MASK (0x400000U) +#define MRCC_MRCC_GLB_RST1_GPIO2_SHIFT (22U) +/*! GPIO2 - GPIO2 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_GPIO2_SHIFT)) & MRCC_MRCC_GLB_RST1_GPIO2_MASK) + +#define MRCC_MRCC_GLB_RST1_GPIO3_MASK (0x800000U) +#define MRCC_MRCC_GLB_RST1_GPIO3_SHIFT (23U) +/*! GPIO3 - GPIO3 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_GPIO3_SHIFT)) & MRCC_MRCC_GLB_RST1_GPIO3_MASK) + +#define MRCC_MRCC_GLB_RST1_GPIO4_MASK (0x1000000U) +#define MRCC_MRCC_GLB_RST1_GPIO4_SHIFT (24U) +/*! GPIO4 - GPIO4 + * 0b0..Peripheral is held in reset + * 0b1..Peripheral is released from reset + */ +#define MRCC_MRCC_GLB_RST1_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_GPIO4_SHIFT)) & MRCC_MRCC_GLB_RST1_GPIO4_MASK) +/*! @} */ + +/*! @name MRCC_GLB_RST1_SET - Peripheral Reset Control Set 1 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_RST1_SET_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_RST1_SET_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */ +#define MRCC_MRCC_GLB_RST1_SET_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_RST1_SET_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_RST1_CLR - Peripheral Reset Control Clear 1 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_RST1_CLR_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_RST1_CLR_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_RSTn. */ +#define MRCC_MRCC_GLB_RST1_CLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_RST1_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_RST1_CLR_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_CC0 - AHB Clock Control 0 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_CC0_INPUTMUX0_MASK (0x1U) +#define MRCC_MRCC_GLB_CC0_INPUTMUX0_SHIFT (0U) +/*! INPUTMUX0 - INPUTMUX0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_INPUTMUX0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_INPUTMUX0_SHIFT)) & MRCC_MRCC_GLB_CC0_INPUTMUX0_MASK) + +#define MRCC_MRCC_GLB_CC0_I3C0_MASK (0x2U) +#define MRCC_MRCC_GLB_CC0_I3C0_SHIFT (1U) +/*! I3C0 - I3C0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_I3C0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_I3C0_SHIFT)) & MRCC_MRCC_GLB_CC0_I3C0_MASK) + +#define MRCC_MRCC_GLB_CC0_CTIMER0_MASK (0x4U) +#define MRCC_MRCC_GLB_CC0_CTIMER0_SHIFT (2U) +/*! CTIMER0 - CTIMER0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CTIMER0_SHIFT)) & MRCC_MRCC_GLB_CC0_CTIMER0_MASK) + +#define MRCC_MRCC_GLB_CC0_CTIMER1_MASK (0x8U) +#define MRCC_MRCC_GLB_CC0_CTIMER1_SHIFT (3U) +/*! CTIMER1 - CTIMER1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CTIMER1_SHIFT)) & MRCC_MRCC_GLB_CC0_CTIMER1_MASK) + +#define MRCC_MRCC_GLB_CC0_CTIMER2_MASK (0x10U) +#define MRCC_MRCC_GLB_CC0_CTIMER2_SHIFT (4U) +/*! CTIMER2 - CTIMER2 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CTIMER2_SHIFT)) & MRCC_MRCC_GLB_CC0_CTIMER2_MASK) + +#define MRCC_MRCC_GLB_CC0_CTIMER3_MASK (0x20U) +#define MRCC_MRCC_GLB_CC0_CTIMER3_SHIFT (5U) +/*! CTIMER3 - CTIMER3 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CTIMER3_SHIFT)) & MRCC_MRCC_GLB_CC0_CTIMER3_MASK) + +#define MRCC_MRCC_GLB_CC0_CTIMER4_MASK (0x40U) +#define MRCC_MRCC_GLB_CC0_CTIMER4_SHIFT (6U) +/*! CTIMER4 - CTIMER4 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CTIMER4_SHIFT)) & MRCC_MRCC_GLB_CC0_CTIMER4_MASK) + +#define MRCC_MRCC_GLB_CC0_FREQME_MASK (0x80U) +#define MRCC_MRCC_GLB_CC0_FREQME_SHIFT (7U) +/*! FREQME - FREQME + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_FREQME(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_FREQME_SHIFT)) & MRCC_MRCC_GLB_CC0_FREQME_MASK) + +#define MRCC_MRCC_GLB_CC0_UTICK0_MASK (0x100U) +#define MRCC_MRCC_GLB_CC0_UTICK0_SHIFT (8U) +/*! UTICK0 - UTICK0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_UTICK0_SHIFT)) & MRCC_MRCC_GLB_CC0_UTICK0_MASK) + +#define MRCC_MRCC_GLB_CC0_WWDT0_MASK (0x200U) +#define MRCC_MRCC_GLB_CC0_WWDT0_SHIFT (9U) +/*! WWDT0 - WWDT0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_WWDT0_SHIFT)) & MRCC_MRCC_GLB_CC0_WWDT0_MASK) + +#define MRCC_MRCC_GLB_CC0_DMA_MASK (0x400U) +#define MRCC_MRCC_GLB_CC0_DMA_SHIFT (10U) +/*! DMA - DMA + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_DMA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_DMA_SHIFT)) & MRCC_MRCC_GLB_CC0_DMA_MASK) + +#define MRCC_MRCC_GLB_CC0_AOI0_MASK (0x800U) +#define MRCC_MRCC_GLB_CC0_AOI0_SHIFT (11U) +/*! AOI0 - AOI0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_AOI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_AOI0_SHIFT)) & MRCC_MRCC_GLB_CC0_AOI0_MASK) + +#define MRCC_MRCC_GLB_CC0_CRC0_MASK (0x1000U) +#define MRCC_MRCC_GLB_CC0_CRC0_SHIFT (12U) +/*! CRC0 - CRC0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_CRC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CRC0_SHIFT)) & MRCC_MRCC_GLB_CC0_CRC0_MASK) + +#define MRCC_MRCC_GLB_CC0_EIM0_MASK (0x2000U) +#define MRCC_MRCC_GLB_CC0_EIM0_SHIFT (13U) +/*! EIM0 - EIM0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_EIM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_EIM0_SHIFT)) & MRCC_MRCC_GLB_CC0_EIM0_MASK) + +#define MRCC_MRCC_GLB_CC0_ERM0_MASK (0x4000U) +#define MRCC_MRCC_GLB_CC0_ERM0_SHIFT (14U) +/*! ERM0 - ERM0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_ERM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_ERM0_SHIFT)) & MRCC_MRCC_GLB_CC0_ERM0_MASK) + +#define MRCC_MRCC_GLB_CC0_FMC_MASK (0x8000U) +#define MRCC_MRCC_GLB_CC0_FMC_SHIFT (15U) +/*! FMC - FMC + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_FMC(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_FMC_SHIFT)) & MRCC_MRCC_GLB_CC0_FMC_MASK) + +#define MRCC_MRCC_GLB_CC0_AOI1_MASK (0x10000U) +#define MRCC_MRCC_GLB_CC0_AOI1_SHIFT (16U) +/*! AOI1 - AOI1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_AOI1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_AOI1_SHIFT)) & MRCC_MRCC_GLB_CC0_AOI1_MASK) + +#define MRCC_MRCC_GLB_CC0_FLEXIO0_MASK (0x20000U) +#define MRCC_MRCC_GLB_CC0_FLEXIO0_SHIFT (17U) +/*! FLEXIO0 - FLEXIO0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_FLEXIO0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_FLEXIO0_SHIFT)) & MRCC_MRCC_GLB_CC0_FLEXIO0_MASK) + +#define MRCC_MRCC_GLB_CC0_LPI2C0_MASK (0x40000U) +#define MRCC_MRCC_GLB_CC0_LPI2C0_SHIFT (18U) +/*! LPI2C0 - LPI2C0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPI2C0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPI2C0_SHIFT)) & MRCC_MRCC_GLB_CC0_LPI2C0_MASK) + +#define MRCC_MRCC_GLB_CC0_LPI2C1_MASK (0x80000U) +#define MRCC_MRCC_GLB_CC0_LPI2C1_SHIFT (19U) +/*! LPI2C1 - LPI2C1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPI2C1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPI2C1_SHIFT)) & MRCC_MRCC_GLB_CC0_LPI2C1_MASK) + +#define MRCC_MRCC_GLB_CC0_LPSPI0_MASK (0x100000U) +#define MRCC_MRCC_GLB_CC0_LPSPI0_SHIFT (20U) +/*! LPSPI0 - LPSPI0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPSPI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPSPI0_SHIFT)) & MRCC_MRCC_GLB_CC0_LPSPI0_MASK) + +#define MRCC_MRCC_GLB_CC0_LPSPI1_MASK (0x200000U) +#define MRCC_MRCC_GLB_CC0_LPSPI1_SHIFT (21U) +/*! LPSPI1 - LPSPI1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPSPI1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPSPI1_SHIFT)) & MRCC_MRCC_GLB_CC0_LPSPI1_MASK) + +#define MRCC_MRCC_GLB_CC0_LPUART0_MASK (0x400000U) +#define MRCC_MRCC_GLB_CC0_LPUART0_SHIFT (22U) +/*! LPUART0 - LPUART0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPUART0_SHIFT)) & MRCC_MRCC_GLB_CC0_LPUART0_MASK) + +#define MRCC_MRCC_GLB_CC0_LPUART1_MASK (0x800000U) +#define MRCC_MRCC_GLB_CC0_LPUART1_SHIFT (23U) +/*! LPUART1 - LPUART1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPUART1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPUART1_SHIFT)) & MRCC_MRCC_GLB_CC0_LPUART1_MASK) + +#define MRCC_MRCC_GLB_CC0_LPUART2_MASK (0x1000000U) +#define MRCC_MRCC_GLB_CC0_LPUART2_SHIFT (24U) +/*! LPUART2 - LPUART2 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPUART2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPUART2_SHIFT)) & MRCC_MRCC_GLB_CC0_LPUART2_MASK) + +#define MRCC_MRCC_GLB_CC0_LPUART3_MASK (0x2000000U) +#define MRCC_MRCC_GLB_CC0_LPUART3_SHIFT (25U) +/*! LPUART3 - LPUART3 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPUART3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPUART3_SHIFT)) & MRCC_MRCC_GLB_CC0_LPUART3_MASK) + +#define MRCC_MRCC_GLB_CC0_LPUART4_MASK (0x4000000U) +#define MRCC_MRCC_GLB_CC0_LPUART4_SHIFT (26U) +/*! LPUART4 - LPUART4 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_LPUART4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_LPUART4_SHIFT)) & MRCC_MRCC_GLB_CC0_LPUART4_MASK) + +#define MRCC_MRCC_GLB_CC0_USB0_MASK (0x8000000U) +#define MRCC_MRCC_GLB_CC0_USB0_SHIFT (27U) +/*! USB0 - USB0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_USB0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_USB0_SHIFT)) & MRCC_MRCC_GLB_CC0_USB0_MASK) + +#define MRCC_MRCC_GLB_CC0_QDC0_MASK (0x10000000U) +#define MRCC_MRCC_GLB_CC0_QDC0_SHIFT (28U) +/*! QDC0 - QDC0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_QDC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_QDC0_SHIFT)) & MRCC_MRCC_GLB_CC0_QDC0_MASK) + +#define MRCC_MRCC_GLB_CC0_QDC1_MASK (0x20000000U) +#define MRCC_MRCC_GLB_CC0_QDC1_SHIFT (29U) +/*! QDC1 - QDC1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_QDC1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_QDC1_SHIFT)) & MRCC_MRCC_GLB_CC0_QDC1_MASK) + +#define MRCC_MRCC_GLB_CC0_FLEXPWM0_MASK (0x40000000U) +#define MRCC_MRCC_GLB_CC0_FLEXPWM0_SHIFT (30U) +/*! FLEXPWM0 - FLEXPWM0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_FLEXPWM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_FLEXPWM0_SHIFT)) & MRCC_MRCC_GLB_CC0_FLEXPWM0_MASK) + +#define MRCC_MRCC_GLB_CC0_FLEXPWM1_MASK (0x80000000U) +#define MRCC_MRCC_GLB_CC0_FLEXPWM1_SHIFT (31U) +/*! FLEXPWM1 - FLEXPWM1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC0_FLEXPWM1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_FLEXPWM1_SHIFT)) & MRCC_MRCC_GLB_CC0_FLEXPWM1_MASK) +/*! @} */ + +/*! @name MRCC_GLB_CC0_SET - AHB Clock Control Set 0 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_CC0_SET_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_CC0_SET_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */ +#define MRCC_MRCC_GLB_CC0_SET_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_CC0_SET_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_CC0_CLR - AHB Clock Control Clear 0 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_CC0_CLR_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_CC0_CLR_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */ +#define MRCC_MRCC_GLB_CC0_CLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC0_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_CC0_CLR_DATA_MASK) +/*! @} */ + +/*! @name MRCC_GLB_CC1 - AHB Clock Control 1 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_CC1_OSTIMER0_MASK (0x1U) +#define MRCC_MRCC_GLB_CC1_OSTIMER0_SHIFT (0U) +/*! OSTIMER0 - OSTIMER0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_OSTIMER0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_OSTIMER0_SHIFT)) & MRCC_MRCC_GLB_CC1_OSTIMER0_MASK) + +#define MRCC_MRCC_GLB_CC1_ADC0_MASK (0x2U) +#define MRCC_MRCC_GLB_CC1_ADC0_SHIFT (1U) +/*! ADC0 - ADC0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_ADC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_ADC0_SHIFT)) & MRCC_MRCC_GLB_CC1_ADC0_MASK) + +#define MRCC_MRCC_GLB_CC1_ADC1_MASK (0x4U) +#define MRCC_MRCC_GLB_CC1_ADC1_SHIFT (2U) +/*! ADC1 - ADC1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_ADC1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_ADC1_SHIFT)) & MRCC_MRCC_GLB_CC1_ADC1_MASK) + +#define MRCC_MRCC_GLB_CC1_CMP0_MASK (0x8U) +#define MRCC_MRCC_GLB_CC1_CMP0_SHIFT (3U) +/*! CMP0 - CMP0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_CMP0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_CMP0_SHIFT)) & MRCC_MRCC_GLB_CC1_CMP0_MASK) + +#define MRCC_MRCC_GLB_CC1_CMP1_MASK (0x10U) +#define MRCC_MRCC_GLB_CC1_CMP1_SHIFT (4U) +/*! CMP1 - CMP1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_CMP1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_CMP1_SHIFT)) & MRCC_MRCC_GLB_CC1_CMP1_MASK) + +#define MRCC_MRCC_GLB_CC1_DAC0_MASK (0x20U) +#define MRCC_MRCC_GLB_CC1_DAC0_SHIFT (5U) +/*! DAC0 - DAC0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_DAC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_DAC0_SHIFT)) & MRCC_MRCC_GLB_CC1_DAC0_MASK) + +#define MRCC_MRCC_GLB_CC1_OPAMP0_MASK (0x40U) +#define MRCC_MRCC_GLB_CC1_OPAMP0_SHIFT (6U) +/*! OPAMP0 - OPAMP0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_OPAMP0_SHIFT)) & MRCC_MRCC_GLB_CC1_OPAMP0_MASK) + +#define MRCC_MRCC_GLB_CC1_PORT0_MASK (0x80U) +#define MRCC_MRCC_GLB_CC1_PORT0_SHIFT (7U) +/*! PORT0 - PORT0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_PORT0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_PORT0_SHIFT)) & MRCC_MRCC_GLB_CC1_PORT0_MASK) + +#define MRCC_MRCC_GLB_CC1_PORT1_MASK (0x100U) +#define MRCC_MRCC_GLB_CC1_PORT1_SHIFT (8U) +/*! PORT1 - PORT1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_PORT1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_PORT1_SHIFT)) & MRCC_MRCC_GLB_CC1_PORT1_MASK) + +#define MRCC_MRCC_GLB_CC1_PORT2_MASK (0x200U) +#define MRCC_MRCC_GLB_CC1_PORT2_SHIFT (9U) +/*! PORT2 - PORT2 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_PORT2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_PORT2_SHIFT)) & MRCC_MRCC_GLB_CC1_PORT2_MASK) + +#define MRCC_MRCC_GLB_CC1_PORT3_MASK (0x400U) +#define MRCC_MRCC_GLB_CC1_PORT3_SHIFT (10U) +/*! PORT3 - PORT3 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_PORT3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_PORT3_SHIFT)) & MRCC_MRCC_GLB_CC1_PORT3_MASK) + +#define MRCC_MRCC_GLB_CC1_PORT4_MASK (0x800U) +#define MRCC_MRCC_GLB_CC1_PORT4_SHIFT (11U) +/*! PORT4 - PORT4 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_PORT4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_PORT4_SHIFT)) & MRCC_MRCC_GLB_CC1_PORT4_MASK) + +#define MRCC_MRCC_GLB_CC1_FLEXCAN0_MASK (0x1000U) +#define MRCC_MRCC_GLB_CC1_FLEXCAN0_SHIFT (12U) +/*! FLEXCAN0 - FLEXCAN0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_FLEXCAN0_SHIFT)) & MRCC_MRCC_GLB_CC1_FLEXCAN0_MASK) + +#define MRCC_MRCC_GLB_CC1_LPI2C2_MASK (0x2000U) +#define MRCC_MRCC_GLB_CC1_LPI2C2_SHIFT (13U) +/*! LPI2C2 - LPI2C2 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_LPI2C2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_LPI2C2_SHIFT)) & MRCC_MRCC_GLB_CC1_LPI2C2_MASK) + +#define MRCC_MRCC_GLB_CC1_LPI2C3_MASK (0x4000U) +#define MRCC_MRCC_GLB_CC1_LPI2C3_SHIFT (14U) +/*! LPI2C3 - LPI2C3 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_LPI2C3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_LPI2C3_SHIFT)) & MRCC_MRCC_GLB_CC1_LPI2C3_MASK) + +#define MRCC_MRCC_GLB_CC1_RAMA_MASK (0x40000U) +#define MRCC_MRCC_GLB_CC1_RAMA_SHIFT (18U) +/*! RAMA - RAMA + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_RAMA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_RAMA_SHIFT)) & MRCC_MRCC_GLB_CC1_RAMA_MASK) + +#define MRCC_MRCC_GLB_CC1_RAMB_MASK (0x80000U) +#define MRCC_MRCC_GLB_CC1_RAMB_SHIFT (19U) +/*! RAMB - RAMB + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_RAMB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_RAMB_SHIFT)) & MRCC_MRCC_GLB_CC1_RAMB_MASK) + +#define MRCC_MRCC_GLB_CC1_GPIO0_MASK (0x100000U) +#define MRCC_MRCC_GLB_CC1_GPIO0_SHIFT (20U) +/*! GPIO0 - GPIO0 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_GPIO0_SHIFT)) & MRCC_MRCC_GLB_CC1_GPIO0_MASK) + +#define MRCC_MRCC_GLB_CC1_GPIO1_MASK (0x200000U) +#define MRCC_MRCC_GLB_CC1_GPIO1_SHIFT (21U) +/*! GPIO1 - GPIO1 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_GPIO1_SHIFT)) & MRCC_MRCC_GLB_CC1_GPIO1_MASK) + +#define MRCC_MRCC_GLB_CC1_GPIO2_MASK (0x400000U) +#define MRCC_MRCC_GLB_CC1_GPIO2_SHIFT (22U) +/*! GPIO2 - GPIO2 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_GPIO2_SHIFT)) & MRCC_MRCC_GLB_CC1_GPIO2_MASK) + +#define MRCC_MRCC_GLB_CC1_GPIO3_MASK (0x800000U) +#define MRCC_MRCC_GLB_CC1_GPIO3_SHIFT (23U) +/*! GPIO3 - GPIO3 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_GPIO3_SHIFT)) & MRCC_MRCC_GLB_CC1_GPIO3_MASK) + +#define MRCC_MRCC_GLB_CC1_GPIO4_MASK (0x1000000U) +#define MRCC_MRCC_GLB_CC1_GPIO4_SHIFT (24U) +/*! GPIO4 - GPIO4 + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_GPIO4_SHIFT)) & MRCC_MRCC_GLB_CC1_GPIO4_MASK) + +#define MRCC_MRCC_GLB_CC1_ROMC_MASK (0x2000000U) +#define MRCC_MRCC_GLB_CC1_ROMC_SHIFT (25U) +/*! ROMC - ROMC + * 0b0..Peripheral clock is disabled + * 0b1..Peripheral clock is enabled + */ +#define MRCC_MRCC_GLB_CC1_ROMC(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC1_ROMC_SHIFT)) & MRCC_MRCC_GLB_CC1_ROMC_MASK) +/*! @} */ + +/*! @name MRCC_GLB_CC_SET - AHB Clock Control Set 1 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_CC_SET_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_CC_SET_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */ +#define MRCC_MRCC_GLB_CC_SET_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC_SET_DATA_SHIFT)) & MRCC_MRCC_GLB_CC_SET_DATA_MASK) +/*! @} */ + +/* The count of MRCC_MRCC_GLB_CC_SET */ +#define MRCC_MRCC_GLB_CC_SET_COUNT (1U) + +/*! @name MRCC_GLB_CC_CLR - AHB Clock Control Clear 1 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_CC_CLR_DATA_MASK (0xFFFFFFFFU) +#define MRCC_MRCC_GLB_CC_CLR_DATA_SHIFT (0U) +/*! DATA - Data array value, refer to corresponding position in MRCC_GLB_CCn. */ +#define MRCC_MRCC_GLB_CC_CLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_CC_CLR_DATA_SHIFT)) & MRCC_MRCC_GLB_CC_CLR_DATA_MASK) +/*! @} */ + +/* The count of MRCC_MRCC_GLB_CC_CLR */ +#define MRCC_MRCC_GLB_CC_CLR_COUNT (1U) + +/*! @name MRCC_GLB_ACC0 - Control Automatic Clock Gating 0 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_ACC0_INPUTMUX0_MASK (0x1U) +#define MRCC_MRCC_GLB_ACC0_INPUTMUX0_SHIFT (0U) +/*! INPUTMUX0 - INPUTMUX0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_INPUTMUX0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_INPUTMUX0_SHIFT)) & MRCC_MRCC_GLB_ACC0_INPUTMUX0_MASK) + +#define MRCC_MRCC_GLB_ACC0_I3C0_MASK (0x2U) +#define MRCC_MRCC_GLB_ACC0_I3C0_SHIFT (1U) +/*! I3C0 - I3C0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_I3C0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_I3C0_SHIFT)) & MRCC_MRCC_GLB_ACC0_I3C0_MASK) + +#define MRCC_MRCC_GLB_ACC0_CTIMER0_MASK (0x4U) +#define MRCC_MRCC_GLB_ACC0_CTIMER0_SHIFT (2U) +/*! CTIMER0 - CTIMER0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CTIMER0_SHIFT)) & MRCC_MRCC_GLB_ACC0_CTIMER0_MASK) + +#define MRCC_MRCC_GLB_ACC0_CTIMER1_MASK (0x8U) +#define MRCC_MRCC_GLB_ACC0_CTIMER1_SHIFT (3U) +/*! CTIMER1 - CTIMER1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CTIMER1_SHIFT)) & MRCC_MRCC_GLB_ACC0_CTIMER1_MASK) + +#define MRCC_MRCC_GLB_ACC0_CTIMER2_MASK (0x10U) +#define MRCC_MRCC_GLB_ACC0_CTIMER2_SHIFT (4U) +/*! CTIMER2 - CTIMER2 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CTIMER2_SHIFT)) & MRCC_MRCC_GLB_ACC0_CTIMER2_MASK) + +#define MRCC_MRCC_GLB_ACC0_CTIMER3_MASK (0x20U) +#define MRCC_MRCC_GLB_ACC0_CTIMER3_SHIFT (5U) +/*! CTIMER3 - CTIMER3 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CTIMER3_SHIFT)) & MRCC_MRCC_GLB_ACC0_CTIMER3_MASK) + +#define MRCC_MRCC_GLB_ACC0_CTIMER4_MASK (0x40U) +#define MRCC_MRCC_GLB_ACC0_CTIMER4_SHIFT (6U) +/*! CTIMER4 - CTIMER4 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CTIMER4_SHIFT)) & MRCC_MRCC_GLB_ACC0_CTIMER4_MASK) + +#define MRCC_MRCC_GLB_ACC0_FREQME_MASK (0x80U) +#define MRCC_MRCC_GLB_ACC0_FREQME_SHIFT (7U) +/*! FREQME - FREQME + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_FREQME(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_FREQME_SHIFT)) & MRCC_MRCC_GLB_ACC0_FREQME_MASK) + +#define MRCC_MRCC_GLB_ACC0_UTICK0_MASK (0x100U) +#define MRCC_MRCC_GLB_ACC0_UTICK0_SHIFT (8U) +/*! UTICK0 - UTICK0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_UTICK0_SHIFT)) & MRCC_MRCC_GLB_ACC0_UTICK0_MASK) + +#define MRCC_MRCC_GLB_ACC0_WWDT0_MASK (0x200U) +#define MRCC_MRCC_GLB_ACC0_WWDT0_SHIFT (9U) +/*! WWDT0 - WWDT0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_WWDT0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_WWDT0_SHIFT)) & MRCC_MRCC_GLB_ACC0_WWDT0_MASK) + +#define MRCC_MRCC_GLB_ACC0_DMA_MASK (0x400U) +#define MRCC_MRCC_GLB_ACC0_DMA_SHIFT (10U) +/*! DMA - DMA + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_DMA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_DMA_SHIFT)) & MRCC_MRCC_GLB_ACC0_DMA_MASK) + +#define MRCC_MRCC_GLB_ACC0_AOI0_MASK (0x800U) +#define MRCC_MRCC_GLB_ACC0_AOI0_SHIFT (11U) +/*! AOI0 - AOI0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_AOI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_AOI0_SHIFT)) & MRCC_MRCC_GLB_ACC0_AOI0_MASK) + +#define MRCC_MRCC_GLB_ACC0_CRC0_MASK (0x1000U) +#define MRCC_MRCC_GLB_ACC0_CRC0_SHIFT (12U) +/*! CRC0 - CRC0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_CRC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_CRC0_SHIFT)) & MRCC_MRCC_GLB_ACC0_CRC0_MASK) + +#define MRCC_MRCC_GLB_ACC0_EIM0_MASK (0x2000U) +#define MRCC_MRCC_GLB_ACC0_EIM0_SHIFT (13U) +/*! EIM0 - EIM0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_EIM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_EIM0_SHIFT)) & MRCC_MRCC_GLB_ACC0_EIM0_MASK) + +#define MRCC_MRCC_GLB_ACC0_ERM0_MASK (0x4000U) +#define MRCC_MRCC_GLB_ACC0_ERM0_SHIFT (14U) +/*! ERM0 - ERM0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_ERM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_ERM0_SHIFT)) & MRCC_MRCC_GLB_ACC0_ERM0_MASK) + +#define MRCC_MRCC_GLB_ACC0_FMC_MASK (0x8000U) +#define MRCC_MRCC_GLB_ACC0_FMC_SHIFT (15U) +/*! FMC - FMC + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_FMC(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_FMC_SHIFT)) & MRCC_MRCC_GLB_ACC0_FMC_MASK) + +#define MRCC_MRCC_GLB_ACC0_AOI1_MASK (0x10000U) +#define MRCC_MRCC_GLB_ACC0_AOI1_SHIFT (16U) +/*! AOI1 - AOI1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_AOI1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_AOI1_SHIFT)) & MRCC_MRCC_GLB_ACC0_AOI1_MASK) + +#define MRCC_MRCC_GLB_ACC0_FLEXIO0_MASK (0x20000U) +#define MRCC_MRCC_GLB_ACC0_FLEXIO0_SHIFT (17U) +/*! FLEXIO0 - FLEXIO0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_FLEXIO0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_FLEXIO0_SHIFT)) & MRCC_MRCC_GLB_ACC0_FLEXIO0_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPI2C0_MASK (0x40000U) +#define MRCC_MRCC_GLB_ACC0_LPI2C0_SHIFT (18U) +/*! LPI2C0 - LPI2C0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPI2C0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPI2C0_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPI2C0_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPI2C1_MASK (0x80000U) +#define MRCC_MRCC_GLB_ACC0_LPI2C1_SHIFT (19U) +/*! LPI2C1 - LPI2C1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPI2C1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPI2C1_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPI2C1_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPSPI0_MASK (0x100000U) +#define MRCC_MRCC_GLB_ACC0_LPSPI0_SHIFT (20U) +/*! LPSPI0 - LPSPI0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPSPI0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPSPI0_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPSPI0_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPSPI1_MASK (0x200000U) +#define MRCC_MRCC_GLB_ACC0_LPSPI1_SHIFT (21U) +/*! LPSPI1 - LPSPI1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPSPI1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPSPI1_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPSPI1_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPUART0_MASK (0x400000U) +#define MRCC_MRCC_GLB_ACC0_LPUART0_SHIFT (22U) +/*! LPUART0 - LPUART0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPUART0_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPUART0_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPUART1_MASK (0x800000U) +#define MRCC_MRCC_GLB_ACC0_LPUART1_SHIFT (23U) +/*! LPUART1 - LPUART1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPUART1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPUART1_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPUART1_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPUART2_MASK (0x1000000U) +#define MRCC_MRCC_GLB_ACC0_LPUART2_SHIFT (24U) +/*! LPUART2 - LPUART2 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPUART2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPUART2_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPUART2_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPUART3_MASK (0x2000000U) +#define MRCC_MRCC_GLB_ACC0_LPUART3_SHIFT (25U) +/*! LPUART3 - LPUART3 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPUART3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPUART3_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPUART3_MASK) + +#define MRCC_MRCC_GLB_ACC0_LPUART4_MASK (0x4000000U) +#define MRCC_MRCC_GLB_ACC0_LPUART4_SHIFT (26U) +/*! LPUART4 - LPUART4 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_LPUART4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_LPUART4_SHIFT)) & MRCC_MRCC_GLB_ACC0_LPUART4_MASK) + +#define MRCC_MRCC_GLB_ACC0_USB0_MASK (0x8000000U) +#define MRCC_MRCC_GLB_ACC0_USB0_SHIFT (27U) +/*! USB0 - USB0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_USB0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_USB0_SHIFT)) & MRCC_MRCC_GLB_ACC0_USB0_MASK) + +#define MRCC_MRCC_GLB_ACC0_QDC0_MASK (0x10000000U) +#define MRCC_MRCC_GLB_ACC0_QDC0_SHIFT (28U) +/*! QDC0 - QDC0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_QDC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_QDC0_SHIFT)) & MRCC_MRCC_GLB_ACC0_QDC0_MASK) + +#define MRCC_MRCC_GLB_ACC0_QDC1_MASK (0x20000000U) +#define MRCC_MRCC_GLB_ACC0_QDC1_SHIFT (29U) +/*! QDC1 - QDC1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_QDC1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_QDC1_SHIFT)) & MRCC_MRCC_GLB_ACC0_QDC1_MASK) + +#define MRCC_MRCC_GLB_ACC0_FLEXPWM0_MASK (0x40000000U) +#define MRCC_MRCC_GLB_ACC0_FLEXPWM0_SHIFT (30U) +/*! FLEXPWM0 - FLEXPWM0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_FLEXPWM0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_FLEXPWM0_SHIFT)) & MRCC_MRCC_GLB_ACC0_FLEXPWM0_MASK) + +#define MRCC_MRCC_GLB_ACC0_FLEXPWM1_MASK (0x80000000U) +#define MRCC_MRCC_GLB_ACC0_FLEXPWM1_SHIFT (31U) +/*! FLEXPWM1 - FLEXPWM1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC0_FLEXPWM1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC0_FLEXPWM1_SHIFT)) & MRCC_MRCC_GLB_ACC0_FLEXPWM1_MASK) +/*! @} */ + +/*! @name MRCC_GLB_ACC1 - Control Automatic Clock Gating 1 */ +/*! @{ */ + +#define MRCC_MRCC_GLB_ACC1_OSTIMER0_MASK (0x1U) +#define MRCC_MRCC_GLB_ACC1_OSTIMER0_SHIFT (0U) +/*! OSTIMER0 - OSTIMER0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_OSTIMER0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_OSTIMER0_SHIFT)) & MRCC_MRCC_GLB_ACC1_OSTIMER0_MASK) + +#define MRCC_MRCC_GLB_ACC1_ADC0_MASK (0x2U) +#define MRCC_MRCC_GLB_ACC1_ADC0_SHIFT (1U) +/*! ADC0 - ADC0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_ADC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_ADC0_SHIFT)) & MRCC_MRCC_GLB_ACC1_ADC0_MASK) + +#define MRCC_MRCC_GLB_ACC1_ADC1_MASK (0x4U) +#define MRCC_MRCC_GLB_ACC1_ADC1_SHIFT (2U) +/*! ADC1 - ADC1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_ADC1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_ADC1_SHIFT)) & MRCC_MRCC_GLB_ACC1_ADC1_MASK) + +#define MRCC_MRCC_GLB_ACC1_CMP0_MASK (0x8U) +#define MRCC_MRCC_GLB_ACC1_CMP0_SHIFT (3U) +/*! CMP0 - CMP0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_CMP0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_CMP0_SHIFT)) & MRCC_MRCC_GLB_ACC1_CMP0_MASK) + +#define MRCC_MRCC_GLB_ACC1_CMP1_MASK (0x10U) +#define MRCC_MRCC_GLB_ACC1_CMP1_SHIFT (4U) +/*! CMP1 - CMP1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_CMP1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_CMP1_SHIFT)) & MRCC_MRCC_GLB_ACC1_CMP1_MASK) + +#define MRCC_MRCC_GLB_ACC1_DAC0_MASK (0x20U) +#define MRCC_MRCC_GLB_ACC1_DAC0_SHIFT (5U) +/*! DAC0 - DAC0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_DAC0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_DAC0_SHIFT)) & MRCC_MRCC_GLB_ACC1_DAC0_MASK) + +#define MRCC_MRCC_GLB_ACC1_OPAMP0_MASK (0x40U) +#define MRCC_MRCC_GLB_ACC1_OPAMP0_SHIFT (6U) +/*! OPAMP0 - OPAMP0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_OPAMP0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_OPAMP0_SHIFT)) & MRCC_MRCC_GLB_ACC1_OPAMP0_MASK) + +#define MRCC_MRCC_GLB_ACC1_PORT0_MASK (0x80U) +#define MRCC_MRCC_GLB_ACC1_PORT0_SHIFT (7U) +/*! PORT0 - PORT0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_PORT0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_PORT0_SHIFT)) & MRCC_MRCC_GLB_ACC1_PORT0_MASK) + +#define MRCC_MRCC_GLB_ACC1_PORT1_MASK (0x100U) +#define MRCC_MRCC_GLB_ACC1_PORT1_SHIFT (8U) +/*! PORT1 - PORT1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_PORT1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_PORT1_SHIFT)) & MRCC_MRCC_GLB_ACC1_PORT1_MASK) + +#define MRCC_MRCC_GLB_ACC1_PORT2_MASK (0x200U) +#define MRCC_MRCC_GLB_ACC1_PORT2_SHIFT (9U) +/*! PORT2 - PORT2 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_PORT2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_PORT2_SHIFT)) & MRCC_MRCC_GLB_ACC1_PORT2_MASK) + +#define MRCC_MRCC_GLB_ACC1_PORT3_MASK (0x400U) +#define MRCC_MRCC_GLB_ACC1_PORT3_SHIFT (10U) +/*! PORT3 - PORT3 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_PORT3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_PORT3_SHIFT)) & MRCC_MRCC_GLB_ACC1_PORT3_MASK) + +#define MRCC_MRCC_GLB_ACC1_PORT4_MASK (0x800U) +#define MRCC_MRCC_GLB_ACC1_PORT4_SHIFT (11U) +/*! PORT4 - PORT4 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_PORT4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_PORT4_SHIFT)) & MRCC_MRCC_GLB_ACC1_PORT4_MASK) + +#define MRCC_MRCC_GLB_ACC1_FLEXCAN0_MASK (0x1000U) +#define MRCC_MRCC_GLB_ACC1_FLEXCAN0_SHIFT (12U) +/*! FLEXCAN0 - FLEXCAN0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_FLEXCAN0_SHIFT)) & MRCC_MRCC_GLB_ACC1_FLEXCAN0_MASK) + +#define MRCC_MRCC_GLB_ACC1_LPI2C2_MASK (0x2000U) +#define MRCC_MRCC_GLB_ACC1_LPI2C2_SHIFT (13U) +/*! LPI2C2 - LPI2C2 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_LPI2C2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_LPI2C2_SHIFT)) & MRCC_MRCC_GLB_ACC1_LPI2C2_MASK) + +#define MRCC_MRCC_GLB_ACC1_LPI2C3_MASK (0x4000U) +#define MRCC_MRCC_GLB_ACC1_LPI2C3_SHIFT (14U) +/*! LPI2C3 - LPI2C3 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_LPI2C3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_LPI2C3_SHIFT)) & MRCC_MRCC_GLB_ACC1_LPI2C3_MASK) + +#define MRCC_MRCC_GLB_ACC1_RAMA_MASK (0x40000U) +#define MRCC_MRCC_GLB_ACC1_RAMA_SHIFT (18U) +/*! RAMA - RAMA + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_RAMA(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_RAMA_SHIFT)) & MRCC_MRCC_GLB_ACC1_RAMA_MASK) + +#define MRCC_MRCC_GLB_ACC1_RAMB_MASK (0x80000U) +#define MRCC_MRCC_GLB_ACC1_RAMB_SHIFT (19U) +/*! RAMB - RAMB + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_RAMB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_RAMB_SHIFT)) & MRCC_MRCC_GLB_ACC1_RAMB_MASK) + +#define MRCC_MRCC_GLB_ACC1_GPIO0_MASK (0x100000U) +#define MRCC_MRCC_GLB_ACC1_GPIO0_SHIFT (20U) +/*! GPIO0 - GPIO0 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_GPIO0_SHIFT)) & MRCC_MRCC_GLB_ACC1_GPIO0_MASK) + +#define MRCC_MRCC_GLB_ACC1_GPIO1_MASK (0x200000U) +#define MRCC_MRCC_GLB_ACC1_GPIO1_SHIFT (21U) +/*! GPIO1 - GPIO1 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_GPIO1_SHIFT)) & MRCC_MRCC_GLB_ACC1_GPIO1_MASK) + +#define MRCC_MRCC_GLB_ACC1_GPIO2_MASK (0x400000U) +#define MRCC_MRCC_GLB_ACC1_GPIO2_SHIFT (22U) +/*! GPIO2 - GPIO2 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_GPIO2_SHIFT)) & MRCC_MRCC_GLB_ACC1_GPIO2_MASK) + +#define MRCC_MRCC_GLB_ACC1_GPIO3_MASK (0x800000U) +#define MRCC_MRCC_GLB_ACC1_GPIO3_SHIFT (23U) +/*! GPIO3 - GPIO3 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_GPIO3_SHIFT)) & MRCC_MRCC_GLB_ACC1_GPIO3_MASK) + +#define MRCC_MRCC_GLB_ACC1_GPIO4_MASK (0x1000000U) +#define MRCC_MRCC_GLB_ACC1_GPIO4_SHIFT (24U) +/*! GPIO4 - GPIO4 + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_GPIO4_SHIFT)) & MRCC_MRCC_GLB_ACC1_GPIO4_MASK) + +#define MRCC_MRCC_GLB_ACC1_ROMC_MASK (0x2000000U) +#define MRCC_MRCC_GLB_ACC1_ROMC_SHIFT (25U) +/*! ROMC - ROMC + * 0b0..Automatic clock gating is disabled + * 0b1..Automatic clock gating is enabled + */ +#define MRCC_MRCC_GLB_ACC1_ROMC(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_GLB_ACC1_ROMC_SHIFT)) & MRCC_MRCC_GLB_ACC1_ROMC_MASK) +/*! @} */ + +/*! @name MRCC_I3C0_FCLK_CLKSEL - I3C0_FCLK clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_I3C0_FCLK_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_I3C0_FCLK_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b101..CLK_1M + * 0b011..CLK_IN + * 0b010..FRO_HF_DIV + * 0b000..FRO_12M + */ +#define MRCC_MRCC_I3C0_FCLK_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_I3C0_FCLK_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_I3C0_FCLK_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_I3C0_FCLK_CLKDIV - I3C0_FCLK clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_I3C0_FCLK_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_I3C0_FCLK_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_I3C0_FCLK_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_I3C0_FCLK_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_I3C0_FCLK_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_I3C0_FCLK_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_I3C0_FCLK_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_I3C0_FCLK_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_I3C0_FCLK_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_I3C0_FCLK_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_I3C0_FCLK_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_I3C0_FCLK_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_I3C0_FCLK_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_I3C0_FCLK_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_I3C0_FCLK_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_I3C0_FCLK_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_I3C0_FCLK_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_I3C0_FCLK_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_I3C0_FCLK_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_I3C0_FCLK_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER0_CLKSEL - CTIMER0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER0_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_CTIMER0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b101..CLK_1M + * 0b100..CLK_16K + * 0b011..CLK_IN + * 0b001..FRO_HF_GATED + * 0b000..FRO_12M + */ +#define MRCC_MRCC_CTIMER0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CTIMER0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER0_CLKDIV - CTIMER0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CTIMER0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CTIMER0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CTIMER0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CTIMER0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CTIMER0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CTIMER0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CTIMER0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CTIMER0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CTIMER0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CTIMER0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CTIMER0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CTIMER0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER1_CLKSEL - CTIMER1 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER1_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_CTIMER1_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b101..CLK_1M + * 0b100..CLK_16K + * 0b011..CLK_IN + * 0b001..FRO_HF_GATED + * 0b000..FRO_12M + */ +#define MRCC_MRCC_CTIMER1_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CTIMER1_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER1_CLKDIV - CTIMER1 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER1_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CTIMER1_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CTIMER1_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CTIMER1_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CTIMER1_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CTIMER1_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CTIMER1_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CTIMER1_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CTIMER1_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CTIMER1_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CTIMER1_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CTIMER1_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CTIMER1_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER2_CLKSEL - CTIMER2 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER2_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_CTIMER2_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b101..CLK_1M + * 0b100..CLK_16K + * 0b011..CLK_IN + * 0b001..FRO_HF_GATED + * 0b000..FRO_12M + */ +#define MRCC_MRCC_CTIMER2_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CTIMER2_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER2_CLKDIV - CTIMER2 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER2_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CTIMER2_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CTIMER2_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CTIMER2_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CTIMER2_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CTIMER2_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CTIMER2_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CTIMER2_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CTIMER2_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CTIMER2_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CTIMER2_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CTIMER2_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CTIMER2_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER3_CLKSEL - CTIMER3 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER3_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_CTIMER3_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b101..CLK_1M + * 0b100..CLK_16K + * 0b011..CLK_IN + * 0b001..FRO_HF_GATED + * 0b000..FRO_12M + */ +#define MRCC_MRCC_CTIMER3_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER3_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CTIMER3_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER3_CLKDIV - CTIMER3 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER3_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CTIMER3_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CTIMER3_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER3_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CTIMER3_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CTIMER3_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CTIMER3_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CTIMER3_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER3_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CTIMER3_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CTIMER3_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CTIMER3_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CTIMER3_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER3_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CTIMER3_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CTIMER3_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CTIMER3_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CTIMER3_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER3_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CTIMER3_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER4_CLKSEL - CTIMER4 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER4_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_CTIMER4_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b101..CLK_1M + * 0b100..CLK_16K + * 0b011..CLK_IN + * 0b001..FRO_HF_GATED + * 0b000..FRO_12M + */ +#define MRCC_MRCC_CTIMER4_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER4_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CTIMER4_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_CTIMER4_CLKDIV - CTIMER4 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CTIMER4_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CTIMER4_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CTIMER4_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER4_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CTIMER4_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CTIMER4_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CTIMER4_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CTIMER4_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER4_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CTIMER4_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CTIMER4_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CTIMER4_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CTIMER4_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER4_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CTIMER4_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CTIMER4_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CTIMER4_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CTIMER4_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CTIMER4_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CTIMER4_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_WWDT0_CLKDIV - WWDT0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_WWDT0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_WWDT0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_WWDT0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_WWDT0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_WWDT0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_WWDT0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_WWDT0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_WWDT0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_WWDT0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_WWDT0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_WWDT0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_WWDT0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_WWDT0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_WWDT0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_WWDT0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_WWDT0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_WWDT0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_WWDT0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_WWDT0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_WWDT0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_FLEXIO0_CLKSEL - FLEXIO0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_FLEXIO0_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_FLEXIO0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b101..CLK_1M + * 0b011..CLK_IN + * 0b001..FRO_HF_GATED + * 0b000..FRO_12M + */ +#define MRCC_MRCC_FLEXIO0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXIO0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_FLEXIO0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_FLEXIO0_CLKDIV - FLEXIO0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_FLEXIO0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_FLEXIO0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_FLEXIO0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXIO0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_FLEXIO0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_FLEXIO0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_FLEXIO0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_FLEXIO0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXIO0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_FLEXIO0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_FLEXIO0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_FLEXIO0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_FLEXIO0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXIO0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_FLEXIO0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_FLEXIO0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_FLEXIO0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_FLEXIO0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXIO0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_FLEXIO0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPI2C0_CLKSEL - LPI2C0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPI2C0_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPI2C0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b101..CLK_1M + * 0b011..CLK_IN + * 0b010..FRO_HF_DIV + * 0b000..FRO_12M + */ +#define MRCC_MRCC_LPI2C0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPI2C0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPI2C0_CLKDIV - LPI2C0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPI2C0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPI2C0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPI2C0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPI2C0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPI2C0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPI2C0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPI2C0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPI2C0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPI2C0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPI2C0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPI2C0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPI2C0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPI2C0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPI2C1_CLKSEL - LPI2C1 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPI2C1_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPI2C1_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b101..CLK_1M + * 0b011..CLK_IN + * 0b010..FRO_HF_DIV + * 0b000..FRO_12M + */ +#define MRCC_MRCC_LPI2C1_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPI2C1_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPI2C1_CLKDIV - LPI2C1 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPI2C1_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPI2C1_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPI2C1_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPI2C1_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPI2C1_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPI2C1_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPI2C1_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPI2C1_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPI2C1_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPI2C1_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPI2C1_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPI2C1_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPI2C1_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPI2C1_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPI2C1_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C1_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPI2C1_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPSPI0_CLKSEL - LPSPI0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPSPI0_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPSPI0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b101..CLK_1M + * 0b011..CLK_IN + * 0b010..FRO_HF_DIV + * 0b000..FRO_12M + */ +#define MRCC_MRCC_LPSPI0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPSPI0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPSPI0_CLKDIV - LPSPI0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPSPI0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPSPI0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPSPI0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPSPI0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPSPI0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPSPI0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPSPI0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPSPI0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPSPI0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPSPI0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPSPI0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPSPI0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPSPI0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPSPI1_CLKSEL - LPSPI1 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPSPI1_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPSPI1_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b101..CLK_1M + * 0b011..CLK_IN + * 0b010..FRO_HF_DIV + * 0b000..FRO_12M + */ +#define MRCC_MRCC_LPSPI1_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPSPI1_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPSPI1_CLKDIV - LPSPI1 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPSPI1_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPSPI1_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPSPI1_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPSPI1_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPSPI1_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPSPI1_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPSPI1_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPSPI1_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPSPI1_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPSPI1_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPSPI1_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPSPI1_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPSPI1_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPUART0_CLKSEL - LPUART0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART0_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPUART0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b101..CLK_1M + * 0b100..CLK_16K + * 0b011..CLK_IN + * 0b010..FRO_HF_DIV + * 0b000..FRO_12M + */ +#define MRCC_MRCC_LPUART0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPUART0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPUART0_CLKDIV - LPUART0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPUART0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPUART0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPUART0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPUART0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPUART0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPUART0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPUART0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPUART0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPUART0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPUART0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPUART0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPUART0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPUART0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPUART0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPUART0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPUART1_CLKSEL - LPUART1 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART1_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPUART1_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b101..CLK_1M + * 0b100..CLK_16K + * 0b011..CLK_IN + * 0b010..FRO_HF_DIV + * 0b000..FRO_12M + */ +#define MRCC_MRCC_LPUART1_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPUART1_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPUART1_CLKDIV - LPUART1 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART1_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPUART1_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPUART1_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPUART1_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPUART1_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPUART1_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPUART1_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPUART1_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPUART1_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPUART1_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPUART1_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPUART1_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPUART1_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPUART1_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPUART1_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART1_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPUART1_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPUART2_CLKSEL - LPUART2 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART2_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPUART2_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b101..CLK_1M + * 0b100..CLK_16K + * 0b011..CLK_IN + * 0b010..FRO_HF_DIV + * 0b000..FRO_12M + */ +#define MRCC_MRCC_LPUART2_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPUART2_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPUART2_CLKDIV - LPUART2 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART2_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPUART2_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPUART2_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPUART2_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPUART2_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPUART2_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPUART2_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPUART2_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPUART2_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPUART2_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPUART2_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPUART2_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPUART2_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPUART2_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPUART2_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART2_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPUART2_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPUART3_CLKSEL - LPUART3 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART3_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPUART3_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b101..CLK_1M + * 0b100..CLK_16K + * 0b011..CLK_IN + * 0b010..FRO_HF_DIV + * 0b000..FRO_12M + */ +#define MRCC_MRCC_LPUART3_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART3_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPUART3_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPUART3_CLKDIV - LPUART3 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART3_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPUART3_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPUART3_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART3_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPUART3_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPUART3_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPUART3_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPUART3_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART3_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPUART3_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPUART3_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPUART3_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPUART3_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART3_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPUART3_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPUART3_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPUART3_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPUART3_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART3_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPUART3_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPUART4_CLKSEL - LPUART4 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART4_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPUART4_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b101..CLK_1M + * 0b100..CLK_16K + * 0b011..CLK_IN + * 0b010..FRO_HF_DIV + * 0b000..FRO_12M + */ +#define MRCC_MRCC_LPUART4_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART4_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPUART4_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPUART4_CLKDIV - LPUART4 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPUART4_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPUART4_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPUART4_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART4_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPUART4_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPUART4_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPUART4_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPUART4_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART4_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPUART4_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPUART4_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPUART4_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPUART4_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART4_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPUART4_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPUART4_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPUART4_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPUART4_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPUART4_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPUART4_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_USB0_CLKSEL - USB0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_USB0_CLKSEL_MUX_MASK (0x3U) +#define MRCC_MRCC_USB0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b11..Reserved(NO Clock) + * 0b10..CLK_IN + * 0b01..CLK_48M + */ +#define MRCC_MRCC_USB0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_USB0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_USB0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPTMR0_CLKSEL - LPTMR0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPTMR0_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPTMR0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b101..CLK_1M + * 0b011..CLK_IN + * 0b010..FRO_HF_DIV + * 0b000..FRO_12M + */ +#define MRCC_MRCC_LPTMR0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPTMR0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPTMR0_CLKDIV - LPTMR0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPTMR0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPTMR0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPTMR0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPTMR0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPTMR0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPTMR0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPTMR0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPTMR0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPTMR0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPTMR0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPTMR0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPTMR0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPTMR0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_OSTIMER0_CLKSEL - OSTIMER0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_OSTIMER0_CLKSEL_MUX_MASK (0x3U) +#define MRCC_MRCC_OSTIMER0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b11..Reserved2(NO Clock) + * 0b10..CLK_1M + * 0b00..CLK_16K + */ +#define MRCC_MRCC_OSTIMER0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_OSTIMER0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_OSTIMER0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_ADC0_CLKSEL - ADC0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_ADC0_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_ADC0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b101..CLK_1M + * 0b011..CLK_IN + * 0b001..FRO_HF_GATED + * 0b000..FRO_12M + */ +#define MRCC_MRCC_ADC0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_ADC0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_ADC0_CLKDIV - ADC0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_ADC0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_ADC0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_ADC0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_ADC0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_ADC0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_ADC0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_ADC0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_ADC0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_ADC0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_ADC0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_ADC0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_ADC0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_ADC0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_ADC0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_ADC0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_ADC0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_ADC1_CLKSEL - ADC1 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_ADC1_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_ADC1_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b101..CLK_1M + * 0b011..CLK_IN + * 0b001..FRO_HF_GATED + * 0b000..FRO_12M + */ +#define MRCC_MRCC_ADC1_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC1_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_ADC1_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_ADC1_CLKDIV - ADC1 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_ADC1_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_ADC1_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_ADC1_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC1_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_ADC1_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_ADC1_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_ADC1_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_ADC1_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC1_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_ADC1_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_ADC1_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_ADC1_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_ADC1_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC1_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_ADC1_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_ADC1_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_ADC1_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_ADC1_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_ADC1_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_ADC1_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CMP0_FUNC_CLKDIV - CMP0_FUNC clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP0_FUNC_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP0_FUNC_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP0_FUNC_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP0_FUNC_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CMP0_RR_CLKSEL - CMP0_RR clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_CMP0_RR_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_CMP0_RR_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b101..CLK_1M + * 0b011..CLK_IN + * 0b010..FRO_HF_DIV + * 0b000..FRO_12M + */ +#define MRCC_MRCC_CMP0_RR_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_CMP0_RR_CLKDIV - CMP0_RR clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CMP0_RR_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CMP0_RR_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CMP0_RR_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CMP0_RR_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CMP0_RR_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CMP0_RR_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CMP0_RR_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CMP0_RR_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CMP0_RR_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP0_RR_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CMP1_FUNC_CLKDIV - CMP1_FUNC clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP1_FUNC_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP1_FUNC_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP1_FUNC_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP1_FUNC_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CMP1_RR_CLKSEL - CMP1_RR clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_CMP1_RR_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_CMP1_RR_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b101..CLK_1M + * 0b011..CLK_IN + * 0b010..FRO_HF_DIV + * 0b000..FRO_12M + */ +#define MRCC_MRCC_CMP1_RR_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_CMP1_RR_CLKDIV - CMP1_RR clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CMP1_RR_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CMP1_RR_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CMP1_RR_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CMP1_RR_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CMP1_RR_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CMP1_RR_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CMP1_RR_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CMP1_RR_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CMP1_RR_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CMP1_RR_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_DAC0_CLKSEL - DAC0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_DAC0_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_DAC0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b101..CLK_1M + * 0b011..CLK_IN + * 0b010..FRO_HF_DIV + * 0b000..FRO_12M + */ +#define MRCC_MRCC_DAC0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DAC0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_DAC0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_DAC0_CLKDIV - DAC0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_DAC0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_DAC0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_DAC0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DAC0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_DAC0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_DAC0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_DAC0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_DAC0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DAC0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_DAC0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_DAC0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_DAC0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_DAC0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DAC0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_DAC0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_DAC0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_DAC0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_DAC0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DAC0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_DAC0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_FLEXCAN0_CLKSEL - FLEXCAN0 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_FLEXCAN0_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_FLEXCAN0_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b011..CLK_IN + * 0b010..FRO_HF_DIV + */ +#define MRCC_MRCC_FLEXCAN0_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN0_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_FLEXCAN0_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_FLEXCAN0_CLKDIV - FLEXCAN0 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_FLEXCAN0_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_FLEXCAN0_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_FLEXCAN0_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN0_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_FLEXCAN0_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_FLEXCAN0_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_FLEXCAN0_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_FLEXCAN0_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN0_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_FLEXCAN0_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_FLEXCAN0_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_FLEXCAN0_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_FLEXCAN0_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN0_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_FLEXCAN0_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_FLEXCAN0_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_FLEXCAN0_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_FLEXCAN0_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FLEXCAN0_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_FLEXCAN0_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPI2C2_CLKSEL - LPI2C2 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPI2C2_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPI2C2_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b101..CLK_1M + * 0b011..CLK_IN + * 0b010..FRO_HF_DIV + * 0b000..FRO_12M + */ +#define MRCC_MRCC_LPI2C2_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C2_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPI2C2_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPI2C2_CLKDIV - LPI2C2 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPI2C2_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPI2C2_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPI2C2_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C2_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPI2C2_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPI2C2_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPI2C2_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPI2C2_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C2_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPI2C2_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPI2C2_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPI2C2_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPI2C2_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C2_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPI2C2_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPI2C2_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPI2C2_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPI2C2_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C2_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPI2C2_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_LPI2C3_CLKSEL - LPI2C3 clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_LPI2C3_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_LPI2C3_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b101..CLK_1M + * 0b011..CLK_IN + * 0b010..FRO_HF_DIV + * 0b000..FRO_12M + */ +#define MRCC_MRCC_LPI2C3_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C3_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_LPI2C3_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_LPI2C3_CLKDIV - LPI2C3 clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_LPI2C3_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_LPI2C3_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_LPI2C3_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C3_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_LPI2C3_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_LPI2C3_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_LPI2C3_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_LPI2C3_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C3_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_LPI2C3_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_LPI2C3_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_LPI2C3_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_LPI2C3_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C3_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_LPI2C3_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_LPI2C3_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_LPI2C3_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_LPI2C3_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_LPI2C3_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_LPI2C3_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_DBG_TRACE_CLKSEL - DBG_TRACE clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_DBG_TRACE_CLKSEL_MUX_MASK (0x3U) +#define MRCC_MRCC_DBG_TRACE_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b11..Reserved1(NO Clock) + * 0b10..CLK_16K + * 0b01..CLK_1M + * 0b00..CPU_CLK + */ +#define MRCC_MRCC_DBG_TRACE_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_DBG_TRACE_CLKDIV - DBG_TRACE clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_DBG_TRACE_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_DBG_TRACE_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_DBG_TRACE_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_DBG_TRACE_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_DBG_TRACE_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_DBG_TRACE_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_DBG_TRACE_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_DBG_TRACE_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_DBG_TRACE_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_DBG_TRACE_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_CLKOUT_CLKSEL - CLKOUT clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_CLKOUT_CLKSEL_MUX_MASK (0x7U) +#define MRCC_MRCC_CLKOUT_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b111..Reserved(NO Clock) + * 0b110..SLOW_CLK + * 0b011..CLK_16K + * 0b010..CLK_IN + * 0b001..FRO_HF_DIV + * 0b000..FRO_12M + */ +#define MRCC_MRCC_CLKOUT_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_CLKOUT_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_CLKOUT_CLKDIV - CLKOUT clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_CLKOUT_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_CLKOUT_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_CLKOUT_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_CLKOUT_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_CLKOUT_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_CLKOUT_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_CLKOUT_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_CLKOUT_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_CLKOUT_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_CLKOUT_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_CLKOUT_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_CLKOUT_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_CLKOUT_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_SYSTICK_CLKSEL - SYSTICK clock selection control */ +/*! @{ */ + +#define MRCC_MRCC_SYSTICK_CLKSEL_MUX_MASK (0x3U) +#define MRCC_MRCC_SYSTICK_CLKSEL_MUX_SHIFT (0U) +/*! MUX - Functional Clock Mux Select + * 0b11..Reserved1(NO Clock) + * 0b10..CLK_16K + * 0b01..CLK_1M + * 0b00..CPU_CLK + */ +#define MRCC_MRCC_SYSTICK_CLKSEL_MUX(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SYSTICK_CLKSEL_MUX_SHIFT)) & MRCC_MRCC_SYSTICK_CLKSEL_MUX_MASK) +/*! @} */ + +/*! @name MRCC_SYSTICK_CLKDIV - SYSTICK clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_SYSTICK_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_SYSTICK_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_SYSTICK_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SYSTICK_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_SYSTICK_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_SYSTICK_CLKDIV_RESET_MASK (0x20000000U) +#define MRCC_MRCC_SYSTICK_CLKDIV_RESET_SHIFT (29U) +/*! RESET - Reset divider counter + * 0b0..Divider isn't reset + * 0b1..Divider is reset + */ +#define MRCC_MRCC_SYSTICK_CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SYSTICK_CLKDIV_RESET_SHIFT)) & MRCC_MRCC_SYSTICK_CLKDIV_RESET_MASK) + +#define MRCC_MRCC_SYSTICK_CLKDIV_HALT_MASK (0x40000000U) +#define MRCC_MRCC_SYSTICK_CLKDIV_HALT_SHIFT (30U) +/*! HALT - Halt divider counter + * 0b0..Divider clock is running + * 0b1..Divider clock is stopped + */ +#define MRCC_MRCC_SYSTICK_CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SYSTICK_CLKDIV_HALT_SHIFT)) & MRCC_MRCC_SYSTICK_CLKDIV_HALT_MASK) + +#define MRCC_MRCC_SYSTICK_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_SYSTICK_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_SYSTICK_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_SYSTICK_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_SYSTICK_CLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name MRCC_FRO_HF_DIV_CLKDIV - FRO_HF_DIV clock divider control */ +/*! @{ */ + +#define MRCC_MRCC_FRO_HF_DIV_CLKDIV_DIV_MASK (0xFU) +#define MRCC_MRCC_FRO_HF_DIV_CLKDIV_DIV_SHIFT (0U) +/*! DIV - Functional Clock Divider */ +#define MRCC_MRCC_FRO_HF_DIV_CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FRO_HF_DIV_CLKDIV_DIV_SHIFT)) & MRCC_MRCC_FRO_HF_DIV_CLKDIV_DIV_MASK) + +#define MRCC_MRCC_FRO_HF_DIV_CLKDIV_UNSTAB_MASK (0x80000000U) +#define MRCC_MRCC_FRO_HF_DIV_CLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b0..Divider clock is stable + * 0b1..Clock frequency isn't stable + */ +#define MRCC_MRCC_FRO_HF_DIV_CLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << MRCC_MRCC_FRO_HF_DIV_CLKDIV_UNSTAB_SHIFT)) & MRCC_MRCC_FRO_HF_DIV_CLKDIV_UNSTAB_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MRCC_Register_Masks */ + + +/* MRCC - Peripheral instance base addresses */ +/** Peripheral MRCC0 base address */ +#define MRCC0_BASE (0x40091000u) +/** Peripheral MRCC0 base pointer */ +#define MRCC0 ((MRCC_Type *)MRCC0_BASE) +/** Array initializer of MRCC peripheral base addresses */ +#define MRCC_BASE_ADDRS { MRCC0_BASE } +/** Array initializer of MRCC peripheral base pointers */ +#define MRCC_BASE_PTRS { MRCC0 } + +/*! + * @} + */ /* end of group MRCC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OPAMP Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OPAMP_Peripheral_Access_Layer OPAMP Peripheral Access Layer + * @{ + */ + +/** OPAMP - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t OPAMP_CTR; /**< OPAMP Control, offset: 0x8 */ +} OPAMP_Type; + +/* ---------------------------------------------------------------------------- + -- OPAMP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OPAMP_Register_Masks OPAMP Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define OPAMP_VERID_FEATURE_MASK (0xFFFFU) +#define OPAMP_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number */ +#define OPAMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_VERID_FEATURE_SHIFT)) & OPAMP_VERID_FEATURE_MASK) + +#define OPAMP_VERID_MINOR_MASK (0xFF0000U) +#define OPAMP_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define OPAMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_VERID_MINOR_SHIFT)) & OPAMP_VERID_MINOR_MASK) + +#define OPAMP_VERID_MAJOR_MASK (0xFF000000U) +#define OPAMP_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define OPAMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_VERID_MAJOR_SHIFT)) & OPAMP_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define OPAMP_PARAM_PGA_FUNCTION_MASK (0x1U) +#define OPAMP_PARAM_PGA_FUNCTION_SHIFT (0U) +/*! PGA_FUNCTION - PGA Function Option + * 0b0..Core amplifier enabled + * 0b1..PGA function enabled + */ +#define OPAMP_PARAM_PGA_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_PARAM_PGA_FUNCTION_SHIFT)) & OPAMP_PARAM_PGA_FUNCTION_MASK) +/*! @} */ + +/*! @name OPAMP_CTR - OPAMP Control */ +/*! @{ */ + +#define OPAMP_OPAMP_CTR_EN_MASK (0x1U) +#define OPAMP_OPAMP_CTR_EN_SHIFT (0U) +/*! EN - OPAMP Enable + * 0b0..Disable + * 0b1..Enable + */ +#define OPAMP_OPAMP_CTR_EN(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_EN_SHIFT)) & OPAMP_OPAMP_CTR_EN_MASK) + +#define OPAMP_OPAMP_CTR_MODE_MASK (0x2U) +#define OPAMP_OPAMP_CTR_MODE_SHIFT (1U) +/*! MODE - Mode Selection + * 0b0..High performance mode + * 0b1..Low power mode + */ +#define OPAMP_OPAMP_CTR_MODE(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_MODE_SHIFT)) & OPAMP_OPAMP_CTR_MODE_MASK) + +#define OPAMP_OPAMP_CTR_BIASC_MASK (0xCU) +#define OPAMP_OPAMP_CTR_BIASC_SHIFT (2U) +/*! BIASC - Bias Current Trim Selection + * 0b00..Default + * 0b01..Increase current + * 0b10..Decrease current + * 0b11..Further decrease current + */ +#define OPAMP_OPAMP_CTR_BIASC(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_BIASC_SHIFT)) & OPAMP_OPAMP_CTR_BIASC_MASK) + +#define OPAMP_OPAMP_CTR_INTREF_MASK (0x30U) +#define OPAMP_OPAMP_CTR_INTREF_SHIFT (4U) +/*! INTREF - Provide OPAMP rail to rail voltage selection + * 0b00..Select OPAMP input rail to rail voltage from 0 to VDD_ANA + * 0b01..Select OPAMP input rail to rail voltage from 0 to VDD_ANA-0.8V + * 0b10..Select OPAMP input rail to rail voltage from 0.8V to VDD_ANA + * 0b11..Not allowed + */ +#define OPAMP_OPAMP_CTR_INTREF(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_INTREF_SHIFT)) & OPAMP_OPAMP_CTR_INTREF_MASK) + +#define OPAMP_OPAMP_CTR_TRIGMD_MASK (0x100U) +#define OPAMP_OPAMP_CTR_TRIGMD_SHIFT (8U) +/*! TRIGMD - Trigger Mode + * 0b0..Disable + * 0b1..Enable + */ +#define OPAMP_OPAMP_CTR_TRIGMD(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_TRIGMD_SHIFT)) & OPAMP_OPAMP_CTR_TRIGMD_MASK) + +#define OPAMP_OPAMP_CTR_INPSEL_MASK (0x200U) +#define OPAMP_OPAMP_CTR_INPSEL_SHIFT (9U) +/*! INPSEL - Positive Input Channel Selection + * 0b0..When OPAMP is not in trigger mode, select positive input 0 (INP0) + * 0b1..When OPAMP is not in trigger mode, select positive input 1 (INP1) + */ +#define OPAMP_OPAMP_CTR_INPSEL(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_INPSEL_SHIFT)) & OPAMP_OPAMP_CTR_INPSEL_MASK) + +#define OPAMP_OPAMP_CTR_INPF_MASK (0x1000U) +#define OPAMP_OPAMP_CTR_INPF_SHIFT (12U) +/*! INPF - Positive Input Connection Status + * 0b0..Positive input 0 (INP0) + * 0b1..Positive input 1 (INP1) + */ +#define OPAMP_OPAMP_CTR_INPF(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_INPF_SHIFT)) & OPAMP_OPAMP_CTR_INPF_MASK) + +#define OPAMP_OPAMP_CTR_BUFEN_MASK (0x10000U) +#define OPAMP_OPAMP_CTR_BUFEN_SHIFT (16U) +/*! BUFEN - Reference Buffer + * 0b0..Disables + * 0b1..Enables + */ +#define OPAMP_OPAMP_CTR_BUFEN(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_BUFEN_SHIFT)) & OPAMP_OPAMP_CTR_BUFEN_MASK) + +#define OPAMP_OPAMP_CTR_PREF_MASK (0x60000U) +#define OPAMP_OPAMP_CTR_PREF_SHIFT (17U) +/*! PREF - Positive Reference Voltage Selection + * 0b00..Input 0 + * 0b01..Input 1 + * 0b10..Input 2 + * 0b11..Input 3 + */ +#define OPAMP_OPAMP_CTR_PREF(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_PREF_SHIFT)) & OPAMP_OPAMP_CTR_PREF_MASK) + +#define OPAMP_OPAMP_CTR_ADCSW1_MASK (0x100000U) +#define OPAMP_OPAMP_CTR_ADCSW1_SHIFT (20U) +/*! ADCSW1 - Measure Switch 1 + * 0b0..Measure negative gain resistor ladder voltage switch off + * 0b1..Measure negative gain resistor ladder voltage switch on + */ +#define OPAMP_OPAMP_CTR_ADCSW1(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_ADCSW1_SHIFT)) & OPAMP_OPAMP_CTR_ADCSW1_MASK) + +#define OPAMP_OPAMP_CTR_ADCSW2_MASK (0x200000U) +#define OPAMP_OPAMP_CTR_ADCSW2_SHIFT (21U) +/*! ADCSW2 - Measure Switch 2 + * 0b0..Measure positive gain resistor ladder reference voltage switch off + * 0b1..Measure positive gain resistor ladder reference voltage switch on + */ +#define OPAMP_OPAMP_CTR_ADCSW2(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_ADCSW2_SHIFT)) & OPAMP_OPAMP_CTR_ADCSW2_MASK) + +#define OPAMP_OPAMP_CTR_OUTSW_MASK (0x400000U) +#define OPAMP_OPAMP_CTR_OUTSW_SHIFT (22U) +/*! OUTSW - Output Switch + * 0b0..OPAMP out to negative gain resistor ladder switch off + * 0b1..OPAMP out to negative gain resistor ladder switch on + */ +#define OPAMP_OPAMP_CTR_OUTSW(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_OUTSW_SHIFT)) & OPAMP_OPAMP_CTR_OUTSW_MASK) + +#define OPAMP_OPAMP_CTR_PGAIN_MASK (0x7000000U) +#define OPAMP_OPAMP_CTR_PGAIN_SHIFT (24U) +/*! PGAIN - Positive PGA Selection + * 0b000..Positive input 1 (INP1) + * 0b001..Pgain=1 + * 0b010..Pgain=2 + * 0b011..Pgain=4 + * 0b100..Pgain=8 + * 0b101..Pgain=16 + * 0b110..Pgain=33 + * 0b111..Pgain=64 + */ +#define OPAMP_OPAMP_CTR_PGAIN(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_PGAIN_SHIFT)) & OPAMP_OPAMP_CTR_PGAIN_MASK) + +#define OPAMP_OPAMP_CTR_NGAIN_MASK (0x70000000U) +#define OPAMP_OPAMP_CTR_NGAIN_SHIFT (28U) +/*! NGAIN - Negative PGA Selection + * 0b000..Buffer + * 0b001..Ngain=1 + * 0b010..Ngain=2 + * 0b011..Ngain=4 + * 0b100..Ngain=8 + * 0b101..Ngain=16 + * 0b110..Ngain=33 + * 0b111..Ngain=64 + */ +#define OPAMP_OPAMP_CTR_NGAIN(x) (((uint32_t)(((uint32_t)(x)) << OPAMP_OPAMP_CTR_NGAIN_SHIFT)) & OPAMP_OPAMP_CTR_NGAIN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OPAMP_Register_Masks */ + + +/* OPAMP - Peripheral instance base addresses */ +/** Peripheral OPAMP0 base address */ +#define OPAMP0_BASE (0x400B7000u) +/** Peripheral OPAMP0 base pointer */ +#define OPAMP0 ((OPAMP_Type *)OPAMP0_BASE) +/** Array initializer of OPAMP peripheral base addresses */ +#define OPAMP_BASE_ADDRS { OPAMP0_BASE } +/** Array initializer of OPAMP peripheral base pointers */ +#define OPAMP_BASE_PTRS { OPAMP0 } + +/*! + * @} + */ /* end of group OPAMP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- OSTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Peripheral_Access_Layer OSTIMER Peripheral Access Layer + * @{ + */ + +/** OSTIMER - Register Layout Typedef */ +typedef struct { + __I uint32_t EVTIMERL; /**< EVTIMER Low, offset: 0x0 */ + __I uint32_t EVTIMERH; /**< EVTIMER High, offset: 0x4 */ + __I uint32_t CAPTURE_L; /**< Local Capture Low for CPU, offset: 0x8 */ + __I uint32_t CAPTURE_H; /**< Local Capture High for CPU, offset: 0xC */ + __IO uint32_t MATCH_L; /**< Local Match Low for CPU, offset: 0x10 */ + __IO uint32_t MATCH_H; /**< Local Match High for CPU, offset: 0x14 */ + uint8_t RESERVED_0[4]; + __IO uint32_t OSEVENT_CTRL; /**< OSTIMER Control for CPU, offset: 0x1C */ +} OSTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- OSTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OSTIMER_Register_Masks OSTIMER Register Masks + * @{ + */ + +/*! @name EVTIMERL - EVTIMER Low */ +/*! @{ */ + +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - EVTimer Count Value */ +#define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name EVTIMERH - EVTIMER High */ +/*! @{ */ + +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU) +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - EVTimer Count Value */ +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) +/*! @} */ + +/*! @name CAPTURE_L - Local Capture Low for CPU */ +/*! @{ */ + +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - EVTimer Capture Value */ +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK) +/*! @} */ + +/*! @name CAPTURE_H - Local Capture High for CPU */ +/*! @{ */ + +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK (0x3FFU) +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - EVTimer Capture Value */ +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK) +/*! @} */ + +/*! @name MATCH_L - Local Match Low for CPU */ +/*! @{ */ + +#define OSTIMER_MATCH_L_MATCH_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - EVTimer Match Value */ +#define OSTIMER_MATCH_L_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK) +/*! @} */ + +/*! @name MATCH_H - Local Match High for CPU */ +/*! @{ */ + +#define OSTIMER_MATCH_H_MATCH_VALUE_MASK (0x3FFU) +#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - EVTimer Match Value */ +#define OSTIMER_MATCH_H_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK) +/*! @} */ + +/*! @name OSEVENT_CTRL - OSTIMER Control for CPU */ +/*! @{ */ + +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) +/*! OSTIMER_INTRFLAG - Interrupt Flag */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) + +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) +/*! OSTIMER_INTENA - Interrupt or Wake-Up Request + * 0b0..Interrupts blocked + * 0b1..Interrupts enabled + */ +#define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) + +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK (0x4U) +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT (2U) +/*! MATCH_WR_RDY - EVTimer Match Write Ready */ +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK) + +#define OSTIMER_OSEVENT_CTRL_DEBUG_EN_MASK (0x8U) +#define OSTIMER_OSEVENT_CTRL_DEBUG_EN_SHIFT (3U) +/*! DEBUG_EN - Debug Enable + * 0b0..Disables + * 0b1..Enables + */ +#define OSTIMER_OSEVENT_CTRL_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_DEBUG_EN_SHIFT)) & OSTIMER_OSEVENT_CTRL_DEBUG_EN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group OSTIMER_Register_Masks */ + + +/* OSTIMER - Peripheral instance base addresses */ +/** Peripheral OSTIMER0 base address */ +#define OSTIMER0_BASE (0x400AD000u) +/** Peripheral OSTIMER0 base pointer */ +#define OSTIMER0 ((OSTIMER_Type *)OSTIMER0_BASE) +/** Array initializer of OSTIMER peripheral base addresses */ +#define OSTIMER_BASE_ADDRS { OSTIMER0_BASE } +/** Array initializer of OSTIMER peripheral base pointers */ +#define OSTIMER_BASE_PTRS { OSTIMER0 } +/** Interrupt vectors for the OSTIMER peripheral type */ +#define OSTIMER_IRQS { OS_EVENT_IRQn } + +/*! + * @} + */ /* end of group OSTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PORT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer + * @{ + */ + +/** PORT - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __O uint32_t GPCLR; /**< Global Pin Control Low, offset: 0x10 */ + __O uint32_t GPCHR; /**< Global Pin Control High, offset: 0x14 */ + uint8_t RESERVED_1[8]; + __IO uint32_t CONFIG; /**< Configuration, offset: 0x20 */ + uint8_t RESERVED_2[60]; + __IO uint32_t CALIB0; /**< Calibration 0, offset: 0x60, available only on: PORT0, PORT1, PORT3, PORT4 (missing on PORT2) */ + __IO uint32_t CALIB1; /**< Calibration 1, offset: 0x64, available only on: PORT0, PORT1, PORT3, PORT4 (missing on PORT2) */ + uint8_t RESERVED_3[24]; + __IO uint32_t PCR[32]; /**< Pin Control 0..Pin Control 31, array offset: 0x80, array step: 0x4 */ +} PORT_Type; + +/* ---------------------------------------------------------------------------- + -- PORT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PORT_Register_Masks PORT Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define PORT_VERID_FEATURE_MASK (0xFFFFU) +#define PORT_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Basic implementation + */ +#define PORT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << PORT_VERID_FEATURE_SHIFT)) & PORT_VERID_FEATURE_MASK) + +#define PORT_VERID_MINOR_MASK (0xFF0000U) +#define PORT_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define PORT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << PORT_VERID_MINOR_SHIFT)) & PORT_VERID_MINOR_MASK) + +#define PORT_VERID_MAJOR_MASK (0xFF000000U) +#define PORT_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define PORT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << PORT_VERID_MAJOR_SHIFT)) & PORT_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name GPCLR - Global Pin Control Low */ +/*! @{ */ + +#define PORT_GPCLR_GPWD_MASK (0xFFFFU) +#define PORT_GPCLR_GPWD_SHIFT (0U) +/*! GPWD - Global Pin Write Data */ +#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) + +#define PORT_GPCLR_GPWE0_MASK (0x10000U) +#define PORT_GPCLR_GPWE0_SHIFT (16U) +/*! GPWE0 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE0_SHIFT)) & PORT_GPCLR_GPWE0_MASK) + +#define PORT_GPCLR_GPWE1_MASK (0x20000U) +#define PORT_GPCLR_GPWE1_SHIFT (17U) +/*! GPWE1 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE1_SHIFT)) & PORT_GPCLR_GPWE1_MASK) + +#define PORT_GPCLR_GPWE2_MASK (0x40000U) +#define PORT_GPCLR_GPWE2_SHIFT (18U) +/*! GPWE2 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE2_SHIFT)) & PORT_GPCLR_GPWE2_MASK) + +#define PORT_GPCLR_GPWE3_MASK (0x80000U) +#define PORT_GPCLR_GPWE3_SHIFT (19U) +/*! GPWE3 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE3_SHIFT)) & PORT_GPCLR_GPWE3_MASK) + +#define PORT_GPCLR_GPWE4_MASK (0x100000U) +#define PORT_GPCLR_GPWE4_SHIFT (20U) +/*! GPWE4 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE4_SHIFT)) & PORT_GPCLR_GPWE4_MASK) + +#define PORT_GPCLR_GPWE5_MASK (0x200000U) +#define PORT_GPCLR_GPWE5_SHIFT (21U) +/*! GPWE5 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE5_SHIFT)) & PORT_GPCLR_GPWE5_MASK) + +#define PORT_GPCLR_GPWE6_MASK (0x400000U) +#define PORT_GPCLR_GPWE6_SHIFT (22U) +/*! GPWE6 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE6_SHIFT)) & PORT_GPCLR_GPWE6_MASK) + +#define PORT_GPCLR_GPWE7_MASK (0x800000U) +#define PORT_GPCLR_GPWE7_SHIFT (23U) +/*! GPWE7 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE7_SHIFT)) & PORT_GPCLR_GPWE7_MASK) + +#define PORT_GPCLR_GPWE8_MASK (0x1000000U) +#define PORT_GPCLR_GPWE8_SHIFT (24U) +/*! GPWE8 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE8(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE8_SHIFT)) & PORT_GPCLR_GPWE8_MASK) + +#define PORT_GPCLR_GPWE9_MASK (0x2000000U) +#define PORT_GPCLR_GPWE9_SHIFT (25U) +/*! GPWE9 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE9(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE9_SHIFT)) & PORT_GPCLR_GPWE9_MASK) + +#define PORT_GPCLR_GPWE10_MASK (0x4000000U) +#define PORT_GPCLR_GPWE10_SHIFT (26U) +/*! GPWE10 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE10(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE10_SHIFT)) & PORT_GPCLR_GPWE10_MASK) + +#define PORT_GPCLR_GPWE11_MASK (0x8000000U) +#define PORT_GPCLR_GPWE11_SHIFT (27U) +/*! GPWE11 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE11(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE11_SHIFT)) & PORT_GPCLR_GPWE11_MASK) + +#define PORT_GPCLR_GPWE12_MASK (0x10000000U) +#define PORT_GPCLR_GPWE12_SHIFT (28U) +/*! GPWE12 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE12(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE12_SHIFT)) & PORT_GPCLR_GPWE12_MASK) + +#define PORT_GPCLR_GPWE13_MASK (0x20000000U) +#define PORT_GPCLR_GPWE13_SHIFT (29U) +/*! GPWE13 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE13(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE13_SHIFT)) & PORT_GPCLR_GPWE13_MASK) + +#define PORT_GPCLR_GPWE14_MASK (0x40000000U) +#define PORT_GPCLR_GPWE14_SHIFT (30U) +/*! GPWE14 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE14(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE14_SHIFT)) & PORT_GPCLR_GPWE14_MASK) + +#define PORT_GPCLR_GPWE15_MASK (0x80000000U) +#define PORT_GPCLR_GPWE15_SHIFT (31U) +/*! GPWE15 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCLR_GPWE15(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE15_SHIFT)) & PORT_GPCLR_GPWE15_MASK) +/*! @} */ + +/*! @name GPCHR - Global Pin Control High */ +/*! @{ */ + +#define PORT_GPCHR_GPWD_MASK (0xFFFFU) +#define PORT_GPCHR_GPWD_SHIFT (0U) +/*! GPWD - Global Pin Write Data */ +#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) + +#define PORT_GPCHR_GPWE16_MASK (0x10000U) +#define PORT_GPCHR_GPWE16_SHIFT (16U) +/*! GPWE16 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE16(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE16_SHIFT)) & PORT_GPCHR_GPWE16_MASK) + +#define PORT_GPCHR_GPWE17_MASK (0x20000U) +#define PORT_GPCHR_GPWE17_SHIFT (17U) +/*! GPWE17 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE17(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE17_SHIFT)) & PORT_GPCHR_GPWE17_MASK) + +#define PORT_GPCHR_GPWE18_MASK (0x40000U) +#define PORT_GPCHR_GPWE18_SHIFT (18U) +/*! GPWE18 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE18(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE18_SHIFT)) & PORT_GPCHR_GPWE18_MASK) + +#define PORT_GPCHR_GPWE19_MASK (0x80000U) +#define PORT_GPCHR_GPWE19_SHIFT (19U) +/*! GPWE19 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE19(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE19_SHIFT)) & PORT_GPCHR_GPWE19_MASK) + +#define PORT_GPCHR_GPWE20_MASK (0x100000U) +#define PORT_GPCHR_GPWE20_SHIFT (20U) +/*! GPWE20 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE20(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE20_SHIFT)) & PORT_GPCHR_GPWE20_MASK) + +#define PORT_GPCHR_GPWE21_MASK (0x200000U) +#define PORT_GPCHR_GPWE21_SHIFT (21U) +/*! GPWE21 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE21(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE21_SHIFT)) & PORT_GPCHR_GPWE21_MASK) + +#define PORT_GPCHR_GPWE22_MASK (0x400000U) +#define PORT_GPCHR_GPWE22_SHIFT (22U) +/*! GPWE22 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE22(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE22_SHIFT)) & PORT_GPCHR_GPWE22_MASK) + +#define PORT_GPCHR_GPWE23_MASK (0x800000U) +#define PORT_GPCHR_GPWE23_SHIFT (23U) +/*! GPWE23 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE23(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE23_SHIFT)) & PORT_GPCHR_GPWE23_MASK) + +#define PORT_GPCHR_GPWE24_MASK (0x1000000U) +#define PORT_GPCHR_GPWE24_SHIFT (24U) +/*! GPWE24 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE24(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE24_SHIFT)) & PORT_GPCHR_GPWE24_MASK) + +#define PORT_GPCHR_GPWE25_MASK (0x2000000U) +#define PORT_GPCHR_GPWE25_SHIFT (25U) +/*! GPWE25 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE25(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE25_SHIFT)) & PORT_GPCHR_GPWE25_MASK) + +#define PORT_GPCHR_GPWE26_MASK (0x4000000U) +#define PORT_GPCHR_GPWE26_SHIFT (26U) +/*! GPWE26 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE26(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE26_SHIFT)) & PORT_GPCHR_GPWE26_MASK) + +#define PORT_GPCHR_GPWE27_MASK (0x8000000U) +#define PORT_GPCHR_GPWE27_SHIFT (27U) +/*! GPWE27 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE27(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE27_SHIFT)) & PORT_GPCHR_GPWE27_MASK) + +#define PORT_GPCHR_GPWE28_MASK (0x10000000U) +#define PORT_GPCHR_GPWE28_SHIFT (28U) +/*! GPWE28 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE28(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE28_SHIFT)) & PORT_GPCHR_GPWE28_MASK) + +#define PORT_GPCHR_GPWE29_MASK (0x20000000U) +#define PORT_GPCHR_GPWE29_SHIFT (29U) +/*! GPWE29 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE29(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE29_SHIFT)) & PORT_GPCHR_GPWE29_MASK) + +#define PORT_GPCHR_GPWE30_MASK (0x40000000U) +#define PORT_GPCHR_GPWE30_SHIFT (30U) +/*! GPWE30 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE30(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE30_SHIFT)) & PORT_GPCHR_GPWE30_MASK) + +#define PORT_GPCHR_GPWE31_MASK (0x80000000U) +#define PORT_GPCHR_GPWE31_SHIFT (31U) +/*! GPWE31 - Global Pin Write Enable + * 0b0..Not updated + * 0b1..Updated + */ +#define PORT_GPCHR_GPWE31(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE31_SHIFT)) & PORT_GPCHR_GPWE31_MASK) +/*! @} */ + +/*! @name CONFIG - Configuration */ +/*! @{ */ + +#define PORT_CONFIG_RANGE_MASK (0x1U) +#define PORT_CONFIG_RANGE_SHIFT (0U) +/*! RANGE - Port Voltage Range + * 0b0..1.71 V-3.6 V + * 0b1..2.70 V-3.6 V + */ +#define PORT_CONFIG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << PORT_CONFIG_RANGE_SHIFT)) & PORT_CONFIG_RANGE_MASK) +/*! @} */ + +/*! @name CALIB0 - Calibration 0 */ +/*! @{ */ + +#define PORT_CALIB0_NCAL_MASK (0x3FU) +#define PORT_CALIB0_NCAL_SHIFT (0U) +/*! NCAL - Calibration of NMOS Output Driver */ +#define PORT_CALIB0_NCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB0_NCAL_SHIFT)) & PORT_CALIB0_NCAL_MASK) + +#define PORT_CALIB0_PCAL_MASK (0x3F0000U) +#define PORT_CALIB0_PCAL_SHIFT (16U) +/*! PCAL - Calibration of PMOS Output Driver */ +#define PORT_CALIB0_PCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB0_PCAL_SHIFT)) & PORT_CALIB0_PCAL_MASK) +/*! @} */ + +/*! @name CALIB1 - Calibration 1 */ +/*! @{ */ + +#define PORT_CALIB1_NCAL_MASK (0x3FU) +#define PORT_CALIB1_NCAL_SHIFT (0U) +/*! NCAL - Calibration of NMOS Output Driver */ +#define PORT_CALIB1_NCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB1_NCAL_SHIFT)) & PORT_CALIB1_NCAL_MASK) + +#define PORT_CALIB1_PCAL_MASK (0x3F0000U) +#define PORT_CALIB1_PCAL_SHIFT (16U) +/*! PCAL - Calibration of PMOS Output Driver */ +#define PORT_CALIB1_PCAL(x) (((uint32_t)(((uint32_t)(x)) << PORT_CALIB1_PCAL_SHIFT)) & PORT_CALIB1_PCAL_MASK) +/*! @} */ + +/*! @name PCR - Pin Control 0..Pin Control 31 */ +/*! @{ */ + +#define PORT_PCR_PS_MASK (0x1U) +#define PORT_PCR_PS_SHIFT (0U) +/*! PS - Pull Select + * 0b0..Enables internal pulldown resistor + * 0b1..Enables internal pullup resistor + */ +#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) + +#define PORT_PCR_PE_MASK (0x2U) +#define PORT_PCR_PE_SHIFT (1U) +/*! PE - Pull Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) + +#define PORT_PCR_PV_MASK (0x4U) +#define PORT_PCR_PV_SHIFT (2U) +/*! PV - Pull Value + * 0b0..Low + * 0b1..High + */ +#define PORT_PCR_PV(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PV_SHIFT)) & PORT_PCR_PV_MASK) + +#define PORT_PCR_SRE_MASK (0x8U) +#define PORT_PCR_SRE_SHIFT (3U) +/*! SRE - Slew Rate Enable + * 0b0..Fast + * 0b1..Slow + */ +#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) + +#define PORT_PCR_PFE_MASK (0x10U) +#define PORT_PCR_PFE_SHIFT (4U) +/*! PFE - Passive Filter Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) + +#define PORT_PCR_ODE_MASK (0x20U) +#define PORT_PCR_ODE_SHIFT (5U) +/*! ODE - Open Drain Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK) + +#define PORT_PCR_DSE_MASK (0x40U) +#define PORT_PCR_DSE_SHIFT (6U) +/*! DSE - Drive Strength Enable + * 0b0..Low + * 0b1..High + */ +#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK) + +#define PORT_PCR_DSE1_MASK (0x80U) +#define PORT_PCR_DSE1_SHIFT (7U) +/*! DSE1 - Drive Strength Enable + * 0b0..Normal + * 0b1..Double + */ +#define PORT_PCR_DSE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE1_SHIFT)) & PORT_PCR_DSE1_MASK) + +#define PORT_PCR_MUX_MASK (0xF00U) /* Merged from fields with different position or width, of widths (2, 3, 4), largest definition used */ +#define PORT_PCR_MUX_SHIFT (8U) +/*! MUX - Pin Multiplex Control + * 0b0000..Alternative 0 (GPIO) + * 0b0001..Alternative 1 (chip-specific) + * 0b0010..Alternative 2 (chip-specific) + * 0b0011..Alternative 3 (chip-specific) + * 0b0100..Alternative 4 (chip-specific) + * 0b0101..Alternative 5 (chip-specific) + * 0b0110..Alternative 6 (chip-specific) + * 0b0111..Alternative 7 (chip-specific) + * 0b1000..Alternative 8 (chip-specific) + * 0b1001..Alternative 9 (chip-specific) + * 0b1010..Alternative 10 (chip-specific) + * 0b1011..Alternative 11 (chip-specific) + * 0b1100..Alternative 12 (chip-specific) + * 0b1101..Alternative 13 (chip-specific) + */ +#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) /* Merged from fields with different position or width, of widths (2, 3, 4), largest definition used */ + +#define PORT_PCR_IBE_MASK (0x1000U) +#define PORT_PCR_IBE_SHIFT (12U) +/*! IBE - Input Buffer Enable + * 0b0..Disables + * 0b1..Enables + */ +#define PORT_PCR_IBE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IBE_SHIFT)) & PORT_PCR_IBE_MASK) + +#define PORT_PCR_INV_MASK (0x2000U) +#define PORT_PCR_INV_SHIFT (13U) +/*! INV - Invert Input + * 0b0..Does not invert + * 0b1..Inverts + */ +#define PORT_PCR_INV(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_INV_SHIFT)) & PORT_PCR_INV_MASK) + +#define PORT_PCR_LK_MASK (0x8000U) +#define PORT_PCR_LK_SHIFT (15U) +/*! LK - Lock Register + * 0b0..Does not lock + * 0b1..Locks + */ +#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK) +/*! @} */ + +/* The count of PORT_PCR */ +#define PORT_PCR_COUNT (32U) + + +/*! + * @} + */ /* end of group PORT_Register_Masks */ + + +/* PORT - Peripheral instance base addresses */ +/** Peripheral PORT0 base address */ +#define PORT0_BASE (0x400BC000u) +/** Peripheral PORT0 base pointer */ +#define PORT0 ((PORT_Type *)PORT0_BASE) +/** Peripheral PORT1 base address */ +#define PORT1_BASE (0x400BD000u) +/** Peripheral PORT1 base pointer */ +#define PORT1 ((PORT_Type *)PORT1_BASE) +/** Peripheral PORT2 base address */ +#define PORT2_BASE (0x400BE000u) +/** Peripheral PORT2 base pointer */ +#define PORT2 ((PORT_Type *)PORT2_BASE) +/** Peripheral PORT3 base address */ +#define PORT3_BASE (0x400BF000u) +/** Peripheral PORT3 base pointer */ +#define PORT3 ((PORT_Type *)PORT3_BASE) +/** Peripheral PORT4 base address */ +#define PORT4_BASE (0x400C0000u) +/** Peripheral PORT4 base pointer */ +#define PORT4 ((PORT_Type *)PORT4_BASE) +/** Array initializer of PORT peripheral base addresses */ +#define PORT_BASE_ADDRS { PORT0_BASE, PORT1_BASE, PORT2_BASE, PORT3_BASE, PORT4_BASE } +/** Array initializer of PORT peripheral base pointers */ +#define PORT_BASE_PTRS { PORT0, PORT1, PORT2, PORT3, PORT4 } + +/*! + * @} + */ /* end of group PORT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PWM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer + * @{ + */ + +/** PWM - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x60 */ + __I uint16_t CNT; /**< Counter Register, array offset: 0x0, array step: 0x60 */ + __IO uint16_t INIT; /**< Initial Count Register, array offset: 0x2, array step: 0x60 */ + __IO uint16_t CTRL2; /**< Control 2 Register, array offset: 0x4, array step: 0x60 */ + __IO uint16_t CTRL; /**< Control Register, array offset: 0x6, array step: 0x60 */ + uint8_t RESERVED_0[2]; + __IO uint16_t VAL0; /**< Value Register 0, array offset: 0xA, array step: 0x60 */ + uint8_t RESERVED_1[2]; + __IO uint16_t VAL1; /**< Value Register 1, array offset: 0xE, array step: 0x60 */ + uint8_t RESERVED_2[2]; + __IO uint16_t VAL2; /**< Value Register 2, array offset: 0x12, array step: 0x60 */ + uint8_t RESERVED_3[2]; + __IO uint16_t VAL3; /**< Value Register 3, array offset: 0x16, array step: 0x60 */ + uint8_t RESERVED_4[2]; + __IO uint16_t VAL4; /**< Value Register 4, array offset: 0x1A, array step: 0x60 */ + uint8_t RESERVED_5[2]; + __IO uint16_t VAL5; /**< Value Register 5, array offset: 0x1E, array step: 0x60 */ + uint8_t RESERVED_6[2]; + __IO uint16_t OCTRL; /**< Output Control Register, array offset: 0x22, array step: 0x60 */ + __IO uint16_t STS; /**< Status Register, array offset: 0x24, array step: 0x60 */ + __IO uint16_t INTEN; /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */ + __IO uint16_t DMAEN; /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */ + __IO uint16_t TCTRL; /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */ + __IO uint16_t DISMAP[1]; /**< Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2 */ + uint8_t RESERVED_7[2]; + __IO uint16_t DTCNT0; /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */ + __IO uint16_t DTCNT1; /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */ + uint8_t RESERVED_8[8]; + __IO uint16_t CAPTCTRLX; /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */ + __IO uint16_t CAPTCOMPX; /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */ + __I uint16_t CVAL0; /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */ + __I uint16_t CVAL0CYC; /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */ + __I uint16_t CVAL1; /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */ + __I uint16_t CVAL1CYC; /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */ + uint8_t RESERVED_9[16]; + __IO uint16_t PHASEDLY; /**< Phase Delay Register, array offset: 0x58, array step: 0x60, valid indices: [1-2] */ + uint8_t RESERVED_10[4]; + __IO uint16_t CAPTFILTX; /**< Capture PWM_X Input Filter Register, array offset: 0x5E, array step: 0x60 */ + } SM[3]; + uint8_t RESERVED_0[96]; + __IO uint16_t OUTEN; /**< Output Enable Register, offset: 0x180 */ + __IO uint16_t MASK; /**< Mask Register, offset: 0x182 */ + __IO uint16_t SWCOUT; /**< Software Controlled Output Register, offset: 0x184 */ + __IO uint16_t DTSRCSEL; /**< PWM Source Select Register, offset: 0x186 */ + __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ + __IO uint16_t MCTRL2; /**< Master Control 2 Register, offset: 0x18A */ + __IO uint16_t FCTRL; /**< Fault Control Register, offset: 0x18C */ + __IO uint16_t FSTS; /**< Fault Status Register, offset: 0x18E */ + __IO uint16_t FFILT; /**< Fault Filter Register, offset: 0x190 */ + __IO uint16_t FTST; /**< Fault Test Register, offset: 0x192 */ + __IO uint16_t FCTRL2; /**< Fault Control 2 Register, offset: 0x194 */ +} PWM_Type; + +/* ---------------------------------------------------------------------------- + -- PWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Register_Masks PWM Register Masks + * @{ + */ + +/*! @name CNT - Counter Register */ +/*! @{ */ + +#define PWM_CNT_CNT_MASK (0xFFFFU) +#define PWM_CNT_CNT_SHIFT (0U) +/*! CNT - Counter Register Bits */ +#define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CNT */ +#define PWM_CNT_COUNT (3U) + +/*! @name INIT - Initial Count Register */ +/*! @{ */ + +#define PWM_INIT_INIT_MASK (0xFFFFU) +#define PWM_INIT_INIT_SHIFT (0U) +/*! INIT - Initial Count Register Bits */ +#define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK) +/*! @} */ + +/* The count of PWM_INIT */ +#define PWM_INIT_COUNT (3U) + +/*! @name CTRL2 - Control 2 Register */ +/*! @{ */ + +#define PWM_CTRL2_CLK_SEL_MASK (0x3U) +#define PWM_CTRL2_CLK_SEL_SHIFT (0U) +/*! CLK_SEL - Clock Source Select + * 0b00..The IPBus clock is used as the clock for the local prescaler and counter. + * 0b01..EXT_CLK is used as the clock for the local prescaler and counter. + * 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This + * setting should not be used in submodule 0 as it forces the clock to logic 0. + * 0b11..Reserved + */ +#define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK) + +#define PWM_CTRL2_RELOAD_SEL_MASK (0x4U) +#define PWM_CTRL2_RELOAD_SEL_SHIFT (2U) +/*! RELOAD_SEL - Reload Source Select + * 0b0..The local RELOAD signal is used to reload registers. + * 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used + * in submodule 0 as it forces the RELOAD signal to logic 0. + */ +#define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK) + +#define PWM_CTRL2_FORCE_SEL_MASK (0x38U) +#define PWM_CTRL2_FORCE_SEL_SHIFT (3U) +/*! FORCE_SEL - Force Select + * 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates. + * 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in + * submodule 0 as it holds the FORCE OUTPUT signal to logic 0. + * 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK. + * 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should + * not be used in submodule0 as it holds the FORCE OUTPUT signal to logic 0. + * 0b100..The local sync signal from this submodule is used to force updates. + * 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in + * submodule0 as it holds the FORCE OUTPUT signal to logic 0. + * 0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates. + * 0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates. + */ +#define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK) + +#define PWM_CTRL2_FORCE_MASK (0x40U) +#define PWM_CTRL2_FORCE_SHIFT (6U) +/*! FORCE - Force Initialization */ +#define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK) + +#define PWM_CTRL2_FRCEN_MASK (0x80U) +#define PWM_CTRL2_FRCEN_SHIFT (7U) +/*! FRCEN - Force Enable + * 0b0..Initialization from a FORCE_OUT is disabled. + * 0b1..Initialization from a FORCE_OUT is enabled. + */ +#define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK) + +#define PWM_CTRL2_INIT_SEL_MASK (0x300U) +#define PWM_CTRL2_INIT_SEL_SHIFT (8U) +/*! INIT_SEL - Initialization Control Select + * 0b00..Local sync (PWM_X) causes initialization. + * 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as + * it forces the INIT signal to logic 0. The submodule counter will only re-initialize when a master reload + * occurs. + * 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it forces the INIT signal to logic 0. + * 0b11..EXT_SYNC causes initialization. + */ +#define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK) + +#define PWM_CTRL2_PWMX_INIT_MASK (0x400U) +#define PWM_CTRL2_PWMX_INIT_SHIFT (10U) +/*! PWMX_INIT - PWM_X Initial Value */ +#define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK) + +#define PWM_CTRL2_PWM45_INIT_MASK (0x800U) +#define PWM_CTRL2_PWM45_INIT_SHIFT (11U) +/*! PWM45_INIT - PWM45 Initial Value */ +#define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK) + +#define PWM_CTRL2_PWM23_INIT_MASK (0x1000U) +#define PWM_CTRL2_PWM23_INIT_SHIFT (12U) +/*! PWM23_INIT - PWM23 Initial Value */ +#define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK) + +#define PWM_CTRL2_INDEP_MASK (0x2000U) +#define PWM_CTRL2_INDEP_SHIFT (13U) +/*! INDEP - Independent or Complementary Pair Operation + * 0b0..PWM_A and PWM_B form a complementary PWM pair. + * 0b1..PWM_A and PWM_B outputs are independent PWMs. + */ +#define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK) + +#define PWM_CTRL2_DBGEN_MASK (0x8000U) +#define PWM_CTRL2_DBGEN_SHIFT (15U) +/*! DBGEN - Debug Enable */ +#define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK) +/*! @} */ + +/* The count of PWM_CTRL2 */ +#define PWM_CTRL2_COUNT (3U) + +/*! @name CTRL - Control Register */ +/*! @{ */ + +#define PWM_CTRL_DBLEN_MASK (0x1U) +#define PWM_CTRL_DBLEN_SHIFT (0U) +/*! DBLEN - Double Switching Enable + * 0b0..Double switching disabled. + * 0b1..Double switching enabled. + */ +#define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK) + +#define PWM_CTRL_DBLX_MASK (0x2U) +#define PWM_CTRL_DBLX_SHIFT (1U) +/*! DBLX - PWM_X Double Switching Enable + * 0b0..PWM_X double pulse disabled. + * 0b1..PWM_X double pulse enabled. + */ +#define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK) + +#define PWM_CTRL_LDMOD_MASK (0x4U) +#define PWM_CTRL_LDMOD_SHIFT (2U) +/*! LDMOD - Load Mode Select + * 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. + * 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. + * In this case, it is not necessary to set CTRL[FULL] or CTRL[HALF]. + */ +#define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK) + +#define PWM_CTRL_SPLIT_MASK (0x8U) +#define PWM_CTRL_SPLIT_SHIFT (3U) +/*! SPLIT - Split the DBLPWM signal to PWM_A and PWM_B + * 0b0..DBLPWM is not split. PWM_A and PWM_B each have double pulses. + * 0b1..DBLPWM is split to PWM_A and PWM_B. + */ +#define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK) + +#define PWM_CTRL_PRSC_MASK (0x70U) +#define PWM_CTRL_PRSC_SHIFT (4U) +/*! PRSC - Prescaler + * 0b000..Prescaler 1 + * 0b001..Prescaler 2 + * 0b010..Prescaler 4 + * 0b011..Prescaler 8 + * 0b100..Prescaler 16 + * 0b101..Prescaler 32 + * 0b110..Prescaler 64 + * 0b111..Prescaler 128 + */ +#define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK) + +#define PWM_CTRL_COMPMODE_MASK (0x80U) +#define PWM_CTRL_COMPMODE_SHIFT (7U) +/*! COMPMODE - Compare Mode + * 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges + * are only produced when the counter is equal to one of the VAL* register values. This implies that a PWM_A + * output that is high at the end of a period maintains this state until a match with VAL3 clears the output + * in the following period. + * 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This + * means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register + * values. This implies that a PWM_A output that is high at the end of a period could go low at the start of the + * next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. + */ +#define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK) + +#define PWM_CTRL_DT_MASK (0x300U) +#define PWM_CTRL_DT_SHIFT (8U) +/*! DT - Deadtime */ +#define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK) + +#define PWM_CTRL_FULL_MASK (0x400U) +#define PWM_CTRL_FULL_SHIFT (10U) +/*! FULL - Full Cycle Reload + * 0b0..Full-cycle reloads disabled. + * 0b1..Full-cycle reloads enabled. + */ +#define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK) + +#define PWM_CTRL_HALF_MASK (0x800U) +#define PWM_CTRL_HALF_SHIFT (11U) +/*! HALF - Half Cycle Reload + * 0b0..Half-cycle reloads disabled. + * 0b1..Half-cycle reloads enabled. + */ +#define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK) + +#define PWM_CTRL_LDFQ_MASK (0xF000U) +#define PWM_CTRL_LDFQ_SHIFT (12U) +/*! LDFQ - Load Frequency + * 0b0000..Every PWM opportunity + * 0b0001..Every 2 PWM opportunities + * 0b0010..Every 3 PWM opportunities + * 0b0011..Every 4 PWM opportunities + * 0b0100..Every 5 PWM opportunities + * 0b0101..Every 6 PWM opportunities + * 0b0110..Every 7 PWM opportunities + * 0b0111..Every 8 PWM opportunities + * 0b1000..Every 9 PWM opportunities + * 0b1001..Every 10 PWM opportunities + * 0b1010..Every 11 PWM opportunities + * 0b1011..Every 12 PWM opportunities + * 0b1100..Every 13 PWM opportunities + * 0b1101..Every 14 PWM opportunities + * 0b1110..Every 15 PWM opportunities + * 0b1111..Every 16 PWM opportunities + */ +#define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK) +/*! @} */ + +/* The count of PWM_CTRL */ +#define PWM_CTRL_COUNT (3U) + +/*! @name VAL0 - Value Register 0 */ +/*! @{ */ + +#define PWM_VAL0_VAL0_MASK (0xFFFFU) +#define PWM_VAL0_VAL0_SHIFT (0U) +/*! VAL0 - Value 0 */ +#define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK) +/*! @} */ + +/* The count of PWM_VAL0 */ +#define PWM_VAL0_COUNT (3U) + +/*! @name VAL1 - Value Register 1 */ +/*! @{ */ + +#define PWM_VAL1_VAL1_MASK (0xFFFFU) +#define PWM_VAL1_VAL1_SHIFT (0U) +/*! VAL1 - Value 1 */ +#define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK) +/*! @} */ + +/* The count of PWM_VAL1 */ +#define PWM_VAL1_COUNT (3U) + +/*! @name VAL2 - Value Register 2 */ +/*! @{ */ + +#define PWM_VAL2_VAL2_MASK (0xFFFFU) +#define PWM_VAL2_VAL2_SHIFT (0U) +/*! VAL2 - Value 2 */ +#define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK) +/*! @} */ + +/* The count of PWM_VAL2 */ +#define PWM_VAL2_COUNT (3U) + +/*! @name VAL3 - Value Register 3 */ +/*! @{ */ + +#define PWM_VAL3_VAL3_MASK (0xFFFFU) +#define PWM_VAL3_VAL3_SHIFT (0U) +/*! VAL3 - Value 3 */ +#define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK) +/*! @} */ + +/* The count of PWM_VAL3 */ +#define PWM_VAL3_COUNT (3U) + +/*! @name VAL4 - Value Register 4 */ +/*! @{ */ + +#define PWM_VAL4_VAL4_MASK (0xFFFFU) +#define PWM_VAL4_VAL4_SHIFT (0U) +/*! VAL4 - Value 4 */ +#define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK) +/*! @} */ + +/* The count of PWM_VAL4 */ +#define PWM_VAL4_COUNT (3U) + +/*! @name VAL5 - Value Register 5 */ +/*! @{ */ + +#define PWM_VAL5_VAL5_MASK (0xFFFFU) +#define PWM_VAL5_VAL5_SHIFT (0U) +/*! VAL5 - Value 5 */ +#define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK) +/*! @} */ + +/* The count of PWM_VAL5 */ +#define PWM_VAL5_COUNT (3U) + +/*! @name OCTRL - Output Control Register */ +/*! @{ */ + +#define PWM_OCTRL_PWMXFS_MASK (0x3U) +#define PWM_OCTRL_PWMXFS_SHIFT (0U) +/*! PWMXFS - PWM_X Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10, 0b11..Output is put in a high-impedance state. + */ +#define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK) + +#define PWM_OCTRL_PWMBFS_MASK (0xCU) +#define PWM_OCTRL_PWMBFS_SHIFT (2U) +/*! PWMBFS - PWM_B Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10, 0b11..Output is put in a high-impedance state. + */ +#define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK) + +#define PWM_OCTRL_PWMAFS_MASK (0x30U) +#define PWM_OCTRL_PWMAFS_SHIFT (4U) +/*! PWMAFS - PWM_A Fault State + * 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. + * 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. + * 0b10, 0b11..Output is put in a high-impedance state. + */ +#define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK) + +#define PWM_OCTRL_POLX_MASK (0x100U) +#define PWM_OCTRL_POLX_SHIFT (8U) +/*! POLX - PWM_X Output Polarity + * 0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. + * 0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK) + +#define PWM_OCTRL_POLB_MASK (0x200U) +#define PWM_OCTRL_POLB_SHIFT (9U) +/*! POLB - PWM_B Output Polarity + * 0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. + * 0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK) + +#define PWM_OCTRL_POLA_MASK (0x400U) +#define PWM_OCTRL_POLA_SHIFT (10U) +/*! POLA - PWM_A Output Polarity + * 0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. + * 0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. + */ +#define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK) + +#define PWM_OCTRL_PWMX_IN_MASK (0x2000U) +#define PWM_OCTRL_PWMX_IN_SHIFT (13U) +/*! PWMX_IN - PWM_X Input */ +#define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK) + +#define PWM_OCTRL_PWMB_IN_MASK (0x4000U) +#define PWM_OCTRL_PWMB_IN_SHIFT (14U) +/*! PWMB_IN - PWM_B Input */ +#define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK) + +#define PWM_OCTRL_PWMA_IN_MASK (0x8000U) +#define PWM_OCTRL_PWMA_IN_SHIFT (15U) +/*! PWMA_IN - PWM_A Input */ +#define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK) +/*! @} */ + +/* The count of PWM_OCTRL */ +#define PWM_OCTRL_COUNT (3U) + +/*! @name STS - Status Register */ +/*! @{ */ + +#define PWM_STS_CMPF_MASK (0x3FU) +#define PWM_STS_CMPF_SHIFT (0U) +/*! CMPF - Compare Flags + * 0b000000..No compare event has occurred for a particular VALx value. + * 0b000001..A compare event has occurred for a particular VALx value. + */ +#define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK) + +#define PWM_STS_CFX0_MASK (0x40U) +#define PWM_STS_CFX0_SHIFT (6U) +/*! CFX0 - Capture Flag X0 */ +#define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK) + +#define PWM_STS_CFX1_MASK (0x80U) +#define PWM_STS_CFX1_SHIFT (7U) +/*! CFX1 - Capture Flag X1 */ +#define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK) + +#define PWM_STS_RF_MASK (0x1000U) +#define PWM_STS_RF_SHIFT (12U) +/*! RF - Reload Flag + * 0b0..No new reload cycle since last STS[RF] clearing + * 0b1..New reload cycle since last STS[RF] clearing + */ +#define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK) + +#define PWM_STS_REF_MASK (0x2000U) +#define PWM_STS_REF_SHIFT (13U) +/*! REF - Reload Error Flag + * 0b0..No reload error occurred. + * 0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. + */ +#define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK) + +#define PWM_STS_RUF_MASK (0x4000U) +#define PWM_STS_RUF_SHIFT (14U) +/*! RUF - Registers Updated Flag + * 0b0..No register update has occurred since last reload. + * 0b1..At least one of the double buffered registers has been updated since the last reload. + */ +#define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK) +/*! @} */ + +/* The count of PWM_STS */ +#define PWM_STS_COUNT (3U) + +/*! @name INTEN - Interrupt Enable Register */ +/*! @{ */ + +#define PWM_INTEN_CMPIE_MASK (0x3FU) +#define PWM_INTEN_CMPIE_SHIFT (0U) +/*! CMPIE - Compare Interrupt Enables + * 0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request. + * 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request. + */ +#define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) + +#define PWM_INTEN_CX0IE_MASK (0x40U) +#define PWM_INTEN_CX0IE_SHIFT (6U) +/*! CX0IE - Capture X 0 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX0]. + * 0b1..Interrupt request enabled for STS[CFX0]. + */ +#define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) + +#define PWM_INTEN_CX1IE_MASK (0x80U) +#define PWM_INTEN_CX1IE_SHIFT (7U) +/*! CX1IE - Capture X 1 Interrupt Enable + * 0b0..Interrupt request disabled for STS[CFX1]. + * 0b1..Interrupt request enabled for STS[CFX1]. + */ +#define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) + +#define PWM_INTEN_RIE_MASK (0x1000U) +#define PWM_INTEN_RIE_SHIFT (12U) +/*! RIE - Reload Interrupt Enable + * 0b0..STS[RF] CPU interrupt requests disabled + * 0b1..STS[RF] CPU interrupt requests enabled + */ +#define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) + +#define PWM_INTEN_REIE_MASK (0x2000U) +#define PWM_INTEN_REIE_SHIFT (13U) +/*! REIE - Reload Error Interrupt Enable + * 0b0..STS[REF] CPU interrupt requests disabled + * 0b1..STS[REF] CPU interrupt requests enabled + */ +#define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) +/*! @} */ + +/* The count of PWM_INTEN */ +#define PWM_INTEN_COUNT (3U) + +/*! @name DMAEN - DMA Enable Register */ +/*! @{ */ + +#define PWM_DMAEN_CX0DE_MASK (0x1U) +#define PWM_DMAEN_CX0DE_SHIFT (0U) +/*! CX0DE - Capture X0 FIFO DMA Enable */ +#define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK) + +#define PWM_DMAEN_CX1DE_MASK (0x2U) +#define PWM_DMAEN_CX1DE_SHIFT (1U) +/*! CX1DE - Capture X1 FIFO DMA Enable */ +#define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK) + +#define PWM_DMAEN_CAPTDE_MASK (0xC0U) +#define PWM_DMAEN_CAPTDE_SHIFT (6U) +/*! CAPTDE - Capture DMA Enable Source Select + * 0b00..Read DMA requests disabled. + * 0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], + * DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to be set to determine which + * watermark(s) the DMA request is sensitive. + * 0b10..A local synchronization (VAL1 matches counter) sets the read DMA request. + * 0b11..A local reload (STS[RF] being set) sets the read DMA request. + */ +#define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK) + +#define PWM_DMAEN_FAND_MASK (0x100U) +#define PWM_DMAEN_FAND_SHIFT (8U) +/*! FAND - FIFO Watermark AND Control + * 0b0..Selected FIFO watermarks are OR'ed together. + * 0b1..Selected FIFO watermarks are AND'ed together. + */ +#define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK) + +#define PWM_DMAEN_VALDE_MASK (0x200U) +#define PWM_DMAEN_VALDE_SHIFT (9U) +/*! VALDE - Value Registers DMA Enable + * 0b0..DMA write requests disabled + * 0b1..Enabled + */ +#define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK) +/*! @} */ + +/* The count of PWM_DMAEN */ +#define PWM_DMAEN_COUNT (3U) + +/*! @name TCTRL - Output Trigger Control Register */ +/*! @{ */ + +#define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU) +#define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U) +/*! OUT_TRIG_EN - Output Trigger Enables + * 0bxxxxx1..PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value. + * 0bxxxx1x..PWM_OUT_TRIG1 will set when the counter value matches the VAL1 value. + * 0bxxx1xx..PWM_OUT_TRIG0 will set when the counter value matches the VAL2 value. + * 0bxx1xxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL3 value. + * 0bx1xxxx..PWM_OUT_TRIG0 will set when the counter value matches the VAL4 value. + * 0b1xxxxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL5 value. + */ +#define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK) + +#define PWM_TCTRL_TRGFRQ_MASK (0x1000U) +#define PWM_TCTRL_TRGFRQ_SHIFT (12U) +/*! TRGFRQ - Trigger Frequency + * 0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. + * 0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM + * is not reloaded every period due to CTRL[LDFQ] being non-zero. + */ +#define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK) + +#define PWM_TCTRL_PWBOT1_MASK (0x4000U) +#define PWM_TCTRL_PWBOT1_SHIFT (14U) +/*! PWBOT1 - Mux Output Trigger 1 Source Select + * 0b0..Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port. + * 0b1..Route the PWM_B output to the PWM_MUX_TRIG1 port. + */ +#define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK) + +#define PWM_TCTRL_PWAOT0_MASK (0x8000U) +#define PWM_TCTRL_PWAOT0_SHIFT (15U) +/*! PWAOT0 - Mux Output Trigger 0 Source Select + * 0b0..Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port. + * 0b1..Route the PWM_A output to the PWM_MUX_TRIG0 port. + */ +#define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK) +/*! @} */ + +/* The count of PWM_TCTRL */ +#define PWM_TCTRL_COUNT (3U) + +/*! @name DISMAP - Fault Disable Mapping Register 0 */ +/*! @{ */ + +#define PWM_DISMAP_DIS0A_MASK (0xFU) +#define PWM_DISMAP_DIS0A_SHIFT (0U) +/*! DIS0A - PWM_A Fault Disable Mask 0 */ +#define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK) + +#define PWM_DISMAP_DIS0B_MASK (0xF0U) +#define PWM_DISMAP_DIS0B_SHIFT (4U) +/*! DIS0B - PWM_B Fault Disable Mask 0 */ +#define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK) + +#define PWM_DISMAP_DIS0X_MASK (0xF00U) +#define PWM_DISMAP_DIS0X_SHIFT (8U) +/*! DIS0X - PWM_X Fault Disable Mask 0 */ +#define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK) +/*! @} */ + +/* The count of PWM_DISMAP */ +#define PWM_DISMAP_COUNT (3U) + +/* The count of PWM_DISMAP */ +#define PWM_DISMAP_COUNT2 (1U) + +/*! @name DTCNT0 - Deadtime Count Register 0 */ +/*! @{ */ + +#define PWM_DTCNT0_DTCNT0_MASK (0x7FFU) +#define PWM_DTCNT0_DTCNT0_SHIFT (0U) +/*! DTCNT0 - Deadtime Count Register 0 */ +#define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK) +/*! @} */ + +/* The count of PWM_DTCNT0 */ +#define PWM_DTCNT0_COUNT (3U) + +/*! @name DTCNT1 - Deadtime Count Register 1 */ +/*! @{ */ + +#define PWM_DTCNT1_DTCNT1_MASK (0x7FFU) +#define PWM_DTCNT1_DTCNT1_SHIFT (0U) +/*! DTCNT1 - Deadtime Count Register 1 */ +#define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK) +/*! @} */ + +/* The count of PWM_DTCNT1 */ +#define PWM_DTCNT1_COUNT (3U) + +/*! @name CAPTCTRLX - Capture Control X Register */ +/*! @{ */ + +#define PWM_CAPTCTRLX_ARMX_MASK (0x1U) +#define PWM_CAPTCTRLX_ARMX_SHIFT (0U) +/*! ARMX - Arm X + * 0b0..Input capture operation is disabled. + * 0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. + */ +#define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK) + +#define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U) +#define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U) +/*! ONESHOTX - One Shot Mode Aux + * 0b0..Free Running + * 0b1..One Shot + */ +#define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK) + +#define PWM_CAPTCTRLX_EDGX0_MASK (0xCU) +#define PWM_CAPTCTRLX_EDGX0_SHIFT (2U) +/*! EDGX0 - Edge X 0 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK) + +#define PWM_CAPTCTRLX_EDGX1_MASK (0x30U) +#define PWM_CAPTCTRLX_EDGX1_SHIFT (4U) +/*! EDGX1 - Edge X 1 + * 0b00..Disabled + * 0b01..Capture falling edges + * 0b10..Capture rising edges + * 0b11..Capture any edge + */ +#define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK) + +#define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U) +#define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U) +/*! INP_SELX - Input Select X + * 0b0..Raw PWM_X input signal selected as source. + * 0b1..Edge Counter + */ +#define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK) + +#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U) +#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U) +/*! EDGCNTX_EN - Edge Counter X Enable + * 0b0..Edge counter disabled and held in reset + * 0b1..Edge counter enabled + */ +#define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK) + +#define PWM_CAPTCTRLX_CFXWM_MASK (0x300U) +#define PWM_CAPTCTRLX_CFXWM_SHIFT (8U) +/*! CFXWM - Capture X FIFOs Water Mark */ +#define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK) + +#define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U) +#define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U) +/*! CX0CNT - Capture X0 FIFO Word Count */ +#define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK) + +#define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U) +#define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U) +/*! CX1CNT - Capture X1 FIFO Word Count */ +#define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTCTRLX */ +#define PWM_CAPTCTRLX_COUNT (3U) + +/*! @name CAPTCOMPX - Capture Compare X Register */ +/*! @{ */ + +#define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU) +#define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U) +/*! EDGCMPX - Edge Compare X */ +#define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK) + +#define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U) +#define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U) +/*! EDGCNTX - Edge Counter X */ +#define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK) +/*! @} */ + +/* The count of PWM_CAPTCOMPX */ +#define PWM_CAPTCOMPX_COUNT (3U) + +/*! @name CVAL0 - Capture Value 0 Register */ +/*! @{ */ + +#define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU) +#define PWM_CVAL0_CAPTVAL0_SHIFT (0U) +/*! CAPTVAL0 - Capture Value 0 */ +#define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK) +/*! @} */ + +/* The count of PWM_CVAL0 */ +#define PWM_CVAL0_COUNT (3U) + +/*! @name CVAL0CYC - Capture Value 0 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU) +#define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U) +/*! CVAL0CYC - Capture Value 0 Cycle */ +#define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL0CYC */ +#define PWM_CVAL0CYC_COUNT (3U) + +/*! @name CVAL1 - Capture Value 1 Register */ +/*! @{ */ + +#define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU) +#define PWM_CVAL1_CAPTVAL1_SHIFT (0U) +/*! CAPTVAL1 - Capture Value 1 */ +#define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK) +/*! @} */ + +/* The count of PWM_CVAL1 */ +#define PWM_CVAL1_COUNT (3U) + +/*! @name CVAL1CYC - Capture Value 1 Cycle Register */ +/*! @{ */ + +#define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU) +#define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U) +/*! CVAL1CYC - Capture Value 1 Cycle */ +#define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK) +/*! @} */ + +/* The count of PWM_CVAL1CYC */ +#define PWM_CVAL1CYC_COUNT (3U) + +/*! @name PHASEDLY - Phase Delay Register */ +/*! @{ */ + +#define PWM_PHASEDLY_PHASEDLY_MASK (0xFFFFU) +#define PWM_PHASEDLY_PHASEDLY_SHIFT (0U) +/*! PHASEDLY - Initial Count Register Bits */ +#define PWM_PHASEDLY_PHASEDLY(x) (((uint16_t)(((uint16_t)(x)) << PWM_PHASEDLY_PHASEDLY_SHIFT)) & PWM_PHASEDLY_PHASEDLY_MASK) +/*! @} */ + +/* The count of PWM_PHASEDLY */ +#define PWM_PHASEDLY_COUNT (3U) + +/*! @name CAPTFILTX - Capture PWM_X Input Filter Register */ +/*! @{ */ + +#define PWM_CAPTFILTX_CAPTX_FILT_PER_MASK (0xFFU) +#define PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT (0U) +/*! CAPTX_FILT_PER - Input Capture Filter Period */ +#define PWM_CAPTFILTX_CAPTX_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_PER_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_PER_MASK) + +#define PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK (0x700U) +#define PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT (8U) +/*! CAPTX_FILT_CNT - Input Capture Filter Count */ +#define PWM_CAPTFILTX_CAPTX_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTFILTX_CAPTX_FILT_CNT_SHIFT)) & PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK) +/*! @} */ + +/* The count of PWM_CAPTFILTX */ +#define PWM_CAPTFILTX_COUNT (3U) + +/*! @name OUTEN - Output Enable Register */ +/*! @{ */ + +#define PWM_OUTEN_PWMX_EN_MASK (0x7U) +#define PWM_OUTEN_PWMX_EN_SHIFT (0U) +/*! PWMX_EN - PWM_X Output Enables */ +#define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK) + +#define PWM_OUTEN_PWMB_EN_MASK (0x70U) +#define PWM_OUTEN_PWMB_EN_SHIFT (4U) +/*! PWMB_EN - PWM_B Output Enables */ +#define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK) + +#define PWM_OUTEN_PWMA_EN_MASK (0x700U) +#define PWM_OUTEN_PWMA_EN_SHIFT (8U) +/*! PWMA_EN - PWM_A Output Enables */ +#define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK) +/*! @} */ + +/*! @name MASK - Mask Register */ +/*! @{ */ + +#define PWM_MASK_MASKX_MASK (0x7U) +#define PWM_MASK_MASKX_SHIFT (0U) +/*! MASKX - PWM_X Masks */ +#define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK) + +#define PWM_MASK_MASKB_MASK (0x70U) +#define PWM_MASK_MASKB_SHIFT (4U) +/*! MASKB - PWM_B Masks */ +#define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK) + +#define PWM_MASK_MASKA_MASK (0x700U) +#define PWM_MASK_MASKA_SHIFT (8U) +/*! MASKA - PWM_A Masks */ +#define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK) + +#define PWM_MASK_UPDATE_MASK_MASK (0x7000U) +#define PWM_MASK_UPDATE_MASK_SHIFT (12U) +/*! UPDATE_MASK - Update Mask Bits Immediately */ +#define PWM_MASK_UPDATE_MASK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK) +/*! @} */ + +/*! @name SWCOUT - Software Controlled Output Register */ +/*! @{ */ + +#define PWM_SWCOUT_SM0OUT45_MASK (0x1U) +#define PWM_SWCOUT_SM0OUT45_SHIFT (0U) +/*! SM0OUT45 - Submodule 0 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. + */ +#define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK) + +#define PWM_SWCOUT_SM0OUT23_MASK (0x2U) +#define PWM_SWCOUT_SM0OUT23_SHIFT (1U) +/*! SM0OUT23 - Submodule 0 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. + */ +#define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK) + +#define PWM_SWCOUT_SM1OUT45_MASK (0x4U) +#define PWM_SWCOUT_SM1OUT45_SHIFT (2U) +/*! SM1OUT45 - Submodule 1 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. + */ +#define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK) + +#define PWM_SWCOUT_SM1OUT23_MASK (0x8U) +#define PWM_SWCOUT_SM1OUT23_SHIFT (3U) +/*! SM1OUT23 - Submodule 1 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. + */ +#define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK) + +#define PWM_SWCOUT_SM2OUT45_MASK (0x10U) +#define PWM_SWCOUT_SM2OUT45_SHIFT (4U) +/*! SM2OUT45 - Submodule 2 Software Controlled Output 45 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. + */ +#define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK) + +#define PWM_SWCOUT_SM2OUT23_MASK (0x20U) +#define PWM_SWCOUT_SM2OUT23_SHIFT (5U) +/*! SM2OUT23 - Submodule 2 Software Controlled Output 23 + * 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. + * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. + */ +#define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK) +/*! @} */ + +/*! @name DTSRCSEL - PWM Source Select Register */ +/*! @{ */ + +#define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U) +#define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U) +/*! SM0SEL45 - Submodule 0 PWM45 Control Select + * 0b00..Generated SM0PWM45 signal used by the deadtime logic. + * 0b01..Inverted generated SM0PWM45 signal used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT45] used by the deadtime logic. + * 0b11..Reserved + */ +#define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK) + +#define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU) +#define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U) +/*! SM0SEL23 - Submodule 0 PWM23 Control Select + * 0b00..Generated SM0PWM23 signal used by the deadtime logic. + * 0b01..Inverted generated SM0PWM23 signal used by the deadtime logic. + * 0b10..SWCOUT[SM0OUT23] used by the deadtime logic. + * 0b11..PWM0_EXTA signal used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK) + +#define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U) +#define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U) +/*! SM1SEL45 - Submodule 1 PWM45 Control Select + * 0b00..Generated SM1PWM45 signal used by the deadtime logic. + * 0b01..Inverted generated SM1PWM45 signal used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT45] used by the deadtime logic. + * 0b11..Reserved + */ +#define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK) + +#define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U) +#define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U) +/*! SM1SEL23 - Submodule 1 PWM23 Control Select + * 0b00..Generated SM1PWM23 signal used by the deadtime logic. + * 0b01..Inverted generated SM1PWM23 signal used by the deadtime logic. + * 0b10..SWCOUT[SM1OUT23] used by the deadtime logic. + * 0b11..PWM1_EXTA signal used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK) + +#define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U) +#define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U) +/*! SM2SEL45 - Submodule 2 PWM45 Control Select + * 0b00..Generated SM2PWM45 signal used by the deadtime logic. + * 0b01..Inverted generated SM2PWM45 signal used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT45] used by the deadtime logic. + * 0b11..Reserved + */ +#define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK) + +#define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U) +#define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U) +/*! SM2SEL23 - Submodule 2 PWM23 Control Select + * 0b00..Generated SM2PWM23 signal used by the deadtime logic. + * 0b01..Inverted generated SM2PWM23 signal used by the deadtime logic. + * 0b10..SWCOUT[SM2OUT23] used by the deadtime logic. + * 0b11..PWM2_EXTA signal used by the deadtime logic. + */ +#define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK) +/*! @} */ + +/*! @name MCTRL - Master Control Register */ +/*! @{ */ + +#define PWM_MCTRL_LDOK_MASK (0x7U) +#define PWM_MCTRL_LDOK_SHIFT (0U) +/*! LDOK - Load Okay + * 0b000..Do not load new values. + * 0b001..Load prescaler, modulus, and PWM values of the corresponding submodule. + */ +#define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK) + +#define PWM_MCTRL_CLDOK_MASK (0x70U) +#define PWM_MCTRL_CLDOK_SHIFT (4U) +/*! CLDOK - Clear Load Okay */ +#define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK) + +#define PWM_MCTRL_RUN_MASK (0x700U) +#define PWM_MCTRL_RUN_SHIFT (8U) +/*! RUN - Run + * 0b000..PWM counter is stopped, but PWM outputs hold the current state. + * 0b001..PWM counter is started in the corresponding submodule. + */ +#define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK) + +#define PWM_MCTRL_IPOL_MASK (0x7000U) +#define PWM_MCTRL_IPOL_SHIFT (12U) +/*! IPOL - Current Polarity + * 0b000..PWM23 is used to generate complementary PWM pair in the corresponding submodule. + * 0b001..PWM45 is used to generate complementary PWM pair in the corresponding submodule. + */ +#define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK) +/*! @} */ + +/*! @name MCTRL2 - Master Control 2 Register */ +/*! @{ */ + +#define PWM_MCTRL2_WRPROT_MASK (0xCU) +#define PWM_MCTRL2_WRPROT_SHIFT (2U) +/*! WRPROT - Write protect + * 0b00..Write protection off (default). + * 0b01..Write protection on. + * 0b10..Write protection off and locked until chip reset. + * 0b11..Write protection on and locked until chip reset. + */ +#define PWM_MCTRL2_WRPROT(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_WRPROT_SHIFT)) & PWM_MCTRL2_WRPROT_MASK) + +#define PWM_MCTRL2_STRETCH_CNT_PRSC_MASK (0xC0U) +#define PWM_MCTRL2_STRETCH_CNT_PRSC_SHIFT (6U) +/*! STRETCH_CNT_PRSC - Stretch IPBus clock count prescaler for mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig + * 0b00..Stretch count is zero, no stretch. + * 0b01..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 2 IPBus clock period. + * 0b10..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 4 IPBus clock period. + * 0b11..Stretch mux0_trig/mux1_trig/out0_trig/out1_trig/pwma_trig/pwmb_trig for 8 IPBus clock period. + */ +#define PWM_MCTRL2_STRETCH_CNT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_STRETCH_CNT_PRSC_SHIFT)) & PWM_MCTRL2_STRETCH_CNT_PRSC_MASK) +/*! @} */ + +/*! @name FCTRL - Fault Control Register */ +/*! @{ */ + +#define PWM_FCTRL_FIE_MASK (0xFU) +#define PWM_FCTRL_FIE_SHIFT (0U) +/*! FIE - Fault Interrupt Enables + * 0b0000..FAULTx CPU interrupt requests disabled. + * 0b0001..FAULTx CPU interrupt requests enabled. + */ +#define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK) + +#define PWM_FCTRL_FSAFE_MASK (0xF0U) +#define PWM_FCTRL_FSAFE_SHIFT (4U) +/*! FSAFE - Fault Safety Mode + * 0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the + * start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard + * to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is set, then the fault condition cannot be + * cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input + * signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in + * DISMAPn). + * 0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and + * FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and + * FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared. + */ +#define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK) + +#define PWM_FCTRL_FAUTO_MASK (0xF00U) +#define PWM_FCTRL_FAUTO_SHIFT (8U) +/*! FAUTO - Automatic Fault Clearing + * 0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear + * at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL]. If + * neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled + * by FCTRL[FSAFE]. + * 0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at + * the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without + * regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition + * cannot be cleared. + */ +#define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK) + +#define PWM_FCTRL_FLVL_MASK (0xF000U) +#define PWM_FCTRL_FLVL_SHIFT (12U) +/*! FLVL - Fault Level + * 0b0000..A logic 0 on the fault input indicates a fault condition. + * 0b0001..A logic 1 on the fault input indicates a fault condition. + */ +#define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK) +/*! @} */ + +/*! @name FSTS - Fault Status Register */ +/*! @{ */ + +#define PWM_FSTS_FFLAG_MASK (0xFU) +#define PWM_FSTS_FFLAG_SHIFT (0U) +/*! FFLAG - Fault Flags + * 0b0000..No fault on the FAULTx pin. + * 0b0001..Fault on the FAULTx pin. + */ +#define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK) + +#define PWM_FSTS_FFULL_MASK (0xF0U) +#define PWM_FSTS_FFULL_SHIFT (4U) +/*! FFULL - Full Cycle + * 0b0000..PWM outputs are not re-enabled at the start of a full cycle + * 0b0001..PWM outputs are re-enabled at the start of a full cycle + */ +#define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK) + +#define PWM_FSTS_FFPIN_MASK (0xF00U) +#define PWM_FSTS_FFPIN_SHIFT (8U) +/*! FFPIN - Filtered Fault Pins */ +#define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK) + +#define PWM_FSTS_FHALF_MASK (0xF000U) +#define PWM_FSTS_FHALF_SHIFT (12U) +/*! FHALF - Half Cycle Fault Recovery + * 0b0000..PWM outputs are not re-enabled at the start of a half cycle. + * 0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0). + */ +#define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK) +/*! @} */ + +/*! @name FFILT - Fault Filter Register */ +/*! @{ */ + +#define PWM_FFILT_FILT_PER_MASK (0xFFU) +#define PWM_FFILT_FILT_PER_SHIFT (0U) +/*! FILT_PER - Fault Filter Period */ +#define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK) + +#define PWM_FFILT_FILT_CNT_MASK (0x700U) +#define PWM_FFILT_FILT_CNT_SHIFT (8U) +/*! FILT_CNT - Fault Filter Count */ +#define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK) + +#define PWM_FFILT_GSTR_MASK (0x8000U) +#define PWM_FFILT_GSTR_SHIFT (15U) +/*! GSTR - Fault Glitch Stretch Enable + * 0b0..Fault input glitch stretching is disabled. + * 0b1..Input fault signals are stretched to at least 2 IPBus clock cycles. + */ +#define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK) +/*! @} */ + +/*! @name FTST - Fault Test Register */ +/*! @{ */ + +#define PWM_FTST_FTEST_MASK (0x1U) +#define PWM_FTST_FTEST_SHIFT (0U) +/*! FTEST - Fault Test + * 0b0..No fault + * 0b1..Cause a simulated fault + */ +#define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK) +/*! @} */ + +/*! @name FCTRL2 - Fault Control 2 Register */ +/*! @{ */ + +#define PWM_FCTRL2_NOCOMB_MASK (0xFU) +#define PWM_FCTRL2_NOCOMB_SHIFT (0U) +/*! NOCOMB - No Combinational Path From Fault Input To PWM Output + * 0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined + * with the filtered and latched fault signals to disable the PWM outputs. + * 0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered + * and latched fault signals are used to disable the PWM outputs. + */ +#define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PWM_Register_Masks */ + + +/* PWM - Peripheral instance base addresses */ +/** Peripheral FLEXPWM0 base address */ +#define FLEXPWM0_BASE (0x400A9000u) +/** Peripheral FLEXPWM0 base pointer */ +#define FLEXPWM0 ((PWM_Type *)FLEXPWM0_BASE) +/** Peripheral FLEXPWM1 base address */ +#define FLEXPWM1_BASE (0x400AA000u) +/** Peripheral FLEXPWM1 base pointer */ +#define FLEXPWM1 ((PWM_Type *)FLEXPWM1_BASE) +/** Array initializer of PWM peripheral base addresses */ +#define PWM_BASE_ADDRS { FLEXPWM0_BASE, FLEXPWM1_BASE } +/** Array initializer of PWM peripheral base pointers */ +#define PWM_BASE_PTRS { FLEXPWM0, FLEXPWM1 } +/** Interrupt vectors for the PWM peripheral type */ +#define PWM_CMP_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn } } +#define PWM_RELOAD_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn } } +#define PWM_CAPTURE_IRQS { { FLEXPWM0_SUBMODULE0_IRQn, FLEXPWM0_SUBMODULE1_IRQn, FLEXPWM0_SUBMODULE2_IRQn }, { FLEXPWM1_SUBMODULE0_IRQn, FLEXPWM1_SUBMODULE1_IRQn, FLEXPWM1_SUBMODULE2_IRQn } } +#define PWM_FAULT_IRQS { FLEXPWM0_FAULT_IRQn, FLEXPWM1_FAULT_IRQn } +#define PWM_RELOAD_ERROR_IRQS { FLEXPWM0_RELOAD_ERROR_IRQn, FLEXPWM1_RELOAD_ERROR_IRQn } + +/*! + * @} + */ /* end of group PWM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SCG Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCG_Peripheral_Access_Layer SCG Peripheral Access Layer + * @{ + */ + +/** SCG - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t TRIM_LOCK; /**< Trim Lock register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __I uint32_t CSR; /**< Clock Status Register, offset: 0x10 */ + __IO uint32_t RCCR; /**< Run Clock Control Register, offset: 0x14 */ + uint8_t RESERVED_1[232]; + __IO uint32_t SOSCCSR; /**< SOSC Control Status Register, offset: 0x100 */ + uint8_t RESERVED_2[4]; + __IO uint32_t SOSCCFG; /**< SOSC Configuration Register, offset: 0x108 */ + uint8_t RESERVED_3[244]; + __IO uint32_t SIRCCSR; /**< SIRC Control Status Register, offset: 0x200 */ + uint8_t RESERVED_4[8]; + __IO uint32_t SIRCTCFG; /**< SIRC Trim Configuration Register, offset: 0x20C */ + __IO uint32_t SIRCTRIM; /**< SIRC Trim Register, offset: 0x210 */ + uint8_t RESERVED_5[4]; + __IO uint32_t SIRCSTAT; /**< SIRC Auto-trimming Status Register, offset: 0x218 */ + uint8_t RESERVED_6[228]; + __IO uint32_t FIRCCSR; /**< FIRC Control Status Register, offset: 0x300 */ + uint8_t RESERVED_7[4]; + __IO uint32_t FIRCCFG; /**< FIRC Configuration Register, offset: 0x308 */ + __IO uint32_t FIRCTCFG; /**< FIRC Trim Configuration Register, offset: 0x30C */ + __IO uint32_t FIRCTRIM; /**< FIRC Trim Register, offset: 0x310 */ + uint8_t RESERVED_8[4]; + __IO uint32_t FIRCSTAT; /**< FIRC Auto-trimming Status Register, offset: 0x318 */ + __IO uint32_t FIRCATC1; /**< FIRC Auto-trimming Counter 1, offset: 0x31C */ + __IO uint32_t FIRCATC2; /**< FIRC Auto-trimming Counter 2, offset: 0x320 */ + __IO uint32_t FIRCATC3; /**< FIRC Auto-trimming Counter 2, offset: 0x324 */ + uint8_t RESERVED_9[216]; + __IO uint32_t ROSCCSR; /**< ROSC Control Status Register, offset: 0x400 */ +} SCG_Type; + +/* ---------------------------------------------------------------------------- + -- SCG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCG_Register_Masks SCG Register Masks + * @{ + */ + +/*! @name VERID - Version ID Register */ +/*! @{ */ + +#define SCG_VERID_VERSION_MASK (0xFFFFFFFFU) +#define SCG_VERID_VERSION_SHIFT (0U) +/*! VERSION - SCG Version Number */ +#define SCG_VERID_VERSION(x) (((uint32_t)(((uint32_t)(x)) << SCG_VERID_VERSION_SHIFT)) & SCG_VERID_VERSION_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ + +#define SCG_PARAM_SOSCCLKPRES_MASK (0x2U) +#define SCG_PARAM_SOSCCLKPRES_SHIFT (1U) +/*! SOSCCLKPRES - SOSC Clock Present + * 0b1..SOSC clock source is present + * 0b0..SOSC clock source is not present + */ +#define SCG_PARAM_SOSCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SOSCCLKPRES_SHIFT)) & SCG_PARAM_SOSCCLKPRES_MASK) + +#define SCG_PARAM_SIRCCLKPRES_MASK (0x4U) +#define SCG_PARAM_SIRCCLKPRES_SHIFT (2U) +/*! SIRCCLKPRES - SIRC Clock Present + * 0b1..SIRC clock source is present + * 0b0..SIRC clock source is not present + */ +#define SCG_PARAM_SIRCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_SIRCCLKPRES_SHIFT)) & SCG_PARAM_SIRCCLKPRES_MASK) + +#define SCG_PARAM_FIRCCLKPRES_MASK (0x8U) +#define SCG_PARAM_FIRCCLKPRES_SHIFT (3U) +/*! FIRCCLKPRES - FIRC Clock Present + * 0b1..FIRC clock source is present + * 0b0..FIRC clock source is not present + */ +#define SCG_PARAM_FIRCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_FIRCCLKPRES_SHIFT)) & SCG_PARAM_FIRCCLKPRES_MASK) + +#define SCG_PARAM_ROSCCLKPRES_MASK (0x10U) +#define SCG_PARAM_ROSCCLKPRES_SHIFT (4U) +/*! ROSCCLKPRES - ROSC Clock Present + * 0b1..ROSC clock source is present + * 0b0..ROSC clock source is not present + */ +#define SCG_PARAM_ROSCCLKPRES(x) (((uint32_t)(((uint32_t)(x)) << SCG_PARAM_ROSCCLKPRES_SHIFT)) & SCG_PARAM_ROSCCLKPRES_MASK) +/*! @} */ + +/*! @name TRIM_LOCK - Trim Lock register */ +/*! @{ */ + +#define SCG_TRIM_LOCK_TRIM_UNLOCK_MASK (0x1U) +#define SCG_TRIM_LOCK_TRIM_UNLOCK_SHIFT (0U) +/*! TRIM_UNLOCK - TRIM_UNLOCK + * 0b0..SCG Trim Registers locked and not writable. + * 0b1..SCG Trim registers unlocked and writable. + */ +#define SCG_TRIM_LOCK_TRIM_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_TRIM_UNLOCK_SHIFT)) & SCG_TRIM_LOCK_TRIM_UNLOCK_MASK) + +#define SCG_TRIM_LOCK_IFR_DISABLE_MASK (0x2U) +#define SCG_TRIM_LOCK_IFR_DISABLE_SHIFT (1U) +/*! IFR_DISABLE - IFR_DISABLE + * 0b0..IFR write access to SCG trim registers not disabled. The SCG Trim registers are reprogrammed with the IFR values after any system reset. + * 0b1..IFR write access to SCG trim registers during system reset is blocked. + */ +#define SCG_TRIM_LOCK_IFR_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_IFR_DISABLE_SHIFT)) & SCG_TRIM_LOCK_IFR_DISABLE_MASK) + +#define SCG_TRIM_LOCK_TRIM_LOCK_KEY_MASK (0xFFFF0000U) +#define SCG_TRIM_LOCK_TRIM_LOCK_KEY_SHIFT (16U) +/*! TRIM_LOCK_KEY - TRIM_LOCK_KEY */ +#define SCG_TRIM_LOCK_TRIM_LOCK_KEY(x) (((uint32_t)(((uint32_t)(x)) << SCG_TRIM_LOCK_TRIM_LOCK_KEY_SHIFT)) & SCG_TRIM_LOCK_TRIM_LOCK_KEY_MASK) +/*! @} */ + +/*! @name CSR - Clock Status Register */ +/*! @{ */ + +#define SCG_CSR_SCS_MASK (0x7000000U) +#define SCG_CSR_SCS_SHIFT (24U) +/*! SCS - System Clock Source + * 0b000..Reserved + * 0b001..SOSC + * 0b010..SIRC + * 0b011..FIRC + * 0b100..ROSC + * 0b101-0b111..Reserved + */ +#define SCG_CSR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_CSR_SCS_SHIFT)) & SCG_CSR_SCS_MASK) +/*! @} */ + +/*! @name RCCR - Run Clock Control Register */ +/*! @{ */ + +#define SCG_RCCR_SCS_MASK (0x7000000U) +#define SCG_RCCR_SCS_SHIFT (24U) +/*! SCS - System Clock Source + * 0b000..Reserved + * 0b001..SOSC + * 0b010..SIRC + * 0b011..FIRC + * 0b100..ROSC + * 0b101-0b111..Reserved + */ +#define SCG_RCCR_SCS(x) (((uint32_t)(((uint32_t)(x)) << SCG_RCCR_SCS_SHIFT)) & SCG_RCCR_SCS_MASK) +/*! @} */ + +/*! @name SOSCCSR - SOSC Control Status Register */ +/*! @{ */ + +#define SCG_SOSCCSR_SOSCEN_MASK (0x1U) +#define SCG_SOSCCSR_SOSCEN_SHIFT (0U) +/*! SOSCEN - SOSC Enable + * 0b0..SOSC is disabled + * 0b1..SOSC is enabled + */ +#define SCG_SOSCCSR_SOSCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCEN_SHIFT)) & SCG_SOSCCSR_SOSCEN_MASK) + +#define SCG_SOSCCSR_SOSCSTEN_MASK (0x2U) +#define SCG_SOSCCSR_SOSCSTEN_SHIFT (1U) +/*! SOSCSTEN - SOSC Stop Enable + * 0b0..SOSC is disabled in Deep Sleep mode + * 0b1..SOSC is enabled in Deep Sleep mode only if SOSCEN is set + */ +#define SCG_SOSCCSR_SOSCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSTEN_SHIFT)) & SCG_SOSCCSR_SOSCSTEN_MASK) + +#define SCG_SOSCCSR_SOSCCM_MASK (0x10000U) +#define SCG_SOSCCSR_SOSCCM_SHIFT (16U) +/*! SOSCCM - SOSC Clock Monitor Enable + * 0b0..SOSC Clock Monitor is disabled + * 0b1..SOSC Clock Monitor is enabled + */ +#define SCG_SOSCCSR_SOSCCM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCM_SHIFT)) & SCG_SOSCCSR_SOSCCM_MASK) + +#define SCG_SOSCCSR_SOSCCMRE_MASK (0x20000U) +#define SCG_SOSCCSR_SOSCCMRE_SHIFT (17U) +/*! SOSCCMRE - SOSC Clock Monitor Reset Enable + * 0b0..Clock monitor generates an interrupt when an error is detected + * 0b1..Clock monitor generates a reset when an error is detected + */ +#define SCG_SOSCCSR_SOSCCMRE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCCMRE_SHIFT)) & SCG_SOSCCSR_SOSCCMRE_MASK) + +#define SCG_SOSCCSR_LK_MASK (0x800000U) +#define SCG_SOSCCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..This Control Status Register can be written + * 0b1..This Control Status Register cannot be written + */ +#define SCG_SOSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_LK_SHIFT)) & SCG_SOSCCSR_LK_MASK) + +#define SCG_SOSCCSR_SOSCVLD_MASK (0x1000000U) +#define SCG_SOSCCSR_SOSCVLD_SHIFT (24U) +/*! SOSCVLD - SOSC Valid + * 0b0..SOSC is not enabled or clock is not valid + * 0b1..SOSC is enabled and output clock is valid + */ +#define SCG_SOSCCSR_SOSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_SHIFT)) & SCG_SOSCCSR_SOSCVLD_MASK) + +#define SCG_SOSCCSR_SOSCSEL_MASK (0x2000000U) +#define SCG_SOSCCSR_SOSCSEL_SHIFT (25U) +/*! SOSCSEL - SOSC Selected + * 0b0..SOSC is not the system clock source + * 0b1..SOSC is the system clock source + */ +#define SCG_SOSCCSR_SOSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCSEL_SHIFT)) & SCG_SOSCCSR_SOSCSEL_MASK) + +#define SCG_SOSCCSR_SOSCERR_MASK (0x4000000U) +#define SCG_SOSCCSR_SOSCERR_SHIFT (26U) +/*! SOSCERR - SOSC Clock Error + * 0b0..SOSC Clock Monitor is disabled or has not detected an error + * 0b1..SOSC Clock Monitor is enabled and detected an error + */ +#define SCG_SOSCCSR_SOSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCERR_SHIFT)) & SCG_SOSCCSR_SOSCERR_MASK) + +#define SCG_SOSCCSR_SOSCVLD_IE_MASK (0x40000000U) +#define SCG_SOSCCSR_SOSCVLD_IE_SHIFT (30U) +/*! SOSCVLD_IE - SOSC Valid Interrupt Enable + * 0b0..SOSCVLD interrupt is not enabled + * 0b1..SOSCVLD interrupt is enabled + */ +#define SCG_SOSCCSR_SOSCVLD_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCSR_SOSCVLD_IE_SHIFT)) & SCG_SOSCCSR_SOSCVLD_IE_MASK) +/*! @} */ + +/*! @name SOSCCFG - SOSC Configuration Register */ +/*! @{ */ + +#define SCG_SOSCCFG_EREFS_MASK (0x4U) +#define SCG_SOSCCFG_EREFS_SHIFT (2U) +/*! EREFS - External Reference Select + * 0b0..External reference clock selected. + * 0b1..Internal crystal oscillator of OSC selected. + */ +#define SCG_SOSCCFG_EREFS(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_EREFS_SHIFT)) & SCG_SOSCCFG_EREFS_MASK) + +#define SCG_SOSCCFG_RANGE_MASK (0x30U) +#define SCG_SOSCCFG_RANGE_SHIFT (4U) +/*! RANGE - SOSC Range Select + * 0b00..Frequency range select of 8-16 MHz. + * 0b01..Frequency range select of 16-25 MHz. + * 0b10..Frequency range select of 25-40 MHz. + * 0b11..Frequency range select of 40-50 MHz. + */ +#define SCG_SOSCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SOSCCFG_RANGE_SHIFT)) & SCG_SOSCCFG_RANGE_MASK) +/*! @} */ + +/*! @name SIRCCSR - SIRC Control Status Register */ +/*! @{ */ + +#define SCG_SIRCCSR_SIRCSTEN_MASK (0x2U) +#define SCG_SIRCCSR_SIRCSTEN_SHIFT (1U) +/*! SIRCSTEN - SIRC Stop Enable + * 0b0..SIRC is disabled in Deep Sleep mode + * 0b1..SIRC is enabled in Deep Sleep mode + */ +#define SCG_SIRCCSR_SIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSTEN_SHIFT)) & SCG_SIRCCSR_SIRCSTEN_MASK) + +#define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK (0x20U) +#define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_SHIFT (5U) +/*! SIRC_CLK_PERIPH_EN - SIRC Clock to Peripherals Enable + * 0b0..SIRC clock to peripherals is disabled + * 0b1..SIRC clock to peripherals is enabled + */ +#define SCG_SIRCCSR_SIRC_CLK_PERIPH_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_SHIFT)) & SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK) + +#define SCG_SIRCCSR_SIRCTREN_MASK (0x100U) +#define SCG_SIRCCSR_SIRCTREN_SHIFT (8U) +/*! SIRCTREN - SIRC 12 MHz Trim Enable (SIRCCFG[RANGE]=1) + * 0b0..Disables trimming SIRC to an external clock source + * 0b1..Enables trimming SIRC to an external clock source + */ +#define SCG_SIRCCSR_SIRCTREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCTREN_SHIFT)) & SCG_SIRCCSR_SIRCTREN_MASK) + +#define SCG_SIRCCSR_SIRCTRUP_MASK (0x200U) +#define SCG_SIRCCSR_SIRCTRUP_SHIFT (9U) +/*! SIRCTRUP - SIRC Trim Update + * 0b0..Disables SIRC trimming updates + * 0b1..Enables SIRC trimming updates + */ +#define SCG_SIRCCSR_SIRCTRUP(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCTRUP_SHIFT)) & SCG_SIRCCSR_SIRCTRUP_MASK) + +#define SCG_SIRCCSR_TRIM_LOCK_MASK (0x400U) +#define SCG_SIRCCSR_TRIM_LOCK_SHIFT (10U) +/*! TRIM_LOCK - SIRC TRIM LOCK + * 0b0..SIRC auto trim not locked to target frequency range + * 0b1..SIRC auto trim locked to target frequency range + */ +#define SCG_SIRCCSR_TRIM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_TRIM_LOCK_SHIFT)) & SCG_SIRCCSR_TRIM_LOCK_MASK) + +#define SCG_SIRCCSR_COARSE_TRIM_BYPASS_MASK (0x800U) +#define SCG_SIRCCSR_COARSE_TRIM_BYPASS_SHIFT (11U) +/*! COARSE_TRIM_BYPASS - Coarse Auto Trim Bypass + * 0b0..SIRC Coarse Auto Trim NOT Bypassed + * 0b1..SIRC Coarse Auto Trim Bypassed + */ +#define SCG_SIRCCSR_COARSE_TRIM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_COARSE_TRIM_BYPASS_SHIFT)) & SCG_SIRCCSR_COARSE_TRIM_BYPASS_MASK) + +#define SCG_SIRCCSR_LK_MASK (0x800000U) +#define SCG_SIRCCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_SIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_LK_SHIFT)) & SCG_SIRCCSR_LK_MASK) + +#define SCG_SIRCCSR_SIRCVLD_MASK (0x1000000U) +#define SCG_SIRCCSR_SIRCVLD_SHIFT (24U) +/*! SIRCVLD - SIRC Valid + * 0b0..SIRC is not enabled or clock is not valid + * 0b1..SIRC is enabled and output clock is valid + */ +#define SCG_SIRCCSR_SIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCVLD_SHIFT)) & SCG_SIRCCSR_SIRCVLD_MASK) + +#define SCG_SIRCCSR_SIRCSEL_MASK (0x2000000U) +#define SCG_SIRCCSR_SIRCSEL_SHIFT (25U) +/*! SIRCSEL - SIRC Selected + * 0b0..SIRC is not the system clock source + * 0b1..SIRC is the system clock source + */ +#define SCG_SIRCCSR_SIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCSEL_SHIFT)) & SCG_SIRCCSR_SIRCSEL_MASK) + +#define SCG_SIRCCSR_SIRCERR_MASK (0x4000000U) +#define SCG_SIRCCSR_SIRCERR_SHIFT (26U) +/*! SIRCERR - SIRC Clock Error + * 0b0..Error not detected with the SIRC trimming + * 0b1..Error detected with the SIRC trimming + */ +#define SCG_SIRCCSR_SIRCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCERR_SHIFT)) & SCG_SIRCCSR_SIRCERR_MASK) + +#define SCG_SIRCCSR_SIRCERR_IE_MASK (0x8000000U) +#define SCG_SIRCCSR_SIRCERR_IE_SHIFT (27U) +/*! SIRCERR_IE - SIRC Clock Error Interrupt Enable + * 0b0..SIRCERR interrupt is not enabled + * 0b1..SIRCERR interrupt is enabled + */ +#define SCG_SIRCCSR_SIRCERR_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCCSR_SIRCERR_IE_SHIFT)) & SCG_SIRCCSR_SIRCERR_IE_MASK) +/*! @} */ + +/*! @name SIRCTCFG - SIRC Trim Configuration Register */ +/*! @{ */ + +#define SCG_SIRCTCFG_TRIMSRC_MASK (0x3U) +#define SCG_SIRCTCFG_TRIMSRC_SHIFT (0U) +/*! TRIMSRC - Trim Source + * 0b00..Reserved + * 0b01..Reserved + * 0b10..SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz. + * 0b11..Reserved + */ +#define SCG_SIRCTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTCFG_TRIMSRC_SHIFT)) & SCG_SIRCTCFG_TRIMSRC_MASK) + +#define SCG_SIRCTCFG_TRIMDIV_MASK (0x7F0000U) +#define SCG_SIRCTCFG_TRIMDIV_SHIFT (16U) +/*! TRIMDIV - SIRC Trim Pre-divider */ +#define SCG_SIRCTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTCFG_TRIMDIV_SHIFT)) & SCG_SIRCTCFG_TRIMDIV_MASK) +/*! @} */ + +/*! @name SIRCTRIM - SIRC Trim Register */ +/*! @{ */ + +#define SCG_SIRCTRIM_CCOTRIM_MASK (0x3FU) +#define SCG_SIRCTRIM_CCOTRIM_SHIFT (0U) +/*! CCOTRIM - CCO Trim */ +#define SCG_SIRCTRIM_CCOTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_CCOTRIM_SHIFT)) & SCG_SIRCTRIM_CCOTRIM_MASK) + +#define SCG_SIRCTRIM_CLTRIM_MASK (0x3F00U) +#define SCG_SIRCTRIM_CLTRIM_SHIFT (8U) +/*! CLTRIM - CL Trim */ +#define SCG_SIRCTRIM_CLTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_CLTRIM_SHIFT)) & SCG_SIRCTRIM_CLTRIM_MASK) + +#define SCG_SIRCTRIM_TCTRIM_MASK (0x1F0000U) +#define SCG_SIRCTRIM_TCTRIM_SHIFT (16U) +/*! TCTRIM - Trim Temp */ +#define SCG_SIRCTRIM_TCTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_TCTRIM_SHIFT)) & SCG_SIRCTRIM_TCTRIM_MASK) + +#define SCG_SIRCTRIM_FVCHTRIM_MASK (0x1F000000U) +#define SCG_SIRCTRIM_FVCHTRIM_SHIFT (24U) +#define SCG_SIRCTRIM_FVCHTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCTRIM_FVCHTRIM_SHIFT)) & SCG_SIRCTRIM_FVCHTRIM_MASK) +/*! @} */ + +/*! @name SIRCSTAT - SIRC Auto-trimming Status Register */ +/*! @{ */ + +#define SCG_SIRCSTAT_CCOTRIM_MASK (0x3FU) +#define SCG_SIRCSTAT_CCOTRIM_SHIFT (0U) +/*! CCOTRIM - CCO Trim */ +#define SCG_SIRCSTAT_CCOTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCSTAT_CCOTRIM_SHIFT)) & SCG_SIRCSTAT_CCOTRIM_MASK) + +#define SCG_SIRCSTAT_CLTRIM_MASK (0x3F00U) +#define SCG_SIRCSTAT_CLTRIM_SHIFT (8U) +/*! CLTRIM - CL Trim */ +#define SCG_SIRCSTAT_CLTRIM(x) (((uint32_t)(((uint32_t)(x)) << SCG_SIRCSTAT_CLTRIM_SHIFT)) & SCG_SIRCSTAT_CLTRIM_MASK) +/*! @} */ + +/*! @name FIRCCSR - FIRC Control Status Register */ +/*! @{ */ + +#define SCG_FIRCCSR_FIRCEN_MASK (0x1U) +#define SCG_FIRCCSR_FIRCEN_SHIFT (0U) +/*! FIRCEN - FIRC Enable + * 0b0..FIRC is disabled + * 0b1..FIRC is enabled + */ +#define SCG_FIRCCSR_FIRCEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCEN_SHIFT)) & SCG_FIRCCSR_FIRCEN_MASK) + +#define SCG_FIRCCSR_FIRCSTEN_MASK (0x2U) +#define SCG_FIRCCSR_FIRCSTEN_SHIFT (1U) +/*! FIRCSTEN - FIRC Stop Enable + * 0b0..FIRC is disabled in Deep Sleep mode + * 0b1..FIRC is enabled in Deep Sleep mode + */ +#define SCG_FIRCCSR_FIRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSTEN_SHIFT)) & SCG_FIRCCSR_FIRCSTEN_MASK) + +#define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK (0x10U) +#define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT (4U) +/*! FIRC_SCLK_PERIPH_EN - FIRC 48 MHz Clock to peripherals Enable + * 0b0..FIRC 48 MHz to peripherals is disabled + * 0b1..FIRC 48 MHz to peripherals is enabled + */ +#define SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT)) & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) + +#define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK (0x20U) +#define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT (5U) +/*! FIRC_FCLK_PERIPH_EN - FRO_HF Clock to peripherals Enable + * 0b0..FRO_HF to peripherals is disabled + * 0b1..FRO_HF to peripherals is enabled + */ +#define SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT)) & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK) + +#define SCG_FIRCCSR_FIRCTREN_MASK (0x100U) +#define SCG_FIRCCSR_FIRCTREN_SHIFT (8U) +/*! FIRCTREN - FRO_HF Trim Enable + * 0b0..Disables trimming FRO_HF by an external clock source + * 0b1..Enables trimming FRO_HF by an external clock source + */ +#define SCG_FIRCCSR_FIRCTREN(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTREN_SHIFT)) & SCG_FIRCCSR_FIRCTREN_MASK) + +#define SCG_FIRCCSR_FIRCTRUP_MASK (0x200U) +#define SCG_FIRCCSR_FIRCTRUP_SHIFT (9U) +/*! FIRCTRUP - FIRC Trim Update + * 0b0..Disables FIRC trimming updates + * 0b1..Enables FIRC trimming updates + */ +#define SCG_FIRCCSR_FIRCTRUP(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCTRUP_SHIFT)) & SCG_FIRCCSR_FIRCTRUP_MASK) + +#define SCG_FIRCCSR_TRIM_LOCK_MASK (0x400U) +#define SCG_FIRCCSR_TRIM_LOCK_SHIFT (10U) +/*! TRIM_LOCK - FIRC TRIM LOCK + * 0b0..FIRC auto trim not locked to target frequency range + * 0b1..FIRC auto trim locked to target frequency range + */ +#define SCG_FIRCCSR_TRIM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_TRIM_LOCK_SHIFT)) & SCG_FIRCCSR_TRIM_LOCK_MASK) + +#define SCG_FIRCCSR_COARSE_TRIM_BYPASS_MASK (0x800U) +#define SCG_FIRCCSR_COARSE_TRIM_BYPASS_SHIFT (11U) +/*! COARSE_TRIM_BYPASS - Coarse Auto Trim Bypass + * 0b0..FIRC Coarse Auto Trim NOT Bypassed + * 0b1..FIRC Coarse Auto Trim Bypassed + */ +#define SCG_FIRCCSR_COARSE_TRIM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_COARSE_TRIM_BYPASS_SHIFT)) & SCG_FIRCCSR_COARSE_TRIM_BYPASS_MASK) + +#define SCG_FIRCCSR_LK_MASK (0x800000U) +#define SCG_FIRCCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_FIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_LK_SHIFT)) & SCG_FIRCCSR_LK_MASK) + +#define SCG_FIRCCSR_FIRCVLD_MASK (0x1000000U) +#define SCG_FIRCCSR_FIRCVLD_SHIFT (24U) +/*! FIRCVLD - FIRC Valid status + * 0b0..FIRC is not enabled or clock is not valid. + * 0b1..FIRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog. + */ +#define SCG_FIRCCSR_FIRCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCVLD_SHIFT)) & SCG_FIRCCSR_FIRCVLD_MASK) + +#define SCG_FIRCCSR_FIRCSEL_MASK (0x2000000U) +#define SCG_FIRCCSR_FIRCSEL_SHIFT (25U) +/*! FIRCSEL - FIRC Selected + * 0b0..FIRC is not the system clock source + * 0b1..FIRC is the system clock source + */ +#define SCG_FIRCCSR_FIRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCSEL_SHIFT)) & SCG_FIRCCSR_FIRCSEL_MASK) + +#define SCG_FIRCCSR_FIRCERR_MASK (0x4000000U) +#define SCG_FIRCCSR_FIRCERR_SHIFT (26U) +/*! FIRCERR - FIRC Clock Error + * 0b0..Error not detected with the FIRC trimming + * 0b1..Error detected with the FIRC trimming + */ +#define SCG_FIRCCSR_FIRCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_SHIFT)) & SCG_FIRCCSR_FIRCERR_MASK) + +#define SCG_FIRCCSR_FIRCERR_IE_MASK (0x8000000U) +#define SCG_FIRCCSR_FIRCERR_IE_SHIFT (27U) +/*! FIRCERR_IE - FIRC Clock Error Interrupt Enable + * 0b0..FIRCERR interrupt is not enabled + * 0b1..FIRCERR interrupt is enabled + */ +#define SCG_FIRCCSR_FIRCERR_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCERR_IE_SHIFT)) & SCG_FIRCCSR_FIRCERR_IE_MASK) + +#define SCG_FIRCCSR_FIRCACC_IE_MASK (0x40000000U) +#define SCG_FIRCCSR_FIRCACC_IE_SHIFT (30U) +/*! FIRCACC_IE - FIRC Accurate Interrupt Enable + * 0b0..FIRCACC interrupt is not enabled + * 0b1..FIRCACC interrupt is enabled + */ +#define SCG_FIRCCSR_FIRCACC_IE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCACC_IE_SHIFT)) & SCG_FIRCCSR_FIRCACC_IE_MASK) + +#define SCG_FIRCCSR_FIRCACC_MASK (0x80000000U) +#define SCG_FIRCCSR_FIRCACC_SHIFT (31U) +/*! FIRCACC - FIRC Frequency Accurate + * 0b0..FIRC is not enabled or clock is not accurate. + * 0b1..FIRC is enabled and output clock is accurate after some preparation time which is obtained by counting FRO_HF clock. + */ +#define SCG_FIRCCSR_FIRCACC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCSR_FIRCACC_SHIFT)) & SCG_FIRCCSR_FIRCACC_MASK) +/*! @} */ + +/*! @name FIRCCFG - FIRC Configuration Register */ +/*! @{ */ + +#define SCG_FIRCCFG_FREQ_SEL_MASK (0xEU) +#define SCG_FIRCCFG_FREQ_SEL_SHIFT (1U) +/*! FREQ_SEL - Frequency select + * 0b111..192 MHz FIRC clock selected + * 0b101..96 MHz FIRC clock selected + * 0b011..64 MHz FIRC clock selected + * 0b001..48 MHz FIRC clock selected, divided from 192 MHz + */ +#define SCG_FIRCCFG_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCCFG_FREQ_SEL_SHIFT)) & SCG_FIRCCFG_FREQ_SEL_MASK) +/*! @} */ + +/*! @name FIRCTCFG - FIRC Trim Configuration Register */ +/*! @{ */ + +#define SCG_FIRCTCFG_TRIMSRC_MASK (0x3U) +#define SCG_FIRCTCFG_TRIMSRC_SHIFT (0U) +/*! TRIMSRC - Trim Source + * 0b00..USB0 Start of Frame (1 KHz). This option does not use TRIMDIV . + * 0b01..Reserved + * 0b10..SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz. + * 0b11..Reserved + */ +#define SCG_FIRCTCFG_TRIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMSRC_SHIFT)) & SCG_FIRCTCFG_TRIMSRC_MASK) + +#define SCG_FIRCTCFG_TRIMDIV_MASK (0x7F0000U) +#define SCG_FIRCTCFG_TRIMDIV_SHIFT (16U) +/*! TRIMDIV - FIRC Trim Pre-divider */ +#define SCG_FIRCTCFG_TRIMDIV(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTCFG_TRIMDIV_SHIFT)) & SCG_FIRCTCFG_TRIMDIV_MASK) +/*! @} */ + +/*! @name FIRCTRIM - FIRC Trim Register */ +/*! @{ */ + +#define SCG_FIRCTRIM_TRIMFINE_MASK (0xFFU) +#define SCG_FIRCTRIM_TRIMFINE_SHIFT (0U) +/*! TRIMFINE - Trim Fine */ +#define SCG_FIRCTRIM_TRIMFINE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMFINE_SHIFT)) & SCG_FIRCTRIM_TRIMFINE_MASK) + +#define SCG_FIRCTRIM_TRIMCOAR_MASK (0x3F00U) +#define SCG_FIRCTRIM_TRIMCOAR_SHIFT (8U) +/*! TRIMCOAR - Trim Coarse */ +#define SCG_FIRCTRIM_TRIMCOAR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMCOAR_SHIFT)) & SCG_FIRCTRIM_TRIMCOAR_MASK) + +#define SCG_FIRCTRIM_TRIMTEMP2_MASK (0xC0000U) +#define SCG_FIRCTRIM_TRIMTEMP2_SHIFT (18U) +/*! TRIMTEMP2 - Trim Temperature2 */ +#define SCG_FIRCTRIM_TRIMTEMP2(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMTEMP2_SHIFT)) & SCG_FIRCTRIM_TRIMTEMP2_MASK) + +#define SCG_FIRCTRIM_TRIMSTART_MASK (0x3F000000U) +#define SCG_FIRCTRIM_TRIMSTART_SHIFT (24U) +/*! TRIMSTART - Trim Start */ +#define SCG_FIRCTRIM_TRIMSTART(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCTRIM_TRIMSTART_SHIFT)) & SCG_FIRCTRIM_TRIMSTART_MASK) +/*! @} */ + +/*! @name FIRCSTAT - FIRC Auto-trimming Status Register */ +/*! @{ */ + +#define SCG_FIRCSTAT_TRIMFINE_MASK (0xFFU) +#define SCG_FIRCSTAT_TRIMFINE_SHIFT (0U) +/*! TRIMFINE - Trim Fine */ +#define SCG_FIRCSTAT_TRIMFINE(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMFINE_SHIFT)) & SCG_FIRCSTAT_TRIMFINE_MASK) + +#define SCG_FIRCSTAT_TRIMCOAR_MASK (0x3F00U) +#define SCG_FIRCSTAT_TRIMCOAR_SHIFT (8U) +/*! TRIMCOAR - Trim Coarse */ +#define SCG_FIRCSTAT_TRIMCOAR(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCSTAT_TRIMCOAR_SHIFT)) & SCG_FIRCSTAT_TRIMCOAR_MASK) +/*! @} */ + +/*! @name FIRCATC1 - FIRC Auto-trimming Counter 1 */ +/*! @{ */ + +#define SCG_FIRCATC1_IDEALC_MASK (0xFFFFU) +#define SCG_FIRCATC1_IDEALC_SHIFT (0U) +/*! IDEALC - Ideal Counter */ +#define SCG_FIRCATC1_IDEALC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCATC1_IDEALC_SHIFT)) & SCG_FIRCATC1_IDEALC_MASK) +/*! @} */ + +/*! @name FIRCATC2 - FIRC Auto-trimming Counter 2 */ +/*! @{ */ + +#define SCG_FIRCATC2_COARMINC_MASK (0xFFFFU) +#define SCG_FIRCATC2_COARMINC_SHIFT (0U) +/*! COARMINC - Coarse Trim Minimum Counter */ +#define SCG_FIRCATC2_COARMINC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCATC2_COARMINC_SHIFT)) & SCG_FIRCATC2_COARMINC_MASK) + +#define SCG_FIRCATC2_COARMAXC_MASK (0xFFFF0000U) +#define SCG_FIRCATC2_COARMAXC_SHIFT (16U) +/*! COARMAXC - Coarse Trim Maximum Counter */ +#define SCG_FIRCATC2_COARMAXC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCATC2_COARMAXC_SHIFT)) & SCG_FIRCATC2_COARMAXC_MASK) +/*! @} */ + +/*! @name FIRCATC3 - FIRC Auto-trimming Counter 2 */ +/*! @{ */ + +#define SCG_FIRCATC3_FINEMINC_MASK (0xFFFFU) +#define SCG_FIRCATC3_FINEMINC_SHIFT (0U) +/*! FINEMINC - Fine Trim Minimum Counter */ +#define SCG_FIRCATC3_FINEMINC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCATC3_FINEMINC_SHIFT)) & SCG_FIRCATC3_FINEMINC_MASK) + +#define SCG_FIRCATC3_FINEMAXC_MASK (0xFFFF0000U) +#define SCG_FIRCATC3_FINEMAXC_SHIFT (16U) +/*! FINEMAXC - Fine Trim Maximum Counter */ +#define SCG_FIRCATC3_FINEMAXC(x) (((uint32_t)(((uint32_t)(x)) << SCG_FIRCATC3_FINEMAXC_SHIFT)) & SCG_FIRCATC3_FINEMAXC_MASK) +/*! @} */ + +/*! @name ROSCCSR - ROSC Control Status Register */ +/*! @{ */ + +#define SCG_ROSCCSR_LK_MASK (0x800000U) +#define SCG_ROSCCSR_LK_SHIFT (23U) +/*! LK - Lock Register + * 0b0..Control Status Register can be written + * 0b1..Control Status Register cannot be written + */ +#define SCG_ROSCCSR_LK(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_LK_SHIFT)) & SCG_ROSCCSR_LK_MASK) + +#define SCG_ROSCCSR_ROSCVLD_MASK (0x1000000U) +#define SCG_ROSCCSR_ROSCVLD_SHIFT (24U) +/*! ROSCVLD - ROSC Valid + * 0b0..ROSC is not enabled or clock is not valid + * 0b1..ROSC is enabled and output clock is valid + */ +#define SCG_ROSCCSR_ROSCVLD(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCVLD_SHIFT)) & SCG_ROSCCSR_ROSCVLD_MASK) + +#define SCG_ROSCCSR_ROSCSEL_MASK (0x2000000U) +#define SCG_ROSCCSR_ROSCSEL_SHIFT (25U) +/*! ROSCSEL - ROSC Selected + * 0b0..ROSC is not the system clock source + * 0b1..ROSC is the system clock source + */ +#define SCG_ROSCCSR_ROSCSEL(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCSEL_SHIFT)) & SCG_ROSCCSR_ROSCSEL_MASK) + +#define SCG_ROSCCSR_ROSCERR_MASK (0x4000000U) +#define SCG_ROSCCSR_ROSCERR_SHIFT (26U) +/*! ROSCERR - ROSC Clock Error + * 0b0..ROSC Clock has not detected an error + * 0b1..ROSC Clock has detected an error + */ +#define SCG_ROSCCSR_ROSCERR(x) (((uint32_t)(((uint32_t)(x)) << SCG_ROSCCSR_ROSCERR_SHIFT)) & SCG_ROSCCSR_ROSCERR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SCG_Register_Masks */ + + +/* SCG - Peripheral instance base addresses */ +/** Peripheral SCG0 base address */ +#define SCG0_BASE (0x4008F000u) +/** Peripheral SCG0 base pointer */ +#define SCG0 ((SCG_Type *)SCG0_BASE) +/** Array initializer of SCG peripheral base addresses */ +#define SCG_BASE_ADDRS { SCG0_BASE } +/** Array initializer of SCG peripheral base pointers */ +#define SCG_BASE_PTRS { SCG0 } + +/*! + * @} + */ /* end of group SCG_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPC_Peripheral_Access_Layer SPC Peripheral Access Layer + * @{ + */ + +/** SPC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t SC; /**< Status Control, offset: 0x10 */ + uint8_t RESERVED_1[8]; + __IO uint32_t LPREQ_CFG; /**< Low-Power Request Configuration, offset: 0x1C */ + uint8_t RESERVED_2[16]; + __IO uint32_t PD_STATUS[1]; /**< SPC Power Domain Mode Status, array offset: 0x30, array step: 0x4 */ + uint8_t RESERVED_3[12]; + __IO uint32_t SRAMCTL; /**< SRAM Control, offset: 0x40 */ + uint8_t RESERVED_4[16]; + __IO uint32_t SRAMRETLDO_REFTRIM; /**< SRAM Retention Reference Trim, offset: 0x54 */ + __IO uint32_t SRAMRETLDO_CNTRL; /**< SRAM Retention LDO Control, offset: 0x58 */ + uint8_t RESERVED_5[164]; + __IO uint32_t ACTIVE_CFG; /**< Active Power Mode Configuration, offset: 0x100 */ + __IO uint32_t ACTIVE_CFG1; /**< Active Power Mode Configuration 1, offset: 0x104 */ + __IO uint32_t LP_CFG; /**< Low-Power Mode Configuration, offset: 0x108 */ + __IO uint32_t LP_CFG1; /**< Low Power Mode Configuration 1, offset: 0x10C */ + uint8_t RESERVED_6[16]; + __IO uint32_t LPWKUP_DELAY; /**< Low Power Wake-Up Delay, offset: 0x120 */ + __IO uint32_t ACTIVE_VDELAY; /**< Active Voltage Trim Delay, offset: 0x124 */ + uint8_t RESERVED_7[8]; + __IO uint32_t VD_STAT; /**< Voltage Detect Status, offset: 0x130 */ + __IO uint32_t VD_CORE_CFG; /**< Core Voltage Detect Configuration, offset: 0x134 */ + __IO uint32_t VD_SYS_CFG; /**< System Voltage Detect Configuration, offset: 0x138 */ + uint8_t RESERVED_8[4]; + __IO uint32_t EVD_CFG; /**< External Voltage Domain Configuration, offset: 0x140 */ + uint8_t RESERVED_9[444]; + uint32_t CORELDO_CFG; /**< LDO_CORE Configuration, offset: 0x300 */ +} SPC_Type; + +/* ---------------------------------------------------------------------------- + -- SPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPC_Register_Masks SPC Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define SPC_VERID_FEATURE_MASK (0xFFFFU) +#define SPC_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features + * *.. + */ +#define SPC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VERID_FEATURE_SHIFT)) & SPC_VERID_FEATURE_MASK) + +#define SPC_VERID_MINOR_MASK (0xFF0000U) +#define SPC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define SPC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SPC_VERID_MINOR_SHIFT)) & SPC_VERID_MINOR_MASK) + +#define SPC_VERID_MAJOR_MASK (0xFF000000U) +#define SPC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define SPC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << SPC_VERID_MAJOR_SHIFT)) & SPC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name SC - Status Control */ +/*! @{ */ + +#define SPC_SC_BUSY_MASK (0x1U) +#define SPC_SC_BUSY_SHIFT (0U) +/*! BUSY - SPC Busy Status Flag + * 0b0..Not busy + * 0b1..Busy + */ +#define SPC_SC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_BUSY_SHIFT)) & SPC_SC_BUSY_MASK) + +#define SPC_SC_SPC_LP_REQ_MASK (0x2U) +#define SPC_SC_SPC_LP_REQ_SHIFT (1U) +/*! SPC_LP_REQ - SPC Power Mode Configuration Status Flag + * 0b0..SPC is in Active mode; the ACTIVE_CFG register has control + * 0b1..All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_SC_SPC_LP_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_SPC_LP_REQ_SHIFT)) & SPC_SC_SPC_LP_REQ_MASK) + +#define SPC_SC_SPC_LP_MODE_MASK (0xF0U) +#define SPC_SC_SPC_LP_MODE_SHIFT (4U) +/*! SPC_LP_MODE - Power Domain Low-Power Mode Request + * 0b0000..Sleep mode with system clock running + * 0b0001..DSLEEP with system clock off + * 0b0010..PDOWN with system clock off + * 0b0100.. + * 0b1000..DPDOWN with system clock off + */ +#define SPC_SC_SPC_LP_MODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_SPC_LP_MODE_SHIFT)) & SPC_SC_SPC_LP_MODE_MASK) + +#define SPC_SC_ISO_CLR_MASK (0x10000U) +#define SPC_SC_ISO_CLR_SHIFT (16U) +/*! ISO_CLR - Isolation Clear Flags */ +#define SPC_SC_ISO_CLR(x) (((uint32_t)(((uint32_t)(x)) << SPC_SC_ISO_CLR_SHIFT)) & SPC_SC_ISO_CLR_MASK) +/*! @} */ + +/*! @name LPREQ_CFG - Low-Power Request Configuration */ +/*! @{ */ + +#define SPC_LPREQ_CFG_LPREQOE_MASK (0x1U) +#define SPC_LPREQ_CFG_LPREQOE_SHIFT (0U) +/*! LPREQOE - Low-Power Request Output Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LPREQ_CFG_LPREQOE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQOE_SHIFT)) & SPC_LPREQ_CFG_LPREQOE_MASK) + +#define SPC_LPREQ_CFG_LPREQPOL_MASK (0x2U) +#define SPC_LPREQ_CFG_LPREQPOL_SHIFT (1U) +/*! LPREQPOL - Low-Power Request Output Pin Polarity Control + * 0b0..High + * 0b1..Low + */ +#define SPC_LPREQ_CFG_LPREQPOL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQPOL_SHIFT)) & SPC_LPREQ_CFG_LPREQPOL_MASK) + +#define SPC_LPREQ_CFG_LPREQOV_MASK (0xCU) +#define SPC_LPREQ_CFG_LPREQOV_SHIFT (2U) +/*! LPREQOV - Low-Power Request Output Override + * 0b00..Not forced + * 0b01.. + * 0b10..Forced low (ignore LPREQPOL settings) + * 0b11..Forced high (ignore LPREQPOL settings) + */ +#define SPC_LPREQ_CFG_LPREQOV(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPREQ_CFG_LPREQOV_SHIFT)) & SPC_LPREQ_CFG_LPREQOV_MASK) +/*! @} */ + +/*! @name PD_STATUS - SPC Power Domain Mode Status */ +/*! @{ */ + +#define SPC_PD_STATUS_PWR_REQ_STATUS_MASK (0x1U) +#define SPC_PD_STATUS_PWR_REQ_STATUS_SHIFT (0U) +/*! PWR_REQ_STATUS - Power Request Status Flag + * 0b0..Did not request + * 0b1..Requested + */ +#define SPC_PD_STATUS_PWR_REQ_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_PWR_REQ_STATUS_SHIFT)) & SPC_PD_STATUS_PWR_REQ_STATUS_MASK) + +#define SPC_PD_STATUS_PD_LP_REQ_MASK (0x10U) +#define SPC_PD_STATUS_PD_LP_REQ_SHIFT (4U) +/*! PD_LP_REQ - Power Domain Low Power Request Flag + * 0b0..Did not request + * 0b1..Requested + */ +#define SPC_PD_STATUS_PD_LP_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_PD_LP_REQ_SHIFT)) & SPC_PD_STATUS_PD_LP_REQ_MASK) + +#define SPC_PD_STATUS_LP_MODE_MASK (0xF00U) +#define SPC_PD_STATUS_LP_MODE_SHIFT (8U) +/*! LP_MODE - Power Domain Low Power Mode Request + * 0b0000..SLEEP with system clock running + * 0b0001..DSLEEP with system clock off + * 0b0010..PDOWN with system clock off + * 0b0100.. + * 0b1000..DPDOWN with system clock off + */ +#define SPC_PD_STATUS_LP_MODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_PD_STATUS_LP_MODE_SHIFT)) & SPC_PD_STATUS_LP_MODE_MASK) +/*! @} */ + +/* The count of SPC_PD_STATUS */ +#define SPC_PD_STATUS_COUNT (1U) + +/*! @name SRAMCTL - SRAM Control */ +/*! @{ */ + +#define SPC_SRAMCTL_VSM_MASK (0x3U) +#define SPC_SRAMCTL_VSM_SHIFT (0U) +/*! VSM - Voltage Select Margin + * 0b00.. + * 0b01..1.0 V + * 0b10..1.1 V + * 0b11.. + */ +#define SPC_SRAMCTL_VSM(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_VSM_SHIFT)) & SPC_SRAMCTL_VSM_MASK) + +#define SPC_SRAMCTL_REQ_MASK (0x40000000U) +#define SPC_SRAMCTL_REQ_SHIFT (30U) +/*! REQ - SRAM Voltage Update Request + * 0b0..Do not request + * 0b1..Request + */ +#define SPC_SRAMCTL_REQ(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_REQ_SHIFT)) & SPC_SRAMCTL_REQ_MASK) + +#define SPC_SRAMCTL_ACK_MASK (0x80000000U) +#define SPC_SRAMCTL_ACK_SHIFT (31U) +/*! ACK - SRAM Voltage Update Request Acknowledge + * 0b0..Not acknowledged + * 0b1..Acknowledged + */ +#define SPC_SRAMCTL_ACK(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMCTL_ACK_SHIFT)) & SPC_SRAMCTL_ACK_MASK) +/*! @} */ + +/*! @name SRAMRETLDO_REFTRIM - SRAM Retention Reference Trim */ +/*! @{ */ + +#define SPC_SRAMRETLDO_REFTRIM_REFTRIM_MASK (0x1FU) +#define SPC_SRAMRETLDO_REFTRIM_REFTRIM_SHIFT (0U) +/*! REFTRIM - Reference Trim. Voltage range is around 0.48V - 0.85V. Trim step is 12 mV. */ +#define SPC_SRAMRETLDO_REFTRIM_REFTRIM(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMRETLDO_REFTRIM_REFTRIM_SHIFT)) & SPC_SRAMRETLDO_REFTRIM_REFTRIM_MASK) +/*! @} */ + +/*! @name SRAMRETLDO_CNTRL - SRAM Retention LDO Control */ +/*! @{ */ + +#define SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK (0x1U) +#define SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_SHIFT (0U) +/*! SRAMLDO_ON - SRAM LDO Regulator Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_SHIFT)) & SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK) + +#define SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN_MASK (0xF00U) +#define SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN_SHIFT (8U) +/*! SRAM_RET_EN - SRAM Retention */ +#define SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN(x) (((uint32_t)(((uint32_t)(x)) << SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN_SHIFT)) & SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN_MASK) +/*! @} */ + +/*! @name ACTIVE_CFG - Active Power Mode Configuration */ +/*! @{ */ + +#define SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK (0x1U) +#define SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT (0U) +/*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength + * 0b0..Low + * 0b1..Normal + */ +#define SPC_ACTIVE_CFG_CORELDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT)) & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) + +#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK (0xCU) +#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT (2U) +/*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level + * 0b00.. + * 0b01..Regulate to mid voltage (1.0 V) + * 0b10..Regulate to normal voltage (1.1 V) + * 0b11..Reserved + * 0b11..Reserved + */ +#define SPC_ACTIVE_CFG_CORELDO_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) + +#define SPC_ACTIVE_CFG_BGMODE_MASK (0x300000U) +#define SPC_ACTIVE_CFG_BGMODE_SHIFT (20U) +/*! BGMODE - Bandgap Mode + * 0b00..Bandgap disabled + * 0b01..Bandgap enabled, buffer disabled + * 0b10..Bandgap enabled, buffer enabled + * 0b11.. + */ +#define SPC_ACTIVE_CFG_BGMODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_BGMODE_SHIFT)) & SPC_ACTIVE_CFG_BGMODE_MASK) + +#define SPC_ACTIVE_CFG_VDD_VD_DISABLE_MASK (0x800000U) +#define SPC_ACTIVE_CFG_VDD_VD_DISABLE_SHIFT (23U) +/*! VDD_VD_DISABLE - VDD Voltage Detect Disable + * 0b0..Enable + * 0b1..Disable + */ +#define SPC_ACTIVE_CFG_VDD_VD_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_VDD_VD_DISABLE_SHIFT)) & SPC_ACTIVE_CFG_VDD_VD_DISABLE_MASK) + +#define SPC_ACTIVE_CFG_CORE_LVDE_MASK (0x1000000U) +#define SPC_ACTIVE_CFG_CORE_LVDE_SHIFT (24U) +/*! CORE_LVDE - Core Low-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_CORE_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_CORE_LVDE_SHIFT)) & SPC_ACTIVE_CFG_CORE_LVDE_MASK) + +#define SPC_ACTIVE_CFG_SYS_LVDE_MASK (0x2000000U) +#define SPC_ACTIVE_CFG_SYS_LVDE_SHIFT (25U) +/*! SYS_LVDE - System Low-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_SYS_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYS_LVDE_SHIFT)) & SPC_ACTIVE_CFG_SYS_LVDE_MASK) + +#define SPC_ACTIVE_CFG_SYS_HVDE_MASK (0x10000000U) +#define SPC_ACTIVE_CFG_SYS_HVDE_SHIFT (28U) +/*! SYS_HVDE - System High-Voltage Detection Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_ACTIVE_CFG_SYS_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG_SYS_HVDE_SHIFT)) & SPC_ACTIVE_CFG_SYS_HVDE_MASK) +/*! @} */ + +/*! @name ACTIVE_CFG1 - Active Power Mode Configuration 1 */ +/*! @{ */ + +#define SPC_ACTIVE_CFG1_SOC_CNTRL_MASK (0xFFFFFFFFU) +#define SPC_ACTIVE_CFG1_SOC_CNTRL_SHIFT (0U) +/*! SOC_CNTRL - Active Config Chip Control */ +#define SPC_ACTIVE_CFG1_SOC_CNTRL(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_CFG1_SOC_CNTRL_SHIFT)) & SPC_ACTIVE_CFG1_SOC_CNTRL_MASK) +/*! @} */ + +/*! @name LP_CFG - Low-Power Mode Configuration */ +/*! @{ */ + +#define SPC_LP_CFG_CORELDO_VDD_DS_MASK (0x1U) +#define SPC_LP_CFG_CORELDO_VDD_DS_SHIFT (0U) +/*! CORELDO_VDD_DS - LDO_CORE VDD Drive Strength + * 0b0..Low + * 0b1..Normal + */ +#define SPC_LP_CFG_CORELDO_VDD_DS(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORELDO_VDD_DS_SHIFT)) & SPC_LP_CFG_CORELDO_VDD_DS_MASK) + +#define SPC_LP_CFG_CORELDO_VDD_LVL_MASK (0xCU) +#define SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT (2U) +/*! CORELDO_VDD_LVL - LDO_CORE VDD Regulator Voltage Level + * 0b00..Retention voltage + * 0b01..Mid voltage (1.0 V) + * 0b10..Normal voltage (1.1 V) + * 0b11..Reserved + * 0b11..Overdrive voltage (1.15 V) + */ +#define SPC_LP_CFG_CORELDO_VDD_LVL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT)) & SPC_LP_CFG_CORELDO_VDD_LVL_MASK) + +#define SPC_LP_CFG_SRAMLDO_DPD_ON_MASK (0x80000U) +#define SPC_LP_CFG_SRAMLDO_DPD_ON_SHIFT (19U) +/*! SRAMLDO_DPD_ON - SRAM_LDO Deep Power Low Power IREF Enable + * 0b0..Low Power IREF is disabled for power saving in Deep Power Down mode + * 0b1..Low Power IREF is enabled + */ +#define SPC_LP_CFG_SRAMLDO_DPD_ON(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SRAMLDO_DPD_ON_SHIFT)) & SPC_LP_CFG_SRAMLDO_DPD_ON_MASK) + +#define SPC_LP_CFG_BGMODE_MASK (0x300000U) +#define SPC_LP_CFG_BGMODE_SHIFT (20U) +/*! BGMODE - Bandgap Mode + * 0b00..Bandgap disabled + * 0b01..Bandgap enabled, buffer disabled + * 0b10..Bandgap enabled, buffer enabled + * 0b11.. + */ +#define SPC_LP_CFG_BGMODE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_BGMODE_SHIFT)) & SPC_LP_CFG_BGMODE_MASK) + +#define SPC_LP_CFG_LP_IREFEN_MASK (0x800000U) +#define SPC_LP_CFG_LP_IREFEN_SHIFT (23U) +/*! LP_IREFEN - Low-Power IREF Enable + * 0b0..Disable for power saving in Deep Power Down mode + * 0b1..Enable + */ +#define SPC_LP_CFG_LP_IREFEN(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_LP_IREFEN_SHIFT)) & SPC_LP_CFG_LP_IREFEN_MASK) + +#define SPC_LP_CFG_CORE_LVDE_MASK (0x1000000U) +#define SPC_LP_CFG_CORE_LVDE_SHIFT (24U) +/*! CORE_LVDE - Core Low Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_CORE_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_CORE_LVDE_SHIFT)) & SPC_LP_CFG_CORE_LVDE_MASK) + +#define SPC_LP_CFG_SYS_LVDE_MASK (0x2000000U) +#define SPC_LP_CFG_SYS_LVDE_SHIFT (25U) +/*! SYS_LVDE - System Low Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_SYS_LVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYS_LVDE_SHIFT)) & SPC_LP_CFG_SYS_LVDE_MASK) + +#define SPC_LP_CFG_SYS_HVDE_MASK (0x10000000U) +#define SPC_LP_CFG_SYS_HVDE_SHIFT (28U) +/*! SYS_HVDE - System High Voltage Detect Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_LP_CFG_SYS_HVDE(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG_SYS_HVDE_SHIFT)) & SPC_LP_CFG_SYS_HVDE_MASK) +/*! @} */ + +/*! @name LP_CFG1 - Low Power Mode Configuration 1 */ +/*! @{ */ + +#define SPC_LP_CFG1_SOC_CNTRL_MASK (0xFFFFFFFFU) +#define SPC_LP_CFG1_SOC_CNTRL_SHIFT (0U) +/*! SOC_CNTRL - Low-Power Configuration Chip Control */ +#define SPC_LP_CFG1_SOC_CNTRL(x) (((uint32_t)(((uint32_t)(x)) << SPC_LP_CFG1_SOC_CNTRL_SHIFT)) & SPC_LP_CFG1_SOC_CNTRL_MASK) +/*! @} */ + +/*! @name LPWKUP_DELAY - Low Power Wake-Up Delay */ +/*! @{ */ + +#define SPC_LPWKUP_DELAY_LPWKUP_DELAY_MASK (0xFFFFU) +#define SPC_LPWKUP_DELAY_LPWKUP_DELAY_SHIFT (0U) +/*! LPWKUP_DELAY - Low-Power Wake-Up Delay */ +#define SPC_LPWKUP_DELAY_LPWKUP_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPC_LPWKUP_DELAY_LPWKUP_DELAY_SHIFT)) & SPC_LPWKUP_DELAY_LPWKUP_DELAY_MASK) +/*! @} */ + +/*! @name ACTIVE_VDELAY - Active Voltage Trim Delay */ +/*! @{ */ + +#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_MASK (0xFFFFU) +#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_SHIFT (0U) +/*! ACTIVE_VDELAY - Active Voltage Delay */ +#define SPC_ACTIVE_VDELAY_ACTIVE_VDELAY(x) (((uint32_t)(((uint32_t)(x)) << SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_SHIFT)) & SPC_ACTIVE_VDELAY_ACTIVE_VDELAY_MASK) +/*! @} */ + +/*! @name VD_STAT - Voltage Detect Status */ +/*! @{ */ + +#define SPC_VD_STAT_COREVDD_LVDF_MASK (0x1U) +#define SPC_VD_STAT_COREVDD_LVDF_SHIFT (0U) +/*! COREVDD_LVDF - Core Low-Voltage Detect Flag + * 0b0..Event not detected + * 0b1..Event detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_VD_STAT_COREVDD_LVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_COREVDD_LVDF_SHIFT)) & SPC_VD_STAT_COREVDD_LVDF_MASK) + +#define SPC_VD_STAT_SYSVDD_LVDF_MASK (0x2U) +#define SPC_VD_STAT_SYSVDD_LVDF_SHIFT (1U) +/*! SYSVDD_LVDF - System Low-Voltage Detect Flag + * 0b0..Event not detected + * 0b1..Event detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_VD_STAT_SYSVDD_LVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_SYSVDD_LVDF_SHIFT)) & SPC_VD_STAT_SYSVDD_LVDF_MASK) + +#define SPC_VD_STAT_SYSVDD_HVDF_MASK (0x20U) +#define SPC_VD_STAT_SYSVDD_HVDF_SHIFT (5U) +/*! SYSVDD_HVDF - System HVD Flag + * 0b0..Event not detected + * 0b1..Event detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define SPC_VD_STAT_SYSVDD_HVDF(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_STAT_SYSVDD_HVDF_SHIFT)) & SPC_VD_STAT_SYSVDD_HVDF_MASK) +/*! @} */ + +/*! @name VD_CORE_CFG - Core Voltage Detect Configuration */ +/*! @{ */ + +#define SPC_VD_CORE_CFG_LVDRE_MASK (0x1U) +#define SPC_VD_CORE_CFG_LVDRE_SHIFT (0U) +/*! LVDRE - Core LVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_CORE_CFG_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LVDRE_SHIFT)) & SPC_VD_CORE_CFG_LVDRE_MASK) + +#define SPC_VD_CORE_CFG_LVDIE_MASK (0x2U) +#define SPC_VD_CORE_CFG_LVDIE_SHIFT (1U) +/*! LVDIE - Core LVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_CORE_CFG_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LVDIE_SHIFT)) & SPC_VD_CORE_CFG_LVDIE_MASK) + +#define SPC_VD_CORE_CFG_LOCK_MASK (0x10000U) +#define SPC_VD_CORE_CFG_LOCK_SHIFT (16U) +/*! LOCK - Core Voltage Detect Reset Enable Lock + * 0b0..Allow + * 0b1..Deny + */ +#define SPC_VD_CORE_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_CORE_CFG_LOCK_SHIFT)) & SPC_VD_CORE_CFG_LOCK_MASK) +/*! @} */ + +/*! @name VD_SYS_CFG - System Voltage Detect Configuration */ +/*! @{ */ + +#define SPC_VD_SYS_CFG_LVDRE_MASK (0x1U) +#define SPC_VD_SYS_CFG_LVDRE_SHIFT (0U) +/*! LVDRE - System LVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_SYS_CFG_LVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVDRE_SHIFT)) & SPC_VD_SYS_CFG_LVDRE_MASK) + +#define SPC_VD_SYS_CFG_LVDIE_MASK (0x2U) +#define SPC_VD_SYS_CFG_LVDIE_SHIFT (1U) +/*! LVDIE - System LVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_SYS_CFG_LVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVDIE_SHIFT)) & SPC_VD_SYS_CFG_LVDIE_MASK) + +#define SPC_VD_SYS_CFG_HVDRE_MASK (0x4U) +#define SPC_VD_SYS_CFG_HVDRE_SHIFT (2U) +/*! HVDRE - System HVD Reset Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_SYS_CFG_HVDRE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDRE_SHIFT)) & SPC_VD_SYS_CFG_HVDRE_MASK) + +#define SPC_VD_SYS_CFG_HVDIE_MASK (0x8U) +#define SPC_VD_SYS_CFG_HVDIE_SHIFT (3U) +/*! HVDIE - System HVD Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define SPC_VD_SYS_CFG_HVDIE(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_HVDIE_SHIFT)) & SPC_VD_SYS_CFG_HVDIE_MASK) + +#define SPC_VD_SYS_CFG_LVSEL_MASK (0x100U) +#define SPC_VD_SYS_CFG_LVSEL_SHIFT (8U) +/*! LVSEL - System Low-Voltage Level Select + * 0b0..Normal + * 0b1..Safe + */ +#define SPC_VD_SYS_CFG_LVSEL(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LVSEL_SHIFT)) & SPC_VD_SYS_CFG_LVSEL_MASK) + +#define SPC_VD_SYS_CFG_LOCK_MASK (0x10000U) +#define SPC_VD_SYS_CFG_LOCK_SHIFT (16U) +/*! LOCK - System Voltage Detect Reset Enable Lock + * 0b0..Allow + * 0b1..Deny + */ +#define SPC_VD_SYS_CFG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPC_VD_SYS_CFG_LOCK_SHIFT)) & SPC_VD_SYS_CFG_LOCK_MASK) +/*! @} */ + +/*! @name EVD_CFG - External Voltage Domain Configuration */ +/*! @{ */ + +#define SPC_EVD_CFG_EVDISO_MASK (0xFU) +#define SPC_EVD_CFG_EVDISO_SHIFT (0U) +/*! EVDISO - External Voltage Domain Isolation */ +#define SPC_EVD_CFG_EVDISO(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDISO_SHIFT)) & SPC_EVD_CFG_EVDISO_MASK) + +#define SPC_EVD_CFG_EVDLPISO_MASK (0xF00U) +#define SPC_EVD_CFG_EVDLPISO_SHIFT (8U) +/*! EVDLPISO - External Voltage Domain Low-Power Isolation */ +#define SPC_EVD_CFG_EVDLPISO(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDLPISO_SHIFT)) & SPC_EVD_CFG_EVDLPISO_MASK) + +#define SPC_EVD_CFG_EVDSTAT_MASK (0xF0000U) +#define SPC_EVD_CFG_EVDSTAT_SHIFT (16U) +/*! EVDSTAT - External Voltage Domain Status */ +#define SPC_EVD_CFG_EVDSTAT(x) (((uint32_t)(((uint32_t)(x)) << SPC_EVD_CFG_EVDSTAT_SHIFT)) & SPC_EVD_CFG_EVDSTAT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPC_Register_Masks */ + + +/* SPC - Peripheral instance base addresses */ +/** Peripheral SPC0 base address */ +#define SPC0_BASE (0x40090000u) +/** Peripheral SPC0 base pointer */ +#define SPC0 ((SPC_Type *)SPC0_BASE) +/** Array initializer of SPC peripheral base addresses */ +#define SPC_BASE_ADDRS { SPC0_BASE } +/** Array initializer of SPC peripheral base pointers */ +#define SPC_BASE_PTRS { SPC0 } + +/*! + * @} + */ /* end of group SPC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer + * @{ + */ + +/** SYSCON - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[512]; + __IO uint32_t REMAP; /**< AHB Matrix Remap Control, offset: 0x200 */ + uint8_t RESERVED_1[12]; + __IO uint32_t AHBMATPRIO; /**< AHB Matrix Priority Control, offset: 0x210 */ + uint8_t RESERVED_2[40]; + __IO uint32_t CPU0NSTCKCAL; /**< Non-Secure CPU0 System Tick Calibration, offset: 0x23C */ + uint8_t RESERVED_3[8]; + __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x248 */ + uint8_t RESERVED_4[300]; + __IO uint32_t SLOWCLKDIV; /**< SLOW_CLK Clock Divider, offset: 0x378 */ + uint8_t RESERVED_5[4]; + __IO uint32_t AHBCLKDIV; /**< System Clock Divider, offset: 0x380 */ + uint8_t RESERVED_6[120]; + __IO uint32_t CLKUNLOCK; /**< Clock Configuration Unlock, offset: 0x3FC */ + __IO uint32_t NVM_CTRL; /**< NVM Control, offset: 0x400 */ + uint32_t ROMCR; /**< ROM Wait State, offset: 0x404 */ + uint8_t RESERVED_7[1028]; + __I uint32_t CPUSTAT; /**< CPU Status, offset: 0x80C */ + uint8_t RESERVED_8[20]; + __IO uint32_t LPCAC_CTRL; /**< LPCAC Control, offset: 0x824 */ + uint8_t RESERVED_9[272]; + __IO uint32_t PWM0SUBCTL; /**< PWM0 Submodule Control, offset: 0x938 */ + __IO uint32_t PWM1SUBCTL; /**< PWM1 Submodule Control, offset: 0x93C */ + __IO uint32_t CTIMERGLOBALSTARTEN; /**< CTIMER Global Start Enable, offset: 0x940 */ + __IO uint32_t RAM_CTRL; /**< RAM Control, offset: 0x944 */ + uint8_t RESERVED_10[536]; + __IO uint32_t GRAY_CODE_LSB; /**< Gray to Binary Converter Gray Code [31:0], offset: 0xB60 */ + __IO uint32_t GRAY_CODE_MSB; /**< Gray to Binary Converter Gray Code [41:32], offset: 0xB64 */ + __I uint32_t BINARY_CODE_LSB; /**< Gray to Binary Converter Binary Code [31:0], offset: 0xB68 */ + __I uint32_t BINARY_CODE_MSB; /**< Gray to Binary Converter Binary Code [41:32], offset: 0xB6C */ + uint8_t RESERVED_11[716]; + __I uint32_t ROP_STATE; /**< ROP State Register, offset: 0xE3C */ + __I uint32_t OVP_PAD_STATE; /**< OVP_PAD_STATE, offset: 0xE40 */ + __I uint32_t PROBE_STATE; /**< PROBE_STATE, offset: 0xE44 */ + __I uint32_t FT_STATE_A; /**< FT_STATE_A, offset: 0xE48 */ + __I uint32_t FT_STATE_B; /**< FT_STATE_B, offset: 0xE4C */ + uint8_t RESERVED_12[8]; + __IO uint32_t SRAM_XEN; /**< RAM XEN Control, offset: 0xE58 */ + __IO uint32_t SRAM_XEN_DP; /**< RAM XEN Control (Duplicate), offset: 0xE5C */ + uint8_t RESERVED_13[32]; + __I uint32_t ELS_OTP_LC_STATE; /**< Life Cycle State Register, offset: 0xE80 */ + __I uint32_t ELS_OTP_LC_STATE_DP; /**< Life Cycle State Register (Duplicate), offset: 0xE84 */ + uint8_t RESERVED_14[280]; + __IO uint32_t DEBUG_LOCK_EN; /**< Control Write Access to Security, offset: 0xFA0 */ + __IO uint32_t DEBUG_FEATURES; /**< Cortex Debug Features Control, offset: 0xFA4 */ + __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex Debug Features Control (Duplicate), offset: 0xFA8 */ + uint8_t RESERVED_15[8]; + __IO uint32_t SWD_ACCESS_CPU0; /**< CPU0 Software Debug Access, offset: 0xFB4 */ + uint8_t RESERVED_16[8]; + __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug Authentication BEACON, offset: 0xFC0 */ + uint8_t RESERVED_17[44]; + __I uint32_t JTAG_ID; /**< JTAG Chip ID, offset: 0xFF0 */ + __I uint32_t DEVICE_TYPE; /**< Device Type, offset: 0xFF4 */ + __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ + __I uint32_t DIEID; /**< Chip Revision ID and Number, offset: 0xFFC */ +} SYSCON_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Register_Masks SYSCON Register Masks + * @{ + */ + +/*! @name REMAP - AHB Matrix Remap Control */ +/*! @{ */ + +#define SYSCON_REMAP_CPU0_SBUS_MASK (0x3U) +#define SYSCON_REMAP_CPU0_SBUS_SHIFT (0U) +/*! CPU0_SBUS - RAMX0 address remap for CPU System bus + * 0b00..RAMX0: 0x04000000 - 0x04001fff + * 0b01..RAMX0: 0x2001e000 - 0x2001ffff(for 128KB RAM chip) / 0x20016000 - 0x20017fff(for 96KB RAM chip) / 0x2000e000 - 0x2000ffff(for 64KB RAM chip) + */ +#define SYSCON_REMAP_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_CPU0_SBUS_SHIFT)) & SYSCON_REMAP_CPU0_SBUS_MASK) + +#define SYSCON_REMAP_DMA0_MASK (0xCU) +#define SYSCON_REMAP_DMA0_SHIFT (2U) +/*! DMA0 - RAMX0 address remap for DMA0 + * 0b00..RAMX0: 0x04000000 - 0x04001fff + * 0b01..RAMX0: same alias space as CPU0_SBUS + */ +#define SYSCON_REMAP_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_DMA0_SHIFT)) & SYSCON_REMAP_DMA0_MASK) + +#define SYSCON_REMAP_USB0_MASK (0x30U) +#define SYSCON_REMAP_USB0_SHIFT (4U) +/*! USB0 - RAMX0 address remap for USB0 + * 0b00..RAMX0: 0x04000000 - 0x04001fff + * 0b01..RAMX0: same alias space as CPU0_SBUS + */ +#define SYSCON_REMAP_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_USB0_SHIFT)) & SYSCON_REMAP_USB0_MASK) + +#define SYSCON_REMAP_LOCK_MASK (0x80000000U) +#define SYSCON_REMAP_LOCK_SHIFT (31U) +/*! LOCK - This 1-bit field provides a mechanism to limit writes to the this register to protect its + * contents. Once set, this bit remains asserted until a system reset. + * 0b0..This register is not locked and can be altered. + * 0b1..This register is locked and cannot be altered until a system reset. + */ +#define SYSCON_REMAP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_REMAP_LOCK_SHIFT)) & SYSCON_REMAP_LOCK_MASK) +/*! @} */ + +/*! @name AHBMATPRIO - AHB Matrix Priority Control */ +/*! @{ */ + +#define SYSCON_AHBMATPRIO_CPU0_CBUS_MASK (0x3U) +#define SYSCON_AHBMATPRIO_CPU0_CBUS_SHIFT (0U) +/*! CPU0_CBUS - CPU0 C-AHB bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_CPU0_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_CPU0_CBUS_MASK) + +#define SYSCON_AHBMATPRIO_CPU0_SBUS_MASK (0xCU) +#define SYSCON_AHBMATPRIO_CPU0_SBUS_SHIFT (2U) +/*! CPU0_SBUS - CPU0 S-AHB bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_CPU0_SBUS_MASK) + +#define SYSCON_AHBMATPRIO_DMA0_MASK (0x300U) +#define SYSCON_AHBMATPRIO_DMA0_SHIFT (8U) +/*! DMA0 - DMA0 controller bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_DMA0_SHIFT)) & SYSCON_AHBMATPRIO_DMA0_MASK) + +#define SYSCON_AHBMATPRIO_USB_FS_ENET_MASK (0x3000000U) +#define SYSCON_AHBMATPRIO_USB_FS_ENET_SHIFT (24U) +/*! USB_FS_ENET - USB-FS bus master priority level + * 0b00..level 0 + * 0b01..level 1 + * 0b10..level 2 + * 0b11..level 3 + */ +#define SYSCON_AHBMATPRIO_USB_FS_ENET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_USB_FS_ENET_SHIFT)) & SYSCON_AHBMATPRIO_USB_FS_ENET_MASK) +/*! @} */ + +/*! @name CPU0NSTCKCAL - Non-Secure CPU0 System Tick Calibration */ +/*! @{ */ + +#define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the + * value reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU0NSTCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK) + +#define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Indicates whether the TENMS value is exact. + * 0b0..TENMS value is exact + * 0b1..TENMS value is not exact or not given + */ +#define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) + +#define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Indicates whether the device provides a reference clock to the processor. + * 0b0..Reference clock is provided + * 0b1..No reference clock is provided + */ +#define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name NMISRC - NMI Source Select */ +/*! @{ */ + +#define SYSCON_NMISRC_IRQCPU0_MASK (0xFFU) +#define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) +/*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0. */ +#define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) + +#define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) +#define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) +/*! NMIENCPU0 - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. + * 0b1..Enable. + * 0b0..Disable. + */ +#define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) +/*! @} */ + +/*! @name SLOWCLKDIV - SLOW_CLK Clock Divider */ +/*! @{ */ + +#define SYSCON_SLOWCLKDIV_RESET_MASK (0x20000000U) +#define SYSCON_SLOWCLKDIV_RESET_SHIFT (29U) +/*! RESET - Resets the divider counter + * 0b1..Divider is reset + * 0b0..Divider is not reset + */ +#define SYSCON_SLOWCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_RESET_SHIFT)) & SYSCON_SLOWCLKDIV_RESET_MASK) + +#define SYSCON_SLOWCLKDIV_HALT_MASK (0x40000000U) +#define SYSCON_SLOWCLKDIV_HALT_SHIFT (30U) +/*! HALT - Halts the divider counter + * 0b1..Divider clock is stopped + * 0b0..Divider clock is running + */ +#define SYSCON_SLOWCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_HALT_SHIFT)) & SYSCON_SLOWCLKDIV_HALT_MASK) + +#define SYSCON_SLOWCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_SLOWCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_SLOWCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SLOWCLKDIV_UNSTAB_SHIFT)) & SYSCON_SLOWCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name AHBCLKDIV - System Clock Divider */ +/*! @{ */ + +#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value */ +#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) + +#define SYSCON_AHBCLKDIV_UNSTAB_MASK (0x80000000U) +#define SYSCON_AHBCLKDIV_UNSTAB_SHIFT (31U) +/*! UNSTAB - Divider status flag + * 0b1..Clock frequency is not stable + * 0b0..Divider clock is stable + */ +#define SYSCON_AHBCLKDIV_UNSTAB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_UNSTAB_SHIFT)) & SYSCON_AHBCLKDIV_UNSTAB_MASK) +/*! @} */ + +/*! @name CLKUNLOCK - Clock Configuration Unlock */ +/*! @{ */ + +#define SYSCON_CLKUNLOCK_UNLOCK_MASK (0x1U) +#define SYSCON_CLKUNLOCK_UNLOCK_SHIFT (0U) +/*! UNLOCK - Controls clock configuration registers access (for example, MRCC_xxx_CLKDIV, MRCC_xxx_CLKSEL, MRCC_GLB_xxx) + * 0b1..Freezes all clock configuration registers update. + * 0b0..Updates are allowed to all clock configuration registers + */ +#define SYSCON_CLKUNLOCK_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKUNLOCK_UNLOCK_SHIFT)) & SYSCON_CLKUNLOCK_UNLOCK_MASK) +/*! @} */ + +/*! @name NVM_CTRL - NVM Control */ +/*! @{ */ + +#define SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK (0x1U) +#define SYSCON_NVM_CTRL_DIS_FLASH_SPEC_SHIFT (0U) +/*! DIS_FLASH_SPEC - Flash speculation control + * 0b0..Enables flash speculation + * 0b1..Disables flash speculation + */ +#define SYSCON_NVM_CTRL_DIS_FLASH_SPEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_FLASH_SPEC_SHIFT)) & SYSCON_NVM_CTRL_DIS_FLASH_SPEC_MASK) + +#define SYSCON_NVM_CTRL_DIS_DATA_SPEC_MASK (0x2U) +#define SYSCON_NVM_CTRL_DIS_DATA_SPEC_SHIFT (1U) +/*! DIS_DATA_SPEC - Flash data speculation control + * 0b0..Enables data speculation + * 0b1..Disables data speculation + */ +#define SYSCON_NVM_CTRL_DIS_DATA_SPEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_DATA_SPEC_SHIFT)) & SYSCON_NVM_CTRL_DIS_DATA_SPEC_MASK) + +#define SYSCON_NVM_CTRL_FLASH_STALL_EN_MASK (0x400U) +#define SYSCON_NVM_CTRL_FLASH_STALL_EN_SHIFT (10U) +/*! FLASH_STALL_EN - FLASH stall on busy control + * 0b0..No stall on FLASH busy + * 0b1..Stall on FLASH busy + */ +#define SYSCON_NVM_CTRL_FLASH_STALL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_FLASH_STALL_EN_SHIFT)) & SYSCON_NVM_CTRL_FLASH_STALL_EN_MASK) + +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK (0x10000U) +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_SHIFT (16U) +/*! DIS_MBECC_ERR_INST + * 0b0..Enables bus error on multi-bit ECC error for instruction + * 0b1..Disables bus error on multi-bit ECC error for instruction + */ +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_SHIFT)) & SYSCON_NVM_CTRL_DIS_MBECC_ERR_INST_MASK) + +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK (0x20000U) +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_SHIFT (17U) +/*! DIS_MBECC_ERR_DATA + * 0b0..Enables bus error on multi-bit ECC error for data + * 0b1..Disables bus error on multi-bit ECC error for data + */ +#define SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_SHIFT)) & SYSCON_NVM_CTRL_DIS_MBECC_ERR_DATA_MASK) +/*! @} */ + +/*! @name CPUSTAT - CPU Status */ +/*! @{ */ + +#define SYSCON_CPUSTAT_CPU0SLEEPING_MASK (0x1U) +#define SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT (0U) +/*! CPU0SLEEPING - CPU0 sleeping state + * 0b1..CPU is sleeping + * 0b0..CPU is not sleeping + */ +#define SYSCON_CPUSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPUSTAT_CPU0SLEEPING_MASK) + +#define SYSCON_CPUSTAT_CPU0LOCKUP_MASK (0x4U) +#define SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT (2U) +/*! CPU0LOCKUP - CPU0 lockup state + * 0b1..CPU is in lockup + * 0b0..CPU is not in lockup + */ +#define SYSCON_CPUSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPUSTAT_CPU0LOCKUP_MASK) +/*! @} */ + +/*! @name LPCAC_CTRL - LPCAC Control */ +/*! @{ */ + +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK (0x1U) +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT (0U) +/*! DIS_LPCAC - Disables/enables the cache function. + * 0b0..Enabled + * 0b1..Disabled + */ +#define SYSCON_LPCAC_CTRL_DIS_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_DIS_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK) + +#define SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK (0x2U) +#define SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT (1U) +/*! CLR_LPCAC - Clears the cache function. + * 0b0..Unclears the cache + * 0b1..Clears the cache + */ +#define SYSCON_LPCAC_CTRL_CLR_LPCAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_CLR_LPCAC_SHIFT)) & SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK) + +#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK (0x4U) +#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT (2U) +/*! FRC_NO_ALLOC - Forces no allocation. + * 0b0..Forces allocation + * 0b1..Forces no allocation + */ +#define SYSCON_LPCAC_CTRL_FRC_NO_ALLOC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_SHIFT)) & SYSCON_LPCAC_CTRL_FRC_NO_ALLOC_MASK) + +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK (0x10U) +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_SHIFT (4U) +/*! DIS_LPCAC_WTBF - Disable LPCAC Write Through Buffer. + * 0b1..Disables write through buffer + * 0b0..Enables write through buffer + */ +#define SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_SHIFT)) & SYSCON_LPCAC_CTRL_DIS_LPCAC_WTBF_MASK) + +#define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK (0x20U) +#define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_SHIFT (5U) +/*! LIM_LPCAC_WTBF - Limit LPCAC Write Through Buffer. + * 0b1..Write buffer enabled when transaction is cacheable and bufferable + * 0b0..Write buffer enabled when transaction is bufferable. + */ +#define SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_SHIFT)) & SYSCON_LPCAC_CTRL_LIM_LPCAC_WTBF_MASK) + +#define SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK (0x80U) +#define SYSCON_LPCAC_CTRL_LPCAC_XOM_SHIFT (7U) +/*! LPCAC_XOM - LPCAC XOM(eXecute-Only-Memory) attribute control + * 0b1..Enabled. + * 0b0..Disabled. + */ +#define SYSCON_LPCAC_CTRL_LPCAC_XOM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LPCAC_XOM_SHIFT)) & SYSCON_LPCAC_CTRL_LPCAC_XOM_MASK) + +#define SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK (0x100U) +#define SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_SHIFT (8U) +/*! LPCAC_MEM_REQ - Request LPCAC memories. + * 0b1..Configure shared memories RAMX1 as LPCAC memories, write one lock until a system reset. + * 0b0..Configure shared memories RAMX1 as general memories. + */ +#define SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_SHIFT)) & SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK) +/*! @} */ + +/*! @name PWM0SUBCTL - PWM0 Submodule Control */ +/*! @{ */ + +#define SYSCON_PWM0SUBCTL_CLK0_EN_MASK (0x1U) +#define SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT (0U) +/*! CLK0_EN - Enables PWM0 SUB Clock0 + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_PWM0SUBCTL_CLK0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK0_EN_MASK) + +#define SYSCON_PWM0SUBCTL_CLK1_EN_MASK (0x2U) +#define SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT (1U) +/*! CLK1_EN - Enables PWM0 SUB Clock1 + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_PWM0SUBCTL_CLK1_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK1_EN_MASK) + +#define SYSCON_PWM0SUBCTL_CLK2_EN_MASK (0x4U) +#define SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT (2U) +/*! CLK2_EN - Enables PWM0 SUB Clock2 + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_PWM0SUBCTL_CLK2_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK2_EN_MASK) + +#define SYSCON_PWM0SUBCTL_CLK3_EN_MASK (0x8U) +#define SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT (3U) +/*! CLK3_EN - Enables PWM0 SUB Clock3 + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_PWM0SUBCTL_CLK3_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM0SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM0SUBCTL_CLK3_EN_MASK) +/*! @} */ + +/*! @name PWM1SUBCTL - PWM1 Submodule Control */ +/*! @{ */ + +#define SYSCON_PWM1SUBCTL_CLK0_EN_MASK (0x1U) +#define SYSCON_PWM1SUBCTL_CLK0_EN_SHIFT (0U) +/*! CLK0_EN - Enables PWM1 SUB Clock0 + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_PWM1SUBCTL_CLK0_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK0_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK0_EN_MASK) + +#define SYSCON_PWM1SUBCTL_CLK1_EN_MASK (0x2U) +#define SYSCON_PWM1SUBCTL_CLK1_EN_SHIFT (1U) +/*! CLK1_EN - Enables PWM1 SUB Clock1 + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_PWM1SUBCTL_CLK1_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK1_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK1_EN_MASK) + +#define SYSCON_PWM1SUBCTL_CLK2_EN_MASK (0x4U) +#define SYSCON_PWM1SUBCTL_CLK2_EN_SHIFT (2U) +/*! CLK2_EN - Enables PWM1 SUB Clock2 + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_PWM1SUBCTL_CLK2_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK2_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK2_EN_MASK) + +#define SYSCON_PWM1SUBCTL_CLK3_EN_MASK (0x8U) +#define SYSCON_PWM1SUBCTL_CLK3_EN_SHIFT (3U) +/*! CLK3_EN - Enables PWM1 SUB Clock3 + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_PWM1SUBCTL_CLK3_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PWM1SUBCTL_CLK3_EN_SHIFT)) & SYSCON_PWM1SUBCTL_CLK3_EN_MASK) +/*! @} */ + +/*! @name CTIMERGLOBALSTARTEN - CTIMER Global Start Enable */ +/*! @{ */ + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK (0x1U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT (0U) +/*! CTIMER0_CLK_EN - Enables the CTIMER0 function clock + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK (0x2U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT (1U) +/*! CTIMER1_CLK_EN - Enables the CTIMER1 function clock + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK (0x4U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT (2U) +/*! CTIMER2_CLK_EN - Enables the CTIMER2 function clock + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_MASK (0x8U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_SHIFT (3U) +/*! CTIMER3_CLK_EN - Enables the CTIMER3 function clock + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN_MASK) + +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_MASK (0x10U) +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_SHIFT (4U) +/*! CTIMER4_CLK_EN - Enables the CTIMER4 function clock + * 0b1..Enable + * 0b0..Disable + */ +#define SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_SHIFT)) & SYSCON_CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN_MASK) +/*! @} */ + +/*! @name RAM_CTRL - RAM Control */ +/*! @{ */ + +#define SYSCON_RAM_CTRL_RAMA_ECC_ENABLE_MASK (0x1U) +#define SYSCON_RAM_CTRL_RAMA_ECC_ENABLE_SHIFT (0U) +/*! RAMA_ECC_ENABLE - RAMA0 ECC enable + * 0b1..ECC is enabled + * 0b0..ECC is disabled + */ +#define SYSCON_RAM_CTRL_RAMA_ECC_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_CTRL_RAMA_ECC_ENABLE_SHIFT)) & SYSCON_RAM_CTRL_RAMA_ECC_ENABLE_MASK) + +#define SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE_MASK (0x10000U) +#define SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE_SHIFT (16U) +/*! RAMA_CG_OVERRIDE - RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0. + * 0b1..Auto clock gating feature is disabled + * 0b0..Memory bank clock is gated automatically if no access more than 16 clock cycles + */ +#define SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE_SHIFT)) & SYSCON_RAM_CTRL_RAMA_CG_OVERRIDE_MASK) + +#define SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE_MASK (0x20000U) +#define SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE_SHIFT (17U) +/*! RAMX_CG_OVERRIDE - RAMX bank clock gating control + * 0b1..Auto clock gating feature is disabled + * 0b0..Memory bank clock is gated automatically if no access more than 16 clock cycles + */ +#define SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE_SHIFT)) & SYSCON_RAM_CTRL_RAMX_CG_OVERRIDE_MASK) + +#define SYSCON_RAM_CTRL_RAMB_CG_OVERRIDE_MASK (0x40000U) +#define SYSCON_RAM_CTRL_RAMB_CG_OVERRIDE_SHIFT (18U) +/*! RAMB_CG_OVERRIDE - RAMB bank clock gating control + * 0b1..Auto clock gating feature is disabled + * 0b0..Memory bank clock is gated automatically if no access more than 16 clock cycles + */ +#define SYSCON_RAM_CTRL_RAMB_CG_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RAM_CTRL_RAMB_CG_OVERRIDE_SHIFT)) & SYSCON_RAM_CTRL_RAMB_CG_OVERRIDE_MASK) +/*! @} */ + +/*! @name GRAY_CODE_LSB - Gray to Binary Converter Gray Code [31:0] */ +/*! @{ */ + +#define SYSCON_GRAY_CODE_LSB_code_gray_31_0_MASK (0xFFFFFFFFU) +#define SYSCON_GRAY_CODE_LSB_code_gray_31_0_SHIFT (0U) +/*! code_gray_31_0 - Gray code [31:0] */ +#define SYSCON_GRAY_CODE_LSB_code_gray_31_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GRAY_CODE_LSB_code_gray_31_0_SHIFT)) & SYSCON_GRAY_CODE_LSB_code_gray_31_0_MASK) +/*! @} */ + +/*! @name GRAY_CODE_MSB - Gray to Binary Converter Gray Code [41:32] */ +/*! @{ */ + +#define SYSCON_GRAY_CODE_MSB_code_gray_41_32_MASK (0x3FFU) +#define SYSCON_GRAY_CODE_MSB_code_gray_41_32_SHIFT (0U) +/*! code_gray_41_32 - Gray code [41:32] */ +#define SYSCON_GRAY_CODE_MSB_code_gray_41_32(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GRAY_CODE_MSB_code_gray_41_32_SHIFT)) & SYSCON_GRAY_CODE_MSB_code_gray_41_32_MASK) +/*! @} */ + +/*! @name BINARY_CODE_LSB - Gray to Binary Converter Binary Code [31:0] */ +/*! @{ */ + +#define SYSCON_BINARY_CODE_LSB_code_bin_31_0_MASK (0xFFFFFFFFU) +#define SYSCON_BINARY_CODE_LSB_code_bin_31_0_SHIFT (0U) +/*! code_bin_31_0 - Binary code [31:0] */ +#define SYSCON_BINARY_CODE_LSB_code_bin_31_0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BINARY_CODE_LSB_code_bin_31_0_SHIFT)) & SYSCON_BINARY_CODE_LSB_code_bin_31_0_MASK) +/*! @} */ + +/*! @name BINARY_CODE_MSB - Gray to Binary Converter Binary Code [41:32] */ +/*! @{ */ + +#define SYSCON_BINARY_CODE_MSB_code_bin_41_32_MASK (0x3FFU) +#define SYSCON_BINARY_CODE_MSB_code_bin_41_32_SHIFT (0U) +/*! code_bin_41_32 - Binary code [41:32] */ +#define SYSCON_BINARY_CODE_MSB_code_bin_41_32(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BINARY_CODE_MSB_code_bin_41_32_SHIFT)) & SYSCON_BINARY_CODE_MSB_code_bin_41_32_MASK) +/*! @} */ + +/*! @name ROP_STATE - ROP State Register */ +/*! @{ */ + +#define SYSCON_ROP_STATE_ROP_STATE_MASK (0xFFFFFFFFU) +#define SYSCON_ROP_STATE_ROP_STATE_SHIFT (0U) +/*! ROP_STATE - ROP state */ +#define SYSCON_ROP_STATE_ROP_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ROP_STATE_ROP_STATE_SHIFT)) & SYSCON_ROP_STATE_ROP_STATE_MASK) +/*! @} */ + +/*! @name OVP_PAD_STATE - OVP_PAD_STATE */ +/*! @{ */ + +#define SYSCON_OVP_PAD_STATE_OVP_PAD_STATE_MASK (0xFFFFFFFFU) +#define SYSCON_OVP_PAD_STATE_OVP_PAD_STATE_SHIFT (0U) +/*! OVP_PAD_STATE - OVP_PAD_STATE */ +#define SYSCON_OVP_PAD_STATE_OVP_PAD_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_OVP_PAD_STATE_OVP_PAD_STATE_SHIFT)) & SYSCON_OVP_PAD_STATE_OVP_PAD_STATE_MASK) +/*! @} */ + +/*! @name PROBE_STATE - PROBE_STATE */ +/*! @{ */ + +#define SYSCON_PROBE_STATE_PROBE_STATE_MASK (0xFFFFFFFFU) +#define SYSCON_PROBE_STATE_PROBE_STATE_SHIFT (0U) +/*! PROBE_STATE - PROBE_STATE */ +#define SYSCON_PROBE_STATE_PROBE_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PROBE_STATE_PROBE_STATE_SHIFT)) & SYSCON_PROBE_STATE_PROBE_STATE_MASK) +/*! @} */ + +/*! @name FT_STATE_A - FT_STATE_A */ +/*! @{ */ + +#define SYSCON_FT_STATE_A_FT_STATE_A_MASK (0xFFFFFFFFU) +#define SYSCON_FT_STATE_A_FT_STATE_A_SHIFT (0U) +/*! FT_STATE_A - FT_STATE_A */ +#define SYSCON_FT_STATE_A_FT_STATE_A(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FT_STATE_A_FT_STATE_A_SHIFT)) & SYSCON_FT_STATE_A_FT_STATE_A_MASK) +/*! @} */ + +/*! @name FT_STATE_B - FT_STATE_B */ +/*! @{ */ + +#define SYSCON_FT_STATE_B_FT_STATE_B_MASK (0xFFFFFFFFU) +#define SYSCON_FT_STATE_B_FT_STATE_B_SHIFT (0U) +/*! FT_STATE_B - FT_STATE_B */ +#define SYSCON_FT_STATE_B_FT_STATE_B(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FT_STATE_B_FT_STATE_B_SHIFT)) & SYSCON_FT_STATE_B_FT_STATE_B_MASK) +/*! @} */ + +/*! @name SRAM_XEN - RAM XEN Control */ +/*! @{ */ + +#define SYSCON_SRAM_XEN_RAMX0_XEN_MASK (0x1U) +#define SYSCON_SRAM_XEN_RAMX0_XEN_SHIFT (0U) +/*! RAMX0_XEN - RAMX0 Execute permission control. + * 0b1..Execute permission is enabled, R/W/X are enabled. + * 0b0..Execute permission is disabled, R/W are enabled. + */ +#define SYSCON_SRAM_XEN_RAMX0_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMX0_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMX0_XEN_MASK) + +#define SYSCON_SRAM_XEN_RAMX1_XEN_MASK (0x2U) +#define SYSCON_SRAM_XEN_RAMX1_XEN_SHIFT (1U) +/*! RAMX1_XEN - RAMX1 Execute permission control. + * 0b1..Execute permission is enabled, R/W/X are enabled. + * 0b0..Execute permission is disabled, R/W are enabled. + */ +#define SYSCON_SRAM_XEN_RAMX1_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMX1_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMX1_XEN_MASK) + +#define SYSCON_SRAM_XEN_RAMA0_XEN_MASK (0x4U) +#define SYSCON_SRAM_XEN_RAMA0_XEN_SHIFT (2U) +/*! RAMA0_XEN - RAMA0 Execute permission control. + * 0b1..Execute permission is enabled, R/W/X are enabled. + * 0b0..Execute permission is disabled, R/W are enabled. + */ +#define SYSCON_SRAM_XEN_RAMA0_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMA0_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMA0_XEN_MASK) + +#define SYSCON_SRAM_XEN_RAMA1_XEN_MASK (0x8U) +#define SYSCON_SRAM_XEN_RAMA1_XEN_SHIFT (3U) +/*! RAMA1_XEN - RAMAx (excepts RAMA0) Execute permission control. + * 0b1..Execute permission is enabled, R/W/X are enabled. + * 0b0..Execute permission is disabled, R/W are enabled. + */ +#define SYSCON_SRAM_XEN_RAMA1_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMA1_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMA1_XEN_MASK) + +#define SYSCON_SRAM_XEN_RAMB_XEN_MASK (0x10U) +#define SYSCON_SRAM_XEN_RAMB_XEN_SHIFT (4U) +/*! RAMB_XEN - RAMBx Execute permission control. + * 0b1..Execute permission is enabled, R/W/X are enabled. + * 0b0..Execute permission is disabled, R/W are enabled. + */ +#define SYSCON_SRAM_XEN_RAMB_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_RAMB_XEN_SHIFT)) & SYSCON_SRAM_XEN_RAMB_XEN_MASK) + +#define SYSCON_SRAM_XEN_LOCK_MASK (0x80000000U) +#define SYSCON_SRAM_XEN_LOCK_SHIFT (31U) +/*! LOCK - This 1-bit field provides a mechanism to limit writes to the this register (and + * SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset. + * 0b0..This register is not locked and can be altered. + * 0b1..This register is locked and cannot be altered. + */ +#define SYSCON_SRAM_XEN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_LOCK_SHIFT)) & SYSCON_SRAM_XEN_LOCK_MASK) +/*! @} */ + +/*! @name SRAM_XEN_DP - RAM XEN Control (Duplicate) */ +/*! @{ */ + +#define SYSCON_SRAM_XEN_DP_RAMX0_XEN_MASK (0x1U) +#define SYSCON_SRAM_XEN_DP_RAMX0_XEN_SHIFT (0U) +/*! RAMX0_XEN - Refer to SRAM_XEN for more details. */ +#define SYSCON_SRAM_XEN_DP_RAMX0_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMX0_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMX0_XEN_MASK) + +#define SYSCON_SRAM_XEN_DP_RAMX1_XEN_MASK (0x2U) +#define SYSCON_SRAM_XEN_DP_RAMX1_XEN_SHIFT (1U) +/*! RAMX1_XEN - Refer to SRAM_XEN for more details. */ +#define SYSCON_SRAM_XEN_DP_RAMX1_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMX1_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMX1_XEN_MASK) + +#define SYSCON_SRAM_XEN_DP_RAMA0_XEN_MASK (0x4U) +#define SYSCON_SRAM_XEN_DP_RAMA0_XEN_SHIFT (2U) +/*! RAMA0_XEN - Refer to SRAM_XEN for more details. */ +#define SYSCON_SRAM_XEN_DP_RAMA0_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMA0_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMA0_XEN_MASK) + +#define SYSCON_SRAM_XEN_DP_RAMA1_XEN_MASK (0x8U) +#define SYSCON_SRAM_XEN_DP_RAMA1_XEN_SHIFT (3U) +/*! RAMA1_XEN - Refer to SRAM_XEN for more details. */ +#define SYSCON_SRAM_XEN_DP_RAMA1_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMA1_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMA1_XEN_MASK) + +#define SYSCON_SRAM_XEN_DP_RAMB_XEN_MASK (0x10U) +#define SYSCON_SRAM_XEN_DP_RAMB_XEN_SHIFT (4U) +/*! RAMB_XEN - Refer to SRAM_XEN for more details. */ +#define SYSCON_SRAM_XEN_DP_RAMB_XEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SRAM_XEN_DP_RAMB_XEN_SHIFT)) & SYSCON_SRAM_XEN_DP_RAMB_XEN_MASK) +/*! @} */ + +/*! @name ELS_OTP_LC_STATE - Life Cycle State Register */ +/*! @{ */ + +#define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_MASK (0xFFU) +#define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_SHIFT (0U) +/*! OTP_LC_STATE - OTP life cycle state */ +#define SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_SHIFT)) & SYSCON_ELS_OTP_LC_STATE_OTP_LC_STATE_MASK) +/*! @} */ + +/*! @name ELS_OTP_LC_STATE_DP - Life Cycle State Register (Duplicate) */ +/*! @{ */ + +#define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_MASK (0xFFU) +#define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_SHIFT (0U) +/*! OTP_LC_STATE_DP - OTP life cycle state */ +#define SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_SHIFT)) & SYSCON_ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP_MASK) +/*! @} */ + +/*! @name DEBUG_LOCK_EN - Control Write Access to Security */ +/*! @{ */ + +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) +/*! LOCK_ALL - Controls write access to the security registers + * 0b1010..Enables write access to all registers + * 0b0000..Any other value than b1010: disables write access to all registers + */ +#define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES - Cortex Debug Features Control */ +/*! @{ */ + +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 non-invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK) +/*! @} */ + +/*! @name DEBUG_FEATURES_DP - Cortex Debug Features Control (Duplicate) */ +/*! @{ */ + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 non-invasive debug control + * 0b01..Disables debug + * 0b10..Enables debug + */ +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK) +/*! @} */ + +/*! @name SWD_ACCESS_CPU0 - CPU0 Software Debug Access */ +/*! @{ */ + +#define SYSCON_SWD_ACCESS_CPU0_SEC_CODE_MASK (0xFFFFFFFFU) +#define SYSCON_SWD_ACCESS_CPU0_SEC_CODE_SHIFT (0U) +/*! SEC_CODE - CPU0 SWD-AP: 0x12345678 + * 0b00010010001101000101011001111000..Value to write to enable CPU0 SWD access. Reading back register is read as 0xA. + * 0b00000000000000000000000000000000..CPU0 DAP is not allowed. Reading back register is read as 0x5. + */ +#define SYSCON_SWD_ACCESS_CPU0_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SWD_ACCESS_CPU0_SEC_CODE_SHIFT)) & SYSCON_SWD_ACCESS_CPU0_SEC_CODE_MASK) +/*! @} */ + +/*! @name DEBUG_AUTH_BEACON - Debug Authentication BEACON */ +/*! @{ */ + +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU) +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U) +/*! BEACON - Sets by the debug authentication code in ROM to pass the debug beacons (Credential + * Beacon and Authentication Beacon) to the application code. + */ +#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK) +/*! @} */ + +/*! @name JTAG_ID - JTAG Chip ID */ +/*! @{ */ + +#define SYSCON_JTAG_ID_JTAG_ID_MASK (0xFFFFFFFFU) +#define SYSCON_JTAG_ID_JTAG_ID_SHIFT (0U) +/*! JTAG_ID - Indicates the device ID */ +#define SYSCON_JTAG_ID_JTAG_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAG_ID_JTAG_ID_SHIFT)) & SYSCON_JTAG_ID_JTAG_ID_MASK) +/*! @} */ + +/*! @name DEVICE_TYPE - Device Type */ +/*! @{ */ + +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_MASK (0xFFFFFFFFU) +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE_SHIFT (0U) +/*! DEVICE_TYPE - Indicates DEVICE TYPE. */ +#define SYSCON_DEVICE_TYPE_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_TYPE_DEVICE_TYPE_SHIFT)) & SYSCON_DEVICE_TYPE_DEVICE_TYPE_MASK) +/*! @} */ + +/*! @name DEVICE_ID0 - Device ID */ +/*! @{ */ + +#define SYSCON_DEVICE_ID0_RAM_SIZE_MASK (0xFU) +#define SYSCON_DEVICE_ID0_RAM_SIZE_SHIFT (0U) +/*! RAM_SIZE - Chip RAM Size + * 0b0000..8KB. + * 0b0001..16KB. + * 0b0010..32KB. + * 0b0011..64KB. + * 0b0100..96KB. + * 0b0101..128KB. + * 0b0110..160KB. + * 0b0111..192KB. + * 0b1000..256KB. + * 0b1001..288KB. + * 0b1010..352KB. + * 0b1011..512KB. + */ +#define SYSCON_DEVICE_ID0_RAM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_RAM_SIZE_SHIFT)) & SYSCON_DEVICE_ID0_RAM_SIZE_MASK) + +#define SYSCON_DEVICE_ID0_FLASH_SIZE_MASK (0xF0U) +#define SYSCON_DEVICE_ID0_FLASH_SIZE_SHIFT (4U) +/*! FLASH_SIZE - Chip FLASH Size + * 0b0000..32KB. + * 0b0001..64KB. + * 0b0010..128KB. + * 0b0011..256KB. + * 0b0100..512KB. + * 0b0101..768KB. + * 0b0110..1MB. + * 0b0111..1.5MB. + * 0b1000..2MB. + */ +#define SYSCON_DEVICE_ID0_FLASH_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_FLASH_SIZE_SHIFT)) & SYSCON_DEVICE_ID0_FLASH_SIZE_MASK) + +#define SYSCON_DEVICE_ID0_SECURITY_MASK (0xF000000U) +#define SYSCON_DEVICE_ID0_SECURITY_SHIFT (24U) +/*! SECURITY + * 0b1010..Non secure version. + * 0b0101..Secure version. + */ +#define SYSCON_DEVICE_ID0_SECURITY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_SECURITY_SHIFT)) & SYSCON_DEVICE_ID0_SECURITY_MASK) +/*! @} */ + +/*! @name DIEID - Chip Revision ID and Number */ +/*! @{ */ + +#define SYSCON_DIEID_MINOR_REVISION_MASK (0xFU) +#define SYSCON_DIEID_MINOR_REVISION_SHIFT (0U) +/*! MINOR_REVISION - Chip minor revision */ +#define SYSCON_DIEID_MINOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MINOR_REVISION_SHIFT)) & SYSCON_DIEID_MINOR_REVISION_MASK) + +#define SYSCON_DIEID_MAJOR_REVISION_MASK (0xF0U) +#define SYSCON_DIEID_MAJOR_REVISION_SHIFT (4U) +/*! MAJOR_REVISION - Chip major revision */ +#define SYSCON_DIEID_MAJOR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MAJOR_REVISION_SHIFT)) & SYSCON_DIEID_MAJOR_REVISION_MASK) + +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF00U) +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (8U) +/*! MCO_NUM_IN_DIE_ID - Chip number */ +#define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCON_Register_Masks */ + + +/* SYSCON - Peripheral instance base addresses */ +/** Peripheral SYSCON base address */ +#define SYSCON_BASE (0x40091000u) +/** Peripheral SYSCON base pointer */ +#define SYSCON ((SYSCON_Type *)SYSCON_BASE) +/** Array initializer of SYSCON peripheral base addresses */ +#define SYSCON_BASE_ADDRS { SYSCON_BASE } +/** Array initializer of SYSCON peripheral base pointers */ +#define SYSCON_BASE_PTRS { SYSCON } + +/*! + * @} + */ /* end of group SYSCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- TRDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRDC_Peripheral_Access_Layer TRDC Peripheral Access Layer + * @{ + */ + +/** TRDC - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x1AC */ + __IO uint32_t MBC_MEM_GLBCFG[4]; /**< MBC Global Configuration Register, array offset: 0x0, array step: index*0x1AC, index2*0x4 */ + uint8_t RESERVED_0[16]; + __IO uint32_t MBC_MEMN_GLBAC[8]; /**< MBC Global Access Control, array offset: 0x20, array step: index*0x1AC, index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x40, array step: index*0x1AC, index2*0x4 */ + uint8_t RESERVED_1[288]; + __IO uint32_t MBC_DOM0_MEM1_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x180, array step: index*0x1AC, index2*0x4 */ + uint8_t RESERVED_2[36]; + __IO uint32_t MBC_DOM0_MEM2_BLK_CFG_W[1]; /**< MBC Memory Block Configuration Word, array offset: 0x1A8, array step: index*0x1AC, index2*0x4 */ + } MBC_INDEX[1]; +} TRDC_Type; + +/* ---------------------------------------------------------------------------- + -- TRDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TRDC_Register_Masks TRDC Register Masks + * @{ + */ + +/*! @name MBC_INDEX_MBC_MEM_GLBCFG - MBC Global Configuration Register */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_MASK (0x3FFU) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_SHIFT (0U) +/*! NBLKS - Number of blocks in this memory */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_NBLKS_MASK) + +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_MASK (0x1F0000U) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT (16U) +/*! SIZE_LOG2 - Log2 size per block */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_SIZE_LOG2_MASK) + +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_MASK (0xC0000000U) +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_SHIFT (30U) +/*! CLRE - Clear Error */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_SHIFT)) & TRDC_MBC_INDEX_MBC_MEM_GLBCFG_CLRE_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_MEM_GLBCFG */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_MEM_GLBCFG */ +#define TRDC_MBC_INDEX_MBC_MEM_GLBCFG_COUNT2 (4U) + +/*! @name MBC_INDEX_MBC_MEMN_GLBAC - MBC Global Access Control */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_MASK (0x1U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_SHIFT (0U) +/*! NUX - NonsecureUser Execute + * 0b0..Execute access is not allowed in Nonsecure User mode. + * 0b1..Execute access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_MASK (0x2U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_SHIFT (1U) +/*! NUW - NonsecureUser Write + * 0b0..Write access is not allowed in Nonsecure User mode. + * 0b1..Write access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_MASK (0x4U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_SHIFT (2U) +/*! NUR - NonsecureUser Read + * 0b0..Read access is not allowed in Nonsecure User mode. + * 0b1..Read access is allowed in Nonsecure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NUR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_MASK (0x10U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_SHIFT (4U) +/*! NPX - NonsecurePriv Execute + * 0b0..Execute access is not allowed in Nonsecure Privilege mode. + * 0b1..Execute access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_MASK (0x20U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_SHIFT (5U) +/*! NPW - NonsecurePriv Write + * 0b0..Write access is not allowed in Nonsecure Privilege mode. + * 0b1..Write access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_MASK (0x40U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_SHIFT (6U) +/*! NPR - NonsecurePriv Read + * 0b0..Read access is not allowed in Nonsecure Privilege mode. + * 0b1..Read access is allowed in Nonsecure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_NPR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_MASK (0x100U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_SHIFT (8U) +/*! SUX - SecureUser Execute + * 0b0..Execute access is not allowed in Secure User mode. + * 0b1..Execute access is allowed in Secure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_MASK (0x200U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_SHIFT (9U) +/*! SUW - SecureUser Write + * 0b0..Write access is not allowed in Secure User mode. + * 0b1..Write access is allowed in Secure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_MASK (0x400U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_SHIFT (10U) +/*! SUR - SecureUser Read + * 0b0..Read access is not allowed in Secure User mode. + * 0b1..Read access is allowed in Secure User mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SUR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_MASK (0x1000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_SHIFT (12U) +/*! SPX - SecurePriv Execute + * 0b0..Execute access is not allowed in Secure Privilege mode. + * 0b1..Execute access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPX_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_MASK (0x2000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_SHIFT (13U) +/*! SPW - SecurePriv Write + * 0b0..Write access is not allowed in Secure Privilege mode. + * 0b1..Write access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPW_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_MASK (0x4000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_SHIFT (14U) +/*! SPR - SecurePriv Read + * 0b0..Read access is not allowed in Secure Privilege mode. + * 0b1..Read access is allowed in Secure Privilege mode. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_SPR_MASK) + +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_SHIFT (31U) +/*! LK - LOCK + * 0b0..This register is not locked and can be altered. + * 0b1..This register is locked and cannot be altered. + */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_SHIFT)) & TRDC_MBC_INDEX_MBC_MEMN_GLBAC_LK_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_MEMN_GLBAC */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_MEMN_GLBAC */ +#define TRDC_MBC_INDEX_MBC_MEMN_GLBAC_COUNT2 (8U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM0_BLK_CFG_W_MBC_DOM0_MEM0_BLK_CFG_W_COUNT2 (8U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM1_BLK_CFG_W_MBC_DOM0_MEM1_BLK_CFG_W_COUNT2 (1U) + +/*! @name MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W - MBC Memory Block Configuration Word */ +/*! @{ */ + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK (0x7U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT (0U) +/*! MBACSEL0 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK (0x8U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT (3U) +/*! NSE0 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE0_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK (0x70U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT (4U) +/*! MBACSEL1 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK (0x80U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT (7U) +/*! NSE1 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE1_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK (0x700U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT (8U) +/*! MBACSEL2 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK (0x800U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT (11U) +/*! NSE2 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE2_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK (0x7000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT (12U) +/*! MBACSEL3 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK (0x8000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT (15U) +/*! NSE3 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE3_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK (0x70000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT (16U) +/*! MBACSEL4 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK (0x80000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT (19U) +/*! NSE4 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE4_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK (0x700000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT (20U) +/*! MBACSEL5 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK (0x800000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT (23U) +/*! NSE5 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE5_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK (0x7000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT (24U) +/*! MBACSEL6 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK (0x8000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT (27U) +/*! NSE6 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE6_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK (0x70000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT (28U) +/*! MBACSEL7 - Memory Block Access Control Select for block B + * 0b000..select MBC_MEMN_GLBAC0 access control policy for block B + * 0b001..select MBC_MEMN_GLBAC1 access control policy for block B + * 0b010..select MBC_MEMN_GLBAC2 access control policy for block B + * 0b011..select MBC_MEMN_GLBAC3 access control policy for block B + * 0b100..select MBC_MEMN_GLBAC4 access control policy for block B + * 0b101..select MBC_MEMN_GLBAC5 access control policy for block B + * 0b110..select MBC_MEMN_GLBAC6 access control policy for block B + * 0b111..select MBC_MEMN_GLBAC7 access control policy for block B + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_MBACSEL7_MASK) + +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK (0x80000000U) +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT (31U) +/*! NSE7 - NonSecure Enable for block B + * 0b0..Secure accesses to block B are based on corresponding MBACSEL field in this register + * (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]), nonsecure accesses to block B are not allowed. + * 0b1..Secure accesses to block B are not allowed, nonsecure accesses to block B are based on corresponding + * MBACSEL field in this register (MBCm_DOMd_MEMs_BLK_CFG_Ww[MBACSEL]). + */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7(x) (((uint32_t)(((uint32_t)(x)) << TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_SHIFT)) & TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_NSE7_MASK) +/*! @} */ + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_COUNT (1U) + +/* The count of TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W */ +#define TRDC_MBC_INDEX_MBC_INDEX_DOM0_MEM2_BLK_CFG_W_MBC_DOM0_MEM2_BLK_CFG_W_COUNT2 (1U) + + +/*! + * @} + */ /* end of group TRDC_Register_Masks */ + + +/* TRDC - Peripheral instance base addresses */ +/** Peripheral MBC0 base address */ +#define MBC0_BASE (0x4008E000u) +/** Peripheral MBC0 base pointer */ +#define MBC0 ((TRDC_Type *)MBC0_BASE) +/** Array initializer of TRDC peripheral base addresses */ +#define TRDC_BASE_ADDRS { MBC0_BASE } +/** Array initializer of TRDC peripheral base pointers */ +#define TRDC_BASE_PTRS { MBC0 } +#define MBC0_MEMORY_CFG_WORD_COUNT {1,2,4,1} +#define MBC1_MEMORY_CFG_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_CFG_WORD_COUNT {9,6,1,1} +#define MBC3_MEMORY_CFG_WORD_COUNT {3,0,0,0} +#define MBC_MEMORY_CFG_WORD_COUNT {MBC0_MEMORY_CFG_WORD_COUNT , MBC1_MEMORY_CFG_WORD_COUNT, MBC2_MEMORY_CFG_WORD_COUNT, MBC3_MEMORY_CFG_WORD_COUNT} +#define MBC0_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC1_MEMORY_NSE_WORD_COUNT {1,1,1,1} +#define MBC2_MEMORY_NSE_WORD_COUNT {3,2,1,1} +#define MBC3_MEMORY_NSE_WORD_COUNT {1,0,0,0} +#define MBC_MEMORY_NSE_WORD_COUNT {MBC0_MEMORY_NSE_WORD_COUNT , MBC1_MEMORY_NSE_WORD_COUNT, MBC2_MEMORY_NSE_WORD_COUNT, MBC3_MEMORY_NSE_WORD_COUNT} + + +/*! + * @} + */ /* end of group TRDC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __I uint8_t PERID; /**< Peripheral ID, offset: 0x0 */ + uint8_t RESERVED_0[3]; + __I uint8_t IDCOMP; /**< Peripheral ID Complement, offset: 0x4 */ + uint8_t RESERVED_1[3]; + __I uint8_t REV; /**< Peripheral Revision, offset: 0x8 */ + uint8_t RESERVED_2[19]; + __IO uint8_t OTGCTL; /**< OTG Control, offset: 0x1C */ + uint8_t RESERVED_3[99]; + __IO uint8_t ISTAT; /**< Interrupt Status, offset: 0x80 */ + uint8_t RESERVED_4[3]; + __IO uint8_t INTEN; /**< Interrupt Enable, offset: 0x84 */ + uint8_t RESERVED_5[3]; + __IO uint8_t ERRSTAT; /**< Error Interrupt Status, offset: 0x88 */ + uint8_t RESERVED_6[3]; + __IO uint8_t ERREN; /**< Error Interrupt Enable, offset: 0x8C */ + uint8_t RESERVED_7[3]; + __I uint8_t STAT; /**< Status, offset: 0x90 */ + uint8_t RESERVED_8[3]; + __IO uint8_t CTL; /**< Control, offset: 0x94 */ + uint8_t RESERVED_9[3]; + __IO uint8_t ADDR; /**< Address, offset: 0x98 */ + uint8_t RESERVED_10[3]; + __IO uint8_t BDTPAGE1; /**< BDT Page 1, offset: 0x9C */ + uint8_t RESERVED_11[3]; + __I uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */ + uint8_t RESERVED_12[3]; + __I uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */ + uint8_t RESERVED_13[11]; + __IO uint8_t BDTPAGE2; /**< BDT Page 2, offset: 0xB0 */ + uint8_t RESERVED_14[3]; + __IO uint8_t BDTPAGE3; /**< BDT Page 3, offset: 0xB4 */ + uint8_t RESERVED_15[11]; + struct { /* offset: 0xC0, array step: 0x4 */ + __IO uint8_t ENDPT; /**< Endpoint Control, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_0[3]; + } ENDPOINT[16]; + __IO uint8_t USBCTRL; /**< USB Control, offset: 0x100 */ + uint8_t RESERVED_16[3]; + __I uint8_t OBSERVE; /**< USB OTG Observe, offset: 0x104 */ + uint8_t RESERVED_17[3]; + __IO uint8_t CONTROL; /**< USB OTG Control, offset: 0x108 */ + uint8_t RESERVED_18[3]; + __IO uint8_t USBTRC0; /**< USB Transceiver Control 0, offset: 0x10C */ + uint8_t RESERVED_19[23]; + uint8_t KEEP_ALIVE_CTRL_RSVD; /**< Reserved, offset: 0x124 */ + uint8_t RESERVED_20[3]; + uint8_t KEEP_ALIVE_WKCTRL_RSVD; /**< Reserved, offset: 0x128 */ + uint8_t RESERVED_21[3]; + __IO uint8_t MISCCTRL; /**< Miscellaneous Control, offset: 0x12C */ + uint8_t RESERVED_22[3]; + __IO uint8_t STALL_IL_DIS; /**< Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction, offset: 0x130 */ + uint8_t RESERVED_23[3]; + __IO uint8_t STALL_IH_DIS; /**< Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction, offset: 0x134 */ + uint8_t RESERVED_24[3]; + __IO uint8_t STALL_OL_DIS; /**< Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction, offset: 0x138 */ + uint8_t RESERVED_25[3]; + __IO uint8_t STALL_OH_DIS; /**< Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction, offset: 0x13C */ + uint8_t RESERVED_26[3]; + __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock Recovery Control, offset: 0x140 */ + uint8_t RESERVED_27[3]; + __IO uint8_t CLK_RECOVER_IRC_EN; /**< FIRC Oscillator Enable, offset: 0x144 */ + uint8_t RESERVED_28[15]; + __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock Recovery Combined Interrupt Enable, offset: 0x154 */ + uint8_t RESERVED_29[7]; + __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock Recovery Separated Interrupt Status, offset: 0x15C */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name PERID - Peripheral ID */ +/*! @{ */ + +#define USB_PERID_ID_MASK (0x3FU) +#define USB_PERID_ID_SHIFT (0U) +/*! ID - Peripheral Identification */ +#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK) +/*! @} */ + +/*! @name IDCOMP - Peripheral ID Complement */ +/*! @{ */ + +#define USB_IDCOMP_NID_MASK (0x3FU) +#define USB_IDCOMP_NID_SHIFT (0U) +/*! NID - Negative Peripheral ID */ +#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK) +/*! @} */ + +/*! @name REV - Peripheral Revision */ +/*! @{ */ + +#define USB_REV_REV_MASK (0xFFU) +#define USB_REV_REV_SHIFT (0U) +/*! REV - Revision */ +#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK) +/*! @} */ + +/*! @name OTGCTL - OTG Control */ +/*! @{ */ + +#define USB_OTGCTL_DPHIGH_MASK (0x80U) +#define USB_OTGCTL_DPHIGH_SHIFT (7U) +/*! DPHIGH - D+ Data Line Pullup Resistor Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK) +/*! @} */ + +/*! @name ISTAT - Interrupt Status */ +/*! @{ */ + +#define USB_ISTAT_USBRST_MASK (0x1U) +#define USB_ISTAT_USBRST_SHIFT (0U) +/*! USBRST - USB Reset Flag + * 0b0..Not detected + * 0b1..Detected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK) + +#define USB_ISTAT_ERROR_MASK (0x2U) +#define USB_ISTAT_ERROR_SHIFT (1U) +/*! ERROR - Error Flag + * 0b0..Error did not occur + * 0b1..Error occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK) + +#define USB_ISTAT_SOFTOK_MASK (0x4U) +#define USB_ISTAT_SOFTOK_SHIFT (2U) +/*! SOFTOK - Start Of Frame (SOF) Token Flag + * 0b0..Did not receive + * 0b1..Received + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK) + +#define USB_ISTAT_TOKDNE_MASK (0x8U) +#define USB_ISTAT_TOKDNE_SHIFT (3U) +/*! TOKDNE - Current Token Processing Flag + * 0b0..Not processed + * 0b1..Processed + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK) + +#define USB_ISTAT_SLEEP_MASK (0x10U) +#define USB_ISTAT_SLEEP_SHIFT (4U) +/*! SLEEP - Sleep Flag + * 0b0..Interrupt did not occur + * 0b1..Interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK) + +#define USB_ISTAT_RESUME_MASK (0x20U) +#define USB_ISTAT_RESUME_SHIFT (5U) +/*! RESUME - Resume Flag + * 0b0..Interrupt did not occur + * 0b1..Interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK) + +#define USB_ISTAT_STALL_MASK (0x80U) +#define USB_ISTAT_STALL_SHIFT (7U) +/*! STALL - Stall Interrupt Flag + * 0b0..Interrupt did not occur + * 0b1..Interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK) +/*! @} */ + +/*! @name INTEN - Interrupt Enable */ +/*! @{ */ + +#define USB_INTEN_USBRSTEN_MASK (0x1U) +#define USB_INTEN_USBRSTEN_SHIFT (0U) +/*! USBRSTEN - USBRST Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK) + +#define USB_INTEN_ERROREN_MASK (0x2U) +#define USB_INTEN_ERROREN_SHIFT (1U) +/*! ERROREN - ERROR Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK) + +#define USB_INTEN_SOFTOKEN_MASK (0x4U) +#define USB_INTEN_SOFTOKEN_SHIFT (2U) +/*! SOFTOKEN - SOFTOK Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK) + +#define USB_INTEN_TOKDNEEN_MASK (0x8U) +#define USB_INTEN_TOKDNEEN_SHIFT (3U) +/*! TOKDNEEN - TOKDNE Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK) + +#define USB_INTEN_SLEEPEN_MASK (0x10U) +#define USB_INTEN_SLEEPEN_SHIFT (4U) +/*! SLEEPEN - SLEEP Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK) + +#define USB_INTEN_RESUMEEN_MASK (0x20U) +#define USB_INTEN_RESUMEEN_SHIFT (5U) +/*! RESUMEEN - RESUME Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK) + +#define USB_INTEN_STALLEN_MASK (0x80U) +#define USB_INTEN_STALLEN_SHIFT (7U) +/*! STALLEN - STALL Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK) +/*! @} */ + +/*! @name ERRSTAT - Error Interrupt Status */ +/*! @{ */ + +#define USB_ERRSTAT_PIDERR_MASK (0x1U) +#define USB_ERRSTAT_PIDERR_SHIFT (0U) +/*! PIDERR - PID Error Flag + * 0b0..Did not fail + * 0b1..Failed + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK) + +#define USB_ERRSTAT_CRC5EOF_MASK (0x2U) +#define USB_ERRSTAT_CRC5EOF_SHIFT (1U) +/*! CRC5EOF - CRC5 Error or End of Frame Error Flag + * 0b0..Interrupt did not occur + * 0b1..Interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK) + +#define USB_ERRSTAT_CRC16_MASK (0x4U) +#define USB_ERRSTAT_CRC16_SHIFT (2U) +/*! CRC16 - CRC16 Error Flag + * 0b0..Not rejected + * 0b1..Rejected + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK) + +#define USB_ERRSTAT_DFN8_MASK (0x8U) +#define USB_ERRSTAT_DFN8_SHIFT (3U) +/*! DFN8 - Data Field Not 8 Bits Flag + * 0b0..Integer number of bytes + * 0b1..Not an integer number of bytes + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK) + +#define USB_ERRSTAT_BTOERR_MASK (0x10U) +#define USB_ERRSTAT_BTOERR_SHIFT (4U) +/*! BTOERR - Bus Turnaround Timeout Error Flag + * 0b0..Not timed out + * 0b1..Timed out + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK) + +#define USB_ERRSTAT_DMAERR_MASK (0x20U) +#define USB_ERRSTAT_DMAERR_SHIFT (5U) +/*! DMAERR - DMA Access Error Flag + * 0b0..Interrupt did not occur + * 0b1..Interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK) + +#define USB_ERRSTAT_OWNERR_MASK (0x40U) +#define USB_ERRSTAT_OWNERR_SHIFT (6U) +/*! OWNERR - BD Unavailable Error Flag + * 0b0..Interrupt did not occur + * 0b1..Interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ERRSTAT_OWNERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK) + +#define USB_ERRSTAT_BTSERR_MASK (0x80U) +#define USB_ERRSTAT_BTSERR_SHIFT (7U) +/*! BTSERR - Bit Stuff Error Flag + * 0b0..Packet not rejected due to the error + * 0b1..Packet rejected due to the error + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK) +/*! @} */ + +/*! @name ERREN - Error Interrupt Enable */ +/*! @{ */ + +#define USB_ERREN_PIDERREN_MASK (0x1U) +#define USB_ERREN_PIDERREN_SHIFT (0U) +/*! PIDERREN - PIDERR Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK) + +#define USB_ERREN_CRC5EOFEN_MASK (0x2U) +#define USB_ERREN_CRC5EOFEN_SHIFT (1U) +/*! CRC5EOFEN - CRC5/EOF Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK) + +#define USB_ERREN_CRC16EN_MASK (0x4U) +#define USB_ERREN_CRC16EN_SHIFT (2U) +/*! CRC16EN - CRC16 Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK) + +#define USB_ERREN_DFN8EN_MASK (0x8U) +#define USB_ERREN_DFN8EN_SHIFT (3U) +/*! DFN8EN - DFN8 (Data Field Not Integer Number of Bytes) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK) + +#define USB_ERREN_BTOERREN_MASK (0x10U) +#define USB_ERREN_BTOERREN_SHIFT (4U) +/*! BTOERREN - BTOERR (Bus Timeout Error) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK) + +#define USB_ERREN_DMAERREN_MASK (0x20U) +#define USB_ERREN_DMAERREN_SHIFT (5U) +/*! DMAERREN - DMAERR Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK) + +#define USB_ERREN_OWNERREN_MASK (0x40U) +#define USB_ERREN_OWNERREN_SHIFT (6U) +/*! OWNERREN - OWNERR Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_OWNERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK) + +#define USB_ERREN_BTSERREN_MASK (0x80U) +#define USB_ERREN_BTSERREN_SHIFT (7U) +/*! BTSERREN - BTSERR (Bit Stuff Error) Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK) +/*! @} */ + +/*! @name STAT - Status */ +/*! @{ */ + +#define USB_STAT_ODD_MASK (0x4U) +#define USB_STAT_ODD_SHIFT (2U) +/*! ODD - Odd Bank + * 0b0..Not in the odd bank + * 0b1..In the odd bank + */ +#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK) + +#define USB_STAT_TX_MASK (0x8U) +#define USB_STAT_TX_SHIFT (3U) +/*! TX - Transmit Indicator + * 0b0..Receive + * 0b1..Transmit + */ +#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK) + +#define USB_STAT_ENDP_MASK (0xF0U) +#define USB_STAT_ENDP_SHIFT (4U) +/*! ENDP - Endpoint address */ +#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK) +/*! @} */ + +/*! @name CTL - Control */ +/*! @{ */ + +#define USB_CTL_USBENSOFEN_MASK (0x1U) +#define USB_CTL_USBENSOFEN_SHIFT (0U) +/*! USBENSOFEN - USB Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK) + +#define USB_CTL_ODDRST_MASK (0x2U) +#define USB_CTL_ODDRST_SHIFT (1U) +/*! ODDRST - Odd Reset */ +#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK) + +#define USB_CTL_RESUME_MASK (0x4U) +#define USB_CTL_RESUME_SHIFT (2U) +/*! RESUME - Resume */ +#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK) + +#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U) +#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U) +/*! TXSUSPENDTOKENBUSY - TXD Suspend And Token Busy */ +#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) + +#define USB_CTL_SE0_MASK (0x40U) +#define USB_CTL_SE0_SHIFT (6U) +/*! SE0 - Live USB Single-Ended Zero signal */ +#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK) +/*! @} */ + +/*! @name ADDR - Address */ +/*! @{ */ + +#define USB_ADDR_ADDR_MASK (0x7FU) +#define USB_ADDR_ADDR_SHIFT (0U) +/*! ADDR - USB Address */ +#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK) +/*! @} */ + +/*! @name BDTPAGE1 - BDT Page 1 */ +/*! @{ */ + +#define USB_BDTPAGE1_BDTBA_MASK (0xFEU) +#define USB_BDTPAGE1_BDTBA_SHIFT (1U) +/*! BDTBA - BDT Base Address */ +#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK) +/*! @} */ + +/*! @name FRMNUML - Frame Number Register Low */ +/*! @{ */ + +#define USB_FRMNUML_FRM_MASK (0xFFU) +#define USB_FRMNUML_FRM_SHIFT (0U) +/*! FRM - Frame Number, Bits 0-7 */ +#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK) +/*! @} */ + +/*! @name FRMNUMH - Frame Number Register High */ +/*! @{ */ + +#define USB_FRMNUMH_FRM_MASK (0x7U) +#define USB_FRMNUMH_FRM_SHIFT (0U) +/*! FRM - Frame Number, Bits 8-10 */ +#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK) +/*! @} */ + +/*! @name BDTPAGE2 - BDT Page 2 */ +/*! @{ */ + +#define USB_BDTPAGE2_BDTBA_MASK (0xFFU) +#define USB_BDTPAGE2_BDTBA_SHIFT (0U) +/*! BDTBA - BDT Base Address */ +#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK) +/*! @} */ + +/*! @name BDTPAGE3 - BDT Page 3 */ +/*! @{ */ + +#define USB_BDTPAGE3_BDTBA_MASK (0xFFU) +#define USB_BDTPAGE3_BDTBA_SHIFT (0U) +/*! BDTBA - BDT Base Address */ +#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK) +/*! @} */ + +/*! @name ENDPT - Endpoint Control */ +/*! @{ */ + +#define USB_ENDPT_EPHSHK_MASK (0x1U) +#define USB_ENDPT_EPHSHK_SHIFT (0U) +/*! EPHSHK - Endpoint Handshaking Enable */ +#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK) + +#define USB_ENDPT_EPSTALL_MASK (0x2U) +#define USB_ENDPT_EPSTALL_SHIFT (1U) +/*! EPSTALL - Endpoint Stalled */ +#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK) + +#define USB_ENDPT_EPTXEN_MASK (0x4U) +#define USB_ENDPT_EPTXEN_SHIFT (2U) +/*! EPTXEN - Endpoint for TX transfers enable */ +#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK) + +#define USB_ENDPT_EPRXEN_MASK (0x8U) +#define USB_ENDPT_EPRXEN_SHIFT (3U) +/*! EPRXEN - Endpoint for RX transfers enable */ +#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK) + +#define USB_ENDPT_EPCTLDIS_MASK (0x10U) +#define USB_ENDPT_EPCTLDIS_SHIFT (4U) +/*! EPCTLDIS - Control Transfer Disable + * 0b0..Enable + * 0b1..Disable + */ +#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK) +/*! @} */ + +/* The count of USB_ENDPT */ +#define USB_ENDPT_COUNT (16U) + +/*! @name USBCTRL - USB Control */ +/*! @{ */ + +#define USB_USBCTRL_DPDM_LANE_REVERSE_MASK (0x4U) +#define USB_USBCTRL_DPDM_LANE_REVERSE_SHIFT (2U) +/*! DPDM_LANE_REVERSE - DP and DM Lane Reversal Control + * 0b0..Standard USB DP and DM package pin assignment + * 0b1..Reverse roles of USB DP and DM package pins + */ +#define USB_USBCTRL_DPDM_LANE_REVERSE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_DPDM_LANE_REVERSE_SHIFT)) & USB_USBCTRL_DPDM_LANE_REVERSE_MASK) + +#define USB_USBCTRL_UARTSEL_MASK (0x10U) +#define USB_USBCTRL_UARTSEL_SHIFT (4U) +/*! UARTSEL - UART Select + * 0b0..USB DP and DM external package pins are used for USB signaling. + * 0b1..USB DP and DM external package pins are used for UART signaling. + */ +#define USB_USBCTRL_UARTSEL(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK) + +#define USB_USBCTRL_UARTCHLS_MASK (0x20U) +#define USB_USBCTRL_UARTCHLS_SHIFT (5U) +/*! UARTCHLS - UART Signal Channel Select + * 0b0..USB DP and DM signals are used as UART TX/RX. + * 0b1..USB DP and DM signals are used as UART RX/TX. + */ +#define USB_USBCTRL_UARTCHLS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK) + +#define USB_USBCTRL_PDE_MASK (0x40U) +#define USB_USBCTRL_PDE_SHIFT (6U) +/*! PDE - Pulldown Enable + * 0b0..Disable on D+ and D- + * 0b1..Enable on D+ and D- + */ +#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK) + +#define USB_USBCTRL_SUSP_MASK (0x80U) +#define USB_USBCTRL_SUSP_SHIFT (7U) +/*! SUSP - Suspend + * 0b0..Not in Suspend state + * 0b1..In Suspend state + */ +#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK) +/*! @} */ + +/*! @name OBSERVE - USB OTG Observe */ +/*! @{ */ + +#define USB_OBSERVE_DMPD_MASK (0x10U) +#define USB_OBSERVE_DMPD_SHIFT (4U) +/*! DMPD - D- Pulldown + * 0b0..Disabled + * 0b1..Enabled + */ +#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK) + +#define USB_OBSERVE_DPPD_MASK (0x40U) +#define USB_OBSERVE_DPPD_SHIFT (6U) +/*! DPPD - D+ Pulldown + * 0b0..Disabled + * 0b1..Enabled + */ +#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK) + +#define USB_OBSERVE_DPPU_MASK (0x80U) +#define USB_OBSERVE_DPPU_SHIFT (7U) +/*! DPPU - D+ Pullup + * 0b0..Disabled + * 0b1..Enabled + */ +#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK) +/*! @} */ + +/*! @name CONTROL - USB OTG Control */ +/*! @{ */ + +#define USB_CONTROL_VBUS_SOURCE_SEL_MASK (0x1U) +#define USB_CONTROL_VBUS_SOURCE_SEL_SHIFT (0U) +/*! VBUS_SOURCE_SEL - VBUS Monitoring Source Select + * 0b0..Reserved + * 0b1..Resistive divider attached to a GPIO pin + */ +#define USB_CONTROL_VBUS_SOURCE_SEL(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_VBUS_SOURCE_SEL_SHIFT)) & USB_CONTROL_VBUS_SOURCE_SEL_MASK) + +#define USB_CONTROL_SESS_VLD_MASK (0x2U) +#define USB_CONTROL_SESS_VLD_SHIFT (1U) +/*! SESS_VLD - VBUS Session Valid status + * 0b1..Above + * 0b0..Below + */ +#define USB_CONTROL_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_SESS_VLD_SHIFT)) & USB_CONTROL_SESS_VLD_MASK) + +#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U) +#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U) +/*! DPPULLUPNONOTG - DP Pullup in Non-OTG Device Mode + * 0b0..Disable + * 0b1..Enabled + */ +#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK) +/*! @} */ + +/*! @name USBTRC0 - USB Transceiver Control 0 */ +/*! @{ */ + +#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U) +#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U) +/*! USB_RESUME_INT - USB Asynchronous Interrupt + * 0b0..Not generated + * 0b1..Generated because of the USB asynchronous interrupt + */ +#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK) + +#define USB_USBTRC0_SYNC_DET_MASK (0x2U) +#define USB_USBTRC0_SYNC_DET_SHIFT (1U) +/*! SYNC_DET - Synchronous USB Interrupt Detect + * 0b0..Not detected + * 0b1..Detected + */ +#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK) + +#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U) +#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U) +/*! USB_CLK_RECOVERY_INT - Combined USB Clock Recovery interrupt status */ +#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) + +#define USB_USBTRC0_VREDG_DET_MASK (0x8U) +#define USB_USBTRC0_VREDG_DET_SHIFT (3U) +/*! VREDG_DET - VREGIN Rising Edge Interrupt Detect + * 0b0..Not detected + * 0b1..Detected + */ +#define USB_USBTRC0_VREDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK) + +#define USB_USBTRC0_VFEDG_DET_MASK (0x10U) +#define USB_USBTRC0_VFEDG_DET_SHIFT (4U) +/*! VFEDG_DET - VREGIN Falling Edge Interrupt Detect + * 0b0..Not detected + * 0b1..Detected + */ +#define USB_USBTRC0_VFEDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK) + +#define USB_USBTRC0_USBRESMEN_MASK (0x20U) +#define USB_USBTRC0_USBRESMEN_SHIFT (5U) +/*! USBRESMEN - Asynchronous Resume Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK) + +#define USB_USBTRC0_VREGIN_STS_MASK (0x40U) +#define USB_USBTRC0_VREGIN_STS_SHIFT (6U) +/*! VREGIN_STS - VREGIN Status */ +#define USB_USBTRC0_VREGIN_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREGIN_STS_SHIFT)) & USB_USBTRC0_VREGIN_STS_MASK) + +#define USB_USBTRC0_USBRESET_MASK (0x80U) +#define USB_USBTRC0_USBRESET_SHIFT (7U) +/*! USBRESET - USB Reset + * 0b0..Normal USBFS operation + * 0b1..Returns USBFS to its reset state + */ +#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK) +/*! @} */ + +/*! @name MISCCTRL - Miscellaneous Control */ +/*! @{ */ + +#define USB_MISCCTRL_OWNERRISODIS_MASK (0x4U) +#define USB_MISCCTRL_OWNERRISODIS_SHIFT (2U) +/*! OWNERRISODIS - OWN Error Detect for ISO IN and ISO OUT Disable + * 0b0..Enable + * 0b1..Disable + */ +#define USB_MISCCTRL_OWNERRISODIS(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK) + +#define USB_MISCCTRL_VREDG_EN_MASK (0x8U) +#define USB_MISCCTRL_VREDG_EN_SHIFT (3U) +/*! VREDG_EN - VREGIN Rising Edge Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_MISCCTRL_VREDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK) + +#define USB_MISCCTRL_VFEDG_EN_MASK (0x10U) +#define USB_MISCCTRL_VFEDG_EN_SHIFT (4U) +/*! VFEDG_EN - VREGIN Falling Edge Interrupt Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_MISCCTRL_VFEDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK) + +#define USB_MISCCTRL_STL_ADJ_EN_MASK (0x80U) +#define USB_MISCCTRL_STL_ADJ_EN_SHIFT (7U) +/*! STL_ADJ_EN - USB Peripheral Mode Stall Adjust Enable + * 0b0..If ENDPTn[END_STALL] = 1, both IN and OUT directions for the associated endpoint stalls. + * 0b1..If ENDPTn[END_STALL] = 1, the STALL_xx_DIS registers control which directions for the associated endpoint stalls. + */ +#define USB_MISCCTRL_STL_ADJ_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_STL_ADJ_EN_SHIFT)) & USB_MISCCTRL_STL_ADJ_EN_MASK) +/*! @} */ + +/*! @name STALL_IL_DIS - Peripheral Mode Stall Disable for Endpoints 7 to 0 in IN Direction */ +/*! @{ */ + +#define USB_STALL_IL_DIS_STALL_I_DIS0_MASK (0x1U) +#define USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT (0U) +/*! STALL_I_DIS0 - Disable Endpoint 0 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS0_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS1_MASK (0x2U) +#define USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT (1U) +/*! STALL_I_DIS1 - Disable Endpoint 1 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS1_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS2_MASK (0x4U) +#define USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT (2U) +/*! STALL_I_DIS2 - Disable Endpoint 2 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS2_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS3_MASK (0x8U) +#define USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT (3U) +/*! STALL_I_DIS3 - Disable Endpoint 3 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS3_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS4_MASK (0x10U) +#define USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT (4U) +/*! STALL_I_DIS4 - Disable Endpoint 4 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS4_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS5_MASK (0x20U) +#define USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT (5U) +/*! STALL_I_DIS5 - Disable Endpoint 5 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS5_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS6_MASK (0x40U) +#define USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT (6U) +/*! STALL_I_DIS6 - Disable Endpoint 6 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS6_MASK) + +#define USB_STALL_IL_DIS_STALL_I_DIS7_MASK (0x80U) +#define USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT (7U) +/*! STALL_I_DIS7 - Disable Endpoint 7 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IL_DIS_STALL_I_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS7_MASK) +/*! @} */ + +/*! @name STALL_IH_DIS - Peripheral Mode Stall Disable for Endpoints 15 to 8 in IN Direction */ +/*! @{ */ + +#define USB_STALL_IH_DIS_STALL_I_DIS8_MASK (0x1U) +#define USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT (0U) +/*! STALL_I_DIS8 - Disable Endpoint 8 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS8_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS9_MASK (0x2U) +#define USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT (1U) +/*! STALL_I_DIS9 - Disable Endpoint 9 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS9_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS10_MASK (0x4U) +#define USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT (2U) +/*! STALL_I_DIS10 - Disable Endpoint 10 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS10_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS11_MASK (0x8U) +#define USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT (3U) +/*! STALL_I_DIS11 - Disable Endpoint 11 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS11_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS12_MASK (0x10U) +#define USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT (4U) +/*! STALL_I_DIS12 - Disable Endpoint 12 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS12_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS13_MASK (0x20U) +#define USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT (5U) +/*! STALL_I_DIS13 - Disable Endpoint 13 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS13_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS14_MASK (0x40U) +#define USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT (6U) +/*! STALL_I_DIS14 - Disable Endpoint 14 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS14_MASK) + +#define USB_STALL_IH_DIS_STALL_I_DIS15_MASK (0x80U) +#define USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT (7U) +/*! STALL_I_DIS15 - Disable Endpoint 15 IN Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_IH_DIS_STALL_I_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS15_MASK) +/*! @} */ + +/*! @name STALL_OL_DIS - Peripheral Mode Stall Disable for Endpoints 7 to 0 in OUT Direction */ +/*! @{ */ + +#define USB_STALL_OL_DIS_STALL_O_DIS0_MASK (0x1U) +#define USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT (0U) +/*! STALL_O_DIS0 - Disable Endpoint 0 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS0_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS1_MASK (0x2U) +#define USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT (1U) +/*! STALL_O_DIS1 - Disable Endpoint 1 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS1_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS2_MASK (0x4U) +#define USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT (2U) +/*! STALL_O_DIS2 - Disable Endpoint 2 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS2_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS3_MASK (0x8U) +#define USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT (3U) +/*! STALL_O_DIS3 - Disable Endpoint 3 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS3_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS4_MASK (0x10U) +#define USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT (4U) +/*! STALL_O_DIS4 - Disable Endpoint 4 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS4_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS5_MASK (0x20U) +#define USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT (5U) +/*! STALL_O_DIS5 - Disable Endpoint 5 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS5_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS6_MASK (0x40U) +#define USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT (6U) +/*! STALL_O_DIS6 - Disable Endpoint 6 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS6_MASK) + +#define USB_STALL_OL_DIS_STALL_O_DIS7_MASK (0x80U) +#define USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT (7U) +/*! STALL_O_DIS7 - Disable Endpoint 7 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OL_DIS_STALL_O_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS7_MASK) +/*! @} */ + +/*! @name STALL_OH_DIS - Peripheral Mode Stall Disable for Endpoints 15 to 8 in OUT Direction */ +/*! @{ */ + +#define USB_STALL_OH_DIS_STALL_O_DIS8_MASK (0x1U) +#define USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT (0U) +/*! STALL_O_DIS8 - Disable Endpoint 8 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS8_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS9_MASK (0x2U) +#define USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT (1U) +/*! STALL_O_DIS9 - Disable Endpoint 9 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS9_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS10_MASK (0x4U) +#define USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT (2U) +/*! STALL_O_DIS10 - Disable Endpoint 10 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS10_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS11_MASK (0x8U) +#define USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT (3U) +/*! STALL_O_DIS11 - Disable Endpoint 11 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS11_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS12_MASK (0x10U) +#define USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT (4U) +/*! STALL_O_DIS12 - Disable endpoint 12 OUT direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS12_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS13_MASK (0x20U) +#define USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT (5U) +/*! STALL_O_DIS13 - Disable Endpoint 13 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS13_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS14_MASK (0x40U) +#define USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT (6U) +/*! STALL_O_DIS14 - Disable Endpoint 14 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS14_MASK) + +#define USB_STALL_OH_DIS_STALL_O_DIS15_MASK (0x80U) +#define USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT (7U) +/*! STALL_O_DIS15 - Disable Endpoint 15 OUT Direction + * 0b0..Enable + * 0b1..Disable + */ +#define USB_STALL_OH_DIS_STALL_O_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS15_MASK) +/*! @} */ + +/*! @name CLK_RECOVER_CTRL - USB Clock Recovery Control */ +/*! @{ */ + +#define USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_MASK (0x8U) +#define USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_SHIFT (3U) +/*! TRIM_INIT_VAL_SEL - Selects the source for the initial FIRC trim fine value used after a reset. + * 0b0..Mid-scale + * 0b1..IFR + */ +#define USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_SHIFT)) & USB_CLK_RECOVER_CTRL_TRIM_INIT_VAL_SEL_MASK) + +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U) +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U) +/*! RESTART_IFRTRIM_EN - Restart from IFR Trim Value + * 0b0..Trim fine adjustment always works based on the previous updated trim fine value. + * 0b1..Trim fine restarts from the IFR trim value whenever you detect bus_reset or bus_resume or deassert module enable. + */ +#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) + +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U) +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U) +/*! RESET_RESUME_ROUGH_EN - Reset or Resume to Rough Phase Enable + * 0b0..Always works in tracking phase after the first time rough phase, to track transition. + * 0b1..Go back to rough stage whenever a bus reset or bus resume occurs. + */ +#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) + +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U) +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U) +/*! CLOCK_RECOVER_EN - Crystal-Less USB Enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) +/*! @} */ + +/*! @name CLK_RECOVER_IRC_EN - FIRC Oscillator Enable */ +/*! @{ */ + +#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U) +#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U) +/*! IRC_EN - Fast IRC enable + * 0b0..Disable + * 0b1..Enable + */ +#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) +/*! @} */ + +/*! @name CLK_RECOVER_INT_EN - Clock Recovery Combined Interrupt Enable */ +/*! @{ */ + +#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U) +#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U) +/*! OVF_ERROR_EN - Overflow error interrupt enable + * 0b0..The interrupt is masked + * 0b1..The interrupt is enabled + */ +#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK) +/*! @} */ + +/*! @name CLK_RECOVER_INT_STATUS - Clock Recovery Separated Interrupt Status */ +/*! @{ */ + +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U) +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U) +/*! OVF_ERROR - Overflow Error Interrupt Status Flag + * 0b0..Interrupt did not occur + * 0b1..Unmasked interrupt occurred + * 0b0..No effect + * 0b1..Clear the flag + */ +#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB0 base address */ +#define USB0_BASE (0x400A4000u) +/** Peripheral USB0 base pointer */ +#define USB0 ((USB_Type *)USB0_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { USB0_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { USB0 } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } +/* Backward compatibility */ +#define USBFS_IRQS USB_IRQS +#define USBFS_IRQHandler USB0_IRQHandler + + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UTICK Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer + * @{ + */ + +/** UTICK - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control, offset: 0x0 */ + __IO uint32_t STAT; /**< Status, offset: 0x4 */ + __IO uint32_t CFG; /**< Capture Configuration, offset: 0x8 */ + __O uint32_t CAPCLR; /**< Capture Clear, offset: 0xC */ + __I uint32_t CAP[4]; /**< Capture, array offset: 0x10, array step: 0x4 */ +} UTICK_Type; + +/* ---------------------------------------------------------------------------- + -- UTICK Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Register_Masks UTICK Register Masks + * @{ + */ + +/*! @name CTRL - Control */ +/*! @{ */ + +#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) +#define UTICK_CTRL_DELAYVAL_SHIFT (0U) +/*! DELAYVAL - Tick Interval + * 0b0000000000000000000000000000000.. + * *..Clock cycles as defined in the description + */ +#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) + +#define UTICK_CTRL_REPEAT_MASK (0x80000000U) +#define UTICK_CTRL_REPEAT_SHIFT (31U) +/*! REPEAT - Repeat Delay + * 0b0..One-time delay + * 0b1..Delay repeats continuously + */ +#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) +/*! @} */ + +/*! @name STAT - Status */ +/*! @{ */ + +#define UTICK_STAT_INTR_MASK (0x1U) +#define UTICK_STAT_INTR_SHIFT (0U) +/*! INTR - Interrupt Flag + * 0b0..Not pending + * 0b1..Pending + */ +#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) + +#define UTICK_STAT_ACTIVE_MASK (0x2U) +#define UTICK_STAT_ACTIVE_SHIFT (1U) +/*! ACTIVE - Timer Active Flag + * 0b0..Inactive (stopped) + * 0b1..Active + */ +#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) +/*! @} */ + +/*! @name CFG - Capture Configuration */ +/*! @{ */ + +#define UTICK_CFG_CAPEN0_MASK (0x1U) +#define UTICK_CFG_CAPEN0_SHIFT (0U) +/*! CAPEN0 - Enable Capture 0 + * 0b0..Disable + * 0b1..Enable + */ +#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) + +#define UTICK_CFG_CAPEN1_MASK (0x2U) +#define UTICK_CFG_CAPEN1_SHIFT (1U) +/*! CAPEN1 - Enable Capture 1 + * 0b0..Disable + * 0b1..Enable + */ +#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) + +#define UTICK_CFG_CAPEN2_MASK (0x4U) +#define UTICK_CFG_CAPEN2_SHIFT (2U) +/*! CAPEN2 - Enable Capture 2 + * 0b0..Disable + * 0b1..Enable + */ +#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) + +#define UTICK_CFG_CAPEN3_MASK (0x8U) +#define UTICK_CFG_CAPEN3_SHIFT (3U) +/*! CAPEN3 - Enable Capture 3 + * 0b0..Disable + * 0b1..Enable + */ +#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) + +#define UTICK_CFG_CAPPOL0_MASK (0x100U) +#define UTICK_CFG_CAPPOL0_SHIFT (8U) +/*! CAPPOL0 - Capture Polarity 0 + * 0b0..Positive + * 0b1..Negative + */ +#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) + +#define UTICK_CFG_CAPPOL1_MASK (0x200U) +#define UTICK_CFG_CAPPOL1_SHIFT (9U) +/*! CAPPOL1 - Capture-Polarity 1 + * 0b0..Positive + * 0b1..Negative + */ +#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) + +#define UTICK_CFG_CAPPOL2_MASK (0x400U) +#define UTICK_CFG_CAPPOL2_SHIFT (10U) +/*! CAPPOL2 - Capture Polarity 2 + * 0b0..Positive + * 0b1..Negative + */ +#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) + +#define UTICK_CFG_CAPPOL3_MASK (0x800U) +#define UTICK_CFG_CAPPOL3_SHIFT (11U) +/*! CAPPOL3 - Capture Polarity 3 + * 0b0..Positive + * 0b1..Negative + */ +#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) +/*! @} */ + +/*! @name CAPCLR - Capture Clear */ +/*! @{ */ + +#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) +#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) +/*! CAPCLR0 - Clear Capture 0 + * 0b0..Does nothing + * 0b1..Clears the CAP0 register value + */ +#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) + +#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) +#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) +/*! CAPCLR1 - Clear Capture 1 + * 0b0..Does nothing + * 0b1..Clears the CAP1 register value + */ +#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) + +#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) +#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) +/*! CAPCLR2 - Clear Capture 2 + * 0b0..Does nothing + * 0b1..Clears the CAP2 register value + */ +#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) + +#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) +#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) +/*! CAPCLR3 - Clear Capture 3 + * 0b0..Does nothing + * 0b1..Clears the CAP3 register value + */ +#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) +/*! @} */ + +/*! @name CAP - Capture */ +/*! @{ */ + +#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) +#define UTICK_CAP_CAP_VALUE_SHIFT (0U) +/*! CAP_VALUE - Captured Value for the Related Capture Event */ +#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) + +#define UTICK_CAP_VALID_MASK (0x80000000U) +#define UTICK_CAP_VALID_SHIFT (31U) +/*! VALID - Captured Value Valid Flag + * 0b0..Valid value not captured + * 0b1..Valid value captured + */ +#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) +/*! @} */ + +/* The count of UTICK_CAP */ +#define UTICK_CAP_COUNT (4U) + + +/*! + * @} + */ /* end of group UTICK_Register_Masks */ + + +/* UTICK - Peripheral instance base addresses */ +/** Peripheral UTICK0 base address */ +#define UTICK0_BASE (0x4000B000u) +/** Peripheral UTICK0 base pointer */ +#define UTICK0 ((UTICK_Type *)UTICK0_BASE) +/** Array initializer of UTICK peripheral base addresses */ +#define UTICK_BASE_ADDRS { UTICK0_BASE } +/** Array initializer of UTICK peripheral base pointers */ +#define UTICK_BASE_PTRS { UTICK0 } +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/*! + * @} + */ /* end of group UTICK_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- VBAT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VBAT_Peripheral_Access_Layer VBAT Peripheral Access Layer + * @{ + */ + +/** VBAT - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + uint8_t RESERVED_0[508]; + __IO uint32_t FROCTLA; /**< FRO16K Control A, offset: 0x200 */ + uint8_t RESERVED_1[20]; + __IO uint32_t FROLCKA; /**< FRO16K Lock A, offset: 0x218 */ + uint8_t RESERVED_2[4]; + __IO uint32_t FROCLKE; /**< FRO16K Clock Enable, offset: 0x220 */ + uint8_t RESERVED_3[1244]; + struct { /* offset: 0x700, array step: 0x8 */ + __IO uint32_t WAKEUPA; /**< Wakeup 0 Register A, array offset: 0x700, array step: 0x8 */ + uint8_t RESERVED_0[4]; + } WAKEUP[2]; + uint8_t RESERVED_4[232]; + __IO uint32_t WAKLCKA; /**< Wakeup Lock A, offset: 0x7F8 */ +} VBAT_Type; + +/* ---------------------------------------------------------------------------- + -- VBAT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VBAT_Register_Masks VBAT Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define VBAT_VERID_FEATURE_MASK (0xFFFFU) +#define VBAT_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number */ +#define VBAT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_FEATURE_SHIFT)) & VBAT_VERID_FEATURE_MASK) + +#define VBAT_VERID_MINOR_MASK (0xFF0000U) +#define VBAT_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define VBAT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_MINOR_SHIFT)) & VBAT_VERID_MINOR_MASK) + +#define VBAT_VERID_MAJOR_MASK (0xFF000000U) +#define VBAT_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define VBAT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << VBAT_VERID_MAJOR_SHIFT)) & VBAT_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name FROCTLA - FRO16K Control A */ +/*! @{ */ + +#define VBAT_FROCTLA_FRO_EN_MASK (0x1U) +#define VBAT_FROCTLA_FRO_EN_SHIFT (0U) +/*! FRO_EN - FRO16K Enable + * 0b0..Disable + * 0b1..Enable + */ +#define VBAT_FROCTLA_FRO_EN(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROCTLA_FRO_EN_SHIFT)) & VBAT_FROCTLA_FRO_EN_MASK) +/*! @} */ + +/*! @name FROLCKA - FRO16K Lock A */ +/*! @{ */ + +#define VBAT_FROLCKA_LOCK_MASK (0x1U) +#define VBAT_FROLCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Do not block + * 0b1..Block + */ +#define VBAT_FROLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROLCKA_LOCK_SHIFT)) & VBAT_FROLCKA_LOCK_MASK) +/*! @} */ + +/*! @name FROCLKE - FRO16K Clock Enable */ +/*! @{ */ + +#define VBAT_FROCLKE_CLKE_MASK (0x3U) +#define VBAT_FROCLKE_CLKE_SHIFT (0U) +/*! CLKE - Clock Enable */ +#define VBAT_FROCLKE_CLKE(x) (((uint32_t)(((uint32_t)(x)) << VBAT_FROCLKE_CLKE_SHIFT)) & VBAT_FROCLKE_CLKE_MASK) +/*! @} */ + +/*! @name WAKEUP_WAKEUPA - Wakeup 0 Register A */ +/*! @{ */ + +#define VBAT_WAKEUP_WAKEUPA_REG_MASK (0xFFFFFFFFU) +#define VBAT_WAKEUP_WAKEUPA_REG_SHIFT (0U) +/*! REG - Register */ +#define VBAT_WAKEUP_WAKEUPA_REG(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKEUP_WAKEUPA_REG_SHIFT)) & VBAT_WAKEUP_WAKEUPA_REG_MASK) +/*! @} */ + +/* The count of VBAT_WAKEUP_WAKEUPA */ +#define VBAT_WAKEUP_WAKEUPA_COUNT (2U) + +/*! @name WAKLCKA - Wakeup Lock A */ +/*! @{ */ + +#define VBAT_WAKLCKA_LOCK_MASK (0x1U) +#define VBAT_WAKLCKA_LOCK_SHIFT (0U) +/*! LOCK - Lock + * 0b0..Lock is disabled + * 0b1..Lock is enabled + */ +#define VBAT_WAKLCKA_LOCK(x) (((uint32_t)(((uint32_t)(x)) << VBAT_WAKLCKA_LOCK_SHIFT)) & VBAT_WAKLCKA_LOCK_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group VBAT_Register_Masks */ + + +/* VBAT - Peripheral instance base addresses */ +/** Peripheral VBAT0 base address */ +#define VBAT0_BASE (0x40093000u) +/** Peripheral VBAT0 base pointer */ +#define VBAT0 ((VBAT_Type *)VBAT0_BASE) +/** Array initializer of VBAT peripheral base addresses */ +#define VBAT_BASE_ADDRS { VBAT0_BASE } +/** Array initializer of VBAT peripheral base pointers */ +#define VBAT_BASE_PTRS { VBAT0 } + +/*! + * @} + */ /* end of group VBAT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WAKETIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WAKETIMER_Peripheral_Access_Layer WAKETIMER Peripheral Access Layer + * @{ + */ + +/** WAKETIMER - Register Layout Typedef */ +typedef struct { + __IO uint32_t WAKE_TIMER_CTRL; /**< Wake Timer Control, offset: 0x0 */ + uint8_t RESERVED_0[8]; + __IO uint32_t WAKE_TIMER_CNT; /**< Wake Timer Counter, offset: 0xC */ +} WAKETIMER_Type; + +/* ---------------------------------------------------------------------------- + -- WAKETIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WAKETIMER_Register_Masks WAKETIMER Register Masks + * @{ + */ + +/*! @name WAKE_TIMER_CTRL - Wake Timer Control */ +/*! @{ */ + +#define WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG_MASK (0x2U) +#define WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT (1U) +/*! WAKE_FLAG - Wake Timer Status Flag + * 0b0..Wake timer has not timed out. + * 0b1..Wake timer has timed out. + */ +#define WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG_SHIFT)) & WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG_MASK) + +#define WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK (0x4U) +#define WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT (2U) +/*! CLR_WAKE_TIMER - Clear Wake Timer + * 0b0..No effect. + * 0b1..Clears the wake timer counter and halts operation until a new count value is loaded. + */ +#define WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER(x) (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_SHIFT)) & WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK) + +#define WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK (0x10U) +#define WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT (4U) +/*! OSC_DIV_ENA - OSC Divide Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA(x) (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA_SHIFT)) & WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK) + +#define WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_MASK (0x20U) +#define WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_SHIFT (5U) +/*! INTR_EN - Enable Interrupt + * 0b0..Disabled + * 0b1..Enabled + */ +#define WAKETIMER_WAKE_TIMER_CTRL_INTR_EN(x) (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_SHIFT)) & WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_MASK) +/*! @} */ + +/*! @name WAKE_TIMER_CNT - Wake Timer Counter */ +/*! @{ */ + +#define WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT_MASK (0xFFFFFFFFU) +#define WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT_SHIFT (0U) +/*! WAKE_CNT - Wake Counter */ +#define WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT(x) (((uint32_t)(((uint32_t)(x)) << WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT_SHIFT)) & WAKETIMER_WAKE_TIMER_CNT_WAKE_CNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WAKETIMER_Register_Masks */ + + +/* WAKETIMER - Peripheral instance base addresses */ +/** Peripheral WAKETIMER0 base address */ +#define WAKETIMER0_BASE (0x400AE000u) +/** Peripheral WAKETIMER0 base pointer */ +#define WAKETIMER0 ((WAKETIMER_Type *)WAKETIMER0_BASE) +/** Array initializer of WAKETIMER peripheral base addresses */ +#define WAKETIMER_BASE_ADDRS { WAKETIMER0_BASE } +/** Array initializer of WAKETIMER peripheral base pointers */ +#define WAKETIMER_BASE_PTRS { WAKETIMER0 } +/** Interrupt vectors for the WAKETIMER peripheral type */ +#define WAKETIMER_IRQS { WAKETIMER0_IRQn } + +/*! + * @} + */ /* end of group WAKETIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WUU Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WUU_Peripheral_Access_Layer WUU Peripheral Access Layer + * @{ + */ + +/** WUU - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t PE1; /**< Pin Enable 1, offset: 0x8 */ + __IO uint32_t PE2; /**< Pin Enable 2, offset: 0xC */ + uint8_t RESERVED_0[8]; + __IO uint32_t ME; /**< Module Interrupt Enable, offset: 0x18 */ + __IO uint32_t DE; /**< Module DMA/Trigger Enable, offset: 0x1C */ + __IO uint32_t PF; /**< Pin Flag, offset: 0x20 */ + uint8_t RESERVED_1[12]; + __IO uint32_t FILT; /**< Pin Filter, offset: 0x30 */ + uint8_t RESERVED_2[4]; + __IO uint32_t PDC1; /**< Pin DMA/Trigger Configuration 1, offset: 0x38 */ + __IO uint32_t PDC2; /**< Pin DMA/Trigger Configuration 2, offset: 0x3C */ + uint8_t RESERVED_3[8]; + __IO uint32_t FDC; /**< Pin Filter DMA/Trigger Configuration, offset: 0x48 */ + uint8_t RESERVED_4[4]; + __IO uint32_t PMC; /**< Pin Mode Configuration, offset: 0x50 */ + uint8_t RESERVED_5[4]; + __IO uint32_t FMC; /**< Pin Filter Mode Configuration, offset: 0x58 */ +} WUU_Type; + +/* ---------------------------------------------------------------------------- + -- WUU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WUU_Register_Masks WUU Register Masks + * @{ + */ + +/*! @name VERID - Version ID */ +/*! @{ */ + +#define WUU_VERID_FEATURE_MASK (0xFFFFU) +#define WUU_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features implemented + * 0b0000000000000001..Support for DMA/Trigger generation from wake-up pins and filters enabled. Support for + * external pin/filter detection during all power modes enabled. + * *.. + */ +#define WUU_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_FEATURE_SHIFT)) & WUU_VERID_FEATURE_MASK) + +#define WUU_VERID_MINOR_MASK (0xFF0000U) +#define WUU_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number */ +#define WUU_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_MINOR_SHIFT)) & WUU_VERID_MINOR_MASK) + +#define WUU_VERID_MAJOR_MASK (0xFF000000U) +#define WUU_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number */ +#define WUU_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << WUU_VERID_MAJOR_SHIFT)) & WUU_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter */ +/*! @{ */ + +#define WUU_PARAM_FILTERS_MASK (0xFFU) +#define WUU_PARAM_FILTERS_SHIFT (0U) +/*! FILTERS - Filter Number */ +#define WUU_PARAM_FILTERS(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_FILTERS_SHIFT)) & WUU_PARAM_FILTERS_MASK) + +#define WUU_PARAM_DMAS_MASK (0xFF00U) +#define WUU_PARAM_DMAS_SHIFT (8U) +/*! DMAS - DMA Number */ +#define WUU_PARAM_DMAS(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_DMAS_SHIFT)) & WUU_PARAM_DMAS_MASK) + +#define WUU_PARAM_MODULES_MASK (0xFF0000U) +#define WUU_PARAM_MODULES_SHIFT (16U) +/*! MODULES - Module Number */ +#define WUU_PARAM_MODULES(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_MODULES_SHIFT)) & WUU_PARAM_MODULES_MASK) + +#define WUU_PARAM_PINS_MASK (0xFF000000U) +#define WUU_PARAM_PINS_SHIFT (24U) +/*! PINS - Pin Number */ +#define WUU_PARAM_PINS(x) (((uint32_t)(((uint32_t)(x)) << WUU_PARAM_PINS_SHIFT)) & WUU_PARAM_PINS_MASK) +/*! @} */ + +/*! @name PE1 - Pin Enable 1 */ +/*! @{ */ + +#define WUU_PE1_Reserved0_MASK (0x3U) +#define WUU_PE1_Reserved0_SHIFT (0U) +/*! Reserved0 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE1_Reserved0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_Reserved0_SHIFT)) & WUU_PE1_Reserved0_MASK) + +#define WUU_PE1_Reserved1_MASK (0xCU) +#define WUU_PE1_Reserved1_SHIFT (2U) +/*! Reserved1 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE1_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_Reserved1_SHIFT)) & WUU_PE1_Reserved1_MASK) + +#define WUU_PE1_WUPE2_MASK (0x30U) +#define WUU_PE1_WUPE2_SHIFT (4U) +/*! WUPE2 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE2_SHIFT)) & WUU_PE1_WUPE2_MASK) + +#define WUU_PE1_Reserved3_MASK (0xC0U) +#define WUU_PE1_Reserved3_SHIFT (6U) +/*! Reserved3 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE1_Reserved3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_Reserved3_SHIFT)) & WUU_PE1_Reserved3_MASK) + +#define WUU_PE1_Reserved4_MASK (0x300U) +#define WUU_PE1_Reserved4_SHIFT (8U) +/*! Reserved4 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE1_Reserved4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_Reserved4_SHIFT)) & WUU_PE1_Reserved4_MASK) + +#define WUU_PE1_Reserved5_MASK (0xC00U) +#define WUU_PE1_Reserved5_SHIFT (10U) +/*! Reserved5 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE1_Reserved5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_Reserved5_SHIFT)) & WUU_PE1_Reserved5_MASK) + +#define WUU_PE1_WUPE6_MASK (0x3000U) +#define WUU_PE1_WUPE6_SHIFT (12U) +/*! WUPE6 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE6_SHIFT)) & WUU_PE1_WUPE6_MASK) + +#define WUU_PE1_WUPE7_MASK (0xC000U) +#define WUU_PE1_WUPE7_SHIFT (14U) +/*! WUPE7 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE7_SHIFT)) & WUU_PE1_WUPE7_MASK) + +#define WUU_PE1_WUPE8_MASK (0x30000U) +#define WUU_PE1_WUPE8_SHIFT (16U) +/*! WUPE8 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE8_SHIFT)) & WUU_PE1_WUPE8_MASK) + +#define WUU_PE1_WUPE9_MASK (0xC0000U) +#define WUU_PE1_WUPE9_SHIFT (18U) +/*! WUPE9 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE9_SHIFT)) & WUU_PE1_WUPE9_MASK) + +#define WUU_PE1_WUPE10_MASK (0x300000U) +#define WUU_PE1_WUPE10_SHIFT (20U) +/*! WUPE10 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE10_SHIFT)) & WUU_PE1_WUPE10_MASK) + +#define WUU_PE1_WUPE11_MASK (0xC00000U) +#define WUU_PE1_WUPE11_SHIFT (22U) +/*! WUPE11 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE11_SHIFT)) & WUU_PE1_WUPE11_MASK) + +#define WUU_PE1_WUPE12_MASK (0x3000000U) +#define WUU_PE1_WUPE12_SHIFT (24U) +/*! WUPE12 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE1_WUPE12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_WUPE12_SHIFT)) & WUU_PE1_WUPE12_MASK) + +#define WUU_PE1_Reserved13_MASK (0xC000000U) +#define WUU_PE1_Reserved13_SHIFT (26U) +/*! Reserved13 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE1_Reserved13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_Reserved13_SHIFT)) & WUU_PE1_Reserved13_MASK) + +#define WUU_PE1_Reserved14_MASK (0x30000000U) +#define WUU_PE1_Reserved14_SHIFT (28U) +/*! Reserved14 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE1_Reserved14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_Reserved14_SHIFT)) & WUU_PE1_Reserved14_MASK) + +#define WUU_PE1_Reserved15_MASK (0xC0000000U) +#define WUU_PE1_Reserved15_SHIFT (30U) +/*! Reserved15 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE1_Reserved15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE1_Reserved15_SHIFT)) & WUU_PE1_Reserved15_MASK) +/*! @} */ + +/*! @name PE2 - Pin Enable 2 */ +/*! @{ */ + +#define WUU_PE2_WUPE16_MASK (0x3U) +#define WUU_PE2_WUPE16_SHIFT (0U) +/*! WUPE16 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE16_SHIFT)) & WUU_PE2_WUPE16_MASK) + +#define WUU_PE2_WUPE17_MASK (0xCU) +#define WUU_PE2_WUPE17_SHIFT (2U) +/*! WUPE17 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE17_SHIFT)) & WUU_PE2_WUPE17_MASK) + +#define WUU_PE2_WUPE18_MASK (0x30U) +#define WUU_PE2_WUPE18_SHIFT (4U) +/*! WUPE18 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE18_SHIFT)) & WUU_PE2_WUPE18_MASK) + +#define WUU_PE2_WUPE19_MASK (0xC0U) +#define WUU_PE2_WUPE19_SHIFT (6U) +/*! WUPE19 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE19_SHIFT)) & WUU_PE2_WUPE19_MASK) + +#define WUU_PE2_WUPE20_MASK (0x300U) +#define WUU_PE2_WUPE20_SHIFT (8U) +/*! WUPE20 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE20_SHIFT)) & WUU_PE2_WUPE20_MASK) + +#define WUU_PE2_Reserved21_MASK (0xC00U) +#define WUU_PE2_Reserved21_SHIFT (10U) +/*! Reserved21 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PE2_Reserved21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_Reserved21_SHIFT)) & WUU_PE2_Reserved21_MASK) + +#define WUU_PE2_WUPE22_MASK (0x3000U) +#define WUU_PE2_WUPE22_SHIFT (12U) +/*! WUPE22 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE22_SHIFT)) & WUU_PE2_WUPE22_MASK) + +#define WUU_PE2_WUPE23_MASK (0xC000U) +#define WUU_PE2_WUPE23_SHIFT (14U) +/*! WUPE23 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE23_SHIFT)) & WUU_PE2_WUPE23_MASK) + +#define WUU_PE2_WUPE24_MASK (0x30000U) +#define WUU_PE2_WUPE24_SHIFT (16U) +/*! WUPE24 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE24_SHIFT)) & WUU_PE2_WUPE24_MASK) + +#define WUU_PE2_WUPE25_MASK (0xC0000U) +#define WUU_PE2_WUPE25_SHIFT (18U) +/*! WUPE25 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE25_SHIFT)) & WUU_PE2_WUPE25_MASK) + +#define WUU_PE2_WUPE26_MASK (0x300000U) +#define WUU_PE2_WUPE26_SHIFT (20U) +/*! WUPE26 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE26_SHIFT)) & WUU_PE2_WUPE26_MASK) + +#define WUU_PE2_WUPE27_MASK (0xC00000U) +#define WUU_PE2_WUPE27_SHIFT (22U) +/*! WUPE27 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE27_SHIFT)) & WUU_PE2_WUPE27_MASK) + +#define WUU_PE2_WUPE28_MASK (0x3000000U) +#define WUU_PE2_WUPE28_SHIFT (24U) +/*! WUPE28 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE28_SHIFT)) & WUU_PE2_WUPE28_MASK) + +#define WUU_PE2_WUPE29_MASK (0xC000000U) +#define WUU_PE2_WUPE29_SHIFT (26U) +/*! WUPE29 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE29_SHIFT)) & WUU_PE2_WUPE29_MASK) + +#define WUU_PE2_WUPE30_MASK (0x30000000U) +#define WUU_PE2_WUPE30_SHIFT (28U) +/*! WUPE30 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE30_SHIFT)) & WUU_PE2_WUPE30_MASK) + +#define WUU_PE2_WUPE31_MASK (0xC0000000U) +#define WUU_PE2_WUPE31_SHIFT (30U) +/*! WUPE31 - Wake-up Pin Enable for WUU_Pn + * 0b00..Disable + * 0b01..Enable (detect on rising edge or high level) + * 0b10..Enable (detect on falling edge or low level) + * 0b11..Enable (detect on any edge) + */ +#define WUU_PE2_WUPE31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PE2_WUPE31_SHIFT)) & WUU_PE2_WUPE31_MASK) +/*! @} */ + +/*! @name ME - Module Interrupt Enable */ +/*! @{ */ + +#define WUU_ME_WUME0_MASK (0x1U) +#define WUU_ME_WUME0_SHIFT (0U) +/*! WUME0 - Module Interrupt Wake-up Enable for Module 0 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME0(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME0_SHIFT)) & WUU_ME_WUME0_MASK) + +#define WUU_ME_WUME2_MASK (0x4U) +#define WUU_ME_WUME2_SHIFT (2U) +/*! WUME2 - Module Interrupt Wake-up Enable for Module 2 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME2(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME2_SHIFT)) & WUU_ME_WUME2_MASK) + +#define WUU_ME_WUME6_MASK (0x40U) +#define WUU_ME_WUME6_SHIFT (6U) +/*! WUME6 - Module Interrupt Wake-up Enable for Module 6 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME6(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME6_SHIFT)) & WUU_ME_WUME6_MASK) + +#define WUU_ME_WUME8_MASK (0x100U) +#define WUU_ME_WUME8_SHIFT (8U) +/*! WUME8 - Module Interrupt Wake-up Enable for Module 8 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_ME_WUME8(x) (((uint32_t)(((uint32_t)(x)) << WUU_ME_WUME8_SHIFT)) & WUU_ME_WUME8_MASK) +/*! @} */ + +/*! @name DE - Module DMA/Trigger Enable */ +/*! @{ */ + +#define WUU_DE_WUDE4_MASK (0x10U) +#define WUU_DE_WUDE4_SHIFT (4U) +/*! WUDE4 - DMA/Trigger Wake-up Enable for Module 4 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE4(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE4_SHIFT)) & WUU_DE_WUDE4_MASK) + +#define WUU_DE_WUDE6_MASK (0x40U) +#define WUU_DE_WUDE6_SHIFT (6U) +/*! WUDE6 - DMA/Trigger Wake-up Enable for Module 6 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE6(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE6_SHIFT)) & WUU_DE_WUDE6_MASK) + +#define WUU_DE_WUDE8_MASK (0x100U) +#define WUU_DE_WUDE8_SHIFT (8U) +/*! WUDE8 - DMA/Trigger Wake-up Enable for Module 8 + * 0b0..Disable + * 0b1..Enable + */ +#define WUU_DE_WUDE8(x) (((uint32_t)(((uint32_t)(x)) << WUU_DE_WUDE8_SHIFT)) & WUU_DE_WUDE8_MASK) +/*! @} */ + +/*! @name PF - Pin Flag */ +/*! @{ */ + +#define WUU_PF_Reserved0_MASK (0x1U) +#define WUU_PF_Reserved0_SHIFT (0U) +/*! Reserved0 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved0_SHIFT)) & WUU_PF_Reserved0_MASK) + +#define WUU_PF_Reserved1_MASK (0x2U) +#define WUU_PF_Reserved1_SHIFT (1U) +/*! Reserved1 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved1_SHIFT)) & WUU_PF_Reserved1_MASK) + +#define WUU_PF_WUF2_MASK (0x4U) +#define WUU_PF_WUF2_SHIFT (2U) +/*! WUF2 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF2_SHIFT)) & WUU_PF_WUF2_MASK) + +#define WUU_PF_Reserved3_MASK (0x8U) +#define WUU_PF_Reserved3_SHIFT (3U) +/*! Reserved3 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved3_SHIFT)) & WUU_PF_Reserved3_MASK) + +#define WUU_PF_Reserved4_MASK (0x10U) +#define WUU_PF_Reserved4_SHIFT (4U) +/*! Reserved4 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved4_SHIFT)) & WUU_PF_Reserved4_MASK) + +#define WUU_PF_Reserved5_MASK (0x20U) +#define WUU_PF_Reserved5_SHIFT (5U) +/*! Reserved5 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved5_SHIFT)) & WUU_PF_Reserved5_MASK) + +#define WUU_PF_WUF6_MASK (0x40U) +#define WUU_PF_WUF6_SHIFT (6U) +/*! WUF6 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF6_SHIFT)) & WUU_PF_WUF6_MASK) + +#define WUU_PF_WUF7_MASK (0x80U) +#define WUU_PF_WUF7_SHIFT (7U) +/*! WUF7 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF7_SHIFT)) & WUU_PF_WUF7_MASK) + +#define WUU_PF_WUF8_MASK (0x100U) +#define WUU_PF_WUF8_SHIFT (8U) +/*! WUF8 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF8_SHIFT)) & WUU_PF_WUF8_MASK) + +#define WUU_PF_WUF9_MASK (0x200U) +#define WUU_PF_WUF9_SHIFT (9U) +/*! WUF9 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF9_SHIFT)) & WUU_PF_WUF9_MASK) + +#define WUU_PF_WUF10_MASK (0x400U) +#define WUU_PF_WUF10_SHIFT (10U) +/*! WUF10 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF10_SHIFT)) & WUU_PF_WUF10_MASK) + +#define WUU_PF_WUF11_MASK (0x800U) +#define WUU_PF_WUF11_SHIFT (11U) +/*! WUF11 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF11_SHIFT)) & WUU_PF_WUF11_MASK) + +#define WUU_PF_WUF12_MASK (0x1000U) +#define WUU_PF_WUF12_SHIFT (12U) +/*! WUF12 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF12_SHIFT)) & WUU_PF_WUF12_MASK) + +#define WUU_PF_Reserved13_MASK (0x2000U) +#define WUU_PF_Reserved13_SHIFT (13U) +/*! Reserved13 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved13_SHIFT)) & WUU_PF_Reserved13_MASK) + +#define WUU_PF_Reserved14_MASK (0x4000U) +#define WUU_PF_Reserved14_SHIFT (14U) +/*! Reserved14 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved14_SHIFT)) & WUU_PF_Reserved14_MASK) + +#define WUU_PF_Reserved15_MASK (0x8000U) +#define WUU_PF_Reserved15_SHIFT (15U) +/*! Reserved15 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved15_SHIFT)) & WUU_PF_Reserved15_MASK) + +#define WUU_PF_WUF16_MASK (0x10000U) +#define WUU_PF_WUF16_SHIFT (16U) +/*! WUF16 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF16_SHIFT)) & WUU_PF_WUF16_MASK) + +#define WUU_PF_WUF17_MASK (0x20000U) +#define WUU_PF_WUF17_SHIFT (17U) +/*! WUF17 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF17_SHIFT)) & WUU_PF_WUF17_MASK) + +#define WUU_PF_WUF18_MASK (0x40000U) +#define WUU_PF_WUF18_SHIFT (18U) +/*! WUF18 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF18_SHIFT)) & WUU_PF_WUF18_MASK) + +#define WUU_PF_WUF19_MASK (0x80000U) +#define WUU_PF_WUF19_SHIFT (19U) +/*! WUF19 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF19_SHIFT)) & WUU_PF_WUF19_MASK) + +#define WUU_PF_WUF20_MASK (0x100000U) +#define WUU_PF_WUF20_SHIFT (20U) +/*! WUF20 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF20_SHIFT)) & WUU_PF_WUF20_MASK) + +#define WUU_PF_Reserved21_MASK (0x200000U) +#define WUU_PF_Reserved21_SHIFT (21U) +/*! Reserved21 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PF_Reserved21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_Reserved21_SHIFT)) & WUU_PF_Reserved21_MASK) + +#define WUU_PF_WUF22_MASK (0x400000U) +#define WUU_PF_WUF22_SHIFT (22U) +/*! WUF22 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF22_SHIFT)) & WUU_PF_WUF22_MASK) + +#define WUU_PF_WUF23_MASK (0x800000U) +#define WUU_PF_WUF23_SHIFT (23U) +/*! WUF23 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF23_SHIFT)) & WUU_PF_WUF23_MASK) + +#define WUU_PF_WUF24_MASK (0x1000000U) +#define WUU_PF_WUF24_SHIFT (24U) +/*! WUF24 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF24_SHIFT)) & WUU_PF_WUF24_MASK) + +#define WUU_PF_WUF25_MASK (0x2000000U) +#define WUU_PF_WUF25_SHIFT (25U) +/*! WUF25 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF25_SHIFT)) & WUU_PF_WUF25_MASK) + +#define WUU_PF_WUF26_MASK (0x4000000U) +#define WUU_PF_WUF26_SHIFT (26U) +/*! WUF26 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF26_SHIFT)) & WUU_PF_WUF26_MASK) + +#define WUU_PF_WUF27_MASK (0x8000000U) +#define WUU_PF_WUF27_SHIFT (27U) +/*! WUF27 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF27_SHIFT)) & WUU_PF_WUF27_MASK) + +#define WUU_PF_WUF28_MASK (0x10000000U) +#define WUU_PF_WUF28_SHIFT (28U) +/*! WUF28 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF28_SHIFT)) & WUU_PF_WUF28_MASK) + +#define WUU_PF_WUF29_MASK (0x20000000U) +#define WUU_PF_WUF29_SHIFT (29U) +/*! WUF29 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF29_SHIFT)) & WUU_PF_WUF29_MASK) + +#define WUU_PF_WUF30_MASK (0x40000000U) +#define WUU_PF_WUF30_SHIFT (30U) +/*! WUF30 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF30_SHIFT)) & WUU_PF_WUF30_MASK) + +#define WUU_PF_WUF31_MASK (0x80000000U) +#define WUU_PF_WUF31_SHIFT (31U) +/*! WUF31 - Wake-up Flag for WUU_Pn + * 0b0..No + * 0b1..Yes + */ +#define WUU_PF_WUF31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PF_WUF31_SHIFT)) & WUU_PF_WUF31_MASK) +/*! @} */ + +/*! @name FILT - Pin Filter */ +/*! @{ */ + +#define WUU_FILT_FILTSEL1_MASK (0x1FU) +#define WUU_FILT_FILTSEL1_SHIFT (0U) +/*! FILTSEL1 - Filter 1 Pin Select */ +#define WUU_FILT_FILTSEL1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL1_SHIFT)) & WUU_FILT_FILTSEL1_MASK) + +#define WUU_FILT_FILTE1_MASK (0x60U) +#define WUU_FILT_FILTE1_SHIFT (5U) +/*! FILTE1 - Filter 1 Enable + * 0b00..Disable + * 0b01..Enable (Detect on rising edge or high level) + * 0b10..Enable (Detect on falling edge or low level) + * 0b11..Enable (Detect on any edge) + */ +#define WUU_FILT_FILTE1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE1_SHIFT)) & WUU_FILT_FILTE1_MASK) + +#define WUU_FILT_FILTF1_MASK (0x80U) +#define WUU_FILT_FILTF1_SHIFT (7U) +/*! FILTF1 - Filter 1 Flag + * 0b0..No + * 0b1..Yes + */ +#define WUU_FILT_FILTF1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF1_SHIFT)) & WUU_FILT_FILTF1_MASK) + +#define WUU_FILT_FILTSEL2_MASK (0x1F00U) +#define WUU_FILT_FILTSEL2_SHIFT (8U) +/*! FILTSEL2 - Filter 2 Pin Select */ +#define WUU_FILT_FILTSEL2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTSEL2_SHIFT)) & WUU_FILT_FILTSEL2_MASK) + +#define WUU_FILT_FILTE2_MASK (0x6000U) +#define WUU_FILT_FILTE2_SHIFT (13U) +/*! FILTE2 - Filter 2 Enable + * 0b00..Disable + * 0b01..Enable (Detect on rising edge or high level) + * 0b10..Enable (Detect on falling edge or low level) + * 0b11..Enable (Detect on any edge) + */ +#define WUU_FILT_FILTE2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTE2_SHIFT)) & WUU_FILT_FILTE2_MASK) + +#define WUU_FILT_FILTF2_MASK (0x8000U) +#define WUU_FILT_FILTF2_SHIFT (15U) +/*! FILTF2 - Filter 2 Flag + * 0b0..No + * 0b1..Yes + */ +#define WUU_FILT_FILTF2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FILT_FILTF2_SHIFT)) & WUU_FILT_FILTF2_MASK) +/*! @} */ + +/*! @name PDC1 - Pin DMA/Trigger Configuration 1 */ +/*! @{ */ + +#define WUU_PDC1_Reserved0_MASK (0x3U) +#define WUU_PDC1_Reserved0_SHIFT (0U) +/*! Reserved0 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC1_Reserved0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_Reserved0_SHIFT)) & WUU_PDC1_Reserved0_MASK) + +#define WUU_PDC1_Reserved1_MASK (0xCU) +#define WUU_PDC1_Reserved1_SHIFT (2U) +/*! Reserved1 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC1_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_Reserved1_SHIFT)) & WUU_PDC1_Reserved1_MASK) + +#define WUU_PDC1_WUPDC2_MASK (0x30U) +#define WUU_PDC1_WUPDC2_SHIFT (4U) +/*! WUPDC2 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC2_SHIFT)) & WUU_PDC1_WUPDC2_MASK) + +#define WUU_PDC1_Reserved3_MASK (0xC0U) +#define WUU_PDC1_Reserved3_SHIFT (6U) +/*! Reserved3 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC1_Reserved3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_Reserved3_SHIFT)) & WUU_PDC1_Reserved3_MASK) + +#define WUU_PDC1_Reserved4_MASK (0x300U) +#define WUU_PDC1_Reserved4_SHIFT (8U) +/*! Reserved4 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC1_Reserved4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_Reserved4_SHIFT)) & WUU_PDC1_Reserved4_MASK) + +#define WUU_PDC1_Reserved5_MASK (0xC00U) +#define WUU_PDC1_Reserved5_SHIFT (10U) +/*! Reserved5 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC1_Reserved5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_Reserved5_SHIFT)) & WUU_PDC1_Reserved5_MASK) + +#define WUU_PDC1_WUPDC6_MASK (0x3000U) +#define WUU_PDC1_WUPDC6_SHIFT (12U) +/*! WUPDC6 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC6_SHIFT)) & WUU_PDC1_WUPDC6_MASK) + +#define WUU_PDC1_WUPDC7_MASK (0xC000U) +#define WUU_PDC1_WUPDC7_SHIFT (14U) +/*! WUPDC7 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC7_SHIFT)) & WUU_PDC1_WUPDC7_MASK) + +#define WUU_PDC1_WUPDC8_MASK (0x30000U) +#define WUU_PDC1_WUPDC8_SHIFT (16U) +/*! WUPDC8 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC8_SHIFT)) & WUU_PDC1_WUPDC8_MASK) + +#define WUU_PDC1_WUPDC9_MASK (0xC0000U) +#define WUU_PDC1_WUPDC9_SHIFT (18U) +/*! WUPDC9 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC9_SHIFT)) & WUU_PDC1_WUPDC9_MASK) + +#define WUU_PDC1_WUPDC10_MASK (0x300000U) +#define WUU_PDC1_WUPDC10_SHIFT (20U) +/*! WUPDC10 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC10_SHIFT)) & WUU_PDC1_WUPDC10_MASK) + +#define WUU_PDC1_WUPDC11_MASK (0xC00000U) +#define WUU_PDC1_WUPDC11_SHIFT (22U) +/*! WUPDC11 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC11_SHIFT)) & WUU_PDC1_WUPDC11_MASK) + +#define WUU_PDC1_WUPDC12_MASK (0x3000000U) +#define WUU_PDC1_WUPDC12_SHIFT (24U) +/*! WUPDC12 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC1_WUPDC12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_WUPDC12_SHIFT)) & WUU_PDC1_WUPDC12_MASK) + +#define WUU_PDC1_Reserved13_MASK (0xC000000U) +#define WUU_PDC1_Reserved13_SHIFT (26U) +/*! Reserved13 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC1_Reserved13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_Reserved13_SHIFT)) & WUU_PDC1_Reserved13_MASK) + +#define WUU_PDC1_Reserved14_MASK (0x30000000U) +#define WUU_PDC1_Reserved14_SHIFT (28U) +/*! Reserved14 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC1_Reserved14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_Reserved14_SHIFT)) & WUU_PDC1_Reserved14_MASK) + +#define WUU_PDC1_Reserved15_MASK (0xC0000000U) +#define WUU_PDC1_Reserved15_SHIFT (30U) +/*! Reserved15 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC1_Reserved15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC1_Reserved15_SHIFT)) & WUU_PDC1_Reserved15_MASK) +/*! @} */ + +/*! @name PDC2 - Pin DMA/Trigger Configuration 2 */ +/*! @{ */ + +#define WUU_PDC2_WUPDC16_MASK (0x3U) +#define WUU_PDC2_WUPDC16_SHIFT (0U) +/*! WUPDC16 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC16_SHIFT)) & WUU_PDC2_WUPDC16_MASK) + +#define WUU_PDC2_WUPDC17_MASK (0xCU) +#define WUU_PDC2_WUPDC17_SHIFT (2U) +/*! WUPDC17 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC17_SHIFT)) & WUU_PDC2_WUPDC17_MASK) + +#define WUU_PDC2_WUPDC18_MASK (0x30U) +#define WUU_PDC2_WUPDC18_SHIFT (4U) +/*! WUPDC18 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC18_SHIFT)) & WUU_PDC2_WUPDC18_MASK) + +#define WUU_PDC2_WUPDC19_MASK (0xC0U) +#define WUU_PDC2_WUPDC19_SHIFT (6U) +/*! WUPDC19 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC19_SHIFT)) & WUU_PDC2_WUPDC19_MASK) + +#define WUU_PDC2_WUPDC20_MASK (0x300U) +#define WUU_PDC2_WUPDC20_SHIFT (8U) +/*! WUPDC20 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC20_SHIFT)) & WUU_PDC2_WUPDC20_MASK) + +#define WUU_PDC2_Reserved21_MASK (0xC00U) +#define WUU_PDC2_Reserved21_SHIFT (10U) +/*! Reserved21 - Reserved + * 0b00..Not supported + * 0b01..Not supported + * 0b10..Not supported + * 0b11..Not supported + */ +#define WUU_PDC2_Reserved21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_Reserved21_SHIFT)) & WUU_PDC2_Reserved21_MASK) + +#define WUU_PDC2_WUPDC22_MASK (0x3000U) +#define WUU_PDC2_WUPDC22_SHIFT (12U) +/*! WUPDC22 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC22_SHIFT)) & WUU_PDC2_WUPDC22_MASK) + +#define WUU_PDC2_WUPDC23_MASK (0xC000U) +#define WUU_PDC2_WUPDC23_SHIFT (14U) +/*! WUPDC23 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC23_SHIFT)) & WUU_PDC2_WUPDC23_MASK) + +#define WUU_PDC2_WUPDC24_MASK (0x30000U) +#define WUU_PDC2_WUPDC24_SHIFT (16U) +/*! WUPDC24 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC24_SHIFT)) & WUU_PDC2_WUPDC24_MASK) + +#define WUU_PDC2_WUPDC25_MASK (0xC0000U) +#define WUU_PDC2_WUPDC25_SHIFT (18U) +/*! WUPDC25 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC25_SHIFT)) & WUU_PDC2_WUPDC25_MASK) + +#define WUU_PDC2_WUPDC26_MASK (0x300000U) +#define WUU_PDC2_WUPDC26_SHIFT (20U) +/*! WUPDC26 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC26_SHIFT)) & WUU_PDC2_WUPDC26_MASK) + +#define WUU_PDC2_WUPDC27_MASK (0xC00000U) +#define WUU_PDC2_WUPDC27_SHIFT (22U) +/*! WUPDC27 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC27_SHIFT)) & WUU_PDC2_WUPDC27_MASK) + +#define WUU_PDC2_WUPDC28_MASK (0x3000000U) +#define WUU_PDC2_WUPDC28_SHIFT (24U) +/*! WUPDC28 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC28_SHIFT)) & WUU_PDC2_WUPDC28_MASK) + +#define WUU_PDC2_WUPDC29_MASK (0xC000000U) +#define WUU_PDC2_WUPDC29_SHIFT (26U) +/*! WUPDC29 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC29_SHIFT)) & WUU_PDC2_WUPDC29_MASK) + +#define WUU_PDC2_WUPDC30_MASK (0x30000000U) +#define WUU_PDC2_WUPDC30_SHIFT (28U) +/*! WUPDC30 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC30_SHIFT)) & WUU_PDC2_WUPDC30_MASK) + +#define WUU_PDC2_WUPDC31_MASK (0xC0000000U) +#define WUU_PDC2_WUPDC31_SHIFT (30U) +/*! WUPDC31 - Wake-up Pin Configuration for WUU_Pn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_PDC2_WUPDC31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PDC2_WUPDC31_SHIFT)) & WUU_PDC2_WUPDC31_MASK) +/*! @} */ + +/*! @name FDC - Pin Filter DMA/Trigger Configuration */ +/*! @{ */ + +#define WUU_FDC_FILTC1_MASK (0x3U) +#define WUU_FDC_FILTC1_SHIFT (0U) +/*! FILTC1 - Filter Configuration for FILTn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_FDC_FILTC1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC1_SHIFT)) & WUU_FDC_FILTC1_MASK) + +#define WUU_FDC_FILTC2_MASK (0xCU) +#define WUU_FDC_FILTC2_SHIFT (2U) +/*! FILTC2 - Filter Configuration for FILTn + * 0b00..Interrupt + * 0b01..DMA request + * 0b10..Trigger event + * 0b11..Reserved + */ +#define WUU_FDC_FILTC2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FDC_FILTC2_SHIFT)) & WUU_FDC_FILTC2_MASK) +/*! @} */ + +/*! @name PMC - Pin Mode Configuration */ +/*! @{ */ + +#define WUU_PMC_Reserved0_MASK (0x1U) +#define WUU_PMC_Reserved0_SHIFT (0U) +/*! Reserved0 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved0(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved0_SHIFT)) & WUU_PMC_Reserved0_MASK) + +#define WUU_PMC_Reserved1_MASK (0x2U) +#define WUU_PMC_Reserved1_SHIFT (1U) +/*! Reserved1 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved1_SHIFT)) & WUU_PMC_Reserved1_MASK) + +#define WUU_PMC_WUPMC2_MASK (0x4U) +#define WUU_PMC_WUPMC2_SHIFT (2U) +/*! WUPMC2 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC2(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC2_SHIFT)) & WUU_PMC_WUPMC2_MASK) + +#define WUU_PMC_Reserved3_MASK (0x8U) +#define WUU_PMC_Reserved3_SHIFT (3U) +/*! Reserved3 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved3(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved3_SHIFT)) & WUU_PMC_Reserved3_MASK) + +#define WUU_PMC_Reserved4_MASK (0x10U) +#define WUU_PMC_Reserved4_SHIFT (4U) +/*! Reserved4 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved4(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved4_SHIFT)) & WUU_PMC_Reserved4_MASK) + +#define WUU_PMC_Reserved5_MASK (0x20U) +#define WUU_PMC_Reserved5_SHIFT (5U) +/*! Reserved5 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved5(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved5_SHIFT)) & WUU_PMC_Reserved5_MASK) + +#define WUU_PMC_WUPMC6_MASK (0x40U) +#define WUU_PMC_WUPMC6_SHIFT (6U) +/*! WUPMC6 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC6(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC6_SHIFT)) & WUU_PMC_WUPMC6_MASK) + +#define WUU_PMC_WUPMC7_MASK (0x80U) +#define WUU_PMC_WUPMC7_SHIFT (7U) +/*! WUPMC7 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC7(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC7_SHIFT)) & WUU_PMC_WUPMC7_MASK) + +#define WUU_PMC_WUPMC8_MASK (0x100U) +#define WUU_PMC_WUPMC8_SHIFT (8U) +/*! WUPMC8 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC8(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC8_SHIFT)) & WUU_PMC_WUPMC8_MASK) + +#define WUU_PMC_WUPMC9_MASK (0x200U) +#define WUU_PMC_WUPMC9_SHIFT (9U) +/*! WUPMC9 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC9(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC9_SHIFT)) & WUU_PMC_WUPMC9_MASK) + +#define WUU_PMC_WUPMC10_MASK (0x400U) +#define WUU_PMC_WUPMC10_SHIFT (10U) +/*! WUPMC10 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC10(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC10_SHIFT)) & WUU_PMC_WUPMC10_MASK) + +#define WUU_PMC_WUPMC11_MASK (0x800U) +#define WUU_PMC_WUPMC11_SHIFT (11U) +/*! WUPMC11 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC11(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC11_SHIFT)) & WUU_PMC_WUPMC11_MASK) + +#define WUU_PMC_WUPMC12_MASK (0x1000U) +#define WUU_PMC_WUPMC12_SHIFT (12U) +/*! WUPMC12 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC12(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC12_SHIFT)) & WUU_PMC_WUPMC12_MASK) + +#define WUU_PMC_Reserved13_MASK (0x2000U) +#define WUU_PMC_Reserved13_SHIFT (13U) +/*! Reserved13 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved13(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved13_SHIFT)) & WUU_PMC_Reserved13_MASK) + +#define WUU_PMC_Reserved14_MASK (0x4000U) +#define WUU_PMC_Reserved14_SHIFT (14U) +/*! Reserved14 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved14(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved14_SHIFT)) & WUU_PMC_Reserved14_MASK) + +#define WUU_PMC_Reserved15_MASK (0x8000U) +#define WUU_PMC_Reserved15_SHIFT (15U) +/*! Reserved15 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved15(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved15_SHIFT)) & WUU_PMC_Reserved15_MASK) + +#define WUU_PMC_WUPMC16_MASK (0x10000U) +#define WUU_PMC_WUPMC16_SHIFT (16U) +/*! WUPMC16 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC16(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC16_SHIFT)) & WUU_PMC_WUPMC16_MASK) + +#define WUU_PMC_WUPMC17_MASK (0x20000U) +#define WUU_PMC_WUPMC17_SHIFT (17U) +/*! WUPMC17 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC17(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC17_SHIFT)) & WUU_PMC_WUPMC17_MASK) + +#define WUU_PMC_WUPMC18_MASK (0x40000U) +#define WUU_PMC_WUPMC18_SHIFT (18U) +/*! WUPMC18 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC18(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC18_SHIFT)) & WUU_PMC_WUPMC18_MASK) + +#define WUU_PMC_WUPMC19_MASK (0x80000U) +#define WUU_PMC_WUPMC19_SHIFT (19U) +/*! WUPMC19 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC19(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC19_SHIFT)) & WUU_PMC_WUPMC19_MASK) + +#define WUU_PMC_WUPMC20_MASK (0x100000U) +#define WUU_PMC_WUPMC20_SHIFT (20U) +/*! WUPMC20 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC20(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC20_SHIFT)) & WUU_PMC_WUPMC20_MASK) + +#define WUU_PMC_Reserved21_MASK (0x200000U) +#define WUU_PMC_Reserved21_SHIFT (21U) +/*! Reserved21 - Reserved + * 0b0..Not supported + * 0b1..Not supported + */ +#define WUU_PMC_Reserved21(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_Reserved21_SHIFT)) & WUU_PMC_Reserved21_MASK) + +#define WUU_PMC_WUPMC22_MASK (0x400000U) +#define WUU_PMC_WUPMC22_SHIFT (22U) +/*! WUPMC22 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC22(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC22_SHIFT)) & WUU_PMC_WUPMC22_MASK) + +#define WUU_PMC_WUPMC23_MASK (0x800000U) +#define WUU_PMC_WUPMC23_SHIFT (23U) +/*! WUPMC23 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC23(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC23_SHIFT)) & WUU_PMC_WUPMC23_MASK) + +#define WUU_PMC_WUPMC24_MASK (0x1000000U) +#define WUU_PMC_WUPMC24_SHIFT (24U) +/*! WUPMC24 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC24(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC24_SHIFT)) & WUU_PMC_WUPMC24_MASK) + +#define WUU_PMC_WUPMC25_MASK (0x2000000U) +#define WUU_PMC_WUPMC25_SHIFT (25U) +/*! WUPMC25 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC25(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC25_SHIFT)) & WUU_PMC_WUPMC25_MASK) + +#define WUU_PMC_WUPMC26_MASK (0x4000000U) +#define WUU_PMC_WUPMC26_SHIFT (26U) +/*! WUPMC26 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC26(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC26_SHIFT)) & WUU_PMC_WUPMC26_MASK) + +#define WUU_PMC_WUPMC27_MASK (0x8000000U) +#define WUU_PMC_WUPMC27_SHIFT (27U) +/*! WUPMC27 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC27(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC27_SHIFT)) & WUU_PMC_WUPMC27_MASK) + +#define WUU_PMC_WUPMC28_MASK (0x10000000U) +#define WUU_PMC_WUPMC28_SHIFT (28U) +/*! WUPMC28 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC28(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC28_SHIFT)) & WUU_PMC_WUPMC28_MASK) + +#define WUU_PMC_WUPMC29_MASK (0x20000000U) +#define WUU_PMC_WUPMC29_SHIFT (29U) +/*! WUPMC29 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC29(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC29_SHIFT)) & WUU_PMC_WUPMC29_MASK) + +#define WUU_PMC_WUPMC30_MASK (0x40000000U) +#define WUU_PMC_WUPMC30_SHIFT (30U) +/*! WUPMC30 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC30(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC30_SHIFT)) & WUU_PMC_WUPMC30_MASK) + +#define WUU_PMC_WUPMC31_MASK (0x80000000U) +#define WUU_PMC_WUPMC31_SHIFT (31U) +/*! WUPMC31 - Wake-up Pin Mode Configuration for WUU_Pn + * 0b0..Active only during a low-leakage mode. You can modify the corresponding fields within Pin Enable (PEn) or + * Pin DMA/Trigger Configuration (PDCn). + * 0b1..Active during all power modes. Do not modify the corresponding fields within Pin Enable (PEn) or Pin DMA/Trigger Configuration (PDCn). + */ +#define WUU_PMC_WUPMC31(x) (((uint32_t)(((uint32_t)(x)) << WUU_PMC_WUPMC31_SHIFT)) & WUU_PMC_WUPMC31_MASK) +/*! @} */ + +/*! @name FMC - Pin Filter Mode Configuration */ +/*! @{ */ + +#define WUU_FMC_FILTM1_MASK (0x1U) +#define WUU_FMC_FILTM1_SHIFT (0U) +/*! FILTM1 - Filter Mode for FILTn + * 0b0..Active only during Power Down/Deep Power Down mode + * 0b1..Active during all power modes + */ +#define WUU_FMC_FILTM1(x) (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM1_SHIFT)) & WUU_FMC_FILTM1_MASK) + +#define WUU_FMC_FILTM2_MASK (0x2U) +#define WUU_FMC_FILTM2_SHIFT (1U) +/*! FILTM2 - Filter Mode for FILTn + * 0b0..Active only during Power Down/Deep Power Down mode + * 0b1..Active during all power modes + */ +#define WUU_FMC_FILTM2(x) (((uint32_t)(((uint32_t)(x)) << WUU_FMC_FILTM2_SHIFT)) & WUU_FMC_FILTM2_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WUU_Register_Masks */ + + +/* WUU - Peripheral instance base addresses */ +/** Peripheral WUU0 base address */ +#define WUU0_BASE (0x40092000u) +/** Peripheral WUU0 base pointer */ +#define WUU0 ((WUU_Type *)WUU0_BASE) +/** Array initializer of WUU peripheral base addresses */ +#define WUU_BASE_ADDRS { WUU0_BASE } +/** Array initializer of WUU peripheral base pointers */ +#define WUU_BASE_PTRS { WUU0 } + +/*! + * @} + */ /* end of group WUU_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WWDT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer + * @{ + */ + +/** WWDT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MOD; /**< Mode, offset: 0x0 */ + __IO uint32_t TC; /**< Timer Constant, offset: 0x4 */ + __O uint32_t FEED; /**< Feed Sequence, offset: 0x8 */ + __I uint32_t TV; /**< Timer Value, offset: 0xC */ + uint8_t RESERVED_0[4]; + __IO uint32_t WARNINT; /**< Warning Interrupt Compare Value, offset: 0x14 */ + __IO uint32_t WINDOW; /**< Window Compare Value, offset: 0x18 */ +} WWDT_Type; + +/* ---------------------------------------------------------------------------- + -- WWDT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Register_Masks WWDT Register Masks + * @{ + */ + +/*! @name MOD - Mode */ +/*! @{ */ + +#define WWDT_MOD_WDEN_MASK (0x1U) +#define WWDT_MOD_WDEN_SHIFT (0U) +/*! WDEN - Watchdog Enable + * 0b0..Timer stopped + * 0b1..Timer running + */ +#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) + +#define WWDT_MOD_WDRESET_MASK (0x2U) +#define WWDT_MOD_WDRESET_SHIFT (1U) +/*! WDRESET - Watchdog Reset Enable + * 0b0..Interrupt + * 0b1..Reset + */ +#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) + +#define WWDT_MOD_WDTOF_MASK (0x4U) +#define WWDT_MOD_WDTOF_SHIFT (2U) +/*! WDTOF - Watchdog Timeout Flag + * 0b0..Watchdog event has not occurred. + * 0b1..Watchdog event has occurred (causes a chip reset if WDRESET = 1). + */ +#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) + +#define WWDT_MOD_WDINT_MASK (0x8U) +#define WWDT_MOD_WDINT_SHIFT (3U) +/*! WDINT - Warning Interrupt Flag + * 0b0..No flag + * 0b1..Flag + */ +#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) + +#define WWDT_MOD_WDPROTECT_MASK (0x10U) +#define WWDT_MOD_WDPROTECT_SHIFT (4U) +/*! WDPROTECT - Watchdog Update Mode + * 0b0..Flexible + * 0b1..Threshold + */ +#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) + +#define WWDT_MOD_LOCK_MASK (0x20U) +#define WWDT_MOD_LOCK_SHIFT (5U) +/*! LOCK - Lock + * 0b0..No Lock + * 0b1..Lock + */ +#define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK) + +#define WWDT_MOD_DEBUG_EN_MASK (0x40U) +#define WWDT_MOD_DEBUG_EN_SHIFT (6U) +/*! DEBUG_EN - Debug Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define WWDT_MOD_DEBUG_EN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_DEBUG_EN_SHIFT)) & WWDT_MOD_DEBUG_EN_MASK) +/*! @} */ + +/*! @name TC - Timer Constant */ +/*! @{ */ + +#define WWDT_TC_COUNT_MASK (0xFFFFFFU) +#define WWDT_TC_COUNT_SHIFT (0U) +/*! COUNT - Watchdog Timeout Value */ +#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) +/*! @} */ + +/*! @name FEED - Feed Sequence */ +/*! @{ */ + +#define WWDT_FEED_FEED_MASK (0xFFU) +#define WWDT_FEED_FEED_SHIFT (0U) +/*! FEED - Feed Value */ +#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) +/*! @} */ + +/*! @name TV - Timer Value */ +/*! @{ */ + +#define WWDT_TV_COUNT_MASK (0xFFFFFFU) +#define WWDT_TV_COUNT_SHIFT (0U) +/*! COUNT - Counter Timer Value */ +#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) +/*! @} */ + +/*! @name WARNINT - Warning Interrupt Compare Value */ +/*! @{ */ + +#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) +#define WWDT_WARNINT_WARNINT_SHIFT (0U) +/*! WARNINT - Watchdog Warning Interrupt Compare Value */ +#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) +/*! @} */ + +/*! @name WINDOW - Window Compare Value */ +/*! @{ */ + +#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) +#define WWDT_WINDOW_WINDOW_SHIFT (0U) +/*! WINDOW - Watchdog Window Value */ +#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WWDT_Register_Masks */ + + +/* WWDT - Peripheral instance base addresses */ +/** Peripheral WWDT0 base address */ +#define WWDT0_BASE (0x4000C000u) +/** Peripheral WWDT0 base pointer */ +#define WWDT0 ((WWDT_Type *)WWDT0_BASE) +/** Array initializer of WWDT peripheral base addresses */ +#define WWDT_BASE_ADDRS { WWDT0_BASE } +/** Array initializer of WWDT peripheral base pointers */ +#define WWDT_BASE_PTRS { WWDT0 } + +/*! + * @} + */ /* end of group WWDT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/** High Speed SPI (Flexcomm 8) interrupt name */ +#define LSPI_HS_IRQn FLEXCOMM8_IRQn + + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* MCXA156_H_ */ + diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/MCXA156_features.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/MCXA156_features.h new file mode 100644 index 00000000000..b362ed44e65 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/MCXA156_features.h @@ -0,0 +1,793 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2022-03-29 +** Build: b240411 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-03-29) +** Initial version based on v0.1UM +** +** ################################################################### +*/ + +#ifndef _MCXA156_FEATURES_H_ +#define _MCXA156_FEATURES_H_ + +/* SOC module features */ + +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (2) +/* @brief CDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CDOG_COUNT (1) +/* @brief CMC availability on the SoC. */ +#define FSL_FEATURE_SOC_CMC_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (1) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (1) +/* @brief EQDC availability on the SoC. */ +#define FSL_FEATURE_SOC_EQDC_COUNT (2) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (1) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FREQME availability on the SoC. */ +#define FSL_FEATURE_SOC_FREQME_COUNT (1) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (5) +/* @brief SPC availability on the SoC. */ +#define FSL_FEATURE_SOC_SPC_COUNT (1) +/* @brief I3C availability on the SoC. */ +#define FSL_FEATURE_SOC_I3C_COUNT (1) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (2) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (2) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (1) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (4) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (2) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (1) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (5) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (1) +/* @brief OSTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_OSTIMER_COUNT (1) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (5) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (2) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (1) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief WAKETIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_WAKETIMER_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) +/* @brief WUU availability on the SoC. */ +#define FSL_FEATURE_SOC_WUU_COUNT (1) + +/* LPADC module features */ + +/* @brief FIFO availability on the SoC. */ +#define FSL_FEATURE_LPADC_FIFO_COUNT (1) +/* @brief Has subsequent trigger priority (bitfield CFG[TPRICTRL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_SUBSEQUENT_PRIORITY (1) +/* @brief Has differential mode (bitfield CMDLn[DIFF]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0) +/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0) +/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1) +/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1) +/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1) +/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */ +#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1) +/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1) +/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1) +/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1) +/* @brief Has internal clock (bitfield CFG[ADCKEN]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0) +/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0) +/* @brief Has calibration (bitfield CFG[CALOFS]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) +/* @brief Has offset trim (register OFSTRIM). */ +#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief OFSTRIM availability on the SoC. */ +#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (1) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4) +/* @brief Has B side channels. */ +#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (0) +/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1) +/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1) +/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1) +/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */ +#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1) +/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1) +/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */ +#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1) +/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1) +/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1) +/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1) +/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */ +#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2) +/* @brief Has internal temperature sensor. */ +#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (738.0f) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (287.5f) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (10.06f) +/* @brief The buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U) + +/* AOI module features */ + +/* @brief Maximum value of input mux. */ +#define FSL_FEATURE_AOI_MODULE_INPUTS (4) +/* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ +#define FSL_FEATURE_AOI_EVENT_COUNT (4) + +/* FLEXCAN module features */ + +/* @brief Has more than 64 MBs. */ +#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0) +/* @brief Message buffer size */ +#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32) +/* @brief Has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) +/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1) +/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ +#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) +/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ +#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) +/* @brief Instance has extended bit timing register (register CBT). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) +/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) +/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) +/* @brief Remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1) +/* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1) +/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) +/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0) +/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0) +/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */ +#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0) +/* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1) +/* @brief CAN instance support Flexible Data rate (CAN FD) protocol. */ +#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(x) (1) +/* @brief Has memory error control (register MECR). */ +#define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (0) +/* @brief Has enhanced bit timing register (register EPRS, ENCBT, EDCBT and ETDC). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG (1) +/* @brief Has Pretended Networking mode support. */ +#define FSL_FEATURE_FLEXCAN_HAS_PN_MODE (1) +/* @brief Has Enhanced Rx FIFO. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO (1) +/* @brief Enhanced Rx FIFO size (Indicates how many CAN FD messages can be stored). */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE (12) +/* @brief The number of enhanced Rx FIFO filter element registers. */ +#define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32) +/* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */ +#define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1) + +/* CDOG module features */ + +/* @brief CDOG Has No Reset */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) + +/* CMC module features */ + +/* @brief Has SRAM_DIS register */ +#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (0) +/* @brief Has BSR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (0) +/* @brief Has RSTCNT register */ +#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (1) +/* @brief Has BLR register */ +#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (0) + +/* LPCMP module features */ + +/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1) +/* @brief Has IER RRF_IE bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1) +/* @brief Has CSR RRF bitfield. */ +#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1) +/* @brief Has Round Robin mode (related to existence of registers RRCR0). */ +#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1) +/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */ +#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) +/* @brief CTIMER Has register MSR */ +#define FSL_FEATURE_CTIMER_HAS_MSR (1) + +/* LPDAC module features */ + +/* @brief FIFO size. */ +#define FSL_FEATURE_LPDAC_FIFO_SIZE (16) +/* @brief Has OPAMP as buffer, speed control signal (bitfield GCR[BUF_SPD_CTRL]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL (1) +/* @brief Buffer Enable(bitfield GCR[BUF_EN]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN (1) +/* @brief RCLK cycles before data latch(bitfield GCR[LATCH_CYC]). */ +#define FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC (1) +/* @brief VREF source number. */ +#define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3) +/* @brief Has internal reference current options. */ +#define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1) + +/* EDMA module features */ + +/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL (8) +/* @brief If 8 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1) +/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ +#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) +/* @brief If 16 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) +/* @brief Has DMA_Error interrupt vector. */ +#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) +/* @brief If 64 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1) +/* @brief If channel clock controlled independently */ +#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (1) +/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */ +#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (8) +/* @brief If 128 bytes transfer supported. */ +#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1) +/* @brief Has no register bit fields MP_CSR[EBW]. */ +#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1) +/* @brief Has register CH_CSR. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1) +/* @brief If dma has common clock gate */ +#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0) +/* @brief Has channel mux */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1) +/* @brief If dma channel IRQ support parameter */ +#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0) +/* @brief Instance has channel mux */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0) +/* @brief Has register CH_SBR. */ +#define FSL_FEATURE_EDMA_HAS_SBR (1) +/* @brief NBYTES must be multiple of 8 when using scatter gather. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0) +/* @brief Has no register bit fields CH_SBR[ATTR]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1) +/* @brief Has register bit fields MP_CSR[GMRC]. */ +#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1) +/* @brief Has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0) +/* @brief Instance has register bit field CH_CSR[SWAP]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0) +/* @brief Has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0) +/* @brief Instance has register bit field CH_SBR[INSTR]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0) +/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE (0) +/* @brief Instance has register CH_MATTR. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0) +/* @brief Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0) +/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0) +/* @brief Has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1) +/* @brief Instance has register bit field TCD_CSR[BWC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1) +/* @brief Has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0) +/* @brief Instance has register bit fields TCD_CSR[TMC]. */ +#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0) +/* @brief Has no register bit fields CH_SBR[SEC]. */ +#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (1) + +/* FLEXIO module features */ + +/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ +#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) +/* @brief Has Pin Data Input Register (FLEXIO_PIN) */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) +/* @brief Has pin input output related registers */ +#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1) +/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1) +/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1) +/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ +#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1) +/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1) +/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ +#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1) +/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ +#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1) +/* @brief Reset value of the FLEXIO_VERID register */ +#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003) +/* @brief Reset value of the FLEXIO_PARAM register */ +#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4200404) +/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */ +#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3) + +/* PWM module features */ + +/* @brief If (e)FlexPWM has module A channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELA (1) +/* @brief If (e)FlexPWM has module B channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELB (1) +/* @brief If (e)FlexPWM has module X channels (outputs). */ +#define FSL_FEATURE_PWM_HAS_CHANNELX (1) +/* @brief If (e)FlexPWM has fractional feature. */ +#define FSL_FEATURE_PWM_HAS_FRACTIONAL (0) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) +/* @brief Number of submodules in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_SUBMODULE_COUNT (3) +/* @brief Number of fault channel in each (e)FlexPWM module. */ +#define FSL_FEATURE_PWM_FAULT_CH_COUNT (1) +/* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */ +#define FSL_FEATURE_PWM_HAS_NO_WAITEN (1) +/* @brief If (e)FlexPWM has phase delay feature. */ +#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1) +/* @brief If (e)FlexPWM has input filter capture feature. */ +#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1) +/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (0) +/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (0) +/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */ +#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1) + +/* FMU module features */ + +/* @brief Is the flash module msf1? */ +#define FSL_FEATURE_FSL_FEATURE_FLASH_IS_MSF1 (1) +/* @brief P-Flash block count. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) +/* @brief P-Flash block0 start address. */ +#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000U) +/* @brief P-Flash block0 size. */ +#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (0x100000U) +/* @brief P-Flash sector size. */ +#define FSL_FEATURE_FLASH_PFLASH_SECTOR_SIZE (0x2000U) +/* @brief P-Flash page size. */ +#define FSL_FEATURE_FLASH_PFLASH_PAGE_SIZE (128) +/* @brief P-Flash phrase size. */ +#define FSL_FEATURE_FLASH_PFLASH_PHRASE_SIZE (16) +/* @brief Has IFR memory. */ +#define FSL_FEATURE_FLASH_HAS_IFR (1) +/* @brief flash BLOCK0 IFR0 start address. */ +#define FSL_FEATURE_FLASH_IFR0_START_ADDRESS (0x01000000u) +/* @brief flash BLOCK0 IFR1 start address. */ +#define FSL_FEATURE_FLASH_IFR1_START_ADDRESS (0x02100000U) +/* @brief flash block IFR0 size. */ +#define FSL_FEATURE_FLASH_IFR0_SIZE (0x8000U) +/* @brief flash block IFR1 size. */ +#define FSL_FEATURE_FLASH_IFR1_SIZE (0x2000U) +/* @brief IFR sector size. */ +#define FSL_FEATURE_FLASH_IFR_SECTOR_SIZE (0x2000U) +/* @brief IFR page size. */ +#define FSL_FEATURE_FLASH_IFR_PAGE_SIZE (128) + +/* GLIKEY module features */ + +/* @brief GLIKEY has 8 step FSM configuration */ +#define FSL_FEATURE_GLIKEY_HAS_EIGHT_STEPS (1) + +/* GPIO module features */ + +/* @brief Has GPIO attribute checker register (GACR). */ +#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) +/* @brief Has GPIO version ID register (VERID). */ +#define FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has secure/non-secure access protection registers (LOCK, PCNS, PCNP, ICNS, ICNP). */ +#define FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL (0) +/* @brief Has GPIO port input disable register (PIDR). */ +#define FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL (1) +/* @brief Has GPIO interrupt/DMA request/trigger output selection. */ +#define FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT (0) + +/* I3C module features */ + +/* @brief Has TERM bitfile in MERRWARN register. */ +#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0) +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_I3C_HAS_NO_RESET (0) +/* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH (0) +/* @brief Register SCONFIG do not have IDRAND bitfield. */ +#define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1) +/* @brief Register SCONFIG has HDROK bitfield. */ +#define FSL_FEATURE_I3C_HAS_HDROK (1) +/* @brief SOC doesn't support slave IBI/MR/HJ. */ +#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0) +/* @brief Has SCL delay after START. */ +#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1) + +/* LPI2C module features */ + +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) + +/* LPSPI module features */ + +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (4) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has CCR1 (related to existence of registers CCR1). */ +#define FSL_FEATURE_LPSPI_HAS_CCR1 (1) +/* @brief Has no PCSCFG bit in CFGR1 register */ +#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0) +/* @brief Has no WIDTH bits in TCR register */ +#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0) + +/* LPTMR module features */ + +/* @brief Has shared interrupt handler with another LPTMR module. */ +#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) +/* @brief Whether LPTMR counter is 32 bits width. */ +#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1) +/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ +#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) +/* @brief Do not has prescaler clock source 0. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (1) +/* @brief Do not has prescaler clock source 1. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0) +/* @brief Do not has prescaler clock source 2. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (1) +/* @brief Do not has prescaler clock source 3. */ +#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0) + +/* LPUART module features */ + +/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ +#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) +/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) +/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_HAS_FIFO (1) +/* @brief Has 32-bit register MODIR */ +#define FSL_FEATURE_LPUART_HAS_MODIR (1) +/* @brief Hardware flow control (RTS, CTS) is supported. */ +#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) +/* @brief Infrared (modulation) is supported. */ +#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) +/* @brief 2 bits long stop bit is available. */ +#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) +/* @brief If 10-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) +/* @brief If 7-bit mode is supported. */ +#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) +/* @brief Baud rate fine adjustment is available. */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) +/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) +/* @brief Baud rate oversampling is available. */ +#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) +/* @brief Peripheral type. */ +#define FSL_FEATURE_LPUART_IS_SCI (1) +/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ +#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) +/* @brief Supports two match addresses to filter incoming frames. */ +#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) +/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) +/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ +#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) +/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ +#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) +/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ +#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) +/* @brief Has improved smart card (ISO7816 protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) +/* @brief Has local operation network (CEA709.1-B protocol) support. */ +#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) +/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ +#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) +/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ +#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) +/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ +#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Has separate RX and TX interrupts. */ +#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) +/* @brief Has LPAURT_PARAM. */ +#define FSL_FEATURE_LPUART_HAS_PARAM (1) +/* @brief Has LPUART_VERID. */ +#define FSL_FEATURE_LPUART_HAS_VERID (1) +/* @brief Has LPUART_GLOBAL. */ +#define FSL_FEATURE_LPUART_HAS_GLOBAL (1) +/* @brief Has LPUART_PINCFG. */ +#define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* @brief Has register MODEM Control. */ +#define FSL_FEATURE_LPUART_HAS_MCR (0) +/* @brief Has register Half Duplex Control. */ +#define FSL_FEATURE_LPUART_HAS_HDCR (0) +/* @brief Has register Timeout. */ +#define FSL_FEATURE_LPUART_HAS_TIMEOUT (0) + +/* TRDC module features */ + +/* @brief Process master count. */ +#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2) +/* @brief TRDC instance has PID configuration or not. */ +#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0) +/* @brief TRDC instance has MBC. */ +#define FSL_FEATURE_TRDC_HAS_MBC (1) +/* @brief TRDC instance has MRC. */ +#define FSL_FEATURE_TRDC_HAS_MRC (0) +/* @brief TRDC instance has TRDC_CR. */ +#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0) +/* @brief TRDC instance has MDA_Wx_y_DFMT. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0) +/* @brief TRDC instance has TRDC_FDID. */ +#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0) +/* @brief TRDC instance has TRDC_FLW_CTL. */ +#define FSL_FEATURE_TRDC_HAS_FLW (0) + +/* OPAMP module features */ + +/* @brief Opamp has OPAMP_CTR OUTSW bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW (1) +/* @brief Opamp has OPAMP_CTR ADCSW1 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 (1) +/* @brief Opamp has OPAMP_CTR ADCSW2 bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 (1) +/* @brief Opamp has OPAMP_CTR BUFEN bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN (1) +/* @brief Opamp has OPAMP_CTR INPSEL bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL (1) +/* @brief Opamp has OPAMP_CTR TRIGMD bit */ +#define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (1) +/* @brief OPAMP support reference buffer */ +#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1U) + +/* PORT module features */ + +/* @brief Has control lock (register bit PCR[LK]). */ +#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) +/* @brief Has open drain control (register bit PCR[ODE]). */ +#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) +/* @brief Has digital filter (registers DFER, DFCR and DFWR). */ +#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) +/* @brief Has DMA request (register bit field PCR[IRQC] or ICR[IRQC] values). */ +#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (0) +/* @brief Has pull resistor selection available. */ +#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) +/* @brief Has pull resistor enable (register bit PCR[PE]). */ +#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) +/* @brief Has slew rate control (register bit PCR[SRE]). */ +#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) +/* @brief Has passive filter (register bit field PCR[PFE]). */ +#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) +/* @brief Do not has interrupt control (register ISFR). */ +#define FSL_FEATURE_PORT_HAS_NO_INTERRUPT (1) +/* @brief Has pull value (register bit field PCR[PV]). */ +#define FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE (1) +/* @brief Has drive strength1 control (register bit PCR[DSE1]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 (1) +/* @brief Has version ID register (register VERID). */ +#define FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER (1) +/* @brief Has voltage range control (register bit CONFIG[RANGE]). */ +#define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1) +/* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */ +#define FSL_FEATURE_PORT_SUPPORT_EFT (0) +/* @brief Function 0 is GPIO. */ +#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0) +/* @brief Has drive strength control (register bit PCR[DSE]). */ +#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) +/* @brief Defines width of PCR[MUX] field. */ +#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (4) +/* @brief Has dedicated interrupt vector. */ +#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) +/* @brief Has independent interrupt control(register ICR). */ +#define FSL_FEATURE_PORT_HAS_INDEPENDENT_INTERRUPT_CONTROL (0) +/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ +#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) +/* @brief Has Input Buffer Enable (register bit field PCR[IBE]). */ +#define FSL_FEATURE_PORT_HAS_INPUT_BUFFER (1) +/* @brief Has Invert Input (register bit field PCR[INV]). */ +#define FSL_FEATURE_PORT_HAS_INVERT_INPUT (1) +/* @brief Defines whether PCR[IRQC] bit-field has flag states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) +/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ +#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) + +/* EQDC module features */ + +/* @brief If EQDC CTRL2 register has EMIP bit field. */ +#define FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD (1) + +/* SPC module features */ + +/* @brief Has DCDC */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC (0) +/* @brief Has SYS LDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (0) +/* @brief Has IOVDD_LVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (0) +/* @brief Has COREVDD_HVDF */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (0) +/* @brief Has CORELDO_VDD_DS */ +#define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1) +/* @brief Has LPBUFF_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (0) +/* @brief Has COREVDD_IVS_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (0) +/* @brief Has SWITCH_STATE */ +#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0) +/* @brief Has SRAMRETLDO */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (1) +/* @brief Has CFG register */ +#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0) +/* @brief Has SRAMLDO_DPD_ON */ +#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (1) +/* @brief Has CNTRL register */ +#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (0) +/* @brief Has DPDOWN_PULLDOWN_DISABLE */ +#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (0) +/* @brief Not have glitch detect */ +#define FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT (1) +/* @brief Has BLEED_EN */ +#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (0) + +/* SYSCON module features */ + +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (128) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (8192) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (1048576) +/* @brief Support ROMAPI */ +#define FSL_FEATURE_SYSCON_ROMAPI (1) +/* @brief Powerlib API is different with other series devices */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) +/* @brief No OSTIMER register in PMC */ +#define FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG (1) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) + +/* USB module features */ + +/* @brief KHCI module instance count */ +#define FSL_FEATURE_USB_KHCI_COUNT (1) +/* @brief HOST mode enabled */ +#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (0) +/* @brief OTG mode enabled */ +#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (0) +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_KHCI_USB_RAM (0) +/* @brief Has KEEP_ALIVE_CTRL register */ +#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) +/* @brief Has the Dynamic SOF threshold compare support */ +#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0) +/* @brief Has the VBUS detect support */ +#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (1) +/* @brief Has the IRC48M module clock support */ +#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USB_ENDPT_COUNT (16) +/* @brief Has STALL_IL/OL_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (1) +/* @brief Has STALL_IH/OH_DIS registers */ +#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (1) + +/* UTICK module features */ + +/* @brief UTICK does not support PD configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) + +/* VBAT module features */ + +/* @brief Has STATUS register */ +#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (0) +/* @brief Has TAMPER register */ +#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (0) +/* @brief Has BANDGAP register */ +#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (0) +/* @brief Has LDOCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (0) +/* @brief Has OSCCTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (0) +/* @brief Has SWICTL register */ +#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (0) +/* @brief Has CLKMON register */ +#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0) + +/* WWDT module features */ + +/* @brief Has no RESET register. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) + +#endif /* _MCXA156_FEATURES_H_ */ + diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/arm/MCXA156_flash.scf b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/arm/MCXA156_flash.scf new file mode 100644 index 00000000000..265cd9533cc --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/arm/MCXA156_flash.scf @@ -0,0 +1,71 @@ +#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c +/* +** ################################################################### +** Processors: MCXA156VLL +** MCXA156VMP +** MCXA156VPJ +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: MCXA18 User manual +** Version: rev. 1.0, 2022-03-29 +** Build: b240104 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#define m_interrupts_start 0x00000000 +#define m_interrupts_size 0x00000200 + +#define m_text_start 0x00000200 +#define m_text_size 0x000FFE00 + +#define m_data_start 0x20000000 +#define m_data_size 0x0001E000 + +#define m_sramx0_start 0x04000000; +#define m_sramx0_size 0x00002000; + +LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region + + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (.isr_vector,+FIRST) + } + + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } + +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/arm/MCXA156_ram.scf b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/arm/MCXA156_ram.scf new file mode 100644 index 00000000000..d3cdf8c9006 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/arm/MCXA156_ram.scf @@ -0,0 +1,68 @@ +#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c +/* +** ################################################################### +** Processors: MCXA156VLL +** MCXA156VMP +** MCXA156VPJ +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: MCXA18 User manual +** Version: rev. 1.0, 2022-03-29 +** Build: b240104 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#define m_interrupts_start 0x20000000 +#define m_interrupts_size 0x00000200 + +#define m_text_start 0x20000200 +#define m_text_size 0x00005E00 + +#define m_data_start 0x20006000 +#define m_data_size 0x00018000 + +LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region + + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (.isr_vector,+FIRST) + } + + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } + +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/arm/MCXA15X.dbgconf b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/arm/MCXA15X.dbgconf new file mode 100644 index 00000000000..a59776c1989 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/arm/MCXA15X.dbgconf @@ -0,0 +1,18 @@ +// <<< Use Configuration Wizard in Context Menu >>> + +// SWO pin +// The SWO (Serial Wire Output) pin optionally provides data from the ITM +// for an external debug tool to evaluate. +// <0=> PIO0_10 +// <1=> PIO0_8 +SWO_Pin = 0; +// + +// Debug Configuration +// StopAfterBootloader Stop after Bootloader +// +Dbg_CR = 0x00000001; +// + + +// <<< end of configuration section >>> diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/arm/MCXA15X_1024.FLM b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/arm/MCXA15X_1024.FLM new file mode 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config->PT0AC = (aoi_input_config_t)temp; + temp = (value & AOI_BFCRT01_PT0_BC_MASK) >> AOI_BFCRT01_PT0_BC_SHIFT; + config->PT0BC = (aoi_input_config_t)temp; + temp = (value & AOI_BFCRT01_PT0_CC_MASK) >> AOI_BFCRT01_PT0_CC_SHIFT; + config->PT0CC = (aoi_input_config_t)temp; + temp = (value & AOI_BFCRT01_PT0_DC_MASK) >> AOI_BFCRT01_PT0_DC_SHIFT; + config->PT0DC = (aoi_input_config_t)temp; + + temp = (value & AOI_BFCRT01_PT1_AC_MASK) >> AOI_BFCRT01_PT1_AC_SHIFT; + config->PT1AC = (aoi_input_config_t)temp; + temp = (value & AOI_BFCRT01_PT1_BC_MASK) >> AOI_BFCRT01_PT1_BC_SHIFT; + config->PT1BC = (aoi_input_config_t)temp; + temp = (value & AOI_BFCRT01_PT1_CC_MASK) >> AOI_BFCRT01_PT1_CC_SHIFT; + config->PT1CC = (aoi_input_config_t)temp; + temp = (value & AOI_BFCRT01_PT1_DC_MASK) >> AOI_BFCRT01_PT1_DC_SHIFT; + config->PT1DC = (aoi_input_config_t)temp; + + /* Read BFCRT23 register at event index. */ + value = base->BFCRT[event].BFCRT23; + + temp = (value & AOI_BFCRT23_PT2_AC_MASK) >> AOI_BFCRT23_PT2_AC_SHIFT; + config->PT2AC = (aoi_input_config_t)temp; + temp = (value & AOI_BFCRT23_PT2_BC_MASK) >> AOI_BFCRT23_PT2_BC_SHIFT; + config->PT2BC = (aoi_input_config_t)temp; + temp = (value & AOI_BFCRT23_PT2_CC_MASK) >> AOI_BFCRT23_PT2_CC_SHIFT; + config->PT2CC = (aoi_input_config_t)temp; + temp = (value & AOI_BFCRT23_PT2_DC_MASK) >> AOI_BFCRT23_PT2_DC_SHIFT; + config->PT2DC = (aoi_input_config_t)temp; + + temp = (value & AOI_BFCRT23_PT3_AC_MASK) >> AOI_BFCRT23_PT3_AC_SHIFT; + config->PT3AC = (aoi_input_config_t)temp; + temp = (value & AOI_BFCRT23_PT3_BC_MASK) >> AOI_BFCRT23_PT3_BC_SHIFT; + config->PT3BC = (aoi_input_config_t)temp; + temp = (value & AOI_BFCRT23_PT3_CC_MASK) >> AOI_BFCRT23_PT3_CC_SHIFT; + config->PT3CC = (aoi_input_config_t)temp; + temp = (value & AOI_BFCRT23_PT3_DC_MASK) >> AOI_BFCRT23_PT3_DC_SHIFT; + config->PT3DC = (aoi_input_config_t)temp; +} + +/*! + * brief Configures an AOI event. + * + * This function configures an AOI event according + * to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D) + * of all product terms (0, 1, 2, and 3) of a desired event. + * + * Example: + code + aoi_event_config_t demoEventLogicStruct; + + demoEventLogicStruct.PT0AC = kAOI_InvInputSignal; + demoEventLogicStruct.PT0BC = kAOI_InputSignal; + demoEventLogicStruct.PT0CC = kAOI_LogicOne; + demoEventLogicStruct.PT0DC = kAOI_LogicOne; + + demoEventLogicStruct.PT1AC = kAOI_LogicZero; + demoEventLogicStruct.PT1BC = kAOI_LogicOne; + demoEventLogicStruct.PT1CC = kAOI_LogicOne; + demoEventLogicStruct.PT1DC = kAOI_LogicOne; + + demoEventLogicStruct.PT2AC = kAOI_LogicZero; + demoEventLogicStruct.PT2BC = kAOI_LogicOne; + demoEventLogicStruct.PT2CC = kAOI_LogicOne; + demoEventLogicStruct.PT2DC = kAOI_LogicOne; + + demoEventLogicStruct.PT3AC = kAOI_LogicZero; + demoEventLogicStruct.PT3BC = kAOI_LogicOne; + demoEventLogicStruct.PT3CC = kAOI_LogicOne; + demoEventLogicStruct.PT3DC = kAOI_LogicOne; + + AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct); + endcode + * + * param base AOI peripheral address. + * param event Event which will be configured of type aoi_event_t. + * param eventConfig Pointer to type aoi_event_config_t structure. The user is responsible for + * filling out the members of this structure and passing the pointer to this function. + */ +void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig) +{ + assert(eventConfig != NULL); + assert((uint32_t)event < (uint32_t)FSL_FEATURE_AOI_EVENT_COUNT); + + uint16_t value; + /* Calculate value to configure product term 0, 1 */ + value = AOI_BFCRT01_PT0_AC(eventConfig->PT0AC) | AOI_BFCRT01_PT0_BC(eventConfig->PT0BC) | + AOI_BFCRT01_PT0_CC(eventConfig->PT0CC) | AOI_BFCRT01_PT0_DC(eventConfig->PT0DC) | + AOI_BFCRT01_PT1_AC(eventConfig->PT1AC) | AOI_BFCRT01_PT1_BC(eventConfig->PT1BC) | + AOI_BFCRT01_PT1_CC(eventConfig->PT1CC) | AOI_BFCRT01_PT1_DC(eventConfig->PT1DC); + /* Write value to register */ + base->BFCRT[event].BFCRT01 = value; + + /* Reset and calculate value to configure product term 2, 3 */ + value = AOI_BFCRT23_PT2_AC(eventConfig->PT2AC) | AOI_BFCRT23_PT2_BC(eventConfig->PT2BC) | + AOI_BFCRT23_PT2_CC(eventConfig->PT2CC) | AOI_BFCRT23_PT2_DC(eventConfig->PT2DC) | + AOI_BFCRT23_PT3_AC(eventConfig->PT3AC) | AOI_BFCRT23_PT3_BC(eventConfig->PT3BC) | + AOI_BFCRT23_PT3_CC(eventConfig->PT3CC) | AOI_BFCRT23_PT3_DC(eventConfig->PT3DC); + /* Write value to register */ + base->BFCRT[event].BFCRT23 = value; +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_aoi.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_aoi.h new file mode 100644 index 00000000000..3b1126e623e --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_aoi.h @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_AOI_H_ +#define FSL_AOI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup aoi + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifndef AOI +#define AOI AOI0 /*!< AOI peripheral address */ +#endif + +/*! @name Driver version */ +/*! @{ */ +#define FSL_AOI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2. */ +/*! @} */ + +/*! + * @brief AOI input configurations. + * + * The selection item represents the Boolean evaluations. + */ +typedef enum _aoi_input_config +{ + kAOI_LogicZero = 0x0U, /*!< Forces the input to logical zero. */ + kAOI_InputSignal = 0x1U, /*!< Passes the input signal. */ + kAOI_InvInputSignal = 0x2U, /*!< Inverts the input signal. */ + kAOI_LogicOne = 0x3U /*!< Forces the input to logical one. */ +} aoi_input_config_t; + +/*! + * @brief AOI event indexes, where an event is the collection of the four product + * terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D). + */ +typedef enum _aoi_event +{ + kAOI_Event0 = 0x0U, /*!< Event 0 index */ + kAOI_Event1 = 0x1U, /*!< Event 1 index */ + kAOI_Event2 = 0x2U, /*!< Event 2 index */ + kAOI_Event3 = 0x3U /*!< Event 3 index */ +} aoi_event_t; + +/*! + * @brief AOI event configuration structure + * + * Defines structure _aoi_event_config and use the AOI_SetEventLogicConfig() function to make + * whole event configuration. + */ +typedef struct _aoi_event_config +{ + aoi_input_config_t PT0AC; /*!< Product term 0 input A */ + aoi_input_config_t PT0BC; /*!< Product term 0 input B */ + aoi_input_config_t PT0CC; /*!< Product term 0 input C */ + aoi_input_config_t PT0DC; /*!< Product term 0 input D */ + aoi_input_config_t PT1AC; /*!< Product term 1 input A */ + aoi_input_config_t PT1BC; /*!< Product term 1 input B */ + aoi_input_config_t PT1CC; /*!< Product term 1 input C */ + aoi_input_config_t PT1DC; /*!< Product term 1 input D */ + aoi_input_config_t PT2AC; /*!< Product term 2 input A */ + aoi_input_config_t PT2BC; /*!< Product term 2 input B */ + aoi_input_config_t PT2CC; /*!< Product term 2 input C */ + aoi_input_config_t PT2DC; /*!< Product term 2 input D */ + aoi_input_config_t PT3AC; /*!< Product term 3 input A */ + aoi_input_config_t PT3BC; /*!< Product term 3 input B */ + aoi_input_config_t PT3CC; /*!< Product term 3 input C */ + aoi_input_config_t PT3DC; /*!< Product term 3 input D */ +} aoi_event_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @name AOI Initialization + * @{ + */ + +/*! + * @brief Initializes an AOI instance for operation. + * + * This function un-gates the AOI clock. + * + * @param base AOI peripheral address. + */ +void AOI_Init(AOI_Type *base); + +/*! + * @brief Deinitializes an AOI instance for operation. + * + * This function shutdowns AOI module. + * + * @param base AOI peripheral address. + */ +void AOI_Deinit(AOI_Type *base); + +/*! @} */ + +/*! + * @name AOI Get Set Operation + * @{ + */ + +/*! + * @brief Gets the Boolean evaluation associated. + * + * This function returns the Boolean evaluation associated. + * + * Example: + @code + aoi_event_config_t demoEventLogicStruct; + + AOI_GetEventLogicConfig(AOI, kAOI_Event0, &demoEventLogicStruct); + @endcode + * + * @param base AOI peripheral address. + * @param event Index of the event which will be set of type aoi_event_t. + * @param config Selected input configuration . + */ +void AOI_GetEventLogicConfig(AOI_Type *base, aoi_event_t event, aoi_event_config_t *config); + +/*! + * @brief Configures an AOI event. + * + * This function configures an AOI event according + * to the aoiEventConfig structure. This function configures all inputs (A, B, C, and D) + * of all product terms (0, 1, 2, and 3) of a desired event. + * + * Example: + @code + aoi_event_config_t demoEventLogicStruct; + + demoEventLogicStruct.PT0AC = kAOI_InvInputSignal; + demoEventLogicStruct.PT0BC = kAOI_InputSignal; + demoEventLogicStruct.PT0CC = kAOI_LogicOne; + demoEventLogicStruct.PT0DC = kAOI_LogicOne; + + demoEventLogicStruct.PT1AC = kAOI_LogicZero; + demoEventLogicStruct.PT1BC = kAOI_LogicOne; + demoEventLogicStruct.PT1CC = kAOI_LogicOne; + demoEventLogicStruct.PT1DC = kAOI_LogicOne; + + demoEventLogicStruct.PT2AC = kAOI_LogicZero; + demoEventLogicStruct.PT2BC = kAOI_LogicOne; + demoEventLogicStruct.PT2CC = kAOI_LogicOne; + demoEventLogicStruct.PT2DC = kAOI_LogicOne; + + demoEventLogicStruct.PT3AC = kAOI_LogicZero; + demoEventLogicStruct.PT3BC = kAOI_LogicOne; + demoEventLogicStruct.PT3CC = kAOI_LogicOne; + demoEventLogicStruct.PT3DC = kAOI_LogicOne; + + AOI_SetEventLogicConfig(AOI, kAOI_Event0, demoEventLogicStruct); + @endcode + * + * @param base AOI peripheral address. + * @param event Event which will be configured of type aoi_event_t. + * @param eventConfig Pointer to type aoi_event_config_t structure. The user is responsible for + * filling out the members of this structure and passing the pointer to this function. + */ +void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_config_t *eventConfig); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @} */ + +/*!* @} */ + +#endif /* FSL_AOI_H_*/ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_cdog.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_cdog.c new file mode 100644 index 00000000000..cd3ed6eaa3f --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_cdog.c @@ -0,0 +1,378 @@ +/* + * Copyright 2020-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_cdog.h" + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.cdog" +#endif + +/* Reset CONTROL mask */ +#define RESERVED_CTRL_MASK 0x800u + +#if defined(CDOG_IRQS) +/* Array of IRQs */ +static const IRQn_Type s_CdogIrqs[] = CDOG_IRQS; +#endif /* CDOG_IRQS */ + +#ifdef CDOG_CLOCKS +static const clock_ip_name_t s_CdogClocks[] = CDOG_CLOCKS; +#endif /* CDOG_CLOCKS */ + +#ifdef CDOG_BASE_PTRS +static const CDOG_Type* s_cdogBases[] = CDOG_BASE_PTRS; +#endif /* CDOG_BASE_PTRS */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t CDOG_GetInstance(CDOG_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_cdogBases); instance++) + { + if (s_cdogBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_cdogBases)); + + return instance; +} + +/*! + * brief Sets the default configuration of CDOG + * + * This function initialize CDOG config structure to default values. + * + * param conf CDOG configuration structure + */ +void CDOG_GetDefaultConfig(cdog_config_t *conf) +{ + /* Default configuration after reset */ + conf->lock = (uint8_t)kCDOG_LockCtrl_Unlock; /* Lock control */ + conf->timeout = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Timeout control */ + conf->miscompare = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Miscompare control */ + conf->sequence = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Sequence control */ + conf->state = (uint8_t)kCDOG_FaultCtrl_NoAction; /* State control */ + conf->address = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Address control */ + conf->irq_pause = (uint8_t)kCDOG_IrqPauseCtrl_Run; /* IRQ pause control */ + conf->debug_halt = (uint8_t)kCDOG_DebugHaltCtrl_Run; /* Debug halt control */ + return; +} + +/*! + * brief Sets secure counter and instruction timer values + * + * This function sets value in RELOAD and START registers for instruction timer. + * + * param base CDOG peripheral base address + * param reload reload value + * param start start value + */ +void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start) +{ + base->RELOAD = reload; + base->START = start; +} + +/*! + * brief Stops secure counter and instruction timer + * + * This function stops instruction timer and secure counter. + * This also change state of CDOG to IDLE. + * + * param base CDOG peripheral base address + * param stop expected value which will be compared with value of secure counter + */ +void CDOG_Stop(CDOG_Type *base, uint32_t stop) +{ + base->STOP = stop; +} + +/*! + * brief Sets secure counter and instruction timer values + * + * This function sets value in STOP, RELOAD and START registers + * for instruction timer and secure counter. + * + * param base CDOG peripheral base address + * param stop expected value which will be compared with value of secure counter + * param reload reload value for instruction timer + * param start start value for secure timer + */ +void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start) +{ + base->STOP = stop; + base->RELOAD = reload; + base->START = start; +} + +/*! + * brief Add value to secure counter + * + * This function add specified value to secure counter. + * + * param base CDOG peripheral base address. + * param add Value to be added. + */ +void CDOG_Add(CDOG_Type *base, uint32_t add) +{ + base->ADD = (secure_counter_t)add; +} + +/*! + * brief Add 1 to secure counter + * + * This function add 1 to secure counter. + * + * param base CDOG peripheral base address. + * param add Value to be added. + */ +void CDOG_Add1(CDOG_Type *base) +{ + base->ADD1 = (secure_counter_t)0x1U; +} + +/*! + * brief Add 16 to secure counter + * + * This function add 16 to secure counter. + * + * param base CDOG peripheral base address. + * param add Value to be added. + */ +void CDOG_Add16(CDOG_Type *base) +{ + base->ADD16 = (secure_counter_t)0x1U; +} + +/*! + * brief Add 256 to secure counter + * + * This function add 256 to secure counter. + * + * param base CDOG peripheral base address. + * param add Value to be added. + */ +void CDOG_Add256(CDOG_Type *base) +{ + base->ADD256 = (secure_counter_t)0x1U; +} + +/*! + * brief Substract value to secure counter + * + * This function substract specified value to secure counter. + * + * param base CDOG peripheral base address. + * param sub Value to be substracted. + */ +void CDOG_Sub(CDOG_Type *base, uint32_t sub) +{ + base->SUB = (secure_counter_t)sub; +} + +/*! + * brief Substract 1 from secure counter + * + * This function substract specified 1 from secure counter. + * + * param base CDOG peripheral base address. + */ +void CDOG_Sub1(CDOG_Type *base) +{ + base->SUB1 = (secure_counter_t)0x1U; +} + +/*! + * brief Substract 16 from secure counter + * + * This function substract specified 16 from secure counter. + * + * param base CDOG peripheral base address. + */ +void CDOG_Sub16(CDOG_Type *base) +{ + base->SUB16 = (secure_counter_t)0x1U; +} + +/*! + * brief Substract 256 from secure counter + * + * This function substract specified 256 from secure counter. + * + * param base CDOG peripheral base address. + */ +void CDOG_Sub256(CDOG_Type *base) +{ + base->SUB256 = (secure_counter_t)0x1U; +} + +/*! + * brief Checks secure counter. + * + * This function compares stop value with secure counter value + * by writting to RELOAD refister. + * + * param base CDOG peripheral base address + * param check expected (stop) value. + */ +void CDOG_Check(CDOG_Type *base, uint32_t check) +{ +#if defined(FLS_FEATURE_CDOG_USE_RESTART) + base->RESTART = check; +#else + base->STOP = check; + base->RELOAD = base->RELOAD; + base->START= check; +#endif +} + +/*! + * brief Set the CDOG persistent word. + * + * param base CDOG peripheral base address. + * param value The value to be written. + */ +void CDOG_WritePersistent(CDOG_Type *base, uint32_t value) +{ + base->PERSISTENT = value; +} + +/*! + * brief Get the CDOG persistent word. + * + * param base CDOG peripheral base address. + * return The persistent word. + */ +uint32_t CDOG_ReadPersistent(CDOG_Type *base) +{ + return base->PERSISTENT; +} + +/*! + * brief Initialize CDOG + * + * This function initializes CDOG setting and enable all interrupts. + * + * param base CDOG peripheral base address + * param conf CDOG configuration structure + * return Status of the init operation + */ +status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf) +{ + /* Ungate clock to CDOG engine and reset it */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#ifdef CDOG_CLOCKS + CLOCK_EnableClock(s_CdogClocks[CDOG_GetInstance(base)]); +#endif /* CDOG_CLOCKS */ +#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET) + RESET_PeripheralReset(kCDOG_RST_SHIFT_RSTn); +#endif /* !FSL_FEATURE_CDOG_HAS_NO_RESET */ + + if (base->CONTROL == 0x0U) + { + /* CDOG is not in IDLE mode, which may be cause after SW reset. */ + /* Writing to CONTROL register will trigger fault. */ + return kStatus_Fail; + } + + /* Clear pending errors, otherwise the device will reset */ + /* itself immediately after enable Code Watchdog */ + if ((uint32_t)kCDOG_LockCtrl_Lock == + ((base->CONTROL & CDOG_CONTROL_LOCK_CTRL_MASK) >> CDOG_CONTROL_LOCK_CTRL_SHIFT)) + + { + base->FLAGS = CDOG_FLAGS_TO_FLAG(1U) | CDOG_FLAGS_MISCOM_FLAG(1U) | CDOG_FLAGS_SEQ_FLAG(1U) | + CDOG_FLAGS_CNT_FLAG(1U) | CDOG_FLAGS_STATE_FLAG(1U) | CDOG_FLAGS_ADDR_FLAG(1U) | + CDOG_FLAGS_POR_FLAG(1U); + } + else + { +/* load default values for CDOG->CONTROL before flags clear */ +#if defined(FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF) && (FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF > 0) + cdog_config_t default_conf; + + /* Initialize CDOG */ + CDOG_GetDefaultConfig(&default_conf); + + /* Write default value to CDOG->CONTROL*/ + base->CONTROL = + CDOG_CONTROL_TIMEOUT_CTRL(default_conf.timeout) | /* Action if the timeout event is triggered */ + CDOG_CONTROL_MISCOMPARE_CTRL(default_conf.miscompare) | /* Action if the miscompare error event is triggered */ + CDOG_CONTROL_SEQUENCE_CTRL(default_conf.sequence) | /* Action if the sequence error event is triggered */ + CDOG_CONTROL_STATE_CTRL(default_conf.state) | /* Action if the state error event is triggered */ + CDOG_CONTROL_ADDRESS_CTRL(default_conf.address) | /* Action if the address error event is triggered */ + CDOG_CONTROL_IRQ_PAUSE(default_conf.irq_pause) | /* Pause running during interrupts setup */ + CDOG_CONTROL_DEBUG_HALT_CTRL(default_conf.debug_halt) | /* Halt CDOG timer during debug */ + CDOG_CONTROL_LOCK_CTRL(default_conf.lock) | RESERVED_CTRL_MASK; /* Lock control register, RESERVED */ +#endif /* FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF */ + + base->FLAGS = CDOG_FLAGS_TO_FLAG(0U) | CDOG_FLAGS_MISCOM_FLAG(0U) | CDOG_FLAGS_SEQ_FLAG(0U) | + CDOG_FLAGS_CNT_FLAG(0U) | CDOG_FLAGS_STATE_FLAG(0U) | CDOG_FLAGS_ADDR_FLAG(0U) | + CDOG_FLAGS_POR_FLAG(0U); + } + + base->CONTROL = + CDOG_CONTROL_TIMEOUT_CTRL(conf->timeout) | /* Action if the timeout event is triggered */ + CDOG_CONTROL_MISCOMPARE_CTRL(conf->miscompare) | /* Action if the miscompare error event is triggered */ + CDOG_CONTROL_SEQUENCE_CTRL(conf->sequence) | /* Action if the sequence error event is triggered */ + CDOG_CONTROL_STATE_CTRL(conf->state) | /* Action if the state error event is triggered */ + CDOG_CONTROL_ADDRESS_CTRL(conf->address) | /* Action if the address error event is triggered */ + CDOG_CONTROL_IRQ_PAUSE(conf->irq_pause) | /* Pause running during interrupts setup */ + CDOG_CONTROL_DEBUG_HALT_CTRL(conf->debug_halt) | /* Halt CDOG timer during debug */ + CDOG_CONTROL_LOCK_CTRL(conf->lock) | RESERVED_CTRL_MASK; /* Lock control register, RESERVED */ + +#if defined(CDOG_IRQS) + /* Enable peripheral IRQ */ + NVIC_EnableIRQ(s_CdogIrqs[CDOG_GetInstance(base)]); +#endif /* CDOG_IRQS */ + + return kStatus_Success; +} + +/*! + * brief Deinitialize CDOG + * + * This function stops CDOG secure counter. + * + * param base CDOG peripheral base address + */ +void CDOG_Deinit(CDOG_Type *base) +{ +#if defined(CDOG_IRQS) + /* Disable peripheral IRQ */ + NVIC_DisableIRQ(s_CdogIrqs[CDOG_GetInstance(base)]); +#endif /* CDOG_IRQS */ + +#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET) + RESET_SetPeripheralReset(kCDOG_RST_SHIFT_RSTn); +#endif /* !FSL_FEATURE_CDOG_HAS_NO_RESET */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#ifdef CDOG_CLOCKS + CLOCK_DisableClock(s_CdogClocks[CDOG_GetInstance(base)]); +#endif /* CDOG_CLOCKS */ +#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_cdog.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_cdog.h new file mode 100644 index 00000000000..7252eaccd8c --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_cdog.h @@ -0,0 +1,329 @@ +/* + * Copyright 2020-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_CDOG_H_ +#define FSL_CDOG_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup CDOG + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief Defines CDOG driver version 2.1.3. + * + * Change log: + * - Version 2.1.3 + * - Re-design multiple instance IRQs and Clocks + * - Add fix for RESTART command errata + * - Version 2.1.2 + * - Support multiple IRQs + * - Fix default CONTROL values + * - Version 2.1.1 + * - Remove bit CONTROL[CONTROL_CTRL] + * - Version 2.1.0 + * - Rename CWT to CDOG + * - Version 2.0.2 + * - Fix MISRA-2012 issues + * - Version 2.0.1 + * - Fix doxygen issues + * - Version 2.0.0 + * - initial version + */ +#define FSL_CDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) +/*! @} */ + +typedef struct +{ + uint8_t lock : 2; + uint8_t timeout : 3; + uint8_t miscompare : 3; + uint8_t sequence : 3; + uint8_t state : 3; + uint8_t address : 3; + uint8_t reserved : 8; + uint8_t irq_pause : 2; + uint8_t debug_halt : 2; +} cdog_config_t; + +enum __cdog_debug_Action_ctrl_enum +{ + kCDOG_DebugHaltCtrl_Run = 0x1, + kCDOG_DebugHaltCtrl_Pause = 0x2, +}; + +enum __cdog_irq_pause_ctrl_enum +{ + kCDOG_IrqPauseCtrl_Run = 0x1, + kCDOG_IrqPauseCtrl_Pause = 0x2, +}; + +enum __cdog_fault_ctrl_enum +{ + kCDOG_FaultCtrl_EnableReset = 0x1U, + kCDOG_FaultCtrl_EnableInterrupt = 0x2U, + kCDOG_FaultCtrl_NoAction = 0x4U, +}; + +enum __code_lock_ctrl_enum +{ + kCDOG_LockCtrl_Lock = 0x1, + kCDOG_LockCtrl_Unlock = 0x2, +}; + +typedef uint32_t secure_counter_t; + +#define SC_ADD(add) \ + do \ + { \ + CDOG->ADD = (secure_counter_t)(add); \ + } while (0) + +#define SC_ADD1 \ + do \ + { \ + CDOG->ADD1 = (secure_counter_t)0x1U; \ + } while (0) + +#define SC_ADD16 \ + do \ + { \ + CDOG->ADD16 = (secure_counter_t)0x1U; \ + } while (0) + +#define SC_ADD256 \ + do \ + { \ + CDOG->ADD256 = (secure_counter_t)0x1U; \ + } while (0) + +#define SC_SUB(sub) \ + do \ + { \ + CDOG->SUB = (secure_counter_t)(sub); \ + } while (0) + +#define SC_SUB1 \ + do \ + { \ + CDOG->SUB1 = (secure_counter_t)0x1U; \ + } while (0) + +#define SC_SUB16 \ + do \ + { \ + CDOG->SUB16 = (secure_counter_t)0x1U; \ + } while (0) + +#define SC_SUB256 \ + do \ + { \ + CDOG->SUB256 = (secure_counter_t)0x1U; \ + } while (0) + +#define SC_CHECK(val) \ + do \ + { \ + CDOG->RESTART = (secure_counter_t)val; \ + } while (0) + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name CDOG Functional Operation + * @{ + */ + +/*! + * @brief Initialize CDOG + * + * This function initializes CDOG block and setting. + * + * @param base CDOG peripheral base address + * @param conf CDOG configuration structure + * @return Status of the init operation + */ +status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf); + +/*! + * @brief Deinitialize CDOG + * + * This function deinitializes CDOG secure counter. + * + * @param base CDOG peripheral base address + */ +void CDOG_Deinit(CDOG_Type *base); + +/*! + * @brief Sets the default configuration of CDOG + * + * This function initialize CDOG config structure to default values. + * + * @param conf CDOG configuration structure + */ +void CDOG_GetDefaultConfig(cdog_config_t *conf); + +/*! + * @brief Stops secure counter and instruction timer + * + * This function stops instruction timer and secure counter. + * This also change state od CDOG to IDLE. + * + * @param base CDOG peripheral base address + * @param stop expected value which will be compared with value of secure counter + */ +void CDOG_Stop(CDOG_Type *base, uint32_t stop); + +/*! + * @brief Sets secure counter and instruction timer values + * + * This function sets value in RELOAD and START registers + * for instruction timer and secure counter + * + * @param base CDOG peripheral base address + * @param reload reload value + * @param start start value + */ +void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start); + +/*! + * @brief Checks secure counter. + * + * This function compares stop value in handler with secure counter value + * by writting to RELOAD refister. + * + * @param base CDOG peripheral base address + * @param check expected (stop) value + */ +void CDOG_Check(CDOG_Type *base, uint32_t check); + +/*! + * @brief Sets secure counter and instruction timer values + * + * This function sets value in STOP, RELOAD and START registers + * for instruction timer and secure counter. + * + * @param base CDOG peripheral base address + * @param stop expected value which will be compared with value of secure counter + * @param reload reload value for instruction timer + * @param start start value for secure timer + */ +void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start); + +/*! + * @brief Add value to secure counter + * + * This function add specified value to secure counter. + * + * @param base CDOG peripheral base address. + * @param add Value to be added. + */ +void CDOG_Add(CDOG_Type *base, uint32_t add); + +/*! + * @brief Add 1 to secure counter + * + * This function add 1 to secure counter. + * + * @param base CDOG peripheral base address. + */ +void CDOG_Add1(CDOG_Type *base); + +/*! + * @brief Add 16 to secure counter + * + * This function add 16 to secure counter. + * + * @param base CDOG peripheral base address. + */ +void CDOG_Add16(CDOG_Type *base); + +/*! + * @brief Add 256 to secure counter + * + * This function add 256 to secure counter. + * + * @param base CDOG peripheral base address. + */ +void CDOG_Add256(CDOG_Type *base); + +/*! + * brief Substract value to secure counter + * + * This function substract specified value to secure counter. + * + * param base CDOG peripheral base address. + * param sub Value to be substracted. + */ +void CDOG_Sub(CDOG_Type *base, uint32_t sub); + +/*! + * @brief Substract 1 from secure counter + * + * This function substract specified 1 from secure counter. + * + * @param base CDOG peripheral base address. + */ +void CDOG_Sub1(CDOG_Type *base); + +/*! + * @brief Substract 16 from secure counter + * + * This function substract specified 16 from secure counter. + * + * @param base CDOG peripheral base address. + */ +void CDOG_Sub16(CDOG_Type *base); + +/*! + * @brief Substract 256 from secure counter + * + * This function substract specified 256 from secure counter. + * + * @param base CDOG peripheral base address. + */ +void CDOG_Sub256(CDOG_Type *base); + +/*! + * @brief Set the CDOG persistent word. + * + * @param base CDOG peripheral base address. + * @param value The value to be written. + */ +void CDOG_WritePersistent(CDOG_Type *base, uint32_t value); + +/*! + * @brief Get the CDOG persistent word. + * + * @param base CDOG peripheral base address. + * @return The persistent word. + */ +uint32_t CDOG_ReadPersistent(CDOG_Type *base); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ /* end of group cdog */ + +#endif /* FSL_CDOG_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_clock.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_clock.c new file mode 100644 index 00000000000..00f13896cd5 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_clock.c @@ -0,0 +1,1353 @@ +/* + * Copyright 2023, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_clock.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +/** External clock rate on the CLKIN pin in Hz. If not used, + set this to 0. Otherwise, set it to the exact rate in Hz this pin is + being driven at. */ +volatile static uint32_t s_Ext_Clk_Freq = 16000000U; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/* Get FRO 12M Clk */ +static uint32_t CLOCK_GetFro12MFreq(void); +/* Get CLK 1M Clk */ +static uint32_t CLOCK_GetClk1MFreq(void); +/* Get HF FRO Clk */ +static uint32_t CLOCK_GetFroHfFreq(void); +/* Get CLK 48M Clk */ +static uint32_t CLOCK_GetClk48MFreq(void); +/* Get CLK 16K Clk */ +static uint32_t CLOCK_GetClk16KFreq(uint8_t id); +/* Get EXT OSC Clk */ +static uint32_t CLOCK_GetExtClkFreq(void); +/* Get Main_Clk */ +uint32_t CLOCK_GetMainClk(void); +/* Get FRO_16K */ +static uint32_t CLOCK_GetFRO16KFreq(void); + +/* Check if DIV is halt */ +static inline bool CLOCK_IsDivHalt(uint32_t div_value) +{ + if (0U != (div_value & (1UL << 30U))) + { + return true; + } + else + { + return false; + } +} + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Clock Selection for IP */ +/** + * brief Configure the clock selection muxes. + * param connection : Clock to be configured. + * return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection) +{ + const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); + const uint32_t clk_sel = CLK_ATTACH_CLK_SEL(connection); + + if (kNONE_to_NONE != connection) + { + CLOCK_SetClockSelect((clock_select_name_t)reg_offset, clk_sel); + } +} + +/* Return the actual clock attach id */ +/** + * brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * param connection : Clock attach id to get. + * return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t connection) +{ + const uint32_t reg_offset = CLK_ATTACH_REG_OFFSET(connection); + uint32_t actual_sel = 0U; + uint32_t clock_attach_id = 0U; + + if (kNONE_to_NONE == connection) + { + return kNONE_to_NONE; + } + + actual_sel = CLOCK_GetClockSelect((clock_select_name_t)reg_offset); + clock_attach_id = CLK_ATTACH_MUX(reg_offset, actual_sel); + + return (clock_attach_id_t)clock_attach_id; +} + +/* Set the clock selection value */ +void CLOCK_SetClockSelect(clock_select_name_t sel_name, uint32_t value) +{ + volatile uint32_t *pClkCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)sel_name); + assert(sel_name <= kCLOCK_SelMax); + + if (sel_name == kCLOCK_SelSCGSCS) + { + SCG0->RCCR = (SCG0->RCCR & ~(SCG_RCCR_SCS_MASK)) | SCG_RCCR_SCS(value); + while ((SCG0->CSR & SCG_CSR_SCS_MASK) != SCG_CSR_SCS(value)) + { + } + } + else + { + /* Unlock clock configuration */ + SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK; + + *pClkCtrl = value; + + /* Freeze clock configuration */ + SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK; + } +} + +/* Get the clock selection value */ +uint32_t CLOCK_GetClockSelect(clock_select_name_t sel_name) +{ + volatile uint32_t *pClkCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)sel_name); + uint32_t actual_sel = 0U; + assert(sel_name <= kCLOCK_SelMax); + + if (sel_name == kCLOCK_SelSCGSCS) + { + actual_sel = (uint32_t)((SCG0->RCCR & SCG_RCCR_SCS_MASK) >> SCG_RCCR_SCS_SHIFT); + } + else + { + actual_sel = *pClkCtrl; + } + + return actual_sel; +} + +/* Set the clock divider value */ +void CLOCK_SetClockDiv(clock_div_name_t div_name, uint32_t value) +{ + volatile uint32_t *pDivCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)div_name); + assert(div_name <= kCLOCK_DivMax); + + /* Unlock clock configuration */ + SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK; + + /* halt and reset clock dividers */ + *pDivCtrl = 0x3UL << 29U; + + if (value == 0U) /*!< halt */ + { + *pDivCtrl |= (1UL << 30U); + } + else + { + *pDivCtrl = (value - 1U); + } + + /* Freeze clock configuration */ + SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK; +} + +/* Get the clock divider value */ +uint32_t CLOCK_GetClockDiv(clock_div_name_t div_name) +{ + volatile uint32_t *pDivCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)div_name); + assert(div_name <= kCLOCK_DivMax); + + if (((*pDivCtrl) & (1UL << 30U)) != 0U) + { + return 0; + } + else + { + return ((*pDivCtrl & 0xFFU) + 1U); + } +} + +/* Halt the clock divider value */ +void CLOCK_HaltClockDiv(clock_div_name_t div_name) +{ + volatile uint32_t *pDivCtrl = (volatile uint32_t *)(MRCC0_BASE + (uint32_t)div_name); + assert(div_name <= kCLOCK_DivMax); + + /* Unlock clock configuration */ + SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK; + + *pDivCtrl |= (1UL << 30U); + + /* Freeze clock configuration */ + SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK; +} + +/* Initialize the FROHF to given frequency (48,64,96,192) */ +status_t CLOCK_SetupFROHFClocking(uint32_t iFreq) +{ + uint8_t freq_select = 0x0U; + switch (iFreq) + { + case 48000000U: + freq_select = 1U; + break; + case 64000000U: + freq_select = 3U; + break; + case 96000000U: + freq_select = 5U; + break; + case 192000000U: + freq_select = 7U; + break; + default: + freq_select = 0xFU; + break; + } + + if (0xFU == freq_select) + { + return kStatus_Fail; + } + + /* Set FIRC frequency */ + SCG0->FIRCCFG = SCG_FIRCCFG_FREQ_SEL(freq_select); + + /* Unlock FIRCCSR */ + SCG0->FIRCCSR &= ~SCG_FIRCCSR_LK_MASK; + + /* Enable CLK 48 MHz clock for peripheral use */ + SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; + /* Enable FIRC HF clock for peripheral use */ + SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_MASK; + /* Enable FIRC */ + SCG0->FIRCCSR |= SCG_FIRCCSR_FIRCEN_MASK; + + /* Lock FIRCCSR */ + SCG0->FIRCCSR |= SCG_FIRCCSR_LK_MASK; + + /* Wait for FIRC clock to be valid. */ + while ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK) == 0U) + { + } + + return kStatus_Success; +} + +/* Initialize the FRO12M. */ +status_t CLOCK_SetupFRO12MClocking(void) +{ + /* Unlock SIRCCSR */ + SCG0->SIRCCSR &= ~SCG_SIRCCSR_LK_MASK; + + /* Enable FRO12M clock for peripheral use */ + SCG0->SIRCCSR |= SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK; + + /* Lock SIRCCSR */ + SCG0->SIRCCSR |= SCG_SIRCCSR_LK_MASK; + + /* Wait for SIRC clock to be valid. */ + while ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK) == 0U) + { + } + + return kStatus_Success; +} + +/*! + * brief Initialize the FRO16K. + * This function turns on FRO16K. + * return returns success or fail status. + */ +status_t CLOCK_SetupFRO16KClocking(uint8_t clk_16k_enable_mask) +{ + VBAT0->FROCTLA |= VBAT_FROCTLA_FRO_EN_MASK; + VBAT0->FROLCKA |= VBAT_FROLCKA_LOCK_MASK; + + /* enable clk_16k output clock to corresponding modules according to the enable_mask. */ + VBAT0->FROCLKE |= VBAT_FROCLKE_CLKE(((uint32_t)clk_16k_enable_mask)); + + return kStatus_Success; +} + +/*! + * brief Initialize the external osc clock to given frequency. + * param iFreq : Desired frequency (must be equal to exact rate in Hz) + * return returns success or fail status. + */ +status_t CLOCK_SetupExtClocking(uint32_t iFreq) +{ + uint8_t range = 0U; + + if ((iFreq >= 8000000U) && (iFreq < 16000000U)) + { + range = 0U; + } + else if ((iFreq >= 16000000U) && (iFreq < 25000000U)) + { + range = 1U; + } + else if ((iFreq >= 25000000U) && (iFreq < 40000000U)) + { + range = 2U; + } + else if ((iFreq >= 40000000U) && (iFreq <= 50000000U)) + { + range = 3U; + } + else + { + return kStatus_InvalidArgument; + } + + /* If configure register is locked, return error. */ + if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U) + { + return kStatus_ReadOnly; + } + + /* De-initializes the SCG SOSC */ + SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK; + + /* Select SOSC source (internal crystal oscillator) and Configure SOSC range */ + SCG0->SOSCCFG = SCG_SOSCCFG_EREFS_MASK | SCG_SOSCCFG_RANGE(range); + + /* Unlock SOSCCSR */ + SCG0->SOSCCSR &= ~SCG_SOSCCSR_LK_MASK; + + /* Enable SOSC clock monitor and Enable SOSC */ + SCG0->SOSCCSR |= (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCEN_MASK); + + /* Wait for SOSC clock to be valid. */ + while ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0U) + { + } + + s_Ext_Clk_Freq = iFreq; + + return kStatus_Success; +} + +/*! + * @brief Initialize the external reference clock to given frequency. + * param iFreq : Desired frequency (must be equal to exact rate in Hz) + * return returns success or fail status. + */ +status_t CLOCK_SetupExtRefClocking(uint32_t iFreq) +{ + + if (iFreq > 50000000U) + { + return kStatus_InvalidArgument; + } + + /* If configure register is locked, return error. */ + if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U) + { + return kStatus_ReadOnly; + } + + /* De-initializes the SCG SOSC */ + SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK; + + /* Select SOSC source (external reference clock)*/ + SCG0->SOSCCFG &= ~SCG_SOSCCFG_EREFS_MASK; + + /* Unlock SOSCCSR */ + SCG0->SOSCCSR &= ~SCG_SOSCCSR_LK_MASK; + + /* Enable SOSC clock monitor and Enable SOSC */ + SCG0->SOSCCSR |= (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCEN_MASK); + + /* Wait for SOSC clock to be valid. */ + while ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0U) + { + } + + s_Ext_Clk_Freq = iFreq; + + return kStatus_Success; +} + +/* Get IP Clk */ +/*! brief Return Frequency of selected clock + * return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName) +{ + uint32_t freq = 0U; + + switch (clockName) + { + case kCLOCK_MainClk: /* MAIN_CLK */ + freq = CLOCK_GetMainClk(); + break; + case kCLOCK_CoreSysClk: /* Core/system clock(CPU_CLK) */ + freq = CLOCK_GetCoreSysClkFreq(); + break; + case kCLOCK_SYSTEM_CLK: /* AHB clock */ + freq = CLOCK_GetCoreSysClkFreq(); + break; + case kCLOCK_BusClk: /* Bus clock (AHB clock) */ + freq = CLOCK_GetCoreSysClkFreq(); + break; + case kCLOCK_ExtClk: /* External Clock */ + freq = CLOCK_GetExtClkFreq(); + break; + case kCLOCK_FroHf: /* FROHF */ + freq = CLOCK_GetFroHfFreq(); + break; + case kCLOCK_FroHfDiv: /* Divided by FROHF */ + freq = CLOCK_GetFroHfFreq() / ((MRCC0->MRCC_FRO_HF_DIV_CLKDIV & 0xfU) + 1U); + break; + case kCLOCK_Clk48M: /* CLK48M */ + freq = CLOCK_GetClk48MFreq(); + break; + case kCLOCK_Fro12M: /* FRO12M */ + freq = CLOCK_GetFro12MFreq(); + break; + case kCLOCK_Clk1M: /* CLK1M */ + freq = CLOCK_GetClk1MFreq(); + break; + case kCLOCK_Fro16K: /* FRO16K */ + freq = CLOCK_GetFRO16KFreq(); + break; + case kCLOCK_Clk16K0: /* CLK16K[0] */ + freq = CLOCK_GetClk16KFreq(0); + break; + case kCLOCK_Clk16K1: /* CLK16K[1] */ + freq = CLOCK_GetClk16KFreq(1); + break; + case kCLOCK_SLOW_CLK: /* SYSTEM_CLK divided by 4 */ + freq = CLOCK_GetCoreSysClkFreq() >> 2; + break; + default: + freq = 0U; + break; + } + return freq; +} + +/* Get FRO 12M Clk */ +/*! brief Return Frequency of FRO 12MHz + * return Frequency of FRO 12MHz + */ +static uint32_t CLOCK_GetFro12MFreq(void) +{ + return ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRC_CLK_PERIPH_EN_MASK) != 0U) ? 12000000U : 0U; +} + +/* Get CLK 1M Clk */ +/*! brief Return Frequency of CLK 1MHz + * return Frequency of CLK 1MHz + */ +static uint32_t CLOCK_GetClk1MFreq(void) +{ + return 1000000U; +} + +/* Get HF FRO Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ +static uint32_t CLOCK_GetFroHfFreq(void) +{ + uint32_t freq; + + if (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK) == 0U) || + ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_FCLK_PERIPH_EN_SHIFT) == 0U)) + { + freq = 0U; + } + + switch ((SCG0->FIRCCFG & SCG_FIRCCFG_FREQ_SEL_MASK) >> SCG_FIRCCFG_FREQ_SEL_SHIFT) + { + case 0U: + freq = 36000000U; + break; + case 1U: + freq = 48000000U; + break; + case 2U: + freq = 48000000U; + break; + case 3U: + freq = 64000000U; + break; + case 4U: + freq = 72000000U; + break; + case 5U: + freq = 96000000U; + break; + case 6U: + freq = 144000000U; + break; + case 7U: + freq = 192000000U; + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/* Get CLK 48M Clk */ +/*! brief Return Frequency of CLK 48MHz + * return Frequency of CLK 48MHz + */ +static uint32_t CLOCK_GetClk48MFreq(void) +{ + return (((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK) != 0U) || + ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_SHIFT) == 0U)) ? + 48000000U : + 0U; +} + +/*! brief Return Frequency of FRO16K + * return Frequency of FRO_16K + */ +static uint32_t CLOCK_GetFRO16KFreq(void) +{ + return ((VBAT0->FROCTLA & VBAT_FROCTLA_FRO_EN_MASK) != 0U) ? 16000U : 0U; +} +/* Get CLK 16K Clk */ +/*! brief Return Frequency of CLK 16KHz + * return Frequency of CLK 16KHz + */ +static uint32_t CLOCK_GetClk16KFreq(uint8_t id) +{ + return (((VBAT0->FROCTLA & VBAT_FROCTLA_FRO_EN_MASK) != 0U) && + ((VBAT0->FROCLKE & VBAT_FROCLKE_CLKE((((uint32_t)id) << 1U))) != 0U)) ? + 16000U : + 0U; +} + +/* Get EXT OSC Clk */ +/*! brief Return Frequency of External Clock + * return Frequency of External Clock. If no external clock is used returns 0. + */ +static uint32_t CLOCK_GetExtClkFreq(void) +{ + return ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) != 0U) ? s_Ext_Clk_Freq : 0U; +} + +/* Get MAIN Clk */ +/*! brief Return Frequency of Core System + * return Frequency of Core System + */ +uint32_t CLOCK_GetMainClk(void) +{ + uint32_t freq = 0U; + + switch ((SCG0->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) + { + case 1U: + freq = CLOCK_GetExtClkFreq(); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetClk16KFreq(1); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/*! brief Return Frequency of core + * return Frequency of the core + */ +uint32_t CLOCK_GetCoreSysClkFreq(void) +{ + return CLOCK_GetMainClk() / ((SYSCON->AHBCLKDIV & 0xFFU) + 1U); +} + +/* Get I3C Clk */ +/*! brief Return Frequency of I3C Clock + * return Frequency of I3C Clock + */ +uint32_t CLOCK_GetI3CFClkFreq(void) +{ + uint32_t freq = 0U; + uint32_t clksel = (MRCC0->MRCC_I3C0_FCLK_CLKSEL); + uint32_t clkdiv = (MRCC0->MRCC_I3C0_FCLK_CLKDIV); + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq() / ((MRCC0->MRCC_FRO_HF_DIV_CLKDIV & 0xfU) + 1U); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/* Get CTimer Clk */ +/*! brief Return Frequency of CTimer functional Clock + * return Frequency of CTimer functional Clock + */ +uint32_t CLOCK_GetCTimerClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t clksel = 0U; + uint32_t clkdiv = 0U; + + switch (id) + { + case 0U: + clksel = MRCC0->MRCC_CTIMER0_CLKSEL; + clkdiv = MRCC0->MRCC_CTIMER0_CLKDIV; + break; + case 1U: + clksel = MRCC0->MRCC_CTIMER1_CLKSEL; + clkdiv = MRCC0->MRCC_CTIMER1_CLKDIV; + break; + case 2U: + clksel = MRCC0->MRCC_CTIMER2_CLKSEL; + clkdiv = MRCC0->MRCC_CTIMER2_CLKDIV; + break; + case 3U: + clksel = MRCC0->MRCC_CTIMER3_CLKSEL; + clkdiv = MRCC0->MRCC_CTIMER3_CLKDIV; + break; + case 4U: + clksel = MRCC0->MRCC_CTIMER4_CLKSEL; + clkdiv = MRCC0->MRCC_CTIMER4_CLKDIV; + break; + default: + clksel = MRCC0->MRCC_CTIMER0_CLKSEL; + clkdiv = MRCC0->MRCC_CTIMER0_CLKDIV; + break; + } + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 1U: + freq = CLOCK_GetFroHfFreq(); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 4U: + freq = CLOCK_GetClk16KFreq(1); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/* Get LPI2C Clk */ +/*! brief Return Frequency of LPI2C functional Clock + * return Frequency of LPI2C functional Clock + */ +uint32_t CLOCK_GetLpi2cClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + uint32_t clksel = 0U; + uint32_t clkdiv = 0U; + + switch (id) + { + case 0U: + clksel = MRCC0->MRCC_LPI2C0_CLKSEL; + clkdiv = MRCC0->MRCC_LPI2C0_CLKDIV; + break; + case 1U: + clksel = MRCC0->MRCC_LPI2C1_CLKSEL; + clkdiv = MRCC0->MRCC_LPI2C1_CLKDIV; + break; + case 2U: + clksel = MRCC0->MRCC_LPI2C2_CLKSEL; + clkdiv = MRCC0->MRCC_LPI2C2_CLKDIV; + break; + case 3U: + clksel = MRCC0->MRCC_LPI2C3_CLKSEL; + clkdiv = MRCC0->MRCC_LPI2C3_CLKDIV; + break; + default: + clksel = MRCC0->MRCC_LPI2C0_CLKSEL; + clkdiv = MRCC0->MRCC_LPI2C0_CLKDIV; + break; + } + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq() / ((MRCC0->MRCC_FRO_HF_DIV_CLKDIV & 0xfU) + 1U); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of LPSPI Clock + * return Frequency of LPSPI Clock + */ +uint32_t CLOCK_GetLpspiClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t clksel = (0U == id) ? (MRCC0->MRCC_LPSPI0_CLKSEL) : (MRCC0->MRCC_LPSPI1_CLKSEL); + uint32_t clkdiv = (0U == id) ? (MRCC0->MRCC_LPSPI0_CLKDIV) : (MRCC0->MRCC_LPSPI1_CLKDIV); + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq() / ((MRCC0->MRCC_FRO_HF_DIV_CLKDIV & 0xfU) + 1U); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of LPUART Clock + * return Frequency of LPUART Clock + */ +uint32_t CLOCK_GetLpuartClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t clksel = 0U; + uint32_t clkdiv = 0U; + + switch (id) + { + case 0U: + clksel = MRCC0->MRCC_LPUART0_CLKSEL; + clkdiv = MRCC0->MRCC_LPUART0_CLKDIV; + break; + case 1U: + clksel = MRCC0->MRCC_LPUART1_CLKSEL; + clkdiv = MRCC0->MRCC_LPUART1_CLKDIV; + break; + case 2U: + clksel = MRCC0->MRCC_LPUART2_CLKSEL; + clkdiv = MRCC0->MRCC_LPUART2_CLKDIV; + break; + case 3U: + clksel = MRCC0->MRCC_LPUART3_CLKSEL; + clkdiv = MRCC0->MRCC_LPUART3_CLKDIV; + break; + case 4U: + clksel = MRCC0->MRCC_LPUART4_CLKSEL; + clkdiv = MRCC0->MRCC_LPUART4_CLKDIV; + break; + default: + clksel = MRCC0->MRCC_LPUART0_CLKSEL; + clkdiv = MRCC0->MRCC_LPUART0_CLKDIV; + break; + } + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq() / ((MRCC0->MRCC_FRO_HF_DIV_CLKDIV & 0xfU) + 1U); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 4U: + freq = CLOCK_GetClk16KFreq(1); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of LPTMR Clock + * return Frequency of LPTMR Clock + */ +uint32_t CLOCK_GetLptmrClkFreq(void) +{ + uint32_t freq = 0U; + uint32_t clksel = (MRCC0->MRCC_LPTMR0_CLKSEL); + uint32_t clkdiv = (MRCC0->MRCC_LPTMR0_CLKDIV); + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq() / ((MRCC0->MRCC_FRO_HF_DIV_CLKDIV & 0xfU) + 1U); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of OSTIMER + * return Frequency of OSTIMER Clock + */ +uint32_t CLOCK_GetOstimerClkFreq(void) +{ + uint32_t freq = 0U; + uint32_t clksel = (MRCC0->MRCC_OSTIMER0_CLKSEL); + + switch (clksel) + { + case 0U: + freq = CLOCK_GetClk16KFreq(1); + break; + case 2U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/*! brief Return Frequency of Adc Clock + * return Frequency of Adc. + */ +uint32_t CLOCK_GetAdcClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + + uint32_t clksel = (0U == id) ? (MRCC0->MRCC_ADC0_CLKSEL) : (MRCC0->MRCC_ADC1_CLKSEL); + uint32_t clkdiv = (0U == id) ? (MRCC0->MRCC_ADC0_CLKDIV) : (MRCC0->MRCC_ADC1_CLKDIV); + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 1U: + freq = CLOCK_GetFroHfFreq(); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of Dac Clock + * return Frequency of Dac. + */ +uint32_t CLOCK_GetDacClkFreq(void) +{ + uint32_t freq = 0U; + uint32_t clksel = (MRCC0->MRCC_DAC0_CLKSEL); + uint32_t clkdiv = (MRCC0->MRCC_DAC0_CLKDIV); + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 1U: + freq = CLOCK_GetFroHfFreq() / ((MRCC0->MRCC_FRO_HF_DIV_CLKDIV & 0xfU) + 1U); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of CMP Function Clock + * return Frequency of CMP Function. + */ +uint32_t CLOCK_GetCmpFClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t clksel = (0U == id) ? (MRCC0->MRCC_CMP0_RR_CLKSEL) : (MRCC0->MRCC_CMP1_RR_CLKSEL); + uint32_t clkdiv = (0U == id) ? (MRCC0->MRCC_CMP0_FUNC_CLKDIV) : (MRCC0->MRCC_CMP1_FUNC_CLKDIV); + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq() / ((MRCC0->MRCC_FRO_HF_DIV_CLKDIV & 0xfU) + 1U); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of CMP Round Robin Clock + * return Frequency of CMP Round Robin. + */ +uint32_t CLOCK_GetCmpRRClkFreq(uint32_t id) +{ + uint32_t freq = 0U; + uint32_t clksel = (0U == id) ? (MRCC0->MRCC_CMP0_RR_CLKSEL) : (MRCC0->MRCC_CMP1_RR_CLKSEL); + uint32_t clkdiv = (0U == id) ? (MRCC0->MRCC_CMP0_RR_CLKDIV) : (MRCC0->MRCC_CMP1_RR_CLKDIV); + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq() / ((MRCC0->MRCC_FRO_HF_DIV_CLKDIV & 0xfU) + 1U); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of Trace Clock + * return Frequency of Trace. + */ +uint32_t CLOCK_GetTraceClkFreq(void) +{ + uint32_t freq = 0U; + uint32_t clksel = (MRCC0->MRCC_DBG_TRACE_CLKSEL); + uint32_t clkdiv = (MRCC0->MRCC_DBG_TRACE_CLKDIV); + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetClk1MFreq(); + break; + case 2U: + freq = CLOCK_GetClk16KFreq(1); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of CLKOUT Clock + * return Frequency of CLKOUT. + */ +uint32_t CLOCK_GetClkoutClkFreq(void) +{ + uint32_t freq = 0U; + uint32_t clksel = (MRCC0->MRCC_CLKOUT_CLKSEL); + uint32_t clkdiv = (MRCC0->MRCC_CLKOUT_CLKDIV); + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 1U: + freq = CLOCK_GetFroHfFreq() / ((MRCC0->MRCC_FRO_HF_DIV_CLKDIV & 0xfU) + 1U); + break; + case 2U: + freq = CLOCK_GetExtClkFreq(); + break; + case 3U: + freq = CLOCK_GetClk16KFreq(1); + break; + case 6U: + freq = CLOCK_GetCoreSysClkFreq() >> 2; + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of Systick Clock + * return Frequency of Systick. + */ +uint32_t CLOCK_GetSystickClkFreq(void) +{ + uint32_t freq = 0U; + uint32_t clksel = (MRCC0->MRCC_SYSTICK_CLKSEL); + uint32_t clkdiv = (MRCC0->MRCC_SYSTICK_CLKDIV); + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetClk1MFreq(); + break; + case 2U: + freq = CLOCK_GetClk16KFreq(1); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of Systick Clock + * return Frequency of Systick. + */ +uint32_t CLOCK_GetWwdtClkFreq(void) +{ + uint32_t freq = 0U; + uint32_t clkdiv = (MRCC0->MRCC_WWDT0_CLKDIV); + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + freq = CLOCK_GetClk1MFreq(); + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of FLEXIO FCLK + * return Frequency of FLEXIO FCLK. + */ +uint32_t CLOCK_GetFlexioClkFreq(void) +{ + uint32_t freq = 0U; + + uint32_t clksel = MRCC0->MRCC_FLEXIO0_CLKSEL; + uint32_t clkdiv = MRCC0->MRCC_FLEXIO0_CLKDIV; + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 1U: + freq = CLOCK_GetFroHfFreq(); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + case 5U: + freq = CLOCK_GetClk1MFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/*! brief Return Frequency of FlexCAN FCLK + * return Frequency of FlexCAN FCLK. + */ +uint32_t CLOCK_GetFlexcanClkFreq(void) +{ + uint32_t freq = 0U; + + uint32_t clksel = MRCC0->MRCC_FLEXCAN0_CLKSEL; + uint32_t clkdiv = MRCC0->MRCC_FLEXCAN0_CLKDIV; + + if (true == CLOCK_IsDivHalt(clkdiv)) + { + return 0; + } + + switch (clksel) + { + case 2U: + freq = CLOCK_GetFroHfFreq() / ((MRCC0->MRCC_FRO_HF_DIV_CLKDIV & 0xfU) + 1U); + break; + case 3U: + freq = CLOCK_GetExtClkFreq(); + break; + default: + freq = 0U; + break; + } + + return freq / ((clkdiv & 0xFFU) + 1U); +} + +/** + * @brief Setup FROHF trim. + * @param config : FROHF trim value + * @return returns success or fail status. + */ +status_t CLOCK_FROHFTrimConfig(firc_trim_config_t config) +{ + SCG0->FIRCTCFG = SCG_FIRCTCFG_TRIMDIV(config.trimDiv) | SCG_FIRCTCFG_TRIMSRC(config.trimSrc); + + if (kSCG_FircTrimNonUpdate == config.trimMode) + { + SCG0->FIRCSTAT = SCG_FIRCSTAT_TRIMFINE(config.trimFine); + } + + /* Set trim mode. */ + SCG0->FIRCCSR = (uint32_t)config.trimMode; + + if ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK) == SCG_FIRCCSR_FIRCERR_MASK) + { + return (status_t)kStatus_Fail; + } + + return (status_t)kStatus_Success; +} + +/** + * @brief Setup FRO 12M trim. + * @param config : FRO 12M trim value + * @return returns success or fail status. + */ +status_t CLOCK_FRO12MTrimConfig(sirc_trim_config_t config) +{ + SCG0->SIRCTCFG = SCG_SIRCTCFG_TRIMDIV(config.trimDiv) | SCG_SIRCTCFG_TRIMSRC(config.trimSrc); + + if (kSCG_SircTrimNonUpdate == config.trimMode) + { + SCG0->SIRCSTAT = SCG_SIRCSTAT_CCOTRIM(config.cltrim); + SCG0->SIRCSTAT = SCG_SIRCSTAT_CCOTRIM(config.ccotrim); + } + + /* Set trim mode. */ + SCG0->SIRCCSR = (uint32_t)config.trimMode; + + if ((SCG0->SIRCCSR & SCG_SIRCCSR_SIRCERR_MASK) == SCG_SIRCCSR_SIRCERR_MASK) + { + return (status_t)kStatus_Fail; + } + + return (status_t)kStatus_Success; +} + +/*! + * @brief Sets the system OSC monitor mode. + * + * This function sets the system OSC monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetSysOscMonitorMode(scg_sosc_monitor_mode_t mode) +{ + uint32_t reg = SCG0->SOSCCSR; + + reg &= ~(SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCCMRE_MASK); + + reg |= (uint32_t)mode; + + SCG0->SOSCCSR = reg; +} + +/*! brief Enable USB FS clock. + * Enable USB Full Speed clock. + */ +bool CLOCK_EnableUsbfsClock(void) +{ + /* Enable USB clock */ + CLOCK_EnableClock(kCLOCK_GateUSB0); + + /* Enable FROHF with 48MHZ if it is disabled */ + if (0U == (SCG0->FIRCCSR & SCG_FIRCCSR_FIRCEN_MASK)) + { + if (kStatus_Success != CLOCK_SetupFROHFClocking(48000000U)) + { + return false; + } + } + + /* Enable CLK_48 MHz clock for peripheral use */ + SCG0->FIRCCSR |= SCG_FIRCCSR_FIRC_SCLK_PERIPH_EN_MASK; + + /* Use clk_48M for USB FS */ + CLOCK_AttachClk(kCLK_48M_to_USB0); + + return true; +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_clock.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_clock.h new file mode 100644 index 00000000000..2e43e7fbed8 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_clock.h @@ -0,0 +1,983 @@ +/* + * Copyright 2023, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 1.0.0. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/*@}*/ + +/*! @brief Configure whether driver controls clock + * + * When set to 0, peripheral drivers will enable clock in initialize function + * and disable clock in de-initialize function. When set to 1, peripheral + * driver will not control the clock, application could control the clock out of + * the driver. + * + * @note All drivers share this feature switcher. If it is set to 1, application + * should handle clock enable and disable for all drivers. + */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0U +#endif + +/* Definition for delay API in clock driver, users can redefine it to the real application. */ +#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (96000000U) +#endif + +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +/*------------------------------------------------------------------------------ + clock_ip_name_t definition: +------------------------------------------------------------------------------*/ +#define CLK_GATE_REG_OFFSET(value) (((uint32_t)(value)) >> 16U) +#define CLK_GATE_BIT_SHIFT(value) (((uint32_t)(value)) & 0x0000FFFFU) + +#define REG_PWM0SUBCTL (250U) +#define REG_PWM1SUBCTL (240U) + +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +typedef enum _clock_ip_name +{ + kCLOCK_InputMux = (0x0000U | (0U)), /*!< Clock gate name: INPUTMUX0 */ + kCLOCK_GateINPUTMUX0 = (0x0000U | (0U)), /*!< Clock gate name: INPUTMUX0 */ + kCLOCK_GateI3C0 = (0x0000U | (1U)), /*!< Clock gate name: I3C0 */ + kCLOCK_GateCTIMER0 = (0x0000U | (2U)), /*!< Clock gate name: CTIMER0 */ + kCLOCK_GateCTIMER1 = (0x0000U | (3U)), /*!< Clock gate name: CTIMER1 */ + kCLOCK_GateCTIMER2 = (0x0000U | (4U)), /*!< Clock gate name: CTIMER2 */ + kCLOCK_GateCTIMER3 = (0x0000U | (5U)), /*!< Clock gate name: CTIMER3 */ + kCLOCK_GateCTIMER4 = (0x0000U | (6U)), /*!< Clock gate name: CTIMER4 */ + kCLOCK_GateFREQME = (0x0000U | (7U)), /*!< Clock gate name: FREQME */ + kCLOCK_GateUTICK0 = (0x0000U | (8U)), /*!< Clock gate name: UTICK0 */ + kCLOCK_GateWWDT0 = (0x0000U | (9U)), /*!< Clock gate name: WWDT0 */ + kCLOCK_GateDMA = (0x0000U | (10U)), /*!< Clock gate name: DMA */ + kCLOCK_GateAOI0 = (0x0000U | (11U)), /*!< Clock gate name: AOI0 */ + kCLOCK_GateCRC0 = (0x0000U | (12U)), /*!< Clock gate name: CRC0 */ + kCLOCK_Crc0 = (0x0000U | (12U)), /*!< Clock gate name: CRC0 */ + kCLOCK_GateEIM0 = (0x0000U | (13U)), /*!< Clock gate name: EIM0 */ + kCLOCK_GateERM0 = (0x0000U | (14U)), /*!< Clock gate name: ERM0 */ + kCLOCK_GateFMC = (0x0000U | (15U)), /*!< Clock gate name: FMC */ + kCLOCK_GateAOI1 = (0x0000U | (16U)), /*!< Clock gate name: AOI1 */ + kCLOCK_GateFLEXIO0 = (0x0000U | (17U)), /*!< Clock gate name: FLEXIO0 */ + kCLOCK_GateLPI2C0 = (0x0000U | (18U)), /*!< Clock gate name: LPI2C0 */ + kCLOCK_GateLPI2C1 = (0x0000U | (19U)), /*!< Clock gate name: LPI2C1 */ + kCLOCK_GateLPSPI0 = (0x0000U | (20U)), /*!< Clock gate name: LPSPI0 */ + kCLOCK_GateLPSPI1 = (0x0000U | (21U)), /*!< Clock gate name: LPSPI1 */ + kCLOCK_GateLPUART0 = (0x0000U | (22U)), /*!< Clock gate name: LPUART0 */ + kCLOCK_GateLPUART1 = (0x0000U | (23U)), /*!< Clock gate name: LPUART1 */ + kCLOCK_GateLPUART2 = (0x0000U | (24U)), /*!< Clock gate name: LPUART2 */ + kCLOCK_GateLPUART3 = (0x0000U | (25U)), /*!< Clock gate name: LPUART3 */ + kCLOCK_GateLPUART4 = (0x0000U | (26U)), /*!< Clock gate name: LPUART4 */ + kCLOCK_GateUSB0 = (0x0000U | (27U)), /*!< Clock gate name: USB0 */ + kCLOCK_GateQDC0 = (0x0000U | (28U)), /*!< Clock gate name: QDC0 */ + kCLOCK_GateQDC1 = (0x0000U | (29U)), /*!< Clock gate name: QDC1 */ + kCLOCK_GateFLEXPWM0 = (0x0000U | (30U)), /*!< Clock gate name: FLEXPWM0 */ + kCLOCK_GateFLEXPWM1 = (0x0000U | (31U)), /*!< Clock gate name: FLEXPWM1 */ + kCLOCK_GateOSTIMER0 = ((0x10U << 16U) | (0U)), /*!< Clock gate name: OSTIMER0 */ + kCLOCK_GateADC0 = ((0x10U << 16U) | (1U)), /*!< Clock gate name: ADC0 */ + kCLOCK_GateADC1 = ((0x10U << 16U) | (2U)), /*!< Clock gate name: ADC1 */ + kCLOCK_GateCMP0 = ((0x10U << 16U) | (3U)), /*!< Clock gate name: CMP0 */ + kCLOCK_GateCMP1 = ((0x10U << 16U) | (4U)), /*!< Clock gate name: CMP1 */ + kCLOCK_GateDAC0 = ((0x10U << 16U) | (5U)), /*!< Clock gate name: DAC0 */ + kCLOCK_GateOPAMP0 = ((0x10U << 16U) | (6U)), /*!< Clock gate name: OPAMP0 */ + kCLOCK_GatePORT0 = ((0x10U << 16U) | (7U)), /*!< Clock gate name: PORT0 */ + kCLOCK_GatePORT1 = ((0x10U << 16U) | (8U)), /*!< Clock gate name: PORT1 */ + kCLOCK_GatePORT2 = ((0x10U << 16U) | (9U)), /*!< Clock gate name: PORT2 */ + kCLOCK_GatePORT3 = ((0x10U << 16U) | (10U)), /*!< Clock gate name: PORT3 */ + kCLOCK_GatePORT4 = ((0x10U << 16U) | (11U)), /*!< Clock gate name: PORT4 */ + kCLOCK_GateFLEXCAN0 = ((0x10U << 16U) | (12U)), /*!< Clock gate name: FLEXCAN0 */ + kCLOCK_GateLPI2C2 = ((0x10U << 16U) | (13U)), /*!< Clock gate name: LPI2C2 */ + kCLOCK_GateLPI2C3 = ((0x10U << 16U) | (14U)), /*!< Clock gate name: LPI2C3 */ + kCLOCK_GateMTR = ((0x10U << 16U) | (16U)), /*!< Clock gate name: MTR */ + kCLOCK_GateTCU = ((0x10U << 16U) | (17U)), /*!< Clock gate name: TCU */ + kCLOCK_GateRAMA = ((0x10U << 16U) | (18U)), /*!< Clock gate name: RAMA */ + kCLOCK_GateRAMB = ((0x10U << 16U) | (19U)), /*!< Clock gate name: RAMB */ + kCLOCK_GateGPIO0 = ((0x10U << 16U) | (20U)), /*!< Clock gate name: GPIO0 */ + kCLOCK_GateGPIO1 = ((0x10U << 16U) | (21U)), /*!< Clock gate name: GPIO1 */ + kCLOCK_GateGPIO2 = ((0x10U << 16U) | (22U)), /*!< Clock gate name: GPIO2 */ + kCLOCK_GateGPIO3 = ((0x10U << 16U) | (23U)), /*!< Clock gate name: GPIO3 */ + kCLOCK_GateGPIO4 = ((0x10U << 16U) | (24U)), /*!< Clock gate name: GPIO4 */ + kCLOCK_GateROMC = ((0x10U << 16U) | (25U)), /*!< Clock gate name: ROMC */ + kCLOCK_GatePWM0SM0 = ((REG_PWM0SUBCTL << 16U) | (0U)), /*!< Clock gate name: FlexPWM0 SM0 */ + kCLOCK_GatePWM0SM1 = ((REG_PWM0SUBCTL << 16U) | (1U)), /*!< Clock gate name: FlexPWM0 SM1 */ + kCLOCK_GatePWM0SM2 = ((REG_PWM0SUBCTL << 16U) | (2U)), /*!< Clock gate name: FlexPWM0 SM2 */ + kCLOCK_GatePWM1SM0 = ((REG_PWM1SUBCTL << 16U) | (0U)), /*!< Clock gate name: FlexPWM1 SM0 */ + kCLOCK_GatePWM1SM1 = ((REG_PWM1SUBCTL << 16U) | (1U)), /*!< Clock gate name: FlexPWM1 SM1 */ + kCLOCK_GatePWM1SM2 = ((REG_PWM1SUBCTL << 16U) | (2U)), /*!< Clock gate name: FlexPWM1 SM2 */ + kCLOCK_GateNotAvail = (0xFFFFFFFFU), /**< Clock gate name: None */ +} clock_ip_name_t; + +/*! @brief Clock ip name array for AOI. */ +#define AOI_CLOCKS \ + { \ + kCLOCK_GateAOI0, kCLOCK_GateAOI1 \ + } +/*! @brief Clock ip name array for CRC. */ +#define CRC_CLOCKS \ + { \ + kCLOCK_GateCRC0 \ + } +/*! @brief Clock ip name array for CTIMER. */ +#define CTIMER_CLOCKS \ + { \ + kCLOCK_GateCTIMER0, kCLOCK_GateCTIMER1, kCLOCK_GateCTIMER2, kCLOCK_GateCTIMER3, kCLOCK_GateCTIMER4 \ + } +/*! @brief Clock ip name array for DAC. */ +#define LPDAC_CLOCKS \ + { \ + kCLOCK_GateDAC0 \ + } +/*! @brief Clock ip name array for DMA. */ +#define DMA_CLOCKS \ + { \ + kCLOCK_GateDMA \ + } +/*! @brief Clock gate name array for EDMA. */ +#define EDMA_CLOCKS \ + { \ + kCLOCK_GateDMA \ + } +/*! @brief Clock ip name array for ERM. */ +#define ERM_CLOCKS \ + { \ + kCLOCK_GateERM0 \ + } +/*! @brief Clock ip name array for EIM. */ +#define EIM_CLOCKS \ + { \ + kCLOCK_GateEIM0 \ + } +/*! @brief Clock ip name array for FLEXCAN. */ +#define FLEXCAN_CLOCKS \ + { \ + kCLOCK_GateFLEXCAN0 \ + } +/*! @brief Clock ip name array for FLEXIO. */ +#define FLEXIO_CLOCKS \ + { \ + kCLOCK_GateFLEXIO0 \ + } +/*! @brief Clock ip name array for FREQME. */ +#define FREQME_CLOCKS \ + { \ + kCLOCK_GateFREQME \ + } +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_GateGPIO0, kCLOCK_GateGPIO1, kCLOCK_GateGPIO2, kCLOCK_GateGPIO3, kCLOCK_GateGPIO4 \ + } +/*! @brief Clock ip name array for I3C */ +#define I3C_CLOCKS \ + { \ + kCLOCK_GateI3C0 \ + } +/*! @brief Clock ip name array for INPUTMUX. */ +#define INPUTMUX_CLOCKS \ + { \ + kCLOCK_GateINPUTMUX0 \ + } +/*! @brief Clock ip name array for GPIO. */ +#define LPCMP_CLOCKS \ + { \ + kCLOCK_GateCMP0, kCLOCK_GateCMP1 \ + } +/*! @brief Clock ip name array for LPADC. */ +#define LPADC_CLOCKS \ + { \ + kCLOCK_GateADC0, kCLOCK_GateADC1 \ + } +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_GateLPUART0, kCLOCK_GateLPUART1, kCLOCK_GateLPUART2, kCLOCK_GateLPUART3, kCLOCK_GateLPUART4 \ + } +/*! @brief Clock ip name array for LPI2C. */ +#define LPI2C_CLOCKS \ + { \ + kCLOCK_GateLPI2C0, kCLOCK_GateLPI2C1, kCLOCK_GateLPI2C2, kCLOCK_GateLPI2C3 \ + } +/*! @brief Clock ip name array for LSPI. */ +#define LPSPI_CLOCKS \ + { \ + kCLOCK_GateLPSPI0, kCLOCK_GateLPSPI1 \ + } +/*! @brief Clock ip name array for MTR. */ +#define MTR_CLOCKS \ + { \ + kCLOCK_GateMTR \ + } +/*! @brief Clock ip name array for OSTIMER. */ +#define OSTIMER_CLOCKS \ + { \ + kCLOCK_GateOSTIMER0 \ + } +/*! @brief Clock ip name array for DAC. */ +#define OPAMP_CLOCKS \ + { \ + kCLOCK_GateOPAMP0 \ + } +/*! @brief Clock ip name array for PWM. */ +#define PWM_CLOCKS \ + { \ + {kCLOCK_GatePWM0SM0, kCLOCK_GatePWM0SM1, kCLOCK_GatePWM0SM2}, \ + { \ + kCLOCK_GatePWM1SM0, kCLOCK_GatePWM1SM1, kCLOCK_GatePWM1SM2 \ + } \ + } +/*! @brief Clock ip name array for QDC. */ +#define QDC_CLOCKS \ + { \ + kCLOCK_GateQDC0, kCLOCK_GateQDC1 \ + } +/*! @brief Clock ip name array for UTICK. */ +#define UTICK_CLOCKS \ + { \ + kCLOCK_GateUTICK0 \ + } +/*! @brief Clock ip name array for WWDT. */ +#define WWDT_CLOCKS \ + { \ + kCLOCK_GateWWDT0 \ + } + +/*! @brief Peripherals clock source definition. */ +#define BUS_CLK kCLOCK_BusClk + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_MainClk, /*!< MAIN_CLK */ + kCLOCK_CoreSysClk, /*!< Core/system clock(CPU_CLK) */ + kCLOCK_SYSTEM_CLK, /*!< AHB clock */ + kCLOCK_BusClk, /*!< Bus clock (AHB clock) */ + kCLOCK_ExtClk, /*!< External Clock */ + kCLOCK_FroHf, /*!< FRO192 */ + kCLOCK_FroHfDiv, /*!< Divided by FRO192 */ + kCLOCK_Clk48M, /*!< CLK48M */ + kCLOCK_Fro12M, /*!< FRO12M */ + kCLOCK_Clk1M, /*!< CLK1M */ + kCLOCK_Fro16K, /*!< FRO16K */ + kCLOCK_Clk16K0, /*!< CLK16K[0] */ + kCLOCK_Clk16K1, /*!< CLK16K[1] */ + kCLOCK_SLOW_CLK, /*!< SYSTEM_CLK divided by 4 */ +} clock_name_t; + +/*! @brief Clock Mux Switches + * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable + * starting from LSB upwards + * + * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]* + * + */ + +#define CLK_ATTACH_REG_OFFSET(value) (((uint32_t)(value)) >> 16U) +#define CLK_ATTACH_CLK_SEL(value) (((uint32_t)(value)) & 0x0000FFFFU) +#define CLK_ATTACH_MUX(reg, sel) ((((uint32_t)(reg)) << 16U) | (sel)) + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_select_name +{ + kCLOCK_SelI3C0_FCLK = (0x0A0), /*MRCC_GLB_CC0_SET)) + reg_offset); + + if (clk == kCLOCK_GateNotAvail) + { + return; + } + + /* Unlock clock configuration */ + SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK; + + if (reg_offset == REG_PWM0SUBCTL) + { + SYSCON->PWM0SUBCTL |= (1UL << bit_shift); + MRCC0->MRCC_GLB_CC0_SET = MRCC_MRCC_GLB_CC0_FLEXPWM0_MASK; + } + else if (reg_offset == REG_PWM1SUBCTL) + { + SYSCON->PWM1SUBCTL |= (1UL << bit_shift); + MRCC0->MRCC_GLB_CC0_SET = MRCC_MRCC_GLB_CC0_FLEXPWM1_MASK; + } + else + { + *pClkCtrl = (1UL << bit_shift); + } + + /* Freeze clock configuration */ + SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK; +} + +/** + * @brief Disable the clock for specific IP. + * @param clk : Clock to be Disabled. + * @return Nothing + */ +static inline void CLOCK_DisableClock(clock_ip_name_t clk) +{ + uint32_t reg_offset = CLK_GATE_REG_OFFSET(clk); + uint32_t bit_shift = CLK_GATE_BIT_SHIFT(clk); + volatile uint32_t *pClkCtrl = (volatile uint32_t *)((uint32_t)(&(MRCC0->MRCC_GLB_CC0_CLR)) + reg_offset); + + if (clk == kCLOCK_GateNotAvail) + { + return; + } + + /* Unlock clock configuration */ + SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK; + + if (reg_offset == REG_PWM0SUBCTL) + { + SYSCON->PWM0SUBCTL &= ~(1UL << bit_shift); + + if (0U == (SYSCON->PWM0SUBCTL & 0xFU)) + { + MRCC0->MRCC_GLB_CC0_CLR = MRCC_MRCC_GLB_CC0_FLEXPWM0_MASK; + } + } + else if (reg_offset == REG_PWM1SUBCTL) + { + SYSCON->PWM1SUBCTL &= ~(1UL << bit_shift); + + if (0U == (SYSCON->PWM1SUBCTL & 0xFU)) + { + MRCC0->MRCC_GLB_CC0_CLR = MRCC_MRCC_GLB_CC0_FLEXPWM1_MASK; + } + } + else + { + *pClkCtrl = (1UL << bit_shift); + } + + /* Freeze clock configuration */ + SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK; +} + +/** + * @brief Configure the clock selection muxes. + * @param connection : Clock to be configured. + * @return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection); + +/** + * @brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * @param connection : Clock attach id to get. + * @return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t connection); + +/** + * @brief Set the clock select value. + * This fuction set the peripheral clock select value. + * @param sel_name : Clock select. + * @param value : value to be set. + */ +void CLOCK_SetClockSelect(clock_select_name_t sel_name, uint32_t value); + +/** + * @brief Get the clock select value. + * This fuction get the peripheral clock select value. + * @param sel_name : Clock select. + * @return Clock source value. + */ +uint32_t CLOCK_GetClockSelect(clock_select_name_t sel_name); + +/** + * @brief Setup peripheral clock dividers. + * @param div_name : Clock divider name + * @param value : Value to be divided + * @return Nothing + */ +void CLOCK_SetClockDiv(clock_div_name_t div_name, uint32_t value); + +/** + * @brief Get peripheral clock dividers. + * @param div_name : Clock divider name + * @return peripheral clock dividers + */ +uint32_t CLOCK_GetClockDiv(clock_div_name_t div_name); + +/** + * @brief Halt peripheral clock dividers. + * @param div_name : Clock divider name + * @return Nothing + */ +void CLOCK_HaltClockDiv(clock_div_name_t div_name); + +/** + * @brief Initialize the FROHF to given frequency (48,64,96,192). + * This function turns on FIRC and select the given frequency as the source of fro_hf + * @param iFreq : Desired frequency. + * @return returns success or fail status. + */ +status_t CLOCK_SetupFROHFClocking(uint32_t iFreq); + +/** + * @brief Initialize the FRO12M. + * This function turns on FRO12M. + * @return returns success or fail status. + */ +status_t CLOCK_SetupFRO12MClocking(void); + +/** + * @brief Initialize the FRO16K. + * This function turns on FRO16K. + * @param clk_16k_enable_mask: 0-3 + * 0b00: disable both clk_16k0 and clk_16k1 + * 0b01: only enable clk_16k0 + * 0b10: only enable clk_16k1 + * 0b11: enable both clk_16k0 and clk_16k1 + * @return returns success or fail status. + */ +status_t CLOCK_SetupFRO16KClocking(uint8_t clk_16k_enable_mask); + +/** + * @brief Initialize the external osc clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtClocking(uint32_t iFreq); + +/** + * @brief Initialize the external reference clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupExtRefClocking(uint32_t iFreq); + +/*! @brief Return Frequency of selected clock + * @return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName); + +/*! @brief Return Frequency of core + * @return Frequency of the core + */ +uint32_t CLOCK_GetCoreSysClkFreq(void); + +/*! @brief Return Frequency of I3C FCLK + * @return Frequency of I3C FCLK. + */ +uint32_t CLOCK_GetI3CFClkFreq(void); + +/*! @brief Return Frequency of CTimer functional Clock + * @return Frequency of CTimer functional Clock + */ +uint32_t CLOCK_GetCTimerClkFreq(uint32_t id); + +/*! @brief Return Frequency of LPI2C0 functional Clock + * @return Frequency of LPI2C0 functional Clock + */ +uint32_t CLOCK_GetLpi2cClkFreq(uint32_t id); + +/*! @brief Return Frequency of LPSPI functional Clock + * @return Frequency of LPSPI functional Clock + */ +uint32_t CLOCK_GetLpspiClkFreq(uint32_t id); + +/*! @brief Return Frequency of LPUART functional Clock + * @return Frequency of LPUART functional Clock + */ +uint32_t CLOCK_GetLpuartClkFreq(uint32_t id); + +/*! @brief Return Frequency of LPTMR functional Clock + * @return Frequency of LPTMR functional Clock + */ +uint32_t CLOCK_GetLptmrClkFreq(void); + +/*! @brief Return Frequency of OSTIMER + * @return Frequency of OSTIMER Clock + */ +uint32_t CLOCK_GetOstimerClkFreq(void); + +/*! @brief Return Frequency of Adc Clock + * @return Frequency of Adc. + */ +uint32_t CLOCK_GetAdcClkFreq(uint32_t id); + +/*! @brief Return Frequency of Dac Clock + * @return Frequency of Dac. + */ +uint32_t CLOCK_GetDacClkFreq(void); + +/*! @brief Return Frequency of CMP Function Clock + * @return Frequency of CMP Function. + */ +uint32_t CLOCK_GetCmpFClkFreq(uint32_t id); + +/*! @brief Return Frequency of CMP Round Robin Clock + * @return Frequency of CMP Round Robin. + */ +uint32_t CLOCK_GetCmpRRClkFreq(uint32_t id); + +/*! @brief Return Frequency of Trace Clock + * @return Frequency of Trace. + */ +uint32_t CLOCK_GetTraceClkFreq(void); + +/*! @brief Return Frequency of CLKOUT Clock + * @return Frequency of CLKOUT. + */ +uint32_t CLOCK_GetClkoutClkFreq(void); + +/*! @brief Return Frequency of Systick Clock + * @return Frequency of Systick. + */ +uint32_t CLOCK_GetSystickClkFreq(void); + +/*! brief Return Frequency of Systick Clock + * return Frequency of Systick. + */ +uint32_t CLOCK_GetWwdtClkFreq(void); + +/*! @brief Return Frequency of FLEXIO FCLK + * @return Frequency of FLEXIO FCLK. + */ +uint32_t CLOCK_GetFlexioClkFreq(void); + +/*! @brief Return Frequency of FlexCAN FCLK + * @return Frequency of FlexCAN FCLK. + */ +uint32_t CLOCK_GetFlexcanClkFreq(void); + +/** + * @brief Setup FROHF trim. + * @param config : FROHF trim value + * @return returns success or fail status. + */ +status_t CLOCK_FROHFTrimConfig(firc_trim_config_t config); + +/** + * @brief Setup FRO 12M trim. + * @param config : FRO 12M trim value + * @return returns success or fail status. + */ +status_t CLOCK_FRO12MTrimConfig(sirc_trim_config_t config); + +/*! + * @brief Sets the system OSC monitor mode. + * + * This function sets the system OSC monitor mode. The mode can be disabled, + * it can generate an interrupt when the error is disabled, or reset when the error is detected. + * + * @param mode Monitor mode to set. + */ +void CLOCK_SetSysOscMonitorMode(scg_sosc_monitor_mode_t mode); + +/*! brief Enable USB FS clock. + * Enable USB Full Speed clock. + */ +bool CLOCK_EnableUsbfsClock(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_CLOCK_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_cmc.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_cmc.c new file mode 100644 index 00000000000..4e388d9e73a --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_cmc.c @@ -0,0 +1,310 @@ +/* + * Copyright 2022-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_cmc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.mcx_cmc" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +static uint32_t g_savedPrimask; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Sets clock mode. + * + * This function configs the amount of clock gating when the core asserts + * Sleeping due to WFI, WFE or SLEEPONEXIT. + * + * param base CMC peripheral base address. + * param mode System clock mode. + */ +void CMC_SetClockMode(CMC_Type *base, cmc_clock_mode_t mode) +{ + uint32_t reg; + + reg = base->CKCTRL; + reg &= ~CMC_CKCTRL_CKMODE_MASK; + reg |= CMC_CKCTRL_CKMODE((mode)); + base->CKCTRL = reg; +} + +/*! + * brief Configures all power mode protection settings. + * + * This function configures the power mode protection settings for + * supported power modes. This should be done before setting the lowPower mode + * for each power doamin. + * + * The allowed lowpower modes are passed as bit map. For example, to allow + * Sleep and DeepSleep, use CMC_SetPowerModeProtection(CMC_base, kCMC_AllowSleepMode|kCMC_AllowDeepSleepMode). + * To allow all low power modes, use CMC_SetPowerModeProtection(CMC_base, kCMC_AllowAllLowPowerModes). + * + * param base CMC peripheral base address. + * param allowedModes Bitmaps of the allowed power modes. + */ +void CMC_SetPowerModeProtection(CMC_Type *base, uint32_t allowedModes) +{ + uint32_t reg; + + reg = base->PMPROT; + reg &= ~0xFUL; + reg |= allowedModes; + + base->PMPROT = reg; +} + +/*! + * brief Configure reset pin. + * + * This function configures reset pin. When enabled, the low power filter is enabled in both + * Active and Low power modes, the reset filter is only enabled in Active mode. When both filers + * are enabled, they operate in series. + * + * param base CMC peripheral base address. + * param config Pointer to the reset pin config structure. + */ +void CMC_ConfigResetPin(CMC_Type *base, const cmc_reset_pin_config_t *config) +{ + assert(config != NULL); + + uint32_t reg = base->RPC; + + if (config->lowpowerFilterEnable) + { + reg |= CMC_RPC_LPFEN_MASK; + } + else + { + reg &= ~CMC_RPC_LPFEN_MASK; + } + if (config->resetFilterEnable) + { + reg |= (CMC_RPC_FILTEN_MASK | CMC_RPC_FILTCFG(config->resetFilterWidth)); + } + else + { + reg &= ~(CMC_RPC_FILTEN_MASK | CMC_RPC_FILTCFG_MASK); + } + base->RPC = reg; +} + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) +/*! + * brief Power off the selected system SRAM always. + * + * This function powers off the selected system SRAM always. The SRAM arrays should + * not be accessed while they are shut down. SRAM array contents are not retained + * if they are powered off. + * + * param base CMC peripheral base address. + * param mask Bitmap of the SRAM arrays to be powered off all modes. + */ +void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask) +{ + uint32_t reg = base->SRAMDIS[0]; + uint32_t maskToSet = mask & ((uint32_t)kCMC_AllSramArrays); + + reg &= ~((uint32_t)kCMC_AllSramArrays); + reg |= CMC_SRAMDIS_DIS(maskToSet); + base->SRAMDIS[0] = reg; +} + +/*! + * brief Power off the selected system SRAm during low power mode only. + * + * This function powers off the selected system SRAM only during low power mode. + * SRAM array contents are not retained if they are power off. + * + * param base CMC peripheral base address. + * param mask Bitmap of the SRAM arrays to be power off during low power mode only. + */ +void CMC_PowerOffSRAMLowPowerOnly(CMC_Type *base, uint32_t mask) +{ + uint32_t reg = base->SRAMRET[0]; + uint32_t maskToSet = mask & ((uint32_t)kCMC_AllSramArrays); + + reg &= ~((uint32_t)kCMC_AllSramArrays); + reg |= CMC_SRAMRET_RET(maskToSet); + base->SRAMRET[0] = reg; +} +#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */ + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) && FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) +/*! + * brief Configs the low power mode of the on-chip flash memory. + * + * This function configs the low power mode of the on-chip flash memory. + * + * param base CMC peripheral base address. + * param doze true: Flash is disabled while core is sleeping + * false: No effect. + * param disable true: Flash memory is placed in low power state. + * false: No effect. + */ +void CMC_ConfigFlashMode(CMC_Type *base, bool doze, bool disable) +{ + uint32_t reg = 0UL; + + reg |= (disable ? CMC_FLASHCR_FLASHDIS(1U) : CMC_FLASHCR_FLASHDIS(0U)) | + (doze ? CMC_FLASHCR_FLASHDOZE(1U) : CMC_FLASHCR_FLASHDOZE(0U)); + base->FLASHCR = reg; +} +#else +/*! + * brief Configs the low power mode of the on-chip flash memory. + * + * This function config the low power mode of the on-chip flash memory. + * + * param base CMC peripheral base address. + * param wake + * true - Flash will exit low power state during the flash memory accesses. + * false - No effect. + * param doze + * true - Flash is disabled while core is sleeping + * false - No effect. + * param disable + * true - Flash memory is placed in low power state. + * false - No effect. + */ +void CMC_ConfigFlashMode(CMC_Type *base, bool wake, bool doze, bool disable) +{ + uint32_t reg = 0UL; + + reg |= (disable ? CMC_FLASHCR_FLASHDIS(1U) : CMC_FLASHCR_FLASHDIS(0U)) | + (doze ? CMC_FLASHCR_FLASHDOZE(1U) : CMC_FLASHCR_FLASHDOZE(0U)) | + (wake ? CMC_FLASHCR_FLASHWAKE(1U) : CMC_FLASHCR_FLASHWAKE(0U)); + base->FLASHCR = reg; +} +#endif /* FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE */ + +/*! + * brief Prepares to enter stop modes. + * + * This function should be called before entering low power modes. + * + */ +void CMC_PreEnterLowPowerMode(void) +{ + g_savedPrimask = DisableGlobalIRQ(); + __ISB(); +} + +/*! + * brief Recovers after wake up from stop modes. + * + * This function should be called after waking up from low power modes. + * This function should be used with CMC_PreEnterLowPowerMode() + * + */ +void CMC_PostExitLowPowerMode(void) +{ + EnableGlobalIRQ(g_savedPrimask); + __ISB(); +} + +/*! + * brief Configs the entry into the same low power mode for each power domains. + * + * This function provides the feature to entry into the same low power mode for each power + * domains. Before invoking this function, please ensure the selected power mode have been allowed. + * + * param base CMC peripheral base address. + * param lowPowerMode The low power mode to be entered. See @ref cmc_low_power_mode_t for the details. + * + */ +void CMC_GlobalEnterLowPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode) +{ + /* Note: unlock the CKCTRL register if this API will be reinvoked later. */ + CMC_SetClockMode(base, kCMC_GateAllSystemClocksEnterLowPowerMode); + CMC_SetGlobalPowerMode(base, lowPowerMode); + /* Before executing WFI instruction read back the last register to + * ensure all registers writes have completed. */ + (void)base->GPMCTRL; + /* Set the core into DeepSleep mode. */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __DSB(); + __WFI(); + __ISB(); +} + +/*! + * brief Configs the entry into different low power modes for each of the power domains. + * + * This function provides the feature to entry into different low power modes for + * each power domains. Before invoking this function please ensure the selected + * modes are allowed. + * + * param base CMC peripheral base address. + * param base config Pointer to the cmc_power_domain_config_t structure. + */ +void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *config) +{ + assert(config != NULL); + +#if (CMC_PMCTRL_COUNT > 1U) + /* The WAKE domain must never be configured to a lower power mode compared with main power mode. */ + assert(config->wake_domain <= config->main_domain); +#endif /* (CMC_PMCTRL_COUNT > 1U) */ + + if (config->clock_mode < kCMC_GateAllSystemClocksEnterLowPowerMode) + { + /* In This case the power domain doesn't need to be placed in low power state. */ + /* Note: unlock the register if this API will be reinvoked later. */ + CMC_SetClockMode(base, config->clock_mode); + + CMC_SetMAINPowerMode(base, kCMC_ActiveOrSleepMode); +#if (CMC_PMCTRL_COUNT > 1U) + CMC_SetWAKEPowerMode(base, kCMC_ActiveOrSleepMode); +#endif /* (CMC_PMCTRL_COUNT > 1U) */ + + /* Before executing WFI instruction read back the last register to + * ensure all registers writes have completed. */ + (void)base->CKCTRL; + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __DSB(); + __WFI(); + __ISB(); + } + else + { + /* Note: unlock the register if this API will be reinvoked later. */ + CMC_SetClockMode(base, kCMC_GateAllSystemClocksEnterLowPowerMode); + CMC_SetMAINPowerMode(base, config->main_domain); +#if (CMC_PMCTRL_COUNT > 1U) + CMC_SetWAKEPowerMode(base, config->wake_domain); +#endif /* (CMC_PMCTRL_COUNT > 1U) */ + + /* Before execute WFI instruction read back the last register to + * ensure all registers writes have completed. */ +#if (CMC_PMCTRL_COUNT > 1U) + if ((CMC_GetWAKEPowerMode(base) == config->wake_domain) && (CMC_GetMAINPowerMode(base) == config->main_domain)) + { +#endif /* (CMC_PMCTRL_COUNT > 1U) */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + __DSB(); + __WFI(); + __ISB(); +#if (CMC_PMCTRL_COUNT > 1U) + } +#endif /* (CMC_PMCTRL_COUNT > 1U) */ + } +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_cmc.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_cmc.h new file mode 100644 index 00000000000..6dbe8e974bd --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_cmc.h @@ -0,0 +1,929 @@ +/* + * Copyright 2022-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_CMC_H_ +#define FSL_CMC_H_ +#include "fsl_common.h" + +/*! + * @addtogroup mcx_cmc + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief CMC driver version 2.2.2. */ +#define FSL_CMC_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) +/* @} */ + +/*! + * @brief CMC power mode Protection enumeration. + */ +enum _cmc_power_mode_protection +{ + kCMC_AllowDeepSleepMode = 0x1UL, /*!< Allow Deep Sleep mode. */ + kCMC_AllowPowerDownMode = 0x2UL, /*!< Allow Power Down mode. */ + kCMC_AllowDeepPowerDownMode = 0x8UL, /*!< Allow Deep Power Down mode. */ + kCMC_AllowAllLowPowerModes = 0xFUL, /*!< Allow Deep Sleep, Power Down, Deep Power Down modes. */ +}; + +/*! + * @brief Wake up sources from the previous low power mode entry. + * + * @note #kCMC_WakeupFromUsbFs, #kCMC_WakeupFromITRC, #kCMC_WakeupFromCpu1 are not supported in MCXA family. + */ +enum _cmc_wakeup_sources +{ + kCMC_WakeupFromResetInterruptOrPowerDown = + CMC_CKSTAT_WAKEUP(1U << 0U), /*!< Wakeup source is reset interrupt, or wake up from Deep Power Down. */ + kCMC_WakeupFromDebugReuqest = CMC_CKSTAT_WAKEUP(1U << 1U), /*!< Wakeup source is debug request. */ + kCMC_WakeupFromInterrupt = CMC_CKSTAT_WAKEUP(1U << 2U), /*!< Wakeup source is interrupt. */ + kCMC_WakeupFromDMAWakeup = CMC_CKSTAT_WAKEUP(1U << 3U), /*!< Wakeup source is DMA Wakeup. */ + kCMC_WakeupFromWUURequest = CMC_CKSTAT_WAKEUP(1U << 4U), /*!< Wakeup source is WUU request. */ + kCMC_WakeupFromUsbFs = CMC_CKSTAT_WAKEUP(1U << 5U), /*!< Wakeup source is USBFS(USB0). */ + kCMC_WakeupFromITRC = CMC_CKSTAT_WAKEUP(1U << 6U), /*!< Wakeup source is ITRC. */ + kCMC_WakeupFromCpu1 = CMC_CKSTAT_WAKEUP(1U << 7U), /*!< Wakeup source is CPU1. */ +}; + +/*! + * @brief System Reset Interrupt enable enumeration. + */ +enum _cmc_system_reset_interrupt_enable +{ + kCMC_PinResetInterruptEnable = CMC_SRIE_PIN_MASK, /*!< Pin Reset interrupt enable. */ + kCMC_DAPResetInterruptEnable = CMC_SRIE_DAP_MASK, /*!< DAP Reset interrupt enable. */ + kCMC_LowPowerAcknowledgeTimeoutResetInterruptEnable = CMC_SRIE_LPACK_MASK, /*!< Low Power Acknowledge Timeout + Reset interrupt enable. */ + kCMC_WindowedWatchdog0ResetInterruptEnable = CMC_SRIE_WWDT0_MASK, /*!< Windowed Watchdog 0 reset + interrupt enable. */ + kCMC_SoftwareResetInterruptEnable = CMC_SRIE_SW_MASK, /*!< Software Reset interrupt enable. */ + kCMC_LockupResetInterruptEnable = CMC_SRIE_LOCKUP_MASK, /*!< Lockup Reset interrupt enable. */ +#if defined(CMC_SRIE_CPU1_MASK) + kCMC_Cpu1ResetInterruptEnable = CMC_SRIE_CPU1_MASK, /*!< CPU1 Reset interrupt enable. */ +#endif /* CMC_SRIE_CPU1_MASK */ +#if defined(CMC_SRIE_ADVC_MASK) + kCMC_AdvcResetInterruptEnable = CMC_SRIE_ADVC_MASK, /*!< ADVC Reset interrupt enable. */ +#endif /* CMC_SRIE_ADVC_MASK */ +#if defined(CMC_SRIE_VBAT_MASK) + kCMC_VBATResetInterruptEnable = CMC_SRIE_VBAT_MASK, /*!< VBAT reset interrupt enable. */ +#endif /* CMC_SRIE_VBAT_MASK */ +#if defined(CMC_SRIE_WWDT1_MASK) + kCMC_WindowedWatchdog1ResetInterruptEnable = CMC_SRIE_WWDT1_MASK, /*!< Windowed Watchdog 1 reset + interrupt enable. */ +#endif /* CMC_SRIE_WWDT1_MASK */ + kCMC_CodeWatchDog0ResetInterruptEnable = CMC_SRIE_CDOG0_MASK, /*!< Code watchdog 0 reset interrupt enable. */ +#if defined(CMC_SRIE_CDOG1_MASK) + kCMC_CodeWatchDog1ResetInterruptEnable = CMC_SRIE_CDOG1_MASK, /*!< Code watchdog 1 reset interrupt enable. */ +#endif /* CMC_SRIE_CDOG1_MASK */ +}; + +/*! + * @brief CMC System Reset Interrupt Status flag. + */ +enum _cmc_system_reset_interrupt_flag +{ + kCMC_PinResetInterruptFlag = CMC_SRIF_PIN_MASK, /*!< Pin Reset interrupt flag. */ + kCMC_DAPResetInterruptFlag = CMC_SRIF_DAP_MASK, /*!< DAP Reset interrupt flag. */ + kCMC_LowPowerAcknowledgeTimeoutResetFlag = CMC_SRIF_LPACK_MASK, /*!< Low Power Acknowledge + Timeout Reset interrupt flag. */ + kCMC_WindowedWatchdog0ResetInterruptFlag = CMC_SRIF_WWDT0_MASK, /*!< Windowned Watchdog 0 Reset interrupt flag. */ + kCMC_SoftwareResetInterruptFlag = CMC_SRIF_SW_MASK, /*!< Software Reset interrupt flag. */ + kCMC_LockupResetInterruptFlag = CMC_SRIF_LOCKUP_MASK, /*!< Lock up Reset interrupt flag. */ +#if defined(CMC_SRIF_CPU1_MASK) + kCMC_Cpu1ResetInterruptFlag = CMC_SRIF_CPU1_MASK, /*!< CPU1 Reset interrupt flag. */ +#endif /* CMC_SRIF_CPU1_MASK */ +#if defined(CMC_SRIF_ADVC_MASK) + kCMC_AdvcResetInterruptFlag = CMC_SRIF_ADVC_MASK, /*!< ADVC Reset interrupt flag. */ +#endif /* CMC_SRIF_ADVC_MASK */ +#if defined(CMC_SRIF_VBAT_MASK) + kCMC_VbatResetInterruptFlag = CMC_SRIF_VBAT_MASK, /*!< VBAT system reset interrupt flag. */ +#endif /* CMC_SRIF_VBAT_MASK */ +#if defined(CMC_SRIF_WWDT1_MASK) + kCMC_WindowedWatchdog1ResetInterruptFlag = CMC_SRIF_WWDT1_MASK, /*!< Windowned Watchdog 1 Reset interrupt flag. */ +#endif /* CMC_SRIF_WWDT1_MASK */ + kCMC_CodeWatchdog0ResetInterruptFlag = CMC_SRIF_CDOG0_MASK, /*!< Code watchdog0 reset interrupt flag. */ +#if defined(CMC_SRIF_CDOG1_MASK) + kCMC_CodeWatchdog1ResetInterruptFlag = CMC_SRIF_CDOG1_MASK, /*!< Code watchdog1 reset interrupt flag. */ +#endif /* CMC_SRIF_CDOG1_MASK */ +}; + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) +/*! + * @brief CMC System SRAM arrays low power mode enable enumeration. + */ +enum _cmc_system_sram_arrays +{ + kCMC_RAMX0 = 1UL << 0UL, /*!< Used to control RAMX0. */ + kCMC_RAMX1 = 1UL << 1UL, /*!< Used to control RAMX1. */ + kCMC_RAMX2 = 1UL << 2UL, /*!< Used to control RAMX2. */ + kCMC_RAMB = 1UL << 3UL, /*!< Used to control RAMB. */ + kCMC_RAMC0 = 1UL << 4UL, /*!< Used to control RAMC0. */ + kCMC_RAMC1 = 1UL << 5UL, /*!< Used to control RAMC1. */ + kCMC_RAMD0 = 1UL << 6UL, /*!< Used to control RAMD0. */ + kCMC_RAMD1 = 1UL << 7UL, /*!< Used to control RAMD1. */ + kCMC_RAME0 = 1UL << 8UL, /*!< Used to control RAME0. */ + kCMC_RAME1 = 1UL << 9UL, /*!< Used to control RAME1. */ + kCMC_RAMF0 = 1UL << 10UL, /*!< Used to control RAMF0. */ + kCMC_RAMF1 = 1UL << 11UL, /*!< Used to control RAMF1. */ + kCMC_RAMG0_RAMG1 = 1UL << 12UL, /*!< Used to control RAMG0 and RAMG1. */ + kCMC_RAMG2_RAMG3 = 1UL << 13UL, /*!< Used to control RAMG2 and RAMG3. */ + kCMC_RAMH0_RAMH1 = 1UL << 14UL, /*!< Used to control RAMH0 and RAMH1. */ + kCMC_LPCAC = 1UL << 24UL, /*!< Used to control LPCAC. */ + kCMC_DMA0_DMA1_PKC = 1UL << 25UL, /*!< Used to control DMA0, DMA1 and PKC. */ + kCMC_USB0 = 1UL << 26UL, /*!< Used to control USB0. */ + kCMC_PQ = 1UL << 27UL, /*!< Used to control PQ. */ + kCMC_CAN0_CAN1_ENET_USB1 = 1UL << 28UL, /*!< Used to control CAN0, CAN1, ENET, USB1. */ + kCMC_FlexSPI = 1UL << 29UL, /*!< Used to control FlexSPI. */ + + kCMC_AllSramArrays = (kCMC_RAMX0 | kCMC_RAMX1 | kCMC_RAMX2 | kCMC_RAMB | kCMC_RAMC0 | kCMC_RAMC1 | kCMC_RAMD0 | + kCMC_RAMD1 | kCMC_RAME0 | kCMC_RAME1 | kCMC_RAMF0 | kCMC_RAMF1 | kCMC_RAMG0_RAMG1 | + kCMC_RAMG2_RAMG3 | kCMC_RAMH0_RAMH1 | kCMC_LPCAC | kCMC_DMA0_DMA1_PKC | kCMC_USB0 | kCMC_PQ | + kCMC_CAN0_CAN1_ENET_USB1 | kCMC_FlexSPI), /*!< Mask of all System SRAM arrays. */ +}; +#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */ + +/*! + * @brief System reset sources enumeration. + */ +enum _cmc_system_reset_sources +{ + kCMC_WakeUpReset = CMC_SRS_WAKEUP_MASK, /*!< The reset caused by a wakeup from Power Down or + Deep Power Down mode. */ + kCMC_PORReset = CMC_SRS_POR_MASK, /*!< The reset caused by power on reset detection logic. */ + kCMC_VDReset = CMC_SRS_VD_MASK, /*!< The reset caused by an LVD or HVD. */ + kCMC_WarmReset = CMC_SRS_WARM_MASK, /*!< The last reset source is a warm reset source. */ + kCMC_FatalReset = CMC_SRS_FATAL_MASK, /*!< The last reset source is a fatal reset source. */ + kCMC_PinReset = CMC_SRS_PIN_MASK, /*!< The reset caused by the RESET_b pin. */ + kCMC_DAPReset = CMC_SRS_DAP_MASK, /*!< The reset caused by a reset request from the Debug Access port. */ + kCMC_ResetTimeout = CMC_SRS_RSTACK_MASK, /*!< The reset caused by a timeout or other error condition in the system + reset generation. */ + kCMC_LowPowerAcknowledgeTimeoutReset = CMC_SRS_LPACK_MASK, /*!< The reset caused by a timeout in + low power mode entry logic. */ + kCMC_SCGReset = CMC_SRS_SCG_MASK, /*!< The reset caused by a loss of clock or loss of lock event in the SCG. */ + kCMC_WindowedWatchdog0Reset = CMC_SRS_WWDT0_MASK, /*!< The reset caused by the Windowed WatchDog 0 timeout. */ + kCMC_SoftwareReset = CMC_SRS_SW_MASK, /*!< The reset caused by a software reset request. */ + kCMC_LockUoReset = CMC_SRS_LOCKUP_MASK, /*!< The reset caused by the ARM core indication of a LOCKUP event. */ +#if defined(CMC_SRS_CPU1_MASK) + kCMC_Cpu1Reset = CMC_SRS_CPU1_MASK, /*!< The reset caused by a CPU1 system reset. */ +#endif /* CMC_SRS_CPU1_MASK */ +#if defined(CMC_SRS_ADVC_MASK) + kCMC_AdvcReset = CMC_SRS_ADVC_MASK, /*!< The reset caused by ADVC critical reset. */ +#endif /* CMC_SRS_ADVC_MASK */ +#if defined(CMC_SRS_VBAT_MASK) + kCMC_VbatReset = CMC_SRS_VBAT_MASK, /*!< The reset caused by a VBAT POR. */ +#endif /* CMC_SRS_VBAT_MASK */ +#if defined(CMC_SRS_WWDT1_MASK) + kCMC_WindowedWatchdog1Reset = CMC_SRS_WWDT1_MASK, /*!< The reset caused by the Windowed WatchDog 1 timeout. */ +#endif /* CMC_SRS_WWDT1_MASK */ + kCMC_CodeWatchDog0Reset = CMC_SRS_CDOG0_MASK, /*!< The reset caused by the code watchdog0 fault. */ +#if defined(CMC_SRS_CDOG1_MASK) + kCMC_CodeWatchDog1Reset = CMC_SRS_CDOG1_MASK, /*!< The reset caused by the code watchdog1 fault. */ +#endif /* CMC_SRS_CDOG1_MASK */ + kCMC_JTAGSystemReset = CMC_SRS_JTAG_MASK, /*!< The reset caused by a JTAG system reset request. */ +#if defined(CMC_SRS_SECVIO_MASK) + kCMC_SecurityViolationReset = CMC_SRS_SECVIO_MASK, /*!< The reset caused by a Security Violation logic. */ +#endif /* CMC_SRS_SECVIO_MASK */ +#if defined(CMC_SRS_TAMPER_MASK) + kCMC_TapmerReset = CMC_SRS_TAMPER_MASK, /*!< The reset caused by the tamper detection logic. */ +#endif /* CMC_SRS_TAMPER_MASK */ +}; + +/*! + * @brief Indicate the core clock was gated. + */ +typedef enum _cmc_core_clock_gate_status +{ + kCMC_CoreClockNotGated = 0U, /*!< Core clock not gated. */ + kCMC_CoreClockGated = 1U /*!< Core clock was gated due to low power mode entry. */ +} cmc_core_clock_gate_status_t; + +/*! + * @brief CMC clock mode enumeration. + */ +typedef enum _cmc_clock_mode +{ + kCMC_GateNoneClock = 0x00U, /*!< No clock gating. */ + kCMC_GateCoreClock = 0x01U, /*!< Gate Core clock. */ + kCMC_GateCorePlatformClock = 0x03U, /*!< Gate Core clock and platform clock. */ + kCMC_GateAllSystemClocks = 0x07U, /*!< Gate all System clocks, without getting core entering into low power mode. */ + kCMC_GateAllSystemClocksEnterLowPowerMode = 0x0FU /*!< Gate all System clocks, with core + entering into low power mode. */ +} cmc_clock_mode_t; + +/*! + * @brief CMC power mode enumeration. + */ +typedef enum _cmc_low_power_mode +{ + kCMC_ActiveOrSleepMode = 0x0U, /*!< Select Active/Sleep mode. */ + kCMC_DeepSleepMode = 0x1U, /*!< Select Deep Sleep mode when a core executes WFI or WFE instruction. */ + kCMC_PowerDownMode = 0x3U, /*!< Select Power Down mode when a core executes WFI or WFE instruction. */ + kCMC_DeepPowerDown = 0xFU, /*!< Select Deep Power Down mode when a core executes WFI or WFE instruction. */ +} cmc_low_power_mode_t; + +/*! + * @brief CMC reset pin configuration. + */ +typedef struct _cmc_reset_pin_config +{ + bool lowpowerFilterEnable; /*!< Low Power Filter enable. */ + bool resetFilterEnable; /*!< Reset Filter enable. */ + uint8_t resetFilterWidth; /*!< Width of the Reset Filter. */ +} cmc_reset_pin_config_t; + +/*! + * @brief power mode configuration for each power domain. + */ +typedef struct _cmc_power_domain_config +{ + cmc_clock_mode_t clock_mode; /*!< Clock mode for each power domain. */ + cmc_low_power_mode_t main_domain; /*!< The low power mode of the MAIN power domain. */ +#if (CMC_PMCTRL_COUNT > 1U) + cmc_low_power_mode_t wake_domain; /*!< The low power mode of the WAKE power domain. */ +#endif /* (CMC_PMCTRL_COUNT > 1U) */ +} cmc_power_domain_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name CLOCK mode configuration. + * @{ + */ + +/*! + * @brief Sets clock mode. + * + * This function configs the amount of clock gating when the core asserts + * Sleeping due to WFI, WFE or SLEEPONEXIT. + * + * @param base CMC peripheral base address. + * @param mode System clock mode. + */ +void CMC_SetClockMode(CMC_Type *base, cmc_clock_mode_t mode); + +/*! + * @brief Locks the clock mode setting. + * + * After invoking this function, any clock mode setting will be blocked. + * + * @param base CMC peripheral base address. + */ +static inline void CMC_LockClockModeSetting(CMC_Type *base) +{ + base->CKCTRL |= CMC_CKCTRL_LOCK_MASK; +} + +/* @} */ + +/*! + * @name Gets/Clears the Clock Mode, the wake up source, the Reset source. + * @{ + */ + +/*! + * @brief Gets the core clock gated status. + * + * This function get the status to indicate whether the core clock is gated. + * The core clock gated status can be cleared by software. + * + * @param base CMC peripheral base address. + * @return The status to indicate whether the core clock is gated. + */ +static inline cmc_core_clock_gate_status_t CMC_GetCoreClockGatedStatus(CMC_Type *base) +{ + return (cmc_core_clock_gate_status_t)(uint32_t)((base->CKSTAT & CMC_CKSTAT_VALID_MASK) >> CMC_CKSTAT_VALID_SHIFT); +} + +/*! + * @brief Clears the core clock gated status. + * + * This function clear clock status flag by software. + * + * @param base CMC peripheral base address. + */ +static inline void CMC_ClearCoreClockGatedStatus(CMC_Type *base) +{ + base->CKSTAT |= CMC_CKSTAT_VALID_MASK; +} + +/*! + * @brief Gets the Wakeup Source. + * + * This function gets the Wakeup sources from the previous low power mode entry. + * + * @param base CMC peripheral base address. + * @return The Wakeup sources from the previous low power mode entry. See @ref _cmc_wakeup_sources for details. + */ +static inline uint8_t CMC_GetWakeupSource(CMC_Type *base) +{ + return ((uint8_t)((base->CKSTAT & CMC_CKSTAT_WAKEUP_MASK) >> CMC_CKSTAT_WAKEUP_SHIFT)); +} + +/*! + * @brief Gets the Clock mode. + * + * This function gets the clock mode of the previous low power mode entry. + * + * @param base CMC peripheral base address. + * @return The Low Power status. + */ +static inline cmc_clock_mode_t CMC_GetClockMode(CMC_Type *base) +{ + return (cmc_clock_mode_t)(uint32_t)((base->CKSTAT & CMC_CKSTAT_CKMODE_MASK) >> CMC_CKSTAT_CKMODE_SHIFT); +} + +/*! + * @brief Gets the System reset status. + * + * This function returns the system reset status. Those status + * updates on every MAIN Warm Reset to indicate the type/source + * of the most recent reset. + * + * @param base CMC peripheral base address. + * @return The most recent system reset status. See @ref _cmc_system_reset_sources for details. + */ +static inline uint32_t CMC_GetSystemResetStatus(CMC_Type *base) +{ + return base->SRS; +} + +/*! + * @brief Gets the sticky system reset status since the last WAKE Cold Reset. + * + * This function gets all source of system reset that have generated a + * system reset since the last WAKE Cold Reset, and that have not been + * cleared by software. + * + * @param base CMC peripheral base address. + * @return System reset status that have not been cleared by software. See @ref _cmc_system_reset_sources for details. + */ +static inline uint32_t CMC_GetStickySystemResetStatus(CMC_Type *base) +{ + return base->SSRS; +} + +/*! + * @brief Clears the sticky system reset status flags. + * + * @param base CMC peripheral base address. + * @param mask Bitmap of the sticky system reset status to be cleared. + */ +static inline void CMC_ClearStickySystemResetStatus(CMC_Type *base, uint32_t mask) +{ + base->SSRS = mask; +} + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG) && FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG) +/*! + * @brief Gets the number of reset sequences completed since the last Cold Reset. + * + * @param base CMC peripheral base address. + * @return The number of reset sequences. + */ +static inline uint8_t CMC_GetResetCount(CMC_Type *base) +{ + return (uint8_t)(base->RSTCNT & CMC_RSTCNT_COUNT_MASK); +} +#endif /* FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG */ + +/* @} */ + +/*! + * @name Power mode configuration. + * @{ + */ + +/*! + * @brief Configures all power mode protection settings. + * + * This function configures the power mode protection settings for + * supported power modes. This should be done before set the lowPower mode + * for each power doamin. + * + * The allowed lowpower modes are passed as bit map. For example, to allow + * Sleep and DeepSleep, use CMC_SetPowerModeProtection(CMC_base, kCMC_AllowSleepMode|kCMC_AllowDeepSleepMode). + * To allow all low power modes, use CMC_SetPowerModeProtection(CMC_base, kCMC_AllowAllLowPowerModes). + * + * @param base CMC peripheral base address. + * @param allowedModes Bitmaps of the allowed power modes. See @ref _cmc_power_mode_protection for details. + */ +void CMC_SetPowerModeProtection(CMC_Type *base, uint32_t allowedModes); + +/*! + * @brief Locks the power mode protection. + * + * This function locks the power mode protection. After invoking this function, + * any power mode protection setting will be ignored. + * + * @param base CMC peripheral base address. + */ +static inline void CMC_LockPowerModeProtectionSetting(CMC_Type *base) +{ + base->PMPROT |= CMC_PMPROT_LOCK_MASK; +} + +/*! + * @brief Config the same lowPower mode for all power domain. + * + * This function configures the same low power mode for MAIN power domian and WAKE power domain. + * + * @param base CMC peripheral base address. + * @param lowPowerMode The desired lowPower mode. See @ref cmc_low_power_mode_t for details. + */ +static inline void CMC_SetGlobalPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode) +{ + base->GPMCTRL = CMC_GPMCTRL_LPMODE((uint8_t)lowPowerMode); +} + +/*! + * @brief Configures entry into low power mode for the MAIN Power domain. + * + * This function configures the low power mode for the MAIN power domian, + * when the core executes WFI/WFE instruction. The available lowPower modes + * are defined in the @ref cmc_low_power_mode_t. + * + * @param base CMC peripheral base address. + * @param lowPowerMode The desired lowPower mode. See @ref cmc_low_power_mode_t for details. + * + */ +static inline void CMC_SetMAINPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode) +{ + base->PMCTRL[0] = CMC_PMCTRL_LPMODE((uint8_t)lowPowerMode); +} + +/*! + * @brief Gets the power mode of the MAIN Power domain. + * + * @param base CMC peripheral base address. + * @return The power mode of MAIN Power domain. See @ref cmc_low_power_mode_t for details. + */ +static inline cmc_low_power_mode_t CMC_GetMAINPowerMode(CMC_Type *base) +{ + return (cmc_low_power_mode_t)(uint32_t)(base->PMCTRL[0] & CMC_PMCTRL_LPMODE_MASK); +} + +#if (CMC_PMCTRL_COUNT > 1U) +/*! + * @brief Configure entry into low power mode for the WAKE Power domain. + * + * This function configures the low power mode for the WAKE power domian, + * when the core executes WFI/WFE instruction. The available lowPower mode + * are defined in the @ref cmc_low_power_mode_t. + * + * @note The lowPower Mode for the WAKE domain must not be configured to a + * lower power mode than any other power domain. + * + * @param base CMC peripheral base address. + * @param lowPowerMode The desired lowPower mode. See @ref cmc_low_power_mode_t for details. + * + */ +static inline void CMC_SetWAKEPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode) +{ + base->PMCTRL[1] = CMC_PMCTRL_LPMODE((uint8_t)lowPowerMode); +} + +/*! + * @brief Gets the power mode of the WAKE Power domain. + * + * @param base CMC peripheral base address. + * @return The power mode of WAKE Power domain. See @ref cmc_low_power_mode_t for details. + */ +static inline cmc_low_power_mode_t CMC_GetWAKEPowerMode(CMC_Type *base) +{ + return (cmc_low_power_mode_t)(uint32_t)(base->PMCTRL[1] & CMC_PMCTRL_LPMODE_MASK); +} +#endif /* CMC_PMCTRL_COUNT > 1U */ + +/* @} */ + +/*! + * @name Reset Pin configuration. + * @{ + */ + +/*! + * @brief Configure reset pin. + * + * This function configures reset pin. When enabled, the low power filter is enabled in both + * Active and Low power modes, the reset filter is only enabled in Active mode. When both filers + * are enabled, they operate in series. + * + * @param base CMC peripheral base address. + * @param config Pointer to the reset pin config structure. + */ +void CMC_ConfigResetPin(CMC_Type *base, const cmc_reset_pin_config_t *config); + +/* @} */ + +/*! + * @name System Reset Interrupts. + * @{ + */ + +/*! + * @brief Enable system reset interrupts. + * + * This function enables the system reset interrupts. The assertion of + * non-fatal warm reset can be delayed for 258 cycles of the 32K_CLK clock + * while an enabled interrupt is generated. Then Software can perform a graceful + * shutdown or abort the non-fatal warm reset provided the pending reset source is cleared + * by resetting the reset source and then clearing the pending flag. + * + * @param base CMC peripheral base address. + * @param mask System reset interrupts. See @ref _cmc_system_reset_interrupt_enable for details. + * + */ +static inline void CMC_EnableSystemResetInterrupt(CMC_Type *base, uint32_t mask) +{ + base->SRIE |= mask; +} + +/*! + * @brief Disable system reset interrupts. + * + * This function disables the system reset interrupts. + * + * @param base CMC peripheral base address. + * @param mask System reset interrupts. See @ref _cmc_system_reset_interrupt_enable for details. + */ +static inline void CMC_DisableSystemResetInterrupt(CMC_Type *base, uint32_t mask) +{ + base->SRIE &= (uint32_t)(~mask); +} + +/*! + * @brief Gets System Reset interrupt flags. + * + * This function returns the System reset interrupt flags. + * + * @param base CMC peripheral base address. + * @return System reset interrupt flags. See @ref _cmc_system_reset_interrupt_flag for details. + */ +static inline uint32_t CMC_GetSystemResetInterruptFlags(CMC_Type *base) +{ + return base->SRIF; +} + +/*! + * @brief Clears System Reset interrupt flags. + * + * This function clears system reset interrupt flags. The pending reset source + * can be cleared by resetting the source of the reset and then clearing the pending + * flags. + * + * @param base CMC peripheral base address. + * @param mask System Reset interrupt flags. See @ref _cmc_system_reset_interrupt_flag for details. + * + */ +static inline void CMC_ClearSystemResetInterruptFlags(CMC_Type *base, uint32_t mask) +{ + base->SRIF = mask; +} + +/* @} */ + +/*! + * @name Non Maskable Pin interrupt. + * @{ + */ + +/*! + * @brief Enable/Disable Non maskable Pin interrupt. + * + * @param base CMC peripheral base address. + * @param enable Enable or disable Non maskable pin interrupt. + * true - enable Non-maskable pin interrupt. + * false - disable Non-maskable pin interupt. + */ +static inline void CMC_EnableNonMaskablePinInterrupt(CMC_Type *base, bool enable) +{ + if (enable) + { + base->CORECTL |= CMC_CORECTL_NPIE_MASK; + } + else + { + base->CORECTL &= ~CMC_CORECTL_NPIE_MASK; + } +} + +/* @} */ + +/*! + * @name Boot Configuration. + * @{ + */ + +/*! + * @brief Gets the logic state of the ISPMODE_n pin. + * + * This function returns the logic state of the ISPMODE_n pin + * on the last negation of RESET_b pin. + * + * @param base CMC peripheral base address. + * @return The logic state of the ISPMODE_n pin on the last negation of RESET_b pin. + */ +static inline uint8_t CMC_GetISPMODEPinLogic(CMC_Type *base) +{ + return (uint8_t)((base->MR[0] & CMC_MR_ISPMODE_n_MASK) >> CMC_MR_ISPMODE_n_SHIFT); +} + +/*! + * @brief Clears ISPMODE_n pin state. + * + * @param base CMC peripheral base address. + */ +static inline void CMC_ClearISPMODEPinLogic(CMC_Type *base) +{ + base->MR[0] = CMC_MR_ISPMODE_n_MASK; +} + +/*! + * @brief Set the logic state of the BOOT_CONFIGn pin. + * + * This function force the logic state of the Boot_Confign pin to assert + * on next system reset. + * + * @param base CMC peripheral base address. + * @param assert Assert the corresponding pin or not. + * true - Assert corresponding pin on next system reset. + * false - No effect. + */ +static inline void CMC_ForceBootConfiguration(CMC_Type *base, bool assert) +{ + if (assert) + { + base->FM[0] |= CMC_FM_FORCECFG_MASK; + } + else + { + base->FM[0] &= ~CMC_FM_FORCECFG_MASK; + } +} + +/* @} */ + +/*! + * @name BootROM Status. + * @{ + */ + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_BSR_REG) && FSL_FEATURE_MCX_CMC_HAS_BSR_REG) +/*! + * @brief Gets the status information written by the BootROM. + * + * @param base CMC peripheral base address. + * @return The status information written by the BootROM. + */ +static inline uint32_t CMC_GetBootRomStatus(CMC_Type *base) +{ + return base->BSR; +} + +/*! + * @brief Sets the bootROM status value. + * + * @note This function is useful when result of CMC_CheckBootRomRegisterWrittable() is true. + * + * @param base CMC peripheral base address. + * @param stat The state value to set. + */ +static inline void CMC_SetBootRomStatus(CMC_Type *base, uint32_t statValue) +{ + base->BSR = CMC_BSR_STAT(statValue); +} +#endif /* FSL_FEATURE_MCX_CMC_HAS_BSR_REG */ + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_BLR_REG) && FSL_FEATURE_MCX_CMC_HAS_BLR_REG) +/*! + * @brief Check if BootROM status and lock registers is writtable. + * + * @param base CMC peripheral base address. + * @return The result of whether BootROM status and lock register is writtable. + * - \b true BootROM status and lock registers are writtable; + * - \b false BootROM status and lock registers are not writtable. + */ +static inline bool CMC_CheckBootRomRegisterWrittable(CMC_Type *base) +{ + return (base->BLR == 0x2UL); +} + +/*! + * @brief After invoking this function, BootROM status and lock registers cannot be written. + * + * @param base CMC peripheral base address. + */ +static inline void CMC_LockBootRomStatusWritten(CMC_Type *base) +{ + base->BLR = CMC_BLR_LOCK(0x5U); +} + +/*! + * @brief After invoking this function, BootROM status and lock register can be written.s + * + * @param base + */ +static inline void CMC_UnlockBootRomStatusWritten(CMC_Type *base) +{ + base->BLR = CMC_BLR_LOCK(0x2U); +} +#endif /* FSL_FEATURE_MCX_CMC_HAS_BLR_REG */ + +/* @} */ + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) +/*! + * @name System SRAM Configuration. + * @{ + */ + +/*! + * @brief Power off the selected system SRAM always. + * + * @note This function power off the selected system SRAM always. The SRAM arrays should + * not be accessed while they are shut down. SRAM array contents are not retained + * if they are powered off. + * + * @note Once invoked, the previous settings will be overwritten. + * + * @param base CMC peripheral base address. + * @param mask Bitmap of the SRAM arrays to be powered off all modes. + * See @ref _cmc_system_sram_arrays for details. + * Check Reference Manual for the SRAM region and mask bit relationship. + */ +void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask); + +/*! + * @brief Power on SRAM during all mode. + * + * @note Once invoked, the previous settings will be overwritten. + * + * @param base CMC peripheral base address. + * @param mask Bitmap of the SRAM arrays to be powered on all modes. + * See @ref _cmc_system_sram_arrays for details. + * Check Reference Manual for the SRAM region and mask bit relationship. + */ +static inline void CMC_PowerOnSRAMAllMode(CMC_Type *base, uint32_t mask) +{ + base->SRAMDIS[0] &= CMC_SRAMDIS_DIS((uint32_t)(~mask)); +} + +/*! + * @brief Power off the selected system SRAM during low power modes only. + * + * This function power off the selected system SRAM only during low power mode. + * SRAM array contents are not retained if they are power off. + * + * @param base CMC peripheral base address. + * @param mask Bitmap of the SRAM arrays to be power off during low power mode only. + * See @ref _cmc_system_sram_arrays for details. + * Check Reference Manual for the SRAM region and mask bit relationship. + */ +void CMC_PowerOffSRAMLowPowerOnly(CMC_Type *base, uint32_t mask); + +/*! + * @brief Power on the selected system SRAM during low power modes only. + * + * This function power on the selected system SRAM. The SRAM arrray contents are + * retained in low power modes. + * + * @param base CMC peripheral base address. + * @param mask Bitmap of the SRAM arrays to be power on during low power mode only. + * See @ref _cmc_system_sram_arrays for details. + * Check Reference Manual for the SRAM region and mask bit relationship. + */ +static inline void CMC_PowerOnSRAMLowPowerOnly(CMC_Type *base, uint32_t mask) +{ + base->SRAMRET[0] &= CMC_SRAMRET_RET((uint32_t)(~mask)); +} + +/* @} */ +#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */ + +/*! + * @name Flash Low Power Mode configuration. + * @{ + */ + +#if (defined(FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) && FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) +/*! + * @brief Configs the low power mode of the on-chip flash memory. + * + * This function configs the low power mode of the on-chip flash memory. + * + * @param base CMC peripheral base address. + * @param doze true: Flash is disabled while core is sleeping + * false: No effect. + * @param disable true: Flash memory is placed in low power state. + * false: No effect. + */ +void CMC_ConfigFlashMode(CMC_Type *base, bool doze, bool disable); +#else +/*! + * @brief Configs the low power mode of the on-chip flash memory. + * + * This function configs the low power mode of the on-chip flash memory. + * + * @param base CMC peripheral base address. + * @param wake true: Flash will exit low power state during the flash memory accesses. + * false: No effect. + * @param doze true: Flash is disabled while core is sleeping + * false: No effect. + * @param disable true: Flash memory is placed in low power state. + * false: No effect. + */ +void CMC_ConfigFlashMode(CMC_Type *base, bool wake, bool doze, bool disable); +#endif /* FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE */ +/* @} */ + +/*! + * @name Debug Configuration. + */ + +/*! + * @brief Enables/Disables debug Operation when the core sleep. + * + * This function configs what happens to debug when core sleeps. + * + * @param base CMC peripheral base address. + * @param enable Enable or disable Debug when Core is sleeping. + * true - Debug remains enabled when the core is sleeping. + * false - Debug is disabled when the core is sleeping. + */ +static inline void CMC_EnableDebugOperation(CMC_Type *base, bool enable) +{ + if (enable) + { + base->DBGCTL &= ~CMC_DBGCTL_SOD_MASK; + } + else + { + base->DBGCTL |= CMC_DBGCTL_SOD_MASK; + } +} + +/* @} */ + +/*! + * @name Low Power modes enter. + * @{ + */ +/*! + * @brief Prepares to enter low power modes. + * + * This function should be called before entering low power modes. + * + */ +void CMC_PreEnterLowPowerMode(void); + +/*! + * @brief Recovers after wake up from low power modes. + * + * This function should be called after wake up from low power modes. + * This function should be used with CMC_PreEnterLowPowerMode() + * + */ +void CMC_PostExitLowPowerMode(void); + +/*! + * @brief Configs the entry into the same low power mode for each power domains. + * + * This function provides the feature to entry into the same low power mode for each power + * domains. Before invoking this function, please ensure the selected power mode have been allowed. + * + * @param base CMC peripheral base address. + * @param lowPowerMode The low power mode to be entered. See @ref cmc_low_power_mode_t for the details. + * + */ +void CMC_GlobalEnterLowPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMode); + +/*! + * @brief Configs the entry into different low power modes for each power domains. + * + * This function provides the feature to entry into different low power modes for + * each power domains. Before invoking this function please ensure the selected + * modes are allowed. + * + * @param base CMC peripheral base address. + * @param config Pointer to the cmc_power_domain_config_t structure. + */ +void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *config); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ +#endif /* FSL_CMC_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_common.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_common.c new file mode 100644 index 00000000000..d3af9fdfc67 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_common.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" + +#define SDK_MEM_MAGIC_NUMBER 12345U + +typedef struct _mem_align_control_block +{ + uint16_t identifier; /*!< Identifier for the memory control block. */ + uint16_t offset; /*!< offset from aligned address to real address */ +} mem_align_cb_t; + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common" +#endif + +#if !((defined(__DSC__) && defined(__CW__))) +void *SDK_Malloc(size_t size, size_t alignbytes) +{ + mem_align_cb_t *p_cb = NULL; + uint32_t alignedsize; + + /* Check overflow. */ + alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes); + if (alignedsize < size) + { + return NULL; + } + + if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t)) + { + return NULL; + } + + alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t); + + union + { + void *pointer_value; + uintptr_t unsigned_value; + } p_align_addr, p_addr; + + p_addr.pointer_value = malloc((size_t)alignedsize); + + if (p_addr.pointer_value == NULL) + { + return NULL; + } + + p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes); + + p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U); + p_cb->identifier = SDK_MEM_MAGIC_NUMBER; + p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value); + + return p_align_addr.pointer_value; +} + +void SDK_Free(void *ptr) +{ + union + { + void *pointer_value; + uintptr_t unsigned_value; + } p_free; + p_free.pointer_value = ptr; + mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U); + + if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) + { + return; + } + + p_free.unsigned_value = p_free.unsigned_value - p_cb->offset; + + free(p_free.pointer_value); +} +#endif diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_common.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_common.h new file mode 100644 index 00000000000..e6d5cce7190 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_common.h @@ -0,0 +1,345 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_COMMON_H_ +#define FSL_COMMON_H_ + +#include +#include +#include +#include +#include + +#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__) +#include +#endif + +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Configurations + ******************************************************************************/ + +/*! @brief Macro to use the default weak IRQ handler in drivers. */ +#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100L) + (code))) + +/*! @brief Construct the version number for drivers. + * + * The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M) + * and 16-bit platforms(such as DSC). + * + * @verbatim + + | Unused || Major Version || Minor Version || Bug Fix | + 31 25 24 17 16 9 8 0 + + @endverbatim + */ +#define MAKE_VERSION(major, minor, bugfix) (((major)*65536L) + ((minor)*256L) + (bugfix)) + +/*! @name Driver version */ +/*! @{ */ +/*! @brief common driver version. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 4, 1)) +/*! @} */ + +/*! @name Debug console type definition. */ +/*! @{ */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */ +/*! @} */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ + kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ + kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ + kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ + kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ + kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ + kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ + kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ + kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ + kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/ + kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */ + kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */ + kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */ + kStatusGroup_VBAT = 107, /*!< Group number for VBAT status codes */ + kStatusGroup_XSPI = 108, /*!< Group number for XSPI status codes */ + kStatusGroup_PNGDEC = 109, /*!< Group number for PNGDEC status codes */ + kStatusGroup_JPEGDEC = 110, /*!< Group number for JPEGDEC status codes */ + + kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ + kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ + kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ + kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ + kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ + kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ + kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ + kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ + kStatusGroup_HAL_I2S = 129, /*!< Group number for HAL I2S status codes. */ + kStatusGroup_HAL_ADC_SENSOR = 130, /*!< Group number for HAL ADC SENSOR status codes. */ + kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ + kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ + kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ + kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ + kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ + kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ + kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ + kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ + kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ + kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ + kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ + kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */ + kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/ + kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */ + kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */ + kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */ + kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */ + kStatusGroup_MECC = 152, /*!< Group number for MECC status codes. */ + kStatusGroup_ENET_QOS = 153, /*!< Group number for ENET_QOS status codes. */ + kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */ + kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */ + kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */ + kStatusGroup_ELEMU = 157, /*!< Group number for ELEMU status codes. */ + kStatusGroup_QUEUEDSPI = 158, /*!< Group number for QSPI status codes. */ + kStatusGroup_POWER_MANAGER = 159, /*!< Group number for POWER_MANAGER status codes. */ + kStatusGroup_IPED = 160, /*!< Group number for IPED status codes. */ + kStatusGroup_ELS_PKC = 161, /*!< Group number for ELS PKC status codes. */ + kStatusGroup_CSS_PKC = 162, /*!< Group number for CSS PKC status codes. */ + kStatusGroup_HOSTIF = 163, /*!< Group number for HOSTIF status codes. */ + kStatusGroup_CLIF = 164, /*!< Group number for CLIF status codes. */ + kStatusGroup_BMA = 165, /*!< Group number for BMA status codes. */ + kStatusGroup_NETC = 166, /*!< Group number for NETC status codes. */ + kStatusGroup_ELE = 167, /*!< Group number for ELE status codes. */ + kStatusGroup_GLIKEY = 168, /*!< Group number for GLIKEY status codes. */ +}; + +/*! \public + * @brief Generic status return codes. + */ +enum +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */ + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */ + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */ + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */ + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */ + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */ + kStatus_NoTransferInProgress = + MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */ + kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */ + kStatus_NoData = + MAKE_STATUS(kStatusGroup_Generic, 8), /*!< Generic status for no data is found for the operation. */ +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +#ifdef __ZEPHYR__ +#include +#else +/*! + * @name Min/max macros + * @{ + */ +#if !defined(MIN) +/*! Computes the minimum of \a a and \a b. */ +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#if !defined(MAX) +/*! Computes the maximum of \a a and \a b. */ +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +/*! @} */ + +/*! @brief Computes the number of elements in an array. */ +#if !defined(ARRAY_SIZE) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif +#endif /* __ZEPHYR__ */ + +/*! @name UINT16_MAX/UINT32_MAX value */ +/*! @{ */ +#if !defined(UINT16_MAX) +/*! Max value of uint16_t type. */ +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +/*! Max value of uint32_t type. */ +#define UINT32_MAX ((uint32_t)-1) +#endif +/*! @} */ + +/*! Macro to get upper 32 bits of a 64-bit value */ +#if !defined(UINT64_H) +#define UINT64_H(X) ((uint32_t)((((uint64_t) (X)) >> 32U) & 0x0FFFFFFFFULL)) +#endif + +/*! Macro to get lower 32 bits of a 64-bit value */ +#if !defined(UINT64_L) +#define UINT64_L(X) ((uint32_t)(((uint64_t) (X)) & 0x0FFFFFFFFULL)) +#endif + +/*! + * @def SUPPRESS_FALL_THROUGH_WARNING() + * + * For switch case code block, if case section ends without "break;" statement, there wil be + * fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. + * To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each + * case section which misses "break;"statement. + */ +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) +#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough)) +#else +#define SUPPRESS_FALL_THROUGH_WARNING() +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +#if !((defined(__DSC__) && defined(__CW__))) +/*! + * @brief Allocate memory with given alignment and aligned size. + * + * This is provided to support the dynamically allocated memory + * used in cache-able region. + * @param size The length required to malloc. + * @param alignbytes The alignment size. + * @retval The allocated memory. + */ +void *SDK_Malloc(size_t size, size_t alignbytes); + +/*! + * @brief Free memory. + * + * @param ptr The memory to be release. + */ +void SDK_Free(void *ptr); +#endif + +/*! + * @brief Delay at least for some time. + * Please note that, this API uses while loop for delay, different run-time environments make the time not precise, + * if precise delay count was needed, please implement a new delay function with hardware timer. + * + * @param delayTime_us Delay time in unit of microsecond. + * @param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#if (defined(__DSC__) && defined(__CW__)) +#include "fsl_common_dsc.h" +#elif defined(__XTENSA__) +#include "fsl_common_dsp.h" +#else +#include "fsl_common_arm.h" +#endif + +#endif /* FSL_COMMON_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_common_arm.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_common_arm.c new file mode 100644 index 00000000000..e9f32aadf4a --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_common_arm.c @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021, 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common_arm" +#endif + +#ifndef __GIC_PRIO_BITS +#if defined(ENABLE_RAM_VECTOR_TABLE) +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) +{ +#ifdef __VECTOR_TABLE +#undef __VECTOR_TABLE +#endif + +/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$VECTOR_ROM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$ZI$$Limit[]; + +#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base +#define __VECTOR_RAM Image$$VECTOR_RAM$$Base +#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$VECTOR_RAM$$ZI$$Limit - (uint32_t)Image$$VECTOR_RAM$$Base)) +#elif defined(__ICCARM__) + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; + extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; + uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); +#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ + uint32_t n; + uint32_t ret; + uint32_t irqMaskValue; + + irqMaskValue = DisableGlobalIRQ(); + if (SCB->VTOR != (uint32_t)__VECTOR_RAM) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + SCB->VTOR = (uint32_t)__VECTOR_RAM; + } + + ret = __VECTOR_RAM[(int32_t)irq + 16]; + /* make sure the __VECTOR_RAM is noncachable */ + __VECTOR_RAM[(int32_t)irq + 16] = irqHandler; + + EnableGlobalIRQ(irqMaskValue); + + return ret; +} +#endif /* ENABLE_RAM_VECTOR_TABLE. */ +#endif /* __GIC_PRIO_BITS. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/* + * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, + * powerlib should be used instead of these functions. + */ +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) + +/* + * When the SYSCON STARTER registers are discontinuous, these functions are + * implemented in fsl_power.c. + */ +#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) + +void EnableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERSET[index] = 1UL << intNumber; + (void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */ +} + +void DisableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + (void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */ + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERCLR[index] = 1UL << intNumber; +} +#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ +#endif /* FSL_FEATURE_POWERLIB_EXTEND */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#if defined(DWT) +/* Use WDT. */ +void MSDK_EnableCpuCycleCounter(void) +{ + /* Make sure the DWT trace fucntion is enabled. */ + if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR)) + { + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + } + + /* CYCCNT not supported on this device. */ + assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk)); + + /* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */ + if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL)) + { + DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; + } +} + +uint32_t MSDK_GetCpuCycleCount(void) +{ + return DWT->CYCCNT; +} +#endif /* defined(DWT) */ + +#if !(defined(SDK_DELAY_USE_DWT) && defined(DWT)) +/* Use software loop. */ +#if defined(__CC_ARM) /* This macro is arm v5 specific */ +/* clang-format off */ +__ASM static void DelayLoop(uint32_t count) +{ +loop + SUBS R0, R0, #1 + CMP R0, #0 + BNE loop + BX LR +} +#elif defined(__ARM_ARCH_8A__) /* This macro is ARMv8-A specific */ +static void DelayLoop(uint32_t count) +{ + __ASM volatile(" MOV X0, %0" : : "r"(count)); + __ASM volatile( + "loop%=: \n" + " SUB X0, X0, #1 \n" + " CMP X0, #0 \n" + + " BNE loop%= \n" + : + : + : "r0"); +} +/* clang-format on */ +#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__) +/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler, + * use SUB and CMP here for compatibility */ +static void DelayLoop(uint32_t count) +{ + __ASM volatile(" MOV R0, %0" : : "r"(count)); + __ASM volatile( + "loop%=: \n" +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + " SUB R0, R0, #1 \n" +#else + " SUBS R0, R0, #1 \n" +#endif + " CMP R0, #0 \n" + + " BNE loop%= \n" + : + : + : "r0"); +} +#endif /* defined(__CC_ARM) */ +#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ + +/*! + * @brief Delay at least for some time. + * Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have + * effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and + * coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports + * up to 4294967 in current code. If long time delay is needed, please implement a new delay function. + * + * @param delayTime_us Delay time in unit of microsecond. + * @param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) +{ + uint64_t count; + + if (delayTime_us > 0U) + { + count = USEC_TO_COUNT(delayTime_us, coreClock_Hz); + + assert(count <= UINT32_MAX); + +#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */ + + MSDK_EnableCpuCycleCounter(); + /* Calculate the count ticks. */ + count += MSDK_GetCpuCycleCount(); + + if (count > UINT32_MAX) + { + count -= UINT32_MAX; + /* Wait for cyccnt overflow. */ + while (count < MSDK_GetCpuCycleCount()) + { + } + } + + /* Wait for cyccnt reach count value. */ + while (count > MSDK_GetCpuCycleCount()) + { + } +#else +#if defined(__CORTEX_Axx) && ((__CORTEX_Axx == 53) || (__CORTEX_Axx == 55)) + /* + * Cortex-A53/A55 execution throughput: + * - SUB/CMP: 2 instructions per cycle + * - BNE: 1 instruction per cycle + * So, each loop takes 2 CPU cycles. + */ + count = count / 2U; +#elif (__CORTEX_M == 7) + /* Divide value may be different in various environment to ensure delay is precise. + * Every loop count includes three instructions, due to Cortex-M7 sometimes executes + * two instructions in one period, through test here set divide 1.5. Other M cores use + * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does + * not matter because other instructions outside while loop is enough to fill the time. + */ + count = count / 3U * 2U; +#else + count = count / 4U; +#endif + DelayLoop((uint32_t)count); +#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ + } +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_common_arm.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_common_arm.h new file mode 100644 index 00000000000..3d35d76f812 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_common_arm.h @@ -0,0 +1,898 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_COMMON_ARM_H_ +#define FSL_COMMON_ARM_H_ + +/* + * For CMSIS pack RTE. + * CMSIS pack RTE generates "RTC_Components.h" which contains the statements + * of the related element for all selected software components. + */ +#ifdef _RTE_ +#include "RTE_Components.h" +#endif + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/*! @name Atomic modification + * + * These macros are used for atomic access, such as read-modify-write + * to the peripheral registers. + * + * Take @ref SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr + * means the address of the peripheral register or variable you want to modify + * atomically, the parameter @c clearBits is the bits to clear, the parameter + * @c setBits it the bits to set. + * For example, to set a 32-bit register bit1:bit0 to 0b10, use like this: + * + * @code + volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR; + + SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02); + @endcode + * + * In this example, the register bit1:bit0 are cleared and bit1 is set, as a result, + * register bit1:bit0 = 0b10. + * + * @note For the platforms don't support exclusive load and store, these macros + * disable the global interrupt to pretect the modification. + * + * @note These macros only guarantee the local processor atomic operations. For + * the multi-processor devices, use hardware semaphore such as SEMA42 to + * guarantee exclusive access if necessary. + * + * @{ + */ + +/*! + * @def SDK_ATOMIC_LOCAL_ADD(addr, val) + * Add value \a val from the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_SUB(addr, val) + * Subtract value \a val to the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_SET(addr, bits) + * Set the bits specifiled by \a bits to the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_CLEAR(addr, bits) + * Clear the bits specifiled by \a bits to the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) + * Toggle the bits specifiled by \a bits to the variable at address \a address. + * + * @def SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) + * For the variable at address \a address, clear the bits specifiled by \a clearBits + * and set the bits specifiled by \a setBits. + */ + +/* clang-format off */ +#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) +/* clang-format on */ + +/* If the LDREX and STREX are supported, use them. */ +#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXB(addr); \ + (ops); \ + } while (0UL != __STREXB((val), (addr))) + +#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXH(addr); \ + (ops); \ + } while (0UL != __STREXH((val), (addr))) + +#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXW(addr); \ + (ops); \ + } while (0UL != __STREXW((val), (addr))) + +static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalAdd1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \ + _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val)))) + +#define SDK_ATOMIC_LOCAL_SUB(addr, val) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalSub1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSub2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \ + _SDK_AtomicLocalSub4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val)))) + +#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClear1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClear2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalToggle1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalToggle2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(clearBits), (uint8_t)(setBits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(clearBits), (uint16_t)(setBits)) : \ + _SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(clearBits), (uint32_t)(setBits)))) +#else + +#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) += (val); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_SUB(addr, val) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) -= (val); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) |= (bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) &= ~(bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) ^= (bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) = (*(addr) & ~(clearBits)) | (setBits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (false) + +#endif +/*! @} */ + +/*! @name Timer utilities */ +/*! @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000000U / (clockFreqInHz)) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz)) +/*! @} */ + +/*! @name ISR exit barrier + * @{ + * + * ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + * exception return operation might vector to incorrect interrupt. + * For Cortex-M7, if core speed much faster than peripheral register write speed, + * the peripheral interrupt flags may be still set after exiting ISR, this results to + * the same error similar with errata 83869. + */ +#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U)) +#define SDK_ISR_EXIT_BARRIER __DSB() +#else +#define SDK_ISR_EXIT_BARRIER +#endif + +/*! @} */ + +/*! @name Alignment variable definition macros */ +/*! @{ */ +#if (defined(__ICCARM__)) +/* + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + * http:/ /supp.iar.com/Support/?note=24725 + */ +_Pragma("diag_suppress=Pm120") +#define SDK_PRAGMA(x) _Pragma(#x) + _Pragma("diag_error=Pm120") +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +#elif defined(__GNUC__) || defined(DOXYGEN_OUTPUT) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported +#endif + +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) +/*! @} */ + +/*! + * @name Non-cacheable region definition macros + * + * For initialized non-zero non-cacheable variables, please use "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them. For zero-inited non-cacheable + * variables, please use "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, + * these zero-inited variables will be initialized to zero in system startup. + * + * @note For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + * + * @{ + */ + +/*! + * @def AT_NONCACHEABLE_SECTION(var) + * Define a variable \a var, and place it in non-cacheable section. + * + * @def AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) + * Define a variable \a var, and place it in non-cacheable section, the start address + * of the variable is aligned to \a alignbytes. + * + * @def AT_NONCACHEABLE_SECTION_INIT(var) + * Define a variable \a var with initial value, and place it in non-cacheable section. + * + * @def AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) + * Define a variable \a var with initial value, and place it in non-cacheable section, + * the start address of the variable is aligned to \a alignbytes. + */ + +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && \ + defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) + +#if (defined(__ICCARM__)) +#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" + +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var +#if (defined(__CC_ARM)) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var +#else +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var +#endif + +#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT) +/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + */ +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported. +#endif + +#else + +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_ALIGN(var, alignbytes) +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes) + +#endif + +/*! @} */ + +/*! + * @name Time sensitive region + * @{ + */ + +/*! + * @def AT_QUICKACCESS_SECTION_CODE(func) + * Place function in a section which can be accessed quickly by core. + * + * @def AT_QUICKACCESS_SECTION_DATA(var) + * Place data in a section which can be accessed quickly by core. + * + * @def AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) + * Place data in a section which can be accessed quickly by core, and the variable + * address is set to align with \a alignbytes. + */ +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA(var) var @"DataQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + SDK_PRAGMA(data_alignment = alignbytes) var @"DataQuickAccess" +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + __attribute__((section("DataQuickAccess"))) __attribute__((aligned(alignbytes))) var +#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + __attribute__((section("DataQuickAccess"))) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/*! @} */ + +/*! + * @name Ram Function + * @{ + * + * @def RAMFUNCTION_SECTION_CODE(func) + * Place function in ram. + */ +#if (defined(__ICCARM__)) +#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/*! @} */ + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + void DefaultISR(void); +#endif + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ +static inline status_t EnableIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_EnableIRQ(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ +static inline status_t DisableIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_DisableIRQ(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Enable the IRQ, and also set the interrupt priority. + * + * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ to Enable. + * @param priNum Priority number set to interrupt controller register. + * @retval kStatus_Success Interrupt priority set successfully + * @retval kStatus_Fail Failed to set the interrupt priority. + */ +static inline status_t EnableIRQWithPriority(IRQn_Type interrupt, uint8_t priNum) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_SetPriority(interrupt, priNum); + GIC_EnableIRQ(interrupt); +#else + NVIC_SetPriority(interrupt, priNum); + NVIC_EnableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Set the IRQ priority. + * + * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ to set. + * @param priNum Priority number set to interrupt controller register. + * + * @retval kStatus_Success Interrupt priority set successfully + * @retval kStatus_Fail Failed to set the interrupt priority. + */ +static inline status_t IRQ_SetPriority(IRQn_Type interrupt, uint8_t priNum) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_SetPriority(interrupt, priNum); +#else + NVIC_SetPriority(interrupt, priNum); +#endif + } + + return status; +} + +/*! + * @brief Clear the pending IRQ flag. + * + * Only handle LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only handles the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The flag which IRQ to clear. + * + * @retval kStatus_Success Interrupt priority set successfully + * @retval kStatus_Fail Failed to set the interrupt priority. + */ +static inline status_t IRQ_ClearPendingIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_ClearPendingIRQ(interrupt); +#else + NVIC_ClearPendingIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ +static inline uint32_t DisableGlobalIRQ(void) +{ + uint32_t mask; + +#if defined(CPSR_I_Msk) + mask = __get_CPSR() & CPSR_I_Msk; +#elif defined(DAIF_I_BIT) + mask = __get_DAIF() & DAIF_I_BIT; +#else + mask = __get_PRIMASK(); +#endif + __disable_irq(); + + return mask; +} + +/*! + * @brief Enable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ +static inline void EnableGlobalIRQ(uint32_t primask) +{ +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#elif defined(DAIF_I_BIT) + if (0UL == primask) + { + __enable_irq(); + } +#else + __set_PRIMASK(primask); +#endif +} + +#if defined(ENABLE_RAM_VECTOR_TABLE) +/*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address + */ +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/* + * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, + * powerlib should be used instead of these functions. + */ +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) +/*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ +void EnableDeepSleepIRQ(IRQn_Type interrupt); + +/*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ +void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_POWERLIB_EXTEND */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#if defined(DWT) +/*! + * @brief Enable the counter to get CPU cycles. + */ +void MSDK_EnableCpuCycleCounter(void); + +/*! + * @brief Get the current CPU cycle count. + * + * @return Current CPU cycle count. + */ +uint32_t MSDK_GetCpuCycleCount(void); +#endif + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @} */ + +#endif /* FSL_COMMON_ARM_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_crc.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_crc.c new file mode 100644 index 00000000000..f4e303be95e --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_crc.c @@ -0,0 +1,371 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_crc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.crc" +#endif + +/*! @internal @brief Has data register with name CRC. */ +#if defined(FSL_FEATURE_CRC_HAS_CRC_REG) && FSL_FEATURE_CRC_HAS_CRC_REG +#define DATA CRC +#define DATALL CRCLL +#endif + +#if defined(CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT +/* @brief Default user configuration structure for CRC-16-CCITT */ +#define CRC_DRIVER_DEFAULT_POLYNOMIAL 0x1021U +/*< CRC-16-CCIT polynomial x**16 + x**12 + x**5 + x**0 */ +#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU +/*< Default initial checksum */ +#define CRC_DRIVER_DEFAULT_REFLECT_IN false +/*< Default is no transpose */ +#define CRC_DRIVER_DEFAULT_REFLECT_OUT false +/*< Default is transpose bytes */ +#define CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM false +/*< Default is without complement of CRC data register read data */ +#define CRC_DRIVER_DEFAULT_CRC_BITS kCrcBits16 +/*< Default is 16-bit CRC protocol */ +#define CRC_DRIVER_DEFAULT_CRC_RESULT kCrcFinalChecksum +/*< Default is resutl type is final checksum */ +#endif /* CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT */ + +#if defined(CRC_RSTS) +#define CRC_RESETS_ARRAY CRC_RSTS +#endif + +/*! @brief CRC type of transpose of read write data */ +typedef enum _crc_transpose_type +{ + kCrcTransposeNone = 0U, /*! No transpose */ + kCrcTransposeBits = 1U, /*! Tranpose bits in bytes */ + kCrcTransposeBitsAndBytes = 2U, /*! Transpose bytes and bits in bytes */ + kCrcTransposeBytes = 3U, /*! Transpose bytes */ +} crc_transpose_type_t; + +/*! + * @brief CRC module configuration. + * + * This structure holds the configuration for the CRC module. + */ +typedef struct _crc_module_config +{ + uint32_t polynomial; /*!< CRC Polynomial, MSBit first.@n + Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */ + uint32_t seed; /*!< Starting checksum value */ + crc_transpose_type_t readTranspose; /*!< Type of transpose when reading CRC result. */ + crc_transpose_type_t writeTranspose; /*!< Type of transpose when writing CRC input data. */ + bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */ + crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */ +} crc_module_config_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(CRC_RESETS_ARRAY) +/*! + * @brief Get instance number for CRC module. + * + * @param base CRC peripheral base address + */ +static uint32_t CRC_GetInstance(CRC_Type *base); +#endif +/******************************************************************************* + * Variables + ******************************************************************************/ +#if defined(CRC_RESETS_ARRAY) +static CRC_Type *const s_crcBases[] = CRC_BASE_PTRS; + +/* Reset array */ +static const reset_ip_name_t s_crcResets[] = CRC_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(CRC_RESETS_ARRAY) +static uint32_t CRC_GetInstance(CRC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_crcBases); instance++) + { + if (s_crcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_crcBases)); + + return instance; +} +#endif + +/*! + * @brief Returns transpose type for CRC protocol reflect in parameter. + * + * This functions helps to set writeTranspose member of crc_config_t structure. Reflect in is CRC protocol parameter. + * + * @param enable True or false for the selected CRC protocol Reflect In (refin) parameter. + */ +static inline crc_transpose_type_t CRC_GetTransposeTypeFromReflectIn(bool enable) +{ + return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeBytes); +} + +/*! + * @brief Returns transpose type for CRC protocol reflect out parameter. + * + * This functions helps to set readTranspose member of crc_config_t structure. Reflect out is CRC protocol parameter. + * + * @param enable True or false for the selected CRC protocol Reflect Out (refout) parameter. + */ +static inline crc_transpose_type_t CRC_GetTransposeTypeFromReflectOut(bool enable) +{ + return ((enable) ? kCrcTransposeBitsAndBytes : kCrcTransposeNone); +} + +/*! + * @brief Starts checksum computation. + * + * Configures the CRC module for the specified CRC protocol. @n + * Starts the checksum computation by writing the seed value + * + * @param base CRC peripheral address. + * @param config Pointer to protocol configuration structure. + */ +static void CRC_ConfigureAndStart(CRC_Type *base, const crc_module_config_t *config) +{ + uint32_t crcControl; + + /* pre-compute value for CRC control registger based on user configuraton without WAS field */ + crcControl = 0U | CRC_CTRL_TOT(config->writeTranspose) | CRC_CTRL_TOTR(config->readTranspose) | + CRC_CTRL_FXOR(config->complementChecksum) | CRC_CTRL_TCRC(config->crcBits); + + /* make sure the control register is clear - WAS is deasserted, and protocol is set */ + base->CTRL = crcControl; + + /* write polynomial register */ + base->GPOLY = config->polynomial; + + /* write pre-computed control register value along with WAS to start checksum computation */ + base->CTRL = crcControl | CRC_CTRL_WAS(true); + + /* write seed (initial checksum) */ + base->DATA = config->seed; + + /* deassert WAS by writing pre-computed CRC control register value */ + base->CTRL = crcControl; +} + +/*! + * @brief Starts final checksum computation. + * + * Configures the CRC module for the specified CRC protocol. @n + * Starts final checksum computation by writing the seed value. + * @note CRC_Get16bitResult() or CRC_Get32bitResult() return final checksum + * (output reflection and xor functions are applied). + * + * @param base CRC peripheral address. + * @param protocolConfig Pointer to protocol configuration structure. + */ +static void CRC_SetProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig) +{ + crc_module_config_t moduleConfig; + /* convert protocol to CRC peripheral module configuration, prepare for final checksum */ + moduleConfig.polynomial = protocolConfig->polynomial; + moduleConfig.seed = protocolConfig->seed; + moduleConfig.readTranspose = CRC_GetTransposeTypeFromReflectOut(protocolConfig->reflectOut); + moduleConfig.writeTranspose = CRC_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn); + moduleConfig.complementChecksum = protocolConfig->complementChecksum; + moduleConfig.crcBits = protocolConfig->crcBits; + + CRC_ConfigureAndStart(base, &moduleConfig); +} + +/*! + * @brief Starts intermediate checksum computation. + * + * Configures the CRC module for the specified CRC protocol. @n + * Starts intermediate checksum computation by writing the seed value. + * @note CRC_Get16bitResult() or CRC_Get32bitResult() return intermediate checksum (raw data register value). + * + * @param base CRC peripheral address. + * @param protocolConfig Pointer to protocol configuration structure. + */ +static void CRC_SetRawProtocolConfig(CRC_Type *base, const crc_config_t *protocolConfig) +{ + crc_module_config_t moduleConfig; + /* convert protocol to CRC peripheral module configuration, prepare for intermediate checksum */ + moduleConfig.polynomial = protocolConfig->polynomial; + moduleConfig.seed = protocolConfig->seed; + moduleConfig.readTranspose = + kCrcTransposeNone; /* intermediate checksum does no transpose of data register read value */ + moduleConfig.writeTranspose = CRC_GetTransposeTypeFromReflectIn(protocolConfig->reflectIn); + moduleConfig.complementChecksum = false; /* intermediate checksum does no xor of data register read value */ + moduleConfig.crcBits = protocolConfig->crcBits; + + CRC_ConfigureAndStart(base, &moduleConfig); +} + +/*! + * brief Enables and configures the CRC peripheral module. + * + * This function enables the clock gate in the SIM module for the CRC peripheral. + * It also configures the CRC module and starts a checksum computation by writing the seed. + * + * param base CRC peripheral address. + * param config CRC module configuration structure. + */ +void CRC_Init(CRC_Type *base, const crc_config_t *config) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* ungate clock */ + CLOCK_EnableClock(kCLOCK_Crc0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(CRC_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_crcResets[CRC_GetInstance(base)]); +#endif + + /* configure CRC module and write the seed */ + if (config->crcResult == kCrcFinalChecksum) + { + CRC_SetProtocolConfig(base, config); + } + else + { + CRC_SetRawProtocolConfig(base, config); + } +} + +/*! + * brief Loads default values to the CRC protocol configuration structure. + * + * Loads default values to the CRC protocol configuration structure. The default values are as follows. + * code + * config->polynomial = 0x1021; + * config->seed = 0xFFFF; + * config->reflectIn = false; + * config->reflectOut = false; + * config->complementChecksum = false; + * config->crcBits = kCrcBits16; + * config->crcResult = kCrcFinalChecksum; + * endcode + * + * param config CRC protocol configuration structure. + */ +void CRC_GetDefaultConfig(crc_config_t *config) +{ + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + static const crc_config_t crc16ccit = { + CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_SEED, + CRC_DRIVER_DEFAULT_REFLECT_IN, CRC_DRIVER_DEFAULT_REFLECT_OUT, + CRC_DRIVER_DEFAULT_COMPLEMENT_CHECKSUM, CRC_DRIVER_DEFAULT_CRC_BITS, + CRC_DRIVER_DEFAULT_CRC_RESULT, + }; + + *config = crc16ccit; +} + +/*! + * brief Writes data to the CRC module. + * + * Writes input data buffer bytes to the CRC data register. + * The configured type of transpose is applied. + * + * param base CRC peripheral address. + * param data Input data stream, MSByte in data[0]. + * param dataSize Size in bytes of the input data buffer. + */ +void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) +{ + const uint32_t *data32; + + /* 8-bit reads and writes till source address is aligned 4 bytes */ + while ((0U != dataSize) && (0U != ((uint32_t)data & 3U))) + { + base->ACCESS8BIT.DATALL = *data; + data++; + dataSize--; + } + + /* use 32-bit reads and writes as long as possible */ + data32 = (const uint32_t *)(uint32_t)data; + while (dataSize >= sizeof(uint32_t)) + { + base->DATA = *data32; + data32++; + dataSize -= sizeof(uint32_t); + } + + data = (const uint8_t *)data32; + + /* 8-bit reads and writes till end of data buffer */ + while (dataSize != 0U) + { + base->ACCESS8BIT.DATALL = *data; + data++; + dataSize--; + } +} + +/*! + * brief Reads the 32-bit checksum from the CRC module. + * + * Reads the CRC data register (either an intermediate or the final checksum). + * The configured type of transpose and complement is applied. + * + * param base CRC peripheral address. + * return An intermediate or the final 32-bit checksum, after configured transpose and complement operations. + */ +uint32_t CRC_Get32bitResult(CRC_Type *base) +{ + return base->DATA; +} + +/*! + * brief Reads a 16-bit checksum from the CRC module. + * + * Reads the CRC data register (either an intermediate or the final checksum). + * The configured type of transpose and complement is applied. + * + * param base CRC peripheral address. + * return An intermediate or the final 16-bit checksum, after configured transpose and complement operations. + */ +uint16_t CRC_Get16bitResult(CRC_Type *base) +{ + uint32_t retval; + uint32_t totr; /* type of transpose read bitfield */ + + retval = base->DATA; + totr = (base->CTRL & CRC_CTRL_TOTR_MASK) >> CRC_CTRL_TOTR_SHIFT; + + /* check transpose type to get 16-bit out of 32-bit register */ + if (totr >= 2U) + { + /* transpose of bytes for read is set, the result CRC is in CRC_DATA[HU:HL] */ + retval &= 0xFFFF0000U; + retval = retval >> 16U; + } + else + { + /* no transpose of bytes for read, the result CRC is in CRC_DATA[LU:LL] */ + retval &= 0x0000FFFFU; + } + return (uint16_t)retval; +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_crc.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_crc.h new file mode 100644 index 00000000000..487e9f1095f --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_crc.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_CRC_H_ +#define FSL_CRC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup crc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief CRC driver version. Version 2.0.4. + * + * Current version: 2.0.4 + * + * Change log: + * + * - Version 2.0.4 + * - Release peripheral from reset if necessary in init function. + * + * - Version 2.0.3 + * - Fix MISRA issues + * + * - Version 2.0.2 + * - Fix MISRA issues + * + * - Version 2.0.1 + * - move DATA and DATALL macro definition from header file to source file + */ +#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +/*! @} */ + +#ifndef CRC_DRIVER_CUSTOM_DEFAULTS +/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault. */ +#define CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT 1 +#endif + +/*! @brief CRC bit width */ +typedef enum _crc_bits +{ + kCrcBits16 = 0U, /*!< Generate 16-bit CRC code */ + kCrcBits32 = 1U /*!< Generate 32-bit CRC code */ +} crc_bits_t; + +/*! @brief CRC result type */ +typedef enum _crc_result +{ + kCrcFinalChecksum = 0U, /*!< CRC data register read value is the final checksum. + Reflect out and final xor protocol features are applied. */ + kCrcIntermediateChecksum = 1U /*!< CRC data register read value is intermediate checksum (raw value). + Reflect out and final xor protocol feature are not applied. + Intermediate checksum can be used as a seed for CRC_Init() + to continue adding data to this checksum. */ +} crc_result_t; + +/*! + * @brief CRC protocol configuration. + * + * This structure holds the configuration for the CRC protocol. + * + */ +typedef struct _crc_config +{ + uint32_t polynomial; /*!< CRC Polynomial, MSBit first. + Example polynomial: 0x1021 = 1_0000_0010_0001 = x^12+x^5+1 */ + uint32_t seed; /*!< Starting checksum value */ + bool reflectIn; /*!< Reflect bits on input. */ + bool reflectOut; /*!< Reflect bits on output. */ + bool complementChecksum; /*!< True if the result shall be complement of the actual checksum. */ + crc_bits_t crcBits; /*!< Selects 16- or 32- bit CRC protocol. */ + crc_result_t crcResult; /*!< Selects final or intermediate checksum return from CRC_Get16bitResult() or + CRC_Get32bitResult() */ +} crc_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Enables and configures the CRC peripheral module. + * + * This function enables the clock gate in the SIM module for the CRC peripheral. + * It also configures the CRC module and starts a checksum computation by writing the seed. + * + * @param base CRC peripheral address. + * @param config CRC module configuration structure. + */ +void CRC_Init(CRC_Type *base, const crc_config_t *config); + +/*! + * @brief Disables the CRC peripheral module. + * + * This function disables the clock gate in the SIM module for the CRC peripheral. + * + * @param base CRC peripheral address. + */ +static inline void CRC_Deinit(CRC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* gate clock */ + CLOCK_DisableClock(kCLOCK_Crc0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief Loads default values to the CRC protocol configuration structure. + * + * Loads default values to the CRC protocol configuration structure. The default values are as follows. + * @code + * config->polynomial = 0x1021; + * config->seed = 0xFFFF; + * config->reflectIn = false; + * config->reflectOut = false; + * config->complementChecksum = false; + * config->crcBits = kCrcBits16; + * config->crcResult = kCrcFinalChecksum; + * @endcode + * + * @param config CRC protocol configuration structure. + */ +void CRC_GetDefaultConfig(crc_config_t *config); + +/*! + * @brief Writes data to the CRC module. + * + * Writes input data buffer bytes to the CRC data register. + * The configured type of transpose is applied. + * + * @param base CRC peripheral address. + * @param data Input data stream, MSByte in data[0]. + * @param dataSize Size in bytes of the input data buffer. + */ +void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize); + +/*! + * @brief Reads the 32-bit checksum from the CRC module. + * + * Reads the CRC data register (either an intermediate or the final checksum). + * The configured type of transpose and complement is applied. + * + * @param base CRC peripheral address. + * @return An intermediate or the final 32-bit checksum, after configured transpose and complement operations. + */ +uint32_t CRC_Get32bitResult(CRC_Type *base); + +/*! + * @brief Reads a 16-bit checksum from the CRC module. + * + * Reads the CRC data register (either an intermediate or the final checksum). + * The configured type of transpose and complement is applied. + * + * @param base CRC peripheral address. + * @return An intermediate or the final 16-bit checksum, after configured transpose and complement operations. + */ +uint16_t CRC_Get16bitResult(CRC_Type *base); + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* FSL_CRC_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_ctimer.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_ctimer.c new file mode 100644 index 00000000000..3317157fdeb --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_ctimer.c @@ -0,0 +1,604 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_ctimer.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ctimer" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base Ctimer peripheral base address + * + * @return The Timer instance + */ +static uint32_t CTIMER_GetInstance(CTIMER_Type *base); + +/*! + * @brief CTIMER generic IRQ handle function. + * + * @param index FlexCAN peripheral instance index. + */ +static void CTIMER_GenericIRQHandler(uint32_t index); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to Timer bases for each instance. */ +static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to Timer clocks for each instance. */ +static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if defined(FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET +/*! @brief Pointers to Timer resets for each instance, writing a zero asserts the reset */ +static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS_N; +#else +/*! @brief Pointers to Timer resets for each instance, writing a one asserts the reset */ +static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS; +#endif +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/*! @brief Pointers real ISRs installed by drivers for each instance. */ +static ctimer_callback_t *s_ctimerCallback[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = {0}; + +/*! @brief Callback type installed by drivers for each instance. */ +static ctimer_callback_type_t ctimerCallbackType[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = { + kCTIMER_SingleCallback}; + +/*! @brief Array to map timer instance to IRQ number. */ +static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t CTIMER_GetInstance(CTIMER_Type *base) +{ + uint32_t instance; + uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ctimerArrayCount; instance++) + { + if (s_ctimerBases[instance] == base) + { + break; + } + } + + assert(instance < ctimerArrayCount); + + return instance; +} + +/*! + * brief Ungates the clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application before using the driver. + * + * param base Ctimer peripheral base address + * param config Pointer to the user configuration structure. + */ +void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config) +{ + assert(config != NULL); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the timer clock*/ + CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +/* Reset the module. */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) + RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/* Setup the cimer mode and count select */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input); +#endif + /* Setup the timer prescale value */ + base->PR = CTIMER_PR_PRVAL(config->prescale); +} + +/*! + * brief Gates the timer clock. + * + * param base Ctimer peripheral base address + */ +void CTIMER_Deinit(CTIMER_Type *base) +{ + uint32_t index = CTIMER_GetInstance(base); + /* Stop the timer */ + base->TCR &= ~CTIMER_TCR_CEN_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the timer clock*/ + CLOCK_DisableClock(s_ctimerClocks[index]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Disable IRQ at NVIC Level */ + (void)DisableIRQ(s_ctimerIRQ[index]); +} + +/*! + * brief Fills in the timers configuration structure with the default settings. + * + * The default values are: + * code + * config->mode = kCTIMER_TimerMode; + * config->input = kCTIMER_Capture_0; + * config->prescale = 0; + * endcode + * param config Pointer to the user configuration structure. + */ +void CTIMER_GetDefaultConfig(ctimer_config_t *config) +{ + assert(config != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* Run as a timer */ + config->mode = kCTIMER_TimerMode; + /* This field is ignored when mode is timer */ + config->input = kCTIMER_Capture_0; + /* Timer counter is incremented on every APB bus clock */ + config->prescale = 0; +} + +/*! + * brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function can manually assign the specified channel to set the PWM cycle. + * + * note When setting PWM output from multiple output pins, all should use the same PWM + * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. + * + * param base Ctimer peripheral base address + * param pwmPeriodChannel Specify the channel to control the PWM period + * param matchChannel Match pin to be used to output the PWM signal + * param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 + * param pwmFreq_Hz PWM signal frequency in Hz + * param srcClock_Hz Timer counter clock in Hz + * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt will be generated. + * + * return kStatus_Success on success + * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM cycle + */ +status_t CTIMER_SetupPwm(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + bool enableInt) +{ + assert(pwmFreq_Hz > 0U); + + uint32_t reg; + uint32_t period, pulsePeriod = 0; + uint32_t timerClock = srcClock_Hz / (base->PR + 1U); + uint32_t index = CTIMER_GetInstance(base); + + if (matchChannel == pwmPeriodChannel) + { + return kStatus_Fail; + } + + /* Enable PWM mode on the match channel */ + base->PWMC |= (1UL << (uint32_t)matchChannel); + + /* Clear the stop, reset and interrupt bits for this channel */ + reg = base->MCR; + reg &= + ~(((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK)) + << ((uint32_t)matchChannel * 3U)); + + /* If call back function is valid then enable match interrupt for the channel */ + if (enableInt) + { + reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); + } + + /* Reset the counter when match on PWM period channel (pwmPeriodChannel) */ + reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U)); + + base->MCR = reg; + + /* Calculate PWM period match value */ + period = (timerClock / pwmFreq_Hz) - 1U; + + /* Calculate pulse width match value */ + if (dutyCyclePercent == 0U) + { + pulsePeriod = period + 1U; + } + else + { + pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U; + } + + /* Specified channel pwmPeriodChannel will define the PWM period */ + base->MR[pwmPeriodChannel] = period; + + /* This will define the PWM pulse period */ + base->MR[matchChannel] = pulsePeriod; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); + /* If call back function is valid then enable interrupt and update the call back function */ + if (enableInt) + { + (void)EnableIRQ(s_ctimerIRQ[index]); + } + + return kStatus_Success; +} + +/*! + * brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function can manually assign the specified channel to set the PWM cycle. + * + * note When setting PWM output from multiple output pins, all should use the same PWM + * period + * + * param base Ctimer peripheral base address + * param pwmPeriodChannel Specify the channel to control the PWM period + * param matchChannel Match pin to be used to output the PWM signal + * param pwmPeriod PWM period match value + * param pulsePeriod Pulse width match value + * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt will be generated. + * + * return kStatus_Success on success + * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM period + */ +status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint32_t pwmPeriod, + uint32_t pulsePeriod, + bool enableInt) +{ +/* Some CTimers only have 16bits , so the value is limited*/ +#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B + assert(!((FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32) && (pulsePeriod > 0xFFFFU))); +#endif + + uint32_t reg; + uint32_t index = CTIMER_GetInstance(base); + + if (matchChannel == pwmPeriodChannel) + { + return kStatus_Fail; + } + + /* Enable PWM mode on PWM pulse channel */ + base->PWMC |= (1UL << (uint32_t)matchChannel); + + /* Clear the stop, reset and interrupt bits for PWM pulse channel */ + reg = base->MCR; + reg &= + ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) + << ((uint32_t)matchChannel * 3U)); + + /* If call back function is valid then enable match interrupt for PWM pulse channel */ + if (enableInt) + { + reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); + } + + /* Reset the counter when match on PWM period channel (pwmPeriodChannel) */ + reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U)); + + base->MCR = reg; + + /* Specified channel pwmPeriodChannel will define the PWM period */ + base->MR[pwmPeriodChannel] = pwmPeriod; + + /* This will define the PWM pulse period */ + base->MR[matchChannel] = pulsePeriod; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); + /* If call back function is valid then enable interrupt and update the call back function */ + if (enableInt) + { + (void)EnableIRQ(s_ctimerIRQ[index]); + } + + return kStatus_Success; +} + +/*! + * brief Updates the duty cycle of an active PWM signal. + * + * note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. + * This function can manually assign the specified channel to set the PWM cycle. + * + * param base Ctimer peripheral base address + * param pwmPeriodChannel Specify the channel to control the PWM period + * param matchChannel Match pin to be used to output the PWM signal + * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 + */ +void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent) +{ + uint32_t pulsePeriod = 0, period; + + /* Specified channel pwmPeriodChannel defines the PWM period */ + period = base->MR[pwmPeriodChannel]; + + /* For 0% dutycyle, make pulse period greater than period so the event will never occur */ + if (dutyCyclePercent == 0U) + { + pulsePeriod = period + 1U; + } + else + { + pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U; + } + + /* Update dutycycle */ + base->MR[matchChannel] = pulsePeriod; +} + +/*! + * brief Setup the match register. + * + * User configuration is used to setup the match value and action to be taken when a match occurs. + * + * param base Ctimer peripheral base address + * param matchChannel Match register to configure + * param config Pointer to the match configuration structure + */ +void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config) +{ +/* Some CTimers only have 16bits , so the value is limited*/ +#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B + assert(!(FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32 && config->matchValue > 0xFFFFU)); +#endif + uint32_t reg; + uint32_t index = CTIMER_GetInstance(base); + + /* Set the counter operation when a match on this channel occurs */ + reg = base->MCR; + reg &= + ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) + << ((uint32_t)matchChannel * 3U)); + reg |= ((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + ((uint32_t)matchChannel * 3U))); + reg |= ((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + ((uint32_t)matchChannel * 3U))); + reg |= ((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); + base->MCR = reg; + + reg = base->EMR; + /* Set the match output operation when a match on this channel occurs */ + reg &= ~(((uint32_t)CTIMER_EMR_EMC0_MASK) << ((uint32_t)matchChannel * 2U)); + reg |= ((uint32_t)config->outControl) << (CTIMER_EMR_EMC0_SHIFT + ((uint32_t)matchChannel * 2U)); + + /* Set the initial state of the EM bit/output */ + reg &= ~(((uint32_t)CTIMER_EMR_EM0_MASK) << (uint32_t)matchChannel); + reg |= ((uint32_t)config->outPinInitState) << (uint32_t)matchChannel; + base->EMR = reg; + + /* Set the match value */ + base->MR[matchChannel] = config->matchValue; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); + /* If interrupt is enabled then enable interrupt and update the call back function */ + if (config->enableInterrupt) + { + (void)EnableIRQ(s_ctimerIRQ[index]); + } +} + +/*! + * brief Get the status of output match. + * + * This function gets the status of output MAT, whether or not this output is connected to a pin. + * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + * + * param base Ctimer peripheral base address + * param matchChannel External match channel, user can obtain the status of multiple match channels + * at the same time by using the logic of "|" + * enumeration ::ctimer_external_match_t + * return The mask of external match channel status flags. Users need to use the + * _ctimer_external_match type to decode the return variables. + */ +uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel) +{ + return (base->EMR & matchChannel); +} + +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) +/*! + * brief Setup the capture. + * + * param base Ctimer peripheral base address + * param capture Capture channel to configure + * param edge Edge on the channel that will trigger a capture + * param enableInt Flag to enable channel interrupts, if enabled then the registered call back + * is called upon capture + */ +void CTIMER_SetupCapture(CTIMER_Type *base, + ctimer_capture_channel_t capture, + ctimer_capture_edge_t edge, + bool enableInt) +{ + uint32_t reg = base->CCR; + uint32_t index = CTIMER_GetInstance(base); + + /* Set the capture edge */ + reg &= ~((uint32_t)((uint32_t)CTIMER_CCR_CAP0RE_MASK | (uint32_t)CTIMER_CCR_CAP0FE_MASK | + (uint32_t)CTIMER_CCR_CAP0I_MASK) + << ((uint32_t)capture * 3U)); + reg |= ((uint32_t)edge) << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U)); + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, (((uint32_t)kCTIMER_Capture0Flag) << (uint32_t)capture)); + /* If call back function is valid then enable capture interrupt for the channel and update the call back function */ + if (enableInt) + { + reg |= ((uint32_t)CTIMER_CCR_CAP0I_MASK) << ((uint32_t)capture * 3U); + (void)EnableIRQ(s_ctimerIRQ[index]); + } + base->CCR = reg; +} +#endif + +/*! + * brief Register callback. + * + * param base Ctimer peripheral base address + * param cb_func callback function + * param cb_type callback function type, singular or multiple + */ +void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type) +{ + uint32_t index = CTIMER_GetInstance(base); + s_ctimerCallback[index] = cb_func; + ctimerCallbackType[index] = cb_type; +} + +/*! + * brief CTIMER generic IRQ handle function. + * + * param index FlexCAN peripheral instance index. + */ +static void CTIMER_GenericIRQHandler(uint32_t index) +{ + uint32_t int_stat, i, mask; + /* Get Interrupt status flags */ + int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]); + /* Clear the status flags that were set */ + CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat); + if (ctimerCallbackType[index] == kCTIMER_SingleCallback) + { + if (s_ctimerCallback[index][0] != NULL) + { + s_ctimerCallback[index][0](int_stat); + } + } + else + { +#if defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE + for (i = 0; i <= CTIMER_IR_MR3INT_SHIFT; i++) +#else +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT + for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++) +#else +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) + for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++) +#else + for (i = 0; i <= CTIMER_IR_CR1INT_SHIFT; i++) +#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +#endif + { + mask = 0x01UL << i; + /* For each status flag bit that was set call the callback function if it is valid */ + if (((int_stat & mask) != 0U) && (s_ctimerCallback[index][i] != NULL)) + { + s_ctimerCallback[index][i](int_stat); + } + } + } + SDK_ISR_EXIT_BARRIER; +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(CTIMER0) +void CTIMER0_DriverIRQHandler(void); +void CTIMER0_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(0); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER1) +void CTIMER1_DriverIRQHandler(void); +void CTIMER1_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(1); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER2) +void CTIMER2_DriverIRQHandler(void); +void CTIMER2_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(2); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER3) +void CTIMER3_DriverIRQHandler(void); +void CTIMER3_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(3); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER4) +void CTIMER4_DriverIRQHandler(void); +void CTIMER4_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(4); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER5) +void CTIMER5_DriverIRQHandler(void); +void CTIMER5_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(5); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER6) +void CTIMER6_DriverIRQHandler(void); +void CTIMER6_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(6); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CTIMER7) +void CTIMER7_DriverIRQHandler(void); +void CTIMER7_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(7); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_ctimer.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_ctimer.h new file mode 100644 index 00000000000..0ec7286e6c6 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_ctimer.h @@ -0,0 +1,682 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_CTIMER_H_ +#define FSL_CTIMER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ctimer + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*!< Version 2.3.1 */ +/*! @} */ + +/*! @brief List of Timer capture channels */ +typedef enum _ctimer_capture_channel +{ + kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */ + kCTIMER_Capture_1, /*!< Timer capture channel 1 */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + kCTIMER_Capture_2, /*!< Timer capture channel 2 */ +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + kCTIMER_Capture_3 /*!< Timer capture channel 3 */ +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ +} ctimer_capture_channel_t; + +/*! @brief List of capture edge options */ +typedef enum _ctimer_capture_edge +{ + kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */ + kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */ + kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */ +} ctimer_capture_edge_t; + +/*! @brief List of Timer match registers */ +typedef enum _ctimer_match +{ + kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */ + kCTIMER_Match_1, /*!< Timer match register 1 */ + kCTIMER_Match_2, /*!< Timer match register 2 */ + kCTIMER_Match_3 /*!< Timer match register 3 */ +} ctimer_match_t; + +/*! @brief List of external match */ +typedef enum _ctimer_external_match +{ + kCTIMER_External_Match_0 = (1UL << 0), /*!< External match 0 */ + kCTIMER_External_Match_1 = (1UL << 1), /*!< External match 1 */ + kCTIMER_External_Match_2 = (1UL << 2), /*!< External match 2 */ + kCTIMER_External_Match_3 = (1UL << 3) /*!< External match 3 */ +} ctimer_external_match_t; + +/*! @brief List of output control options */ +typedef enum _ctimer_match_output_control +{ + kCTIMER_Output_NoAction = 0U, /*!< No action is taken */ + kCTIMER_Output_Clear, /*!< Clear the EM bit/output to 0 */ + kCTIMER_Output_Set, /*!< Set the EM bit/output to 1 */ + kCTIMER_Output_Toggle /*!< Toggle the EM bit/output */ +} ctimer_match_output_control_t; + +/*! @brief List of Timer modes */ +typedef enum _ctimer_timer_mode +{ + kCTIMER_TimerMode = 0U, /* TC is incremented every rising APB bus clock edge */ + kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */ + kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */ + kCTIMER_IncreaseOnBothEdge /* TC is incremented on both edges of input signal */ +} ctimer_timer_mode_t; + +/*! @brief List of Timer interrupts */ +typedef enum _ctimer_interrupt_enable +{ + kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */ + kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */ + kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */ + kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */ + kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */ +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */ +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ +#endif +} ctimer_interrupt_enable_t; + +/*! @brief List of Timer flags */ +typedef enum _ctimer_status_flags +{ + kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */ + kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */ + kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */ + kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */ + kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) + kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */ +#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */ +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT + kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +#endif +} ctimer_status_flags_t; + +typedef void (*ctimer_callback_t)(uint32_t flags); + +/*! @brief Callback type when registering for a callback. When registering a callback + * an array of function pointers is passed the size could be 1 or 8, the callback + * type will tell that. + */ +typedef enum +{ + kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer. + based on the status flags different channels needs to be handled differently */ + kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. + for both match/capture */ +} ctimer_callback_type_t; + +/*! + * @brief Match configuration + * + * This structure holds the configuration settings for each match register. + */ +typedef struct _ctimer_match_config +{ + uint32_t matchValue; /*!< This is stored in the match register */ + bool enableCounterReset; /*!< true: Match will reset the counter + false: Match will not reser the counter */ + bool enableCounterStop; /*!< true: Match will stop the counter + false: Match will not stop the counter */ + ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */ + bool outPinInitState; /*!< Initial value of the EM bit/output */ + bool enableInterrupt; /*!< true: Generate interrupt upon match + false: Do not generate interrupt on match */ + +} ctimer_match_config_t; + +/*! + * @brief Timer configuration structure + * + * This structure holds the configuration settings for the Timer peripheral. To initialize this + * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a + * pointer to the configuration structure instance. + * + * The configuration structure can be made constant so as to reside in flash. + */ +typedef struct _ctimer_config +{ + ctimer_timer_mode_t mode; /*!< Timer mode */ + ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer + modes that rely on this input signal to increment TC */ + uint32_t prescale; /*!< Prescale value */ +} ctimer_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application before using the driver. + * + * @param base Ctimer peripheral base address + * @param config Pointer to the user configuration structure. + */ +void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config); + +/*! + * @brief Gates the timer clock. + * + * @param base Ctimer peripheral base address + */ +void CTIMER_Deinit(CTIMER_Type *base); + +/*! + * @brief Fills in the timers configuration structure with the default settings. + * + * The default values are: + * @code + * config->mode = kCTIMER_TimerMode; + * config->input = kCTIMER_Capture_0; + * config->prescale = 0; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void CTIMER_GetDefaultConfig(ctimer_config_t *config); + +/*! @}*/ + +/*! + * @name PWM setup operations + * @{ + */ + +/*! + * @brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function can manually assign the specified channel to set the PWM cycle. + * + * @note When setting PWM output from multiple output pins, all should use the same PWM + * period + * + * @param base Ctimer peripheral base address + * @param pwmPeriodChannel Specify the channel to control the PWM period + * @param matchChannel Match pin to be used to output the PWM signal + * @param pwmPeriod PWM period match value + * @param pulsePeriod Pulse width match value + * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt will be generated. + */ +status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint32_t pwmPeriod, + uint32_t pulsePeriod, + bool enableInt); + +/*! + * @brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function can manually assign the specified channel to set the PWM cycle. + * + * @note When setting PWM output from multiple output pins, all should use the same PWM + * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. + * + * @param base Ctimer peripheral base address + * @param pwmPeriodChannel Specify the channel to control the PWM period + * @param matchChannel Match pin to be used to output the PWM signal + * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz Timer counter clock in Hz + * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt will be generated. + */ +status_t CTIMER_SetupPwm(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + bool enableInt); + +/*! + * @brief Updates the pulse period of an active PWM signal. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param pulsePeriod New PWM pulse width match value + */ +static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod) +{ + /* Update PWM pulse period match value */ + base->MR[matchChannel] = pulsePeriod; +} + +/*! + * @brief Updates the duty cycle of an active PWM signal. + * + * @note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. + * This function can manually assign the specified channel to set the PWM cycle. + * + * @param base Ctimer peripheral base address + * @param pwmPeriodChannel Specify the channel to control the PWM period + * @param matchChannel Match pin to be used to output the PWM signal + * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 + */ +void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent); + +/*! @}*/ + +/*! + * @brief Setup the match register. + * + * User configuration is used to setup the match value and action to be taken when a match occurs. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match register to configure + * @param config Pointer to the match configuration structure + */ +void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config); + +/*! + * @brief Get the status of output match. + * + * This function gets the status of output MAT, whether or not this output is connected to a pin. + * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + * + * @param base Ctimer peripheral base address + * @param matchChannel External match channel, user can obtain the status of multiple match channels + * at the same time by using the logic of "|" + * enumeration ::ctimer_external_match_t + * @return The mask of external match channel status flags. Users need to use the + * _ctimer_external_match type to decode the return variables. + */ +uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel); + +/*! + * @brief Setup the capture. + * + * @param base Ctimer peripheral base address + * @param capture Capture channel to configure + * @param edge Edge on the channel that will trigger a capture + * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back + * is called upon capture + */ +void CTIMER_SetupCapture(CTIMER_Type *base, + ctimer_capture_channel_t capture, + ctimer_capture_edge_t edge, + bool enableInt); + +/*! + * @brief Get the timer count value from TC register. + * + * @param base Ctimer peripheral base address. + * @return return the timer count value. + */ +static inline uint32_t CTIMER_GetTimerCountValue(CTIMER_Type *base) +{ + return (base->TC); +} + +/*! + * @brief Register callback. + * + * @param base Ctimer peripheral base address + * @param cb_func callback function + * @param cb_type callback function type, singular or multiple + */ +void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type); + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected Timer interrupts. + * + * @param base Ctimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) +{ + /* Enable match interrupts */ + base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); + +/* Enable capture interrupts */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + | CTIMER_CCR_CAP2I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); +#endif +} + +/*! + * @brief Disables the selected Timer interrupts. + * + * @param base Ctimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask) +{ + /* Disable match interrupts */ + base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK)); + +/* Disable capture interrupts */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + | CTIMER_CCR_CAP2I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + )); +#endif +} + +/*! + * @brief Gets the enabled Timer interrupts. + * + * @param base Ctimer peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base) +{ + uint32_t enabledIntrs = 0; + + /* Get all the match interrupts enabled */ + enabledIntrs = + base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); + +/* Get all the capture interrupts enabled */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + | CTIMER_CCR_CAP2I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); +#endif + + return enabledIntrs; +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the Timer status flags. + * + * @param base Ctimer peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::ctimer_status_flags_t + */ +static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base) +{ + return base->IR; +} + +/*! + * @brief Clears the Timer status flags. + * + * @param base Ctimer peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::ctimer_status_flags_t + */ +static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask) +{ + base->IR = mask; +} + +/*! @}*/ + +/*! + * @name Counter Start and Stop + * @{ + */ + +/*! + * @brief Starts the Timer counter. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_StartTimer(CTIMER_Type *base) +{ + base->TCR |= CTIMER_TCR_CEN_MASK; +} + +/*! + * @brief Stops the Timer counter. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_StopTimer(CTIMER_Type *base) +{ + base->TCR &= ~CTIMER_TCR_CEN_MASK; +} + +/*! @}*/ + +/*! + * @brief Reset the counter. + * + * The timer counter and prescale counter are reset on the next positive edge of the APB clock. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_Reset(CTIMER_Type *base) +{ + base->TCR |= CTIMER_TCR_CRST_MASK; + base->TCR &= ~CTIMER_TCR_CRST_MASK; +} + +/*! + * @brief Setup the timer prescale value. + * + * Specifies the maximum value for the Prescale Counter. + * + * @param base Ctimer peripheral base address + * @param prescale Prescale value + */ +static inline void CTIMER_SetPrescale(CTIMER_Type *base, uint32_t prescale) +{ + base->PR = CTIMER_PR_PRVAL(prescale); +} + +/*! + * @brief Get capture channel value. + * + * Get the counter/timer value on the corresponding capture channel. + * + * @param base Ctimer peripheral base address + * @param capture Select capture channel + * + * @return The timer count capture value. + */ +static inline uint32_t CTIMER_GetCaptureValue(CTIMER_Type *base, ctimer_capture_channel_t capture) +{ + return base->CR[capture]; +} + +/*! + * @brief Enable reset match channel. + * + * Set the specified match channel reset operation. + * + * @param base Ctimer peripheral base address + * @param match match channel used + * @param enable Enable match channel reset operation. + */ +static inline void CTIMER_EnableResetMatchChannel(CTIMER_Type *base, ctimer_match_t match, bool enable) +{ + if (enable) + { + base->MCR |= (1UL << (CTIMER_MCR_MR0R_SHIFT + ((uint32_t)match * 3U))); + } + else + { + base->MCR &= ~(1UL << (CTIMER_MCR_MR0R_SHIFT + ((uint32_t)match * 3U))); + } +} + +/*! + * @brief Enable stop match channel. + * + * Set the specified match channel stop operation. + * + * @param base Ctimer peripheral base address. + * @param match match channel used. + * @param enable Enable match channel stop operation. + */ +static inline void CTIMER_EnableStopMatchChannel(CTIMER_Type *base, ctimer_match_t match, bool enable) +{ + if (enable) + { + base->MCR |= (1UL << (CTIMER_MCR_MR0S_SHIFT + ((uint32_t)match * 3U))); + } + else + { + base->MCR &= ~(1UL << (CTIMER_MCR_MR0S_SHIFT + ((uint32_t)match * 3U))); + } +} + +#if (defined(FSL_FEATURE_CTIMER_HAS_MSR) && (FSL_FEATURE_CTIMER_HAS_MSR)) +/*! + * @brief Enable reload channel falling edge. + * + * Enable the specified match channel reload match shadow value. + * + * @param base Ctimer peripheral base address. + * @param match match channel used. + * @param enable Enable . + */ +static inline void CTIMER_EnableMatchChannelReload(CTIMER_Type *base, ctimer_match_t match, bool enable) +{ + if (enable) + { + base->MCR |= (1UL << (CTIMER_MCR_MR0RL_SHIFT + (uint32_t)match)); + } + else + { + base->MCR &= ~(1UL << (CTIMER_MCR_MR0RL_SHIFT + (uint32_t)match)); + } +} +#endif /* FSL_FEATURE_CTIMER_HAS_MSR */ + +/*! + * @brief Enable capture channel rising edge. + * + * Sets the specified capture channel for rising edge capture. + * + * @param base Ctimer peripheral base address. + * @param capture capture channel used. + * @param enable Enable rising edge capture. + */ +static inline void CTIMER_EnableRisingEdgeCapture(CTIMER_Type *base, ctimer_capture_channel_t capture, bool enable) +{ + if (enable) + { + base->CCR |= (1UL << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U))); + } + else + { + base->CCR &= ~(1UL << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U))); + } +} + +/*! + * @brief Enable capture channel falling edge. + * + * Sets the specified capture channel for falling edge capture. + * + * @param base Ctimer peripheral base address. + * @param capture capture channel used. + * @param enable Enable falling edge capture. + */ +static inline void CTIMER_EnableFallingEdgeCapture(CTIMER_Type *base, ctimer_capture_channel_t capture, bool enable) +{ + if (enable) + { + base->CCR |= (1UL << (CTIMER_CCR_CAP0FE_SHIFT + ((uint32_t)capture * 3U))); + } + else + { + base->CCR &= ~(1UL << (CTIMER_CCR_CAP0FE_SHIFT + ((uint32_t)capture * 3U))); + } +} + +#if (defined(FSL_FEATURE_CTIMER_HAS_MSR) && (FSL_FEATURE_CTIMER_HAS_MSR)) +/*! + * @brief Set the specified match shadow channel. + * + * @param base Ctimer peripheral base address. + * @param match match channel used. + * @param matchvalue Reload the value of the corresponding match register. + */ +static inline void CTIMER_SetShadowValue(CTIMER_Type *base, ctimer_match_t match, uint32_t matchvalue) +{ + base->MSR[match] = matchvalue; +} +#endif /* FSL_FEATURE_CTIMER_HAS_MSR */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_CTIMER_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_dac.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_dac.c new file mode 100644 index 00000000000..09845018deb --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_dac.c @@ -0,0 +1,236 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019, 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_dac.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.dac_1" +#endif + +#if defined(DAC_RSTS) +#define DAC_RESETS_ARRAY DAC_RSTS +#elif defined(DAC_RSTS_N) +#define DAC_RESETS_ARRAY DAC_RSTS_N +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for DAC module. + * + * @param base DAC peripheral base address + */ +static uint32_t DAC_GetInstance(LPDAC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to DAC bases for each instance. */ +static LPDAC_Type *const s_dacBases[] = LPDAC_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to DAC clocks for each instance. */ +static const clock_ip_name_t s_dacClocks[] = LPDAC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(DAC_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_dacResets[] = DAC_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t DAC_GetInstance(LPDAC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_dacBases); instance++) + { + if (s_dacBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_dacBases)); + + return instance; +} + +/*! + * brief Initialize the DAC module with common configuartion. + * + * The clock will be enabled in this function. + * + * param base DAC peripheral base address. + * param config Pointer to configuration structure. + */ +void DAC_Init(LPDAC_Type *base, const dac_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32 = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_dacClocks[DAC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(DAC_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_dacResets[DAC_GetInstance(base)]); +#endif + + /* Reset the logic. */ + DAC_SetReset(base, kDAC_ResetLogic); + DAC_ClearReset(base, kDAC_ResetLogic); + + /* Reset the FIFO. */ + DAC_SetReset(base, kDAC_ResetFIFO); + DAC_ClearReset(base, kDAC_ResetFIFO); + + /* Configuration. */ + if (kDAC_FIFOTriggerBySoftwareMode == config->fifoTriggerMode) + { + tmp32 |= LPDAC_GCR_TRGSEL_MASK; /* Software trigger. */ + } + switch (config->fifoWorkMode) + { + case kDAC_FIFOWorkAsNormalMode: /* Normal FIFO. */ + tmp32 |= LPDAC_GCR_FIFOEN_MASK; + break; + case kDAC_FIFOWorkAsSwingMode: + tmp32 |= LPDAC_GCR_FIFOEN_MASK | LPDAC_GCR_SWMD_MASK; /* Enable swing mode. */ + break; +#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE + case kDAC_FIFOWorkAsPeriodTriggerMode: + tmp32 |= LPDAC_GCR_FIFOEN_MASK | LPDAC_GCR_PTGEN_MASK; /* Enable period trigger mode. */ + /* Set trigger number and width. */ + base->PCR = + LPDAC_PCR_PTG_NUM(config->periodicTriggerNumber) | LPDAC_PCR_PTG_PERIOD(config->periodicTriggerWidth); + break; + case kDAC_FIFOWorkAsPeriodTriggerAndSwingMode: + tmp32 |= LPDAC_GCR_FIFOEN_MASK | LPDAC_GCR_PTGEN_MASK | LPDAC_GCR_SWMD_MASK; + /* Set trigger number and width. */ + base->PCR = + LPDAC_PCR_PTG_NUM(config->periodicTriggerNumber) | LPDAC_PCR_PTG_PERIOD(config->periodicTriggerWidth); + break; +#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */ + default: /* kDAC_FIFODisabled. */ + break; + } + +#if defined(FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG) && FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG + if (config->enableExternalTriggerSource) + { + tmp32 |= LPDAC_GCR_RCV_TRG_MASK; /* Use trigger source from another DAC. */ + } +#endif /* FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG */ +#if defined(FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL) && FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL + if (false == config->enableLowerLowPowerMode) + { + tmp32 |= LPDAC_GCR_BUF_SPD_CTRL_MASK; /* Enable low power. */ + } +#else + if (config->enableLowPowerMode) + { + tmp32 |= LPDAC_GCR_LPEN_MASK; /* Enable low power. */ + } +#endif /* LPDAC_GCR_BUF_SPD_CTRL_MASK */ + +#if defined(FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN) && FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN + tmp32 |= LPDAC_GCR_BUF_EN_MASK; /* Opamp is used as buffer. */ +#endif /* FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN */ +#if defined(FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC) && FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC + /* Configure DAC sync cycles. */ + tmp32 |= LPDAC_GCR_LATCH_CYC(config->syncTime); +#endif /* FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC */ +#if defined(FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT) && FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT + tmp32 |= (uint32_t)config->referenceCurrentSource; +#endif /* FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT */ + /* Set reference voltage source. */ + tmp32 |= LPDAC_GCR_DACRFS(config->referenceVoltageSource); + + base->GCR = tmp32; + base->FCR = LPDAC_FCR_WML(config->fifoWatermarkLevel); + + /* Now, the DAC is disabled. It needs to be enabled in application. */ +} + +/*! + * brief Get the default settings for initialization's configuration. + * + * This function initializes the user configuration structure to a default value. The default values are: + * code + * config->fifoWatermarkLevel = 0U; + * config->fifoTriggerMode = kDAC_FIFOTriggerByHardwareMode; + * config->fifoWorkMode = kDAC_FIFODisabled; + * config->enableLowPowerMode = false; + * config->referenceVoltageSource = kDAC_ReferenceVoltageSourceAlt1; + * endcode + * + * param config Pointer to configuration structure. + * param + */ +void DAC_GetDefaultConfig(dac_config_t *config) +{ + assert(config != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->fifoWatermarkLevel = 0U; + config->fifoTriggerMode = kDAC_FIFOTriggerByHardwareMode; + config->fifoWorkMode = kDAC_FIFODisabled; + +#if defined(FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG) && FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG + config->enableExternalTriggerSource = false; +#endif /* FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG */ +#if defined(FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL) && FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL + config->enableLowerLowPowerMode = true; +#else + config->enableLowPowerMode = false; +#endif /* FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL */ +#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE + config->periodicTriggerNumber = 0UL; + config->periodicTriggerWidth = 0UL; +#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */ +#if defined(FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC) && FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC + /* Configure DAC sync cycles. */ + config->syncTime = 1U; +#endif /* FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC */ +#if defined(FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT) && FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT + config->referenceCurrentSource = kDAC_ReferenceCurrentSourcePtat; +#endif /* FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT */ + config->referenceVoltageSource = kDAC_ReferenceVoltageSourceAlt1; +} + +/*! + * brief De-initialize the DAC module. + * + * The clock will be disabled in this function. + * + * param base DAC peripheral base address. + * param + */ +void DAC_Deinit(LPDAC_Type *base) +{ + /* Disable the module. */ + DAC_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_dacClocks[DAC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_dac.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_dac.h new file mode 100644 index 00000000000..5dcecf2db57 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_dac.h @@ -0,0 +1,442 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020, 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_DAC_H_ +#define FSL_DAC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup dac + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief DAC driver version 2.1.2. */ +#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) +/*! @} */ + +/*! + * @brief DAC reset control. + */ +enum +{ + kDAC_ResetFIFO = LPDAC_RCR_FIFORST_MASK, /*!< Resets the FIFO pointers and flags. */ + kDAC_ResetLogic = LPDAC_RCR_SWRST_MASK, /*!< Resets all DAC registers and internal logic. */ +}; + +/*! + * @brief DAC interrupts. + */ +enum +{ + kDAC_FIFOFullInterruptEnable = LPDAC_IER_FULL_IE_MASK, /*!< FIFO full interrupt enable. */ + kDAC_FIFOEmptyInterruptEnable = LPDAC_IER_EMPTY_IE_MASK, /*!< FIFO empty interrupt enable. */ + kDAC_FIFOWatermarkInterruptEnable = LPDAC_IER_WM_IE_MASK, /*!< FIFO watermark interrupt enable. */ + kDAC_SwingBackInterruptEnable = LPDAC_IER_SWBK_IE_MASK, /*!< Swing back one cycle complete interrupt enable. */ + kDAC_FIFOOverflowInterruptEnable = LPDAC_IER_OF_IE_MASK, /*!< FIFO overflow interrupt enable. */ + kDAC_FIFOUnderflowInterruptEnable = LPDAC_IER_UF_IE_MASK, /*!< FIFO underflow interrupt enable. */ +#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE + kDAC_PeriodTriggerCompleteInterruptEnable = + LPDAC_IER_PTGCOCO_IE_MASK, /*!< Period trigger mode conversion complete interrupt enable */ +#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */ +}; + +/*! + * @brief DAC DMA switchers. + */ +enum +{ + kDAC_FIFOEmptyDMAEnable = LPDAC_DER_EMPTY_DMAEN_MASK, /*!< FIFO empty DMA enable. */ + kDAC_FIFOWatermarkDMAEnable = LPDAC_DER_WM_DMAEN_MASK, /*!< FIFO watermark DMA enable. */ +}; + +/*! + * @brief DAC status flags. + */ +enum +{ + kDAC_FIFOUnderflowFlag = LPDAC_FSR_UF_MASK, /*!< This flag means that there is a new trigger after the buffer is +empty. The FIFO read pointer will not +increase in this case and the data sent to DAC analog conversion will not changed. This flag is cleared by writing a 1 +to it. */ + + kDAC_FIFOOverflowFlag = + LPDAC_FSR_OF_MASK, /*!< This flag indicates that data is intended to write into FIFO after the +buffer is full. The writer pointer will +not increase in this case. The extra data will not be written into the FIFO. This flag is cleared by writing a 1 to it. +*/ + + kDAC_FIFOSwingBackFlag = LPDAC_FSR_SWBK_MASK, /*!< This flag indicates that the DAC has completed one period of +conversion in swing back mode. It means +that the read pointer has increased to the top (write pointer) once and then decreased to zero once. For +example, after three data is written to FIFO, the writer pointer is now 3. Then, if continually triggered, the +read pointer will swing like: 0-1-2-1-0-1-2-, and so on. After the fourth trigger, the flag is set. This flag is +cleared by writing a 1 to it. */ + + kDAC_FIFOWatermarkFlag = LPDAC_FSR_WM_MASK, /*!< This field is set if the remaining data in FIFO is less than or + equal to the setting value of wartermark. By writing data into FIFO by DMA or CPU, this flag is + cleared automatically when the data in FIFO is more than the setting value of watermark. */ + + kDAC_FIFOEmptyFlag = LPDAC_FSR_EMPTY_MASK, /*!< FIFO empty flag. */ + kDAC_FIFOFullFlag = LPDAC_FSR_FULL_MASK, /*!< FIFO full flag. */ +#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE + kDAC_PeriodTriggerCompleteFlag = LPDAC_FSR_PTGCOCO_MASK, /*!< Period trigger mode conversion complete flag. */ +#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */ +}; + +/*! + * @brief DAC FIFO trigger mode. + */ +typedef enum _dac_fifo_trigger_mode +{ + kDAC_FIFOTriggerByHardwareMode = 0U, /*!< Buffer would be triggered by hardware. */ + kDAC_FIFOTriggerBySoftwareMode = 1U, /*!< Buffer would be triggered by software. */ +} dac_fifo_trigger_mode_t; + +/*! + * @brief DAC FIFO work mode. + */ +typedef enum _dac_fifo_work_mode +{ + kDAC_FIFODisabled = 0U, /*!< FIFO mode is disabled and buffer mode is enabled. Any data written to DATA[DATA] goes + to buffer then goes to conversion. */ + kDAC_FIFOWorkAsNormalMode = 1U, /*!< FIFO mode is enabled. Data will be first read from FIFO to buffer then goes to + conversion. */ + kDAC_FIFOWorkAsSwingMode = 2U, /*!< In swing mode, the read pointer swings between the writer pointer and zero. That + is, the trigger increases the read pointer till reach the writer pointer and + decreases the read pointer till zero, and so on. The FIFO empty/full/watermark + flag will not update during swing back mode. */ +#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE + kDAC_FIFOWorkAsPeriodTriggerMode = + 3U, /*!< In periodic trigger mode, user only needs to send the first trigger. Then after every [PTG_PERIOD+1] + RCLK cycles, DAC will be automatically triggered by internal trigger. There will be [PTG_NUM] internal + triggers, thus in total [PTG_NUM+1] conversions including the first trigger sent by user. User can + terminate the current conversion queue by clearing the GCR[PTGEN] bit. Then, after the current conversion + is completed, the conversion is terminated and the PTGCOCO flag is set. If PCR[PTG_NUM] is set to zero, + there will be infinite triggers following the first hardware/software trigger, until the GCR[PTGEN] is + cleared by software. In any case, the conversion can be terminated by FIFORST/SWRST. */ + kDAC_FIFOWorkAsPeriodTriggerAndSwingMode = 4U, /*!< Periodically trigger DAC and swing back. */ +#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */ +} dac_fifo_work_mode_t; + +/*! + * @brief DAC reference voltage source. + */ +typedef enum _dac_reference_voltage_source +{ +#if defined(FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC) && (FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC == 3) + kDAC_ReferenceVoltageSourceAlt1 = 0U, /*!< The DAC selects VDD_ANA as the reference voltage. */ + kDAC_ReferenceVoltageSourceAlt2 = 1U, /*!< The DAC selects VREF_OUT as the reference voltage. */ + kDAC_ReferenceVoltageSourceAlt3 = 2U, /*!< THe DAC selects VREFH as the reference voltage. */ +#else + kDAC_ReferenceVoltageSourceAlt1 = 0U, /*!< The DAC selects VREFH_INT as the reference voltage. */ + kDAC_ReferenceVoltageSourceAlt2 = 1U, /*!< The DAC selects VREFH_EXT as the reference voltage. */ +#endif /* FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC */ +} dac_reference_voltage_source_t; + +#if defined(FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT) && FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT +/* + * @brief DAC internal reference current source + */ +typedef enum _dac_reference_current_source +{ + kDAC_ReferenceCurrentSourcePtat = LPDAC_GCR_IREF_PTAT_EXT_SEL_MASK, /* Internal PTAT Current Reference selected */ + kDAC_ReferenceCurrentSourceZtc = LPDAC_GCR_IREF_ZTC_EXT_SEL_MASK, /* Internal ZTC Current Reference selected */ +} dac_reference_current_source_t; +#endif /* FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT */ + +/*! + * @brief DAC configuration structure. + */ +typedef struct _dac_config +{ + uint32_t fifoWatermarkLevel; /*!< FIFO's watermark, the max value can be the hardware FIFO size. */ + dac_fifo_trigger_mode_t fifoTriggerMode; /*!< Select the trigger mode for FIFO. */ + dac_fifo_work_mode_t fifoWorkMode; /*!< Select the work mode for FIFO. */ +#if defined(FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN) && FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN + bool enableOpampBuffer; /*!< Opamp is used as buffer. */ +#endif /* FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN */ +#if defined(FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG) && FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG + bool enableExternalTriggerSource; /* DAC uses another DAC's hardware/software trigger as its trigger source. */ +#endif /* FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG */ +#if defined(FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL) && FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL + bool enableLowerLowPowerMode; /*!< Enable the lower low power mode. */ +#else + bool enableLowPowerMode; /*!< Enable the low power mode. */ +#endif /* FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL */ +#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE + uint32_t periodicTriggerNumber; /*!< There will be 'periodicTriggerNumber' internal triggers following the first + hardware/software trigger. So there will be 'periodicTriggerNumber + 1' + conversions in total. If set to zero, there will be infinite triggers following + the first hw/sw trigger, until the GCR[PTGEN] is cleared. */ + uint32_t periodicTriggerWidth; /*!< Control the periodic trigger frequency. There will be 'periodicTriggerWidth + 1' + RCLK cycles between each periodic trigger. The periodic trigger frequency should + be configured to not larger than the analog conversion speed. */ +#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */ +#if defined(FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC) && FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC + uint32_t syncTime; /*!< RCLK cycles before data latch. accessible range is 0-15. It is used to configure the DAC + sync cycles which is helpful to reduce glitch on the output. The sync time is (LATCH_CYC+1) + RCLK cycles. User should configure this register according to the RCLK frequency. The + recommended sync time is at least 40ns.*/ +#endif /* FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC */ +#if defined(FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT) && FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT + dac_reference_current_source_t referenceCurrentSource; /*!< Select the internal reference current source. */ +#endif /* FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT */ + dac_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */ +} dac_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and de-initialization + * @{ + */ + +/*! + * @brief Initialize the DAC module with common configuartion. + * + * The clock will be enabled in this function. + * + * @param base DAC peripheral base address. + * @param config Pointer to configuration structure. + */ +void DAC_Init(LPDAC_Type *base, const dac_config_t *config); + +/*! + * @brief Get the default settings for initialization's configuration. + * + * This function initializes the user configuration structure to a default value. The default values are: + * @code + * config->fifoWatermarkLevel = 0U; + * config->fifoTriggerMode = kDAC_FIFOTriggerByHardwareMode; + * config->fifoWorkMode = kDAC_FIFODisabled; + * config->enableLowPowerMode = false; + * config->referenceVoltageSource = kDAC_ReferenceVoltageSourceAlt1; + * @endcode + * + * @param config Pointer to configuration structure. + */ +void DAC_GetDefaultConfig(dac_config_t *config); + +/*! + * @brief De-initialize the DAC module. + * + * The clock will be disabled in this function. + * + * @param base DAC peripheral base address. + */ +void DAC_Deinit(LPDAC_Type *base); + +/*! + * @brief Assert the reset control to part hardware. + * + * This function is to assert the reset control to part hardware. Responding part hardware would remain reset untill + * cleared by software. + * + * @param base DAC peripheral base address. + * @param mask The reset control mask, see to _dac_reset_control_t. + */ +static inline void DAC_SetReset(LPDAC_Type *base, uint32_t mask) +{ + base->RCR |= mask; +} + +/*! + * @brief Clear the reset control to part hardware. + * + * This function is to clear the reset control to part hardware. Responding part hardware would work after the reset + * control is cleared by software. + * + * @param base DAC peripheral base address. + * @param mask The reset control mask, see to _dac_reset_control_t. + */ +static inline void DAC_ClearReset(LPDAC_Type *base, uint32_t mask) +{ + base->RCR &= ~mask; +} + +/*! + * @brief Enable the DAC hardware system or not. + * + * This function is to start the Programmable Reference Generator operation or not. + * + * @param base DAC peripheral base address. + * @param enable Assertion of indicated event. + */ +static inline void DAC_Enable(LPDAC_Type *base, bool enable) +{ + if (enable) + { + base->GCR |= LPDAC_GCR_DACEN_MASK; + } + else + { + base->GCR &= ~LPDAC_GCR_DACEN_MASK; + } +} + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enable the interrupts. + * + * @param base DAC peripheral base address. + * @param mask Mask value of indicated interrupt events. See to _dac_interrupt_enable. + */ +static inline void DAC_EnableInterrupts(LPDAC_Type *base, uint32_t mask) +{ + base->IER |= mask; +} + +/*! + * @brief Disable the interrupts. + * + * @param base DAC peripheral base address. + * @param mask Mask value of indicated interrupt events. See to _dac_interrupt_enable. + */ +static inline void DAC_DisableInterrupts(LPDAC_Type *base, uint32_t mask) +{ + base->IER &= ~mask; +} + +/*! @} */ + +/*! + * @name DMA control + * @{ + */ + +/*! + * @brief Enable the DMA switchers or not. + * + * @param base DAC peripheral base address. + * @param mask Mask value of indicated DMA requeset. See to _dac_dma_enable. + * @param enable Enable the DMA or not. + */ +static inline void DAC_EnableDMA(LPDAC_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->DER |= mask; + } + else + { + base->DER &= ~mask; + } +} + +/*! @} */ + +/*! + * @name Status flags + * @{ + */ + +/*! + * @brief Get status flags of DAC module. + * + * @param base DAC peripheral base address. + * @return Mask value of status flags. See to _dac_status_flags. + */ +static inline uint32_t DAC_GetStatusFlags(LPDAC_Type *base) +{ + return base->FSR; +} + +/*! + * @brief Clear status flags of DAC module. + * + * @param base DAC peripheral base address. + * @param flags Mask value of status flags to be cleared. See to _dac_status_flags. + */ +static inline void DAC_ClearStatusFlags(LPDAC_Type *base, uint32_t flags) +{ + base->FSR = flags; +} + +/*! @} */ + +/*! + * @name Functional feature + * @{ + */ + +/*! + * @brief Set data into the entry of FIFO buffer. + * + * @param base DAC peripheral base address. + * @param value Setting value into FIFO buffer. + */ +static inline void DAC_SetData(LPDAC_Type *base, uint32_t value) +{ + base->DATA = LPDAC_DATA_DATA(value); +} + +/*! + * @brief Get the value of the FIFO write pointer. + * + * @param base DAC peripheral base address. + * @return Current value of the FIFO write pointer. + */ + +static inline uint32_t DAC_GetFIFOWritePointer(LPDAC_Type *base) +{ + return (LPDAC_FPR_FIFO_WPT_MASK & base->FPR) >> LPDAC_FPR_FIFO_WPT_SHIFT; +} + +/*! + * @brief Get the value of the FIFO read pointer. + * + * @param base DAC peripheral base address. + * @return Current value of the FIFO read pointer. + */ + +static inline uint32_t DAC_GetFIFOReadPointer(LPDAC_Type *base) +{ + return (LPDAC_FPR_FIFO_RPT_MASK & base->FPR) >> LPDAC_FPR_FIFO_RPT_SHIFT; +} + +/*! + * @brief Do software trigger to FIFO when in software mode. + * + * @param base DAC peripheral base address. + */ + +static inline void DAC_DoSoftwareTriggerFIFO(LPDAC_Type *base) +{ + base->TCR = LPDAC_TCR_SWTRG_MASK; +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* FSL_DAC12_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_edma.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_edma.c new file mode 100644 index 00000000000..b444faac9be --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_edma.c @@ -0,0 +1,2654 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_edma.h" +#if defined FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET +#include "fsl_memory.h" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.edma4" +#endif +#if defined FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET +#define CONVERT_TO_DMA_ADDRESS(addr) (MEMORY_ConvertMemoryMapAddress((uint32_t)(addr), kMEMORY_Local2DMA)) +#else +#define CONVERT_TO_DMA_ADDRESS(addr) ((uint32_t)(addr)) +#endif +#if defined(DMA_RSTS_N) +#define EDMA_RESETS_ARRAY DMA_RSTS_N +#endif +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Map transfer width. + * + * @param width transfer width. + */ +static edma_transfer_size_t EDMA_TransferWidthMapping(uint32_t width); + +/*! + * @brief validate edma errata. + * + * @param base edma base address. + * @param tcd edma transfer content descriptor. + */ +#if defined FSL_FEATURE_EDMA_HAS_ERRATA_51327 +static inline status_t EDMA_CheckErrata(EDMA_Type *base, edma_tcd_t *tcd); +#endif +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Array to map EDMA instance number to base pointer. */ +static EDMA_Type *const s_edmaBases[] = EDMA_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map EDMA instance number to clock name. */ +static const clock_ip_name_t s_edmaClockName[] = EDMA_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(EDMA_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_edmaResets[] = EDMA_RESETS_ARRAY; +#endif + +/*! @brief Array to map EDMA instance number to IRQ number. */ +static const IRQn_Type s_edmaIRQNumber[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = EDMA_CHN_IRQS; + +/*! @brief Pointers to transfer handle for each EDMA channel. */ +static edma_handle_t *s_EDMAHandle[FSL_FEATURE_SOC_EDMA_COUNT][FSL_FEATURE_EDMA_MODULE_CHANNEL]; +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t EDMA_GetInstance(EDMA_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_edmaBases); instance++) + { + if (s_edmaBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_edmaBases)); + + return instance; +} + +#if defined FSL_FEATURE_EDMA_HAS_ERRATA_51327 +static inline status_t EDMA_CheckErrata(EDMA_Type *base, edma_tcd_t *tcd) +{ + status_t status = kStatus_Success; + /* errata 51327: to use scatter gather feature, NBYTES must be multiple of 8 */ + if ((uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(base) == 1U) + { + if ((EDMA_TCD_NBYTES(tcd, EDMA_TCD_TYPE(base)) % 8U) != 0U) + { + assert(false); + status = kStatus_InvalidArgument; + } + } + + return status; +} +#endif + +/*! + * brief Push content of TCD structure into hardware TCD register. + * + * param base EDMA peripheral base address. + * param channel EDMA channel number. + * param tcd Point to TCD structure. + */ +void EDMA_InstallTCD(EDMA_Type *base, uint32_t channel, edma_tcd_t *tcd) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + assert(tcd != NULL); + + edma_tcd_t *tcdRegs = EDMA_TCD_BASE(base, channel); + +#if defined FSL_FEATURE_EDMA_HAS_ERRATA_51327 + if ((EDMA_TCD_DLAST_SGA(tcd, EDMA_TCD_TYPE(base)) != 0U) && + ((EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) & (uint16_t)DMA_CSR_ESG_MASK) != 0U) && + (EDMA_CheckErrata(base, tcd) != kStatus_Success)) + { + assert(false); + } +#endif + + /* Clear DONE bit first, otherwise ESG cannot be set */ + DMA_CLEAR_DONE_STATUS(base, channel); + /* Push tcd into hardware TCD register */ + EDMA_TCD_SADDR(tcdRegs, EDMA_TCD_TYPE(base)) = EDMA_TCD_SADDR(tcd, EDMA_TCD_TYPE(base)); + EDMA_TCD_SOFF(tcdRegs, EDMA_TCD_TYPE(base)) = EDMA_TCD_SOFF(tcd, EDMA_TCD_TYPE(base)); + EDMA_TCD_ATTR(tcdRegs, EDMA_TCD_TYPE(base)) = EDMA_TCD_ATTR(tcd, EDMA_TCD_TYPE(base)); + EDMA_TCD_NBYTES(tcdRegs, EDMA_TCD_TYPE(base)) = EDMA_TCD_NBYTES(tcd, EDMA_TCD_TYPE(base)); + EDMA_TCD_SLAST(tcdRegs, EDMA_TCD_TYPE(base)) = EDMA_TCD_SLAST(tcd, EDMA_TCD_TYPE(base)); + EDMA_TCD_DADDR(tcdRegs, EDMA_TCD_TYPE(base)) = EDMA_TCD_DADDR(tcd, EDMA_TCD_TYPE(base)); + EDMA_TCD_DOFF(tcdRegs, EDMA_TCD_TYPE(base)) = EDMA_TCD_DOFF(tcd, EDMA_TCD_TYPE(base)); + EDMA_TCD_CITER(tcdRegs, EDMA_TCD_TYPE(base)) = EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE(base)); + EDMA_TCD_DLAST_SGA(tcdRegs, EDMA_TCD_TYPE(base)) = EDMA_TCD_DLAST_SGA(tcd, EDMA_TCD_TYPE(base)); + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(base)) = EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)); + EDMA_TCD_BITER(tcdRegs, EDMA_TCD_TYPE(base)) = EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE(base)); +} + +/*! + * brief Initializes the eDMA peripheral. + * + * This function ungates the eDMA clock and configures the eDMA peripheral according + * to the configuration structure. + * + * param base eDMA peripheral base address. + * param config A pointer to the configuration structure, see "edma_config_t". + * note This function enables the minor loop map feature. + */ +void EDMA_Init(EDMA_Type *base, const edma_config_t *config) +{ + assert(config != NULL); + assert(FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base) != -1); + + uint32_t tmpreg, i = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate EDMA peripheral clock */ + CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(EDMA_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_edmaResets[EDMA_GetInstance(base)]); +#endif + +#if defined(FSL_EDMA_SOC_IP_EDMA) && FSL_EDMA_SOC_IP_EDMA + /* clear all the enabled request, status to make sure EDMA status is in normal condition */ + EDMA_BASE(base)->ERQ = 0U; + EDMA_BASE(base)->INT = 0xFFFFFFFFU; + EDMA_BASE(base)->ERR = 0xFFFFFFFFU; + /* Configure EDMA peripheral according to the configuration structure. */ + tmpreg = EDMA_BASE(base)->CR; + tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK); + tmpreg |= (DMA_CR_ERCA(config->enableRoundRobinArbitration) | DMA_CR_HOE(config->enableHaltOnError) | + DMA_CR_CLM(config->enableContinuousLinkMode) | DMA_CR_EDBG(config->enableDebugMode) | DMA_CR_EMLM(1U)); + EDMA_BASE(base)->CR = tmpreg; +#else + tmpreg = EDMA_MP_BASE(base)->MP_CSR; +#if defined FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION && FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION + tmpreg = (tmpreg & ~(DMA_MP_CSR_HAE_MASK | DMA_MP_CSR_ERCA_MASK | DMA_MP_CSR_EDBG_MASK | DMA_MP_CSR_GCLC_MASK | + DMA_MP_CSR_GMRC_MASK | DMA_MP_CSR_HALT_MASK)) | + DMA_MP_CSR_GMRC(config->enableMasterIdReplication) | DMA_MP_CSR_HAE(config->enableHaltOnError) | + DMA_MP_CSR_ERCA(config->enableRoundRobinArbitration) | DMA_MP_CSR_EDBG(config->enableDebugMode) | + DMA_MP_CSR_GCLC(config->enableGlobalChannelLink); +#else + tmpreg = (tmpreg & ~(DMA_MP_CSR_HAE_MASK | DMA_MP_CSR_ERCA_MASK | DMA_MP_CSR_EDBG_MASK | DMA_MP_CSR_GCLC_MASK | + DMA_MP_CSR_HALT_MASK)) | + DMA_MP_CSR_HAE(config->enableHaltOnError) | DMA_MP_CSR_ERCA(config->enableRoundRobinArbitration) | + DMA_MP_CSR_EDBG(config->enableDebugMode) | DMA_MP_CSR_GCLC(config->enableGlobalChannelLink); +#endif + EDMA_MP_BASE(base)->MP_CSR = tmpreg; + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG + /* channel transfer configuration */ + for (i = 0U; i < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base); i++) + { + if (config->channelConfig[i] != NULL) + { + EDMA_InitChannel(base, i, config->channelConfig[i]); + } + } +#endif +#endif +} + +/*! + * brief Deinitializes the eDMA peripheral. + * + * This function gates the eDMA clock. + * + * param base eDMA peripheral base address. + */ +void EDMA_Deinit(EDMA_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate EDMA peripheral clock */ + CLOCK_DisableClock(s_edmaClockName[EDMA_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG +/*! + * brief EDMA Channel initialization + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param channelConfig pointer to user's eDMA channel config structure, see edma_channel_config_t for detail. + */ +void EDMA_InitChannel(EDMA_Type *base, uint32_t channel, edma_channel_config_t *channelConfig) +{ + assert(channelConfig != NULL); + + EDMA_SetChannelPreemptionConfig(base, channel, &channelConfig->channelPreemptionConfig); + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE && FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE + EDMA_SetChannelSwapSize(base, channel, channelConfig->channelSwapSize); +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE && FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE + EDMA_SetChannelMemoryAttribute(base, channel, channelConfig->channelWriteMemoryAttribute, + channelConfig->channelReadMemoryAttribute); +#endif +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION && FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION + EDMA_SetChannelSignExtension(base, channel, channelConfig->channelDataSignExtensionBitPosition); +#endif +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE && FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE + EDMA_SetChannelAccessType(base, channel, channelConfig->channelAccessType); +#endif + +#if (defined FSL_FEATURE_EDMA_HAS_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) || \ + (defined FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX) + if (0U != (uint32_t)channelConfig->channelRequestSource) + { + /* dma request source */ + EDMA_SetChannelMux(base, channel, (int32_t)channelConfig->channelRequestSource); + } +#endif + + /* master ID replication */ + EDMA_EnableChannelMasterIDReplication(base, channel, channelConfig->enableMasterIDReplication); +#if !(defined(FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) && FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) + /* dma transfer security level */ + EDMA_SetChannelSecurityLevel(base, channel, channelConfig->securityLevel); +#endif + /* dma transfer protection level */ + EDMA_SetChannelProtectionLevel(base, channel, channelConfig->protectionLevel); +} +#endif + +/*! + * brief Gets the eDMA default configuration structure. + * + * This function sets the configuration structure to default values. + * The default configuration is set to the following values. + * code + * config.enableContinuousLinkMode = false; + * config.enableHaltOnError = true; + * config.enableRoundRobinArbitration = false; + * config.enableDebugMode = false; + * endcode + * + * param config A pointer to the eDMA configuration structure. + */ +void EDMA_GetDefaultConfig(edma_config_t *config) +{ + assert(config != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enableRoundRobinArbitration = false; + + config->enableHaltOnError = true; + +#if defined FSL_FEATURE_EDMA_HAS_CONTINUOUS_LINK_MODE && FSL_FEATURE_EDMA_HAS_CONTINUOUS_LINK_MODE + config->enableContinuousLinkMode = false; +#endif + +#if defined FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION && FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION + config->enableMasterIdReplication = false; +#endif + + config->enableDebugMode = false; + + config->enableGlobalChannelLink = true; +} + +/*! + * brief Sets all TCD registers to default values. + * + * This function sets TCD registers for this channel to default values. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * note This function must not be called while the channel transfer is ongoing + * or it causes unpredictable results. + * note This function enables the auto stop request feature. + */ +void EDMA_ResetChannel(EDMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + /* reset channel CSR */ + EDMA_ClearChannelStatusFlags(base, channel, (uint32_t)kEDMA_DoneFlag | (uint32_t)kEDMA_ErrorFlag); + /* reset channel TCD */ + EDMA_TcdResetExt(base, EDMA_TCD_BASE(base, channel)); +} + +/*! + * brief Configures the eDMA transfer attribute. + * + * This function configures the transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the TCD address. + * Example: + * code + * edma_transfer_t config; + * edma_tcd_t tcd; + * config.srcAddr = ..; + * config.destAddr = ..; + * ... + * EDMA_SetTransferConfig(DMA0, channel, &config, &stcd); + * endcode + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param config Pointer to eDMA transfer configuration structure. + * param nextTcd Point to TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * note If nextTcd is not NULL, it means scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the eDMA_ResetChannel. + */ +void EDMA_SetTransferConfig(EDMA_Type *base, + uint32_t channel, + const edma_transfer_config_t *config, + edma_tcd_t *nextTcd) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + assert(config != NULL); + + EDMA_TcdSetTransferConfigExt(base, EDMA_TCD_BASE(base, channel), config, + (edma_tcd_t *)CONVERT_TO_DMA_ADDRESS(nextTcd)); +} + +/*! + * brief Configures the eDMA minor offset feature. + * + * The minor offset means that the signed-extended value is added to the source address or destination + * address after each minor loop. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param config A pointer to the minor offset configuration structure. + */ +void EDMA_SetMinorOffsetConfig(EDMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + assert(config != NULL); + + uint32_t tmpreg; + + tmpreg = EDMA_TCD_NBYTES(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)); + tmpreg &= ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); + tmpreg |= + (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | + DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); + EDMA_TCD_NBYTES(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) = tmpreg; +} + +/*! + * brief Configures the eDMA channel TCD major offset feature. + * + * Adjustment value added to the source address at the completion of the major iteration count + * + * param base eDMA peripheral base address. + * param channel edma channel number. + * param sourceOffset source address offset. + * param destOffset destination address offset. + */ +void EDMA_SetMajorOffsetConfig(EDMA_Type *base, uint32_t channel, int32_t sourceOffset, int32_t destOffset) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + EDMA_TCD_SLAST(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) = (uint32_t)sourceOffset; + EDMA_TCD_DLAST_SGA(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) = (uint32_t)destOffset; +} + +/*! + * brief Configures the eDMA channel preemption feature. + * + * This function configures the channel preemption attribute and the priority of the channel. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number + * param config A pointer to the channel preemption configuration structure. + */ +void EDMA_SetChannelPreemptionConfig(EDMA_Type *base, uint32_t channel, const edma_channel_Preemption_config_t *config) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + assert(config != NULL); + + bool tmpEnablePreemptAbility = config->enablePreemptAbility; + bool tmpEnablchannelPreemption = config->enableChannelPreemption; + uint8_t tmpChannelPriority = config->channelPriority; + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + + volatile uint8_t *tmpReg = &EDMA_BASE(base)->DCHPRI3; + + ((volatile uint8_t *)tmpReg)[DMA_DCHPRI_INDEX(channel)] = + (DMA_DCHPRI0_DPA((true == tmpEnablePreemptAbility ? 0U : 1U)) | + DMA_DCHPRI0_ECP((true == tmpEnablchannelPreemption ? 1U : 0U)) | DMA_DCHPRI0_CHPRI(tmpChannelPriority)); +#else + EDMA_CHANNEL_BASE(base, channel)->CH_PRI = DMA_CH_PRI_ECP(tmpEnablchannelPreemption) | + DMA_CH_PRI_DPA(tmpEnablePreemptAbility) | + DMA_CH_PRI_APL(tmpChannelPriority); +#endif +} + +/*! + * brief Sets the channel link for the eDMA transfer. + * + * This function configures either the minor link or the major link mode. The minor link means that the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param type A channel link type, which can be one of the following: + * arg kEDMA_LinkNone + * arg kEDMA_MinorLink + * arg kEDMA_MajorLink + * param linkedChannel The linked channel number. + * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + */ +void EDMA_SetChannelLink(EDMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + EDMA_TcdSetChannelLinkExt(base, EDMA_TCD_BASE(base, channel), type, linkedChannel); +} + +#if defined FSL_FEATURE_EDMA_HAS_BANDWIDTH && FSL_FEATURE_EDMA_HAS_BANDWIDTH +/*! + * brief Sets the bandwidth for the eDMA transfer. + * + * Because the eDMA processes the minor loop, it continuously generates read/write sequences + * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of + * each read/write access to control the bus request bandwidth seen by the crossbar switch. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param bandWidth A bandwidth setting, which can be one of the following: + * arg kEDMABandwidthStallNone + * arg kEDMABandwidthStall4Cycle + * arg kEDMABandwidthStall8Cycle + */ +void EDMA_SetBandWidth(EDMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) = + (uint16_t)((EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) & (~DMA_CSR_BWC_MASK)) | + DMA_CSR_BWC(bandWidth)); +} +#endif + +/*! + * brief Sets the source modulo and the destination modulo for the eDMA transfer. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param srcModulo A source modulo value. + * param destModulo A destination modulo value. + */ +void EDMA_SetModulo(EDMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + uint16_t tmpreg = EDMA_TCD_ATTR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) & + (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + EDMA_TCD_ATTR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) = + tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); +} + +/*! + * brief Sets all fields to default values for the TCD structure. + * + * This function sets all fields for this TCD structure to default value. + * + * param base eDMA peripheral base address. + * param tcd Pointer to the TCD structure. + * note This function enables the auto stop request feature. + */ +void EDMA_TcdResetExt(EDMA_Type *base, edma_tcd_t *tcd) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + /* Reset channel TCD */ + EDMA_TCD_SADDR(tcd, EDMA_TCD_TYPE(base)) = 0U; + EDMA_TCD_SOFF(tcd, EDMA_TCD_TYPE(base)) = 0U; + EDMA_TCD_ATTR(tcd, EDMA_TCD_TYPE(base)) = 0U; + EDMA_TCD_NBYTES(tcd, EDMA_TCD_TYPE(base)) = 0U; + EDMA_TCD_SLAST(tcd, EDMA_TCD_TYPE(base)) = 0U; + EDMA_TCD_DADDR(tcd, EDMA_TCD_TYPE(base)) = 0U; + EDMA_TCD_DOFF(tcd, EDMA_TCD_TYPE(base)) = 0U; + EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE(base)) = 0U; + EDMA_TCD_DLAST_SGA(tcd, EDMA_TCD_TYPE(base)) = 0U; + /* Enable auto disable request feature */ + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) = DMA_CSR_DREQ(1U); + EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE(base)) = 0U; +} + +/*! + * brief Configures the eDMA TCD transfer attribute. + * + * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. + * The TCD is used in the scatter-gather mode. + * This function configures the TCD transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the next TCD address. + * Example: + * code + * edma_transfer_t config = { + * ... + * } + * edma_tcd_t tcd __aligned(32); + * edma_tcd_t nextTcd __aligned(32); + * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd); + * endcode + * + * param base eDMA peripheral base address. + * param tcd Pointer to the TCD structure. + * param config Pointer to eDMA transfer configuration structure. + * param nextTcd Pointer to the next TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * note TCD address should be 32 bytes aligned or it causes an eDMA error. + * note If the nextTcd is not NULL, the scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the EDMA_TcdReset. + */ +void EDMA_TcdSetTransferConfigExt(EDMA_Type *base, + edma_tcd_t *tcd, + const edma_transfer_config_t *config, + edma_tcd_t *nextTcd) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + assert(config != NULL); + + EDMA_ConfigChannelSoftwareTCDExt(base, tcd, config); + + if (nextTcd != NULL) + { + EDMA_TCD_DLAST_SGA(tcd, EDMA_TCD_TYPE(base)) = CONVERT_TO_DMA_ADDRESS(nextTcd); + /* + Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig, + user must call EDMA_TcdReset or EDMA_ResetChannel which will set + DREQ, so must use "|" or "&" rather than "=". + + Clear the DREQ bit because scatter gather has been enabled, so the + previous transfer is not the last transfer, and channel request should + be enabled at the next transfer(the next TCD). + */ + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) = + (EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MASK; + } +} + +/*! + * brief Sets TCD fields according to the user's channel transfer configuration structure, see + * edma_transfer_config_t. + * + * Application should be careful about the TCD pool buffer storage class, + * - For the platform has cache, the software TCD should be put in non cache section + * - The TCD pool buffer should have a consistent storage class. + * + * param base eDMA peripheral base address. + * param tcd Pointer to the TCD structure. + * param transfer channel transfer configuration pointer. + * + */ +void EDMA_ConfigChannelSoftwareTCDExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_transfer_config_t *transfer) +{ + assert(transfer != NULL); + assert((transfer->minorLoopBytes % (1UL << ((uint32_t)transfer->srcTransferSize))) == 0U); + assert((transfer->minorLoopBytes % (1UL << ((uint32_t)transfer->destTransferSize))) == 0U); + assert(((uint32_t)transfer->srcOffset % (1UL << ((uint32_t)transfer->srcTransferSize))) == 0U); + assert(((uint32_t)transfer->destOffset % (1UL << ((uint32_t)transfer->destTransferSize))) == 0U); + assert((transfer->srcAddr % (1UL << ((uint32_t)transfer->srcTransferSize))) == 0U); + assert((transfer->destAddr % (1UL << ((uint32_t)transfer->destTransferSize))) == 0U); + assert((transfer->srcAddr % (1UL << ((uint32_t)transfer->srcAddrModulo))) == 0U); + assert((transfer->destAddr % (1UL << ((uint32_t)transfer->dstAddrModulo))) == 0U); + + uint16_t tmpreg; + + EDMA_TCD_SADDR(tcd, EDMA_TCD_TYPE(base)) = CONVERT_TO_DMA_ADDRESS(transfer->srcAddr); + /* destination address */ + EDMA_TCD_DADDR(tcd, EDMA_TCD_TYPE(base)) = CONVERT_TO_DMA_ADDRESS(transfer->destAddr); + /* Source data and destination data transfer size */ + EDMA_TCD_ATTR(tcd, EDMA_TCD_TYPE(base)) = + DMA_ATTR_SSIZE(transfer->srcTransferSize) | DMA_ATTR_DSIZE(transfer->destTransferSize); + + /* Source address signed offset */ + EDMA_TCD_SOFF(tcd, EDMA_TCD_TYPE(base)) = (uint16_t)(transfer->srcOffset); + /* Destination address signed offset */ + EDMA_TCD_DOFF(tcd, EDMA_TCD_TYPE(base)) = (uint16_t)(transfer->destOffset); + + if (((transfer->enableSrcMinorLoopOffset) || (transfer->enableDstMinorLoopOffset))) + { + EDMA_TCD_NBYTES(tcd, EDMA_TCD_TYPE(base)) = DMA_NBYTES_MLOFFYES_NBYTES(transfer->minorLoopBytes) | + DMA_NBYTES_MLOFFYES_MLOFF(transfer->minorLoopOffset) | + DMA_NBYTES_MLOFFYES_DMLOE(transfer->enableDstMinorLoopOffset) | + DMA_NBYTES_MLOFFYES_SMLOE(transfer->enableSrcMinorLoopOffset); + } + else + { + EDMA_TCD_NBYTES(tcd, EDMA_TCD_TYPE(base)) = DMA_NBYTES_MLOFFNO_NBYTES(transfer->minorLoopBytes); + } + + /* Current major iteration count */ + EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE(base)) = (uint16_t)(transfer->majorLoopCounts); + /* Starting major iteration count */ + EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE(base)) = (uint16_t)(transfer->majorLoopCounts); + /* reset CSR firstly */ + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) = DMA_CSR_DREQ(1U); + /* Enable scatter/gather processing */ + if (transfer->linkTCD != NULL) + { + EDMA_TCD_DLAST_SGA(tcd, EDMA_TCD_TYPE(base)) = CONVERT_TO_DMA_ADDRESS((uint32_t)((uint8_t *)transfer->linkTCD)); + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) = + (EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MASK; + } + else + { + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_ESG_MASK; + EDMA_TCD_DLAST_SGA(tcd, EDMA_TCD_TYPE(base)) = (uint32_t)transfer->dstMajorLoopOffset; + } + + /* configure interrupt/auto disable channel request */ + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) |= (transfer->enabledInterruptMask & (~(uint16_t)kEDMA_ErrorInterruptEnable)); + + /* Minor link config */ + if (transfer->enableChannelMinorLoopLink) + { + /* Enable minor link */ + EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE(base)) |= DMA_CITER_ELINKYES_ELINK_MASK; + EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE(base)) |= DMA_BITER_ELINKYES_ELINK_MASK; + /* Set linked channel */ + tmpreg = EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE(base)) & (~(uint16_t)DMA_CITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_CITER_ELINKYES_LINKCH(transfer->minorLoopLinkChannel); + EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE(base)) = tmpreg; + tmpreg = EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE(base)) & (~(uint16_t)DMA_BITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_BITER_ELINKYES_LINKCH(transfer->minorLoopLinkChannel); + EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE(base)) = tmpreg; + } + /* Major link config */ + if (transfer->enableChannelMajorLoopLink) + { + /* Enable major link */ + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) |= DMA_CSR_MAJORELINK_MASK; + /* Set major linked channel */ + tmpreg = EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) & (~(uint16_t)DMA_CSR_MAJORLINKCH_MASK); + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) = tmpreg | DMA_CSR_MAJORLINKCH(transfer->majorLoopLinkChannel); + } + + /* clear link relate field if no channel link enabled */ + if ((!transfer->enableChannelMajorLoopLink) && (!transfer->enableChannelMinorLoopLink)) + { + EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CITER_ELINKYES_ELINK_MASK; + EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_BITER_ELINKYES_ELINK_MASK; + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_MAJORELINK_MASK; + } + + /* major loop offset */ + EDMA_TCD_SLAST(tcd, EDMA_TCD_TYPE(base)) = (uint32_t)transfer->srcMajorLoopOffset; + /* modulo feature */ + tmpreg = EDMA_TCD_ATTR(tcd, EDMA_TCD_TYPE(base)) & (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + EDMA_TCD_ATTR(tcd, EDMA_TCD_TYPE(base)) = + tmpreg | DMA_ATTR_DMOD(transfer->dstAddrModulo) | DMA_ATTR_SMOD(transfer->srcAddrModulo); +} + +/*! + * brief Configures the eDMA TCD minor offset feature. + * + * A minor offset is a signed-extended value added to the source address or a destination + * address after each minor loop. + * + * param base eDMA peripheral base address. + * param tcd A point to the TCD structure. + * param config A pointer to the minor offset configuration structure. + */ +void EDMA_TcdSetMinorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_minor_offset_config_t *config) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + uint32_t tmpreg; + + tmpreg = EDMA_TCD_NBYTES(tcd, EDMA_TCD_TYPE(base)) & + ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); + tmpreg |= + (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | + DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); + EDMA_TCD_NBYTES(tcd, EDMA_TCD_TYPE(base)) = tmpreg; +} + +/*! + * brief Configures the eDMA TCD major offset feature. + * + * Adjustment value added to the source address at the completion of the major iteration count + * + * param base eDMA peripheral base address. + * param tcd A point to the TCD structure. + * param sourceOffset source address offset. + * param destOffset destination address offset. + */ +void EDMA_TcdSetMajorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + EDMA_TCD_SLAST(tcd, EDMA_TCD_TYPE(base)) = (uint32_t)sourceOffset; + EDMA_TCD_DLAST_SGA(tcd, EDMA_TCD_TYPE(base)) = (uint32_t)destOffset; +} + +/*! + * brief Sets the channel link for the eDMA TCD. + * + * This function configures either a minor link or a major link. The minor link means the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + * param base eDMA peripheral base address. + * param tcd Point to the TCD structure. + * param type Channel link type, it can be one of: + * arg kEDMA_LinkNone + * arg kEDMA_MinorLink + * arg kEDMA_MajorLink + * param linkedChannel The linked channel number. + */ +void EDMA_TcdSetChannelLinkExt(EDMA_Type *base, edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); + + if (type == kEDMA_MinorLink) /* Minor link config */ + { + uint16_t tmpreg; + + /* Enable minor link */ + EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE(base)) |= DMA_CITER_ELINKYES_ELINK_MASK; + EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE(base)) |= DMA_BITER_ELINKYES_ELINK_MASK; + /* Set linked channel */ + tmpreg = EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE(base)) & (~(uint16_t)DMA_CITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel); + EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE(base)) = tmpreg; + tmpreg = EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE(base)) & (~(uint16_t)DMA_BITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel); + EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE(base)) = tmpreg; + } + else if (type == kEDMA_MajorLink) /* Major link config */ + { + uint16_t tmpreg; + + /* Enable major link */ + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) |= DMA_CSR_MAJORELINK_MASK; + /* Set major linked channel */ + tmpreg = EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) & (~(uint16_t)DMA_CSR_MAJORLINKCH_MASK); + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel); + } + else /* Link none */ + { + EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CITER_ELINKYES_ELINK_MASK; + EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_BITER_ELINKYES_ELINK_MASK; + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_MAJORELINK_MASK; + } +} + +/*! + * brief Sets the source modulo and the destination modulo for the eDMA TCD. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * param base eDMA peripheral base address. + * param tcd A pointer to the TCD structure. + * param srcModulo A source modulo value. + * param destModulo A destination modulo value. + */ +void EDMA_TcdSetModuloExt(EDMA_Type *base, edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + uint16_t tmpreg; + + tmpreg = EDMA_TCD_ATTR(tcd, EDMA_TCD_TYPE(base)) & (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + EDMA_TCD_ATTR(tcd, EDMA_TCD_TYPE(base)) = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); +} + +/*! + * brief Enables the interrupt source for the eDMA TCD. + * + * param base eDMA peripheral base address. + * param tcd Point to the TCD structure. + * param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdEnableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask) +{ + assert(tcd != NULL); + + /* Enable Major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) + { + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) |= DMA_CSR_INTMAJOR_MASK; + } + + /* Enable Half major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) + { + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) |= DMA_CSR_INTHALF_MASK; + } +} + +/*! + * brief Disables the interrupt source for the eDMA TCD. + * + * param base eDMA peripheral base address. + * param tcd Point to the TCD structure. + * param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdDisableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask) +{ + assert(tcd != NULL); + + /* Disable Major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) + { + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK; + } + + /* Disable Half major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) + { + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_INTHALF_MASK; + } +} + +/*! + * brief Sets all fields to default values for the TCD structure. + * + * Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API ref + * EDMA_TcdResetExt + * + * This function sets all fields for this TCD structure to default value. + * + * param tcd Pointer to the TCD structure. + * note This function enables the auto stop request feature. + */ +void EDMA_TcdReset(edma_tcd_t *tcd) +{ + assert(tcd != NULL); + + /* Reset channel TCD */ + EDMA_TCD_SADDR(tcd, kEDMA_EDMA4Flag) = 0U; + EDMA_TCD_SOFF(tcd, kEDMA_EDMA4Flag) = 0U; + EDMA_TCD_ATTR(tcd, kEDMA_EDMA4Flag) = 0U; + EDMA_TCD_NBYTES(tcd, kEDMA_EDMA4Flag) = 0U; + EDMA_TCD_SLAST(tcd, kEDMA_EDMA4Flag) = 0U; + EDMA_TCD_DADDR(tcd, kEDMA_EDMA4Flag) = 0U; + EDMA_TCD_DOFF(tcd, kEDMA_EDMA4Flag) = 0U; + EDMA_TCD_CITER(tcd, kEDMA_EDMA4Flag) = 0U; + EDMA_TCD_DLAST_SGA(tcd, kEDMA_EDMA4Flag) = 0U; + /* Enable auto disable request feature */ + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) = DMA_CSR_DREQ(1U); + EDMA_TCD_BITER(tcd, kEDMA_EDMA4Flag) = 0U; +} + +/*! + * brief Configures the eDMA TCD transfer attribute. + * + * Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API ref + * EDMA_TcdSetTransferConfigExt + * + * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. + * The TCD is used in the scatter-gather mode. + * This function configures the TCD transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the next TCD address. + * Example: + * code + * edma_transfer_t config = { + * ... + * } + * edma_tcd_t tcd __aligned(32); + * edma_tcd_t nextTcd __aligned(32); + * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd); + * endcode + * + * param tcd Pointer to the TCD structure. + * param config Pointer to eDMA transfer configuration structure. + * param nextTcd Pointer to the next TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * note TCD address should be 32 bytes aligned or it causes an eDMA error. + * note If the nextTcd is not NULL, the scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the EDMA_TcdReset. + */ +void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd) +{ + assert(tcd != NULL); + assert(config != NULL); + + EDMA_ConfigChannelSoftwareTCD(tcd, config); + + if (nextTcd != NULL) + { + EDMA_TCD_DLAST_SGA(tcd, kEDMA_EDMA4Flag) = CONVERT_TO_DMA_ADDRESS(nextTcd); + /* + Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig, + user must call EDMA_TcdReset or EDMA_ResetChannel which will set + DREQ, so must use "|" or "&" rather than "=". + + Clear the DREQ bit because scatter gather has been enabled, so the + previous transfer is not the last transfer, and channel request should + be enabled at the next transfer(the next TCD). + */ + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) = + (EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MASK; + } +} + +/*! + * brief Sets TCD fields according to the user's channel transfer configuration structure, see + * edma_transfer_config_t. + * + * Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API ref + * EDMA_ConfigChannelSoftwareTCDExt + * + * Application should be careful about the TCD pool buffer storage class, + * - For the platform has cache, the software TCD should be put in non cache section + * - The TCD pool buffer should have a consistent storage class. + * + * param tcd Pointer to the TCD structure. + * param transfer channel transfer configuration pointer. + * + */ +void EDMA_ConfigChannelSoftwareTCD(edma_tcd_t *tcd, const edma_transfer_config_t *transfer) +{ + assert(transfer != NULL); + assert((transfer->minorLoopBytes % (1UL << ((uint32_t)transfer->srcTransferSize))) == 0U); + assert((transfer->minorLoopBytes % (1UL << ((uint32_t)transfer->destTransferSize))) == 0U); + assert(((uint32_t)transfer->srcOffset % (1UL << ((uint32_t)transfer->srcTransferSize))) == 0U); + assert(((uint32_t)transfer->destOffset % (1UL << ((uint32_t)transfer->destTransferSize))) == 0U); + assert((transfer->srcAddr % (1UL << ((uint32_t)transfer->srcTransferSize))) == 0U); + assert((transfer->destAddr % (1UL << ((uint32_t)transfer->destTransferSize))) == 0U); + assert((transfer->srcAddr % (1UL << ((uint32_t)transfer->srcAddrModulo))) == 0U); + assert((transfer->destAddr % (1UL << ((uint32_t)transfer->dstAddrModulo))) == 0U); + + uint16_t tmpreg; + + EDMA_TCD_SADDR(tcd, kEDMA_EDMA4Flag) = CONVERT_TO_DMA_ADDRESS(transfer->srcAddr); + /* destination address */ + EDMA_TCD_DADDR(tcd, kEDMA_EDMA4Flag) = CONVERT_TO_DMA_ADDRESS(transfer->destAddr); + /* Source data and destination data transfer size */ + EDMA_TCD_ATTR(tcd, kEDMA_EDMA4Flag) = + DMA_ATTR_SSIZE(transfer->srcTransferSize) | DMA_ATTR_DSIZE(transfer->destTransferSize); + + /* Source address signed offset */ + EDMA_TCD_SOFF(tcd, kEDMA_EDMA4Flag) = (uint16_t)(transfer->srcOffset); + /* Destination address signed offset */ + EDMA_TCD_DOFF(tcd, kEDMA_EDMA4Flag) = (uint16_t)(transfer->destOffset); + + if (((transfer->enableSrcMinorLoopOffset) || (transfer->enableDstMinorLoopOffset))) + { + EDMA_TCD_NBYTES(tcd, kEDMA_EDMA4Flag) = DMA_NBYTES_MLOFFYES_NBYTES(transfer->minorLoopBytes) | + DMA_NBYTES_MLOFFYES_MLOFF(transfer->minorLoopOffset) | + DMA_NBYTES_MLOFFYES_DMLOE(transfer->enableDstMinorLoopOffset) | + DMA_NBYTES_MLOFFYES_SMLOE(transfer->enableSrcMinorLoopOffset); + } + else + { + EDMA_TCD_NBYTES(tcd, kEDMA_EDMA4Flag) = DMA_NBYTES_MLOFFNO_NBYTES(transfer->minorLoopBytes); + } + + /* Current major iteration count */ + EDMA_TCD_CITER(tcd, kEDMA_EDMA4Flag) = (uint16_t)(transfer->majorLoopCounts); + /* Starting major iteration count */ + EDMA_TCD_BITER(tcd, kEDMA_EDMA4Flag) = (uint16_t)(transfer->majorLoopCounts); + /* reset CSR firstly */ + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) = DMA_CSR_DREQ(1U); + /* Enable scatter/gather processing */ + if (transfer->linkTCD != NULL) + { + EDMA_TCD_DLAST_SGA(tcd, kEDMA_EDMA4Flag) = CONVERT_TO_DMA_ADDRESS((uint32_t)((uint8_t *)transfer->linkTCD)); + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) = + (EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MASK; + } + else + { + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) &= ~(uint16_t)DMA_CSR_ESG_MASK; + EDMA_TCD_DLAST_SGA(tcd, kEDMA_EDMA4Flag) = (uint32_t)transfer->dstMajorLoopOffset; + } + + /* configure interrupt/auto disable channel request */ + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) |= (transfer->enabledInterruptMask & (~(uint16_t)kEDMA_ErrorInterruptEnable)); + + /* Minor link config */ + if (transfer->enableChannelMinorLoopLink) + { + /* Enable minor link */ + EDMA_TCD_CITER(tcd, kEDMA_EDMA4Flag) |= DMA_CITER_ELINKYES_ELINK_MASK; + EDMA_TCD_BITER(tcd, kEDMA_EDMA4Flag) |= DMA_BITER_ELINKYES_ELINK_MASK; + /* Set linked channel */ + tmpreg = EDMA_TCD_CITER(tcd, kEDMA_EDMA4Flag) & (~(uint16_t)DMA_CITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_CITER_ELINKYES_LINKCH(transfer->minorLoopLinkChannel); + EDMA_TCD_CITER(tcd, kEDMA_EDMA4Flag) = tmpreg; + tmpreg = EDMA_TCD_BITER(tcd, kEDMA_EDMA4Flag) & (~(uint16_t)DMA_BITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_BITER_ELINKYES_LINKCH(transfer->minorLoopLinkChannel); + EDMA_TCD_BITER(tcd, kEDMA_EDMA4Flag) = tmpreg; + } + /* Major link config */ + if (transfer->enableChannelMajorLoopLink) + { + /* Enable major link */ + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) |= DMA_CSR_MAJORELINK_MASK; + /* Set major linked channel */ + tmpreg = EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) & (~(uint16_t)DMA_CSR_MAJORLINKCH_MASK); + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) = tmpreg | DMA_CSR_MAJORLINKCH(transfer->majorLoopLinkChannel); + } + + /* clear link relate field if no channel link enabled */ + if ((!transfer->enableChannelMajorLoopLink) && (!transfer->enableChannelMinorLoopLink)) + { + EDMA_TCD_CITER(tcd, kEDMA_EDMA4Flag) &= ~(uint16_t)DMA_CITER_ELINKYES_ELINK_MASK; + EDMA_TCD_BITER(tcd, kEDMA_EDMA4Flag) &= ~(uint16_t)DMA_BITER_ELINKYES_ELINK_MASK; + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) &= ~(uint16_t)DMA_CSR_MAJORELINK_MASK; + } + + /* major loop offset */ + EDMA_TCD_SLAST(tcd, kEDMA_EDMA4Flag) = (uint32_t)transfer->srcMajorLoopOffset; + /* modulo feature */ + tmpreg = EDMA_TCD_ATTR(tcd, kEDMA_EDMA4Flag) & (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + EDMA_TCD_ATTR(tcd, kEDMA_EDMA4Flag) = + tmpreg | DMA_ATTR_DMOD(transfer->dstAddrModulo) | DMA_ATTR_SMOD(transfer->srcAddrModulo); +} + +/*! + * brief Configures the eDMA TCD minor offset feature. + * + * Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API ref + * EDMA_TcdSetMinorOffsetConfigExt + * + * A minor offset is a signed-extended value added to the source address or a destination + * address after each minor loop. + * + * param tcd A point to the TCD structure. + * param config A pointer to the minor offset configuration structure. + */ +void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config) +{ + assert(tcd != NULL); + + uint32_t tmpreg; + + tmpreg = EDMA_TCD_NBYTES(tcd, kEDMA_EDMA4Flag) & + ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK); + tmpreg |= + (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) | + DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset)); + EDMA_TCD_NBYTES(tcd, kEDMA_EDMA4Flag) = tmpreg; +} + +/*! + * brief Configures the eDMA TCD major offset feature. + * + * Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API ref + * EDMA_TcdSetMajorOffsetConfigExt + * + * Adjustment value added to the source address at the completion of the major iteration count + * + * param tcd A point to the TCD structure. + * param sourceOffset source address offset. + * param destOffset destination address offset. + */ +void EDMA_TcdSetMajorOffsetConfig(edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset) +{ + assert(tcd != NULL); + + EDMA_TCD_SLAST(tcd, kEDMA_EDMA4Flag) = (uint32_t)sourceOffset; + EDMA_TCD_DLAST_SGA(tcd, kEDMA_EDMA4Flag) = (uint32_t)destOffset; +} + +/*! + * brief Sets the channel link for the eDMA TCD. + * + * Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API ref + * EDMA_TcdSetChannelLinkExt + * + * This function configures either a minor link or a major link. The minor link means the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + * param tcd Point to the TCD structure. + * param type Channel link type, it can be one of: + * arg kEDMA_LinkNone + * arg kEDMA_MinorLink + * arg kEDMA_MajorLink + * param linkedChannel The linked channel number. + */ +void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel) +{ + assert(tcd != NULL); + assert(linkedChannel < (uint32_t)FSL_FEATURE_EDMA_MODULE_CHANNEL); + + if (type == kEDMA_MinorLink) /* Minor link config */ + { + uint16_t tmpreg; + + /* Enable minor link */ + EDMA_TCD_CITER(tcd, kEDMA_EDMA4Flag) |= DMA_CITER_ELINKYES_ELINK_MASK; + EDMA_TCD_BITER(tcd, kEDMA_EDMA4Flag) |= DMA_BITER_ELINKYES_ELINK_MASK; + /* Set linked channel */ + tmpreg = EDMA_TCD_CITER(tcd, kEDMA_EDMA4Flag) & (~(uint16_t)DMA_CITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel); + EDMA_TCD_CITER(tcd, kEDMA_EDMA4Flag) = tmpreg; + tmpreg = EDMA_TCD_BITER(tcd, kEDMA_EDMA4Flag) & (~(uint16_t)DMA_BITER_ELINKYES_LINKCH_MASK); + tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel); + EDMA_TCD_BITER(tcd, kEDMA_EDMA4Flag) = tmpreg; + } + else if (type == kEDMA_MajorLink) /* Major link config */ + { + uint16_t tmpreg; + + /* Enable major link */ + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) |= DMA_CSR_MAJORELINK_MASK; + /* Set major linked channel */ + tmpreg = EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) & (~(uint16_t)DMA_CSR_MAJORLINKCH_MASK); + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel); + } + else /* Link none */ + { + EDMA_TCD_CITER(tcd, kEDMA_EDMA4Flag) &= ~(uint16_t)DMA_CITER_ELINKYES_ELINK_MASK; + EDMA_TCD_BITER(tcd, kEDMA_EDMA4Flag) &= ~(uint16_t)DMA_BITER_ELINKYES_ELINK_MASK; + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) &= ~(uint16_t)DMA_CSR_MAJORELINK_MASK; + } +} + +/*! + * brief Sets the source modulo and the destination modulo for the eDMA TCD. + * + * Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API ref + * EDMA_TcdSetModuloExt + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * param tcd A pointer to the TCD structure. + * param srcModulo A source modulo value. + * param destModulo A destination modulo value. + */ +void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo) +{ + assert(tcd != NULL); + + uint16_t tmpreg; + + tmpreg = EDMA_TCD_ATTR(tcd, kEDMA_EDMA4Flag) & (~(uint16_t)(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK)); + EDMA_TCD_ATTR(tcd, kEDMA_EDMA4Flag) = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo); +} + +/*! + * brief Enables the interrupt source for the eDMA TCD. + * + * Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API ref + * EDMA_TcdEnableInterruptsExt + * + * param tcd Point to the TCD structure. + * param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask) +{ + assert(tcd != NULL); + + /* Enable Major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) + { + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) |= DMA_CSR_INTMAJOR_MASK; + } + + /* Enable Half major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) + { + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) |= DMA_CSR_INTHALF_MASK; + } +} + +/*! + * brief Disables the interrupt source for the eDMA TCD. + * + * Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API ref + * EDMA_TcdDisableInterruptsExt + * + * param tcd Point to the TCD structure. + * param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask) +{ + assert(tcd != NULL); + + /* Disable Major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) + { + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK; + } + + /* Disable Half major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) + { + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) &= ~(uint16_t)DMA_CSR_INTHALF_MASK; + } +} + +/*! + * brief Gets the remaining major loop count from the eDMA current channel TCD. + * + * This function checks the TCD (Task Control Descriptor) status for a specified + * eDMA channel and returns the number of major loop count that has not finished. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * return Major loop count which has not been transferred yet for the current TCD. + * note 1. This function can only be used to get unfinished major loop count of transfer without + * the next TCD, or it might be inaccuracy. + * 2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while + * the channel is running. + * Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO + * register is needed while the eDMA IP does not support getting it while a channel is active. + * In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine + * is working with while a channel is running. + * Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example + * copied before enabling the channel) is needed. The formula to calculate it is shown below: + * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured) + */ +uint32_t EDMA_GetRemainingMajorLoopCount(EDMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + uint32_t remainingCount = 0; + + if (0U != DMA_GET_DONE_STATUS(base, channel)) + { + remainingCount = 0; + } + else + { + /* Calculate the unfinished bytes */ + if (0U != (EDMA_TCD_CITER(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) & DMA_CITER_ELINKNO_ELINK_MASK)) + { + remainingCount = (((uint32_t)EDMA_TCD_CITER(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) & + DMA_CITER_ELINKYES_CITER_MASK) >> + DMA_CITER_ELINKYES_CITER_SHIFT); + } + else + { + remainingCount = (((uint32_t)EDMA_TCD_CITER(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) & + DMA_CITER_ELINKNO_CITER_MASK) >> + DMA_CITER_ELINKNO_CITER_SHIFT); + } + } + + return remainingCount; +} + +/*! + * brief Enables the interrupt source for the eDMA transfer. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_EnableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + /* Enable error interrupt */ + if (0U != (mask & (uint32_t)kEDMA_ErrorInterruptEnable)) + { + DMA_ENABLE_ERROR_INT(base, channel); + } + + /* Enable Major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) + { + DMA_ENABLE_MAJOR_INT(base, channel); + } + + /* Enable Half major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) + { + DMA_ENABLE_HALF_INT(base, channel); + } +} + +/*! + * brief Disables the interrupt source for the eDMA transfer. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param mask The mask of the interrupt source to be set. Use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_DisableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + /* Disable error interrupt */ + if (0U != (mask & (uint32_t)kEDMA_ErrorInterruptEnable)) + { + DMA_DISABLE_ERROR_INT(base, channel); + } + + /* Disable Major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_MajorInterruptEnable)) + { + DMA_DISABLE_MAJOR_INT(base, channel); + } + + /* Disable Half major interrupt */ + if (0U != (mask & (uint32_t)kEDMA_HalfInterruptEnable)) + { + DMA_DISABLE_HALF_INT(base, channel); + } +} + +/*! + * brief Gets the eDMA channel status flags. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * return The mask of channel status flags. Users need to use the + * _edma_channel_status_flags type to decode the return variables. + */ +uint32_t EDMA_GetChannelStatusFlags(EDMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + uint32_t retval = 0; + + /* Get DONE bit flag */ + retval |= DMA_GET_DONE_STATUS(base, channel); + /* Get ERROR bit flag */ + retval |= (DMA_GET_ERROR_STATUS(base, channel) << 1U); + /* Get INT bit flag */ + retval |= (DMA_GET_INT_STATUS(base, channel) << 2U); + + return retval; +} + +/*! + * brief Clears the eDMA channel status flags. + * + * param base eDMA peripheral base address. + * param channel eDMA channel number. + * param mask The mask of channel status to be cleared. Users need to use + * the defined _edma_channel_status_flags type. + */ +void EDMA_ClearChannelStatusFlags(EDMA_Type *base, uint32_t channel, uint32_t mask) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + /* Clear DONE bit flag */ + if (0U != (mask & (uint32_t)kEDMA_DoneFlag)) + { + DMA_CLEAR_DONE_STATUS(base, channel); + } + /* Clear ERROR bit flag */ + if (0U != (mask & (uint32_t)kEDMA_ErrorFlag)) + { + DMA_CLEAR_ERROR_STATUS(base, channel); + } + /* Clear INT bit flag */ + if (0U != (mask & (uint32_t)kEDMA_InterruptFlag)) + { + DMA_CLEAR_INT_STATUS(base, channel); + } +} + +/*! + * brief Creates the eDMA handle. + * + * This function is called if using the transactional API for eDMA. This function + * initializes the internal state of the eDMA handle. + * + * param handle eDMA handle pointer. The eDMA handle stores callback function and + * parameters. + * param base eDMA peripheral base address. + * param channel eDMA channel number. + */ +void EDMA_CreateHandle(edma_handle_t *handle, EDMA_Type *base, uint32_t channel) +{ + assert(handle != NULL); + assert(FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base) != -1); + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + uint32_t edmaInstance; + edma_tcd_t *tcdRegs; + + /* Zero the handle */ + (void)memset(handle, 0, sizeof(*handle)); + + handle->channel = channel; + + /* Get the DMA instance number */ + edmaInstance = EDMA_GetInstance(base); + s_EDMAHandle[edmaInstance][channel] = handle; + /* Enable NVIC interrupt */ + (void)EnableIRQ(s_edmaIRQNumber[edmaInstance][channel]); + + handle->tcdBase = EDMA_TCD_BASE(base, channel); + handle->channelBase = EDMA_CHANNEL_BASE(base, channel); + handle->base = base; + /* + Reset TCD registers to zero. Unlike the EDMA_TcdReset(DREQ will be set), + CSR will be 0. Because in order to suit EDMA busy check mechanism in + EDMA_SubmitTransfer, CSR must be set 0. + */ + tcdRegs = handle->tcdBase; + EDMA_TCD_SADDR(tcdRegs, EDMA_TCD_TYPE(base)) = 0; + EDMA_TCD_SOFF(tcdRegs, EDMA_TCD_TYPE(base)) = 0; + EDMA_TCD_ATTR(tcdRegs, EDMA_TCD_TYPE(base)) = 0; + EDMA_TCD_NBYTES(tcdRegs, EDMA_TCD_TYPE(base)) = 0; + EDMA_TCD_SLAST(tcdRegs, EDMA_TCD_TYPE(base)) = 0; + EDMA_TCD_DADDR(tcdRegs, EDMA_TCD_TYPE(base)) = 0; + EDMA_TCD_DOFF(tcdRegs, EDMA_TCD_TYPE(base)) = 0; + EDMA_TCD_CITER(tcdRegs, EDMA_TCD_TYPE(base)) = 0; + EDMA_TCD_DLAST_SGA(tcdRegs, EDMA_TCD_TYPE(base)) = 0; + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(base)) = 0; + EDMA_TCD_BITER(tcdRegs, EDMA_TCD_TYPE(base)) = 0; +} + +/*! + * brief Installs the TCDs memory pool into the eDMA handle. + * + * This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used + * while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block + * (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. + * Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer. + * + * param handle eDMA handle pointer. + * param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned. + * param tcdSize The number of TCD slots. + */ +void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize) +{ + assert(handle != NULL); + assert(((uint32_t)tcdPool & 0x1FU) == 0U); + + /* Initialize tcd queue attribute. */ + /* header should initial as 1, since that it is used to point to the next TCD to be loaded into TCD memory, + * In EDMA driver IRQ handler, header will be used to calculate how many tcd has done, for example, + * If application submit 4 transfer request, A->B->C->D, + * when A finshed, the header is 0, C is the next TCD to be load, since B is already loaded, + * according to EDMA driver IRQ handler, tcdDone = C - A - header = 2 - header = 2, but actually only 1 TCD done, + * so the issue will be the wrong TCD done count will pass to application in first TCD interrupt. + * During first submit, the header should be assigned to 1, since 0 is current one and 1 is next TCD to be loaded, + * but software cannot know which submission is the first one, so assign 1 to header here. + */ + handle->header = 1; + handle->tcdUsed = 0; + handle->tcdSize = (int8_t)tcdSize; + handle->tcdPool = tcdPool; +} + +/*! + * brief Installs a callback function for the eDMA transfer. + * + * This callback is called in the eDMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. This function will be called every time one tcd finished transfer. + * + * param handle eDMA handle pointer. + * param callback eDMA callback function pointer. + * param userData A parameter for the callback function. + */ +void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData) +{ + assert(handle != NULL); + + handle->callback = callback; + handle->userData = userData; +} + +static edma_transfer_size_t EDMA_TransferWidthMapping(uint32_t width) +{ + edma_transfer_size_t transferSize = kEDMA_TransferSize1Bytes; + + /* map width to register value */ + switch (width) + { + /* width 8bit */ + case 1U: + transferSize = kEDMA_TransferSize1Bytes; + break; + /* width 16bit */ + case 2U: + transferSize = kEDMA_TransferSize2Bytes; + break; + /* width 32bit */ + case 4U: + transferSize = kEDMA_TransferSize4Bytes; + break; +#if (defined(FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) + /* width 64bit */ + case 8U: + transferSize = kEDMA_TransferSize8Bytes; + break; +#endif +#if (defined(FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) + /* width 128bit */ + case 16U: + transferSize = kEDMA_TransferSize16Bytes; + break; +#endif + /* width 256bit */ + case 32U: + transferSize = kEDMA_TransferSize32Bytes; + break; +#if (defined(FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) + /* width 512bit */ + case 64U: + transferSize = kEDMA_TransferSize64Bytes; + break; +#endif +#if (defined(FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) + /* width 1024bit */ + case 128U: + transferSize = kEDMA_TransferSize128Bytes; + break; +#endif + default: + /* All the cases have been listed above, the default clause should not be reached. */ + assert(false); + break; + } + + return transferSize; +} + +/*! + * brief Prepares the eDMA transfer structure configurations. + * + * This function prepares the transfer configuration structure according to the user input. + * + * param config The user configuration structure of type edma_transfer_t. + * param srcAddr eDMA transfer source address. + * param srcWidth eDMA transfer source address width(bytes). + * param srcOffset source address offset. + * param destAddr eDMA transfer destination address. + * param destWidth eDMA transfer destination address width(bytes). + * param destOffset destination address offset. + * param bytesEachRequest eDMA transfer bytes per channel request. + * param transferBytes eDMA transfer bytes to be transferred. + * note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + * User can check if 128 bytes support is available for specific instance by + * FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn. + */ +void EDMA_PrepareTransferConfig(edma_transfer_config_t *config, + void *srcAddr, + uint32_t srcWidth, + int16_t srcOffset, + void *destAddr, + uint32_t destWidth, + int16_t destOffset, + uint32_t bytesEachRequest, + uint32_t transferBytes) +{ + assert(config != NULL); + assert(srcAddr != NULL); + assert(destAddr != NULL); +#if (defined(FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) + assert((srcWidth != 0U) && (srcWidth <= 128U) && ((srcWidth & (srcWidth - 1U)) == 0U)); + assert((destWidth != 0U) && (destWidth <= 128U) && ((destWidth & (destWidth - 1U)) == 0U)); +#elif (defined(FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) + assert((srcWidth != 0U) && (srcWidth <= 64U) && ((srcWidth & (srcWidth - 1U)) == 0U)); + assert((destWidth != 0U) && (destWidth <= 64U) && ((destWidth & (destWidth - 1U)) == 0U)); +#else + assert((srcWidth != 0U) && (srcWidth <= 32U) && ((srcWidth & (srcWidth - 1U)) == 0U)); + assert((destWidth != 0U) && (destWidth <= 32U) && ((destWidth & (destWidth - 1U)) == 0U)); +#endif +#if (!defined(FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) || !FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) + assert(srcWidth != 8U); + assert(srcWidth != 8U); +#endif +#if (!defined(FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) || !FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) + assert(srcWidth != 16U); + assert(srcWidth != 16U); +#endif +#if (!defined(FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) || !FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) + assert(srcWidth != 64U); + assert(srcWidth != 64U); +#endif + assert((transferBytes % bytesEachRequest) == 0U); + assert((((uint32_t)(uint8_t *)srcAddr) % srcWidth) == 0U); + assert((((uint32_t)(uint8_t *)destAddr) % destWidth) == 0U); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->destAddr = CONVERT_TO_DMA_ADDRESS((uint32_t)(uint32_t *)destAddr); + config->srcAddr = CONVERT_TO_DMA_ADDRESS((uint32_t)(uint32_t *)srcAddr); + config->minorLoopBytes = bytesEachRequest; + config->majorLoopCounts = transferBytes / bytesEachRequest; + config->srcTransferSize = EDMA_TransferWidthMapping(srcWidth); + config->destTransferSize = EDMA_TransferWidthMapping(destWidth); + config->destOffset = destOffset; + config->srcOffset = srcOffset; + /* enable major interrupt by default */ + config->enabledInterruptMask = (uint16_t)kEDMA_MajorInterruptEnable; +} + +/*! + * brief Prepares the eDMA transfer structure. + * + * This function prepares the transfer configuration structure according to the user input. + * + * param config The user configuration structure of type edma_transfer_t. + * param srcAddr eDMA transfer source address. + * param srcWidth eDMA transfer source address width(bytes). + * param destAddr eDMA transfer destination address. + * param destWidth eDMA transfer destination address width(bytes). + * param bytesEachRequest eDMA transfer bytes per channel request. + * param transferBytes eDMA transfer bytes to be transferred. + * param type eDMA transfer type. + * note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + */ +void EDMA_PrepareTransfer(edma_transfer_config_t *config, + void *srcAddr, + uint32_t srcWidth, + void *destAddr, + uint32_t destWidth, + uint32_t bytesEachRequest, + uint32_t transferBytes, + edma_transfer_type_t type) +{ + assert(config != NULL); + + int16_t srcOffset = 0, destOffset = 0; + + switch (type) + { + case kEDMA_MemoryToMemory: + destOffset = (int16_t)destWidth; + srcOffset = (int16_t)srcWidth; + break; + case kEDMA_MemoryToPeripheral: + destOffset = 0; + srcOffset = (int16_t)srcWidth; + break; + case kEDMA_PeripheralToMemory: + destOffset = (int16_t)destWidth; + srcOffset = 0; + break; + case kEDMA_PeripheralToPeripheral: + destOffset = 0; + srcOffset = 0; + break; + default: + /* All the cases have been listed above, the default clause should not be reached. */ + assert(false); + break; + } + + EDMA_PrepareTransferConfig(config, srcAddr, srcWidth, srcOffset, destAddr, destWidth, destOffset, bytesEachRequest, + transferBytes); +} + +/*! + * brief Prepares the eDMA transfer content descriptor. + * + * This function prepares the transfer content descriptor structure according to the user input. + * + * param handle eDMA handle pointer. + * param tcd Pointer to eDMA transfer content descriptor structure. + * param srcAddr eDMA transfer source address. + * param srcWidth eDMA transfer source address width(bytes). + * param srcOffset source address offset. + * param destAddr eDMA transfer destination address. + * param destWidth eDMA transfer destination address width(bytes). + * param destOffset destination address offset. + * param bytesEachRequest eDMA transfer bytes per channel request. + * param transferBytes eDMA transfer bytes to be transferred. + * param nextTcd eDMA transfer linked TCD address. + * + * note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + */ +void EDMA_PrepareTransferTCD(edma_handle_t *handle, + edma_tcd_t *tcd, + void *srcAddr, + uint32_t srcWidth, + int16_t srcOffset, + void *destAddr, + uint32_t destWidth, + int16_t destOffset, + uint32_t bytesEachRequest, + uint32_t transferBytes, + edma_tcd_t *nextTcd) +{ + assert(tcd != NULL); + assert(srcAddr != NULL); + assert(destAddr != NULL); +#if (defined(FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) + assert((srcWidth != 0U) && (srcWidth <= 128U) && ((srcWidth & (srcWidth - 1U)) == 0U) && + (FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(handle->base) == 1)); + assert((destWidth != 0U) && (destWidth <= 128U) && ((destWidth & (destWidth - 1U)) == 0U) && + (FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(handle->base) == 1)); +#elif (defined(FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) + assert((srcWidth != 0U) && (srcWidth <= 64U) && ((srcWidth & (srcWidth - 1U)) == 0U)); + assert((destWidth != 0U) && (destWidth <= 64U) && ((destWidth & (destWidth - 1U)) == 0U)); +#else + assert((srcWidth != 0U) && (srcWidth <= 32U) && ((srcWidth & (srcWidth - 1U)) == 0U)); + assert((destWidth != 0U) && (destWidth <= 32U) && ((destWidth & (destWidth - 1U)) == 0U)); +#endif +#if (!defined(FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) || !FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) + assert(srcWidth != 8U); + assert(srcWidth != 8U); +#endif +#if (!defined(FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) || !FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) + assert(srcWidth != 16U); + assert(srcWidth != 16U); +#endif +#if (!defined(FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) || !FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) + assert(srcWidth != 64U); + assert(srcWidth != 64U); +#endif + assert((transferBytes % bytesEachRequest) == 0U); + assert((((uint32_t)(uint32_t *)srcAddr) % srcWidth) == 0U); + assert((((uint32_t)(uint32_t *)destAddr) % destWidth) == 0U); + + edma_transfer_size_t srcTransferSize = EDMA_TransferWidthMapping(srcWidth), + destTransferSize = EDMA_TransferWidthMapping(srcWidth); + + /* Initializes the configure structure to zero. */ + EDMA_TcdResetExt(handle->base, tcd); + assert((bytesEachRequest % (1UL << ((uint32_t)srcTransferSize))) == 0U); + assert((bytesEachRequest % (1UL << ((uint32_t)destTransferSize))) == 0U); + assert(((uint32_t)srcOffset % (1UL << ((uint32_t)srcTransferSize))) == 0U); + assert(((uint32_t)destOffset % (1UL << ((uint32_t)destTransferSize))) == 0U); + assert(((uint32_t)(uint32_t *)srcAddr % (1UL << ((uint32_t)srcTransferSize))) == 0U); + assert(((uint32_t)(uint32_t *)destAddr % (1UL << ((uint32_t)destTransferSize))) == 0U); + + EDMA_TCD_SADDR(tcd, EDMA_TCD_TYPE(handle->base)) = CONVERT_TO_DMA_ADDRESS((uint32_t *)srcAddr); + /* destination address */ + EDMA_TCD_DADDR(tcd, EDMA_TCD_TYPE(handle->base)) = CONVERT_TO_DMA_ADDRESS((uint32_t *)destAddr); + /* Source data and destination data transfer size */ + EDMA_TCD_ATTR(tcd, EDMA_TCD_TYPE(handle->base)) = DMA_ATTR_SSIZE(srcTransferSize) | DMA_ATTR_DSIZE(destTransferSize); + + /* Source address signed offset */ + EDMA_TCD_SOFF(tcd, EDMA_TCD_TYPE(handle->base)) = (uint16_t)(srcOffset); + /* Destination address signed offset */ + EDMA_TCD_DOFF(tcd, EDMA_TCD_TYPE(handle->base)) = (uint16_t)(destOffset); + + EDMA_TCD_NBYTES(tcd, EDMA_TCD_TYPE(handle->base)) = DMA_NBYTES_MLOFFNO_NBYTES(bytesEachRequest); + + /* Current major iteration count */ + EDMA_TCD_CITER(tcd, EDMA_TCD_TYPE(handle->base)) = (uint16_t)(transferBytes / bytesEachRequest); + /* Starting major iteration count */ + EDMA_TCD_BITER(tcd, EDMA_TCD_TYPE(handle->base)) = (uint16_t)(transferBytes / bytesEachRequest); + /* reset CSR firstly */ + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(handle->base)) = DMA_CSR_DREQ(1U); + /* Enable scatter/gather processing */ + if (nextTcd != NULL) + { + EDMA_TCD_DLAST_SGA(tcd, EDMA_TCD_TYPE(handle->base)) = CONVERT_TO_DMA_ADDRESS(nextTcd); + /* + Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig, + user must call EDMA_TcdReset or EDMA_ResetChannel which will set + DREQ, so must use "|" or "&" rather than "=". + + Clear the DREQ bit because scatter gather has been enabled, so the + previous transfer is not the last transfer, and channel request should + be enabled at the next transfer(the next TCD). + */ + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(handle->base)) = + (EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(handle->base)) | (uint16_t)DMA_CSR_ESG_MASK) & ~(uint16_t)DMA_CSR_DREQ_MASK; + } + + /* configure interrupt/auto disable channel request, enable major interrupt by default */ + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(handle->base)) |= + (EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(handle->base)) & (~(uint16_t)kEDMA_ErrorInterruptEnable)) | + (uint16_t)kEDMA_MajorInterruptEnable; +} + +/*! + * brief Submits the eDMA transfer content descriptor. + * + * This function submits the eDMA transfer request according to the transfer content descriptor. + * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. + * The tcd pools is setup by call function EDMA_InstallTCDMemory before. + * + * Typical user case: + * 1. submit single transfer + * code + * edma_tcd_t tcd; + * EDMA_PrepareTransferTCD(handle, tcd, ....) + * EDMA_SubmitTransferTCD(handle, tcd) + * EDMA_StartTransfer(handle) + * endcode + * + * 2. submit static link transfer, + * code + * edma_tcd_t tcd[2]; + * EDMA_PrepareTransferTCD(handle, &tcd[0], ....) + * EDMA_PrepareTransferTCD(handle, &tcd[1], ....) + * EDMA_SubmitTransferTCD(handle, &tcd[0]) + * EDMA_StartTransfer(handle) + * endcode + * + * 3. submit dynamic link transfer + * code + * edma_tcd_t tcdpool[2]; + * EDMA_InstallTCDMemory(&g_DMA_Handle, tcdpool, 2); + * edma_tcd_t tcd; + * EDMA_PrepareTransferTCD(handle, tcd, ....) + * EDMA_SubmitTransferTCD(handle, tcd) + * EDMA_PrepareTransferTCD(handle, tcd, ....) + * EDMA_SubmitTransferTCD(handle, tcd) + * EDMA_StartTransfer(handle) + * endcode + * + * 4. submit loop transfer + * code + * edma_tcd_t tcd[2]; + * EDMA_PrepareTransferTCD(handle, &tcd[0], ...,&tcd[1]) + * EDMA_PrepareTransferTCD(handle, &tcd[1], ..., &tcd[0]) + * EDMA_SubmitTransferTCD(handle, &tcd[0]) + * EDMA_StartTransfer(handle) + * endcode + * + * param handle eDMA handle pointer. + * param tcd Pointer to eDMA transfer content descriptor structure. + * + * retval kStatus_EDMA_Success It means submit transfer request succeed. + * retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t EDMA_SubmitTransferTCD(edma_handle_t *handle, edma_tcd_t *tcd) +{ + assert(handle != NULL); + assert(handle->tcdBase != NULL); + + edma_tcd_t *tcdRegs = handle->tcdBase; + + if (handle->tcdPool == NULL) + { + /* + * Check if EDMA channel is busy: + * 1. if channel active bit is set, it implies that minor loop is executing, then channel is busy + * 2. if channel active bit is not set and BITER not equal to CITER, it implies that major loop is executing, + * then channel is busy + * + * There is one case can not be covered in below condition: + * When transfer request is submitted, but no request from peripheral, that is to say channel sevice doesn't + * begin, if application would like to submit another transfer , then the TCD will be overwritten, since the + * ACTIVE is 0 and BITER = CITER, for such case, it is a scatter gather(link TCD) case actually, so + * application should enabled TCD pool for dynamic scatter gather mode by calling EDMA_InstallTCDMemory. + */ +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + if (((tcdRegs->CSR & DMA_CSR_ACTIVE_MASK) != 0U) || +#else + if (((handle->channelBase->CH_CSR & DMA_CH_CSR_ACTIVE_MASK) != 0U) || +#endif + (((EDMA_TCD_CITER(tcdRegs, EDMA_TCD_TYPE(handle->base)) & DMA_CITER_ELINKNO_CITER_MASK) != + (EDMA_TCD_BITER(tcdRegs, EDMA_TCD_TYPE(handle->base)) & DMA_BITER_ELINKNO_BITER_MASK)))) + { + return kStatus_EDMA_Busy; + } + else + { + EDMA_InstallTCD(handle->base, handle->channel, tcd); + /* Enable auto disable request feature */ + EDMA_EnableAutoStopRequest(handle->base, handle->channel, true); + /* Enable major interrupt */ + EDMA_EnableChannelInterrupts(handle->base, handle->channel, kEDMA_MajorInterruptEnable); + + return kStatus_Success; + } + } + else /* Use the TCD queue. */ + { + uint32_t primask; + uint16_t csr; + int8_t currentTcd; + int8_t previousTcd; + int8_t nextTcd; + int8_t tmpTcdUsed; + int8_t tmpTcdSize; + + /* Check if tcd pool is full. */ + primask = DisableGlobalIRQ(); + tmpTcdUsed = handle->tcdUsed; + tmpTcdSize = handle->tcdSize; + if (tmpTcdUsed >= tmpTcdSize) + { + EnableGlobalIRQ(primask); + + return kStatus_EDMA_QueueFull; + } + currentTcd = handle->tail; + handle->tcdUsed++; + /* Calculate index of next TCD */ + nextTcd = currentTcd + 1; + if (nextTcd == handle->tcdSize) + { + nextTcd = 0; + } + /* Advance queue tail index */ + handle->tail = nextTcd; + EnableGlobalIRQ(primask); + /* Calculate index of previous TCD */ + previousTcd = currentTcd != 0 ? currentTcd - 1 : (handle->tcdSize - 1); + + /* Configure current TCD block. */ + EDMA_TcdResetExt(handle->base, &handle->tcdPool[currentTcd]); + (void)memcpy(&handle->tcdPool[currentTcd], tcd, sizeof(edma_tcd_t)); + + /* Enable major interrupt */ + EDMA_TCD_CSR((&handle->tcdPool[currentTcd]), EDMA_TCD_TYPE(handle->base)) |= DMA_CSR_INTMAJOR_MASK; + + if ((EDMA_TCD_DLAST_SGA(tcd, EDMA_TCD_TYPE(handle->base)) == 0U) || + ((EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(handle->base)) & DMA_CSR_ESG_MASK) == 0U)) + { + /* Link current TCD with next TCD for identification of current TCD */ + EDMA_TCD_DLAST_SGA((&handle->tcdPool[currentTcd]), EDMA_TCD_TYPE(handle->base)) = + CONVERT_TO_DMA_ADDRESS((uint32_t)&handle->tcdPool[nextTcd]); + } + + /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */ + if (currentTcd != previousTcd) + { +#if defined FSL_FEATURE_EDMA_HAS_ERRATA_51327 + if (EDMA_CheckErrata(handle->base, &handle->tcdPool[previousTcd]) != kStatus_Success) + { + return kStatus_InvalidArgument; + } +#endif + /* Enable scatter/gather feature in the previous TCD block. */ + csr = EDMA_TCD_CSR((&handle->tcdPool[previousTcd]), EDMA_TCD_TYPE(handle->base)) | + ((uint16_t)DMA_CSR_ESG_MASK); + csr &= ~((uint16_t)DMA_CSR_DREQ_MASK); + EDMA_TCD_CSR((&handle->tcdPool[previousTcd]), EDMA_TCD_TYPE(handle->base)) = csr; + /* + Check if the TCD block in the registers is the previous one (points to current TCD block). It + is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to + link the TCD register in case link the current TCD with the dead chain when TCD loading occurs + before link the previous TCD block. + */ + if (EDMA_TCD_DLAST_SGA(tcdRegs, EDMA_TCD_TYPE(handle->base)) == + CONVERT_TO_DMA_ADDRESS((uint32_t)&handle->tcdPool[currentTcd])) + { + /* Clear the DREQ bits for the dynamic scatter gather */ + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) |= DMA_CSR_DREQ_MASK; + /* Enable scatter/gather also in the TCD registers. */ + csr = EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) | DMA_CSR_ESG_MASK; + /* Must write the CSR register one-time, because the transfer maybe finished anytime. */ + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) = csr; + /* + It is very important to check the ESG bit! + Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can + be used to check if the dynamic TCD link operation is successful. If ESG bit is not set + and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and + the current TCD block has been loaded into TCD registers), it means transfer finished + and TCD link operation fail, so must install TCD content into TCD registers and enable + transfer again. And if ESG is set, it means transfer has not finished, so TCD dynamic + link succeed. + */ + if (0U != (EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) & DMA_CSR_ESG_MASK)) + { + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) &= ~(uint16_t)DMA_CSR_DREQ_MASK; + return kStatus_Success; + } + /* + Check whether the current TCD block is already loaded in the TCD registers. It is another + condition when ESG bit is not set: it means the dynamic TCD link succeed and the current + TCD block has been loaded into TCD registers. + */ + if (EDMA_TCD_DLAST_SGA(tcdRegs, EDMA_TCD_TYPE(handle->base)) == + CONVERT_TO_DMA_ADDRESS((uint32_t)&handle->tcdPool[nextTcd])) + { + return kStatus_Success; + } + /* + If go to this, means the previous transfer finished, and the DONE bit is set. + So shall configure TCD registers. + */ + } + else if (EDMA_TCD_DLAST_SGA(tcdRegs, EDMA_TCD_TYPE(handle->base)) != 0UL) + { + /* The current TCD block has been linked successfully. */ + return kStatus_Success; + } + else + { + /* + DLAST_SGA is 0 and it means the first submit transfer, so shall configure + TCD registers. + */ + } + } + /* There is no live chain, TCD block need to be installed in TCD registers. */ + EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]); + + return kStatus_Success; + } +} + +/*! + * brief Submits the eDMA transfer request. + * + * This function submits the eDMA transfer request according to the transfer configuration structure. + * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. + * The tcd pools is setup by call function EDMA_InstallTCDMemory before. + * + * param handle eDMA handle pointer. + * param config Pointer to eDMA transfer configuration structure. + * retval kStatus_EDMA_Success It means submit transfer request succeed. + * retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config) +{ + assert(handle != NULL); + assert(config != NULL); + assert(handle->tcdBase != NULL); +#if (defined(FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) + assert(((config->srcTransferSize != kEDMA_TransferSize128Bytes) && + (config->destTransferSize != kEDMA_TransferSize128Bytes)) || + (FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(handle->base) == 1)); +#endif + edma_tcd_t *tcdRegs = handle->tcdBase; + + if (handle->tcdPool == NULL) + { + /* + * Check if EDMA channel is busy: + * 1. if channel active bit is set, it implies that minor loop is executing, then channel is busy + * 2. if channel active bit is not set and BITER not equal to CITER, it implies that major loop is executing, + * then channel is busy + * + * There is one case can not be covered in below condition: + * When transfer request is submitted, but no request from peripheral, that is to say channel sevice doesn't + * begin, if application would like to submit another transfer , then the TCD will be overwritten, since the + * ACTIVE is 0 and BITER = CITER, for such case, it is a scatter gather(link TCD) case actually, so + * application should enabled TCD pool for dynamic scatter gather mode by calling EDMA_InstallTCDMemory. + */ +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + if (((tcdRegs->CSR & DMA_CSR_ACTIVE_MASK) != 0U) || +#else + if (((handle->channelBase->CH_CSR & DMA_CH_CSR_ACTIVE_MASK) != 0U) || +#endif + (((EDMA_TCD_CITER(tcdRegs, EDMA_TCD_TYPE(handle->base)) & DMA_CITER_ELINKNO_CITER_MASK) != + (EDMA_TCD_BITER(tcdRegs, EDMA_TCD_TYPE(handle->base)) & DMA_BITER_ELINKNO_BITER_MASK)))) + { + return kStatus_EDMA_Busy; + } + else + { + EDMA_TcdSetTransferConfigExt(handle->base, tcdRegs, config, NULL); + /* Enable auto disable request feature */ + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) |= DMA_CSR_DREQ_MASK; + /* Enable major interrupt */ + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) |= DMA_CSR_INTMAJOR_MASK; + + return kStatus_Success; + } + } + else /* Use the TCD queue. */ + { + uint32_t primask; + uint16_t csr; + int8_t currentTcd; + int8_t previousTcd; + int8_t nextTcd; + int8_t tmpTcdUsed; + int8_t tmpTcdSize; + + /* Check if tcd pool is full. */ + primask = DisableGlobalIRQ(); + tmpTcdUsed = handle->tcdUsed; + tmpTcdSize = handle->tcdSize; + if (tmpTcdUsed >= tmpTcdSize) + { + EnableGlobalIRQ(primask); + + return kStatus_EDMA_QueueFull; + } + currentTcd = handle->tail; + handle->tcdUsed++; + /* Calculate index of next TCD */ + nextTcd = currentTcd + 1; + if (nextTcd == handle->tcdSize) + { + nextTcd = 0; + } + /* Advance queue tail index */ + handle->tail = nextTcd; + EnableGlobalIRQ(primask); + /* Calculate index of previous TCD */ + previousTcd = currentTcd != 0 ? currentTcd - 1 : (handle->tcdSize - 1); + /* Configure current TCD block. */ + EDMA_TcdResetExt(handle->base, &handle->tcdPool[currentTcd]); + EDMA_TcdSetTransferConfigExt(handle->base, &handle->tcdPool[currentTcd], config, NULL); + /* Enable major interrupt */ + EDMA_TCD_CSR((&handle->tcdPool[currentTcd]), EDMA_TCD_TYPE(handle->base)) |= DMA_CSR_INTMAJOR_MASK; + /* Link current TCD with next TCD for identification of current TCD */ + EDMA_TCD_DLAST_SGA((&handle->tcdPool[currentTcd]), EDMA_TCD_TYPE(handle->base)) = + CONVERT_TO_DMA_ADDRESS((uint32_t)&handle->tcdPool[nextTcd]); + /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */ + if (currentTcd != previousTcd) + { +#if defined FSL_FEATURE_EDMA_HAS_ERRATA_51327 + if (EDMA_CheckErrata(handle->base, &handle->tcdPool[previousTcd]) != kStatus_Success) + { + return kStatus_InvalidArgument; + } +#endif + /* Enable scatter/gather feature in the previous TCD block. */ + csr = EDMA_TCD_CSR((&handle->tcdPool[previousTcd]), EDMA_TCD_TYPE(handle->base)) | + ((uint16_t)DMA_CSR_ESG_MASK); + csr &= ~((uint16_t)DMA_CSR_DREQ_MASK); + EDMA_TCD_CSR((&handle->tcdPool[previousTcd]), EDMA_TCD_TYPE(handle->base)) = csr; + /* + Check if the TCD block in the registers is the previous one (points to current TCD block). It + is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to + link the TCD register in case link the current TCD with the dead chain when TCD loading occurs + before link the previous TCD block. + */ + if (EDMA_TCD_DLAST_SGA(handle->tcdBase, EDMA_TCD_TYPE(handle->base)) == + CONVERT_TO_DMA_ADDRESS((uint32_t)&handle->tcdPool[currentTcd])) + { + /* Clear the DREQ bits for the dynamic scatter gather */ + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) |= DMA_CSR_DREQ_MASK; + /* Enable scatter/gather also in the TCD registers. */ + csr = EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) | DMA_CSR_ESG_MASK; + /* Must write the CSR register one-time, because the transfer maybe finished anytime. */ + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) = csr; + /* + It is very important to check the ESG bit! + Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can + be used to check if the dynamic TCD link operation is successful. If ESG bit is not set + and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and + the current TCD block has been loaded into TCD registers), it means transfer finished + and TCD link operation fail, so must install TCD content into TCD registers and enable + transfer again. And if ESG is set, it means transfer has not finished, so TCD dynamic + link succeed. + */ + if (0U != (EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) & DMA_CSR_ESG_MASK)) + { + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) &= ~(uint16_t)DMA_CSR_DREQ_MASK; + return kStatus_Success; + } + /* + Check whether the current TCD block is already loaded in the TCD registers. It is another + condition when ESG bit is not set: it means the dynamic TCD link succeed and the current + TCD block has been loaded into TCD registers. + */ + if (EDMA_TCD_DLAST_SGA(handle->tcdBase, EDMA_TCD_TYPE(handle->base)) == + CONVERT_TO_DMA_ADDRESS((uint32_t)&handle->tcdPool[nextTcd])) + { + return kStatus_Success; + } + /* + If go to this, means the previous transfer finished, and the DONE bit is set. + So shall configure TCD registers. + */ + } + else if (EDMA_TCD_DLAST_SGA(handle->tcdBase, EDMA_TCD_TYPE(handle->base)) != 0UL) + { + /* The current TCD block has been linked successfully. */ + return kStatus_Success; + } + else + { + /* + DLAST_SGA is 0 and it means the first submit transfer, so shall configure + TCD registers. + */ + } + } + /* There is no live chain, TCD block need to be installed in TCD registers. */ + EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]); + + return kStatus_Success; + } +} + +/*! + * brief Submits the eDMA scatter gather transfer configurations. + * + * The function is target for submit loop transfer request, + * the ring transfer request means that the transfer request TAIL is link to HEAD, such as, + * A->B->C->D->A, or A->A + * + * To use the ring transfer feature, the application should allocate several transfer object, such as + * @code + * edma_channel_transfer_config_t transfer[2]; + * EDMA_TransferSubmitLoopTransfer(handle, &transfer, 2U); + * @endcode + * Then eDMA driver will link transfer[0] and transfer[1] to each other + * + * note Application should check the return value of this function to avoid transfer request + * submit failed + * + * param handle eDMA handle pointer + * param transfer pointer to user's eDMA channel configure structure, see edma_channel_transfer_config_t for detail + * param transferLoopCount the count of the transfer ring, if loop count is 1, that means that the one will link to + * itself. + * + * retval #kStatus_Success It means submit transfer request succeed + * retval #kStatus_EDMA_Busy channel is in busy status + * retval #kStatus_InvalidArgument Invalid Argument + */ +status_t EDMA_SubmitLoopTransfer(edma_handle_t *handle, edma_transfer_config_t *transfer, uint32_t transferLoopCount) +{ + assert(transfer != NULL); + assert(handle != NULL); + assert(handle->tcdPool != NULL); + + uint32_t i = 0U; + + if (handle->tcdSize < (int8_t)transferLoopCount) + { + return kStatus_InvalidArgument; + } + + /* + * Check if EDMA channel is busy: + * 1. if channel active bit is set, it implies that minor loop is executing, then channel is busy + * 2. if channel active bit is not set and BITER not equal to CITER, it implies that major loop is executing, + * then channel is busy + * + * There is one case can not be covered in below condition: + * When transfer request is submitted, but no request from peripheral, that is to say channel service doesn't + * begin, if application would like to submit another transfer , then the TCD will be overwritten, since the + * ACTIVE is 0 and BITER = CITER, for such case, it is a scatter gather(link TCD) case actually, so + * application should enabled TCD pool for dynamic scatter gather mode by calling EDMA_InstallTCDMemory. + */ +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + if (((handle->tcdBase->CSR & DMA_CSR_ACTIVE_MASK) != 0U) || +#else + if (((handle->channelBase->CH_CSR & DMA_CH_CSR_ACTIVE_MASK) != 0U) || +#endif + (((EDMA_TCD_CITER(handle->tcdBase, EDMA_TCD_TYPE(handle->base)) & DMA_CITER_ELINKNO_CITER_MASK) != + (EDMA_TCD_BITER(handle->tcdBase, EDMA_TCD_TYPE(handle->base)) & DMA_BITER_ELINKNO_BITER_MASK)))) + { + return kStatus_EDMA_Busy; + } + + (void)memset(handle->tcdPool, 0, (uint32_t)handle->tcdSize * sizeof(edma_tcd_t)); + for (i = 0U; i < transferLoopCount - 1UL; i++) + { + transfer[i].linkTCD = &handle->tcdPool[i + 1UL]; + EDMA_ConfigChannelSoftwareTCDExt(handle->base, &(handle->tcdPool[i]), &transfer[i]); +#if defined FSL_FEATURE_EDMA_HAS_ERRATA_51327 + if (EDMA_CheckErrata(handle->base, &(handle->tcdPool[i])) != kStatus_Success) + { + return kStatus_InvalidArgument; + } +#endif + } + + /* prepare last one in the ring and link it to the HEAD of the ring */ + transfer[i].linkTCD = &handle->tcdPool[0]; + EDMA_ConfigChannelSoftwareTCDExt(handle->base, &(handle->tcdPool[i]), &transfer[i]); + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + if (((transfer->enableSrcMinorLoopOffset) || (transfer->enableDstMinorLoopOffset))) + { + EDMA_EnableMinorLoopMapping(handle->psBase, true); + } +#endif + /* There is no live chain, TCD block need to be installed in TCD registers. */ + EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[0U]); + + /* enable interrupt */ + EDMA_EnableChannelInterrupts(handle->base, handle->channel, + ((uint32_t)transfer->enabledInterruptMask & ~((uint32_t)kEDMA_ErrorInterruptEnable))); + + return kStatus_Success; +} + +/*! + * brief eDMA starts transfer. + * + * This function enables the channel request. Users can call this function after submitting the transfer request + * or before submitting the transfer request. + * + * param handle eDMA handle pointer. + */ +void EDMA_StartTransfer(edma_handle_t *handle) +{ + assert(handle != NULL); + + edma_tcd_t *tcdRegs = handle->tcdBase; + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + if (handle->tcdPool == NULL) + { + handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); + } + else /* Use the TCD queue. */ + { + uint32_t primask; + + /* Check if there was at least one descriptor submitted since reset (TCD in registers is valid) */ + if (tcdRegs->DLAST_SGA != 0U) + { + primask = DisableGlobalIRQ(); + /* Check if channel request is actually disable. */ + if ((handle->base->ERQ & ((uint32_t)1U << handle->channel)) == 0U) + { + /* Check if transfer is paused. */ + tmpCSR = tcdRegs->CSR; + if ((0U == (tmpCSR & DMA_CSR_DONE_MASK)) || (0U != (tmpCSR & DMA_CSR_ESG_MASK))) + { + /* + Re-enable channel request must be as soon as possible, so must put it into + critical section to avoid task switching or interrupt service routine. + */ + handle->base->SERQ = DMA_SERQ_SERQ(handle->channel); + } + } + EnableGlobalIRQ(primask); + } + } +#else +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX +#if defined FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX + if (((uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(handle->base) == 1U) && + (EDMA_MP_BASE(handle->base)->MP_REGS.EDMA5_REG.CH_MUX[handle->channel] == 0U) && + (FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(handle->base) == 1U)) + { + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) |= DMA_CSR_START_MASK; + } + else if (((uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(handle->base) == 1U) && + handle->channelBase->CH_REGS.EDMA4_REG.CH_MUX == 0U && + !(FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(handle->base) == 1U)) + { + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) |= DMA_CSR_START_MASK; + } + else +#else + if (((uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(handle->base) == 1U) && + handle->channelBase->CH_REGS.EDMA4_REG.CH_MUX == 0U) + { + EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) |= DMA_CSR_START_MASK; + } + else +#endif +#endif + if (handle->tcdPool == NULL) + { + handle->channelBase->CH_CSR |= DMA_CH_CSR_ERQ_MASK; + } + else + { + /* Check if channel request is actually disable. */ + if ((handle->channelBase->CH_CSR & DMA_CH_CSR_ERQ_MASK) == 0U) + { + /* Check if transfer is paused. */ + if ((!((handle->channelBase->CH_CSR & DMA_CH_CSR_DONE_MASK) != 0U)) || + ((EDMA_TCD_CSR(tcdRegs, EDMA_TCD_TYPE(handle->base)) & DMA_CSR_ESG_MASK) != 0U)) + { + /* + Re-enable channel request must be as soon as possible, so must put it into + critical section to avoid task switching or interrupt service routine. + */ + handle->channelBase->CH_CSR |= DMA_CH_CSR_ERQ_MASK; + } + } + } +#endif +} + +/*! + * brief eDMA stops transfer. + * + * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() + * again to resume the transfer. + * + * param handle eDMA handle pointer. + */ +void EDMA_StopTransfer(edma_handle_t *handle) +{ + assert(handle != NULL); +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + handle->base->CERQ = DMA_CERQ_CERQ(handle->channel); +#else + handle->channelBase->CH_CSR = handle->channelBase->CH_CSR & (~(DMA_CH_CSR_DONE_MASK | DMA_CH_CSR_ERQ_MASK)); +#endif +} + +/*! + * brief eDMA aborts transfer. + * + * This function disables the channel request and clear transfer status bits. + * Users can submit another transfer after calling this API. + * + * param handle DMA handle pointer. + */ +void EDMA_AbortTransfer(edma_handle_t *handle) +{ + EDMA_StopTransfer(handle); + /* + Clear CSR to release channel. Because if the given channel started transfer, + CSR will be not zero. Because if it is the last transfer, DREQ will be set. + If not, ESG will be set. + */ + EDMA_TcdResetExt(handle->base, handle->tcdBase); + + /* Handle the tcd */ + if (handle->tcdPool != NULL) + { + handle->header = 1; + handle->tail = 0; + handle->tcdUsed = 0; + } +} + +/*! + * brief eDMA IRQ handler for the current major loop transfer completion. + * + * This function clears the channel major interrupt flag and calls + * the callback function if it is not NULL. + * + * Note: + * For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. + * These include the final address adjustments and reloading of the BITER field into the CITER. + * Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from + * memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled). + * + * For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. + * As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index + * in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be + * (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have + * been loaded into the eDMA engine at this point already.). + * + * For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not + * load a new TCD) from the memory pool to the eDMA engine when major loop completes. + * Therefore, ensure that the header and tcdUsed updated are identical for them. + * tcdUsed are both 0 in this case as no TCD to be loaded. + * + * See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for + * further details. + * + * param handle eDMA handle pointer. + */ +void EDMA_HandleIRQ(edma_handle_t *handle) +{ + assert(handle != NULL); + + bool transfer_done; + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + /* Check if transfer is already finished. */ + transfer_done = ((handle->tcdBase->CSR & DMA_CSR_DONE_MASK) != 0U); +#else + transfer_done = (bool)(handle->channelBase->CH_CSR & DMA_CH_CSR_DONE_MASK); +#endif + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + if ((handle->base->INT >> channel) != 0U) + { + handle->base->CINT = channel; + } +#else + if ((handle->channelBase->CH_INT & DMA_CH_INT_INT_MASK) != 0U) + { + handle->channelBase->CH_INT |= DMA_CH_INT_INT_MASK; + } +#endif + + if (handle->tcdPool == NULL) + { + if (handle->callback != NULL) + { + (handle->callback)(handle, handle->userData, transfer_done, 0); + } + } + else /* Use the TCD queue. Please refer to the API descriptions in the eDMA header file for detailed information. */ + { + uint32_t sga = (uint32_t)EDMA_TCD_DLAST_SGA(handle->tcdBase, EDMA_TCD_TYPE(handle->base)); + uint32_t sga_index; + int32_t tcds_done; + uint8_t new_header; + bool esg = ((EDMA_TCD_CSR(handle->tcdBase, EDMA_TCD_TYPE(handle->base)) & DMA_CSR_ESG_MASK) != 0U); + + /* Get the offset of the next transfer TCD blocks to be loaded into the eDMA engine. */ + sga -= CONVERT_TO_DMA_ADDRESS((uint32_t)handle->tcdPool); + /* Get the index of the next transfer TCD blocks to be loaded into the eDMA engine. */ + sga_index = sga / sizeof(edma_tcd_t); + /* Adjust header positions. */ + if (transfer_done) + { + /* New header shall point to the next TCD to be loaded (current one is already finished) */ + new_header = (uint8_t)sga_index; + } + else + { + /* New header shall point to this descriptor currently loaded (not finished yet) */ + new_header = sga_index != 0U ? (uint8_t)sga_index - 1U : (uint8_t)handle->tcdSize - 1U; + } + /* Calculate the number of finished TCDs */ + if (new_header == (uint8_t)handle->header) + { + int8_t tmpTcdUsed = handle->tcdUsed; + int8_t tmpTcdSize = handle->tcdSize; + + /* check esg here for the case that application submit only one request, once the request complete: + * new_header(1) = handle->header(1) + * tcdUsed(1) != tcdSize(>1) + * As the application submit only once, so scatter gather must not enabled, then tcds_done should be 1 + */ + if ((tmpTcdUsed == tmpTcdSize) || (!esg)) + { + tcds_done = handle->tcdUsed; + } + else + { + /* No TCD in the memory are going to be loaded or internal error occurs. */ + tcds_done = 0; + } + } + else + { + tcds_done = (int32_t)new_header - (int32_t)handle->header; + if (tcds_done < 0) + { + tcds_done += handle->tcdSize; + } + /* + * While code run to here, it means a TCD transfer Done and a new TCD has loaded to the hardware + * so clear DONE here to allow submit scatter gather transfer request in the callback to avoid TCD + * overwritten. + */ + if (transfer_done) + { +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + handle->base->CDNE = handle->channel; +#else + handle->channelBase->CH_CSR |= DMA_CH_CSR_DONE_MASK; +#endif + } + } + /* Advance header which points to the TCD to be loaded into the eDMA engine from memory. */ + handle->header = (int8_t)new_header; + /* Release TCD blocks. tcdUsed is the TCD number which can be used/loaded in the memory pool. */ + handle->tcdUsed -= (int8_t)tcds_done; + /* Invoke callback function. */ + if (NULL != handle->callback) + { + (handle->callback)(handle, handle->userData, transfer_done, tcds_done); + } + + /* + * 1.clear the DONE bit here is meaningful for below cases: + * A new TCD has been loaded to EDMA already: + * need to clear the DONE bit in the IRQ handler to avoid TCD in EDMA been overwritten + * if peripheral request isn't coming before next transfer request. + * 2. Don't clear DONE bit for below case, + * for the case that transfer request submitted in the privious edma callback, this is a case that doesn't + * need scatter gather, so keep DONE bit during the next transfer request submission will re-install the TCD and + * the DONE bit will be cleared together with TCD re-installation. + */ + if (transfer_done) + { + if ((EDMA_TCD_CSR(handle->tcdBase, EDMA_TCD_TYPE(handle->base)) & DMA_CSR_ESG_MASK) != 0U) + { +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + handle->base->CDNE = handle->channel; +#else + handle->channelBase->CH_CSR |= DMA_CH_CSR_DONE_MASK; +#endif + } + } + } +} + +void EDMA_DriverIRQHandler(uint32_t instance, uint32_t channel); +void EDMA_DriverIRQHandler(uint32_t instance, uint32_t channel) +{ +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + if ((s_edmaBases[instance]->INT >> channel) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[instance][channel]); + } +#else + if ((EDMA_CHANNEL_BASE(s_edmaBases[instance], channel)->CH_INT & DMA_CH_INT_INT_MASK) != 0U) + { + EDMA_HandleIRQ(s_EDMAHandle[instance][channel]); + } +#endif + SDK_ISR_EXIT_BARRIER; +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_edma.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_edma.h new file mode 100644 index 00000000000..aafd8603ee1 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_edma.h @@ -0,0 +1,1893 @@ +/* + * Copyright 2022-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_EDMA_H_ +#define FSL_EDMA_H_ + +#include "fsl_common.h" +#include "fsl_edma_core.h" +/*! + * @addtogroup edma + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief eDMA driver version */ +#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 10, 0)) /*!< Version 2.10.0. */ +/*! @} */ + +/*! @brief eDMA driver name */ +#ifndef FSL_EDMA_DRIVER_EDMA4 +#define FSL_EDMA_DRIVER_EDMA4 (1) +#endif + +/*!@brief Macro used for allocate edma TCD */ +#define EDMA_ALLOCATE_TCD(name, number) AT_NONCACHEABLE_SECTION_ALIGN(edma_tcd_t name[number], EDMA_TCD_ALIGN_SIZE) + +/*! @brief _edma_transfer_status eDMA transfer status */ +enum +{ + kStatus_EDMA_QueueFull = MAKE_STATUS(kStatusGroup_EDMA, 0), /*!< TCD queue is full. */ + kStatus_EDMA_Busy = MAKE_STATUS(kStatusGroup_EDMA, 1), /*!< Channel is busy and can't handle the + transfer request. */ +}; + +/*! @brief Compute the offset unit from DCHPRI3 */ +#define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3U - ((channel)&0x03U))) + +/*! @brief eDMA transfer configuration */ +typedef enum _edma_transfer_size +{ + kEDMA_TransferSize1Bytes = 0x0U, /*!< Source/Destination data transfer size is 1 byte every time */ + kEDMA_TransferSize2Bytes = 0x1U, /*!< Source/Destination data transfer size is 2 bytes every time */ + kEDMA_TransferSize4Bytes = 0x2U, /*!< Source/Destination data transfer size is 4 bytes every time */ +#if (defined(FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER) + kEDMA_TransferSize8Bytes = 0x3U, /*!< Source/Destination data transfer size is 8 bytes every time */ +#endif +#if (defined(FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) + kEDMA_TransferSize16Bytes = 0x4U, /*!< Source/Destination data transfer size is 16 bytes every time */ +#endif + kEDMA_TransferSize32Bytes = 0x5U, /*!< Source/Destination data transfer size is 32 bytes every time */ +#if (defined(FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER) + kEDMA_TransferSize64Bytes = 0x6U, /*!< Source/Destination data transfer size is 64 bytes every time */ +#endif +#if (defined(FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER) + kEDMA_TransferSize128Bytes = 0x7U, /*!< Source/Destination data transfer size is 128 bytes every time */ +#endif +} edma_transfer_size_t; + +/*! @brief eDMA modulo configuration */ +typedef enum _edma_modulo +{ + kEDMA_ModuloDisable = 0x0U, /*!< Disable modulo */ + kEDMA_Modulo2bytes, /*!< Circular buffer size is 2 bytes. */ + kEDMA_Modulo4bytes, /*!< Circular buffer size is 4 bytes. */ + kEDMA_Modulo8bytes, /*!< Circular buffer size is 8 bytes. */ + kEDMA_Modulo16bytes, /*!< Circular buffer size is 16 bytes. */ + kEDMA_Modulo32bytes, /*!< Circular buffer size is 32 bytes. */ + kEDMA_Modulo64bytes, /*!< Circular buffer size is 64 bytes. */ + kEDMA_Modulo128bytes, /*!< Circular buffer size is 128 bytes. */ + kEDMA_Modulo256bytes, /*!< Circular buffer size is 256 bytes. */ + kEDMA_Modulo512bytes, /*!< Circular buffer size is 512 bytes. */ + kEDMA_Modulo1Kbytes, /*!< Circular buffer size is 1 K bytes. */ + kEDMA_Modulo2Kbytes, /*!< Circular buffer size is 2 K bytes. */ + kEDMA_Modulo4Kbytes, /*!< Circular buffer size is 4 K bytes. */ + kEDMA_Modulo8Kbytes, /*!< Circular buffer size is 8 K bytes. */ + kEDMA_Modulo16Kbytes, /*!< Circular buffer size is 16 K bytes. */ + kEDMA_Modulo32Kbytes, /*!< Circular buffer size is 32 K bytes. */ + kEDMA_Modulo64Kbytes, /*!< Circular buffer size is 64 K bytes. */ + kEDMA_Modulo128Kbytes, /*!< Circular buffer size is 128 K bytes. */ + kEDMA_Modulo256Kbytes, /*!< Circular buffer size is 256 K bytes. */ + kEDMA_Modulo512Kbytes, /*!< Circular buffer size is 512 K bytes. */ + kEDMA_Modulo1Mbytes, /*!< Circular buffer size is 1 M bytes. */ + kEDMA_Modulo2Mbytes, /*!< Circular buffer size is 2 M bytes. */ + kEDMA_Modulo4Mbytes, /*!< Circular buffer size is 4 M bytes. */ + kEDMA_Modulo8Mbytes, /*!< Circular buffer size is 8 M bytes. */ + kEDMA_Modulo16Mbytes, /*!< Circular buffer size is 16 M bytes. */ + kEDMA_Modulo32Mbytes, /*!< Circular buffer size is 32 M bytes. */ + kEDMA_Modulo64Mbytes, /*!< Circular buffer size is 64 M bytes. */ + kEDMA_Modulo128Mbytes, /*!< Circular buffer size is 128 M bytes. */ + kEDMA_Modulo256Mbytes, /*!< Circular buffer size is 256 M bytes. */ + kEDMA_Modulo512Mbytes, /*!< Circular buffer size is 512 M bytes. */ + kEDMA_Modulo1Gbytes, /*!< Circular buffer size is 1 G bytes. */ + kEDMA_Modulo2Gbytes, /*!< Circular buffer size is 2 G bytes. */ +} edma_modulo_t; + +#if defined FSL_FEATURE_EDMA_HAS_BANDWIDTH && FSL_FEATURE_EDMA_HAS_BANDWIDTH +/*! @brief Bandwidth control */ +typedef enum _edma_bandwidth +{ + kEDMA_BandwidthStallNone = 0x0U, /*!< No eDMA engine stalls. */ + kEDMA_BandwidthStall4Cycle = 0x2U, /*!< eDMA engine stalls for 4 cycles after each read/write. */ + kEDMA_BandwidthStall8Cycle = 0x3U, /*!< eDMA engine stalls for 8 cycles after each read/write. */ +} edma_bandwidth_t; +#endif + +/*! @brief Channel link type */ +typedef enum _edma_channel_link_type +{ + kEDMA_LinkNone = 0x0U, /*!< No channel link */ + kEDMA_MinorLink, /*!< Channel link after each minor loop */ + kEDMA_MajorLink, /*!< Channel link while major loop count exhausted */ +} edma_channel_link_type_t; + +/*!@brief _edma_channel_status_flags eDMA channel status flags. */ +enum +{ + kEDMA_DoneFlag = 0x1U, /*!< DONE flag, set while transfer finished, CITER value exhausted*/ + kEDMA_ErrorFlag = 0x2U, /*!< eDMA error flag, an error occurred in a transfer */ + kEDMA_InterruptFlag = 0x4U, /*!< eDMA interrupt flag, set while an interrupt occurred of this channel */ +}; + +/*! @brief _edma_error_status_flags eDMA channel error status flags. */ +enum +{ + kEDMA_DestinationBusErrorFlag = DMA_ERR_DBE_FLAG, /*!< Bus error on destination address */ + kEDMA_SourceBusErrorFlag = DMA_ERR_SBE_FLAG, /*!< Bus error on the source address */ + kEDMA_ScatterGatherErrorFlag = DMA_ERR_SGE_FLAG, /*!< Error on the Scatter/Gather address, not 32byte aligned. */ + kEDMA_NbytesErrorFlag = DMA_ERR_NCE_FLAG, /*!< NBYTES/CITER configuration error */ + kEDMA_DestinationOffsetErrorFlag = DMA_ERR_DOE_FLAG, /*!< Destination offset not aligned with destination size */ + kEDMA_DestinationAddressErrorFlag = DMA_ERR_DAE_FLAG, /*!< Destination address not aligned with destination size */ + kEDMA_SourceOffsetErrorFlag = DMA_ERR_SOE_FLAG, /*!< Source offset not aligned with source size */ + kEDMA_SourceAddressErrorFlag = DMA_ERR_SAE_FLAG, /*!< Source address not aligned with source size*/ + kEDMA_ErrorChannelFlag = DMA_ERR_ERRCHAN_FLAG, /*!< Error channel number of the cancelled channel number */ +#if defined(FSL_FEATURE_EDMA_HAS_PRIORITY_ERROR) && (FSL_FEATURE_EDMA_HAS_PRIORITY_ERROR > 1) + kEDMA_ChannelPriorityErrorFlag = DMA_ERR_CPE_FLAG, /*!< Channel priority is not unique. */ +#endif + kEDMA_TransferCanceledFlag = DMA_ERR_ECX_FLAG, /*!< Transfer cancelled */ +#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1) + kEDMA_GroupPriorityErrorFlag = DMA_ERR_GPE_FLAG, /*!< Group priority is not unique. */ +#endif + kEDMA_ValidFlag = (int)DMA_ERR_FLAG, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */ +}; + +/*! @brief _edma_interrupt_enable eDMA interrupt source */ +enum +{ + kEDMA_ErrorInterruptEnable = 0x1U, /*!< Enable interrupt while channel error occurs. */ + kEDMA_MajorInterruptEnable = DMA_CSR_INTMAJOR_MASK, /*!< Enable interrupt while major count exhausted. */ + kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK, /*!< Enable interrupt while major count to half value. */ +}; + +/*! @brief eDMA transfer type */ +typedef enum _edma_transfer_type +{ + kEDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory */ + kEDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory */ + kEDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral */ + kEDMA_PeripheralToPeripheral, /*!< Transfer from Peripheral to peripheral */ +} edma_transfer_type_t; + +/*! @brief eDMA channel priority configuration */ +typedef struct _edma_channel_Preemption_config +{ + bool enableChannelPreemption; /*!< If true: a channel can be suspended by other channel with higher priority */ + bool enablePreemptAbility; /*!< If true: a channel can suspend other channel with low priority */ + uint8_t channelPriority; /*!< Channel priority */ +} edma_channel_Preemption_config_t; + +/*! @brief eDMA minor offset configuration */ +typedef struct _edma_minor_offset_config +{ + bool enableSrcMinorOffset; /*!< Enable(true) or Disable(false) source minor loop offset. */ + bool enableDestMinorOffset; /*!< Enable(true) or Disable(false) destination minor loop offset. */ + uint32_t minorOffset; /*!< Offset for a minor loop mapping. */ +} edma_minor_offset_config_t; + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE && FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE +/*! @brief eDMA channel memory attribute */ +typedef enum edma_channel_memory_attribute +{ + kEDMA_ChannelNoWriteNoReadNoCacheNoBuffer = + 0x0U, /*!< No write allocate, no read allocate, non-cacheable, non-bufferable. */ + kEDMA_ChannelNoWriteNoReadNoCacheBufferable, /*!< No write allocate, no read allocate, non-cacheable, bufferable. + */ + kEDMA_ChannelNoWriteNoReadCacheableNoBuffer, /*!< No write allocate, no read allocate, cacheable, non-bufferable. + */ + kEDMA_ChannelNoWriteNoReadCacheableBufferable, /*!< No write allocate, no read allocate, cacheable, bufferable. */ + kEDMA_ChannelNoWriteReadNoCacheNoBuffer, /*!< No write allocate, read allocate, non-cacheable, non-bufferable. */ + kEDMA_ChannelNoWriteReadNoCacheBufferable, /*!< No write allocate, read allocate, non-cacheable, bufferable. */ + kEDMA_ChannelNoWriteReadCacheableNoBuffer, /*!< No write allocate, read allocate, cacheable, non-bufferable. */ + kEDMA_ChannelNoWriteReadCacheableBufferable, /*!< No write allocate, read allocate, cacheable, bufferable. */ + kEDMA_ChannelWriteNoReadNoCacheNoBuffer, /*!< write allocate, no read allocate, non-cacheable, non-bufferable. */ + kEDMA_ChannelWriteNoReadNoCacheBufferable, /*!< write allocate, no read allocate, non-cacheable, bufferable. */ + kEDMA_ChannelWriteNoReadCacheableNoBuffer, /*!< write allocate, no read allocate, cacheable, non-bufferable. */ + kEDMA_ChannelWriteNoReadCacheableBufferable, /*!< write allocate, no read allocate, cacheable, bufferable. */ + kEDMA_ChannelWriteReadNoCacheNoBuffer, /*!< write allocate, read allocate, non-cacheable, non-bufferable. */ + kEDMA_ChannelWriteReadNoCacheBufferable, /*!< write allocate, read allocate, non-cacheable, bufferable. */ + kEDMA_ChannelWriteReadCacheableNoBuffer, /*!< write allocate, read allocate, cacheable, non-bufferable. */ + kEDMA_ChannelWriteReadCacheableBufferable, /*!< write allocate, read allocate, cacheable, bufferable. */ +} edma_channel_memory_attribute_t; +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE && FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE +/*! @brief eDMA4 channel swap size */ +typedef enum _edma_channel_swap_size +{ + kEDMA_ChannelSwapDisabled = 0x0U, /*!< Swap is disabled. */ + kEDMA_ChannelReadWith8bitSwap = 0x1U, /*!< Swap occurs with respect to the read 8bit. */ + kEDMA_ChannelReadWith16bitSwap = 0x2U, /*!< Swap occurs with respect to the read 16bit. */ + kEDMA_ChannelReadWith32bitSwap = 0x3U, /*!< Swap occurs with respect to the read 32bit. */ + kEDMA_ChannelWriteWith8bitSwap = 0x9U, /*!< Swap occurs with respect to the write 8bit. */ + kEDMA_ChannelWriteWith16bitSwap = 0x10U, /*!< Swap occurs with respect to the write 16bit. */ + kEDMA_ChannelWriteWith32bitSwap = 0x11U, /*!< Swap occurs with respect to the write 32bit. */ +} edma_channel_swap_size_t; +#endif + +/*! @brief eDMA channel system bus information, _edma_channel_sys_bus_info*/ +enum +{ +#if !(defined(FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR) && FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR) + kEDMA_AttributeOutput = DMA_CH_SBR_ATTR_MASK, /*!< DMA's AHB system bus attribute output value. */ +#endif + + kEDMA_PrivilegedAccessLevel = DMA_CH_SBR_PAL_MASK, /*!< Privileged Access Level for DMA transfers. 0b - User + protection level; 1b - Privileged protection level. */ + kEDMA_MasterId = + DMA_CH_SBR_MID_MASK, /*!< DMA's master ID when channel is active and master ID replication is enabled. */ +}; + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE && FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE +/*! @brief eDMA4 channel access type */ +typedef enum _edma_channel_access_type +{ + kEDMA_ChannelDataAccess = 0x0U, /*!< Data access for eDMA4 transfers. */ + kEDMA_ChannelInstructionAccess = 0x1U, /*!< Instruction access for eDMA4 transfers. */ +} edma_channel_access_type_t; +#endif + +/*! @brief eDMA4 channel protection level */ +typedef enum _edma_channel_protection_level +{ + kEDMA_ChannelProtectionLevelUser = 0x0U, /*!< user protection level for eDMA transfers. */ + kEDMA_ChannelProtectionLevelPrivileged = 0x1U, /*!< Privileged protection level eDMA transfers. */ +} edma_channel_protection_level_t; + +#if !(defined(FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) && FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) + +/*! @brief eDMA4 channel security level */ +typedef enum _edma_channel_security_level +{ + kEDMA_ChannelSecurityLevelNonSecure = 0x0U, /*!< non secure level for eDMA transfers. */ + kEDMA_ChannelSecurityLevelSecure = 0x1U, /*!< secure level for eDMA transfers. */ +} edma_channel_security_level_t; +#endif + +/*! @brief eDMA4 channel configuration*/ +typedef struct _edma_channel_config +{ + edma_channel_Preemption_config_t channelPreemptionConfig; /*!< channel preemption configuration */ + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE && FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE + edma_channel_memory_attribute_t channelReadMemoryAttribute; /*!< channel memory read attribute configuration */ + edma_channel_memory_attribute_t channelWriteMemoryAttribute; /*!< channel memory write attribute configuration */ +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE && FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE + edma_channel_swap_size_t channelSwapSize; /*!< channel swap size configuration */ +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE && FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE + edma_channel_access_type_t channelAccessType; /*!< channel access type configuration */ +#endif + + uint8_t channelDataSignExtensionBitPosition; /*!< channel data sign extension bit psition configuration */ + +#if (defined FSL_FEATURE_EDMA_HAS_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) || (defined FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX) + int channelRequestSource; /*!< hardware service request source for the channel */ +#endif + + bool enableMasterIDReplication; /*!< enable master ID replication */ +#if !(defined(FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) && FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) + edma_channel_security_level_t securityLevel; /*!< security level */ +#endif + edma_channel_protection_level_t protectionLevel; /*!< protection level */ + +} edma_channel_config_t; +#endif + +/*! + * @brief eDMA TCD. + * + * This structure is same as TCD register which is described in reference manual, + * and is used to configure the scatter/gather feature as a next hardware TCD. + */ +typedef edma_core_tcd_t edma_tcd_t; + +/*! @brief edma4 channel transfer configuration + * + * The transfer configuration structure support full feature configuration of the transfer control descriptor. + * + * @note User should pay attention to the transfer size alignment limitation + * 1. the bytesEachRequest should align with the srcWidthOfEachTransfer and the dstWidthOfEachTransfer + * that is to say bytesEachRequest % srcWidthOfEachTransfer should be 0 + * 2. the srcOffsetOfEachTransfer and dstOffsetOfEachTransfer must be aligne with transfer width + * 3. the totalBytes should align with the bytesEachRequest + * 4. the srcAddr should align with the srcWidthOfEachTransfer + * 5. the dstAddr should align with the dstWidthOfEachTransfer + * 6. the srcAddr should align with srcAddrModulo if modulo feature is enabled + * 7. the dstAddr should align with dstAddrModulo if modulo feature is enabled + * If anyone of above condition can not be satisfied, the edma4 interfaces will generate assert error. + * + * 1.To perform a simple transfer, below members should be initialized at least + * .srcAddr - source address + * .dstAddr - destination address + * .srcWidthOfEachTransfer - data width of source address + * .dstWidthOfEachTransfer - data width of destination address, normally it should be as same as + * srcWidthOfEachTransfer .bytesEachRequest - bytes to be transferred in each DMA request .totalBytes - total + * bytes to be transferred .srcOffsetOfEachTransfer - offset value in bytes unit to be applied to source address as + * each source read is completed .dstOffsetOfEachTransfer - offset value in bytes unit to be applied to destination + * address as each destination write is completed enablchannelRequest - channel request can be enabled together with + * transfer configure submission + * + * 2.The transfer configuration structure also support advance feature: + * Programmable source/destination address range(MODULO) + * Programmable minor loop offset + * Programmable major loop offset + * Programmable channel chain feature + * Programmable channel transfer control descriptor link feature + * + */ +typedef struct _edma_transfer_config +{ + uint32_t srcAddr; /*!< Source data address. */ + uint32_t destAddr; /*!< Destination data address. */ + edma_transfer_size_t srcTransferSize; /*!< Source data transfer size. */ + edma_transfer_size_t destTransferSize; /*!< Destination data transfer size. */ + int16_t srcOffset; /*!< Sign-extended offset value in byte unit applied to the current source + address to form the next-state value as each source read is completed */ + int16_t destOffset; /*!< Sign-extended offset value in byte unit applied to the current destination + address to form the next-state value as each destination write is completed. */ + uint32_t minorLoopBytes; /*!< bytes in each minor loop or each request + * range: 1 - (2^30 -1) when minor loop mapping is enabled + * range: 1 - (2^10 - 1) when minor loop mapping is enabled and source or dest minor + * loop offset is enabled + * range: 1 - (2^32 - 1) when minor loop mapping is disabled + */ + uint32_t majorLoopCounts; /*!< minor loop counts in each major loop, should be 1 at least for each + * transfer range: (0 - (2^15 - 1)) when minor loop channel link is + * disabled range: (0 - (2^9 - 1)) when minor loop channel link is enabled + * total bytes in a transfer = minorLoopCountsEachMajorLoop * + * bytesEachMinorLoop + */ + + uint16_t enabledInterruptMask; /*!< channel interrupt to enable, can be OR'ed value of _edma_interrupt_enable */ + + edma_modulo_t srcAddrModulo; /*!< source circular data queue range */ + int32_t srcMajorLoopOffset; /*!< source major loop offset */ + + edma_modulo_t dstAddrModulo; /*!< destination circular data queue range */ + int32_t dstMajorLoopOffset; /*!< destination major loop offset */ + + bool enableSrcMinorLoopOffset; /*!< enable source minor loop offset */ + bool enableDstMinorLoopOffset; /*!< enable dest minor loop offset */ + int32_t minorLoopOffset; /*!< burst offset, the offset will be applied after minor loop update */ + + bool enableChannelMajorLoopLink; /*!< channel link when major loop complete */ + uint32_t majorLoopLinkChannel; /*!< major loop link channel number */ + + bool enableChannelMinorLoopLink; /*!< channel link when minor loop complete */ + uint32_t minorLoopLinkChannel; /*!< minor loop link channel number */ + + edma_tcd_t *linkTCD; /*!< pointer to the link transfer control descriptor */ +} edma_transfer_config_t; + +/*! @brief eDMA global configuration structure.*/ +typedef struct _edma_config +{ +#if defined FSL_FEATURE_EDMA_HAS_CONTINUOUS_LINK_MODE && FSL_FEATURE_EDMA_HAS_CONTINUOUS_LINK_MODE + bool enableContinuousLinkMode; /*!< Enable (true) continuous link mode. Upon minor loop completion, the channel + activates again if that channel has a minor loop channel link enabled and + the link channel is itself. */ +#endif + +#if defined FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION && FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION + bool enableMasterIdReplication; /*!< Enable (true) master ID replication. If Master ID replication is disabled, the + privileged protection level (supervisor mode) for eDMA4 transfers is used. */ +#endif + + bool enableGlobalChannelLink; /*!< Enable(true) channel linking is available and controlled by each channel's link + settings. */ + + bool enableHaltOnError; /*!< Enable (true) transfer halt on error. Any error causes the HALT bit to set. + Subsequently, all service requests are ignored until the HALT bit is cleared.*/ + + bool enableDebugMode; /*!< Enable(true) eDMA4 debug mode. When in debug mode, the eDMA4 stalls the start of + a new channel. Executing channels are allowed to complete. */ + + bool enableRoundRobinArbitration; /*!< Enable(true) channel linking is available and controlled by each channel's + link settings. */ +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG + edma_channel_config_t *channelConfig[FSL_FEATURE_EDMA_MODULE_CHANNEL]; /*!< channel preemption configuration */ +#endif +} edma_config_t; + +/*! @brief Callback for eDMA */ +struct _edma_handle; + +/*! @brief Define callback function for eDMA. + * + * This callback function is called in the EDMA interrupt handle. + * In normal mode, run into callback function means the transfer users need is done. + * In scatter gather mode, run into callback function means a transfer control block (tcd) is finished. Not + * all transfer finished, users can get the finished tcd numbers using interface EDMA_GetUnusedTCDNumber. + * + * @param handle EDMA handle pointer, users shall not touch the values inside. + * @param userData The callback user parameter pointer. Users can use this parameter to involve things users need to + * change in EDMA callback function. + * @param transferDone If the current loaded transfer done. In normal mode it means if all transfer done. In scatter + * gather mode, this parameter shows is the current transfer block in EDMA register is done. As the + * load of core is different, it will be different if the new tcd loaded into EDMA registers while + * this callback called. If true, it always means new tcd still not loaded into registers, while + * false means new tcd already loaded into registers. + * @param tcds How many tcds are done from the last callback. This parameter only used in scatter gather mode. It + * tells user how many tcds are finished between the last callback and this. + */ +typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds); + +/*! @brief eDMA transfer handle structure */ +typedef struct _edma_handle +{ + edma_callback callback; /*!< Callback function for major count exhausted. */ + void *userData; /*!< Callback function parameter. */ + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG + EDMA_ChannelType *channelBase; /*!< eDMA peripheral channel base address. */ +#endif + EDMA_Type *base; /*!< eDMA peripheral base address*/ + EDMA_TCDType *tcdBase; /*!< eDMA peripheral tcd base address. */ + + edma_tcd_t *tcdPool; /*!< Pointer to memory stored TCDs. */ + uint32_t channel; /*!< eDMA channel number. */ + + volatile int8_t header; /*!< The first TCD index. Should point to the next TCD to be loaded into the eDMA engine. */ + volatile int8_t tail; /*!< The last TCD index. Should point to the next TCD to be stored into the memory pool. */ + volatile int8_t tcdUsed; /*!< The number of used TCD slots. Should reflect the number of TCDs can be used/loaded in + the memory. */ + volatile int8_t tcdSize; /*!< The total number of TCD slots in the queue. */ +} edma_handle_t; +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name eDMA initialization and de-initialization + * @{ + */ + +/*! + * @brief Initializes the eDMA peripheral. + * + * This function ungates the eDMA clock and configures the eDMA peripheral according + * to the configuration structure. + * + * @param base eDMA peripheral base address. + * @param config A pointer to the configuration structure, see "edma_config_t". + * @note This function enables the minor loop map feature. + */ +void EDMA_Init(EDMA_Type *base, const edma_config_t *config); + +/*! + * @brief Deinitializes the eDMA peripheral. + * + * This function gates the eDMA clock. + * + * @param base eDMA peripheral base address. + */ +void EDMA_Deinit(EDMA_Type *base); + +/*! + * @brief Push content of TCD structure into hardware TCD register. + * + * @param base EDMA peripheral base address. + * @param channel EDMA channel number. + * @param tcd Point to TCD structure. + */ +void EDMA_InstallTCD(EDMA_Type *base, uint32_t channel, edma_tcd_t *tcd); + +/*! + * @brief Gets the eDMA default configuration structure. + * + * This function sets the configuration structure to default values. + * The default configuration is set to the following values. + * @code + * config.enableContinuousLinkMode = false; + * config.enableHaltOnError = true; + * config.enableRoundRobinArbitration = false; + * config.enableDebugMode = false; + * @endcode + * + * @param config A pointer to the eDMA configuration structure. + */ +void EDMA_GetDefaultConfig(edma_config_t *config); + +#if defined(FSL_FEATURE_DMA_HAS_CONTINUOUS_CHANNEL_LINK) && FSL_FEATURE_DMA_HAS_CONTINUOUS_CHANNEL_LINK +/*! + * @brief Enable/Disable continuous channel link mode. + * + * @note Do not use continuous link mode with a channel linking to itself if there is only one minor loop + * iteration per service request, for example, if the channel's NBYTES value is the same as either + * the source or destination size. The same data transfer profile can be achieved by simply + * increasing the NBYTES value, which provides more efficient, faster processing. + * + * @param base EDMA peripheral base address. + * @param enable true is enable, false is disable. + */ +static inline void EDMA_EnableContinuousChannelLinkMode(EDMA_Type *base, bool enable) +{ + if (enable) + { + EDMA_BASE(base)->CR |= DMA_CR_CLM_MASK; + } + else + { + EDMA_BASE(base)->CR &= ~DMA_CR_CLM_MASK; + } +} +#endif + +#if defined(FSL_FEATURE_DMA_HAS_MINOR_LOOP_MAPPING) && FSL_FEATURE_DMA_HAS_MINOR_LOOP_MAPPING +/*! + * @brief Enable/Disable minor loop mapping. + * + * The TCDn.word2 is redefined to include individual enable fields, an offset field, and the + * NBYTES field. + * + * @param base EDMA peripheral base address. + * @param enable true is enable, false is disable. + */ +static inline void EDMA_EnableMinorLoopMapping(EDMA_Type *base, bool enable) +{ + if (enable) + { + EDMA_BASE(base)->CR |= DMA_CR_EMLM_MASK; + } + else + { + EDMA_BASE(base)->CR &= ~DMA_CR_EMLM_MASK; + } +} +#endif + +/*! @} */ +/*! + * @name eDMA Channel Operation + * @{ + */ + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG +/*! + * @brief EDMA Channel initialization + * + * @param base eDMA4 peripheral base address. + * @param channel eDMA4 channel number. + * @param channelConfig pointer to user's eDMA4 channel config structure, see edma_channel_config_t for detail. + */ +void EDMA_InitChannel(EDMA_Type *base, uint32_t channel, edma_channel_config_t *channelConfig); + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE && FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE +/*! + * @brief Set channel memory attribute. + * + * @param base eDMA4 peripheral base address. + * @param channel eDMA4 channel number. + * @param writeAttribute Attributes associated with a write transaction. + * @param readAttribute Attributes associated with a read transaction. + */ +static inline void EDMA_SetChannelMemoryAttribute(EDMA_Type *base, + uint32_t channel, + edma_channel_memory_attribute_t writeAttribute, + edma_channel_memory_attribute_t readAttribute) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + if (0U != (uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(base)) + { +#if defined FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX + if ((uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(base) == 1U) + { + EDMA_CHANNEL_BASE(base, channel)->CH_REGS.EDMA5_REG.CH_MATTR = + DMA_CH_MATTR_WCACHE(writeAttribute) | DMA_CH_MATTR_RCACHE(readAttribute); + } + else +#endif + { + EDMA_CHANNEL_BASE(base, channel)->CH_REGS.EDMA4_REG.CH_MATTR = + DMA_CH_MATTR_WCACHE(writeAttribute) | DMA_CH_MATTR_RCACHE(readAttribute); + } + } +} +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION && FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION +/*! + * @brief Set channel sign extension. + * + * @param base eDMA4 peripheral base address. + * @param channel eDMA4 channel number. + * @param position A non-zero value specifing the sign extend bit position. + * If 0, sign extension is disabled. + */ +static inline void EDMA_SetChannelSignExtension(EDMA_Type *base, uint32_t channel, uint8_t position) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + if (0U != (uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(base)) + { + EDMA_CHANNEL_BASE(base, channel)->CH_CSR = + (EDMA_CHANNEL_BASE(base, channel)->CH_CSR & (~DMA_CH_CSR_SIGNEXT_MASK)) | + ((uint32_t)position << DMA_CH_CSR_SIGNEXT_SHIFT); + } +} +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE && FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE +/*! + * @brief Set channel swap size. + * + * @param base eDMA4 peripheral base address. + * @param channel eDMA4 channel number. + * @param swapSize Swap occurs with respect to the specified transfer size. + * If 0, swap is disabled. + */ +static inline void EDMA_SetChannelSwapSize(EDMA_Type *base, uint32_t channel, edma_channel_swap_size_t swapSize) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + if (0U != (uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(base)) + { + EDMA_CHANNEL_BASE(base, channel)->CH_CSR = + (EDMA_CHANNEL_BASE(base, channel)->CH_CSR & (~DMA_CH_CSR_SWAP_MASK)) | + ((uint32_t)swapSize << DMA_CH_CSR_SWAP_SHIFT); + } +} +#endif + +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE && FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE +/*! + * @brief Set channel access type. + * + * @param base eDMA4 peripheral base address. + * @param channel eDMA4 channel number. + * @param channelAccessType eDMA4's transactions type on the system bus when the channel is active. + */ +static inline void EDMA_SetChannelAccessType(EDMA_Type *base, + uint32_t channel, + edma_channel_access_type_t channelAccessType) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + if (0U != (uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(base)) + { +#if defined FSL_FEATURE_EDMA_HAS_PROT_REGISTER && FSL_FEATURE_EDMA_HAS_PROT_REGISTER + if (FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(base) == 1) + { + EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_PROT[channel] = + (EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_PROT[channel] & (~DMA_CH_SBR_INSTR_MASK)) | + ((uint32_t)channelAccessType << DMA_CH_SBR_INSTR_SHIFT); + } + else +#endif + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR = + (EDMA_CHANNEL_BASE(base, channel)->CH_SBR & (~DMA_CH_SBR_INSTR_MASK)) | + ((uint32_t)channelAccessType << DMA_CH_SBR_INSTR_SHIFT); + } + } +} +#endif + +#if (defined FSL_FEATURE_EDMA_HAS_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) || \ + (defined FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX) +/*! + * @brief Set channel request source. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param channelRequestSource eDMA hardware service request source for the channel. User need to use + * the dma_request_source_t type as the input parameter. Note that devices + * may use other enum type to express dma request source and User can fined it in + * SOC header or fsl_edma_soc.h. + */ +static inline void EDMA_SetChannelMux(EDMA_Type *base, uint32_t channel, int32_t channelRequestSource) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + if ((uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(base) == 1U) + { + /* Reset channel mux */ +#if defined FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX + if ((uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(base) == 1U) + { + EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_MUX[channel] = DMA_CH_MUX_SOURCE(0); + EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_MUX[channel] = DMA_CH_MUX_SOURCE(channelRequestSource); + } + else +#endif + { +#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX + EDMA_CHANNEL_BASE(base, channel)->CH_REGS.EDMA4_REG.CH_MUX = DMA_CH_MUX_SOURCE(0); + EDMA_CHANNEL_BASE(base, channel)->CH_REGS.EDMA4_REG.CH_MUX = DMA_CH_MUX_SOURCE(channelRequestSource); +#endif + } + } +} +#endif + +/*! + * @brief Gets the channel identification and attribute information on the system bus interface. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @return The mask of the channel system bus information. Users need to use the + * _edma_channel_sys_bus_info type to decode the return variables. + */ +static inline uint32_t EDMA_GetChannelSystemBusInformation(EDMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + return EDMA_CHANNEL_BASE(base, channel)->CH_SBR; +} + +/*! + * @brief Set channel master ID replication. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param enable true is enable, false is disable. + */ +static inline void EDMA_EnableChannelMasterIDReplication(EDMA_Type *base, uint32_t channel, bool enable) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + +#if defined FSL_FEATURE_EDMA_HAS_PROT_REGISTER && FSL_FEATURE_EDMA_HAS_PROT_REGISTER + if (FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(base) == 1) + { + if (enable) + { + EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_PROT[channel] |= DMA_CH_SBR_EMI_MASK; + } + else + { + EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_PROT[channel] &= ~DMA_CH_SBR_EMI_MASK; + } + } + else +#endif + { + if (enable) + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR |= DMA_CH_SBR_EMI_MASK; + } + else + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR &= ~DMA_CH_SBR_EMI_MASK; + } + } +} + +#if !(defined(FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) && FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) +/*! + * @brief Set channel security level. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param level security level. + */ +static inline void EDMA_SetChannelSecurityLevel(EDMA_Type *base, uint32_t channel, edma_channel_security_level_t level) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + +#if defined FSL_FEATURE_EDMA_HAS_PROT_REGISTER && FSL_FEATURE_EDMA_HAS_PROT_REGISTER + if (FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(base) == 1) + { + if (level == kEDMA_ChannelSecurityLevelSecure) + { + EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_PROT[channel] |= DMA_CH_SBR_SEC_MASK; + } + else + { + EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_PROT[channel] &= ~DMA_CH_SBR_SEC_MASK; + } + } + else +#endif + { + if (level == kEDMA_ChannelSecurityLevelSecure) + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR |= DMA_CH_SBR_SEC_MASK; + } + else + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR &= ~DMA_CH_SBR_SEC_MASK; + } + } +} +#endif + +/*! + * @brief Set channel security level. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param level security level. + */ +static inline void EDMA_SetChannelProtectionLevel(EDMA_Type *base, + uint32_t channel, + edma_channel_protection_level_t level) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + +#if defined FSL_FEATURE_EDMA_HAS_PROT_REGISTER && FSL_FEATURE_EDMA_HAS_PROT_REGISTER + if (FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(base) == 1) + { + if (level == kEDMA_ChannelProtectionLevelPrivileged) + { + EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_PROT[channel] |= DMA_CH_SBR_PAL_MASK; + } + else + { + EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_PROT[channel] &= ~DMA_CH_SBR_PAL_MASK; + } + } + else +#endif + { + if (level == kEDMA_ChannelProtectionLevelPrivileged) + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR |= DMA_CH_SBR_PAL_MASK; + } + else + { + EDMA_CHANNEL_BASE(base, channel)->CH_SBR &= ~DMA_CH_SBR_PAL_MASK; + } + } +} + +#endif +/*! + * @brief Sets all TCD registers to default values. + * + * This function sets TCD registers for this channel to default values. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @note This function must not be called while the channel transfer is ongoing + * or it causes unpredictable results. + * @note This function enables the auto stop request feature. + */ +void EDMA_ResetChannel(EDMA_Type *base, uint32_t channel); + +/*! + * @brief Configures the eDMA transfer attribute. + * + * This function configures the transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the TCD address. + * Example: + * @code + * edma_transfer_t config; + * edma_tcd_t tcd; + * config.srcAddr = ..; + * config.destAddr = ..; + * ... + * EDMA_SetTransferConfig(DMA0, channel, &config, &stcd); + * @endcode + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param config Pointer to eDMA transfer configuration structure. + * @param nextTcd Point to TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * @note If nextTcd is not NULL, it means scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the eDMA_ResetChannel. + */ +void EDMA_SetTransferConfig(EDMA_Type *base, + uint32_t channel, + const edma_transfer_config_t *config, + edma_tcd_t *nextTcd); + +/*! + * @brief Configures the eDMA minor offset feature. + * + * The minor offset means that the signed-extended value is added to the source address or destination + * address after each minor loop. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param config A pointer to the minor offset configuration structure. + */ +void EDMA_SetMinorOffsetConfig(EDMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config); + +/*! + * @brief Configures the eDMA channel preemption feature. + * + * This function configures the channel preemption attribute and the priority of the channel. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number + * @param config A pointer to the channel preemption configuration structure. + */ +void EDMA_SetChannelPreemptionConfig(EDMA_Type *base, uint32_t channel, const edma_channel_Preemption_config_t *config); + +/*! + * @brief Sets the channel link for the eDMA transfer. + * + * This function configures either the minor link or the major link mode. The minor link means that the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param type A channel link type, which can be one of the following: + * @arg kEDMA_LinkNone + * @arg kEDMA_MinorLink + * @arg kEDMA_MajorLink + * @param linkedChannel The linked channel number. + * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + */ +void EDMA_SetChannelLink(EDMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel); + +#if defined FSL_FEATURE_EDMA_HAS_BANDWIDTH && FSL_FEATURE_EDMA_HAS_BANDWIDTH +/*! + * @brief Sets the bandwidth for the eDMA transfer. + * + * Because the eDMA processes the minor loop, it continuously generates read/write sequences + * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of + * each read/write access to control the bus request bandwidth seen by the crossbar switch. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param bandWidth A bandwidth setting, which can be one of the following: + * @arg kEDMABandwidthStallNone + * @arg kEDMABandwidthStall4Cycle + * @arg kEDMABandwidthStall8Cycle + */ +void EDMA_SetBandWidth(EDMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth); +#endif + +/*! + * @brief Sets the source modulo and the destination modulo for the eDMA transfer. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param srcModulo A source modulo value. + * @param destModulo A destination modulo value. + */ +void EDMA_SetModulo(EDMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo); + +#if defined(FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT) && FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT +/*! + * @brief Enables an async request for the eDMA transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param enable The command to enable (true) or disable (false). + */ +static inline void EDMA_EnableAsyncRequest(EDMA_Type *base, uint32_t channel, bool enable) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + EDMA_BASE(base)->EARS &= ~((uint32_t)1U << channel); + EDMA_BASE(base)->EARS |= ((uint32_t)(true == enable ? 1U : 0U) << channel); +#else + if (enable) + { + EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_EARQ_MASK; + } + else + { + EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_CSR_EARQ_MASK; + } +#endif +} +#endif + +/*! + * @brief Enables an auto stop request for the eDMA transfer. + * + * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param enable The command to enable (true) or disable (false). + */ +static inline void EDMA_EnableAutoStopRequest(EDMA_Type *base, uint32_t channel, bool enable) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + + if (enable) + { + EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) |= DMA_CSR_DREQ_MASK; + } + else + { + EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_DREQ_MASK; + } +} + +/*! + * @brief Enables the interrupt source for the eDMA transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_EnableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask); + +/*! + * @brief Disables the interrupt source for the eDMA transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param mask The mask of the interrupt source to be set. Use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_DisableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t mask); + +/*! + * @brief Configures the eDMA channel TCD major offset feature. + * + * Adjustment value added to the source address at the completion of the major iteration count + * + * @param base eDMA peripheral base address. + * @param channel edma channel number. + * @param sourceOffset source address offset will be applied to source address after major loop done. + * @param destOffset destination address offset will be applied to source address after major loop done. + */ +void EDMA_SetMajorOffsetConfig(EDMA_Type *base, uint32_t channel, int32_t sourceOffset, int32_t destOffset); + +/*! @} */ +/*! + * @name eDMA TCD Operation + * @{ + */ +/*! + * @brief Sets TCD fields according to the user's channel transfer configuration structure, @ref + * edma_transfer_config_t. + * + * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref + * EDMA_ConfigChannelSoftwareTCDExt + * + * Application should be careful about the TCD pool buffer storage class, + * - For the platform has cache, the software TCD should be put in non cache section + * - The TCD pool buffer should have a consistent storage class. + * + * @param tcd Pointer to the TCD structure. + * @param transfer channel transfer configuration pointer. + * + * @note This function enables the auto stop request feature. + */ +void EDMA_ConfigChannelSoftwareTCD(edma_tcd_t *tcd, const edma_transfer_config_t *transfer); + +/*! + * @brief Sets all fields to default values for the TCD structure. + * + * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref + * EDMA_TcdResetExt + * + * This function sets all fields for this TCD structure to default value. + * + * @param tcd Pointer to the TCD structure. + * @note This function enables the auto stop request feature. + */ +void EDMA_TcdReset(edma_tcd_t *tcd); + +/*! + * @brief Configures the eDMA TCD transfer attribute. + * + * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref + * EDMA_TcdSetTransferConfigExt + * + * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. + * The TCD is used in the scatter-gather mode. + * This function configures the TCD transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the next TCD address. + * Example: + * @code + * edma_transfer_t config = { + * ... + * } + * edma_tcd_t tcd __aligned(32); + * edma_tcd_t nextTcd __aligned(32); + * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd); + * @endcode + * + * @param tcd Pointer to the TCD structure. + * @param config Pointer to eDMA transfer configuration structure. + * @param nextTcd Pointer to the next TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * @note TCD address should be 32 bytes aligned or it causes an eDMA error. + * @note If the nextTcd is not NULL, the scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the EDMA_TcdReset. + */ +void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd); + +/*! + * @brief Configures the eDMA TCD minor offset feature. + * + * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref + * EDMA_TcdSetMinorOffsetConfigExt + * + * A minor offset is a signed-extended value added to the source address or a destination + * address after each minor loop. + * + * @param tcd A point to the TCD structure. + * @param config A pointer to the minor offset configuration structure. + */ +void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config); + +/*! + * @brief Sets the channel link for the eDMA TCD. + * + * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref + * EDMA_TcdSetChannelLinkExt + * + * This function configures either a minor link or a major link. The minor link means the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + * @param tcd Point to the TCD structure. + * @param type Channel link type, it can be one of: + * @arg kEDMA_LinkNone + * @arg kEDMA_MinorLink + * @arg kEDMA_MajorLink + * @param linkedChannel The linked channel number. + */ +void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel); + +#if defined FSL_FEATURE_EDMA_HAS_BANDWIDTH && FSL_FEATURE_EDMA_HAS_BANDWIDTH +/*! + * @brief Sets the bandwidth for the eDMA TCD. + * + * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref + * EDMA_TcdSetBandWidthExt + * + * Because the eDMA processes the minor loop, it continuously generates read/write sequences + * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of + * each read/write access to control the bus request bandwidth seen by the crossbar switch. + * @param tcd A pointer to the TCD structure. + * @param bandWidth A bandwidth setting, which can be one of the following: + * @arg kEDMABandwidthStallNone + * @arg kEDMABandwidthStall4Cycle + * @arg kEDMABandwidthStall8Cycle + */ +static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth) +{ + assert(tcd != NULL); + + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) = + (uint16_t)((EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth)); +} +#endif + +/*! + * @brief Sets the source modulo and the destination modulo for the eDMA TCD. + * + * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref + * EDMA_TcdSetModuloExt + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * @param tcd A pointer to the TCD structure. + * @param srcModulo A source modulo value. + * @param destModulo A destination modulo value. + */ +void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo); + +/*! + * @brief Sets the auto stop request for the eDMA TCD. + * + * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref + * EDMA_TcdEnableAutoStopRequestExt + * + * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. + * + * @param tcd A pointer to the TCD structure. + * @param enable The command to enable (true) or disable (false). + */ +static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable) +{ + assert(tcd != NULL); + + EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) = (uint16_t)((EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) & (~DMA_CSR_DREQ_MASK)) | + DMA_CSR_DREQ((true == enable ? 1U : 0U))); +} + +/*! + * @brief Enables the interrupt source for the eDMA TCD. + * + * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref + * EDMA_TcdEnableInterruptsExt + * + * @param tcd Point to the TCD structure. + * @param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask); + +/*! + * @brief Disables the interrupt source for the eDMA TCD. + * + * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref + * EDMA_TcdDisableInterruptsExt + * + * @param tcd Point to the TCD structure. + * @param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask); + +/*! + * @brief Configures the eDMA TCD major offset feature. + * + * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref + * EDMA_TcdSetMajorOffsetConfigExt + * + * Adjustment value added to the source address at the completion of the major iteration count + * + * @param tcd A point to the TCD structure. + * @param sourceOffset source address offset wiil be applied to source address after major loop done. + * @param destOffset destination address offset will be applied to source address after major loop done. + */ +void EDMA_TcdSetMajorOffsetConfig(edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset); + +/*! + * @brief Sets TCD fields according to the user's channel transfer configuration structure, @ref + * edma_transfer_config_t. + * + * Application should be careful about the TCD pool buffer storage class, + * - For the platform has cache, the software TCD should be put in non cache section + * - The TCD pool buffer should have a consistent storage class. + * + * @param base eDMA peripheral base address. + * @param tcd Pointer to the TCD structure. + * @param transfer channel transfer configuration pointer. + * + * @note This function enables the auto stop request feature. + */ +void EDMA_ConfigChannelSoftwareTCDExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_transfer_config_t *transfer); + +/*! + * @brief Sets all fields to default values for the TCD structure. + * + * This function sets all fields for this TCD structure to default value. + * + * @param base eDMA peripheral base address. + * @param tcd Pointer to the TCD structure. + * @note This function enables the auto stop request feature. + */ +void EDMA_TcdResetExt(EDMA_Type *base, edma_tcd_t *tcd); + +/*! + * @brief Configures the eDMA TCD transfer attribute. + * + * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers. + * The TCD is used in the scatter-gather mode. + * This function configures the TCD transfer attribute, including source address, destination address, + * transfer size, address offset, and so on. It also configures the scatter gather feature if the + * user supplies the next TCD address. + * Example: + * @code + * edma_transfer_t config = { + * ... + * } + * edma_tcd_t tcd __aligned(32); + * edma_tcd_t nextTcd __aligned(32); + * EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd); + * @endcode + * + * @param base eDMA peripheral base address. + * @param tcd Pointer to the TCD structure. + * @param config Pointer to eDMA transfer configuration structure. + * @param nextTcd Pointer to the next TCD structure. It can be NULL if users + * do not want to enable scatter/gather feature. + * @note TCD address should be 32 bytes aligned or it causes an eDMA error. + * @note If the nextTcd is not NULL, the scatter gather feature is enabled + * and DREQ bit is cleared in the previous transfer configuration, which + * is set in the EDMA_TcdReset. + */ +void EDMA_TcdSetTransferConfigExt(EDMA_Type *base, + edma_tcd_t *tcd, + const edma_transfer_config_t *config, + edma_tcd_t *nextTcd); + +/*! + * @brief Configures the eDMA TCD minor offset feature. + * + * A minor offset is a signed-extended value added to the source address or a destination + * address after each minor loop. + * + * @param base eDMA peripheral base address. + * @param tcd A point to the TCD structure. + * @param config A pointer to the minor offset configuration structure. + */ +void EDMA_TcdSetMinorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_minor_offset_config_t *config); + +/*! + * @brief Sets the channel link for the eDMA TCD. + * + * This function configures either a minor link or a major link. The minor link means the channel link is + * triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is + * exhausted. + * + * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid. + * @param base eDMA peripheral base address. + * @param tcd Point to the TCD structure. + * @param type Channel link type, it can be one of: + * @arg kEDMA_LinkNone + * @arg kEDMA_MinorLink + * @arg kEDMA_MajorLink + * @param linkedChannel The linked channel number. + */ +void EDMA_TcdSetChannelLinkExt(EDMA_Type *base, edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel); + +#if defined FSL_FEATURE_EDMA_HAS_BANDWIDTH && FSL_FEATURE_EDMA_HAS_BANDWIDTH +/*! + * @brief Sets the bandwidth for the eDMA TCD. + * + * Because the eDMA processes the minor loop, it continuously generates read/write sequences + * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of + * each read/write access to control the bus request bandwidth seen by the crossbar switch. + * @param base eDMA peripheral base address. + * @param tcd A pointer to the TCD structure. + * @param bandWidth A bandwidth setting, which can be one of the following: + * @arg kEDMABandwidthStallNone + * @arg kEDMABandwidthStall4Cycle + * @arg kEDMABandwidthStall8Cycle + */ +static inline void EDMA_TcdSetBandWidthExt(EDMA_Type *base, edma_tcd_t *tcd, edma_bandwidth_t bandWidth) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) = + (uint16_t)((EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth)); +} +#endif + +/*! + * @brief Sets the source modulo and the destination modulo for the eDMA TCD. + * + * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF) + * calculation is performed or the original register value. It provides the ability to implement a circular data + * queue easily. + * + * @param base eDMA peripheral base address. + * @param tcd A pointer to the TCD structure. + * @param srcModulo A source modulo value. + * @param destModulo A destination modulo value. + */ +void EDMA_TcdSetModuloExt(EDMA_Type *base, edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo); + +/*! + * @brief Sets the auto stop request for the eDMA TCD. + * + * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param tcd A pointer to the TCD structure. + * @param enable The command to enable (true) or disable (false). + */ +static inline void EDMA_TcdEnableAutoStopRequestExt(EDMA_Type *base, edma_tcd_t *tcd, bool enable) +{ + assert(tcd != NULL); + assert(((uint32_t)tcd & 0x1FU) == 0U); + + EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) = (uint16_t)((EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) & (~DMA_CSR_DREQ_MASK)) | + DMA_CSR_DREQ((true == enable ? 1U : 0U))); +} + +/*! + * @brief Enables the interrupt source for the eDMA TCD. + * + * @param base eDMA peripheral base address. + * @param tcd Point to the TCD structure. + * @param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdEnableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask); + +/*! + * @brief Disables the interrupt source for the eDMA TCD. + * + * @param base eDMA peripheral base address. + * @param tcd Point to the TCD structure. + * @param mask The mask of interrupt source to be set. Users need to use + * the defined edma_interrupt_enable_t type. + */ +void EDMA_TcdDisableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask); + +/*! + * @brief Configures the eDMA TCD major offset feature. + * + * Adjustment value added to the source address at the completion of the major iteration count + * + * @param base eDMA peripheral base address. + * @param tcd A point to the TCD structure. + * @param sourceOffset source address offset wiil be applied to source address after major loop done. + * @param destOffset destination address offset will be applied to source address after major loop done. + */ +void EDMA_TcdSetMajorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset); + +/*! @} */ +/*! + * @name eDMA Channel Transfer Operation + * @{ + */ + +/*! + * @brief Enables the eDMA hardware channel request. + * + * This function enables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +static inline void EDMA_EnableChannelRequest(EDMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + EDMA_BASE(base)->SERQ = DMA_SERQ_SERQ(channel); +#else + EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_ERQ_MASK; +#endif +} + +/*! + * @brief Disables the eDMA hardware channel request. + * + * This function disables the hardware channel request. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +static inline void EDMA_DisableChannelRequest(EDMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + EDMA_BASE(base)->CERQ = DMA_CERQ_CERQ(channel); +#else + EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_CSR_ERQ_MASK; +#endif +} + +/*! + * @brief Starts the eDMA transfer by using the software trigger. + * + * This function starts a minor loop transfer. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +static inline void EDMA_TriggerChannelStart(EDMA_Type *base, uint32_t channel) +{ + assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base)); + +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + EDMA_BASE(base)->SSRT = DMA_SSRT_SSRT(channel); +#else + EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) |= DMA_CSR_START_MASK; +#endif +} + +/*! @} */ +/*! + * @name eDMA Channel Status Operation + * @{ + */ + +/*! + * @brief Gets the remaining major loop count from the eDMA current channel TCD. + * + * This function checks the TCD (Task Control Descriptor) status for a specified + * eDMA channel and returns the number of major loop count that has not finished. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @return Major loop count which has not been transferred yet for the current TCD. + * @note 1. This function can only be used to get unfinished major loop count of transfer without + * the next TCD, or it might be inaccuracy. + * 2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while + * the channel is running. + * Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO + * register is needed while the eDMA IP does not support getting it while a channel is active. + * In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine + * is working with while a channel is running. + * Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example + * copied before enabling the channel) is needed. The formula to calculate it is shown below: + * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured) + */ +uint32_t EDMA_GetRemainingMajorLoopCount(EDMA_Type *base, uint32_t channel); + +/*! + * @brief Gets the eDMA channel error status flags. + * + * @param base eDMA peripheral base address. + * @return The mask of error status flags. Users need to use the + * _edma_error_status_flags type to decode the return variables. + */ +static inline uint32_t EDMA_GetErrorStatusFlags(EDMA_Type *base) +{ +#if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA + return EDMA_BASE(base)->ES; +#else + return EDMA_MP_BASE(base)->MP_ES; +#endif +} + +/*! + * @brief Gets the eDMA channel status flags. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @return The mask of channel status flags. Users need to use the + * _edma_channel_status_flags type to decode the return variables. + */ +uint32_t EDMA_GetChannelStatusFlags(EDMA_Type *base, uint32_t channel); + +/*! + * @brief Clears the eDMA channel status flags. + * + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + * @param mask The mask of channel status to be cleared. Users need to use + * the defined _edma_channel_status_flags type. + */ +void EDMA_ClearChannelStatusFlags(EDMA_Type *base, uint32_t channel, uint32_t mask); + +/*! @} */ +/*! + * @name eDMA Transactional Operation + */ + +/*! + * @brief Creates the eDMA handle. + * + * This function is called if using the transactional API for eDMA. This function + * initializes the internal state of the eDMA handle. + * + * @param handle eDMA handle pointer. The eDMA handle stores callback function and + * parameters. + * @param base eDMA peripheral base address. + * @param channel eDMA channel number. + */ +void EDMA_CreateHandle(edma_handle_t *handle, EDMA_Type *base, uint32_t channel); + +/*! + * @brief Installs the TCDs memory pool into the eDMA handle. + * + * This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used + * while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block + * (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer. + * Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer. + * + * @param handle eDMA handle pointer. + * @param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned. + * @param tcdSize The number of TCD slots. + */ +void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize); + +/*! + * @brief Installs a callback function for the eDMA transfer. + * + * This callback is called in the eDMA IRQ handler. Use the callback to do something after + * the current major loop transfer completes. This function will be called every time one tcd finished transfer. + * + * @param handle eDMA handle pointer. + * @param callback eDMA callback function pointer. + * @param userData A parameter for the callback function. + */ +void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData); + +/*! + * @brief Prepares the eDMA transfer structure configurations. + * + * This function prepares the transfer configuration structure according to the user input. + * + * @param config The user configuration structure of type edma_transfer_t. + * @param srcAddr eDMA transfer source address. + * @param srcWidth eDMA transfer source address width(bytes). + * @param srcOffset source address offset. + * @param destAddr eDMA transfer destination address. + * @param destWidth eDMA transfer destination address width(bytes). + * @param destOffset destination address offset. + * @param bytesEachRequest eDMA transfer bytes per channel request. + * @param transferBytes eDMA transfer bytes to be transferred. + * @note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + * User can check if 128 bytes support is available for specific instance by + * FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn. + */ +void EDMA_PrepareTransferConfig(edma_transfer_config_t *config, + void *srcAddr, + uint32_t srcWidth, + int16_t srcOffset, + void *destAddr, + uint32_t destWidth, + int16_t destOffset, + uint32_t bytesEachRequest, + uint32_t transferBytes); + +/*! + * @brief Prepares the eDMA transfer structure. + * + * This function prepares the transfer configuration structure according to the user input. + * + * @param config The user configuration structure of type edma_transfer_t. + * @param srcAddr eDMA transfer source address. + * @param srcWidth eDMA transfer source address width(bytes). + * @param destAddr eDMA transfer destination address. + * @param destWidth eDMA transfer destination address width(bytes). + * @param bytesEachRequest eDMA transfer bytes per channel request. + * @param transferBytes eDMA transfer bytes to be transferred. + * @param type eDMA transfer type. + * @note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + */ +void EDMA_PrepareTransfer(edma_transfer_config_t *config, + void *srcAddr, + uint32_t srcWidth, + void *destAddr, + uint32_t destWidth, + uint32_t bytesEachRequest, + uint32_t transferBytes, + edma_transfer_type_t type); + +/*! + * @brief Prepares the eDMA transfer content descriptor. + * + * This function prepares the transfer content descriptor structure according to the user input. + * + * @param handle eDMA handle pointer. + * @param tcd Pointer to eDMA transfer content descriptor structure. + * @param srcAddr eDMA transfer source address. + * @param srcWidth eDMA transfer source address width(bytes). + * @param srcOffset source address offset. + * @param destAddr eDMA transfer destination address. + * @param destWidth eDMA transfer destination address width(bytes). + * @param destOffset destination address offset. + * @param bytesEachRequest eDMA transfer bytes per channel request. + * @param transferBytes eDMA transfer bytes to be transferred. + * @param nextTcd eDMA transfer linked TCD address. + * + * @note The data address and the data width must be consistent. For example, if the SRC + * is 4 bytes, the source address must be 4 bytes aligned, or it results in + * source address error (SAE). + */ +void EDMA_PrepareTransferTCD(edma_handle_t *handle, + edma_tcd_t *tcd, + void *srcAddr, + uint32_t srcWidth, + int16_t srcOffset, + void *destAddr, + uint32_t destWidth, + int16_t destOffset, + uint32_t bytesEachRequest, + uint32_t transferBytes, + edma_tcd_t *nextTcd); + +/*! + * @brief Submits the eDMA transfer content descriptor. + * + * This function submits the eDMA transfer request according to the transfer content descriptor. + * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. + * The tcd pools is setup by call function EDMA_InstallTCDMemory before. + * + * Typical user case: + * 1. submit single transfer + * @code + * edma_tcd_t tcd; + * EDMA_PrepareTransferTCD(handle, tcd, ....) + * EDMA_SubmitTransferTCD(handle, tcd) + * EDMA_StartTransfer(handle) + * @endcode + * + * 2. submit static link transfer, + * @code + * edma_tcd_t tcd[2]; + * EDMA_PrepareTransferTCD(handle, &tcd[0], ....) + * EDMA_PrepareTransferTCD(handle, &tcd[1], ....) + * EDMA_SubmitTransferTCD(handle, &tcd[0]) + * EDMA_StartTransfer(handle) + * @endcode + * + * 3. submit dynamic link transfer + * @code + * edma_tcd_t tcdpool[2]; + * EDMA_InstallTCDMemory(&g_DMA_Handle, tcdpool, 2); + * edma_tcd_t tcd; + * EDMA_PrepareTransferTCD(handle, tcd, ....) + * EDMA_SubmitTransferTCD(handle, tcd) + * EDMA_PrepareTransferTCD(handle, tcd, ....) + * EDMA_SubmitTransferTCD(handle, tcd) + * EDMA_StartTransfer(handle) + * @endcode + * + * 4. submit loop transfer + * @code + * edma_tcd_t tcd[2]; + * EDMA_PrepareTransferTCD(handle, &tcd[0], ...,&tcd[1]) + * EDMA_PrepareTransferTCD(handle, &tcd[1], ..., &tcd[0]) + * EDMA_SubmitTransferTCD(handle, &tcd[0]) + * EDMA_StartTransfer(handle) + * @endcode + * + * @param handle eDMA handle pointer. + * @param tcd Pointer to eDMA transfer content descriptor structure. + * + * @retval kStatus_EDMA_Success It means submit transfer request succeed. + * @retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * @retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t EDMA_SubmitTransferTCD(edma_handle_t *handle, edma_tcd_t *tcd); + +/*! + * @brief Submits the eDMA transfer request. + * + * This function submits the eDMA transfer request according to the transfer configuration structure. + * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool. + * The tcd pools is setup by call function EDMA_InstallTCDMemory before. + * + * @param handle eDMA handle pointer. + * @param config Pointer to eDMA transfer configuration structure. + * @retval kStatus_EDMA_Success It means submit transfer request succeed. + * @retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed. + * @retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later. + */ +status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config); + +/*! + * @brief Submits the eDMA scatter gather transfer configurations. + * + * The function is target for submit loop transfer request, + * the ring transfer request means that the transfer request TAIL is link to HEAD, such as, + * A->B->C->D->A, or A->A + * + * To use the ring transfer feature, the application should allocate several transfer object, such as + * @code + * edma_channel_transfer_config_t transfer[2]; + * EDMA_TransferSubmitLoopTransfer(psHandle, &transfer, 2U); + * @endcode + * Then eDMA driver will link transfer[0] and transfer[1] to each other + * + * @note Application should check the return value of this function to avoid transfer request + * submit failed + * + * @param handle eDMA handle pointer + * @param transfer pointer to user's eDMA channel configure structure, see edma_channel_transfer_config_t for detail + * @param transferLoopCount the count of the transfer ring, if loop count is 1, that means that the one will link to + * itself. + * + * @retval #kStatus_Success It means submit transfer request succeed + * @retval #kStatus_EDMA_Busy channel is in busy status + * @retval #kStatus_InvalidArgument Invalid Argument + */ +status_t EDMA_SubmitLoopTransfer(edma_handle_t *handle, edma_transfer_config_t *transfer, uint32_t transferLoopCount); + +/*! + * @brief eDMA starts transfer. + * + * This function enables the channel request. Users can call this function after submitting the transfer request + * or before submitting the transfer request. + * + * @param handle eDMA handle pointer. + */ +void EDMA_StartTransfer(edma_handle_t *handle); + +/*! + * @brief eDMA stops transfer. + * + * This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer() + * again to resume the transfer. + * + * @param handle eDMA handle pointer. + */ +void EDMA_StopTransfer(edma_handle_t *handle); + +/*! + * @brief eDMA aborts transfer. + * + * This function disables the channel request and clear transfer status bits. + * Users can submit another transfer after calling this API. + * + * @param handle DMA handle pointer. + */ +void EDMA_AbortTransfer(edma_handle_t *handle); + +/*! + * @brief Get unused TCD slot number. + * + * This function gets current tcd index which is run. If the TCD pool pointer is NULL, it will return 0. + * + * @param handle DMA handle pointer. + * @return The unused tcd slot number. + */ +static inline uint32_t EDMA_GetUnusedTCDNumber(edma_handle_t *handle) +{ + int8_t tmpTcdSize = handle->tcdSize; + int8_t tmpTcdUsed = handle->tcdUsed; + return ((uint32_t)tmpTcdSize - (uint32_t)tmpTcdUsed); +} + +/*! + * @brief Get the next tcd address. + * + * This function gets the next tcd address. If this is last TCD, return 0. + * + * @param handle DMA handle pointer. + * @return The next TCD address. + */ +static inline uint32_t EDMA_GetNextTCDAddress(edma_handle_t *handle) +{ + return (uint32_t)(EDMA_TCD_DLAST_SGA(handle->tcdBase, EDMA_TCD_TYPE(handle->base))); +} + +/*! + * @brief eDMA IRQ handler for the current major loop transfer completion. + * + * This function clears the channel major interrupt flag and calls + * the callback function if it is not NULL. + * + * Note: + * For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed. + * These include the final address adjustments and reloading of the BITER field into the CITER. + * Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from + * memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled). + * + * For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine. + * As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index + * in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be + * (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have + * been loaded into the eDMA engine at this point already.). + * + * For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not + * load a new TCD) from the memory pool to the eDMA engine when major loop completes. + * Therefore, ensure that the header and tcdUsed updated are identical for them. + * tcdUsed are both 0 in this case as no TCD to be loaded. + * + * See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for + * further details. + * + * @param handle eDMA handle pointer. + */ +void EDMA_HandleIRQ(edma_handle_t *handle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /*FSL_EDMA_H_*/ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_edma_core.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_edma_core.h new file mode 100644 index 00000000000..482f4e19883 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_edma_core.h @@ -0,0 +1,357 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_EDMA_CORE_H_ +#define FSL_EDMA_CORE_H_ + +#include "fsl_edma_soc.h" + +/*! + * @addtogroup edma_core + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define DMA_CSR_INTMAJOR_MASK (0x2U) +#define DMA_CSR_INTHALF_MASK (0x4U) +#define DMA_CSR_DREQ_MASK (0x8U) +#define DMA_CSR_ESG_MASK (0x10U) +#define DMA_CSR_BWC_MASK (0xC000U) +#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << (14U))) & (0xC000U)) +#define DMA_CSR_START_MASK (0x1U) +#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) +#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) +#define DMA_CITER_ELINKNO_CITER_SHIFT (0U) +#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) +#define DMA_CITER_ELINKYES_CITER_SHIFT (0U) +#define DMA_ATTR_SMOD_MASK (0xF800U) +#define DMA_ATTR_DMOD_MASK (0xF8U) +#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_CSR_MAJORELINK_MASK (0x20U) +#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_CSR_MAJORLINKCH_MASK (0x1F00U) +#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U) +#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U) +#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) +#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) +#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) +#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) +#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << (3U))) & (0xF8U)) +#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << (11U))) & (0xF800U)) +#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << (9U))) & (0x3E00U)) +#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << (9U))) & (0x3E00U)) +#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << (10U))) & (0x3FFFFC00U)) +#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << (30U))) & (0x40000000U)) +#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << (31U))) & (0x80000000U)) +#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << (0U))) & (0x3FFFFFFFU)) +#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << (0U))) & (0x3FFU)) +#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << (0U))) & (0x7U)) +#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << (8U))) & (0x700U)) +#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << (3U))) & (0x8U)) +#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << (8U))) & (0x1F00U)) +#define DMA_CH_MATTR_WCACHE(x) (((uint16_t)(((uint16_t)(x)) << (4U))) & (0xF0U)) +#define DMA_CH_MATTR_RCACHE(x) (((uint16_t)(((uint16_t)(x)) << (0U))) & (0xFU)) +#define DMA_CH_CSR_SIGNEXT_MASK (0x3F0000U) +#define DMA_CH_CSR_SIGNEXT_SHIFT (16U) +#define DMA_CH_CSR_SWAP_MASK (0xF000U) +#define DMA_CH_CSR_SWAP_SHIFT (12U) +#define DMA_CH_SBR_INSTR_MASK (0x2000U) +#define DMA_CH_SBR_INSTR_SHIFT (13U) +#define DMA_CH_MUX_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << (0U))) & (0xFFU)) + +/*! @brief DMA error flag */ +#if defined(FSL_EDMA_SOC_IP_EDMA) && FSL_EDMA_SOC_IP_EDMA +#define DMA_ERR_DBE_FLAG DMA_ES_DBE_MASK +#define DMA_ERR_SBE_FLAG DMA_ES_SBE_MASK +#define DMA_ERR_SGE_FLAG DMA_ES_SGE_MASK +#define DMA_ERR_NCE_FLAG DMA_ES_NCE_MASK +#define DMA_ERR_DOE_FLAG DMA_ES_DOE_MASK +#define DMA_ERR_DAE_FLAG DMA_ES_DAE_MASK +#define DMA_ERR_SOE_FLAG DMA_ES_SOE_MASK +#define DMA_ERR_SAE_FLAG DMA_ES_SAE_MASK +#define DMA_ERR_ERRCHAN_FLAG DMA_ES_ERRCHN_MASK +#define DMA_ERR_CPE_FLAG DMA_ES_CPE_MASK +#define DMA_ERR_ECX_FLAG DMA_ES_ECX_MASK +#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1) +#define DMA_ERR_GPE_FLAG DMA_ES_GPE_MASK +#endif +#define DMA_ERR_FLAG DMA_ES_VLD_MASK + +/*! @brief get/clear DONE status*/ +#define DMA_CLEAR_DONE_STATUS(base, channel) (EDMA_BASE(base)->CDNE = (uint8_t)channel) +#define DMA_GET_DONE_STATUS(base, channel) \ + ((EDMA_TCD_BASE(base, channel)->CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT) +/*! @brief enable/disable error interrupt*/ +#define DMA_ENABLE_ERROR_INT(base, channel) (base->EEI |= ((uint32_t)0x1U << channel)) +#define DMA_DISABLE_ERROR_INT(base, channel) (base->EEI &= (~((uint32_t)0x1U << channel))) +/*! @brief get/clear error status*/ +#define DMA_GET_ERROR_STATUS(base, channel) (((uint32_t)EDMA_BASE(base)->ERR >> channel) & 0x1U) +#define DMA_CLEAR_ERROR_STATUS(base, channel) ((uint32_t)EDMA_BASE(base)->CERR = (uint8_t)channel) +/*! @brief get/clear int status*/ +#define DMA_GET_INT_STATUS(base, channel) ((((uint32_t)EDMA_BASE(base)->INT >> channel) & 0x1U)) +#define DMA_CLEAR_INT_STATUS(base, channel) ((uint32_t)EDMA_BASE(base)->CINT = (uint8_t)channel) + +#else + +#define DMA_ERR_DBE_FLAG DMA_MP_ES_DBE_MASK +#define DMA_ERR_SBE_FLAG DMA_MP_ES_SBE_MASK +#define DMA_ERR_SGE_FLAG DMA_MP_ES_SGE_MASK +#define DMA_ERR_NCE_FLAG DMA_MP_ES_NCE_MASK +#define DMA_ERR_DOE_FLAG DMA_MP_ES_DOE_MASK +#define DMA_ERR_DAE_FLAG DMA_MP_ES_DAE_MASK +#define DMA_ERR_SOE_FLAG DMA_MP_ES_SOE_MASK +#define DMA_ERR_SAE_FLAG DMA_MP_ES_SAE_MASK +#define DMA_ERR_ERRCHAN_FLAG DMA_MP_ES_ERRCHN_MASK +#define DMA_ERR_ECX_FLAG DMA_MP_ES_ECX_MASK +#define DMA_ERR_FLAG DMA_MP_ES_VLD_MASK + +/*! @brief get/clear DONE bit*/ +#define DMA_CLEAR_DONE_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_DONE_MASK) +#define DMA_GET_DONE_STATUS(base, channel) \ + ((EDMA_CHANNEL_BASE(base, channel)->CH_CSR & DMA_CH_CSR_DONE_MASK) >> DMA_CH_CSR_DONE_SHIFT) +/*! @brief enable/disable error interupt*/ +#define DMA_ENABLE_ERROR_INT(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_EEI_MASK) +#define DMA_DISABLE_ERROR_INT(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_CSR_EEI_MASK) +/*! @brief get/clear error status*/ +#define DMA_CLEAR_ERROR_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_ES |= DMA_CH_ES_ERR_MASK) +#define DMA_GET_ERROR_STATUS(base, channel) \ + (((uint32_t)EDMA_CHANNEL_BASE(base, channel)->CH_ES >> DMA_CH_ES_ERR_SHIFT) & 0x1U) +/*! @brief get/clear INT status*/ +#define DMA_CLEAR_INT_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_INT = DMA_CH_INT_INT_MASK) +#define DMA_GET_INT_STATUS(base, channel) ((((uint32_t)EDMA_CHANNEL_BASE(base, channel)->CH_INT) & 0x1U)) +#endif /*FSL_EDMA_SOC_IP_EDMA*/ + +/*! @brief enable/dsiable MAJOR/HALF INT*/ +#define DMA_ENABLE_MAJOR_INT(base, channel) \ + (EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) |= DMA_CSR_INTMAJOR_MASK) +#define DMA_ENABLE_HALF_INT(base, channel) \ + (EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) |= DMA_CSR_INTHALF_MASK) +#define DMA_DISABLE_MAJOR_INT(base, channel) \ + (EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK) +#define DMA_DISABLE_HALF_INT(base, channel) \ + (EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_INTHALF_MASK) + +/*!@brief EDMA tcd align size */ +#define EDMA_TCD_ALIGN_SIZE (32U) + +/*!@brief edma core channel struture definition */ +typedef struct _edma_core_mp +{ + __IO uint32_t MP_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */ + __IO uint32_t MP_ES; /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */ + union + { + struct + { + __IO uint32_t MP_INT_LOW; /**< Channel Control and Status, array offset: 0x10008, array step: 0x10000 */ + __I uint32_t MP_INT_HIGH; /**< Channel Control and Status, array offset: 0x1000C, array step: 0x10000 */ + __I uint32_t MP_HRS_LOW; /**< Channel Control and Status, array offset: 0x10010, array step: 0x10000 */ + __I uint32_t MP_HRS_HIGH; /**< Channel Control and Status, array offset: 0x10014, array step: 0x10000 */ + uint8_t RESERVED_0[8]; + __IO uint32_t MP_STOPCH; /**< Channel Control and Status, array offset: 0x10020, array step: 0x10000 */ + uint8_t RESERVED_1[12]; + __I uint32_t MP_SSR_LOW; /**< Channel Control and Status, array offset: 0x10030, array step: 0x10000 */ + __I uint32_t MP_SSR_HIGH; /**< Channel Control and Status, array offset: 0x10034, array step: 0x10000 */ + uint8_t RESERVED_2[200]; + __IO uint32_t CH_GRPRI[64]; /**< Channel Control and Status, array offset: 0x10100, array step: 0x10000 */ + __IO uint32_t CH_MUX[64]; /**< Channel Control and Status, array offset: 0x10200, array step: 0x10000 */ + uint8_t RESERVED_3[256]; + __IO uint32_t CH_PROT[64]; /**< Channel Control and Status, array offset: 0x10400, array step: 0x10000 */ + } EDMA5_REG; + } MP_REGS; +} edma_core_mp_t; + +/*!@brief edma core channel struture definition */ +typedef struct _edma_core_channel +{ + __IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */ + __IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */ + __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x10000 */ + __IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0x1000C, array step: 0x10000 */ + __IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x10010, array step: 0x10000 */ + union + { + struct + { + __IO uint8_t RESERVED_1[4]; + __IO uint32_t CH_MATTR; /**< Memory Attributes Register, array offset: 0x10018, array step: 0x8000 */ + } EDMA5_REG; + struct + { + __IO uint32_t CH_MUX; /**< Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000 */ + __IO uint16_t CH_MATTR; /**< Memory Attributes Register, array offset: 0x10018, array step: 0x8000 */ + } EDMA4_REG; + } CH_REGS; +} edma_core_channel_t; + +/*! @brief eDMA tcd flag type */ +typedef enum _edma_tcd_type +{ + kEDMA_EDMA4Flag = 0x0U, /*!< Data access for eDMA4 transfers. */ + kEDMA_EDMA5Flag = 0x1U, /*!< Instruction access for eDMA4 transfers. */ +} edma_tcd_type_t; + +/*!@brief edma5 core TCD struture definition */ +typedef struct _edma5_core_tcd +{ + __IO uint32_t SADDR; /*!< SADDR register, used to save source address */ + __IO uint32_t SADDR_HIGH; /*!< SADDR HIGH register, used to save source address */ + __IO uint16_t SOFF; /*!< SOFF register, save offset bytes every transfer */ + __IO uint16_t ATTR; /*!< ATTR register, source/destination transfer size and modulo */ + __IO uint32_t NBYTES; /*!< Nbytes register, minor loop length in bytes */ + __IO uint32_t SLAST; /*!< SLAST register */ + __IO uint32_t SLAST_SDA_HIGH; /*!< SLAST SDA HIGH register */ + __IO uint32_t DADDR; /*!< DADDR register, used for destination address */ + __IO uint32_t DADDR_HIGH; /*!< DADDR HIGH register, used for destination address */ + __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next tcd address used in scatter-gather mode */ + __IO uint32_t DLAST_SGA_HIGH; /*!< DLASTSGA HIGH register, next tcd address used in scatter-gather mode */ + __IO uint16_t DOFF; /*!< DOFF register, used for destination offset */ + __IO uint16_t CITER; /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/ + __IO uint16_t CSR; /*!< CSR register, for TCD control status */ + __IO uint16_t BITER; /*!< BITER register, begin minor loop count. */ + uint8_t RESERVED[16]; /*!< Aligned 64 bytes */ +} edma5_core_tcd_t; + +/*!@brief edma4 core TCD struture definition */ +typedef struct _edma4_core_tcd +{ + __IO uint32_t SADDR; /*!< SADDR register, used to save source address */ + __IO uint16_t SOFF; /*!< SOFF register, save offset bytes every transfer */ + __IO uint16_t ATTR; /*!< ATTR register, source/destination transfer size and modulo */ + __IO uint32_t NBYTES; /*!< Nbytes register, minor loop length in bytes */ + __IO uint32_t SLAST; /*!< SLAST register */ + __IO uint32_t DADDR; /*!< DADDR register, used for destination address */ + __IO uint16_t DOFF; /*!< DOFF register, used for destination offset */ + __IO uint16_t CITER; /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/ + __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next tcd address used in scatter-gather mode */ + __IO uint16_t CSR; /*!< CSR register, for TCD control status */ + __IO uint16_t BITER; /*!< BITER register, begin minor loop count. */ +} edma4_core_tcd_t; + +/*!@brief edma core TCD struture definition */ +typedef struct _edma_core_tcd +{ + union + { + edma4_core_tcd_t edma4_tcd; +#if defined FSL_EDMA_SOC_IP_DMA5 && FSL_EDMA_SOC_IP_DMA5 + edma5_core_tcd_t edma5_tcd; +#endif /* FSL_EDMA_SOC_IP_DMA5 */ + } TCD_REGS; +} edma_core_tcd_t; + +/*!@brief EDMA typedef */ +typedef edma_core_channel_t EDMA_ChannelType; +typedef edma_core_tcd_t EDMA_TCDType; +typedef void EDMA_Type; + +/*!@brief EDMA base address convert macro */ +#define EDMA_BASE(base) +#define EDMA_CHANNEL_BASE(base, channel) \ + ((edma_core_channel_t *)((uint32_t)(uint32_t *)(base) + EDMA_CHANNEL_OFFSET + \ + (channel)*EDMA_CHANNEL_ARRAY_STEP(base))) +#define EDMA_TCD_BASE(base, channel) \ + ((edma_core_tcd_t *)((uint32_t)(uint32_t *)(base) + EDMA_CHANNEL_OFFSET + \ + (channel)*EDMA_CHANNEL_ARRAY_STEP(base) + 0x20U)) +#define EDMA_MP_BASE(base) ((edma_core_mp_t *)((uint32_t)(uint32_t *)(base))) + +/*!@brief EDMA TCD type macro */ +#if defined FSL_FEATURE_EDMA_TCD_TYPEn +#define EDMA_TCD_TYPE(x) FSL_FEATURE_EDMA_TCD_TYPEn(x) +#else +#define EDMA_TCD_TYPE(x) (0) +#endif + +#if defined FSL_EDMA_SOC_IP_DMA5 && FSL_EDMA_SOC_IP_DMA5 +/*!@brief EDMA TCD address convert macro */ +#define EDMA_TCD_SADDR(tcd, flag) \ + (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SADDR)) : \ + (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->SADDR)))) + +#define EDMA_TCD_SOFF(tcd, flag) \ + (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SOFF)) : \ + (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->SOFF)))) + +#define EDMA_TCD_ATTR(tcd, flag) \ + (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->ATTR)) : \ + (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->ATTR)))) + +#define EDMA_TCD_NBYTES(tcd, flag) \ + (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->NBYTES)) : \ + (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->NBYTES)))) + +#define EDMA_TCD_SLAST(tcd, flag) \ + (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SLAST)) : \ + (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->SLAST)))) + +#define EDMA_TCD_DADDR(tcd, flag) \ + (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DADDR)) : \ + (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->DADDR)))) + +#define EDMA_TCD_DOFF(tcd, flag) \ + (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DOFF)) : \ + (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->DOFF)))) + +#define EDMA_TCD_CITER(tcd, flag) \ + (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CITER)) : \ + (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->CITER)))) + +#define EDMA_TCD_DLAST_SGA(tcd, flag) \ + (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? \ + (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DLAST_SGA)) : \ + (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->DLAST_SGA)))) + +#define EDMA_TCD_CSR(tcd, flag) \ + (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CSR)) : \ + (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->CSR)))) + +#define EDMA_TCD_BITER(tcd, flag) \ + (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->BITER)) : \ + (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->BITER)))) +#else +/*!@brief EDMA TCD address convert macro */ +#define EDMA_TCD_SADDR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SADDR) + +#define EDMA_TCD_SOFF(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SOFF) + +#define EDMA_TCD_ATTR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->ATTR) + +#define EDMA_TCD_NBYTES(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->NBYTES) + +#define EDMA_TCD_SLAST(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SLAST) + +#define EDMA_TCD_DADDR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DADDR) + +#define EDMA_TCD_DOFF(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DOFF) + +#define EDMA_TCD_CITER(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CITER) + +#define EDMA_TCD_DLAST_SGA(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DLAST_SGA) + +#define EDMA_TCD_CSR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CSR) + +#define EDMA_TCD_BITER(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->BITER) +#endif /* FSL_EDMA_SOC_IP_DMA5 */ +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +/*! + * @} + */ + +#endif /* FSL_EDMA_CORE_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_edma_soc.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_edma_soc.c new file mode 100644 index 00000000000..f32c9e0e1b4 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_edma_soc.c @@ -0,0 +1,112 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_edma_soc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.edma_soc" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +extern void DMA_CH0_DriverIRQHandler(void); +extern void DMA_CH1_DriverIRQHandler(void); +extern void DMA_CH2_DriverIRQHandler(void); +extern void DMA_CH3_DriverIRQHandler(void); +extern void DMA_CH4_DriverIRQHandler(void); +extern void DMA_CH5_DriverIRQHandler(void); +extern void DMA_CH6_DriverIRQHandler(void); +extern void DMA_CH7_DriverIRQHandler(void); +extern void EDMA_DriverIRQHandler(uint32_t instance, uint32_t channel); +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief DMA instance 0, channel 0 IRQ handler. + * + */ +void DMA_CH0_DriverIRQHandler(void) +{ + /* Instance 0 channel 0 */ + EDMA_DriverIRQHandler(0U, 0U); +} + +/*! + * brief DMA instance 0, channel 1 IRQ handler. + * + */ +void DMA_CH1_DriverIRQHandler(void) +{ + /* Instance 0 channel 1 */ + EDMA_DriverIRQHandler(0U, 1U); +} + +/*! + * brief DMA instance 0, channel 2 IRQ handler. + * + */ +void DMA_CH2_DriverIRQHandler(void) +{ + /* Instance 0 channel 2 */ + EDMA_DriverIRQHandler(0U, 2U); +} + +/*! + * brief DMA instance 0, channel 3 IRQ handler. + * + */ +void DMA_CH3_DriverIRQHandler(void) +{ + /* Instance 0 channel 3 */ + EDMA_DriverIRQHandler(0U, 3U); +} + +/*! + * brief DMA instance 0, channel 4 IRQ handler. + * + */ +void DMA_CH4_DriverIRQHandler(void) +{ + /* Instance 0 channel 4 */ + EDMA_DriverIRQHandler(0U, 4U); +} +/*! + * brief DMA instance 0, channel 5 IRQ handler. + * + */ +void DMA_CH5_DriverIRQHandler(void) +{ + /* Instance 0 channel 5 */ + EDMA_DriverIRQHandler(0U, 5U); +} + +/*! + * brief DMA instance 0, channel 6 IRQ handler. + * + */ +void DMA_CH6_DriverIRQHandler(void) +{ + /* Instance 0 channel 6 */ + EDMA_DriverIRQHandler(0U, 6U); +} + +/*! + * brief DMA instance 0, channel 7 IRQ handler. + * + */ +void DMA_CH7_DriverIRQHandler(void) +{ + /* Instance 0 channel 7 */ + EDMA_DriverIRQHandler(0U, 7U); +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_edma_soc.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_edma_soc.h new file mode 100644 index 00000000000..7090fdc6f5c --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_edma_soc.h @@ -0,0 +1,64 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_EDMA_SOC_H_ +#define _FSL_EDMA_SOC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup edma_soc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version 2.0.0. */ +#define FSL_EDMA_SOC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*!@brief DMA IP version */ +#define FSL_EDMA_SOC_IP_DMA3 (1) +#define FSL_EDMA_SOC_IP_DMA4 (0) + +/*!@brief DMA base table */ +#define EDMA_BASE_PTRS \ + { \ + DMA0 \ + } + +#define EDMA_CHN_IRQS \ + { \ + { \ + DMA_CH0_IRQn, DMA_CH1_IRQn, DMA_CH2_IRQn, DMA_CH3_IRQn, DMA_CH4_IRQn, DMA_CH5_IRQn, DMA_CH6_IRQn, \ + DMA_CH7_IRQn \ + } \ + } + +/*!@brief EDMA base address convert macro */ +#define EDMA_CHANNEL_OFFSET 0x1000U +#define EDMA_CHANNEL_ARRAY_STEP(base) (0x1000U) + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_EDMA_SOC_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_eim.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_eim.c new file mode 100644 index 00000000000..bae11683f40 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_eim.c @@ -0,0 +1,312 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_eim.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.eim" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to EIM bases for each instance. */ +static EIM_Type *const s_eimBases[] = EIM_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to EIM clocks for each instance. */ +static const clock_ip_name_t s_eimClocks[] = EIM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t EIM_GetInstance(EIM_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_eimBases); instance++) + { + if (s_eimBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_eimBases)); + + return instance; +} + +/*! + * brief EIM module initialization function. + * + * param base EIM base address. + */ +void EIM_Init(EIM_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate EIM clock. */ + CLOCK_EnableClock(s_eimClocks[EIM_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + base->EIMCR = 0x00U; + base->EICHEN = 0x00U; +} + +/*! + * brief Deinitializes the EIM. + * + */ +void EIM_Deinit(EIM_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate EIM clock. */ + CLOCK_DisableClock(s_eimClocks[EIM_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +void EIM_InjectCheckBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask) +{ + switch ((uint8_t)channel) + { + case 0U: + base->EICHD0_WORD0 = EIM_EICHD0_WORD0_CHKBIT_MASK(mask); + break; +#ifdef EIM_EICHEN_EICH1EN_MASK + case 1U: + base->EICHD1_WORD0 = EIM_EICHD1_WORD0_CHKBIT_MASK(mask); + break; +#endif + +#ifdef EIM_EICHEN_EICH2EN_MASK + case 2U: + base->EICHD2_WORD0 = EIM_EICHD2_WORD0_CHKBIT_MASK(mask); + break; +#endif +#ifdef EIM_EICHEN_EICH3EN_MASK + case 3U: + base->EICHD3_WORD0 = EIM_EICHD3_WORD0_CHKBIT_MASK(mask); + break; +#endif +#ifdef EIM_EICHEN_EICH4EN_MASK + case 4U: + base->EICHD4_WORD0 = EIM_EICHD4_WORD0_CHKBIT_MASK(mask); + break; +#endif +#ifdef EIM_EICHEN_EICH5EN_MASK + case 5U: + base->EICHD5_WORD0 = EIM_EICHD5_WORD0_CHKBIT_MASK(mask); + break; +#endif +#ifdef EIM_EICHEN_EICH6EN_MASK + case 6U: + base->EICHD6_WORD0 = EIM_EICHD6_WORD0_CHKBIT_MASK(mask); + break; +#endif +#ifdef EIM_EICHEN_EICH7EN_MASK + case 7U: + base->EICHD7_WORD0 = EIM_EICHD7_WORD0_CHKBIT_MASK(mask); + break; +#endif +#ifdef EIM_EICHEN_EICH8EN_MASK + case 8U: + base->EICHD8_WORD0 = EIM_EICHD8_WORD0_CHKBIT_MASK(mask); + break; +#endif + default: + assert(NULL); + break; + } +} + +uint8_t EIM_GetCheckBitMask(EIM_Type *base, eim_memory_channel_t channel) +{ + uint8_t mask = 0x00U; + + switch ((uint8_t)channel) + { + case 0U: + mask = (uint8_t)((base->EICHD0_WORD0 & EIM_EICHD0_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT); + break; +#ifdef EIM_EICHEN_EICH1EN_MASK + case 1U: + mask = (uint8_t)((base->EICHD1_WORD0 & EIM_EICHD1_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT); + break; +#endif +#ifdef EIM_EICHEN_EICH2EN_MASK + case 2U: + mask = (uint8_t)((base->EICHD2_WORD0 & EIM_EICHD2_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT); + break; +#endif +#ifdef EIM_EICHEN_EICH3EN_MASK + case 3U: + mask = (uint8_t)((base->EICHD3_WORD0 & EIM_EICHD3_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT); + break; +#endif +#ifdef EIM_EICHEN_EICH4EN_MASK + case 4U: + mask = (uint8_t)((base->EICHD4_WORD0 & EIM_EICHD4_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT); + break; +#endif +#ifdef EIM_EICHEN_EICH5EN_MASK + case 5U: + mask = (uint8_t)((base->EICHD5_WORD0 & EIM_EICHD5_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT); + break; +#endif +#ifdef EIM_EICHEN_EICH6EN_MASK + case 6U: + mask = (uint8_t)((base->EICHD6_WORD0 & EIM_EICHD6_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT); + break; +#endif +#ifdef EIM_EICHEN_EICH7EN_MASK + case 7U: + mask = (uint8_t)((base->EICHD7_WORD0 & EIM_EICHD7_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT); + break; +#endif +#ifdef EIM_EICHEN_EICH8EN_MASK + case 8U: + mask = (uint8_t)((base->EICHD8_WORD0 & EIM_EICHD8_WORD0_CHKBIT_MASK_MASK) >> + EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT); + break; +#endif + default: + assert(NULL); + break; + } + + return mask; +} + +void EIM_InjectDataBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask) +{ + switch ((uint8_t)channel) + { + case 0U: + base->EICHD0_WORD1 = mask; + break; +#ifdef EIM_EICHEN_EICH1EN_MASK + case 1U: + base->EICHD1_WORD1 = mask; + break; +#endif +#ifdef EIM_EICHEN_EICH2EN_MASK + case 2U: + base->EICHD2_WORD1 = mask; + break; +#endif +#ifdef EIM_EICHEN_EICH3EN_MASK + case kEIM_MemoryChannelRAMC: + base->EICHD3_WORD1 = mask; + break; +#endif +#ifdef EIM_EICHEN_EICH4EN_MASK + case kEIM_MemoryChannelRAMD: + base->EICHD4_WORD1 = mask; + break; +#endif +#ifdef EIM_EICHEN_EICH5EN_MASK + case kEIM_MemoryChannelRAME: + base->EICHD5_WORD1 = mask; + break; +#endif +#ifdef EIM_EICHEN_EICH6EN_MASK + case kEIM_MemoryChannelRAMF: + base->EICHD6_WORD1 = mask; + break; +#endif +#ifdef EIM_EICHEN_EICH7EN_MASK + case kEIM_MemoryChannelLPCACRAM: + base->EICHD7_WORD1 = mask; + break; +#endif +#ifdef EIM_EICHEN_EICH8EN_MASK + case kEIM_MemoryChannelPKCRAM: + base->EICHD8_WORD1 = mask; + break; +#endif + default: + assert(NULL); + break; + } +} + +uint32_t EIM_GetDataBitMask(EIM_Type *base, eim_memory_channel_t channel) +{ + uint32_t mask = 0x00U; + + switch ((uint8_t)channel) + { + case 0U: + mask = (base->EICHD0_WORD0 & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT; + break; + +#ifdef EIM_EICHEN_EICH1EN_MASK + case 1U: + mask = (base->EICHD1_WORD0 & EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT; + break; +#endif +#ifdef EIM_EICHEN_EICH2EN_MASK + case 2U: + mask = (base->EICHD2_WORD0 & EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT; + break; +#endif +#ifdef EIM_EICHEN_EICH3EN_MASK + case 3U: + mask = (base->EICHD3_WORD0 & EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT; + break; +#endif +#ifdef EIM_EICHEN_EICH4EN_MASK + case 4U: + mask = (base->EICHD4_WORD0 & EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT; + break; +#endif +#ifdef EIM_EICHEN_EICH5EN_MASK + case 5U: + mask = (base->EICHD5_WORD0 & EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT; + break; +#endif +#ifdef EIM_EICHEN_EICH6EN_MASK + case 6U: + mask = (base->EICHD6_WORD0 & EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT; + break; +#endif +#ifdef EIM_EICHEN_EICH7EN_MASK + case 7U: + mask = (base->EICHD7_WORD0 & EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT; + break; +#endif +#ifdef EIM_EICHEN_EICH8EN_MASK + case 8U: + mask = (base->EICHD8_WORD1 & EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT; + break; +#endif + default: + assert(NULL); + break; + } + + return mask; +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_eim.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_eim.h new file mode 100644 index 00000000000..799ff3f20a5 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_eim.h @@ -0,0 +1,144 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_EIM_H_ +#define FSL_EIM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup eim + * @{ + */ + +/****************************************************************************** + * Definitions. + *****************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief Driver version. */ +#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U)) +/*! @} */ + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief EIM module initialization function. + * + * @param base EIM base address. + */ +void EIM_Init(EIM_Type *base); + +/*! + * @brief De-initializes the EIM. + * + */ +void EIM_Deinit(EIM_Type *base); + +/*! @} */ + +/*! + * @name functional + * @{ + */ + +/*! + * @brief EIM module enable global error injection. + * + * @param base EIM base address. + * @param mask The interrupts to enable. + */ +static inline void EIM_EnableGlobalErrorInjection(EIM_Type *base, bool enable) +{ + if (enable) + { + base->EIMCR = EIM_EIMCR_GEIEN_MASK; + } + else + { + base->EIMCR = ~EIM_EIMCR_GEIEN_MASK; + } +} + +/*! + * @brief EIM module enable error injection for memory channel n, this function enables the corresponding error + * injection channel. The Global Error Injection Enable function must also be called to enable error injection. + * + * @param base EIM base address. + * @param mask The interrupts to enable. Refer to "_eim_error_injection_channel_enable" enumeration. + */ +static inline void EIM_EnableErrorInjectionChannels(EIM_Type *base, uint32_t mask) +{ + base->EICHEN |= mask; +} + +/*! + * @brief EIM module disable error injection for memory channel n. + * + * @param base EIM base address. + * @param mask The interrupts to enable. Refer to "_eim_error_injection_channel_enable" enumeration. + */ +static inline void EIM_DisableErrorInjectionChannels(EIM_Type *base, uint32_t mask) +{ + base->EICHEN &= ~mask; +} + +/*! + * @brief EIM module inject checkbit error for memory channel n, an attempt to invert more than 2 bits in one operation + * might result in undefined behavior. + * + * @param base EIM base address. + * @param channel memory channel. + * @param mask The interrupts to enable. + */ +void EIM_InjectCheckBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask); + +/*! + * @brief EIM module get checkbit mask for memory channel n. + * + * @param base EIM base address. + * @param channel memory channel. + * @retval return checkbit mask. + */ +uint8_t EIM_GetCheckBitMask(EIM_Type *base, eim_memory_channel_t channel); + +/*! + * @brief EIM module inject databit error for memory channel n, an attempt to invert more than 2 bits in one operation + * might result in undefined behavior. + * + * @param base EIM base address. + * @param channel memory channel. + * @param mask The interrupts to enable. + */ +void EIM_InjectDataBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask); + +/*! + * @brief EIM module get databit mask for memory channel n. + * + * @param base EIM base address. + * @param channel memory channel. + * @retval return checkbit mask. + */ +uint32_t EIM_GetDataBitMask(EIM_Type *base, eim_memory_channel_t channel); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_eqdc.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_eqdc.c new file mode 100644 index 00000000000..00f5fd8859b --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_eqdc.c @@ -0,0 +1,301 @@ +/* + * Copyright 2022, 2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_eqdc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.eqdc" +#endif + +#if defined(EQDC_RSTS) +#define EQDC_RESETS_ARRAY EQDC_RSTS +#endif +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for EQDC module. + * + * @param base EQDC peripheral base address + */ +static uint32_t EQDC_GetInstance(EQDC_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to EQDC bases for each instance. */ +static EQDC_Type *const s_eqdcBases[] = EQDC_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to EQDC clocks for each instance. */ +#if defined(QDC_CLOCKS) +static const clock_ip_name_t s_eqdcClocks[] = QDC_CLOCKS; +#elif defined(ENC_CLOCKS) +static const clock_ip_name_t s_eqdcClocks[] = ENC_CLOCKS; +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(EQDC_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_eqdcResets[] = EQDC_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t EQDC_GetInstance(EQDC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_eqdcBases); instance++) + { + if (s_eqdcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_eqdcBases)); + + return instance; +} + +/* + * Initializes the EQDC module. + * + * This function initializes the EQDC by enabling the IP bus clock (optional). + * + * param base EQDC peripheral base address. + * param psConfig Pointer to configuration structure. + */ +void EQDC_Init(EQDC_Type *base, const eqdc_config_t *psConfig) +{ + assert(NULL != psConfig); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_eqdcClocks[EQDC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(EQDC_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_eqdcResets[EQDC_GetInstance(base)]); +#endif + + /* Initialize Double-set registers */ + EQDC_ClearBufferedRegisterLoadUpdateMode(base); + EQDC_ClearEqdcLdok(base); + + /* Counter value. */ + EQDC_SetPositionCounterValue(base, psConfig->positionCounterValue); + + /* Initial value. */ + EQDC_SetInitialPositionValue(base, psConfig->positionInitialValue); + + /* Modulus value. */ + EQDC_SetPositionModulusValue(base, psConfig->positionModulusValue); + + /* Compare value. */ + EQDC_SetPositionCompare0Value(base, psConfig->positionCompareValue[0]); + EQDC_SetPositionCompare1Value(base, psConfig->positionCompareValue[1]); + EQDC_SetPositionCompare2Value(base, psConfig->positionCompareValue[2]); + EQDC_SetPositionCompare3Value(base, psConfig->positionCompareValue[3]); + + EQDC_SetEqdcLdok(base); + while (EQDC_GetEqdcLdok(base) != 0U) + { + } + + /* Watchdog. */ + EQDC_SetWatchdogTimeout(base, psConfig->watchdogTimeoutValue); + + /* Clear EQDC_REV */ + base->REV = 0U; + + /* EQDC_IMR. */ + base->IMR = EQDC_IMR_FPHA(psConfig->filterPhaseA) | EQDC_IMR_FPHB(psConfig->filterPhaseB) | + EQDC_IMR_FIND_PRE(psConfig->filterIndPre) | EQDC_IMR_FHOM_ENA(psConfig->filterHomEna); + + /* EQDC_FILT. */ + base->FILT = EQDC_FILT_PRSC(psConfig->prescaler) | /* Prescaler used by LASTEDGE and POSDPER. */ + EQDC_FILT_FILT_CS(psConfig->filterClockSourceselection) | + EQDC_FILT_FILT_CNT(psConfig->filterSampleCount) | EQDC_FILT_FILT_PER(psConfig->filterSamplePeriod); + + /* EQDC_CTRL. */ + base->CTRL = EQDC_CTRL_W1C_FLAGS | /* W1C flags. */ + (uint16_t)psConfig->homeEnableInitPosCounterMode | /* HOME Enable trigger. */ + (uint16_t)psConfig->indexPresetInitPosCounterMode | /* INDEX Preset trigger. */ + EQDC_CTRL_REV(psConfig->enableReverseDirection) | /* Reverse direction. */ + EQDC_CTRL_WDE(psConfig->enableWatchdog) | /* Enable watchdog. */ + EQDC_CTRL_DMAEN(psConfig->enableDma); /* Enable Dma. */ + + /* Set mode of count. */ + EQDC_SetCountMode(base, psConfig->countMode); /* eqdcoder count mode. */ + + /* EQDC_CTRL2. */ + base->CTRL2 = + EQDC_CTRL2_ONCE(psConfig->countOnce) | + EQDC_CTRL2_INITPOS(psConfig->enableTriggerInitPositionCounter) | /* TRIGGER initializes position counter. */ +#if (defined(FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD) && FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD) + EQDC_CTRL2_EMIP(psConfig->enableIndexInitPositionCounter)| /* Index Event Edge Mark initializes position counter */ +#endif /* FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD */ + EQDC_CTRL2_PMEN(psConfig->enablePeriodMeasurement) | /* Enable period measurement. */ + EQDC_CTRL2_OUTCTL(psConfig->outputPulseMode) | /* Output pulse. */ + EQDC_CTRL2_REVMOD(psConfig->revolutionCountCondition) | /* Revolution count condition. */ + EQDC_CTRL2_LDMOD(psConfig->bufferedRegisterLoadMode) | /* Buffered register load (Update) mode select. */ + EQDC_CTRL2_UPDPOS(psConfig->enableTriggerClearPositionRegisters) | /* TRIGGER clears position register. */ + EQDC_CTRL2_UPDHLD(psConfig->enableTriggerHoldPositionRegisters); /* TRIGGER loads position registers. */ + + /* Set mode of operation. */ + EQDC_SetOperateMode(base, psConfig->operateMode); /* eqdcoder work mode. */ + + /* Enable interrupts. */ + EQDC_EnableInterrupts(base, psConfig->enabledInterruptsMask); +} + +/* + * De-initializes the EQDC module. + * + * This function deinitializes the EQDC by: + * 1. Disables the IP bus clock (optional). + * + * param base EQDC peripheral base address. + */ +void EQDC_Deinit(EQDC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_eqdcClocks[EQDC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * Gets an available pre-defined configuration. + * + * The default value are: + * psConfig->enableReverseDirection = false; + * psConfig->countOnce = false; + * psConfig->operateMode = kEQDC_QuadratureDecodeOperationMode; + * psConfig->countMode = kEQDC_QuadratureX4; + * psConfig->homeEnableInitPosCounterMode = kEQDC_HomeInitPosCounterDisabled; + * psConfig->indexPresetInitPosCounterMode = kEQDC_IndexInitPosCounterDisabled; + * psConfig->enableIndexInitPositionCounter = false; + * psConfig->enableDma = false; + * psConfig->bufferedRegisterLoadMode = false; + * psConfig->enableTriggerInitPositionCounter = false; + * psConfig->enableTriggerClearPositionRegisters = false; + * psConfig->enableTriggerHoldPositionRegisters = false; + * psConfig->enableWatchdog = false; + * psConfig->watchdogTimeoutValue = 0xFFFFU; + * psConfig->filterPhaseA = 0U; + * psConfig->filterPhaseB = 0U; + * psConfig->filterIndPre = 0U; + * psConfig->filterHomEna = 0U; + * psConfig->filterClockSourceselection = false; + * psConfig->filterSampleCount = kEQDC_Filter3Samples; + * psConfig->filterSamplePeriod = 0U; + * psConfig->outputPulseMode = kEQDC_OutputPulseOnCounterEqualCompare; + * psConfig->positionCompareValue[0] = 0xFFFFFFFFU; + * psConfig->positionCompareValue[1] = 0xFFFFFFFFU; + * psConfig->positionCompareValue[2] = 0xFFFFFFFFU; + * psConfig->positionCompareValue[3] = 0xFFFFFFFFU; + * psConfig->revolutionCountCondition = kEQDC_RevolutionCountOnIndexPulse; + * psConfig->positionModulusValue = 0U; + * psConfig->positionInitialValue = 0U; + * psConfig->positionCounterValue = 0U; + * psConfig->enablePeriodMeasurement = false; + * psConfig->prescaler = kEQDC_Prescaler1; + * psConfig->enabledInterruptsMask = 0U; + * + * param psConfig Pointer to configuration structure. + */ +void EQDC_GetDefaultConfig(eqdc_config_t *psConfig) +{ + assert(NULL != psConfig); + + psConfig->enableReverseDirection = false; + psConfig->countOnce = false; + psConfig->operateMode = kEQDC_QuadratureDecodeOperationMode; /*!< Decode Mode. */ + psConfig->countMode = kEQDC_QuadratureX4; + psConfig->homeEnableInitPosCounterMode = kEQDC_HomeInitPosCounterDisabled; + psConfig->indexPresetInitPosCounterMode = kEQDC_IndexInitPosCounterDisabled; +#if (defined(FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD) && FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD) + psConfig->enableIndexInitPositionCounter = false; +#endif /* FSL_FEATURE_EQDC_CTRL2_HAS_EMIP_BIT_FIELD */ + psConfig->enableDma = false; + psConfig->bufferedRegisterLoadMode = false; + psConfig->enableTriggerInitPositionCounter = false; + psConfig->enableTriggerClearPositionRegisters = false; + psConfig->enableTriggerHoldPositionRegisters = false; + psConfig->enableWatchdog = false; + psConfig->watchdogTimeoutValue = 0xFFFFU; + psConfig->filterPhaseA = 0U; + psConfig->filterPhaseB = 0U; + psConfig->filterIndPre = 0U; + psConfig->filterHomEna = 0U; + psConfig->filterClockSourceselection = false; + psConfig->filterSampleCount = kEQDC_Filter3Samples; + psConfig->filterSamplePeriod = 0U; + psConfig->outputPulseMode = kEQDC_OutputPulseOnCounterEqualCompare; + psConfig->positionCompareValue[0] = 0xFFFFFFFFU; + psConfig->positionCompareValue[1] = 0xFFFFFFFFU; + psConfig->positionCompareValue[2] = 0xFFFFFFFFU; + psConfig->positionCompareValue[3] = 0xFFFFFFFFU; + psConfig->revolutionCountCondition = kEQDC_RevolutionCountOnIndexPulse; + psConfig->positionModulusValue = 0U; + psConfig->positionInitialValue = 0U; + psConfig->positionCounterValue = 0U; + psConfig->enablePeriodMeasurement = false; + psConfig->prescaler = kEQDC_Prescaler1; + psConfig->enabledInterruptsMask = 0U; +} + +/* + * Initializes the mode of operation. + * + * The Quadrature Decoder operates in following 4 operation modes: + * 1.Quadrature Decode(QDC) Operation Mode (CTRL[PH1] = 0,CTRL2[OPMODE] = 0) + * 2.Quadrature Count(QCT) Operation Mode (CTRL[PH1] = 0,CTRL2[OPMODE] = 1) + * 3.Single Phase Decode(PH1DC) Operation Mode (CTRL[PH1] = 1,CTRL2[OPMODE] = 0) + * 4.Single Phase Count(PH1CT) Operation Mode (CTRL[PH1] = 1,CTRL2[OPMODE] = 1) + * + * param base EQDC peripheral base address. + * param psConfig Pointer to configuration structure. + */ +void EQDC_SetOperateMode(EQDC_Type *base, eqdc_operate_mode_t operateMode) +{ + switch (operateMode) + { + case kEQDC_QuadratureDecodeOperationMode: + base->CTRL &= ~EQDC_CTRL_PH1_MASK; + base->CTRL2 &= ~EQDC_CTRL2_OPMODE_MASK; + break; + + case kEQDC_QuadratureCountOperationMode: + base->CTRL &= ~EQDC_CTRL_PH1_MASK; + base->CTRL2 |= EQDC_CTRL2_OPMODE_MASK; + break; + + case kEQDC_SinglePhaseDecodeOperationMode: + base->CTRL |= EQDC_CTRL_PH1_MASK; + base->CTRL2 &= ~EQDC_CTRL2_OPMODE_MASK; + break; + + case kEQDC_SinglePhaseCountOperationMode: + base->CTRL |= EQDC_CTRL_PH1_MASK; + base->CTRL2 |= EQDC_CTRL2_OPMODE_MASK; + break; + + default: + assert(false); + break; + } +} \ No newline at end of file diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_eqdc.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_eqdc.h new file mode 100644 index 00000000000..3f3ef5baf54 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_eqdc.h @@ -0,0 +1,1211 @@ +/* + * Copyright 2022, 2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_EQDC_H_ +#define FSL_EQDC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup eqdc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define FSL_EQDC_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) + +/*! @brief W1C bits in EQDC CTRL registers. */ +#define EQDC_CTRL_W1C_FLAGS (EQDC_CTRL_HIRQ_MASK | EQDC_CTRL_XIRQ_MASK | EQDC_CTRL_WDIRQ_MASK) + +/*! @brief W1C bits in EQDC INTCTRL registers. */ +#define EQDC_INTCTRL_W1C_FLAGS \ + (EQDC_INTCTRL_SABIRQ_MASK | EQDC_INTCTRL_DIRIRQ_MASK | EQDC_INTCTRL_RUIRQ_MASK | EQDC_INTCTRL_ROIRQ_MASK | \ + EQDC_INTCTRL_CMP0IRQ_MASK | EQDC_INTCTRL_CMP1IRQ_MASK | EQDC_INTCTRL_CMP2IRQ_MASK | EQDC_INTCTRL_CMP3IRQ_MASK) + +/*! @brief Interrupt enable bits in EQDC CTRL registers. */ +#define EQDC_CTRL_INT_EN (EQDC_CTRL_HIE_MASK | EQDC_CTRL_XIE_MASK | EQDC_CTRL_WDIE_MASK) + +/*! @brief Interrupt enable bits in EQDC INTCTRL registers. */ +#if (defined(FSL_FEATURE_EQDC_HAS_NO_COMPARE_INTERRUPT) && FSL_FEATURE_EQDC_HAS_NO_COMPARE_INTERRUPT) +#define EQDC_INTCTRL_INT_EN \ + (EQDC_INTCTRL_SABIE_MASK | EQDC_INTCTRL_DIRIE_MASK | EQDC_INTCTRL_RUIE_MASK | EQDC_INTCTRL_ROIE_MASK) +#else +#define EQDC_INTCTRL_INT_EN \ + (EQDC_INTCTRL_SABIE_MASK | EQDC_INTCTRL_DIRIE_MASK | EQDC_INTCTRL_RUIE_MASK | EQDC_INTCTRL_ROIE_MASK | \ + EQDC_INTCTRL_CMP0IE_MASK | EQDC_INTCTRL_CMP1IE_MASK | EQDC_INTCTRL_CMP2IE_MASK | EQDC_INTCTRL_CMP3IE_MASK) +#endif + +/*! @brief Interrupt flag bits in EQDC CTRL registers. */ +#define EQDC_CTRL_INT_FLAGS (EQDC_CTRL_HIRQ_MASK | EQDC_CTRL_XIRQ_MASK | EQDC_CTRL_WDIRQ_MASK) + +/*! @brief Interrupt flag bits in EQDC INTCTRL registers. */ +#define EQDC_INTCTRL_INT_FLAGS \ + (EQDC_INTCTRL_SABIRQ_MASK | EQDC_INTCTRL_DIRIRQ_MASK | EQDC_INTCTRL_RUIRQ_MASK | EQDC_INTCTRL_ROIRQ_MASK | \ + EQDC_INTCTRL_CMP0IRQ_MASK | EQDC_INTCTRL_CMP1IRQ_MASK | EQDC_INTCTRL_CMP2IRQ_MASK | EQDC_INTCTRL_CMP3IRQ_MASK) + +#if !(defined(FSL_FEATURE_EQDC_HAS_NO_COMPARE_INTERRUPT) && FSL_FEATURE_EQDC_HAS_NO_COMPARE_INTERRUPT) +#define kEQDC_PositionCompare0InerruptEnable kEQDC_PositionCompare0InterruptEnable +#define kEQDC_PositionCompare1InerruptEnable kEQDC_PositionCompare1InterruptEnable +#define kEQDC_PositionCompare2InerruptEnable kEQDC_PositionCompare2InterruptEnable +#define kEQDC_PositionCompare3InerruptEnable kEQDC_PositionCompare3InterruptEnable +#endif + +/*! + * @brief EQDC status flags, these flags indicate the counter's events. + * @anchor _eqdc_status_flags + */ +enum _eqdc_status_flags +{ + kEQDC_HomeEnableTransitionFlag = EQDC_CTRL_HIRQ_MASK, /*!< HOME/ENABLE signal transition occured. */ + kEQDC_IndexPresetPulseFlag = EQDC_CTRL_XIRQ_MASK, /*!< INDEX/PRESET pulse occured. */ + kEQDC_WatchdogTimeoutFlag = EQDC_CTRL_WDIRQ_MASK, /*!< Watchdog timeout occured. */ + + kEQDC_SimultPhaseChangeFlag = (uint32_t)EQDC_INTCTRL_SABIRQ_MASK + << 16U, /*!< Simultaneous change of PHASEA and PHASEB occured. */ + kEQDC_CountDirectionChangeFlag = (uint32_t)EQDC_INTCTRL_DIRIRQ_MASK + << 16U, /*!< Count direction change interrupt enable. */ + kEQDC_PositionRollOverFlag = (uint32_t)EQDC_INTCTRL_ROIRQ_MASK + << 16U, /*!< Position counter rolls over from 0xFFFFFFFF to 0, or + from MOD value to INIT value. */ + kEQDC_PositionRollUnderFlag = (uint32_t)EQDC_INTCTRL_RUIRQ_MASK + << 16U, /*!< Position register roll under from 0 to 0xFFFFFFFF, or + from INIT value to MOD value. */ + + kEQDC_PositionCompare0Flag = (uint32_t)EQDC_INTCTRL_CMP0IRQ_MASK + << 16U, /*!< Position counter match the COMP0 value. */ + kEQDC_PositionCompare1Flag = (uint32_t)EQDC_INTCTRL_CMP1IRQ_MASK + << 16U, /*!< Position counter match the COMP1 value. */ + kEQDC_PositionCompare2Flag = (uint32_t)EQDC_INTCTRL_CMP2IRQ_MASK + << 16U, /*!< Position counter match the COMP2 value. */ + kEQDC_PositionCompare3Flag = (uint32_t)EQDC_INTCTRL_CMP3IRQ_MASK + << 16U, /*!< Position counter match the COMP3 value. */ + + kEQDC_StatusAllFlags = kEQDC_HomeEnableTransitionFlag | kEQDC_IndexPresetPulseFlag | kEQDC_WatchdogTimeoutFlag | + kEQDC_SimultPhaseChangeFlag | kEQDC_PositionRollOverFlag | kEQDC_PositionRollUnderFlag | + kEQDC_PositionCompare0Flag | kEQDC_PositionCompare1Flag | kEQDC_PositionCompare2Flag | + kEQDC_PositionCompare3Flag +}; + +/*! + * @brief Signal status, these flags indicate the raw and filtered input signal status. + * @anchor _eqdc_signal_status + */ +enum _eqdc_signal_status +{ + kEQDC_SignalStatusRawHomeEnable = EQDC_IMR_HOME_ENABLE_MASK, /*!< Raw HOME/ENABLE input. */ + kEQDC_SignalStatusRawIndexPreset = EQDC_IMR_INDEX_PRESET_MASK, /*!< Raw INDEX/PRESET input. */ + kEQDC_SignalStatusRawPhaseB = EQDC_IMR_PHB_MASK, /*!< Raw PHASEB input. */ + kEQDC_SignalStatusRawPhaseA = EQDC_IMR_PHA_MASK, /*!< Raw PHASEA input. */ + kEQDC_SignalStatusFilteredHomeEnable = EQDC_IMR_FHOM_ENA_MASK, /*!< The filtered HOME/ENABLE input. */ + kEQDC_SignalStatusFilteredIndexPreset = EQDC_IMR_FIND_PRE_MASK, /*!< The filtered INDEX/PRESET input. */ + kEQDC_SignalStatusFilteredPhaseB = EQDC_IMR_FPHB_MASK, /*!< The filtered PHASEB input. */ + kEQDC_SignalStatusFilteredPhaseA = EQDC_IMR_FPHA_MASK, /*!< The filtered PHASEA input. */ + + kEQDC_SignalStatusPositionCompare0Flag = EQDC_IMR_CMPF0_MASK, /*!< Position Compare 0 Flag Output. */ + kEQDC_SignalStatusPositionCompare1Flag = EQDC_IMR_CMP1F_MASK, /*!< Position Compare 1 Flag Output. */ + kEQDC_SignalStatusPositionCompare2Flag = EQDC_IMR_CMP2F_MASK, /*!< Position Compare 2 Flag Output. */ + kEQDC_SignalStatusPositionCompare3Flag = EQDC_IMR_CMP3F_MASK, /*!< Position Compare 3 Flag Output. */ + kEQDC_SignalStatusCountDirectionFlagHold = EQDC_IMR_DIRH_MASK, /*!< Count Direction Flag Hold. */ + kEQDC_SignalStatusCountDirectionFlag = EQDC_IMR_DIR_MASK, /*!< Count Direction Flag Output. */ + + kEQDC_SignalStatusAllFlags = kEQDC_SignalStatusRawHomeEnable | kEQDC_SignalStatusRawIndexPreset | + kEQDC_SignalStatusRawPhaseB | kEQDC_SignalStatusRawPhaseA | + kEQDC_SignalStatusFilteredHomeEnable | kEQDC_SignalStatusFilteredIndexPreset | + kEQDC_SignalStatusFilteredPhaseB | kEQDC_SignalStatusFilteredPhaseA | + kEQDC_SignalStatusPositionCompare0Flag | kEQDC_SignalStatusPositionCompare1Flag | + kEQDC_SignalStatusPositionCompare2Flag | kEQDC_SignalStatusPositionCompare3Flag | + kEQDC_SignalStatusCountDirectionFlagHold | kEQDC_SignalStatusCountDirectionFlag +}; + +/*! + * @brief Interrupt enable/disable mask. + * @anchor _eqdc_interrupt_enable + */ +enum _eqdc_interrupt_enable +{ + kEQDC_HomeEnableTransitionInterruptEnable = + EQDC_CTRL_HIE_MASK, /*!< HOME/ENABLE signal transition interrupt enable. */ + kEQDC_IndexPresetPulseInterruptEnable = EQDC_CTRL_XIE_MASK, /*!< INDEX/PRESET pulse interrupt enable. */ + kEQDC_WatchdogTimeoutInterruptEnable = EQDC_CTRL_WDIE_MASK, /*!< Watchdog timeout interrupt enable. */ + + kEQDC_SimultPhaseChangeInterruptEnable = (uint32_t)EQDC_INTCTRL_SABIE_MASK + << 16U, /*!< Simultaneous PHASEA and PHASEB change interrupt enable. */ + kEQDC_CountDirectionChangeInterruptEnable = (uint32_t)EQDC_INTCTRL_DIRIE_MASK + << 16U, /*!< Count direction change interrupt enable. */ + kEQDC_PositionRollOverInterruptEnable = (uint32_t)EQDC_INTCTRL_ROIE_MASK << 16U, /*!< Roll-over interrupt enable. */ + kEQDC_PositionRollUnderInterruptEnable = (uint32_t)EQDC_INTCTRL_RUIE_MASK + << 16U, /*!< Roll-under interrupt enable. */ + +#if !(defined(FSL_FEATURE_EQDC_HAS_NO_COMPARE_INTERRUPT) && FSL_FEATURE_EQDC_HAS_NO_COMPARE_INTERRUPT) + kEQDC_PositionCompare0InterruptEnable = (uint32_t)EQDC_INTCTRL_CMP0IE_MASK + << 16U, /*!< Position compare 0 interrupt enable. */ + kEQDC_PositionCompare1InterruptEnable = (uint32_t)EQDC_INTCTRL_CMP1IE_MASK + << 16U, /*!< Position compare 1 interrupt enable. */ + kEQDC_PositionCompare2InterruptEnable = (uint32_t)EQDC_INTCTRL_CMP2IE_MASK + << 16U, /*!< Position compare 2 interrupt enable. */ + kEQDC_PositionCompare3InterruptEnable = (uint32_t)EQDC_INTCTRL_CMP3IE_MASK + << 16U, /*!< Position compare 3 interrupt enable. */ +#endif + +#if (defined(FSL_FEATURE_EQDC_HAS_NO_COMPARE_INTERRUPT) && FSL_FEATURE_EQDC_HAS_NO_COMPARE_INTERRUPT) + kEQDC_AllInterruptEnable = kEQDC_HomeEnableTransitionInterruptEnable | kEQDC_IndexPresetPulseInterruptEnable | + kEQDC_WatchdogTimeoutInterruptEnable | kEQDC_SimultPhaseChangeInterruptEnable | + kEQDC_CountDirectionChangeInterruptEnable | kEQDC_PositionRollOverInterruptEnable | + kEQDC_PositionRollUnderInterruptEnable +#else + kEQDC_AllInterruptEnable = kEQDC_HomeEnableTransitionInterruptEnable | kEQDC_IndexPresetPulseInterruptEnable | + kEQDC_WatchdogTimeoutInterruptEnable | kEQDC_SimultPhaseChangeInterruptEnable | + kEQDC_CountDirectionChangeInterruptEnable | kEQDC_PositionRollOverInterruptEnable | + kEQDC_PositionRollUnderInterruptEnable | kEQDC_PositionCompare0InterruptEnable | + kEQDC_PositionCompare1InterruptEnable | kEQDC_PositionCompare2InterruptEnable | + kEQDC_PositionCompare3InterruptEnable +#endif +}; + +/*! + * @brief Define HOME/ENABLE signal's trigger mode. + */ +typedef enum _eqdc_home_enable_init_pos_counter_mode +{ + /*! Don't use HOME/ENABLE signal to initialize the position counter. */ + kEQDC_HomeInitPosCounterDisabled = 0U, + + /*! Use positive going edge to trigger initialization of position counters. */ + kEQDC_HomeInitPosCounterOnRisingEdge = EQDC_CTRL_HIP_MASK, + + /*! Use negative going edge to trigger initialization of position counters. */ + kEQDC_HomeInitPosCounterOnFallingEdge = EQDC_CTRL_HIP_MASK | EQDC_CTRL_HNE_MASK, +} eqdc_home_enable_init_pos_counter_mode_t; + +/*! + * @brief Define INDEX/PRESET signal's trigger mode. + */ +typedef enum _eqdc_index_preset_init_pos_counter_mode +{ + /*! INDEX/PRESET pulse does not initialize the position counter. */ + kEQDC_IndexInitPosCounterDisabled = 0U, + + /*! Use INDEX/PRESET pulse rising edge to initialize position counter. */ + kEQDC_IndexInitPosCounterOnRisingEdge = EQDC_CTRL_XIP_MASK, + + /*! Use INDEX/PRESET pulse falling edge to initialize position counter. */ + kEQDC_IndexInitPosCounterOnFallingEdge = EQDC_CTRL_XIP_MASK | EQDC_CTRL_XNE_MASK, +} eqdc_index_preset_init_pos_counter_mode_t; + +/*! + * @brief Define type for decoder opertion mode. + * + * The Quadrature Decoder operates in following 4 operation modes: + * 1.Quadrature Decode(QDC) Operation Mode (CTRL[PH1] = 0,CTRL2[OPMODE] = 0) + * In QDC operation mode, Module uses PHASEA, PHASEB, INDEX, HOME, TRIGGER + * and ICAP[3:1] to decode the PHASEA and PHASEB signals from Speed/Position sensor. + * 2.Quadrature Count(QCT) Operation Mode (CTRL[PH1] = 0,CTRL2[OPMODE] = 1) + * In QCT operation mode, Module uses PHASEA, PHASEB, PRESET, ENABLE, + * TRIGGER and ICAP[3:1] to count the PHASEA and PHASEB signals from Speed/Position sensor. + * 3.Single Phase Decode(PH1DC) Operation Mode (CTRL[PH1] = 1,CTRL2[OPMODE] = 0) + * In PH1DC operation mode, the module uses PHASEA, PHASEB, INDEX, HOME, + * TRIGGER and ICAP[3:1] to decode the PHASEA and PHASEB signals from Speed/Position sensor. + * 4.Single Phase Count(PH1CT) Operation Mode (CTRL[PH1] = 1,CTRL2[OPMODE] = 1) + * In PH1CT operation mode, the module uses PHASEA, PHASEB, PRESET, ENABLE, + * TRIGGER and ICAP[3:1] to count the PHASEA and PHASEB signals from Speed/Position sensor. + */ +typedef enum _eqdc_operate_mode +{ + kEQDC_QuadratureDecodeOperationMode = 0U, /*!< Use standard quadrature decoder with PHASEA/PHASEB, INDEX/HOME. */ + kEQDC_QuadratureCountOperationMode, /*!< Use quadrature count operation mode with PHASEA/PHASEB, PRESET/ENABLE. */ + kEQDC_SinglePhaseDecodeOperationMode, /*!< Use single phase quadrature decoder with PHASEA/PHASEB, INDEX/HOME. */ + kEQDC_SinglePhaseCountOperationMode, /*!< Use single phase count decoder with PHASEA/PHASEB, PRESET/ENABLE. */ +} eqdc_operate_mode_t; + +/*! + * @brief Define type for decoder count mode. + * + * In decode mode, it uses the standard quadrature decoder with PHASEA and PHASEB, + * PHASEA = 0 and PHASEB = 0 mean reverse direction. + * - If PHASEA leads PHASEB, then motion is in the positive direction. + * - If PHASEA trails PHASEB,then motion is in the negative direction. + * In single phase mode, there are three count modes: + * - In Signed Count mode (Single Edge). Both position counter (POS) and position difference counter (POSD) count + * on the input PHASEA rising edge while the input PHASEB provides the selected position counter direction + * (up/down). If CTRL[REV] is 1, then the position counter will count in the opposite direction. + * - In Signed Count mode (double edge), both position counter (POS) and + * position difference counter (POSD) count the input PHASEA on both rising edge and falling edge while the input + * PHASEB provides the selected position counter direction (up/down). + * - In UP/DOWN Pulse Count mode. Both position counter (POS) and position difference counter (POSD) count in the + * up direction when input PHASEA rising edge occurs. Both counters count in the down direction when input PHASEB rising + * edge occurs. If CTRL[REV] is 1, then the position counter will count in the opposite direction. + */ +typedef enum _eqdc_count_mode +{ + kEQDC_QuadratureX4 = 0U, /*!< Active on kEQDC_QuadratureDecodeOperationMode/kEQDC_QuadratureCountOperationMode. */ + kEQDC_QuadratureX2 = 1U, /*!< Active on kEQDC_QuadratureDecodeOperationMode/kEQDC_QuadratureCountOperationMode. */ + kEQDC_QuadratureX1 = 2U, /*!< Active on kEQDC_QuadratureDecodeOperationMode/kEQDC_QuadratureCountOperationMode. */ + kEQDC_UpDownPulseCount = + 0U, /*!< Active on kEQDC_SinglePhaseDecodeOperationMode/kEQDC_SinglePhaseCountOperationMode. */ + kEQDC_SignedCountDoubleEdge = + 1U, /*!< Active on kEQDC_SinglePhaseDecodeOperationMode/kEQDC_SinglePhaseCountOperationMode. */ + kEQDC_SignedCountSingleEdge = + 2U, /*!< Active on kEQDC_SinglePhaseDecodeOperationMode/kEQDC_SinglePhaseCountOperationMode. */ +} eqdc_count_mode_t; + +/*! + * @brief Define type for the condition of POSMATCH pulses. + */ +typedef enum _eqdc_output_pulse_mode +{ + kEQDC_OutputPulseOnCounterEqualCompare = 0U, /*!< POSMATCH pulses when a match occurs between the position counters + (POS) and the compare value (UCOMPx/LCOMPx)(x range is 0-3). */ + kEQDC_OutputPulseOnReadingPositionCounter, /*!< POSMATCH pulses when reading position counter(POS and LPOS), + revolution counter(REV), position difference counter(POSD). */ +} eqdc_output_pulse_mode_t; + +/*! + * @brief Define type for determining how the revolution counter (REV) is incremented/decremented. + */ +typedef enum _eqdc_revolution_count_condition +{ + kEQDC_RevolutionCountOnIndexPulse = 0U, /*!< Use INDEX pulse to increment/decrement revolution counter. */ + kEQDC_RevolutionCountOnRollOverModulus, /*!< Use modulus counting roll-over/under to increment/decrement revolution + counter. */ +} eqdc_revolution_count_condition_t; + +/*! + * @brief Input Filter Sample Count + * + * The Input Filter Sample Count represents the number of consecutive samples + * that must agree, before the input filter accepts an input transition + */ +typedef enum _eqdc_filter_sample_count +{ + kEQDC_Filter3Samples = 0U, /*!< 3 samples. */ + kEQDC_Filter4Samples = 1U, /*!< 4 samples. */ + kEQDC_Filter5Samples = 2U, /*!< 5 samples. */ + kEQDC_Filter6Samples = 3U, /*!< 6 samples. */ + kEQDC_Filter7Samples = 4U, /*!< 7 samples. */ + kEQDC_Filter8Samples = 5U, /*!< 8 samples. */ + kEQDC_Filter9Samples = 6U, /*!< 9 samples. */ + kEQDC_Filter10Samples = 7U, /*!< 10 samples. */ +} eqdc_filter_sample_count_t; + +/*! + * @brief Count direction. + */ +typedef enum _eqdc_count_direction_flag +{ + kEQDC_CountDirectionDown = 0U, /*!< Last count was in down direction. */ + kEQDC_CountDirectionUp, /*!< Last count was in up direction. */ +} eqdc_count_direction_flag_t; + +/*! + * @brief Prescaler used by Last Edge Time (LASTEDGE) and + * Position Difference Period Counter (POSDPER). + */ +typedef enum _eqdc_prescaler +{ + kEQDC_Prescaler1 = 0U, /*!< Prescaler value 1. */ + kEQDC_Prescaler2 = 1U, /*!< Prescaler value 2. */ + kEQDC_Prescaler4 = 2U, /*!< Prescaler value 4. */ + kEQDC_Prescaler8 = 3U, /*!< Prescaler value 8. */ + kEQDC_Prescaler16 = 4U, /*!< Prescaler value 16. */ + kEQDC_Prescaler32 = 5U, /*!< Prescaler value 32. */ + kEQDC_Prescaler64 = 6U, /*!< Prescaler value 64. */ + kEQDC_Prescaler128 = 7U, /*!< Prescaler value 128. */ + kEQDC_Prescaler256 = 8U, /*!< Prescaler value 256. */ + kEQDC_Prescaler512 = 9U, /*!< Prescaler value 512. */ + kEQDC_Prescaler1024 = 10U, /*!< Prescaler value 1024. */ + kEQDC_Prescaler2048 = 11U, /*!< Prescaler value 2048. */ + kEQDC_Prescaler4096 = 12U, /*!< Prescaler value 4096. */ + kEQDC_Prescaler8192 = 13U, /*!< Prescaler value 8192. */ + kEQDC_Prescaler16384 = 14U, /*!< Prescaler value 16384. */ + kEQDC_Prescaler32768 = 15U, /*!< Prescaler value 32768. */ +} eqdc_prescaler_t; + +/*! + * @brief Define user configuration structure for EQDC module. + */ +typedef struct _eqdc_config +{ + /* Basic counter. */ + bool enableReverseDirection; /*!< Enable reverse direction counting. */ + bool countOnce; /*!< Selects modulo loop or one shot counting mode. */ + + bool enableDma; /*!< Enable DMA for new written buffer values of COMPx/INIT/MOD(x range is 0-3) */ + bool bufferedRegisterLoadMode; /*!enableReverseDirection = false; + psConfig->countOnce = false; + psConfig->operateMode = kEQDC_QuadratureDecodeOperationMode; + psConfig->countMode = kEQDC_QuadratureX4; + psConfig->homeEnableInitPosCounterMode = kEQDC_HomeInitPosCounterDisabled; + psConfig->indexPresetInitPosCounterMode = kEQDC_IndexInitPosCounterDisabled; + psConfig->enableIndexInitPositionCounter = false; + psConfig->enableDma = false; + psConfig->bufferedRegisterLoadMode = false; + psConfig->enableTriggerInitPositionCounter = false; + psConfig->enableTriggerClearPositionRegisters = false; + psConfig->enableTriggerHoldPositionRegisters = false; + psConfig->enableWatchdog = false; + psConfig->watchdogTimeoutValue = 0xFFFFU; + psConfig->filterPhaseA = 0U; + psConfig->filterPhaseB = 0U; + psConfig->filterIndPre = 0U; + psConfig->filterHomEna = 0U; + psConfig->filterClockSourceselection = false; + psConfig->filterSampleCount = kEQDC_Filter3Samples; + psConfig->filterSamplePeriod = 0U; + psConfig->outputPulseMode = kEQDC_OutputPulseOnCounterEqualCompare; + psConfig->positionCompareValue[0] = 0xFFFFFFFFU; + psConfig->positionCompareValue[1] = 0xFFFFFFFFU; + psConfig->positionCompareValue[2] = 0xFFFFFFFFU; + psConfig->positionCompareValue[3] = 0xFFFFFFFFU; + psConfig->revolutionCountCondition = kEQDC_RevolutionCountOnIndexPulse; + psConfig->positionModulusValue = 0U; + psConfig->positionInitialValue = 0U; + psConfig->positionCounterValue = 0U; + psConfig->enablePeriodMeasurement = false; + psConfig->prescaler = kEQDC_Prescaler1; + psConfig->enabledInterruptsMask = 0U; + @endcode + * + * @param psConfig Pointer to configuration structure. + */ +void EQDC_GetDefaultConfig(eqdc_config_t *psConfig); + +/*! + * @brief De-initializes the EQDC module. + * + * This function deinitializes the EQDC by disabling the IP bus clock (optional). + * + * @param base EQDC peripheral base address. + */ +void EQDC_Deinit(EQDC_Type *base); + +/*! + * @brief Initializes the mode of operation. + * + * This function initializes mode of operation by enabling the IP bus clock (optional). + * + * @param base EQDC peripheral base address. + * @param operateMode Select operation mode. + */ +void EQDC_SetOperateMode(EQDC_Type *base, eqdc_operate_mode_t operateMode); + +/*! + * @brief Initializes the mode of count. + * + * These bits control the basic counting and behavior of Position Counter and Position Difference Counter. + * Setting CTRL[REV] to 1 can reverse the counting direction. + * 1.In quadrature Mode (CTRL[PH1] = 0): + * 00b - CM0: Normal/Reverse Quadrature X4 + * 01b - CM1: Normal/Reverse Quadrature X2 + * 10b - CM2: Normal/Reverse Quadrature X1 + * 11b - CM3: Reserved + * 2.In Single Phase Mode (CTRL[PH1] = 1): + * 00b - CM0: UP/DOWN Pulse Count Mode + * 01b - CM1: Signed Mode, count PHASEA rising/falling edge, position counter counts up when PHASEB + * is low and counts down when PHASEB is high + * 10b - CM2: Signed Count Mode,count PHASEA rising edge only, position counter counts up when + * PHASEB is low and counts down when PHASEB is high + * 11b - CM3: Reserved + * + * @param base EQDC peripheral base address. + * @param countMode Select count mode. + */ +static inline void EQDC_SetCountMode(EQDC_Type *base, eqdc_count_mode_t countMode) +{ + base->CTRL2 = (base->CTRL2 & (uint16_t)(~EQDC_CTRL2_CMODE_MASK)) | EQDC_CTRL2_CMODE(countMode); +} + +/*! @} */ + +/*! + * @name Watchdog + * @{ + */ + +/*! + * @brief Enable watchdog for EQDC module. + * + * @param base EQDC peripheral base address + * @param bEnable Enables or disables the watchdog + */ +static inline void EQDC_EnableWatchdog(EQDC_Type *base, bool bEnable) +{ + if (bEnable) + { + base->CTRL = (base->CTRL & (~EQDC_CTRL_W1C_FLAGS)) | EQDC_CTRL_WDE_MASK; + } + else + { + base->CTRL = (base->CTRL & (~(EQDC_CTRL_W1C_FLAGS | EQDC_CTRL_WDE_MASK))); + } +} + +/*! + * @brief Set watchdog timeout value. + * + * @param base EQDC peripheral base address + * @param u16Timeout Number of clock cycles, plus one clock cycle that the + * watchdog timer counts before timing out + */ +static inline void EQDC_SetWatchdogTimeout(EQDC_Type *base, uint16_t u16Timeout) +{ + base->WTR = u16Timeout; +} + +/*! @} */ + +/*! + * @name DMA + * @{ + */ + +/*! + * @brief Enable DMA for EQDC module. + * + * @param base EQDC peripheral base address + * @param bEnable Enables or disables the DMA + */ +static inline void EQDC_EnableDMA(EQDC_Type *base, bool bEnable) +{ + if (bEnable) + { + base->CTRL |= EQDC_CTRL_DMAEN_MASK; + } + else + { +#if (defined(FSL_FEATURE_EQDC_HAS_ERRATA_051383) && FSL_FEATURE_EQDC_HAS_ERRATA_051383) + /* Quadrature decoder CTRL[DMAEN] bit can not be cleared except do EQDC reset*/ + assert(false); +#else + base->CTRL &= ~EQDC_CTRL_DMAEN_MASK; +#endif + } +} + +/*! @} */ + +/*! + * @name Double-set Registers Loading Operation + * @{ + */ + +/*! + * @brief Set Buffered Register Load (Update) Mode. + * + * This bit selects the loading time point of the buffered compare registers UCOMPx/LCOMPx, x=0~3, + * initial register (UINIT/LINIT), and modulus register (UMOD/LMOD). + * Buffered registers are loaded and take effect at the next roll-over or roll-under if CTRL[LDOK] is set. + * + * @param base EQDC peripheral base address + */ +static inline void EQDC_SetBufferedRegisterLoadUpdateMode(EQDC_Type *base) +{ + base->CTRL2 |= EQDC_CTRL2_LDMOD_MASK; +} + +/*! + * @brief Clear Buffered Register Load (Update) Mode. + * + * Buffered Register Load (Update) Mode bit selects the loading time point of the buffered compare registers + * UCOMPx/LCOMPx, x=0~3, initial register (UINIT/LINIT), and modulus register (UMOD/LMOD). Buffered registers are loaded + * and take effect immediately upon CTRL[LDOK] is set. + * + * @param base EQDC peripheral base address + */ +static inline void EQDC_ClearBufferedRegisterLoadUpdateMode(EQDC_Type *base) +{ + base->CTRL2 &= ~EQDC_CTRL2_LDMOD_MASK; +} + +/*! + * @brief Set load okay. + * + * Load okay enables that the outer-set values of buffered compare registers (UCOMPx/LCOMPx, x=0~3), + * initial register(UINIT/LINIT) and modulus register(UMOD/LMOD) can be loaded into their inner-sets and + * take effect. + * When LDOK is set, this loading action occurs at the next position counter roll-over or roll-under if + * CTRL2[LDMOD] is set, or it occurs immediately if CTRL2[LDMOD] is cleared. LDOK is automatically + * cleared after the values in outer-set is loaded into the inner-set. + * + * @param base EQDC peripheral base address. + */ +static inline void EQDC_SetEqdcLdok(EQDC_Type *base) +{ + base->CTRL |= EQDC_CTRL_LDOK_MASK; +} + +/*! + * @brief Get load okay. + * + * @param base EQDC peripheral base address. + */ +static inline uint8_t EQDC_GetEqdcLdok(EQDC_Type *base) +{ + return base->CTRL & EQDC_CTRL_LDOK_MASK; +} + +/*! + * @brief Clear load okay. + * + * @param base EQDC peripheral base address. + */ +static inline void EQDC_ClearEqdcLdok(EQDC_Type *base) +{ + base->CTRL &= ~EQDC_CTRL_LDOK_MASK; +} + +/*! @} */ + +/*! + * @name Status + * @{ + */ +/*! + * @brief Get the status flags. + * + * @param base EQDC peripheral base address. + * + * @return Logical OR'ed value of the status flags, @ref _eqdc_status_flags. + */ +static inline uint32_t EQDC_GetStatusFlags(EQDC_Type *base) +{ + uint32_t u32Flags = 0U; + + u32Flags = (uint32_t)(base->CTRL) & EQDC_CTRL_INT_FLAGS; + + u32Flags |= ((uint32_t)(base->INTCTRL) & EQDC_INTCTRL_INT_FLAGS) << 16; + return u32Flags; +} + +/*! + * @brief Clear the status flags. + * + * @param base EQDC peripheral base address. + * @param u32Flags Logical OR'ed value of the flags to clear, @ref _eqdc_status_flags. + */ +static inline void EQDC_ClearStatusFlags(EQDC_Type *base, uint32_t u32Flags) +{ + if (0U != (u32Flags & EQDC_CTRL_INT_FLAGS)) + { + base->CTRL = (base->CTRL & (~EQDC_CTRL_W1C_FLAGS)) | (u32Flags & EQDC_CTRL_INT_FLAGS); + } + + if (0U != ((u32Flags >> 16) & EQDC_INTCTRL_INT_FLAGS)) + { + base->INTCTRL = (base->INTCTRL & (~EQDC_INTCTRL_W1C_FLAGS)) | ((u32Flags >> 16) & EQDC_INTCTRL_INT_FLAGS); + } +} + +/*! + * @brief Get the signals' real-time status. + * + * @param base EQDC peripheral base address. + * @return Logical OR'ed value of the real-time signal status, @ref _eqdc_signal_status. + */ +static inline uint16_t EQDC_GetSignalStatusFlags(EQDC_Type *base) +{ + return base->IMR; +} + +/*! + * @brief Get the direction of the last count. + * + * @param base EQDC peripheral base address. + * @return Direction of the last count. + */ +static inline eqdc_count_direction_flag_t EQDC_GetLastCountDirection(EQDC_Type *base) +{ + return ((0U != (base->IMR & EQDC_IMR_DIR_MASK)) ? kEQDC_CountDirectionUp : kEQDC_CountDirectionDown); +} +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enable the interrupts. + * + * @param base EQDC peripheral base address. + * @param u32Interrupts Logical OR'ed value of the interrupts, @ref _eqdc_interrupt_enable. + */ +static inline void EQDC_EnableInterrupts(EQDC_Type *base, uint32_t u32Interrupts) +{ + if (0U != (u32Interrupts & EQDC_CTRL_INT_EN)) + { + base->CTRL = (base->CTRL & (~EQDC_CTRL_W1C_FLAGS)) | (u32Interrupts & EQDC_CTRL_INT_EN); + } + + if (0U != ((u32Interrupts >> 16) & EQDC_INTCTRL_INT_EN)) + { + base->INTCTRL = (base->INTCTRL & (~EQDC_INTCTRL_W1C_FLAGS)) | ((u32Interrupts >> 16) & EQDC_INTCTRL_INT_EN); + } +} + +/*! + * @brief Disable the interrupts. + * + * @param base EQDC peripheral base address. + * @param u32Interrupts Logical OR'ed value of the interrupts, @ref _eqdc_interrupt_enable. + */ +static inline void EQDC_DisableInterrupts(EQDC_Type *base, uint32_t u32Interrupts) +{ + if (0U != (u32Interrupts & EQDC_CTRL_INT_EN)) + { + base->CTRL = (base->CTRL & (~EQDC_CTRL_W1C_FLAGS)) & (~(u32Interrupts & EQDC_CTRL_INT_EN)); + } + + if (0U != ((u32Interrupts >> 16) & EQDC_INTCTRL_INT_EN)) + { + base->INTCTRL = (base->INTCTRL & (~EQDC_INTCTRL_W1C_FLAGS)) & (~((u32Interrupts >> 16) & EQDC_INTCTRL_INT_EN)); + } +} + +/*! @} */ + +/*! + * @name Counter Operation + * @{ + */ + +/*! + * @brief Load the initial position value to position counter. + * + * Software trigger to load the initial position value (UINIT and LINIT) contents + * to position counter (UPOS and LPOS), so that to provide the consistent + * operation the position counter registers. + * + * @param base EQDC peripheral base address. + */ +static inline void EQDC_DoSoftwareLoadInitialPositionValue(EQDC_Type *base) +{ + base->CTRL = (base->CTRL & (~EQDC_CTRL_W1C_FLAGS)) | EQDC_CTRL_SWIP_MASK; +} + +/*! + * @brief Set initial position value for EQDC module. + * + * Set the position counter initial value (UINIT, LINIT). + * After writing values to the UINIT and LINIT registers, the values are "buffered" into outer-set + * registers temporarily. Values will be loaded into inner-set registers and take effect using + * the following two methods: + * 1. If CTRL2[LDMODE] is 1, "buffered" values are loaded into inner-set and take effect + * at the next roll-over or roll-under if CTRL[LDOK] is set. + * 2. If CTRL2[LDMODE] is 0, "buffered" values are loaded into inner-set and take effect + * immediately when CTRL[LDOK] is set. + * + * @param base EQDC peripheral base address + * @param u32PositionInitValue Position initial value + */ +static inline void EQDC_SetInitialPositionValue(EQDC_Type *base, uint32_t u32PositionInitValue) +{ + base->UINIT = (uint16_t)(u32PositionInitValue >> 16U); + base->LINIT = (uint16_t)(u32PositionInitValue); +} + +/*! + * @brief Set position counter value. + * + * Set the position counter value (POS or UPOS, LPOS). + * + * @param base EQDC peripheral base address + * @param positionCounterValue Position counter value + */ +static inline void EQDC_SetPositionCounterValue(EQDC_Type *base, uint32_t positionCounterValue) +{ + base->UPOS = (uint16_t)(positionCounterValue >> 16U); + base->LPOS = (uint16_t)(positionCounterValue); +} + +/*! + * @brief Set position counter modulus value. + * + * Set the position counter modulus value (UMOD, LMOD). + * After writing values to the UMOD and LMOD registers, the values are "buffered" into outer-set + * registers temporarily. Values will be loaded into inner-set registers and take effect using + * the following two methods: + * 1. If CTRL2[LDMODE] is 1, "buffered" values are loaded into inner-set and take effect + * at the next roll-over or roll-under if CTRL[LDOK] is set. + * 2. If CTRL2[LDMODE] is 0, "buffered" values are loaded into inner-set and take effect + * immediately when CTRL[LDOK] is set. + * + * @param base EQDC peripheral base address + * @param positionModulusValue Position modulus value + */ +static inline void EQDC_SetPositionModulusValue(EQDC_Type *base, uint32_t positionModulusValue) +{ + base->UMOD = (uint16_t)(positionModulusValue >> 16U); + base->LMOD = (uint16_t)(positionModulusValue); +} + +/*! + * @brief Set position counter compare 0 value. + * + * Set the position counter compare 0 value (UCOMP0, LCOMP0). + * After writing values to the UCOMP0 and LCOMP0 registers, the values are "buffered" into outer-set + * registers temporarily. Values will be loaded into inner-set registers and take effect using + * the following two methods: + * 1. If CTRL2[LDMODE] is 1, "buffered" values are loaded into inner-set and take effect + * at the next roll-over or roll-under if CTRL[LDOK] is set. + * 2. If CTRL2[LDMODE] is 0, "buffered" values are loaded into inner-set and take effect + * immediately when CTRL[LDOK] is set. + * + * @param base EQDC peripheral base address + * @param u32PositionComp0Value Position modulus value + */ +static inline void EQDC_SetPositionCompare0Value(EQDC_Type *base, uint32_t u32PositionComp0Value) +{ + base->UCOMP0 = (uint16_t)(u32PositionComp0Value >> 16U); + base->LCOMP0 = (uint16_t)(u32PositionComp0Value); +} + +/*! + * @brief Set position counter compare 1 value. + * + * Set the position counter compare 1 value (UCOMP1, LCOMP1). + * After writing values to the UCOMP1 and LCOMP1 registers, the values are "buffered" into outer-set + * registers temporarily. Values will be loaded into inner-set registers and take effect using + * the following two methods: + * 1. If CTRL2[LDMODE] is 1, "buffered" values are loaded into inner-set and take effect + * at the next roll-over or roll-under if CTRL[LDOK] is set. + * 2. If CTRL2[LDMODE] is 0, "buffered" values are loaded into inner-set and take effect + * immediately when CTRL[LDOK] is set. + * + * @param base EQDC peripheral base address + * @param u32PositionComp1Value Position modulus value + */ +static inline void EQDC_SetPositionCompare1Value(EQDC_Type *base, uint32_t u32PositionComp1Value) +{ + base->UCOMP1 = (uint16_t)(u32PositionComp1Value >> 16U); + base->LCOMP1 = (uint16_t)(u32PositionComp1Value); +} + +/*! + * @brief Set position counter compare 2 value. + * + * Set the position counter compare 2 value (UCOMP2, LCOMP2). + * After writing values to the UCOMP2 and LCOMP2 registers, the values are "buffered" into outer-set + * registers temporarily. Values will be loaded into inner-set registers and take effect using + * the following two methods: + * 1. If CTRL2[LDMODE] is 1, "buffered" values are loaded into inner-set and take effect + * at the next roll-over or roll-under if CTRL[LDOK] is set. + * 2. If CTRL2[LDMODE] is 0, "buffered" values are loaded into inner-set and take effect + * immediately when CTRL[LDOK] is set. + * + * @param base EQDC peripheral base address + * @param u32PositionComp2Value Position modulus value + */ +static inline void EQDC_SetPositionCompare2Value(EQDC_Type *base, uint32_t u32PositionComp2Value) +{ + base->UCOMP2 = (uint16_t)(u32PositionComp2Value >> 16U); + base->LCOMP2 = (uint16_t)(u32PositionComp2Value); +} + +/*! + * @brief Set position counter compare 3 value. + * + * Set the position counter compare 3 value (UCOMP3, LCOMP3). + * After writing values to the UCOMP3 and LCOMP3 registers, the values are "buffered" into outer-set + * registers temporarily. Values will be loaded into inner-set registers and take effect using + * the following two methods: + * 1. If CTRL2[LDMODE] is 1, "buffered" values are loaded into inner-set and take effect + * at the next roll-over or roll-under if CTRL[LDOK] is set. + * 2. If CTRL2[LDMODE] is 0, "buffered" values are loaded into inner-set and take effect + * immediately when CTRL[LDOK] is set. + * + * @param base EQDC peripheral base address + * @param u32PositionComp3Value Position modulus value + */ +static inline void EQDC_SetPositionCompare3Value(EQDC_Type *base, uint32_t u32PositionComp3Value) +{ + base->UCOMP3 = (uint16_t)(u32PositionComp3Value >> 16U); + base->LCOMP3 = (uint16_t)(u32PositionComp3Value); +} + +/*! + * @brief Get the current position counter's value. + * + * @param base EQDC peripheral base address. + * + * @return Current position counter's value. + */ +static inline uint32_t EQDC_GetPosition(EQDC_Type *base) +{ + uint32_t u32Pos; + + u32Pos = base->UPOS; /* Get upper 16 bits and make a snapshot. */ + u32Pos <<= 16U; + u32Pos |= base->LPOSH; /* Get lower 16 bits from hold register. */ + + return u32Pos; +} + +/*! + * @brief Get the hold position counter's value. + * + * The position counter (POS or UPOS, LPOS) value is loaded to hold position (POSH or UPOSH, LPOSH) + * when: + * 1. Position register (POS or UPOS, LPOS), or position difference register (POSD), + * or revolution register (REV) is read. + * 2. TRIGGER happens and TRIGGER is enabled to update the hold registers. + * + * @param base EQDC peripheral base address. + * @return Hold position counter's value. + */ +static inline uint32_t EQDC_GetHoldPosition(EQDC_Type *base) +{ + uint32_t u32Pos; + + u32Pos = base->UPOSH; /* Get upper 16 bits from hold register. */ + u32Pos <<= 16U; + u32Pos |= base->LPOSH; /* Get lower 16 bits from hold register. */ + + return u32Pos; +} + +/*! + * @brief Get the hold position counter1's value. + * + * The Upper Position Counter Hold Register 1(UPOSH1) shares the same address with UCOMP1. + * When read, this register means the value of UPOSH1, which is the upper 16 bits of POSH1. + * The Lower Position Counter Hold Register 1(LPOSH1) shares the same address with LCOMP1. + * When read, this register means the value of LPOSH1, which is the lower 16 bits of POSH1. + * Position counter is captured into POSH1 on the rising edge of ICAP[1]. + * + * @param base EQDC peripheral base address. + * @return Hold position counter1's value. + */ +static inline uint32_t EQDC_GetHoldPosition1(EQDC_Type *base) +{ + uint32_t u32Pos; + + u32Pos = base->UPOSH1; /* Get upper 16 bits from hold register. */ + u32Pos <<= 16U; + u32Pos |= base->LPOSH1; /* Get lower 16 bits from hold register. */ + + return u32Pos; +} + +/*! + * @brief Get the hold position counter2's value. + * + * The Upper Position Counter Hold Register 2(UPOSH2) shares the same address with UCOMP2. + * When read,this register means the value of UPOSH2, which is the upper 16 bits of POSH2. + * The Lower Position Counter Hold Register 2(LPOSH2) shares the same address with LCOMP2. + * When read, this register means the value of LPOSH2, which is the lower 16 bits of POSH2. + * Position counter is captured into POSH2 on the rising edge of ICAP[2]. + * + * @param base EQDC peripheral base address. + * @return Hold position counter2's value. + */ +static inline uint32_t EQDC_GetHoldPosition2(EQDC_Type *base) +{ + uint32_t u32Pos; + + u32Pos = base->UPOSH2; /* Get upper 16 bits from hold register. */ + u32Pos <<= 16U; + u32Pos |= base->LPOSH2; /* Get lower 16 bits from hold register. */ + + return u32Pos; +} + +/*! + * @brief Get the hold position counter3's value. + * + * The Upper Position Counter Hold Register 3(UPOSH3) shares the same address with UCOMP3. + * When read,this register means the value of UPOSH3, which is the upper 16 bits of POSH3. + * The Lower Position Counter Hold Register 3(LPOSH3) shares the same address with LCOMP3. + * When read, this register means the value of LPOSH3, which is the lower 16 bits of POSH3. + * Position counter is captured into POSH3 on the rising edge of ICAP[3]. + * + * @param base EQDC peripheral base address. + * @return Hold position counter3's value. + */ +static inline uint32_t EQDC_GetHoldPosition3(EQDC_Type *base) +{ + uint32_t u32Pos; + + u32Pos = base->UPOSH3; /* Get upper 16 bits from hold register. */ + u32Pos <<= 16U; + u32Pos |= base->LPOSH3; /* Get lower 16 bits from hold register. */ + + return u32Pos; +} + +/*! + * @brief Get the position difference counter's value. + * + * @param base EQDC peripheral base address. + * @return The position difference counter's value. + */ +static inline uint16_t EQDC_GetPositionDifference(EQDC_Type *base) +{ + return base->POSD; +} + +/*! + * @brief Get the hold position difference counter's value. + * + * The position difference (POSD) value is loaded to hold position difference (POSDH) + * when: + * 1. Position register (POS or UPOS, LPOS), or position difference register (POSD), + * or revolution register (REV) is read. When Period Measurement is enabled (CTRL3[PMEN] = 1), + * POSDH will only be udpated when reading POSD. + * 2. TRIGGER happens and TRIGGER is enabled to update the hold registers. + * + * @param base EQDC peripheral base address. + * @return Hold position difference counter's value. + */ +static inline uint16_t EQDC_GetHoldPositionDifference(EQDC_Type *base) +{ + return base->POSDH; +} + +/*! + * @brief Get the revolution counter's value. + * + * Get the revolution counter (REV) value. + * + * @param base EQDC peripheral base address. + * @return The revolution counter's value. + */ +static inline uint16_t EQDC_GetRevolution(EQDC_Type *base) +{ + return base->REV; +} + +/*! + * @brief Get the hold revolution counter's value. + * + * The revolution counter (REV) value is loaded to hold revolution (REVH) + * when: + * 1. Position register (POS or UPOS, LPOS), or position difference register (POSD), + * or revolution register (REV) is read. + * 2. TRIGGER happens and TRIGGER is enabled to update the hold registers. + * + * @param base EQDC peripheral base address. + * @return Hold position revolution counter's value. + */ +static inline uint16_t EQDC_GetHoldRevolution(EQDC_Type *base) +{ + return base->REVH; +} + +/*! + * @brief Get the last edge time. + * + * Last edge time (LASTEDGE) is the time since the last edge occurred on PHASEA or PHASEB. + * The last edge time register counts up using the peripheral clock after prescaler. + * Any edge on PHASEA or PHASEB will reset this register to 0 and start counting. + * If the last edge timer count reaches 0xffff, the counting will stop in order to + * prevent an overflow.Counting will continue when an edge occurs on + * PHASEA or PHASEB. + * + * @param base EQDC peripheral base address. + * + * @return The last edge time. + */ +static inline uint16_t EQDC_GetLastEdgeTime(EQDC_Type *base) +{ + return base->LASTEDGE; +} + +/*! + * @brief Get the hold last edge time. + * + * The hold of last edge time(LASTEDGEH) is update to last edge time(LASTEDGE) + * when the position difference register register (POSD) is read. + * + * @param base EQDC peripheral base address. + * @return Hold of last edge time. + */ +static inline uint16_t EQDC_GetHoldLastEdgeTime(EQDC_Type *base) +{ + return base->LASTEDGEH; +} + +/*! + * @brief Get the Position Difference Period counter value + * + * The Position Difference Period counter (POSDPER) counts up using the + * prescaled peripheral clock. When reading the position difference register(POSD), + * the last edge time (LASTEDGE) will be loaded to position difference period counter(POSDPER). + * If the POSDPER count reaches 0xffff, the counting will stop in order to prevent an + * overflow. Counting will continue when an edge occurs on PHASEA or PHASEB. + * + * @param base EQDC peripheral base address. + * @return The position difference period counter value. + */ +static inline uint16_t EQDC_GetPositionDifferencePeriod(EQDC_Type *base) +{ + return base->POSDPER; +} + +/*! + * @brief Get buffered Position Difference Period counter value + * + * The Bufferd Position Difference Period (POSDPERBFR) value is updated with + * the position difference period counter(POSDPER) when any edge occurs + * on PHASEA or PHASEB. + * + * @param base EQDC peripheral base address. + * @return The buffered position difference period counter value. + */ +static inline uint16_t EQDC_GetBufferedPositionDifferencePeriod(EQDC_Type *base) +{ + return base->POSDPERBFR; +} + +/*! + * @brief Get Hold Position Difference Period counter value + * + * The hold position difference period(POSDPERH) is updated with the value of + * buffered position difference period(POSDPERBFR) when the + * position difference(POSD) register is read. + * + * @param base EQDC peripheral base address. + * @return The hold position difference period counter value. + */ +static inline uint16_t EQDC_GetHoldPositionDifferencePeriod(EQDC_Type *base) +{ + return base->POSDPERH; +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* FSL_EQDC_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_erm.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_erm.c new file mode 100644 index 00000000000..cdd35b56b09 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_erm.c @@ -0,0 +1,317 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_erm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.erm" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to ERM bases for each instance. */ +static ERM_Type *const s_ermBases[] = ERM_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to ERM clocks for each instance. */ +static const clock_ip_name_t s_ermClocks[] = ERM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t ERM_GetInstance(ERM_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_ermBases); instance++) + { + if (s_ermBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_ermBases)); + + return instance; +} + +/*! + * brief ERM module initialization function. + * + * param base ERM base address. + */ +void ERM_Init(ERM_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate ERM clock. */ + CLOCK_EnableClock(s_ermClocks[ERM_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + base->CR0 = 0x00U; +#ifdef ERM_CR1_ENCIE8_MASK + base->CR1 = 0x00U; +#endif + base->SR0 = 0xFFFFFFFFU; +#ifdef ERM_SR1_SBC8_MASK + base->SR1 = 0xFFFFFFFFU; +#endif +} + +/*! + * brief Deinitializes the ERM. + * + */ +void ERM_Deinit(ERM_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate ERM clock. */ + CLOCK_DisableClock(s_ermClocks[ERM_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +uint32_t ERM_GetMemoryErrorAddr(ERM_Type *base, erm_memory_channel_t channel) +{ + uint32_t absoluteErrorAddress = 0x00U; + + switch ((uint8_t)channel) + { + case 0U: + absoluteErrorAddress = base->EAR0; + break; +#ifdef ERM_EAR1_EAR_MASK + case 1U: + absoluteErrorAddress = base->EAR1; + break; +#endif +#ifdef ERM_EAR2_EAR_MASK + case 2U: + absoluteErrorAddress = base->EAR2; + break; +#endif +#ifdef ERM_EAR3_EAR_MASK + case 3U: + absoluteErrorAddress = base->EAR3; + break; +#endif +#ifdef ERM_EAR4_EAR_MASK + case 4U: + absoluteErrorAddress = base->EAR4; + break; +#endif +#ifdef ERM_EAR5_EAR_MASK + case 5U: + absoluteErrorAddress = base->EAR5; + break; +#endif +#ifdef ERM_EAR6_EAR_MASK + case 6U: + absoluteErrorAddress = base->EAR6; + break; +#endif + default: + assert(NULL); + break; + } + + return absoluteErrorAddress; +} + +uint32_t ERM_GetSyndrome(ERM_Type *base, erm_memory_channel_t channel) +{ + uint32_t syndrome = 0x00U; + + switch ((uint8_t)channel) + { + case 0U: + syndrome = (base->SYN0 & ERM_SYN0_SYNDROME_MASK) >> ERM_SYN0_SYNDROME_SHIFT; + break; +#ifdef ERM_SYN1_SYNDROME_MASK + case 1U: + syndrome = (base->SYN1 & ERM_SYN1_SYNDROME_MASK) >> ERM_SYN1_SYNDROME_SHIFT; + break; +#endif +#ifdef ERM_SYN2_SYNDROME_MASK + case 2U: + syndrome = (base->SYN2 & ERM_SYN2_SYNDROME_MASK) >> ERM_SYN2_SYNDROME_SHIFT; + break; +#endif +#ifdef ERM_SYN3_SYNDROME_MASK + case 3U: + syndrome = (base->SYN3 & ERM_SYN3_SYNDROME_MASK) >> ERM_SYN3_SYNDROME_SHIFT; + break; +#endif +#ifdef ERM_SYN4_SYNDROME_MASK + case 4U: + syndrome = (base->SYN4 & ERM_SYN4_SYNDROME_MASK) >> ERM_SYN4_SYNDROME_SHIFT; + break; +#endif +#ifdef ERM_SYN5_SYNDROME_MASK + case 5U: + syndrome = (base->SYN5 & ERM_SYN5_SYNDROME_MASK) >> ERM_SYN5_SYNDROME_SHIFT; + break; +#endif +#ifdef ERM_SYN6_SYNDROME_MASK + case 6U: + syndrome = (base->SYN6 & ERM_SYN6_SYNDROME_MASK) >> ERM_SYN6_SYNDROME_SHIFT; + break; +#endif +#ifdef ERM_SYN7_SYNDROME_MASK + case 7U: + syndrome = (base->SYN7 & ERM_SYN6_SYNDROME_MASK) >> ERM_SYN7_SYNDROME_SHIFT; + break; +#endif +#ifdef ERM_SYN8_SYNDROME_MASK + case 8U: + syndrome = (base->SYN8 & ERM_SYN8_SYNDROME_MASK) >> ERM_SYN8_SYNDROME_SHIFT; + break; +#endif +#ifdef ERM_SYN9_SYNDROME_MASK + case 8U: + syndrome = (base->SYN9 & ERM_SYN9_SYNDROME_MASK) >> ERM_SYN9_SYNDROME_SHIFT; + break; +#endif + default: + assert(NULL); + break; + } + + return syndrome; +} + +uint32_t ERM_GetErrorCount(ERM_Type *base, erm_memory_channel_t channel) +{ + uint32_t count = 0x00U; + + switch ((uint8_t)channel) + { + case 0U: + count = (base->CORR_ERR_CNT0 & ERM_CORR_ERR_CNT0_COUNT_MASK) >> ERM_CORR_ERR_CNT0_COUNT_SHIFT; + break; +#ifdef ERM_CORR_ERR_CNT1_COUNT_MASK + case 1U: + count = (base->CORR_ERR_CNT1 & ERM_CORR_ERR_CNT1_COUNT_MASK) >> ERM_CORR_ERR_CNT1_COUNT_SHIFT; + break; +#endif +#ifdef ERM_CORR_ERR_CNT2_COUNT_MASK + case 2U: + count = (base->CORR_ERR_CNT2 & ERM_CORR_ERR_CNT2_COUNT_MASK) >> ERM_CORR_ERR_CNT2_COUNT_SHIFT; + break; +#endif +#ifdef ERM_CORR_ERR_CNT3_COUNT_MASK + case 3U: + count = (base->CORR_ERR_CNT3 & ERM_CORR_ERR_CNT3_COUNT_MASK) >> ERM_CORR_ERR_CNT3_COUNT_SHIFT; + break; +#endif +#ifdef ERM_CORR_ERR_CNT4_COUNT_MASK + case 4U: + count = (base->CORR_ERR_CNT4 & ERM_CORR_ERR_CNT4_COUNT_MASK) >> ERM_CORR_ERR_CNT4_COUNT_SHIFT; + break; +#endif +#ifdef ERM_CORR_ERR_CNT5_COUNT_MASK + case 5U: + count = (base->CORR_ERR_CNT5 & ERM_CORR_ERR_CNT5_COUNT_MASK) >> ERM_CORR_ERR_CNT5_COUNT_SHIFT; + break; +#endif +#ifdef ERM_CORR_ERR_CNT6_COUNT_MASK + case 6U: + count = (base->CORR_ERR_CNT6 & ERM_CORR_ERR_CNT6_COUNT_MASK) >> ERM_CORR_ERR_CNT6_COUNT_SHIFT; + break; +#endif +#ifdef ERM_CORR_ERR_CNT7_COUNT_MASK + case 7U: + count = (base->CORR_ERR_CNT7 & ERM_CORR_ERR_CNT7_COUNT_MASK) >> ERM_CORR_ERR_CNT7_COUNT_SHIFT; + break; +#endif +#ifdef ERM_CORR_ERR_CNT8_COUNT_MASK + case 8U: + count = (base->CORR_ERR_CNT8 & ERM_CORR_ERR_CNT8_COUNT_MASK) >> ERM_CORR_ERR_CNT8_COUNT_SHIFT; + break; +#endif +#ifdef ERM_CORR_ERR_CNT9_COUNT_MASK + case 9U: + count = (base->CORR_ERR_CNT9 & ERM_CORR_ERR_CNT9_COUNT_MASK) >> ERM_CORR_ERR_CNT9_COUNT_SHIFT; + break; +#endif + default: + assert(NULL); + break; + } + + return count; +} + +void ERM_ResetErrorCount(ERM_Type *base, erm_memory_channel_t channel) +{ + switch ((uint8_t)channel) + { + case 0U: + base->CORR_ERR_CNT0 = 0x00U; + break; + +#ifdef ERM_CORR_ERR_CNT1_COUNT_MASK + case 1U: + base->CORR_ERR_CNT1 = 0x00U; + break; +#endif +#ifdef ERM_CORR_ERR_CNT2_COUNT_MASK + case 2U: + base->CORR_ERR_CNT2 = 0x00U; + break; +#endif +#ifdef ERM_CORR_ERR_CNT3_COUNT_MASK + case 3U: + base->CORR_ERR_CNT3 = 0x00U; + break; +#endif +#ifdef ERM_CORR_ERR_CNT4_COUNT_MASK + case 4U: + base->CORR_ERR_CNT4 = 0x00U; + break; +#endif +#ifdef ERM_CORR_ERR_CNT5_COUNT_MASK + case 5U: + base->CORR_ERR_CNT5 = 0x00U; + break; +#endif +#ifdef ERM_CORR_ERR_CNT6_COUNT_MASK + case 6U: + base->CORR_ERR_CNT6 = 0x00U; + break; +#endif +#ifdef ERM_CORR_ERR_CNT6_COUNT_MASK + case 7U: + base->CORR_ERR_CNT7 = 0x00U; + break; +#endif +#ifdef ERM_CORR_ERR_CNT8_COUNT_MASK + case 8U: + base->CORR_ERR_CNT8 = 0x00U; + break; +#endif +#ifdef ERM_CORR_ERR_CNT9_COUNT_MASK + case 9U: + base->CORR_ERR_CNT9 = 0x00U; + break; +#endif + default: + assert(NULL); + break; + } +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_erm.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_erm.h new file mode 100644 index 00000000000..45303523e76 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_erm.h @@ -0,0 +1,235 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_ERM_H_ +#define FSL_ERM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup erm + * @{ + */ + +/****************************************************************************** + * Definitions. + *****************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief Driver version. */ +#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U)) +/*! @} */ + +/*! + * @brief ERM interrupt configuration structure, default settings all disabled, _erm_interrupt_enable. + * + * This structure contains the settings for all of the ERM interrupt configurations. + */ +enum +{ + kERM_SingleCorrectionIntEnable = 0x08U, /*!< Single Correction Interrupt Notification enable.*/ + kERM_NonCorrectableIntEnable = 0x04U, /*!< Non-Correction Interrupt Notification enable.*/ + + kERM_AllInterruptsEnable = 0xFFFFFFFFUL, /*!< All Interrupts enable */ +}; + +/*! + * @brief ERM interrupt status, _erm_interrupt_flag. + * + * This provides constants for the ERM event status for use in the ERM functions. + */ +enum +{ + kERM_SingleBitCorrectionIntFlag = 0x08U, /*!< Single-Bit Correction Event.*/ + kERM_NonCorrectableErrorIntFlag = 0x04U, /*!< Non-Correctable Error Event.*/ + + kERM_AllIntsFlag = 0xFFFFFFFFUL, /*!< All Events. */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and de-initialization + * @{ + */ + +/*! + * @brief ERM module initialization function. + * + * @param base ERM base address. + */ +void ERM_Init(ERM_Type *base); + +/*! + * @brief De-initializes the ERM. + * + */ +void ERM_Deinit(ERM_Type *base); + +/*! @} */ + +/*! + * @name Interrupt + * @{ + */ +/*! + * @brief ERM enable interrupts. + * + * @param base ERM peripheral base address. + * @param channel memory channel. + * @param mask single correction interrupt or non-correction interrupt enable to disable for one specific memory region. + * Refer to "_erm_interrupt_enable" enumeration. + */ +static inline void ERM_EnableInterrupts(ERM_Type *base, erm_memory_channel_t channel, uint32_t mask) +{ + uint32_t temp = 0x00U; + if ((uint32_t)channel <= 0x07U) + { + temp = base->CR0; + base->CR0 = + (temp & ~(0x0CUL << ((0x07U - (uint32_t)channel) * 4U))) | (mask << ((0x07U - (uint32_t)channel) * 4U)); + } +#ifdef ERM_CR1_ESCIE8_MASK + else + { + temp = base->CR1; + base->CR1 = (temp & ~(0x0CUL << ((0x07U + 0x08U - (uint32_t)channel) * 4U))) | + (mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U)); + } +#endif +} + +/*! + * @brief ERM module disable interrupts. + * + * @param base ERM base address. + * @param channel memory channel. + * @param mask single correction interrupt or non-correction interrupt enable to disable for one specific memory region. + * Refer to "_erm_interrupt_enable" enumeration. + */ +static inline void ERM_DisableInterrupts(ERM_Type *base, erm_memory_channel_t channel, uint32_t mask) +{ + if ((uint32_t)channel <= 0x07U) + { + base->CR0 &= ~(mask << ((0x07U - (uint32_t)channel) * 4U)); + } +#ifdef ERM_CR1_ESCIE8_MASK + else + { + base->CR1 &= ~(mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U)); + } +#endif +} + +/*! + * @brief Gets ERM interrupt flags. + * + * @param base ERM peripheral base address. + * @return ERM event flags. + */ +static inline uint32_t ERM_GetInterruptStatus(ERM_Type *base, erm_memory_channel_t channel) +{ + if ((uint32_t)channel <= 0x07U) + { + return ((base->SR0 & (uint32_t)kERM_AllIntsFlag) >> (0x07U - (uint32_t)channel) * 4U); + } +#ifdef ERM_SR1_SBC8_MASK + else + { + return ((base->SR1 & (uint32_t)kERM_AllIntsFlag) >> ((0x07U + 0x08U - (uint32_t)channel) * 4U)); + } +#else + { + return 0; + } +#endif +} + +/*! + * @brief ERM module clear interrupt status flag. + * + * @param base ERM base address. + * @param mask event flag to clear. Refer to "_erm_interrupt_flag" enumeration. + */ +static inline void ERM_ClearInterruptStatus(ERM_Type *base, erm_memory_channel_t channel, uint32_t mask) +{ + if ((uint32_t)channel <= 0x07U) + { + base->SR0 = mask << ((0x07U - (uint32_t)channel) * 4U); + } +#ifdef ERM_SR1_SBC8_MASK + else + { + base->SR1 = mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U); + } +#endif +} + +/*! @} */ + +/*! + * @name functional + * @{ + */ + +/*! + * @brief ERM get memory error absolute address, which capturing the address of the last ECC event in Memory n. + * + * @param base ERM base address. + * @param channel memory channel. + * @retval memory error absolute address. + */ + +uint32_t ERM_GetMemoryErrorAddr(ERM_Type *base, erm_memory_channel_t channel); + +/*! + * @brief ERM get syndrome, which identifies the pertinent bit position on a correctable, single-bit data inversion or a + * non-correctable, single-bit address inversion. The syndrome value does not provide any additional diagnostic + * information on non-correctable, multi-bit inversions. + * + * @param base ERM base address. + * @param channel memory channel. + * @retval syndrome value. + */ +uint32_t ERM_GetSyndrome(ERM_Type *base, erm_memory_channel_t channel); + +/*! + * @brief ERM get error count, which records the count value of the number of correctable ECC error events for Memory + * n. Non-correctable errors are considered a serious fault, so the ERM does not provide any mechanism to count + * non-correctable errors. Only correctable errors are counted. + * + * @param base ERM base address. + * @param channel memory channel. + * @retval error count. + */ +uint32_t ERM_GetErrorCount(ERM_Type *base, erm_memory_channel_t channel); + +/*! + * @brief ERM reset error count. + * + * @param base ERM base address. + * @param channel memory channel. + */ +void ERM_ResetErrorCount(ERM_Type *base, erm_memory_channel_t channel); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexcan.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexcan.c new file mode 100644 index 00000000000..8717791e182 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexcan.c @@ -0,0 +1,4927 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexcan.h" + +/* + * $Coverage Justification Reference$ + * + * $Justification flexcan_c_ref_1$ + * The FLEXCAN_ReadRxFifo() return fail only when Rx FIFO is diabled. But in IRQ handler, will first check whether the + * FIFO is enabled, and only call FLEXCAN_ReadRxFifo if the FIFO is enabled. So to cover this line/branch, need to + * interrupt the current execution by a high priority IRQ after confirming that the FIFO is enabled, and disabled the + * FIFO in the high priority interrupt. It is difficult to simulate this situation in unit test, so add Justification. + * + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcan" +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) +#define RXINTERMISSION (CAN_DBG1_CFSM(0x2f)) +#define TXINTERMISSION (CAN_DBG1_CFSM(0x14)) +#define BUSIDLE (CAN_DBG1_CFSM(0x02)) +#define CBN_VALUE3 (CAN_DBG1_CBN(0x03)) +#define DELAY_BUSIDLE (200) +#endif + +/* According to CiA doc 1301 v1.0.0, specified data/nominal phase sample point postion for CAN FD at 80 MHz. */ +#define IDEAL_DATA_SP_1 (800U) +#define IDEAL_DATA_SP_2 (750U) +#define IDEAL_DATA_SP_3 (700U) +#define IDEAL_DATA_SP_4 (625U) +#define IDEAL_NOMINAL_SP (800U) + +/* According to CiA doc 301 v4.2.0 and previous version. */ +#define IDEAL_SP_LOW (750U) +#define IDEAL_SP_MID (800U) +#define IDEAL_SP_HIGH (875U) + +#define IDEAL_SP_FACTOR (1000U) + +/* Define the max value of bit timing segments when use different timing register. */ +#define MAX_PROPSEG (CAN_CTRL1_PROPSEG_MASK >> CAN_CTRL1_PROPSEG_SHIFT) +#define MAX_PSEG1 (CAN_CTRL1_PSEG1_MASK >> CAN_CTRL1_PSEG1_SHIFT) +#define MAX_PSEG2 (CAN_CTRL1_PSEG2_MASK >> CAN_CTRL1_PSEG2_SHIFT) +#define MAX_RJW (CAN_CTRL1_RJW_MASK >> CAN_CTRL1_RJW_SHIFT) +#define MAX_PRESDIV (CAN_CTRL1_PRESDIV_MASK >> CAN_CTRL1_PRESDIV_SHIFT) +#define CTRL1_MAX_TIME_QUANTA (1U + MAX_PROPSEG + 1U + MAX_PSEG1 + 1U + MAX_PSEG2 + 1U) +#define CTRL1_MIN_TIME_QUANTA (8U) + +#define MAX_EPROPSEG (CAN_CBT_EPROPSEG_MASK >> CAN_CBT_EPROPSEG_SHIFT) +#define MAX_EPSEG1 (CAN_CBT_EPSEG1_MASK >> CAN_CBT_EPSEG1_SHIFT) +#define MAX_EPSEG2 (CAN_CBT_EPSEG2_MASK >> CAN_CBT_EPSEG2_SHIFT) +#define MAX_ERJW (CAN_CBT_ERJW_MASK >> CAN_CBT_ERJW_SHIFT) +#define MAX_EPRESDIV (CAN_CBT_EPRESDIV_MASK >> CAN_CBT_EPRESDIV_SHIFT) +#define CBT_MAX_TIME_QUANTA (1U + MAX_EPROPSEG + 1U + MAX_EPSEG1 + 1U + MAX_EPSEG2 + 1U) +#define CBT_MIN_TIME_QUANTA (8U) + +#define MAX_FPROPSEG (CAN_FDCBT_FPROPSEG_MASK >> CAN_FDCBT_FPROPSEG_SHIFT) +#define MAX_FPSEG1 (CAN_FDCBT_FPSEG1_MASK >> CAN_FDCBT_FPSEG1_SHIFT) +#define MAX_FPSEG2 (CAN_FDCBT_FPSEG2_MASK >> CAN_FDCBT_FPSEG2_SHIFT) +#define MAX_FRJW (CAN_FDCBT_FRJW_MASK >> CAN_FDCBT_FRJW_SHIFT) +#define MAX_FPRESDIV (CAN_FDCBT_FPRESDIV_MASK >> CAN_FDCBT_FPRESDIV_SHIFT) +#define FDCBT_MAX_TIME_QUANTA (1U + MAX_FPROPSEG + 0U + MAX_FPSEG1 + 1U + MAX_FPSEG2 + 1U) +#define FDCBT_MIN_TIME_QUANTA (5U) + +#define MAX_TDCOFF ((uint32_t)CAN_FDCTRL_TDCOFF_MASK >> CAN_FDCTRL_TDCOFF_SHIFT) + +#define MAX_NTSEG1 (CAN_ENCBT_NTSEG1_MASK >> CAN_ENCBT_NTSEG1_SHIFT) +#define MAX_NTSEG2 (CAN_ENCBT_NTSEG2_MASK >> CAN_ENCBT_NTSEG2_SHIFT) +#define MAX_NRJW (CAN_ENCBT_NRJW_MASK >> CAN_ENCBT_NRJW_SHIFT) +#define MAX_ENPRESDIV (CAN_EPRS_ENPRESDIV_MASK >> CAN_EPRS_ENPRESDIV_SHIFT) +#define ENCBT_MAX_TIME_QUANTA (1U + MAX_NTSEG1 + 1U + MAX_NTSEG2 + 1U) +#define ENCBT_MIN_TIME_QUANTA (8U) + +#define MAX_DTSEG1 (CAN_EDCBT_DTSEG1_MASK >> CAN_EDCBT_DTSEG1_SHIFT) +#define MAX_DTSEG2 (CAN_EDCBT_DTSEG2_MASK >> CAN_EDCBT_DTSEG2_SHIFT) +#define MAX_DRJW (CAN_EDCBT_DRJW_MASK >> CAN_EDCBT_DRJW_SHIFT) +#define MAX_EDPRESDIV (CAN_EPRS_EDPRESDIV_MASK >> CAN_EPRS_EDPRESDIV_SHIFT) +#define EDCBT_MAX_TIME_QUANTA (1U + MAX_DTSEG1 + 1U + MAX_DTSEG2 + 1U) +#define EDCBT_MIN_TIME_QUANTA (5U) + +#define MAX_ETDCOFF ((uint32_t)CAN_ETDC_ETDCOFF_MASK >> CAN_ETDC_ETDCOFF_SHIFT) + +/* TSEG1 corresponds to the sum of xPROPSEG and xPSEG1, TSEG2 corresponds to the xPSEG2 value. */ +#define MIN_TIME_SEGMENT1 (2U) +#define MIN_TIME_SEGMENT2 (2U) + +/* Define maximum CAN and CAN FD bit rate supported by FLEXCAN. */ +#if (defined(FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE)) +#define MAX_CANFD_BITRATE ((uint32_t)(FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE)) +#else +#define MAX_CANFD_BITRATE (8000000U) +#endif +#define MAX_CAN_BITRATE (1000000U) + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) +#define CAN_ESR1_FLTCONF_BUSOFF CAN_ESR1_FLTCONF(2U) +#endif + +/* Define the range of memory that needs to be initialized when the device has memory error detection feature. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +#define CAN_INIT_RXFIR ((uintptr_t)base + 0x4Cu) +#define CAN_INIT_MEMORY_BASE_1 (uint32_t *)((uintptr_t)base + (uintptr_t)FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_1) +#define CAN_INIT_MEMORY_SIZE_1 FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_1 +#define CAN_INIT_MEMORY_BASE_2 (uint32_t *)((uintptr_t)base + (uintptr_t)FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_2) +#define CAN_INIT_MEMORY_SIZE_2 FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_2 +#endif + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#ifndef CAN_CLOCK_CHECK_NO_AFFECTS +/* If no define such MACRO, it mean that the CAN in current device have no clock affect issue. */ +#define CAN_CLOCK_CHECK_NO_AFFECTS (true) +#endif /* CAN_CLOCK_CHECK_NO_AFFECTS */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FLEXCAN_RSTS) +#define FLEXCAN_RESETS_ARRAY FLEXCAN_RSTS +#elif defined(FLEXCAN_RSTS_N) +#define FLEXCAN_RESETS_ARRAY FLEXCAN_RSTS_N +#endif + +/*! @brief FlexCAN Internal State. */ +enum _flexcan_state +{ + kFLEXCAN_StateIdle = 0x0, /*!< MB/RxFIFO idle.*/ + kFLEXCAN_StateRxData = 0x1, /*!< MB receiving.*/ + kFLEXCAN_StateRxRemote = 0x2, /*!< MB receiving remote reply.*/ + kFLEXCAN_StateTxData = 0x3, /*!< MB transmitting.*/ + kFLEXCAN_StateTxRemote = 0x4, /*!< MB transmitting remote request.*/ + kFLEXCAN_StateRxFifo = 0x5, /*!< RxFIFO receiving.*/ +}; + +/*! @brief FlexCAN message buffer CODE for Rx buffers. */ +enum _flexcan_mb_code_rx +{ + kFLEXCAN_RxMbInactive = 0x0, /*!< MB is not active.*/ + kFLEXCAN_RxMbFull = 0x2, /*!< MB is full.*/ + kFLEXCAN_RxMbEmpty = 0x4, /*!< MB is active and empty.*/ + kFLEXCAN_RxMbOverrun = 0x6, /*!< MB is overwritten into a full buffer.*/ + kFLEXCAN_RxMbBusy = 0x8, /*!< FlexCAN is updating the contents of the MB, The CPU must not access the MB.*/ + kFLEXCAN_RxMbRanswer = 0xA, /*!< A frame was configured to recognize a Remote Request Frame and transmit a + Response Frame in return.*/ + kFLEXCAN_RxMbNotUsed = 0xF, /*!< Not used.*/ +}; + +/*! @brief FlexCAN message buffer CODE FOR Tx buffers. */ +enum _flexcan_mb_code_tx +{ + kFLEXCAN_TxMbInactive = 0x8, /*!< MB is not active.*/ + kFLEXCAN_TxMbAbort = 0x9, /*!< MB is aborted.*/ + kFLEXCAN_TxMbDataOrRemote = 0xC, /*!< MB is a TX Data Frame(when MB RTR = 0) or MB is a TX Remote Request + Frame (when MB RTR = 1).*/ + kFLEXCAN_TxMbTanswer = 0xE, /*!< MB is a TX Response Request Frame from an incoming Remote Request Frame.*/ + kFLEXCAN_TxMbNotUsed = 0xF, /*!< Not used.*/ +}; + +/* Typedef for interrupt handler. */ +typedef void (*flexcan_isr_t)(CAN_Type *base, flexcan_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if !defined(NDEBUG) +/*! + * @brief Check if Message Buffer is occupied by Rx FIFO. + * + * This function check if Message Buffer is occupied by Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + * @return TRUE if the index MB is occupied by Rx FIFO, FALSE if the index MB not occupied by Rx FIFO. + */ +static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx); +#endif + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) +/*! + * @brief Get the first valid Message buffer ID of give FlexCAN instance. + * + * This function is a helper function for Errata 5641 workaround. + * + * @param base FlexCAN peripheral base address. + * @return The first valid Message Buffer Number. + */ +static uint8_t FLEXCAN_GetFirstValidMb(CAN_Type *base); +#endif + +/*! + * @brief Reset the FlexCAN Instance. + * + * Restores the FlexCAN module to reset state, notice that this function + * will set all the registers to reset state so the FlexCAN module can not work + * after calling this API. + * + * @param base FlexCAN peripheral base address. + */ +static void FLEXCAN_Reset(CAN_Type *base); + +/*! + * @brief Calculates the segment values for a single bit time for classical CAN. + * + * This function use to calculates the Classical CAN segment values which will be set in CTRL1/CBT/ENCBT register. + * + * @param base FlexCAN peripheral base address. + * @param tqNum Number of time quantas per bit, range in 8 ~ 25 when use CTRL1, range in 8 ~ 129 when use CBT, range in + * 8 ~ 385 when use ENCBT. param pTimingConfig Pointer to the FlexCAN timing configuration structure. + */ +static void FLEXCAN_GetSegments(CAN_Type *base, + uint32_t bitRate, + uint32_t tqNum, + flexcan_timing_config_t *pTimingConfig); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Get Mailbox offset number by dword. + * + * This function gets the offset number of the specified mailbox. + * Mailbox is not consecutive between memory regions when payload is not 8 bytes + * so need to calculate the specified mailbox address. + * For example, in the first memory region, MB[0].CS address is 0x4002_4080. For 32 bytes + * payload frame, the second mailbox is ((1/12)*512 + 1%12*40)/4 = 10, meaning 10 dword + * after the 0x4002_4080, which is actually the address of mailbox MB[1].CS. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx Mailbox index. + */ +static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx); + +/*! + * @brief Calculates the segment values for a single bit time for CAN FD data phase. + * + * This function use to calculates the CAN FD data phase segment values which will be set in CFDCBT/EDCBT + * register. + * + * @param bitRateFD Data phase bit rate + * @param tqNum Number of time quanta per bit + * @param pTimingConfig Pointer to the FlexCAN timing configuration structure. + */ +static void FLEXCAN_FDGetSegments(uint32_t bitRateFD, uint32_t tqNum, flexcan_timing_config_t *pTimingConfig); + +/*! + * @brief Calculates the improved timing values by specific bit rate for CAN FD nominal phase. + * + * This function use to calculates the CAN FD nominal phase timing values according to the given nominal phase bit rate. + * The Calculated timing values will be set in CBT/ENCBT registers. The calculation is based on the recommendation of + * the CiA 1301 v1.0.0 document. + * + * @param bitRate The CAN FD nominal phase speed in bps defined by user, should be less than or equal to 1Mbps. + * @param sourceClock_Hz The Source clock frequency in Hz. + * @param pTimingConfig Pointer to the FlexCAN timing configuration structure. + * + * @return TRUE if timing configuration found, FALSE if failed to find configuration. + */ +static bool FLEXCAN_CalculateImprovedNominalTimingValues(uint32_t bitRate, + uint32_t sourceClock_Hz, + flexcan_timing_config_t *pTimingConfig); + +#endif + +/*! + * @brief Check unhandle interrupt events + * + * @param base FlexCAN peripheral base address. + * @return TRUE if unhandled interrupt action exist, FALSE if no unhandlered interrupt action exist. + */ +static bool FLEXCAN_CheckUnhandleInterruptEvents(CAN_Type *base); + +/*! + * @brief Sub Handler Data Trasfered Events + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param pResult Pointer to the Handle result. + * + * @return the status after handle each data transfered event. + */ +static status_t FLEXCAN_SubHandlerForDataTransfered(CAN_Type *base, flexcan_handle_t *handle, uint32_t *pResult); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Sub Handler Ehanced Rx FIFO event + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param flags FlexCAN interrupt flags. + * + * @return the status after handle Ehanced Rx FIFO event. + */ +static status_t FLEXCAN_SubHandlerForEhancedRxFifo(CAN_Type *base, flexcan_handle_t *handle, uint64_t flags); +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Array of FlexCAN peripheral base address. */ +static CAN_Type *const s_flexcanBases[] = CAN_BASE_PTRS; + +/* Array of FlexCAN IRQ number. */ +static const IRQn_Type s_flexcanRxWarningIRQ[] = CAN_Rx_Warning_IRQS; +static const IRQn_Type s_flexcanTxWarningIRQ[] = CAN_Tx_Warning_IRQS; +static const IRQn_Type s_flexcanWakeUpIRQ[] = CAN_Wake_Up_IRQS; +static const IRQn_Type s_flexcanErrorIRQ[] = CAN_Error_IRQS; +static const IRQn_Type s_flexcanBusOffIRQ[] = CAN_Bus_Off_IRQS; +static const IRQn_Type s_flexcanMbIRQ[] = CAN_ORed_Message_buffer_IRQS; + +/* Array of FlexCAN handle. */ +static flexcan_handle_t *s_flexcanHandle[ARRAY_SIZE(s_flexcanBases)]; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of FlexCAN clock name. */ +static const clock_ip_name_t s_flexcanClock[] = FLEXCAN_CLOCKS; +#if defined(FLEXCAN_PERIPH_CLOCKS) +/* Array of FlexCAN serial clock name. */ +static const clock_ip_name_t s_flexcanPeriphClock[] = FLEXCAN_PERIPH_CLOCKS; +#endif /* FLEXCAN_PERIPH_CLOCKS */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FLEXCAN_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_flexcanResets[] = FLEXCAN_RESETS_ARRAY; +#endif + +/* FlexCAN ISR for transactional APIs. */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +static flexcan_isr_t s_flexcanIsr = (flexcan_isr_t)DefaultISR; +#else +static flexcan_isr_t s_flexcanIsr; +#endif + +/******************************************************************************* + * Implementation of 32-bit memset + ******************************************************************************/ + +static void flexcan_memset(void *s, uint32_t c, size_t n) +{ + size_t m; + volatile uint32_t *ptr = s; + + m = n / sizeof(*ptr); + + while ((m--) != (size_t)0) + { + *ptr++ = c; + } +} + +/******************************************************************************* + * Code + ******************************************************************************/ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Determine whether the FlexCAN instance support CAN FD mode at run time. + * + * note Use this API only if different soc parts share the SOC part name macro define. Otherwise, a different SOC part + * name can be used to determine at compile time whether the FlexCAN instance supports CAN FD mode or not. + * If need use this API to determine if CAN FD mode is supported, the FLEXCAN_Init function needs to be + * executed first, and then call this API and use the return to value determines whether to supports CAN FD mode, + * if return true, continue calling FLEXCAN_FDInit to enable CAN FD mode. + * + * param base FlexCAN peripheral base address. + * return return TRUE if instance support CAN FD mode, FALSE if instance only support classic CAN (2.0) mode. + */ +bool FLEXCAN_IsInstanceHasFDMode(CAN_Type *base) +{ + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + /* Enable CAN FD operation. */ + base->MCR |= CAN_MCR_FDEN_MASK; + + /* There are some SoC parts that don't support CAN FD. + * Checking if FDEN bit is really set to 1 is a way to ensure that CAN FD is supported. + * When SoC parts don't support CAN FD, FDEN bit stuck at 0 and can't be set to 1. */ + if (0U == (base->MCR & CAN_MCR_FDEN_MASK)) + { + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); + return false; + } + else + { + /* Clear CAN FD operation. */ + base->MCR &= ~CAN_MCR_FDEN_MASK; + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); + return true; + } +} +#endif + +/*! + * brief Get the FlexCAN instance from peripheral base address. + * + * param base FlexCAN peripheral base address. + * return FlexCAN instance. + */ +uint32_t FLEXCAN_GetInstance(CAN_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_flexcanBases); instance++) + { + if (s_flexcanBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_flexcanBases)); + + return instance; +} + +/*! + * brief Enter FlexCAN Freeze Mode. + * + * This function makes the FlexCAN work under Freeze Mode. + * + * param base FlexCAN peripheral base address. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) +void FLEXCAN_EnterFreezeMode(CAN_Type *base) +{ + uint32_t u32TimeoutCount = 0U; + uint32_t u32TempMCR = 0U; + uint32_t u32TempIMASK1 = 0U; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint32_t u32TempIMASK2 = 0U; +#endif + + /* Step1: set FRZ enable in MCR. */ + base->MCR |= CAN_MCR_FRZ_MASK; + + /* Step2: to check if MDIS bit set in MCR. if yes, clear it. */ + if (0U != (base->MCR & CAN_MCR_MDIS_MASK)) + { + base->MCR &= ~CAN_MCR_MDIS_MASK; + } + + /* Step3: polling LPMACK. */ + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT; + while ((0U == (base->MCR & CAN_MCR_LPMACK_MASK)) && (u32TimeoutCount > 0U)) + { + u32TimeoutCount--; + } + + /* Step4: to check FLTCONF in ESR1 register */ + if (0U == (base->ESR1 & CAN_ESR1_FLTCONF_BUSOFF)) + { + /* Error Active and Error Passive state */ + /* Step5B: Set Halt bits. */ + base->MCR |= CAN_MCR_HALT_MASK; + + /* Step6B: Poll the MCR register until the Freeze Acknowledge (FRZACK) bit is set, timeout need more than 178 + * CAN bit length, so 20 multiply timeout is enough. */ + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT * 20U; + while ((0U == (base->MCR & CAN_MCR_FRZACK_MASK)) && (u32TimeoutCount > 0U)) + { + u32TimeoutCount--; + } + + /* Merge ERRATA_9595 and ERRATA_8341 because both errata exist on some platform. */ + if (0U == u32TimeoutCount) + { + /* backup MCR and IMASK register. */ + u32TempMCR = base->MCR; + u32TempIMASK1 = base->IMASK1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + u32TempIMASK2 = base->IMASK2; +#endif + /* Set the Soft Reset bit ((SOFTRST) in the MCR.*/ + base->MCR |= CAN_MCR_SOFTRST_MASK; + + /* Poll the MCR register until the Soft Reset (SOFTRST) bit is cleared, timeout need more than 178 + * CAN bit length, so 20 multiply timeout is enough. */ + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT * 20U; + while ((CAN_MCR_SOFTRST_MASK == (base->MCR & CAN_MCR_SOFTRST_MASK)) && (u32TimeoutCount > 0U)) + { + u32TimeoutCount--; + } + + /* Reconfig MCR. */ + base->MCR = u32TempMCR; + + /* Reconfig IMASK. */ + base->IMASK1 = u32TempIMASK1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK2 = u32TempIMASK2; +#endif + } + } + else + { + /* Bus Off state */ + /* backup MCR and IMASK register. Errata document not descript it, but we need backup for step 8A and 9A. */ + u32TempMCR = base->MCR; + u32TempIMASK1 = base->IMASK1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + u32TempIMASK2 = base->IMASK2; +#endif + + /* Step5A: Set the Soft Reset bit ((SOFTRST) in the MCR.*/ + base->MCR |= CAN_MCR_SOFTRST_MASK; + + /* Step6A: Poll the MCR register until the Soft Reset (SOFTRST) bit is cleared. */ + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT; + while ((CAN_MCR_SOFTRST_MASK == (base->MCR & CAN_MCR_SOFTRST_MASK)) && (u32TimeoutCount > 0U)) + { + u32TimeoutCount--; + } + + /* Step7A: Poll the MCR register until the Freeze Acknowledge (FRZACK) bit is set. */ + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT; + while ((0U == (base->MCR & CAN_MCR_FRZACK_MASK)) && (u32TimeoutCount > 0U)) + { + u32TimeoutCount--; + } + + /* Step8A: reconfig MCR. */ + base->MCR = u32TempMCR; + + /* Step9A: reconfig IMASK. */ + base->IMASK1 = u32TempIMASK1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK2 = u32TempIMASK2; +#endif + } +} +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341) +void FLEXCAN_EnterFreezeMode(CAN_Type *base) +{ + uint32_t u32TimeoutCount = 0U; + uint32_t u32TempMCR = 0U; + uint32_t u32TempIMASK1 = 0U; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint32_t u32TempIMASK2 = 0U; +#endif + + /* Step1: set FRZ and HALT bit enable in MCR. */ + base->MCR |= CAN_MCR_FRZ_MASK; + base->MCR |= CAN_MCR_HALT_MASK; + + /* Step2: to check if MDIS bit set in MCR. if yes, clear it. */ + if (0U != (base->MCR & CAN_MCR_MDIS_MASK)) + { + base->MCR &= ~CAN_MCR_MDIS_MASK; + } + + /* Step3: Poll the MCR register until the Freeze Acknowledge (FRZACK) bit is set. */ + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT * 100U; + while ((0U == (base->MCR & CAN_MCR_FRZACK_MASK)) && (u32TimeoutCount > 0U)) + { + u32TimeoutCount--; + } + + /* Step4: check whether the timeout reached. if no skip step5 to step8. */ + if (0U == u32TimeoutCount) + { + /* backup MCR and IMASK register. Errata document not descript it, but we need backup for step 8A and 9A. */ + u32TempMCR = base->MCR; + u32TempIMASK1 = base->IMASK1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + u32TempIMASK2 = base->IMASK2; +#endif + /* Step5: Set the Soft Reset bit ((SOFTRST) in the MCR.*/ + base->MCR |= CAN_MCR_SOFTRST_MASK; + + /* Step6: Poll the MCR register until the Soft Reset (SOFTRST) bit is cleared. */ + while (CAN_MCR_SOFTRST_MASK == (base->MCR & CAN_MCR_SOFTRST_MASK)) + { + } + + /* Step7: reconfig MCR. */ + base->MCR = u32TempMCR; + + /* Step8: reconfig IMASK. */ + base->IMASK1 = u32TempIMASK1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK2 = u32TempIMASK2; +#endif + } +} +#else +void FLEXCAN_EnterFreezeMode(CAN_Type *base) +{ + /* Set Freeze, Halt bits. */ + base->MCR |= CAN_MCR_FRZ_MASK; + base->MCR |= CAN_MCR_HALT_MASK; + while (0U == (base->MCR & CAN_MCR_FRZACK_MASK)) + { + } +} +#endif + +/*! + * brief Exit FlexCAN Freeze Mode. + * + * This function makes the FlexCAN leave Freeze Mode. + * + * param base FlexCAN peripheral base address. + */ +void FLEXCAN_ExitFreezeMode(CAN_Type *base) +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /* Clean FlexCAN Access With Non-Correctable Error Interrupt Flag to avoid be put in freeze mode. */ + FLEXCAN_ClearStatusFlags(base, (uint64_t)kFLEXCAN_FlexCanAccessNonCorrectableErrorIntFlag | + (uint64_t)kFLEXCAN_FlexCanAccessNonCorrectableErrorOverrunFlag); +#endif + + /* Clear Freeze, Halt bits. */ + base->MCR &= ~CAN_MCR_HALT_MASK; + base->MCR &= ~CAN_MCR_FRZ_MASK; + + /* Wait until the FlexCAN Module exit freeze mode. */ + while (0U != (base->MCR & CAN_MCR_FRZACK_MASK)) + { + } +} + +#if !defined(NDEBUG) +/*! + * brief Check if Message Buffer is occupied by Rx FIFO. + * + * This function check if Message Buffer is occupied by Rx FIFO. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN Message Buffer index. + * return TRUE if the index MB is occupied by Rx FIFO, FALSE if the index MB not occupied by Rx FIFO. + */ +static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) +{ + uint8_t lastOccupiedMb; + bool fgRet; + + /* Is Rx FIFO enabled? */ + if (0U != (base->MCR & CAN_MCR_RFEN_MASK)) + { + /* Get RFFN value. */ + lastOccupiedMb = (uint8_t)((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); + /* Calculate the number of last Message Buffer occupied by Rx FIFO. */ + lastOccupiedMb = ((lastOccupiedMb + 1U) * 2U) + 5U; + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + /* the first valid MB should be occupied by ERRATA 5461 or 5829. */ + lastOccupiedMb += 1U; +#endif + fgRet = (mbIdx <= lastOccupiedMb); + } + else + { +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + if (0U == mbIdx) + { + fgRet = true; + } + else +#endif + { + fgRet = false; + } + } + + return fgRet; +} +#endif + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) +/*! + * brief Get the first valid Message buffer ID of give FlexCAN instance. + * + * This function is a helper function for Errata 5641 workaround. + * + * param base FlexCAN peripheral base address. + * return The first valid Message Buffer Number. + */ +static uint8_t FLEXCAN_GetFirstValidMb(CAN_Type *base) +{ + uint8_t firstValidMbNum; + + if (0U != (base->MCR & CAN_MCR_RFEN_MASK)) + { + firstValidMbNum = (uint8_t)((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); + firstValidMbNum = ((firstValidMbNum + 1U) * 2U) + 6U; + } + else + { + firstValidMbNum = 0U; + } + + return firstValidMbNum; +} +#endif + +/*! + * brief Reset the FlexCAN Instance. + * + * Restores the FlexCAN module to reset state, notice that this function + * will set all the registers to reset state so the FlexCAN module can not work + * after calling this API. + * + * param base FlexCAN peripheral base address. + */ +static void FLEXCAN_Reset(CAN_Type *base) +{ + /* The module must should be first exit from low power + * mode, and then soft reset can be applied. + */ + assert(0U == (base->MCR & CAN_MCR_MDIS_MASK)); + + uint8_t i; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + if (0 != (FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(base))) + { + /* De-assert DOZE Enable Bit. */ + base->MCR &= ~CAN_MCR_DOZE_MASK; + } +#endif + + /* Wait until FlexCAN exit from any Low Power Mode. */ + while (0U != (base->MCR & CAN_MCR_LPMACK_MASK)) + { + } + + /* Assert Soft Reset Signal. */ + base->MCR |= CAN_MCR_SOFTRST_MASK; + /* Wait until FlexCAN reset completes. */ + while (0U != (base->MCR & CAN_MCR_SOFTRST_MASK)) + { + } + +/* Reset MCR register. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER) && FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER) + base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_WAKSRC_MASK | + CAN_MCR_MAXMB((uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1U); +#else + base->MCR |= + CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB((uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1U); +#endif + + /* Reset CTRL1 and CTRL2 register, default to eanble SMP feature which enable three sample point to determine the + * received bit's value of the. */ + base->CTRL1 = CAN_CTRL1_SMP_MASK; + base->CTRL2 = CAN_CTRL2_TASD(0x16) | CAN_CTRL2_RRS_MASK | CAN_CTRL2_EACEN_MASK; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /* Enable unrestricted write access to FlexCAN memory. */ + base->CTRL2 |= CAN_CTRL2_WRMFRZ_MASK; + /* Do memory initialization for all FlexCAN RAM in order to have the parity bits in memory properly + updated. */ + *(volatile uint32_t *)CAN_INIT_RXFIR = 0x0U; + flexcan_memset(CAN_INIT_MEMORY_BASE_1, 0, CAN_INIT_MEMORY_SIZE_1); + flexcan_memset(CAN_INIT_MEMORY_BASE_2, 0, CAN_INIT_MEMORY_SIZE_2); + /* Disable unrestricted write access to FlexCAN memory. */ + base->CTRL2 &= ~CAN_CTRL2_WRMFRZ_MASK; + + /* Clean all memory error flags. */ + FLEXCAN_ClearStatusFlags(base, (uint64_t)kFLEXCAN_AllMemoryErrorFlag); +#else + /* Only need clean all Message Buffer memory. */ + flexcan_memset((void *)&base->MB[0], 0, sizeof(base->MB)); +#endif + + /* Clean all individual Rx Mask of Message Buffers. */ + for (i = 0; i < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); i++) + { + base->RXIMR[i] = 0x3FFFFFFF; + } + + /* Clean Global Mask of Message Buffers. */ + base->RXMGMASK = 0x3FFFFFFF; + /* Clean Global Mask of Message Buffer 14. */ + base->RX14MASK = 0x3FFFFFFF; + /* Clean Global Mask of Message Buffer 15. */ + base->RX15MASK = 0x3FFFFFFF; + /* Clean Global Mask of Rx FIFO. */ + base->RXFGMASK = 0x3FFFFFFF; +} + +/*! + * brief Set bit rate of FlexCAN classical CAN frame or CAN FD frame nominal phase. + * + * This function set the bit rate of classical CAN frame or CAN FD frame nominal phase base on + * FLEXCAN_CalculateImprovedTimingValues() API calculated timing values. + * + * note Calling FLEXCAN_SetBitRate() overrides the bit rate set in FLEXCAN_Init(). + * + * param base FlexCAN peripheral base address. + * param sourceClock_Hz Source Clock in Hz. + * param bitRate_Bps Bit rate in Bps. + * return kStatus_Success - Set CAN baud rate (only Nominal phase) successfully. + */ +status_t FLEXCAN_SetBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRate_Bps) +{ + flexcan_timing_config_t timingCfg; + status_t result = kStatus_Fail; + + if (FLEXCAN_CalculateImprovedTimingValues(base, bitRate_Bps, sourceClock_Hz, &timingCfg)) + { + FLEXCAN_SetTimingConfig(base, &timingCfg); + result = kStatus_Success; + } + + return result; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Set bit rate of FlexCAN FD frame. + * + * This function set the baud rate of FLEXCAN FD base on FLEXCAN_FDCalculateImprovedTimingValues() API calculated timing + * values. + * + * @param base FlexCAN peripheral base address. + * @param sourceClock_Hz Source Clock in Hz. + * @param bitRateN_Bps Nominal bit Rate in Bps. + * @param bitRateD_Bps Data bit Rate in Bps. + * @return kStatus_Success - Set CAN FD bit rate (include Nominal and Data phase) successfully. + */ +status_t FLEXCAN_SetFDBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRateN_Bps, uint32_t bitRateD_Bps) +{ + flexcan_timing_config_t timingCfg; + status_t result = kStatus_Fail; + + if (FLEXCAN_FDCalculateImprovedTimingValues(base, bitRateN_Bps, bitRateD_Bps, sourceClock_Hz, &timingCfg)) + { + FLEXCAN_SetFDTimingConfig(base, &timingCfg); + result = kStatus_Success; + } + + return result; +} +#endif + +/*! + * brief Initializes a FlexCAN instance. + * + * This function initializes the FlexCAN module with user-defined settings. + * This example shows how to set up the flexcan_config_t parameters and how + * to call the FLEXCAN_Init function by passing in these parameters. + * code + * flexcan_config_t flexcanConfig; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrc0; + * flexcanConfig.bitRate = 1000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.disableSelfReception = false; + * flexcanConfig.enableListenOnlyMode = false; + * flexcanConfig.enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; + * FLEXCAN_Init(CAN0, &flexcanConfig, 40000000UL); + * endcode + * + * param base FlexCAN peripheral base address. + * param pConfig Pointer to the user-defined configuration structure. + * param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. + */ +void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz) +{ + /* Assertion. */ + assert(NULL != pConfig); + assert((pConfig->maxMbNum > 0U) && + (pConfig->maxMbNum <= (uint8_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base))); + + uint32_t mcrTemp; + uint32_t ctrl1Temp; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance; +#endif + flexcan_timing_config_t timingCfg = pConfig->timingConfig; + /* FlexCAN classical CAN frame or CAN FD frame nominal phase timing setting formula: + * quantum = 1 + (phaseSeg1 + 1) + (phaseSeg2 + 1) + (propSeg + 1); + */ + uint32_t quantum = (1U + ((uint32_t)timingCfg.phaseSeg1 + 1U) + ((uint32_t)timingCfg.phaseSeg2 + 1U) + + ((uint32_t)timingCfg.propSeg + 1U)); + uint32_t tqFre = pConfig->bitRate * quantum; + uint16_t maxDivider; + + /* Assertion: Check bit rate value. */ + assert((pConfig->bitRate != 0U) && (pConfig->bitRate <= 1000000U) && (tqFre <= sourceClock_Hz)); +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + assert((tqFre * MAX_ENPRESDIV) >= sourceClock_Hz); + maxDivider = MAX_ENPRESDIV; +#else + assert((tqFre * MAX_EPRESDIV) >= sourceClock_Hz); + maxDivider = MAX_EPRESDIV; +#endif + } + else + { + assert((tqFre * MAX_PRESDIV) >= sourceClock_Hz); + maxDivider = MAX_PRESDIV; + } +#else + assert((tqFre * MAX_PRESDIV) >= sourceClock_Hz); + maxDivider = MAX_PRESDIV; +#endif + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + instance = FLEXCAN_GetInstance(base); + /* Enable FlexCAN clock. */ + (void)CLOCK_EnableClock(s_flexcanClock[instance]); + /* + * Check the CAN clock in this device whether affected by Other clock gate + * If it affected, we'd better to change other clock source, + * If user insist on using that clock source, user need open these gate at same time, + * In this scene, User need to care the power consumption. + */ + assert(CAN_CLOCK_CHECK_NO_AFFECTS); +#if defined(FLEXCAN_PERIPH_CLOCKS) + /* Enable FlexCAN serial clock. */ + (void)CLOCK_EnableClock(s_flexcanPeriphClock[instance]); +#endif /* FLEXCAN_PERIPH_CLOCKS */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FLEXCAN_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_flexcanResets[FLEXCAN_GetInstance(base)]); +#endif + +#if defined(CAN_CTRL1_CLKSRC_MASK) +#if (defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE) && FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE) + if (0 == FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(base)) +#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */ + { + /* Disable FlexCAN Module. */ + FLEXCAN_Enable(base, false); + + /* Protocol-Engine clock source selection, This bit must be set + * when FlexCAN Module in Disable Mode. + */ + base->CTRL1 = (kFLEXCAN_ClkSrc0 == pConfig->clkSrc) ? (base->CTRL1 & ~CAN_CTRL1_CLKSRC_MASK) : + (base->CTRL1 | CAN_CTRL1_CLKSRC_MASK); + } +#endif /* CAN_CTRL1_CLKSRC_MASK */ + + /* Enable FlexCAN Module for configuration. */ + FLEXCAN_Enable(base, true); + + /* Reset to known status. */ + FLEXCAN_Reset(base); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /* Enable to update in MCER. */ + base->CTRL2 |= CAN_CTRL2_ECRWRE_MASK; + base->MECR &= ~CAN_MECR_ECRWRDIS_MASK; + + /* Enable/Disable Memory Error Detection and Correction.*/ + base->MECR = (pConfig->enableMemoryErrorControl) ? (base->MECR & ~CAN_MECR_ECCDIS_MASK) : + (base->MECR | CAN_MECR_ECCDIS_MASK); + + /* Enable/Disable Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode. */ + base->MECR = (pConfig->enableNonCorrectableErrorEnterFreeze) ? (base->MECR | CAN_MECR_NCEFAFRZ_MASK) : + (base->MECR & ~CAN_MECR_NCEFAFRZ_MASK); + /* Lock MCER register. */ + base->CTRL2 &= ~CAN_CTRL2_ECRWRE_MASK; +#endif + + /* Save current CTRL1 value and enable to enter Freeze mode(enabled by default). */ + ctrl1Temp = base->CTRL1; + + /* Save current MCR value and enable to enter Freeze mode(enabled by default). */ + mcrTemp = base->MCR; + + /* Enable Loop Back Mode? */ + ctrl1Temp = (pConfig->enableLoopBack) ? (ctrl1Temp | CAN_CTRL1_LPB_MASK) : (ctrl1Temp & ~CAN_CTRL1_LPB_MASK); + + /* Enable Timer Sync? */ + ctrl1Temp = (pConfig->enableTimerSync) ? (ctrl1Temp | CAN_CTRL1_TSYN_MASK) : (ctrl1Temp & ~CAN_CTRL1_TSYN_MASK); + + /* Enable Listen Only Mode? */ + ctrl1Temp = (pConfig->enableListenOnlyMode) ? ctrl1Temp | CAN_CTRL1_LOM_MASK : ctrl1Temp & ~CAN_CTRL1_LOM_MASK; + +#if !(defined(FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT) + /* Enable Supervisor Mode? */ + mcrTemp = (pConfig->enableSupervisorMode) ? mcrTemp | CAN_MCR_SUPV_MASK : mcrTemp & ~CAN_MCR_SUPV_MASK; +#endif + + /* Set the maximum number of Message Buffers */ + mcrTemp = (mcrTemp & ~CAN_MCR_MAXMB_MASK) | CAN_MCR_MAXMB((uint32_t)pConfig->maxMbNum - 1U); + + /* Enable Self Wake Up Mode and configure the wake up source. */ + mcrTemp = (pConfig->enableSelfWakeup) ? (mcrTemp | CAN_MCR_SLFWAK_MASK) : (mcrTemp & ~CAN_MCR_SLFWAK_MASK); + mcrTemp = (kFLEXCAN_WakeupSrcFiltered == pConfig->wakeupSrc) ? (mcrTemp | CAN_MCR_WAKSRC_MASK) : + (mcrTemp & ~CAN_MCR_WAKSRC_MASK); +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + /* Enable Pretended Networking Mode? When Pretended Networking mode is set, Self Wake Up feature must be disabled.*/ + mcrTemp = (pConfig->enablePretendedeNetworking) ? ((mcrTemp & ~CAN_MCR_SLFWAK_MASK) | CAN_MCR_PNET_EN_MASK) : + (mcrTemp & ~CAN_MCR_PNET_EN_MASK); +#endif + + /* Enable Individual Rx Masking and Queue feature? */ + mcrTemp = (pConfig->enableIndividMask) ? (mcrTemp | CAN_MCR_IRMQ_MASK) : (mcrTemp & ~CAN_MCR_IRMQ_MASK); + + /* Disable Self Reception? */ + mcrTemp = (pConfig->disableSelfReception) ? mcrTemp | CAN_MCR_SRXDIS_MASK : mcrTemp & ~CAN_MCR_SRXDIS_MASK; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(base)) + { + /* Enable Doze Mode? */ + mcrTemp = (pConfig->enableDoze) ? (mcrTemp | CAN_MCR_DOZE_MASK) : (mcrTemp & ~CAN_MCR_DOZE_MASK); + } +#endif + + /* Write back CTRL1 Configuration to register. */ + base->CTRL1 = ctrl1Temp; + + /* Write back MCR Configuration to register. */ + base->MCR = mcrTemp; + + /* Check whether Nominal Bit Rate Prescaler is overflow. */ + if ((sourceClock_Hz / tqFre - 1U) > maxDivider) + { + timingCfg.preDivider = maxDivider; + } + else + { + timingCfg.preDivider = (uint16_t)(sourceClock_Hz / tqFre) - 1U; + } + + /* Update actual timing characteristic. */ + FLEXCAN_SetTimingConfig(base, &timingCfg); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Initializes a FlexCAN instance. + * + * This function initializes the FlexCAN module with user-defined settings. + * This example shows how to set up the flexcan_config_t parameters and how + * to call the FLEXCAN_FDInit function by passing in these parameters. + * code + * flexcan_config_t flexcanConfig; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrc0; + * flexcanConfig.bitRate = 1000000U; + * flexcanConfig.bitRateFD = 2000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.disableSelfReception = false; + * flexcanConfig.enableListenOnlyMode = false; + * flexcanConfig.enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; + * FLEXCAN_FDInit(CAN0, &flexcanConfig, 80000000UL, kFLEXCAN_16BperMB, true); + * endcode + * + * param base FlexCAN peripheral base address. + * param pConfig Pointer to the user-defined configuration structure. + * param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. + * param dataSize FlexCAN Message Buffer payload size. The actual transmitted or received CAN FD frame data size needs + * to be less than or equal to this value. + * param brs True if bit rate switch is enabled in FD mode. + */ +void FLEXCAN_FDInit( + CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs) +{ + assert((uint32_t)dataSize <= 3U); + assert(((pConfig->bitRate < pConfig->bitRateFD) && brs) || ((pConfig->bitRate == pConfig->bitRateFD) && (!brs))); + + uint32_t fdctrl = 0U; + flexcan_timing_config_t timingCfg = pConfig->timingConfig; + /* FlexCAN FD frame data phase timing setting formula: + * quantum = 1 + (fphaseSeg1 + 1) + (fphaseSeg2 + 1) + fpropSeg; + */ + uint32_t quantum = (1U + ((uint32_t)timingCfg.fphaseSeg1 + 1U) + ((uint32_t)timingCfg.fphaseSeg2 + 1U) + + (uint32_t)timingCfg.fpropSeg); + uint32_t tqFre = pConfig->bitRateFD * quantum; + uint16_t maxDivider; + + /* Check bit rate value. */ + assert((pConfig->bitRateFD <= MAX_CANFD_BITRATE) && (tqFre <= sourceClock_Hz)); +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + assert((tqFre * MAX_EDPRESDIV) >= sourceClock_Hz); + maxDivider = MAX_EDPRESDIV; +#else + assert((tqFre * MAX_FPRESDIV) >= sourceClock_Hz); + maxDivider = MAX_FPRESDIV; +#endif + + /* Initialization of classical CAN. */ + FLEXCAN_Init(base, pConfig, sourceClock_Hz); + + /* Check whether Data Bit Rate Prescaler is overflow. */ + if ((sourceClock_Hz / tqFre - 1U) > maxDivider) + { + timingCfg.fpreDivider = maxDivider; + } + else + { + timingCfg.fpreDivider = (uint16_t)(sourceClock_Hz / tqFre) - 1U; + } + + /* Update actual timing characteristic. */ + FLEXCAN_SetFDTimingConfig(base, &timingCfg); + + /* read FDCTRL register. */ + fdctrl = base->FDCTRL; + + /* Enable FD operation and set bit rate switch. */ + if (brs) + { + fdctrl |= CAN_FDCTRL_FDRATE_MASK; + } + else + { + fdctrl &= ~CAN_FDCTRL_FDRATE_MASK; + } + + /* Before use "|=" operation for multi-bits field, CPU should clean previous Setting. */ + fdctrl = (fdctrl & ~CAN_FDCTRL_MBDSR0_MASK) | CAN_FDCTRL_MBDSR0(dataSize); +#if defined(CAN_FDCTRL_MBDSR1_MASK) + fdctrl = (fdctrl & ~CAN_FDCTRL_MBDSR1_MASK) | CAN_FDCTRL_MBDSR1(dataSize); +#endif +#if defined(CAN_FDCTRL_MBDSR2_MASK) + fdctrl = (fdctrl & ~CAN_FDCTRL_MBDSR2_MASK) | CAN_FDCTRL_MBDSR2(dataSize); +#endif +#if defined(CAN_FDCTRL_MBDSR3_MASK) + fdctrl = (fdctrl & ~CAN_FDCTRL_MBDSR3_MASK) | CAN_FDCTRL_MBDSR3(dataSize); +#endif + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + /* Enable CAN FD operation. */ + base->MCR |= CAN_MCR_FDEN_MASK; + /* Clear SMP bit when CAN FD is enabled (CAN FD only can use one regular sample point plus one optional secondary + * sampling point). */ + base->CTRL1 &= ~CAN_CTRL1_SMP_MASK; + + if (brs && !(pConfig->enableLoopBack)) + { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + /* The TDC offset should be configured as shown in this equation : offset = DTSEG1 + 2 */ + if (((uint32_t)pConfig->timingConfig.fphaseSeg1 + pConfig->timingConfig.fpropSeg + 2U) * + (pConfig->timingConfig.fpreDivider + 1U) < + MAX_ETDCOFF) + { + base->ETDC = + CAN_ETDC_ETDCEN_MASK | CAN_ETDC_TDMDIS(!pConfig->enableTransceiverDelayMeasure) | + CAN_ETDC_ETDCOFF(((uint32_t)pConfig->timingConfig.fphaseSeg1 + pConfig->timingConfig.fpropSeg + 2U) * + (pConfig->timingConfig.fpreDivider + 1U)); + } + else + { + /* Enable the Transceiver Delay Compensation */ + base->ETDC = CAN_ETDC_ETDCEN_MASK | CAN_ETDC_TDMDIS(!pConfig->enableTransceiverDelayMeasure) | + CAN_ETDC_ETDCOFF(MAX_ETDCOFF); + } +#else + /* The TDC offset should be configured as shown in this equation : offset = PSEG1 + PROPSEG + 2 */ + if (((uint32_t)pConfig->timingConfig.fphaseSeg1 + pConfig->timingConfig.fpropSeg + 2U) * + (pConfig->timingConfig.fpreDivider + 1U) < + MAX_TDCOFF) + { + fdctrl = + (fdctrl & ~CAN_FDCTRL_TDCOFF_MASK) | + CAN_FDCTRL_TDCOFF(((uint32_t)pConfig->timingConfig.fphaseSeg1 + pConfig->timingConfig.fpropSeg + 2U) * + (pConfig->timingConfig.fpreDivider + 1U)); + } + else + { + fdctrl = (fdctrl & ~CAN_FDCTRL_TDCOFF_MASK) | CAN_FDCTRL_TDCOFF(MAX_TDCOFF); + } + /* Enable the Transceiver Delay Compensation */ + fdctrl = (fdctrl & ~CAN_FDCTRL_TDCEN_MASK) | CAN_FDCTRL_TDCEN_MASK; +#endif + } + + /* update the FDCTL register. */ + base->FDCTRL = fdctrl; + + /* Enable CAN FD ISO mode by default. */ + base->CTRL2 |= CAN_CTRL2_ISOCANFDEN_MASK; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} +#endif + +/*! + * brief De-initializes a FlexCAN instance. + * + * This function disables the FlexCAN module clock and sets all register values + * to the reset value. + * + * param base FlexCAN peripheral base address. + */ +void FLEXCAN_Deinit(CAN_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance; +#endif + /* Reset all Register Contents. */ + FLEXCAN_Reset(base); + + /* Disable FlexCAN module. */ + FLEXCAN_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + instance = FLEXCAN_GetInstance(base); +#if defined(FLEXCAN_PERIPH_CLOCKS) + /* Disable FlexCAN serial clock. */ + (void)CLOCK_DisableClock(s_flexcanPeriphClock[instance]); +#endif /* FLEXCAN_PERIPH_CLOCKS */ + /* Disable FlexCAN clock. */ + (void)CLOCK_DisableClock(s_flexcanClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Gets the default configuration structure. + * + * This function initializes the FlexCAN configuration structure to default values. The default + * values are as follows. + * flexcanConfig->clkSrc = kFLEXCAN_ClkSrc0; + * flexcanConfig->bitRate = 1000000U; + * flexcanConfig->bitRateFD = 2000000U; + * flexcanConfig->maxMbNum = 16; + * flexcanConfig->enableLoopBack = false; + * flexcanConfig->enableSelfWakeup = false; + * flexcanConfig->enableIndividMask = false; + * flexcanConfig->disableSelfReception = false; + * flexcanConfig->enableListenOnlyMode = false; + * flexcanConfig->enableDoze = false; + * flexcanConfig->enablePretendedeNetworking = false; + * flexcanConfig->enableMemoryErrorControl = true; + * flexcanConfig->enableNonCorrectableErrorEnterFreeze = true; + * flexcanConfig->enableTransceiverDelayMeasure = true; + * flexcanConfig.timingConfig = timingConfig; + * + * param pConfig Pointer to the FlexCAN configuration structure. + */ +void FLEXCAN_GetDefaultConfig(flexcan_config_t *pConfig) +{ + /* Assertion. */ + assert(NULL != pConfig); + + /* Initializes the configure structure to zero. */ + (void)memset(pConfig, 0, sizeof(*pConfig)); + + /* Initialize FlexCAN Module config struct with default value. */ + pConfig->clkSrc = kFLEXCAN_ClkSrc0; + pConfig->bitRate = 1000000U; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + pConfig->bitRateFD = 2000000U; +#endif + pConfig->maxMbNum = 16; + pConfig->enableLoopBack = false; + pConfig->enableTimerSync = true; + pConfig->enableSelfWakeup = false; + pConfig->wakeupSrc = kFLEXCAN_WakeupSrcUnfiltered; + pConfig->enableIndividMask = false; + pConfig->disableSelfReception = false; + pConfig->enableListenOnlyMode = false; +#if !(defined(FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT) + pConfig->enableSupervisorMode = true; +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + pConfig->enableDoze = false; +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + pConfig->enablePretendedeNetworking = false; +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + pConfig->enableMemoryErrorControl = true; + pConfig->enableNonCorrectableErrorEnterFreeze = true; +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + pConfig->enableTransceiverDelayMeasure = true; +#endif + + /* Default protocol timing configuration, nominal bit time quantum is 10 (80% SP), data bit time quantum is 5 + * (60%). Suggest use FLEXCAN_CalculateImprovedTimingValues/FLEXCAN_FDCalculateImprovedTimingValues to get the + * improved timing configuration.*/ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + pConfig->timingConfig.phaseSeg1 = 1; + pConfig->timingConfig.phaseSeg2 = 1; + pConfig->timingConfig.propSeg = 4; + pConfig->timingConfig.rJumpwidth = 1; + pConfig->timingConfig.fphaseSeg1 = 1; + pConfig->timingConfig.fphaseSeg2 = 1; + pConfig->timingConfig.fpropSeg = 0; + pConfig->timingConfig.frJumpwidth = 1; +#else + pConfig->timingConfig.phaseSeg1 = 1; + pConfig->timingConfig.phaseSeg2 = 1; + pConfig->timingConfig.propSeg = 4; + pConfig->timingConfig.rJumpwidth = 1; +#endif +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) +/*! + * brief Configures the FlexCAN Pretended Networking mode. + * + * This function configures the FlexCAN Pretended Networking mode with given configuration. + * + * param base FlexCAN peripheral base address. + * param pConfig Pointer to the FlexCAN Rx FIFO configuration structure. + */ +void FLEXCAN_SetPNConfig(CAN_Type *base, const flexcan_pn_config_t *pConfig) +{ + /* Assertion. */ + assert(NULL != pConfig); + assert(0U != pConfig->matchNum); + uint32_t pnctrl; + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + pnctrl = (pConfig->matchNum > 1U) ? CAN_CTRL1_PN_FCS(0x2U | (uint32_t)pConfig->matchSrc) : + CAN_CTRL1_PN_FCS(pConfig->matchSrc); + pnctrl |= (pConfig->enableMatch) ? (CAN_CTRL1_PN_WUMF_MSK_MASK) : 0U; + pnctrl |= (pConfig->enableTimeout) ? (CAN_CTRL1_PN_WTOF_MSK_MASK) : 0U; + pnctrl |= CAN_CTRL1_PN_NMATCH(pConfig->matchNum) | CAN_CTRL1_PN_IDFS(pConfig->idMatchMode) | + CAN_CTRL1_PN_PLFS(pConfig->dataMatchMode); + base->CTRL1_PN = pnctrl; + base->CTRL2_PN = CAN_CTRL2_PN_MATCHTO(pConfig->timeoutValue); + base->FLT_ID1 = pConfig->idLower; + base->FLT_ID2_IDMASK = pConfig->idUpper; + base->FLT_DLC = CAN_FLT_DLC_FLT_DLC_LO(pConfig->lengthLower) | CAN_FLT_DLC_FLT_DLC_HI(pConfig->lengthUpper); + base->PL1_LO = pConfig->lowerWord0; + base->PL1_HI = pConfig->lowerWord1; + base->PL2_PLMASK_LO = pConfig->upperWord0; + base->PL2_PLMASK_HI = pConfig->upperWord1; + + FLEXCAN_ClearStatusFlags(base, (uint64_t)kFLEXCAN_PNMatchIntFlag | (uint64_t)kFLEXCAN_PNTimeoutIntFlag); + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +/*! + * brief Reads a FlexCAN Message from Wake Up MB. + * + * This function reads a CAN message from the FlexCAN Wake up Message Buffers. There are four Wake up Message Buffers + * (WMBs) used to store incoming messages in Pretended Networking mode. The WMB index indicates the arrival order. The + * last message is stored in WMB3. + * + * param base FlexCAN peripheral base address. + * param pRxFrame Pointer to CAN message frame structure for reception. + * param mbIdx The FlexCAN Wake up Message Buffer index. Range in 0x0 ~ 0x3. + * retval kStatus_Success - Read Message from Wake up Message Buffer successfully. + * retval kStatus_Fail - Wake up Message Buffer has no valid content. + */ +status_t FLEXCAN_ReadPNWakeUpMB(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame) +{ + /* Assertion. */ + assert(NULL != pRxFrame); + assert(mbIdx <= 0x3U); + + uint32_t cs_temp; + status_t status; + + /* Check if Wake Up MB has valid content. */ + if (CAN_WU_MTC_MCOUNTER(mbIdx) < (base->WU_MTC & CAN_WU_MTC_MCOUNTER_MASK)) + { + /* Read CS field of wake up Message Buffer. */ + cs_temp = base->WMB[mbIdx].CS; + + /* Store Message ID. */ + pRxFrame->id = base->WMB[mbIdx].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); + + /* Get the message ID and format. */ + pRxFrame->format = (cs_temp & CAN_CS_IDE_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameFormatExtend : + (uint8_t)kFLEXCAN_FrameFormatStandard; + + /* Get the message type. */ + pRxFrame->type = + (cs_temp & CAN_CS_RTR_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameTypeRemote : (uint8_t)kFLEXCAN_FrameTypeData; + + /* Get the message length. */ + pRxFrame->length = (uint8_t)((cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT); + + /* Messages received during Pretended Networking mode don't have time stamps, and the respective field in the + WMB structure must be ignored. */ + pRxFrame->timestamp = 0x0; + + /* Store Message Payload. */ + pRxFrame->dataWord0 = base->WMB[mbIdx].D03; + pRxFrame->dataWord1 = base->WMB[mbIdx].D47; + + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} +#endif + +/*! + * brief Sets the FlexCAN classical protocol timing characteristic. + * + * This function gives user settings to classical CAN or CAN FD nominal phase timing characteristic. + * The function is for an experienced user. For less experienced users, call the FLEXCAN_GetDefaultConfig() + * and get the default timing characteristicsthe, then call FLEXCAN_Init() and fill the + * bit rate field. + * + * note Calling FLEXCAN_SetTimingConfig() overrides the bit rate set + * in FLEXCAN_Init(). + * + * param base FlexCAN peripheral base address. + * param pConfig Pointer to the timing configuration structure. + */ +void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig) +{ + /* Assertion. */ + assert(NULL != pConfig); + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + /* Enable extended Bit Timing register ENCBT. */ + base->CTRL2 |= CAN_CTRL2_BTE_MASK; + + /* Updating Timing Setting according to configuration structure. */ + base->EPRS = (base->EPRS & (~CAN_EPRS_ENPRESDIV_MASK)) | CAN_EPRS_ENPRESDIV(pConfig->preDivider); + base->ENCBT = CAN_ENCBT_NRJW(pConfig->rJumpwidth) | + CAN_ENCBT_NTSEG1((uint32_t)pConfig->phaseSeg1 + pConfig->propSeg + 1U) | + CAN_ENCBT_NTSEG2(pConfig->phaseSeg2); +#else + /* On RT106x devices, a single write may be ignored, so it is necessary to read back the register value to + * determine whether the value is written successfully. */ + + do + { + /* Enable Bit Timing register CBT, updating Timing Setting according to configuration structure. */ + base->CBT = CAN_CBT_BTF_MASK | CAN_CBT_EPRESDIV(pConfig->preDivider) | CAN_CBT_ERJW(pConfig->rJumpwidth) | + CAN_CBT_EPSEG1(pConfig->phaseSeg1) | CAN_CBT_EPSEG2(pConfig->phaseSeg2) | + CAN_CBT_EPROPSEG(pConfig->propSeg); + + } while ((CAN_CBT_EPRESDIV(pConfig->preDivider) | CAN_CBT_ERJW(pConfig->rJumpwidth) | + CAN_CBT_EPSEG1(pConfig->phaseSeg1) | CAN_CBT_EPSEG2(pConfig->phaseSeg2) | + CAN_CBT_EPROPSEG(pConfig->propSeg)) != + (base->CBT & (CAN_CBT_EPRESDIV_MASK | CAN_CBT_ERJW_MASK | CAN_CBT_EPSEG1_MASK | CAN_CBT_EPSEG2_MASK | + CAN_CBT_EPROPSEG_MASK))); +#endif + } + else + { + /* Cleaning previous Timing Setting. */ + base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | + CAN_CTRL1_PROPSEG_MASK); + + /* Updating Timing Setting according to configuration structure. */ + base->CTRL1 |= (CAN_CTRL1_PRESDIV(pConfig->preDivider) | CAN_CTRL1_RJW(pConfig->rJumpwidth) | + CAN_CTRL1_PSEG1(pConfig->phaseSeg1) | CAN_CTRL1_PSEG2(pConfig->phaseSeg2) | + CAN_CTRL1_PROPSEG(pConfig->propSeg)); + } +#else + /* Cleaning previous Timing Setting. */ + base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | + CAN_CTRL1_PROPSEG_MASK); + + /* Updating Timing Setting according to configuration structure. */ + base->CTRL1 |= (CAN_CTRL1_PRESDIV(pConfig->preDivider) | CAN_CTRL1_RJW(pConfig->rJumpwidth) | + CAN_CTRL1_PSEG1(pConfig->phaseSeg1) | CAN_CTRL1_PSEG2(pConfig->phaseSeg2) | + CAN_CTRL1_PROPSEG(pConfig->propSeg)); +#endif + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Sets the FlexCAN FD data phase timing characteristic. + * + * This function gives user settings to CAN FD data phase timing characteristic. + * The function is for an experienced user. For less experienced users, call the FLEXCAN_GetDefaultConfig() + * and get the default timing characteristicsthe, then call FLEXCAN_FDInit() and fill the + * data phase bit rate field. + * + * note Calling FLEXCAN_SetFDTimingConfig() overrides the bit rate set + * in FLEXCAN_FDInit(). + * + * param base FlexCAN peripheral base address. + * param pConfig Pointer to the timing configuration structure. + */ +void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig) +{ + /* Assertion. */ + assert(NULL != pConfig); + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + /* Enable extended Bit Timing register EDCBT. */ + base->CTRL2 |= CAN_CTRL2_BTE_MASK; + + base->EPRS = (base->EPRS & (~CAN_EPRS_EDPRESDIV_MASK)) | CAN_EPRS_EDPRESDIV(pConfig->fpreDivider); + base->EDCBT = CAN_EDCBT_DRJW(pConfig->frJumpwidth) | CAN_EDCBT_DTSEG2(pConfig->fphaseSeg2) | + CAN_EDCBT_DTSEG1((uint32_t)pConfig->fphaseSeg1 + pConfig->fpropSeg); +#else + /* Enable Bit Timing register FDCBT,*/ + base->CBT |= CAN_CBT_BTF_MASK; + + /* On RT106x devices, a single write may be ignored, so it is necessary to read back the register value to determine + * whether the value is written successfully. */ + do + { + /* Updating Timing Setting according to configuration structure. */ + base->FDCBT = (CAN_FDCBT_FPRESDIV(pConfig->fpreDivider) | CAN_FDCBT_FRJW(pConfig->frJumpwidth) | + CAN_FDCBT_FPSEG1(pConfig->fphaseSeg1) | CAN_FDCBT_FPSEG2(pConfig->fphaseSeg2) | + CAN_FDCBT_FPROPSEG(pConfig->fpropSeg)); + } while ((CAN_FDCBT_FPRESDIV(pConfig->fpreDivider) | CAN_FDCBT_FRJW(pConfig->frJumpwidth) | + CAN_FDCBT_FPSEG1(pConfig->fphaseSeg1) | CAN_FDCBT_FPSEG2(pConfig->fphaseSeg2) | + CAN_FDCBT_FPROPSEG(pConfig->fpropSeg)) != + (base->FDCBT & (CAN_FDCBT_FPRESDIV_MASK | CAN_FDCBT_FRJW_MASK | CAN_FDCBT_FPSEG1_MASK | + CAN_FDCBT_FPSEG2_MASK | CAN_FDCBT_FPROPSEG_MASK))); +#endif + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} +#endif + +/*! + * brief Sets the FlexCAN receive message buffer global mask. + * + * This function sets the global mask for the FlexCAN message buffer in a matching process. + * The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init(). + * + * param base FlexCAN peripheral base address. + * param mask Rx Message Buffer Global Mask value. + */ +void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask) +{ + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Setting Rx Message Buffer Global Mask value. */ + base->RXMGMASK = mask; + base->RX14MASK = mask; + base->RX15MASK = mask; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +/*! + * brief Sets the FlexCAN receive FIFO global mask. + * + * This function sets the global mask for FlexCAN FIFO in a matching process. + * + * param base FlexCAN peripheral base address. + * param mask Rx Fifo Global Mask value. + */ +void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask) +{ + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Setting Rx FIFO Global Mask value. */ + base->RXFGMASK = mask; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +/*! + * brief Sets the FlexCAN receive individual mask. + * + * This function sets the individual mask for the FlexCAN matching process. + * The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init(). + * If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer. + * If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to + * the Rx Filter with the same index. Note that only the first 32 + * individual masks can be used as the Rx FIFO filter mask. + * + * param base FlexCAN peripheral base address. + * param maskIdx The Index of individual Mask. + * param mask Rx Individual Mask value. + */ +void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask) +{ + assert(maskIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Setting Rx Individual Mask value. */ + base->RXIMR[maskIdx] = mask; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +/*! + * brief Configures a FlexCAN transmit message buffer. + * + * This function aborts the previous transmission, cleans the Message Buffer, and + * configures it as a Transmit Message Buffer. + * + * param base FlexCAN peripheral base address. + * param mbIdx The Message Buffer index. + * param enable Enable/disable Tx Message Buffer. + * - true: Enable Tx Message Buffer. + * - false: Disable Tx Message Buffer. + */ +void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + /* Inactivate Message Buffer. */ + if (enable) + { + base->MB[mbIdx].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + } + else + { + base->MB[mbIdx].CS = 0; + } + + /* Clean Message Buffer content. */ + base->MB[mbIdx].ID = 0x0; + base->MB[mbIdx].WORD0 = 0x0; + base->MB[mbIdx].WORD1 = 0x0; +} + +/*! + * brief Calculates the segment values for a single bit time for classical CAN. + * + * This function use to calculates the Classical CAN segment values which will be set in CTRL1/CBT/ENCBT register. + * + * param bitRate The classical CAN bit rate in bps. + * param base FlexCAN peripheral base address. + * param tqNum Number of time quantas per bit, range in 8 ~ 25 when use CTRL1, range in 8 ~ 129 when use CBT, range in + * 8 ~ 385 when use ENCBT. param pTimingConfig Pointer to the FlexCAN timing configuration structure. + */ +static void FLEXCAN_GetSegments(CAN_Type *base, + uint32_t bitRate, + uint32_t tqNum, + flexcan_timing_config_t *pTimingConfig) +{ + uint32_t ideal_sp; + uint32_t seg1Max, proSegMax; + uint32_t seg1Temp; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + /* Maximum value allowed in ENCBT register. */ + seg1Max = MAX_NTSEG2 + 1U; + proSegMax = MAX_NTSEG1 - MAX_NTSEG2; +#else + /* Maximum value allowed in CBT register. */ + seg1Max = MAX_EPSEG1 + 1U; + proSegMax = MAX_EPROPSEG + 1U; +#endif + } + else + { + /* Maximum value allowed in CTRL1 register. */ + seg1Max = MAX_PSEG1 + 1U; + proSegMax = MAX_PROPSEG + 1U; + } +#else + /* Maximum value allowed in CTRL1 register. */ + seg1Max = MAX_PSEG1 + 1U; + proSegMax = MAX_PROPSEG + 1U; +#endif + + /* Try to find the ideal sample point, according to CiA 301 doc.*/ + if (bitRate == 1000000U) + { + ideal_sp = IDEAL_SP_LOW; + } + else if (bitRate >= 800000U) + { + ideal_sp = IDEAL_SP_MID; + } + else + { + ideal_sp = IDEAL_SP_HIGH; + } + /* Calculates phaseSeg2. */ + pTimingConfig->phaseSeg2 = (uint8_t)(tqNum - (tqNum * ideal_sp) / (uint32_t)IDEAL_SP_FACTOR); + if (pTimingConfig->phaseSeg2 < MIN_TIME_SEGMENT2) + { + pTimingConfig->phaseSeg2 = MIN_TIME_SEGMENT2; + } + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { +#if !(defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + if (pTimingConfig->phaseSeg2 > (uint8_t)(MAX_EPSEG2 + 1U)) + { + pTimingConfig->phaseSeg2 = (uint8_t)(MAX_EPSEG2 + 1U); + } +#endif + } +#endif + + /* Calculates phaseSeg1 and propSeg and try to make phaseSeg1 equal to phaseSeg2. */ + if ((tqNum - pTimingConfig->phaseSeg2 - 1U) > (seg1Max + proSegMax)) + { + seg1Temp = seg1Max + proSegMax; + pTimingConfig->phaseSeg2 = (uint8_t)(tqNum - 1U - seg1Temp); + } + else + { + seg1Temp = tqNum - pTimingConfig->phaseSeg2 - 1U; + } + if (seg1Temp > (pTimingConfig->phaseSeg2 + proSegMax)) + { + pTimingConfig->propSeg = (uint8_t)proSegMax; + pTimingConfig->phaseSeg1 = (uint8_t)(seg1Temp - proSegMax); + } + else + { + pTimingConfig->propSeg = (uint8_t)(seg1Temp - pTimingConfig->phaseSeg2); + pTimingConfig->phaseSeg1 = pTimingConfig->phaseSeg2; + } + + /* rJumpwidth (sjw) is the minimum value of phaseSeg1 and phaseSeg2. */ + pTimingConfig->rJumpwidth = + (pTimingConfig->phaseSeg1 > pTimingConfig->phaseSeg2) ? pTimingConfig->phaseSeg2 : pTimingConfig->phaseSeg1; +#if !(defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (pTimingConfig->rJumpwidth > (MAX_RJW + 1U)) + { + pTimingConfig->rJumpwidth = (uint8_t)(MAX_RJW + 1U); + } +#else + if (0 == FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { + if (pTimingConfig->rJumpwidth > (MAX_RJW + 1U)) + { + pTimingConfig->rJumpwidth = (uint8_t)(MAX_RJW + 1U); + } + } +#endif + + pTimingConfig->phaseSeg1 -= 1U; + pTimingConfig->phaseSeg2 -= 1U; + pTimingConfig->propSeg -= 1U; + pTimingConfig->rJumpwidth -= 1U; +} + +/*! + * brief Calculates the improved timing values by specific bit Rates for classical CAN. + * + * This function use to calculates the Classical CAN timing values according to the given bit rate. The Calculated + * timing values will be set in CTRL1/CBT/ENCBT register. The calculation is based on the recommendation of the CiA 301 + * v4.2.0 and previous version document. + * + * param base FlexCAN peripheral base address. + * param bitRate The classical CAN speed in bps defined by user, should be less than or equal to 1Mbps. + * param sourceClock_Hz The Source clock frequency in Hz. + * param pTimingConfig Pointer to the FlexCAN timing configuration structure. + * + * return TRUE if timing configuration found, FALSE if failed to find configuration. + */ +bool FLEXCAN_CalculateImprovedTimingValues(CAN_Type *base, + uint32_t bitRate, + uint32_t sourceClock_Hz, + flexcan_timing_config_t *pTimingConfig) +{ + /* Observe bit rate maximums. */ + assert(bitRate <= MAX_CAN_BITRATE); + + uint32_t clk; + uint32_t tqNum, tqMin, pdivMAX; + uint32_t spTemp = 1000U; + flexcan_timing_config_t configTemp = {0}; + bool fgRet = false; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + /* Auto Improved Protocal timing for ENCBT. */ + tqNum = ENCBT_MAX_TIME_QUANTA; + tqMin = ENCBT_MIN_TIME_QUANTA; + pdivMAX = MAX_ENPRESDIV; +#else + /* Auto Improved Protocal timing for CBT. */ + tqNum = CBT_MAX_TIME_QUANTA; + tqMin = CBT_MIN_TIME_QUANTA; + pdivMAX = MAX_PRESDIV; +#endif + } + else + { + /* Auto Improved Protocal timing for CTRL1. */ + tqNum = CTRL1_MAX_TIME_QUANTA; + tqMin = CTRL1_MIN_TIME_QUANTA; + pdivMAX = MAX_PRESDIV; + } +#else + /* Auto Improved Protocal timing for CTRL1. */ + tqNum = CTRL1_MAX_TIME_QUANTA; + tqMin = CTRL1_MIN_TIME_QUANTA; + pdivMAX = MAX_PRESDIV; +#endif + do + { + clk = bitRate * tqNum; + if (clk > sourceClock_Hz) + { + continue; /* tqNum too large, clk has been exceed sourceClock_Hz. */ + } + + if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) + { + continue; /* Non-supporting: the frequency of clock source is not divisible by target bit rate, the user + should change a divisible bit rate. */ + } + + configTemp.preDivider = (uint16_t)(sourceClock_Hz / clk) - 1U; + if (configTemp.preDivider > pdivMAX) + { + break; /* The frequency of source clock is too large or the bit rate is too small, the pre-divider could + not handle it. */ + } + + /* Calculates the best timing configuration under current tqNum. */ + FLEXCAN_GetSegments(base, bitRate, tqNum, &configTemp); + /* Determine whether the calculated timing configuration can get the optimal sampling point. */ + if (((((uint32_t)configTemp.phaseSeg2 + 1U) * 1000U) / tqNum) < spTemp) + { + spTemp = (((uint32_t)configTemp.phaseSeg2 + 1U) * 1000U) / tqNum; + pTimingConfig->preDivider = configTemp.preDivider; + pTimingConfig->rJumpwidth = configTemp.rJumpwidth; + pTimingConfig->phaseSeg1 = configTemp.phaseSeg1; + pTimingConfig->phaseSeg2 = configTemp.phaseSeg2; + pTimingConfig->propSeg = configTemp.propSeg; + } + fgRet = true; + } while (--tqNum >= tqMin); + + return fgRet; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Get Mailbox offset number by dword. + * + * This function gets the offset number of the specified mailbox. + * Mailbox is not consecutive between memory regions when payload is not 8 bytes + * so need to calculate the specified mailbox address. + * For example, in the first memory region, MB[0].CS address is 0x4002_4080. For 32 bytes + * payload frame, the second mailbox is ((1/12)*512 + 1%12*40)/4 = 10, meaning 10 dword + * after the 0x4002_4080, which is actually the address of mailbox MB[1].CS. + * + * param base FlexCAN peripheral base address. + * param mbIdx Mailbox index. + */ +static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx) +{ + uint32_t offset = 0; + uint32_t dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + if (dataSize == (uint32_t)kFLEXCAN_8BperMB) + { + offset = (((uint32_t)mbIdx / 32U) * 512U + ((uint32_t)mbIdx % 32U) * 16U); + } + else if (dataSize == (uint32_t)kFLEXCAN_16BperMB) + { + offset = (((uint32_t)mbIdx / 21U) * 512U + ((uint32_t)mbIdx % 21U) * 24U); + } + else if (dataSize == (uint32_t)kFLEXCAN_32BperMB) + { + offset = (((uint32_t)mbIdx / 12U) * 512U + ((uint32_t)mbIdx % 12U) * 40U); + } + else + { + offset = (((uint32_t)mbIdx / 7U) * 512U + ((uint32_t)mbIdx % 7U) * 72U); + } + + /* To get the dword aligned offset, need to divide by 4. */ + offset = offset / 4U; + return offset; +} + +/*! + * brief Calculates the segment values for a single bit time for CAN FD data phase. + * + * This function use to calculates the CAN FD data phase segment values which will be set in CFDCBT/EDCBT + * register. + * + * param bitRateFD CAN FD data phase bit rate. + * param tqNum Number of time quanta per bit + * param pTimingConfig Pointer to the FlexCAN timing configuration structure. + */ +static void FLEXCAN_FDGetSegments(uint32_t bitRateFD, uint32_t tqNum, flexcan_timing_config_t *pTimingConfig) +{ + uint32_t ideal_sp; + uint32_t seg1Max, proSegMax, seg2Max; + uint32_t seg1Temp; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + /* Maximum value allowed in EDCBT register. */ + seg1Max = MAX_DTSEG2 + 1U; + proSegMax = MAX_DTSEG1 - MAX_DTSEG2; + seg2Max = MAX_DTSEG2 + 1U; +#else + /* Maximum value allowed in FDCBT register. */ + seg1Max = MAX_FPSEG1 + 1U; + proSegMax = MAX_FPROPSEG; + seg2Max = MAX_FPSEG2 + 1U; +#endif + + /* According to CiA doc 1301 v1.0.0, which specified data phase sample point postion for CAN FD at 80 MHz. */ + if (bitRateFD <= 1000000U) + { + ideal_sp = IDEAL_DATA_SP_1; + } + else if (bitRateFD <= 2000000U) + { + ideal_sp = IDEAL_DATA_SP_2; + } + else if (bitRateFD <= 4000000U) + { + ideal_sp = IDEAL_DATA_SP_3; + } + else + { + ideal_sp = IDEAL_DATA_SP_4; + } + + /* Calculates fphaseSeg2. */ + pTimingConfig->fphaseSeg2 = (uint8_t)(tqNum - (tqNum * ideal_sp) / (uint32_t)IDEAL_SP_FACTOR); + if (pTimingConfig->fphaseSeg2 < MIN_TIME_SEGMENT2) + { + pTimingConfig->fphaseSeg2 = MIN_TIME_SEGMENT2; + } + else if (pTimingConfig->fphaseSeg2 > seg2Max) + { + pTimingConfig->fphaseSeg2 = (uint8_t)seg2Max; + } + else + { + ; /* Intentional empty */ + } + + /* Calculates fphaseSeg1 and fpropSeg and try to make phaseSeg1 equal to phaseSeg2 */ + if ((tqNum - pTimingConfig->fphaseSeg2 - 1U) > (seg1Max + proSegMax)) + { + seg1Temp = seg1Max + proSegMax; + pTimingConfig->fphaseSeg2 = (uint8_t)(tqNum - 1U - seg1Temp); + } + else + { + seg1Temp = tqNum - pTimingConfig->fphaseSeg2 - 1U; + } + if (seg1Temp > (pTimingConfig->fphaseSeg2 + proSegMax)) + { + pTimingConfig->fpropSeg = (uint8_t)proSegMax; + pTimingConfig->fphaseSeg1 = (uint8_t)(seg1Temp - proSegMax); + } + else if (seg1Temp > pTimingConfig->fphaseSeg2) + { + pTimingConfig->fpropSeg = (uint8_t)(seg1Temp - pTimingConfig->fphaseSeg2); + pTimingConfig->fphaseSeg1 = pTimingConfig->fphaseSeg2; + } + else + { + pTimingConfig->fpropSeg = 0U; + pTimingConfig->fphaseSeg1 = (uint8_t)seg1Temp; + } + + /* rJumpwidth (sjw) is the minimum value of phaseSeg1 and phaseSeg2. */ + pTimingConfig->frJumpwidth = + (pTimingConfig->fphaseSeg1 > pTimingConfig->fphaseSeg2) ? pTimingConfig->fphaseSeg2 : pTimingConfig->fphaseSeg1; + + pTimingConfig->fphaseSeg1 -= 1U; + pTimingConfig->fphaseSeg2 -= 1U; + pTimingConfig->frJumpwidth -= 1U; +} + +/*! + * brief Calculates the improved timing values by specific bit rate for CAN FD nominal phase. + * + * This function use to calculates the CAN FD nominal phase timing values according to the given nominal phase bit rate. + * The Calculated timing values will be set in CBT/ENCBT registers. The calculation is based on the recommendation of + * the CiA 1301 v1.0.0 document. + * + * param bitRate The CAN FD nominal phase speed in bps defined by user, should be less than or equal to 1Mbps. + * param sourceClock_Hz The Source clock frequency in Hz. + * param pTimingConfig Pointer to the FlexCAN timing configuration structure. + * + * return TRUE if timing configuration found, FALSE if failed to find configuration. + */ +static bool FLEXCAN_CalculateImprovedNominalTimingValues(uint32_t bitRate, + uint32_t sourceClock_Hz, + flexcan_timing_config_t *pTimingConfig) +{ + /* Observe bit rate maximums. */ + assert(bitRate <= MAX_CAN_BITRATE); + + uint32_t clk; + uint32_t tqNum, tqMin, pdivMAX, seg1Max, proSegMax, seg1Temp; + uint32_t spTemp = 1000U; + flexcan_timing_config_t configTemp = {0}; + bool fgRet = false; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + /* Auto Improved Protocal timing for ENCBT. */ + tqNum = ENCBT_MAX_TIME_QUANTA; + tqMin = ENCBT_MIN_TIME_QUANTA; + pdivMAX = MAX_ENPRESDIV; + seg1Max = MAX_NTSEG2 + 1U; + proSegMax = MAX_NTSEG1 - MAX_NTSEG2; +#else + /* Auto Improved Protocal timing for CBT. */ + tqNum = CBT_MAX_TIME_QUANTA; + tqMin = CBT_MIN_TIME_QUANTA; + pdivMAX = MAX_PRESDIV; + seg1Max = MAX_EPSEG1 + 1U; + proSegMax = MAX_EPROPSEG + 1U; +#endif + + do + { + clk = bitRate * tqNum; + if (clk > sourceClock_Hz) + { + continue; /* tqNum too large, clk has been exceed sourceClock_Hz. */ + } + + if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) + { + continue; /* Non-supporting: the frequency of clock source is not divisible by target bit rate, the user + should change a divisible bit rate. */ + } + + configTemp.preDivider = (uint16_t)(sourceClock_Hz / clk) - 1U; + if (configTemp.preDivider > pdivMAX) + { + break; /* The frequency of source clock is too large or the bit rate is too small, the pre-divider could + not handle it. */ + } + + /* Calculates the best timing configuration under current tqNum. */ + configTemp.phaseSeg2 = (uint8_t)(tqNum - (tqNum * IDEAL_NOMINAL_SP) / (uint32_t)IDEAL_SP_FACTOR); + + /* Calculates phaseSeg1 and propSeg and try to make phaseSeg1 equal to phaseSeg2. */ + if ((tqNum - configTemp.phaseSeg2 - 1U) > (seg1Max + proSegMax)) + { + seg1Temp = seg1Max + proSegMax; + configTemp.phaseSeg2 = (uint8_t)(tqNum - 1U - seg1Temp); + } + else + { + seg1Temp = tqNum - configTemp.phaseSeg2 - 1U; + } + if (seg1Temp > (configTemp.phaseSeg2 + proSegMax)) + { + configTemp.propSeg = (uint8_t)proSegMax; + configTemp.phaseSeg1 = (uint8_t)(seg1Temp - proSegMax); + } + else + { + configTemp.propSeg = (uint8_t)(seg1Temp - configTemp.phaseSeg2); + configTemp.phaseSeg1 = configTemp.phaseSeg2; + } + + /* rJumpwidth (sjw) is the minimum value of phaseSeg1 and phaseSeg2. */ + configTemp.rJumpwidth = + (configTemp.phaseSeg1 > configTemp.phaseSeg2) ? configTemp.phaseSeg2 : configTemp.phaseSeg1; + configTemp.phaseSeg1 -= 1U; + configTemp.phaseSeg2 -= 1U; + configTemp.propSeg -= 1U; + configTemp.rJumpwidth -= 1U; + + if (((((uint32_t)configTemp.phaseSeg2 + 1U) * 1000U) / tqNum) < spTemp) + { + spTemp = (((uint32_t)configTemp.phaseSeg2 + 1U) * 1000U) / tqNum; + pTimingConfig->preDivider = configTemp.preDivider; + pTimingConfig->rJumpwidth = configTemp.rJumpwidth; + pTimingConfig->phaseSeg1 = configTemp.phaseSeg1; + pTimingConfig->phaseSeg2 = configTemp.phaseSeg2; + pTimingConfig->propSeg = configTemp.propSeg; + } + fgRet = true; + } while (--tqNum >= tqMin); + + return fgRet; +} + +/*! + * brief Calculates the improved timing values by specific bit rates for CAN FD. + * + * This function use to calculates the CAN FD timing values according to the given nominal phase bit rate and data phase + * bit rate. The Calculated timing values will be set in CBT/ENCBT and FDCBT/EDCBT registers. The calculation is based + * on the recommendation of the CiA 1301 v1.0.0 document. + * + * param bitRate The CAN FD nominal phase speed in bps defined by user. + * param bitRateFD The CAN FD data phase speed in bps defined by user. Equal to bitRate means disable bit rate + * switching. param sourceClock_Hz The Source clock frequency in Hz. param pTimingConfig Pointer to the FlexCAN timing + * configuration structure. + * + * return TRUE if timing configuration found, FALSE if failed to find configuration + */ +bool FLEXCAN_FDCalculateImprovedTimingValues(CAN_Type *base, + uint32_t bitRate, + uint32_t bitRateFD, + uint32_t sourceClock_Hz, + flexcan_timing_config_t *pTimingConfig) +{ + /* Observe bit rate maximums */ + assert(bitRate <= MAX_CANFD_BITRATE); + assert(bitRateFD <= MAX_CANFD_BITRATE); + /* Data phase bit rate need greater or equal to nominal phase bit rate. */ + assert(bitRate <= bitRateFD); + + uint32_t clk; + uint32_t tqMin, pdivMAX, tqTemp; + bool fgRet = false; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + /* Auto Improved Protocal timing for EDCBT. */ + tqTemp = EDCBT_MAX_TIME_QUANTA; + tqMin = EDCBT_MIN_TIME_QUANTA; + pdivMAX = MAX_EDPRESDIV; +#else + /* Auto Improved Protocal timing for FDCBT. */ + tqTemp = FDCBT_MAX_TIME_QUANTA; + tqMin = FDCBT_MIN_TIME_QUANTA; + pdivMAX = MAX_FPRESDIV; +#endif + + if (bitRate != bitRateFD) + { + /* To minimize errors when processing FD frames, try to get the same bit rate prescaler value for nominal phase + and data phase. */ + do + { + clk = bitRateFD * tqTemp; + if (clk > sourceClock_Hz) + { + continue; /* tqTemp too large, clk x tqTemp has been exceed sourceClock_Hz. */ + } + + if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) + { + continue; /* the frequency of clock source is not divisible by target bit rate. */ + } + + pTimingConfig->fpreDivider = (uint16_t)(sourceClock_Hz / clk) - 1U; + + if (pTimingConfig->fpreDivider > pdivMAX) + { + break; /* The frequency of source clock is too large or the bit rate is too small, the pre-divider + could not handle it. */ + } + + /* Calculates the best data phase timing configuration. */ + FLEXCAN_FDGetSegments(bitRateFD, tqTemp, pTimingConfig); + + if (FLEXCAN_CalculateImprovedNominalTimingValues( + bitRate, sourceClock_Hz / ((uint32_t)pTimingConfig->fpreDivider + 1U), pTimingConfig)) + { + fgRet = true; + if (pTimingConfig->preDivider == 0U) + { + pTimingConfig->preDivider = pTimingConfig->fpreDivider; + break; + } + else + { + pTimingConfig->preDivider = + (pTimingConfig->preDivider + 1U) * (pTimingConfig->fpreDivider + 1U) - 1U; + continue; + } + } + } while (--tqTemp >= tqMin); + } + else + { + if (FLEXCAN_CalculateImprovedNominalTimingValues(bitRate, sourceClock_Hz, pTimingConfig)) + { + /* No need data phase timing configuration, data phase rate equal to nominal phase rate, user don't use Brs + feature. */ + pTimingConfig->fpreDivider = 0U; + pTimingConfig->frJumpwidth = 0U; + pTimingConfig->fphaseSeg1 = 0U; + pTimingConfig->fphaseSeg2 = 0U; + pTimingConfig->fpropSeg = 0U; + fgRet = true; + } + } + return fgRet; +} + +/*! + * brief Configures a FlexCAN transmit message buffer. + * + * This function aborts the previous transmission, cleans the Message Buffer, and + * configures it as a Transmit Message Buffer. + * + * param base FlexCAN peripheral base address. + * param mbIdx The Message Buffer index. + * param enable Enable/disable Tx Message Buffer. + * - true: Enable Tx Message Buffer. + * - false: Disable Tx Message Buffer. + */ +void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + uint8_t cnt = 0; + uint8_t payload_dword = 1; + uint32_t dataSize; + dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base)); +#endif + + /* Inactivate Message Buffer. */ + if (enable) + { + /* Inactivate by writing CS. */ + mbAddr[offset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + } + else + { + mbAddr[offset] = 0x0; + } + + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + for (cnt = 0; cnt < (dataSize + 1U); cnt++) + { + payload_dword *= 2U; + } + + /* Clean ID. */ + mbAddr[offset + 1U] = 0x0U; + /* Clean Message Buffer content, DWORD by DWORD. */ + for (cnt = 0; cnt < payload_dword; cnt++) + { + mbAddr[offset + 2U + cnt] = 0x0U; + } + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); +#endif +} +#endif /* FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE */ + +/*! + * brief Configures a FlexCAN Receive Message Buffer. + * + * This function cleans a FlexCAN build-in Message Buffer and configures it + * as a Receive Message Buffer. + * + * param base FlexCAN peripheral base address. + * param mbIdx The Message Buffer index. + * param pRxMbConfig Pointer to the FlexCAN Message Buffer configuration structure. + * param enable Enable/disable Rx Message Buffer. + * - true: Enable Rx Message Buffer. + * - false: Disable Rx Message Buffer. + */ +void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(((NULL != pRxMbConfig) || (false == enable))); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + uint32_t cs_temp = 0; + + /* Inactivate Message Buffer. */ + base->MB[mbIdx].CS = 0; + + /* Clean Message Buffer content. */ + base->MB[mbIdx].ID = 0x0; + base->MB[mbIdx].WORD0 = 0x0; + base->MB[mbIdx].WORD1 = 0x0; + + if (enable) + { + /* Setup Message Buffer ID. */ + base->MB[mbIdx].ID = pRxMbConfig->id; + + /* Setup Message Buffer format. */ + if (kFLEXCAN_FrameFormatExtend == pRxMbConfig->format) + { + cs_temp |= CAN_CS_IDE_MASK; + } + + /* Setup Message Buffer type. */ + if (kFLEXCAN_FrameTypeRemote == pRxMbConfig->type) + { + cs_temp |= CAN_CS_RTR_MASK; + } + + /* Activate Rx Message Buffer. */ + cs_temp |= CAN_CS_CODE(kFLEXCAN_RxMbEmpty); + base->MB[mbIdx].CS = cs_temp; + } +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Configures a FlexCAN Receive Message Buffer. + * + * This function cleans a FlexCAN build-in Message Buffer and configures it + * as a Receive Message Buffer. + * + * param base FlexCAN peripheral base address. + * param mbIdx The Message Buffer index. + * param pRxMbConfig Pointer to the FlexCAN Message Buffer configuration structure. + * param enable Enable/disable Rx Message Buffer. + * - true: Enable Rx Message Buffer. + * - false: Disable Rx Message Buffer. + */ +void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(((NULL != pRxMbConfig) || (false == enable))); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + uint32_t cs_temp = 0; + uint8_t cnt = 0; + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); + uint8_t payload_dword; + uint32_t dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + + /* Inactivate Message Buffer. */ + mbAddr[offset] = 0U; + + /* Clean Message Buffer content. */ + mbAddr[offset + 1U] = 0U; + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + payload_dword = (2U << dataSize); + for (cnt = 0; cnt < payload_dword; cnt++) + { + mbAddr[offset + 2U + cnt] = 0x0; + } + + if (enable) + { + /* Setup Message Buffer ID. */ + mbAddr[offset + 1U] = pRxMbConfig->id; + + /* Setup Message Buffer format. */ + if (kFLEXCAN_FrameFormatExtend == pRxMbConfig->format) + { + cs_temp |= CAN_CS_IDE_MASK; + } + + /* Setup Message Buffer type. */ + if (kFLEXCAN_FrameTypeRemote == pRxMbConfig->type) + { + cs_temp |= CAN_CS_RTR_MASK; + } + + /* Activate Rx Message Buffer. */ + cs_temp |= CAN_CS_CODE(kFLEXCAN_RxMbEmpty); + mbAddr[offset] = cs_temp; + } +} +#endif + +/*! + * brief Configures the FlexCAN Legacy Rx FIFO. + * + * This function configures the FlexCAN Rx FIFO with given configuration. + * note Legacy Rx FIFO only can receive classic CAN message. + * + * param base FlexCAN peripheral base address. + * param pRxFifoConfig Pointer to the FlexCAN Legacy Rx FIFO configuration structure. Can be NULL when enable parameter + * is false. + * param enable Enable/disable Legacy Rx FIFO. + * - true: Enable Legacy Rx FIFO. + * - false: Disable Legacy Rx FIFO. + */ +void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *pRxFifoConfig, bool enable) +{ + /* Assertion. */ + assert((NULL != pRxFifoConfig) || (false == enable)); + + volatile uint32_t *mbAddr; + uint8_t i, j, k, rffn = 0, numMbOccupy; + uint32_t setup_mb = 0; + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + if (enable) + { + assert(pRxFifoConfig->idFilterNum <= 128U); +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + /* Legacy Rx FIFO and Enhanced Rx FIFO cannot be enabled at the same time. */ + assert((base->ERFCR & CAN_ERFCR_ERFEN_MASK) == 0U); +#endif + + /* Get the setup_mb value. */ + setup_mb = (uint8_t)((base->MCR & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT); + setup_mb = (setup_mb < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)) ? + setup_mb : + (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); + + /* Determine RFFN value. */ + for (i = 0; i <= 0xFU; i++) + { + if ((8U * (i + 1U)) >= pRxFifoConfig->idFilterNum) + { + rffn = i; + assert(((setup_mb - 8U) - (2U * rffn)) > 0U); + + base->CTRL2 = (base->CTRL2 & ~CAN_CTRL2_RFFN_MASK) | CAN_CTRL2_RFFN(rffn); + break; + } + } + + /* caculate the Number of Mailboxes occupied by RX Legacy FIFO and the filter. */ + numMbOccupy = 6U + (rffn + 1U) * 2U; + + /* Copy ID filter table to Message Buffer Region (Fix MISRA_C-2012 Rule 18.1). */ + j = 0U; + for (i = 6U; i < numMbOccupy; i++) + { + /* Get address for current mail box. */ + mbAddr = &(base->MB[i].CS); + + /* One Mail box contain 4U DWORD registers. */ + for (k = 0; k < 4U; k++) + { + /* Fill all valid filter in the mail box occupied by filter. + * Disable unused Rx FIFO Filter, the other rest of register in the last Mail box occupied by fiter set + * as 0xffffffff. + */ + mbAddr[k] = (j < pRxFifoConfig->idFilterNum) ? (pRxFifoConfig->idFilterTable[j]) : 0xFFFFFFFFU; + + /* Try to fill next filter in current Mail Box. */ + j++; + } + } + + /* Setup ID Fitlter Type. */ + switch (pRxFifoConfig->idFilterType) + { + case kFLEXCAN_RxFifoFilterTypeA: + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x0); + break; + case kFLEXCAN_RxFifoFilterTypeB: + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x1); + break; + case kFLEXCAN_RxFifoFilterTypeC: + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x2); + break; + case kFLEXCAN_RxFifoFilterTypeD: + /* All frames rejected. */ + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x3); + break; + default: + /* All the cases have been listed above, the default clause should not be reached. */ + assert(false); + break; + } + + /* Setting Message Reception Priority. */ + base->CTRL2 = (pRxFifoConfig->priority == kFLEXCAN_RxFifoPrioHigh) ? (base->CTRL2 & ~CAN_CTRL2_MRP_MASK) : + (base->CTRL2 | CAN_CTRL2_MRP_MASK); + + /* Enable Rx Message FIFO. */ + base->MCR |= CAN_MCR_RFEN_MASK; + } + else + { + rffn = (uint8_t)((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); + /* caculate the Number of Mailboxes occupied by RX Legacy FIFO and the filter. */ + numMbOccupy = 6U + (rffn + 1U) * 2U; + + /* Disable Rx Message FIFO. */ + base->MCR &= ~CAN_MCR_RFEN_MASK; + + /* Clean MB0 ~ MB5 and all MB occupied by ID filters (Fix MISRA_C-2012 Rule 18.1). */ + + for (i = 0; i < numMbOccupy; i++) + { + FLEXCAN_SetRxMbConfig(base, i, NULL, false); + } + } + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * brief Configures the FlexCAN Enhanced Rx FIFO. + * + * This function configures the Enhanced Rx FIFO with given configuration. + * note Enhanced Rx FIFO support receive classic CAN or CAN FD messages, Legacy Rx FIFO and Enhanced Rx FIFO + * cannot be enabled at the same time. + * + * param base FlexCAN peripheral base address. + * param pConfig Pointer to the FlexCAN Enhanced Rx FIFO configuration structure. Can be NULL when enable parameter + * is false. + * param enable Enable/disable Enhanced Rx FIFO. + * - true: Enable Enhanced Rx FIFO. + * - false: Disable Enhanced Rx FIFO. + */ +void FLEXCAN_SetEnhancedRxFifoConfig(CAN_Type *base, const flexcan_enhanced_rx_fifo_config_t *pConfig, bool enable) +{ + /* Assertion. */ + assert((NULL != pConfig) || (false == enable)); + uint32_t i; + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + if (enable) + { + /* Each pair of filter elements occupies 2 words and can consist of one extended ID filter element or two + * standard ID filter elements. */ + assert((((uint32_t)pConfig->idFilterPairNum * 2UL) < + (uint32_t)FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER) && + (pConfig->extendIdFilterNum <= pConfig->idFilterPairNum) && (0UL != pConfig->idFilterPairNum)); + + /* The Enhanced Rx FIFO Watermark cannot be greater than the enhanced Rx FIFO size. */ + assert(pConfig->fifoWatermark < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE); + + /* Legacy Rx FIFO and Enhanced Rx FIFO cannot be enabled at the same time. */ + assert((base->MCR & CAN_MCR_RFEN_MASK) == 0U); + + /* Reset Enhanced Rx FIFO engine and clear flags. */ + base->ERFSR |= CAN_ERFSR_ERFCLR_MASK | CAN_ERFSR_ERFUFW_MASK | CAN_ERFSR_ERFOVF_MASK | CAN_ERFSR_ERFWMI_MASK | + CAN_ERFSR_ERFDA_MASK; + /* Setting Enhanced Rx FIFO. */ + base->ERFCR = CAN_ERFCR_DMALW(pConfig->dmaPerReadLength) | CAN_ERFCR_NEXIF(pConfig->extendIdFilterNum) | + CAN_ERFCR_NFE((uint32_t)pConfig->idFilterPairNum - 1UL) | CAN_ERFCR_ERFWM(pConfig->fifoWatermark); + /* Copy ID filter table to Enhanced Rx FIFO Filter Element registers. */ + for (i = 0; i < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER; i++) + { + base->ERFFEL[i] = (i < ((uint32_t)pConfig->idFilterPairNum * 2U)) ? pConfig->idFilterTable[i] : 0xFFFFFFFFU; + } + + /* Setting Message Reception Priority. */ + base->CTRL2 = (pConfig->priority == kFLEXCAN_RxFifoPrioHigh) ? (base->CTRL2 & ~CAN_CTRL2_MRP_MASK) : + (base->CTRL2 | CAN_CTRL2_MRP_MASK); + /* Enable Enhanced Rx FIFO. */ + base->ERFCR |= CAN_ERFCR_ERFEN_MASK; + } + else + { + /* Disable Enhanced Rx FIFO. */ + base->ERFCR = 0U; + /* Reset Enhanced Rx FIFO engine and clear flags. */ + base->ERFSR |= CAN_ERFSR_ERFCLR_MASK | CAN_ERFSR_ERFUFW_MASK | CAN_ERFSR_ERFOVF_MASK | CAN_ERFSR_ERFWMI_MASK | + CAN_ERFSR_ERFDA_MASK; + /* Clean all Enhanced Rx FIFO Filter Element registers. */ + for (i = 0; i < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER; i++) + { + base->ERFFEL[i] = 0xFFFFFFFFU; + } + } + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) +/*! + * brief Enables or disables the FlexCAN Legacy/Enhanced Rx FIFO DMA request. + * + * This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO. + * + * param base FlexCAN peripheral base address. + * param enable true to enable, false to disable. + */ +void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable) +{ + if (enable) + { + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Enable FlexCAN DMA. */ + base->MCR |= CAN_MCR_DMA_MASK; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); + } + else + { + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Disable FlexCAN DMA. */ + base->MCR &= ~CAN_MCR_DMA_MASK; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); + } +} +#endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */ + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +/*! + * brief Gets the FlexCAN Memory Error Report registers status. + * + * This function gets the FlexCAN Memory Error Report registers status. + * + * param base FlexCAN peripheral base address. + * param errorStatus Pointer to FlexCAN Memory Error Report registers status structure. + */ +void FLEXCAN_GetMemoryErrorReportStatus(CAN_Type *base, flexcan_memory_error_report_status_t *errorStatus) +{ + uint32_t temp; + /* Disable updates of the error report registers. */ + base->MECR |= CAN_MECR_RERRDIS_MASK; + + errorStatus->accessAddress = (uint16_t)(base->RERRAR & CAN_RERRAR_ERRADDR_MASK); + errorStatus->errorData = base->RERRDR; + errorStatus->errorType = + (base->RERRAR & CAN_RERRAR_NCE_MASK) == 0U ? kFLEXCAN_CorrectableError : kFLEXCAN_NonCorrectableError; + + temp = (base->RERRAR & CAN_RERRAR_SAID_MASK) >> CAN_RERRAR_SAID_SHIFT; + switch (temp) + { + case (uint32_t)kFLEXCAN_MoveOutFlexCanAccess: + case (uint32_t)kFLEXCAN_MoveInAccess: + case (uint32_t)kFLEXCAN_TxArbitrationAccess: + case (uint32_t)kFLEXCAN_RxMatchingAccess: + case (uint32_t)kFLEXCAN_MoveOutHostAccess: + errorStatus->accessType = (flexcan_memory_access_type_t)temp; + break; + default: + assert(false); + break; + } + + for (uint32_t i = 0; i < 4U; i++) + { + temp = (base->RERRSYNR & ((uint32_t)CAN_RERRSYNR_SYND0_MASK << (i * 8U))) >> (i * 8U); + errorStatus->byteStatus[i].byteIsRead = (base->RERRSYNR & ((uint32_t)CAN_RERRSYNR_BE0_MASK << (i * 8U))) != 0U; + switch (temp) + { + case CAN_RERRSYNR_SYND0(kFLEXCAN_NoError): + case CAN_RERRSYNR_SYND0(kFLEXCAN_ParityBits0Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_ParityBits1Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_ParityBits2Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_ParityBits3Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_ParityBits4Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_DataBits0Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_DataBits1Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_DataBits2Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_DataBits3Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_DataBits4Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_DataBits5Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_DataBits6Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_DataBits7Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_AllZeroError): + case CAN_RERRSYNR_SYND0(kFLEXCAN_AllOneError): + errorStatus->byteStatus[i].bitAffected = (flexcan_byte_error_syndrome_t)temp; + break; + default: + errorStatus->byteStatus[i].bitAffected = kFLEXCAN_NonCorrectableErrors; + break; + } + } + + /* Re-enable updates of the error report registers. */ + base->MECR &= CAN_MECR_RERRDIS_MASK; +} +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) +/*! + * FlexCAN: A frame with wrong ID or payload is transmitted into + * the CAN bus when the Message Buffer under transmission is + * either aborted or deactivated while the CAN bus is in the Bus Idle state + * + * This function to do workaround for ERR006032 + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN Message Buffer index. + */ +static void FLEXCAN_ERRATA_6032(CAN_Type *base, volatile uint32_t *mbCSAddr) +{ + uint32_t dbg_temp = 0U; + uint32_t u32TempCS = 0U; + uint32_t u32Timeout = DELAY_BUSIDLE; + /*disable ALL interrupts to prevent any context switching*/ + uint32_t irqMask = DisableGlobalIRQ(); + dbg_temp = (uint32_t)(base->DBG1); + switch (dbg_temp & CAN_DBG1_CFSM_MASK) + { + case RXINTERMISSION: + if (CBN_VALUE3 == (dbg_temp & CAN_DBG1_CBN_MASK)) + { + /*wait until CFSM is different from RXINTERMISSION */ + while (RXINTERMISSION == (base->DBG1 & CAN_DBG1_CFSM_MASK)) + { + __NOP(); + } + } + break; + case TXINTERMISSION: + if (CBN_VALUE3 == (dbg_temp & CAN_DBG1_CBN_MASK)) + { + /*wait until CFSM is different from TXINTERMISSION*/ + while (TXINTERMISSION == (base->DBG1 & CAN_DBG1_CFSM_MASK)) + { + __NOP(); + } + } + break; + default: + /* To avoid MISRA-C 2012 rule 16.4 issue. */ + break; + } + /*Anyway, BUSIDLE need to delay*/ + if (BUSIDLE == (base->DBG1 & CAN_DBG1_CFSM_MASK)) + { + while (u32Timeout-- > 0U) + { + __NOP(); + } + + /*Write 0x0 into Code field of CS word.*/ + u32TempCS = (uint32_t)(*mbCSAddr); + u32TempCS &= ~CAN_CS_CODE_MASK; + *mbCSAddr = u32TempCS; + } + /*restore interruption*/ + EnableGlobalIRQ(irqMask); +} +#endif + +/*! + * brief Writes a FlexCAN Message to the Transmit Message Buffer. + * + * This function writes a CAN Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN Message transmit. After + * that the function returns immediately. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN Message Buffer index. + * param pTxFrame Pointer to CAN message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *pTxFrame) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(NULL != pTxFrame); + assert(pTxFrame->length <= 8U); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + uint32_t cs_temp = 0; + status_t status; + + /* Check if Message Buffer is available. */ + if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK)) + { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) + FLEXCAN_ERRATA_6032(base, &(base->MB[mbIdx].CS)); +#endif + /* Inactive Tx Message Buffer. */ + base->MB[mbIdx].CS = (base->MB[mbIdx].CS & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); + + /* Fill Message ID field. */ + base->MB[mbIdx].ID = pTxFrame->id; + + /* Fill Message Format field. */ + if ((uint32_t)kFLEXCAN_FrameFormatExtend == pTxFrame->format) + { + cs_temp |= CAN_CS_SRR_MASK | CAN_CS_IDE_MASK; + } + + /* Fill Message Type field. */ + if ((uint32_t)kFLEXCAN_FrameTypeRemote == pTxFrame->type) + { + cs_temp |= CAN_CS_RTR_MASK; + } + + cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(pTxFrame->length); + + /* Load Message Payload. */ + base->MB[mbIdx].WORD0 = pTxFrame->dataWord0; + base->MB[mbIdx].WORD1 = pTxFrame->dataWord1; + + /* Activate Tx Message Buffer. */ + base->MB[mbIdx].CS = cs_temp; + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); +#endif + + status = kStatus_Success; + } + else + { + /* Tx Message Buffer is activated, return immediately. */ + status = kStatus_Fail; + } + + return status; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Writes a FlexCAN FD Message to the Transmit Message Buffer. + * + * This function writes a CAN FD Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN FD Message transmit. After + * that the function returns immediately. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN FD Message Buffer index. + * param pTxFrame Pointer to CAN FD message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *pTxFrame) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(NULL != pTxFrame); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + status_t status; + uint32_t cs_temp = 0; + uint8_t cnt = 0; + uint32_t can_cs = 0; + uint8_t payload_dword = 1; + uint32_t dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base)); +#endif + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); + + can_cs = mbAddr[offset]; + /* Check if Message Buffer is available. */ + if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (can_cs & CAN_CS_CODE_MASK)) + { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) + FLEXCAN_ERRATA_6032(base, &(mbAddr[offset])); +#endif + /* Inactive Tx Message Buffer and Fill Message ID field. */ + mbAddr[offset] = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); + mbAddr[offset + 1U] = pTxFrame->id; + + /* Fill Message Format field. */ + if ((uint32_t)kFLEXCAN_FrameFormatExtend == pTxFrame->format) + { + cs_temp |= CAN_CS_SRR_MASK | CAN_CS_IDE_MASK; + } + + /* Fill Message Type field. */ + if ((uint32_t)kFLEXCAN_FrameTypeRemote == pTxFrame->type) + { + cs_temp |= CAN_CS_RTR_MASK; + } + + cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(pTxFrame->length) | CAN_CS_EDL(pTxFrame->edl) | + CAN_CS_BRS(pTxFrame->brs); + + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + for (cnt = 0; cnt < (dataSize + 1U); cnt++) + { + payload_dword *= 2U; + } + + /* Load Message Payload and Activate Tx Message Buffer. */ + for (cnt = 0; cnt < payload_dword; cnt++) + { + mbAddr[offset + 2U + cnt] = pTxFrame->dataWord[cnt]; + } + mbAddr[offset] = cs_temp; + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); +#endif + + status = kStatus_Success; + } + else + { + /* Tx Message Buffer is activated, return immediately. */ + status = kStatus_Fail; + } + + return status; +} +#endif + +/*! + * brief Reads a FlexCAN Message from Receive Message Buffer. + * + * This function reads a CAN message from a specified Receive Message Buffer. + * The function fills a receive CAN message frame structure with + * just received data and activates the Message Buffer again. + * The function returns immediately. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN Message Buffer index. + * param pRxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(NULL != pRxFrame); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + uint32_t cs_temp; + uint32_t rx_code; + status_t status; + + /* Read CS field of Rx Message Buffer to lock Message Buffer. */ + cs_temp = base->MB[mbIdx].CS; + /* Get Rx Message Buffer Code field. */ + rx_code = (cs_temp & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT; + + /* Check to see if Rx Message Buffer is full. */ + if (((uint32_t)kFLEXCAN_RxMbFull == rx_code) || ((uint32_t)kFLEXCAN_RxMbOverrun == rx_code)) + { + /* Store Message ID. */ + pRxFrame->id = base->MB[mbIdx].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); + + /* Get the message ID and format. */ + pRxFrame->format = (cs_temp & CAN_CS_IDE_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameFormatExtend : + (uint8_t)kFLEXCAN_FrameFormatStandard; + + /* Get the message type. */ + pRxFrame->type = + (cs_temp & CAN_CS_RTR_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameTypeRemote : (uint8_t)kFLEXCAN_FrameTypeData; + + /* Get the message length. */ + pRxFrame->length = (uint8_t)((cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT); + + /* Get the time stamp. */ + pRxFrame->timestamp = (uint16_t)((cs_temp & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + + /* Store Message Payload. */ + pRxFrame->dataWord0 = base->MB[mbIdx].WORD0; + pRxFrame->dataWord1 = base->MB[mbIdx].WORD1; + + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + if ((uint32_t)kFLEXCAN_RxMbFull == rx_code) + { + status = kStatus_Success; + } + else + { + status = kStatus_FLEXCAN_RxOverflow; + } + } + else + { + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + status = kStatus_Fail; + } + + return status; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Reads a FlexCAN FD Message from Receive Message Buffer. + * + * This function reads a CAN FD message from a specified Receive Message Buffer. + * The function fills a receive CAN FD message frame structure with + * just received data and activates the Message Buffer again. + * The function returns immediately. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN FD Message Buffer index. + * param pRxFrame Pointer to CAN FD message frame structure for reception. + * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(NULL != pRxFrame); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + status_t status; + uint32_t cs_temp; + uint8_t rx_code; + uint8_t cnt = 0; + uint32_t can_id = 0; + uint32_t dataSize; + dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + uint8_t payload_dword = 1; + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); + + /* Read CS field of Rx Message Buffer to lock Message Buffer. */ + cs_temp = mbAddr[offset]; + can_id = mbAddr[offset + 1U]; + + /* Get Rx Message Buffer Code field. */ + rx_code = (uint8_t)((cs_temp & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT); + + /* Check to see if Rx Message Buffer is full. */ + if (((uint8_t)kFLEXCAN_RxMbFull == rx_code) || ((uint8_t)kFLEXCAN_RxMbOverrun == rx_code)) + { + /* Store Message ID. */ + pRxFrame->id = can_id & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); + + /* Get the message ID and format. */ + pRxFrame->format = (cs_temp & CAN_CS_IDE_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameFormatExtend : + (uint8_t)kFLEXCAN_FrameFormatStandard; + + /* Get Bit Rate Switch flag. */ + pRxFrame->brs = (cs_temp & CAN_CS_BRS_MASK) != 0U ? 1U : 0U; + + /* Get Extended Data Length flag. */ + pRxFrame->edl = (cs_temp & CAN_CS_EDL_MASK) != 0U ? 1U : 0U; + + /* Get the message type. */ + pRxFrame->type = + (cs_temp & CAN_CS_RTR_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameTypeRemote : (uint8_t)kFLEXCAN_FrameTypeData; + + /* Get the message length. */ + pRxFrame->length = (uint8_t)((cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT); + + /* Get the time stamp. */ + pRxFrame->timestamp = (uint16_t)((cs_temp & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + for (cnt = 0; cnt < (dataSize + 1U); cnt++) + { + payload_dword *= 2U; + } + + /* Store Message Payload. */ + for (cnt = 0; cnt < payload_dword; cnt++) + { + pRxFrame->dataWord[cnt] = mbAddr[offset + 2U + cnt]; + } + + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + if ((uint32_t)kFLEXCAN_RxMbFull == rx_code) + { + status = kStatus_Success; + } + else + { + status = kStatus_FLEXCAN_RxOverflow; + } + } + else + { + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + status = kStatus_Fail; + } + + return status; +} +#endif + +/*! + * brief Reads a FlexCAN Message from Legacy Rx FIFO. + * + * This function reads a CAN message from the FlexCAN Legacy Rx FIFO. + * + * param base FlexCAN peripheral base address. + * param pRxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Read Message from Rx FIFO successfully. + * retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *pRxFrame) +{ + /* Assertion. */ + assert(NULL != pRxFrame); + + uint32_t cs_temp; + status_t status; + + /* Check if Legacy Rx FIFO is Enabled. */ + if (0U != (base->MCR & CAN_MCR_RFEN_MASK)) + { + /* Read CS field of Rx Message Buffer to lock Message Buffer. */ + cs_temp = base->MB[0].CS; + + /* Read data from Rx FIFO output port. */ + /* Store Message ID. */ + pRxFrame->id = base->MB[0].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); + + /* Get the message ID and format. */ + pRxFrame->format = (cs_temp & CAN_CS_IDE_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameFormatExtend : + (uint8_t)kFLEXCAN_FrameFormatStandard; + + /* Get the message type. */ + pRxFrame->type = + (cs_temp & CAN_CS_RTR_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameTypeRemote : (uint8_t)kFLEXCAN_FrameTypeData; + + /* Get the message length. */ + pRxFrame->length = (uint8_t)((cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT); + + /* Get the time stamp. */ + pRxFrame->timestamp = (uint16_t)((cs_temp & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + + /* Store Message Payload. */ + pRxFrame->dataWord0 = base->MB[0].WORD0; + pRxFrame->dataWord1 = base->MB[0].WORD1; + + /* Store ID Filter Hit Index. */ + pRxFrame->idhit = (uint16_t)(base->RXFIR & CAN_RXFIR_IDHIT_MASK); + + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * brief Reads a FlexCAN Message from Enhanced Rx FIFO. + * + * This function reads a CAN or CAN FD message from the FlexCAN Enhanced Rx FIFO. + * + * param base FlexCAN peripheral base address. + * param pRxFrame Pointer to CAN FD message frame structure for reception. + * retval kStatus_Success - Read Message from Rx FIFO successfully. + * retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_ReadEnhancedRxFifo(CAN_Type *base, flexcan_fd_frame_t *pRxFrame) +{ + /* Assertion. */ + assert(NULL != pRxFrame); + + status_t status; + uint32_t idHitOff; + + /* Check if Enhanced Rx FIFO is Enabled. */ + if (0U != (base->ERFCR & CAN_ERFCR_ERFEN_MASK)) + { + /* Enhanced Rx FIFO ID HIT offset is changed dynamically according to data length code (DLC) . */ + idHitOff = (DLC_LENGTH_DECODE(((flexcan_fd_frame_t *)E_RX_FIFO(base))->length) + 3U) / 4U + 3U; + /* Copy CAN FD Message from Enhanced Rx FIFO, should use the DLC value to identify the bytes that belong to the + * message which is being read. */ + (void)memcpy((void *)pRxFrame, (void *)(uint32_t *)E_RX_FIFO(base), sizeof(uint32_t) * idHitOff); + pRxFrame->idhit = pRxFrame->dataWord[idHitOff - 3U]; + /* Clear the unused frame data. */ + for (uint32_t i = (idHitOff - 3U); i < 16U; i++) + { + pRxFrame->dataWord[i] = 0x0; + } + + /* Clear data available flag to let FlexCAN know one frame has been read from the Enhanced Rx FIFO. */ + base->ERFSR = CAN_ERFSR_ERFDA_MASK; + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} +#endif + +/*! + * brief Performs a polling send transaction on the CAN bus. + * + * note A transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param mbIdx The FlexCAN Message Buffer index. + * param pTxFrame Pointer to CAN message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pTxFrame) +{ + status_t status; + + /* Write Tx Message Buffer to initiate a data sending. */ + if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, (const flexcan_frame_t *)(uintptr_t)pTxFrame)) + { + /* Wait until CAN Message send out. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (mbIdx >= 64U) + { + while (0U == FLEXCAN_GetHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U))) + { + } + FLEXCAN_ClearHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U)); + } + else + { + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) && FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); +#else + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint32_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint32_t)1U << mbIdx); +#endif + + /*After TX MB tranfered success, update the Timestamp from MB[mbIdx].CS register*/ + pTxFrame->timestamp = (uint16_t)((base->MB[mbIdx].CS & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Performs a polling receive transaction on the CAN bus. + * + * note A transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param mbIdx The FlexCAN Message Buffer index. + * param pRxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame) +{ +/* Wait until Rx Message Buffer non-empty. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (mbIdx >= 64U) + { + while (0U == FLEXCAN_GetHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U))) + { + } + FLEXCAN_ClearHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U)); + } + else + { + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) && FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); +#else + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint32_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint32_t)1U << mbIdx); +#endif + + /* Read Received CAN Message. */ + return FLEXCAN_ReadRxMb(base, mbIdx, pRxFrame); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Performs a polling send transaction on the CAN bus. + * + * note A transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + * param pTxFrame Pointer to CAN FD message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pTxFrame) +{ + status_t status; + + /* Write Tx Message Buffer to initiate a data sending. */ + if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, mbIdx, (const flexcan_fd_frame_t *)(uintptr_t)pTxFrame)) + { + /* Wait until CAN Message send out. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (mbIdx >= 64U) + { + while (0U == FLEXCAN_GetHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U))) + { + } + FLEXCAN_ClearHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U)); + } + else + { + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) && FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); +#else + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint32_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint32_t)1U << mbIdx); +#endif + /*After TX MB tranfered success, update the Timestamp from base->MB[offset for CAN FD].CS register*/ + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); + pTxFrame->timestamp = (uint16_t)((mbAddr[offset] & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Performs a polling receive transaction on the CAN bus. + * + * note A transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + * param pRxFrame Pointer to CAN FD message frame structure for reception. + * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame) +{ +/* Wait until Rx Message Buffer non-empty. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (mbIdx >= 64U) + { + while (0U == FLEXCAN_GetHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U))) + { + } + FLEXCAN_ClearHigh64MbStatusFlags(base, (uint64_t)1U << (mbIdx - 64U)); + } + else + { + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) && FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER) + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint64_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << mbIdx); +#else + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint32_t)1U << mbIdx)) + { + } + FLEXCAN_ClearMbStatusFlags(base, (uint32_t)1U << mbIdx); +#endif + + /* Read Received CAN Message. */ + return FLEXCAN_ReadFDRxMb(base, mbIdx, pRxFrame); +} +#endif + +/*! + * brief Performs a polling receive transaction from Legacy Rx FIFO on the CAN bus. + * + * note A transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param pRxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Read Message from Rx FIFO successfully. + * retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *pRxFrame) +{ + status_t rxFifoStatus; + + /* Wait until Legacy Rx FIFO non-empty. */ + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag)) + { + } + + /* Read data from Legacy Rx FIFO. */ + rxFifoStatus = FLEXCAN_ReadRxFifo(base, pRxFrame); + + /* Clean Rx Fifo available flag. */ + FLEXCAN_ClearMbStatusFlags(base, (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag); + + return rxFifoStatus; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * brief Performs a polling receive transaction from Enhanced Rx FIFO on the CAN bus. + * + * note A transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param pRxFrame Pointer to CAN FD message frame structure for reception. + * retval kStatus_Success - Read Message from Rx FIFO successfully. + * retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_TransferReceiveEnhancedFifoBlocking(CAN_Type *base, flexcan_fd_frame_t *pRxFrame) +{ + status_t rxFifoStatus; + + /* Wait until Enhanced Rx FIFO non-empty. */ + while (0U == (FLEXCAN_GetStatusFlags(base) & (uint64_t)kFLEXCAN_ERxFifoDataAvlIntFlag)) + { + } + + /* Read data from Enhanced Rx FIFO */ + rxFifoStatus = FLEXCAN_ReadEnhancedRxFifo(base, pRxFrame); + + return rxFifoStatus; +} +#endif + +/*! + * brief Initializes the FlexCAN handle. + * + * This function initializes the FlexCAN handle, which can be used for other FlexCAN + * transactional APIs. Usually, for a specified FlexCAN instance, + * call this API once to get the initialized handle. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param callback The callback function. + * param userData The parameter of the callback function. + */ +void FLEXCAN_TransferCreateHandle(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_transfer_callback_t callback, + void *userData) +{ + assert(NULL != handle); + + uint8_t instance; + + /* Clean FlexCAN transfer handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Get instance from peripheral base address. */ + instance = (uint8_t)FLEXCAN_GetInstance(base); + + /* Save the context in global variables to support the double weak mechanism. */ + s_flexcanHandle[instance] = handle; + + /* Register Callback function. */ + handle->callback = callback; + handle->userData = userData; + + s_flexcanIsr = FLEXCAN_TransferHandleIRQ; + + /* We Enable Error & Status interrupt here, because this interrupt just + * report current status of FlexCAN module through Callback function. + * It is insignificance without a available callback function. + */ + if (handle->callback != NULL) + { + FLEXCAN_EnableInterrupts( + base, (uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable | + (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable | + (uint32_t)kFLEXCAN_WakeUpInterruptEnable +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + | (uint64_t)kFLEXCAN_PNMatchWakeUpInterruptEnable | + (uint64_t)kFLEXCAN_PNTimeoutWakeUpInterruptEnable +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + | (uint64_t)kFLEXCAN_HostAccessNCErrorInterruptEnable | + (uint64_t)kFLEXCAN_FlexCanAccessNCErrorInterruptEnable | + (uint64_t)kFLEXCAN_HostOrFlexCanCErrorInterruptEnable +#endif + ); + } + else + { + FLEXCAN_DisableInterrupts( + base, (uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable | + (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable | + (uint32_t)kFLEXCAN_WakeUpInterruptEnable +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + | (uint64_t)kFLEXCAN_PNMatchWakeUpInterruptEnable | + (uint64_t)kFLEXCAN_PNTimeoutWakeUpInterruptEnable +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + | (uint64_t)kFLEXCAN_HostAccessNCErrorInterruptEnable | + (uint64_t)kFLEXCAN_FlexCanAccessNCErrorInterruptEnable | + (uint64_t)kFLEXCAN_HostOrFlexCanCErrorInterruptEnable +#endif + ); + } + + /* Enable interrupts in NVIC. */ + (void)EnableIRQ((IRQn_Type)(s_flexcanRxWarningIRQ[instance])); + (void)EnableIRQ((IRQn_Type)(s_flexcanTxWarningIRQ[instance])); + (void)EnableIRQ((IRQn_Type)(s_flexcanWakeUpIRQ[instance])); + (void)EnableIRQ((IRQn_Type)(s_flexcanErrorIRQ[instance])); + (void)EnableIRQ((IRQn_Type)(s_flexcanBusOffIRQ[instance])); + (void)EnableIRQ((IRQn_Type)(s_flexcanMbIRQ[instance])); +} + +/*! + * brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param pMbXfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * retval kStatus_Success Start Tx Message Buffer sending process successfully. + * retval kStatus_Fail Write Tx Message Buffer failed. + * retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. + */ +status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer) +{ + /* Assertion. */ + assert(NULL != handle); + assert(NULL != pMbXfer); + assert(pMbXfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, pMbXfer->mbIdx)); +#endif + + status_t status; + + /* Check if Message Buffer is idle. */ + if ((uint8_t)kFLEXCAN_StateIdle == handle->mbState[pMbXfer->mbIdx]) + { + /* Distinguish transmit type. */ + if ((uint32_t)kFLEXCAN_FrameTypeRemote == pMbXfer->frame->type) + { + handle->mbState[pMbXfer->mbIdx] = (uint8_t)kFLEXCAN_StateTxRemote; + } + else + { + handle->mbState[pMbXfer->mbIdx] = (uint8_t)kFLEXCAN_StateTxData; + } + + if (kStatus_Success == + FLEXCAN_WriteTxMb(base, pMbXfer->mbIdx, (const flexcan_frame_t *)(uintptr_t)pMbXfer->frame)) + { + /* Enable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (pMbXfer->mbIdx >= 64U) + { + FLEXCAN_EnableHigh64MbInterrupts(base, (uint64_t)1U << (pMbXfer->mbIdx - 64U)); + } + else + { + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); +#else + FLEXCAN_EnableMbInterrupts(base, (uint32_t)1U << pMbXfer->mbIdx); +#endif + status = kStatus_Success; + } + else + { + handle->mbState[pMbXfer->mbIdx] = (uint8_t)kFLEXCAN_StateIdle; + status = kStatus_Fail; + } + } + else + { + status = kStatus_FLEXCAN_TxBusy; + } + + return status; +} + +/*! + * brief Receives a message using IRQ. + * + * This function receives a message using IRQ. This is non-blocking function, which returns + * right away. When the message has been received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param pMbXfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * retval kStatus_Success - Start Rx Message Buffer receiving process successfully. + * retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. + */ +status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer) +{ + status_t status; + + /* Assertion. */ + assert(NULL != handle); + assert(NULL != pMbXfer); + assert(pMbXfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, pMbXfer->mbIdx)); +#endif + + /* Check if Message Buffer is idle. */ + if ((uint8_t)kFLEXCAN_StateIdle == handle->mbState[pMbXfer->mbIdx]) + { + handle->mbState[pMbXfer->mbIdx] = (uint8_t)kFLEXCAN_StateRxData; + + /* Register Message Buffer. */ + handle->mbFrameBuf[pMbXfer->mbIdx] = pMbXfer->frame; + + /* Enable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (pMbXfer->mbIdx >= 64U) + { + FLEXCAN_EnableHigh64MbInterrupts(base, (uint64_t)1U << (pMbXfer->mbIdx - 64U)); + } + else + { + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); +#else + FLEXCAN_EnableMbInterrupts(base, (uint32_t)1U << pMbXfer->mbIdx); +#endif + + status = kStatus_Success; + } + else + { + status = kStatus_FLEXCAN_RxBusy; + } + + return status; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param pMbXfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * retval kStatus_Success Start Tx Message Buffer sending process successfully. + * retval kStatus_Fail Write Tx Message Buffer failed. + * retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. + */ +status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer) +{ + /* Assertion. */ + assert(NULL != handle); + assert(NULL != pMbXfer); + assert(pMbXfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, pMbXfer->mbIdx)); +#endif + + status_t status; + + /* Check if Message Buffer is idle. */ + if ((uint8_t)kFLEXCAN_StateIdle == handle->mbState[pMbXfer->mbIdx]) + { + /* Distinguish transmit type. */ + if ((uint32_t)kFLEXCAN_FrameTypeRemote == pMbXfer->framefd->type) + { + handle->mbState[pMbXfer->mbIdx] = (uint8_t)kFLEXCAN_StateTxRemote; + } + else + { + handle->mbState[pMbXfer->mbIdx] = (uint8_t)kFLEXCAN_StateTxData; + } + + if (kStatus_Success == + FLEXCAN_WriteFDTxMb(base, pMbXfer->mbIdx, (const flexcan_fd_frame_t *)(uintptr_t)pMbXfer->framefd)) + { + /* Enable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (pMbXfer->mbIdx >= 64U) + { + FLEXCAN_EnableHigh64MbInterrupts(base, (uint64_t)1U << (pMbXfer->mbIdx - 64U)); + } + else + { + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); +#else + FLEXCAN_EnableMbInterrupts(base, (uint32_t)1U << pMbXfer->mbIdx); +#endif + + status = kStatus_Success; + } + else + { + handle->mbState[pMbXfer->mbIdx] = (uint8_t)kFLEXCAN_StateIdle; + status = kStatus_Fail; + } + } + else + { + status = kStatus_FLEXCAN_TxBusy; + } + + return status; +} + +/*! + * brief Receives a message using IRQ. + * + * This function receives a message using IRQ. This is non-blocking function, which returns + * right away. When the message has been received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param pMbXfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * retval kStatus_Success - Start Rx Message Buffer receiving process successfully. + * retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. + */ +status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer) +{ + /* Assertion. */ + assert(NULL != handle); + assert(NULL != pMbXfer); + assert(pMbXfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, pMbXfer->mbIdx)); +#endif + + status_t status; + + /* Check if Message Buffer is idle. */ + if ((uint8_t)kFLEXCAN_StateIdle == handle->mbState[pMbXfer->mbIdx]) + { + handle->mbState[pMbXfer->mbIdx] = (uint8_t)kFLEXCAN_StateRxData; + + /* Register Message Buffer. */ + handle->mbFDFrameBuf[pMbXfer->mbIdx] = pMbXfer->framefd; + + /* Enable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (pMbXfer->mbIdx >= 64U) + { + FLEXCAN_EnableHigh64MbInterrupts(base, (uint64_t)1U << (pMbXfer->mbIdx - 64U)); + } + else + { + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_EnableMbInterrupts(base, (uint64_t)1U << pMbXfer->mbIdx); +#else + FLEXCAN_EnableMbInterrupts(base, (uint32_t)1U << pMbXfer->mbIdx); +#endif + + status = kStatus_Success; + } + else + { + status = kStatus_FLEXCAN_RxBusy; + } + + return status; +} +#endif + +/*! + * brief Receives a message from Legacy Rx FIFO using IRQ. + * + * This function receives a message using IRQ. This is a non-blocking function, which returns + * right away. When all messages have been received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param pFifoXfer FlexCAN Rx FIFO transfer structure. See the ref flexcan_fifo_transfer_t. + * retval kStatus_Success - Start Rx FIFO receiving process successfully. + * retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use. + */ +status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer) +{ + /* Assertion. */ + assert(NULL != handle); + assert(NULL != pFifoXfer); + + status_t status; + uint32_t irqMask = (uint32_t)kFLEXCAN_RxFifoOverflowFlag | (uint32_t)kFLEXCAN_RxFifoWarningFlag; + + /* Check if Message Buffer is idle. */ + if ((uint8_t)kFLEXCAN_StateIdle == handle->rxFifoState) + { + handle->rxFifoState = (uint8_t)kFLEXCAN_StateRxFifo; + + /* Register Message Buffer. */ + handle->rxFifoFrameBuf = pFifoXfer->frame; + handle->rxFifoFrameNum = pFifoXfer->frameNum; + handle->rxFifoTransferTotalNum = pFifoXfer->frameNum; + + if (handle->rxFifoTransferTotalNum < 5U) + { + /* Enable data available interrupt. */ + irqMask |= (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag; + } + + /* Enable Message Buffer Interrupt. */ + FLEXCAN_EnableMbInterrupts(base, irqMask); + + status = kStatus_Success; + } + else + { + status = kStatus_FLEXCAN_RxFifoBusy; + } + + return status; +} + +/*! + * brief Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param count Number of CAN messages receive so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ + +status_t FLEXCAN_TransferGetReceiveFifoCount(CAN_Type *base, flexcan_handle_t *handle, size_t *count) +{ + assert(NULL != handle); + + status_t result = kStatus_Success; + + if (handle->rxFifoState == (uint32_t)kFLEXCAN_StateIdle) + { + result = kStatus_NoTransferInProgress; + } + else + { + *count = handle->rxFifoTransferTotalNum - handle->rxFifoFrameNum; + } + + return result; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * brief Receives a message from Enhanced Rx FIFO using IRQ. + * + * This function receives a message using IRQ. This is a non-blocking function, which returns + * right away. When all messages have been received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param pFifoXfer FlexCAN Rx FIFO transfer structure. See the ref flexcan_fifo_transfer_t. + * retval kStatus_Success - Start Rx FIFO receiving process successfully. + * retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use. + */ +status_t FLEXCAN_TransferReceiveEnhancedFifoNonBlocking(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer) +{ + /* Assertion. */ + assert(NULL != handle); + assert(NULL != pFifoXfer); + + status_t status; + uint32_t watermark = ((base->ERFCR & CAN_ERFCR_ERFWM_MASK) >> CAN_ERFCR_ERFWM_SHIFT) + 1U; + uint64_t irqMask = + (uint64_t)kFLEXCAN_ERxFifoUnderflowInterruptEnable | (uint64_t)kFLEXCAN_ERxFifoOverflowInterruptEnable; + + /* Check if Enhanced Rx FIFO is idle. */ + if ((uint8_t)kFLEXCAN_StateIdle == handle->rxFifoState) + { + handle->rxFifoState = (uint8_t)kFLEXCAN_StateRxFifo; + + /* Register Message Buffer. */ + handle->rxFifoFDFrameBuf = pFifoXfer->framefd; + handle->rxFifoFrameNum = pFifoXfer->frameNum; + handle->rxFifoTransferTotalNum = pFifoXfer->frameNum; + + if (handle->rxFifoTransferTotalNum >= watermark) + { + /* Enable watermark interrupt. */ + irqMask |= (uint64_t)kFLEXCAN_ERxFifoWatermarkInterruptEnable; + } + else + { + /* Enable data available interrupt. */ + irqMask |= (uint64_t)kFLEXCAN_ERxFifoDataAvlInterruptEnable; + } + /* Enable Enhanced Rx FIFO Interrupt. */ + FLEXCAN_EnableInterrupts(base, irqMask); + + status = kStatus_Success; + } + else + { + status = kStatus_FLEXCAN_RxFifoBusy; + } + + return status; +} +#endif + +/*! + * brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN Message Buffer index. + */ +void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) +{ + uint16_t timestamp; + + /* Assertion. */ + assert(NULL != handle); + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + /* Disable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (mbIdx >= 64U) + { + FLEXCAN_DisableHigh64MbInterrupts(base, (uint64_t)1U << (mbIdx - 64U)); + } + else + { + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); +#else + FLEXCAN_DisableMbInterrupts(base, (uint32_t)1U << mbIdx); +#endif + + /* Update the TX frame 's time stamp by MB[mbIdx].cs. */ + timestamp = (uint16_t)((base->MB[mbIdx].CS & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + handle->timestamp[mbIdx] = timestamp; + + /* Clean Message Buffer. */ + FLEXCAN_SetTxMbConfig(base, mbIdx, true); + + handle->mbState[mbIdx] = (uint8_t)kFLEXCAN_StateIdle; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + */ +void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) +{ + volatile uint32_t *mbAddr; + uint32_t offset; + uint16_t timestamp; + + /* Assertion. */ + assert(NULL != handle); + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + /* Disable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (mbIdx >= 64U) + { + FLEXCAN_DisableHigh64MbInterrupts(base, (uint64_t)1U << (mbIdx - 64U)); + } + else + { + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); +#else + FLEXCAN_DisableMbInterrupts(base, (uint32_t)1U << mbIdx); +#endif + + /* Update the TX frame 's time stamp by base->MB[offset for CAN FD].CS. */ + mbAddr = &(base->MB[0].CS); + offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); + timestamp = (uint16_t)((mbAddr[offset] & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + handle->timestamp[mbIdx] = timestamp; + + /* Clean Message Buffer. */ + FLEXCAN_SetFDTxMbConfig(base, mbIdx, true); + + handle->mbState[mbIdx] = (uint8_t)kFLEXCAN_StateIdle; +} + +/*! + * brief Aborts the interrupt driven message receive process. + * + * This function aborts the interrupt driven message receive process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + */ +void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) +{ + /* Assertion. */ + assert(NULL != handle); + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + /* Disable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (mbIdx >= 64U) + { + FLEXCAN_DisableHigh64MbInterrupts(base, (uint64_t)1U << (mbIdx - 64U)); + } + else + { + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); +#else + FLEXCAN_DisableMbInterrupts(base, (uint32_t)1U << mbIdx); +#endif + + /* Un-register handle. */ + handle->mbFDFrameBuf[mbIdx] = NULL; + handle->mbState[mbIdx] = (uint8_t)kFLEXCAN_StateIdle; +} +#endif + +/*! + * brief Aborts the interrupt driven message receive process. + * + * This function aborts the interrupt driven message receive process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN Message Buffer index. + */ +void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) +{ + /* Assertion. */ + assert(NULL != handle); + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + /* Disable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (mbIdx >= 64U) + { + FLEXCAN_DisableHigh64MbInterrupts(base, (uint64_t)1U << (mbIdx - 64U)); + } + else + { + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_DisableMbInterrupts(base, (uint64_t)1U << mbIdx); +#else + FLEXCAN_DisableMbInterrupts(base, (uint32_t)1U << mbIdx); +#endif + + /* Un-register handle. */ + handle->mbFrameBuf[mbIdx] = NULL; + handle->mbState[mbIdx] = (uint8_t)kFLEXCAN_StateIdle; +} + +/*! + * brief Aborts the interrupt driven message receive from Legacy Rx FIFO process. + * + * This function aborts the interrupt driven message receive from Legacy Rx FIFO process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle) +{ + /* Assertion. */ + assert(NULL != handle); + + /* Check if Rx FIFO is enabled. */ + if (0U != (base->MCR & CAN_MCR_RFEN_MASK)) + { + /* Disable Rx Message FIFO Interrupts. */ + FLEXCAN_DisableMbInterrupts(base, (uint32_t)kFLEXCAN_RxFifoOverflowFlag | (uint32_t)kFLEXCAN_RxFifoWarningFlag | + (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag); + + /* Un-register handle. */ + handle->rxFifoFrameBuf = NULL; + /* Clear transfer count. */ + handle->rxFifoFrameNum = 0U; + handle->rxFifoTransferTotalNum = 0U; + } + + handle->rxFifoState = (uint8_t)kFLEXCAN_StateIdle; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * brief Aborts the interrupt driven message receive from Enhanced Rx FIFO process. + * + * This function aborts the interrupt driven message receive from Rx FIFO process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferAbortReceiveEnhancedFifo(CAN_Type *base, flexcan_handle_t *handle) +{ + /* Assertion. */ + assert(NULL != handle); + + /* Check if Enhanced Rx FIFO is enabled. */ + if (0U != (base->ERFCR & CAN_ERFCR_ERFEN_MASK)) + { + /* Disable all Rx Message FIFO interrupts. */ + FLEXCAN_DisableInterrupts(base, (uint64_t)kFLEXCAN_ERxFifoUnderflowInterruptEnable | + (uint64_t)kFLEXCAN_ERxFifoOverflowInterruptEnable | + (uint64_t)kFLEXCAN_ERxFifoWatermarkInterruptEnable | + (uint64_t)kFLEXCAN_ERxFifoDataAvlInterruptEnable); + + /* Un-register handle. */ + handle->rxFifoFDFrameBuf = NULL; + /* Clear transfer count. */ + handle->rxFifoFrameNum = 0U; + handle->rxFifoTransferTotalNum = 0U; + } + + handle->rxFifoState = (uint8_t)kFLEXCAN_StateIdle; +} +#endif + +/*! + * brief Gets the detail index of Mailbox's Timestamp by handle. + * + * Then function can only be used when calling non-blocking Data transfer (TX/RX) API, + * After TX/RX data transfer done (User can get the status by handler's callback function), + * we can get the detail index of Mailbox's timestamp by handle, + * Detail non-blocking data transfer API (TX/RX) contain. + * -FLEXCAN_TransferSendNonBlocking + * -FLEXCAN_TransferFDSendNonBlocking + * -FLEXCAN_TransferReceiveNonBlocking + * -FLEXCAN_TransferFDReceiveNonBlocking + * -FLEXCAN_TransferReceiveFifoNonBlocking + * + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + * return the index of mailbox 's timestamp stored in the handle. + * + */ +uint32_t FLEXCAN_GetTimeStamp(flexcan_handle_t *handle, uint8_t mbIdx) +{ + /* Assertion. */ + assert(NULL != handle); + + return (uint32_t)(handle->timestamp[mbIdx]); +} + +/*! + * brief Check unhandle interrupt events + * + * param base FlexCAN peripheral base address. + * return TRUE if unhandled interrupt action exist, FALSE if no unhandlered interrupt action exist. + */ +static bool FLEXCAN_CheckUnhandleInterruptEvents(CAN_Type *base) +{ + uint64_t tempmask; + uint64_t tempflag; + bool fgRet = false; + + if (0U == (FLEXCAN_GetStatusFlags(base) & + (FLEXCAN_ERROR_AND_STATUS_INIT_FLAG | FLEXCAN_WAKE_UP_FLAG | FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG))) + { + /* If no error, wake_up or enhanced RX FIFO status, Checking whether exist MB interrupt status and legacy RX + * FIFO interrupt status */ + tempmask = (uint64_t)base->IMASK1; + tempflag = (uint64_t)base->IFLAG1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + tempmask |= ((uint64_t)base->IMASK2) << 32; + tempflag |= ((uint64_t)base->IFLAG2) << 32; +#endif + fgRet = (0U != (tempmask & tempflag)); +#if defined(CAN_IMASK3_BUF95TO64M_MASK) + if (0U != (base->IMASK3 & base->IFLAG3)) + { + fgRet = true; + } +#endif +#if defined(CAN_IMASK4_BUF127TO96M_MASK) + if (0U != (base->IMASK4 & base->IFLAG4)) + { + fgRet = true; + } +#endif + } +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + else if (0U != (FLEXCAN_GetStatusFlags(base) & FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG)) + { + /* Checking whether exist enhanced RX FIFO interrupt status. */ + tempmask = (uint64_t)base->ERFIER; + tempflag = (uint64_t)base->ERFSR; + fgRet = (0U != (tempmask & tempflag)); + } +#endif + else + { + /* Exist error or wake up flag. */ + fgRet = true; + } + + return fgRet; +} + +/*! + * brief Sub Handler Legacy Rx FIFO Trasfered Events + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param result The MB flag number. + * + * return the status after handle transfered event. + */ +static status_t FLEXCAN_SubHandlerForLegacyRxFIFO(CAN_Type *base, flexcan_handle_t *handle, uint32_t result) +{ + uint32_t u32mask = 1; + status_t status = kStatus_FLEXCAN_UnHandled; + + switch (u32mask << result) + { + case kFLEXCAN_RxFifoOverflowFlag: + status = kStatus_FLEXCAN_RxFifoOverflow; + break; + + case kFLEXCAN_RxFifoWarningFlag: + if ((handle->rxFifoFrameNum > 5U) && (0U != (base->IFLAG1 & (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag))) + { + for (uint32_t i = 0; i < 5UL; i++) + { + status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); + /* + * $Branch Coverage Justification$ + * (kStatus_Success != status) not covered. $ref flexcan_c_ref_1$. + */ + if (kStatus_Success == status) + { + /* Align the current rxfifo timestamp to the timestamp array by handle. */ + handle->timestamp[i] = handle->rxFifoFrameBuf->timestamp; + handle->rxFifoFrameBuf++; + handle->rxFifoFrameNum--; + /* Clean Rx Fifo available flag to discard the frame that has been read. */ + FLEXCAN_ClearMbStatusFlags(base, (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag); + } + else + { + /* + * $Line Coverage Justification$ + * $ref flexcan_c_ref_1$. + */ + return kStatus_FLEXCAN_RxFifoDisabled; + } + } + if (handle->rxFifoFrameNum < 5UL) + { + /* Enable data avaliable interrupt. */ + FLEXCAN_EnableMbInterrupts(base, (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag); + } + status = kStatus_FLEXCAN_RxFifoBusy; + } + else + { + /* Should enter case kFLEXCAN_RxFifoFrameAvlFlag but not, means previous transfer may have + * overflow*/ + status = kStatus_FLEXCAN_RxFifoWarning; + } + break; + + case kFLEXCAN_RxFifoFrameAvlFlag: + /* Whether still has CAN messages remaining to be received. */ + if (handle->rxFifoFrameNum > 0U) + { + status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); + /* + * $Branch Coverage Justification$ + * (kStatus_Success != status) not covered. $ref flexcan_c_ref_1$. + */ + if (kStatus_Success == status) + { + /* Align the current (index 0) rxfifo timestamp to the timestamp array by handle. */ + handle->timestamp[0] = handle->rxFifoFrameBuf->timestamp; + handle->rxFifoFrameBuf++; + handle->rxFifoFrameNum--; + } + else + { + /* + * $Line Coverage Justification$ + * $ref flexcan_c_ref_1$. + */ + return kStatus_FLEXCAN_RxFifoDisabled; + } + } + if (handle->rxFifoFrameNum == 0U) + { + /* Stop receiving Ehanced Rx FIFO when the transmission is over. */ + FLEXCAN_TransferAbortReceiveFifo(base, handle); + status = kStatus_FLEXCAN_RxFifoIdle; + } + else + { + /* Continue use data avaliable interrupt. */ + status = kStatus_FLEXCAN_RxFifoBusy; + } + break; + + default: + status = kStatus_FLEXCAN_UnHandled; + break; + } + + return status; +} + +/*! + * brief Sub Handler Message Buffer Trasfered Events + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param result The MB flag number. + * + * return the status after handle transfered event. + */ +static status_t FLEXCAN_SubHandlerForMB(CAN_Type *base, flexcan_handle_t *handle, uint32_t result) +{ + status_t status = kStatus_FLEXCAN_UnHandled; + + /* Get current State of Message Buffer. */ + switch (handle->mbState[result]) + { + /* Solve Rx Data Frame. */ + case (uint8_t)kFLEXCAN_StateRxData: +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) + { + status = FLEXCAN_ReadFDRxMb(base, (uint8_t)result, handle->mbFDFrameBuf[result]); + if ((kStatus_Success == status) || (kStatus_FLEXCAN_RxOverflow == status)) + { + /* Align the current index of RX MB timestamp to the timestamp array by handle. */ + handle->timestamp[result] = handle->mbFDFrameBuf[result]->timestamp; + + if (kStatus_Success == status) + { + status = kStatus_FLEXCAN_RxIdle; + } + } + } + else +#endif + { + status = FLEXCAN_ReadRxMb(base, (uint8_t)result, handle->mbFrameBuf[result]); + if ((kStatus_Success == status) || (kStatus_FLEXCAN_RxOverflow == status)) + { + /* Align the current index of RX MB timestamp to the timestamp array by handle. */ + handle->timestamp[result] = handle->mbFrameBuf[result]->timestamp; + + if (kStatus_Success == status) + { + status = kStatus_FLEXCAN_RxIdle; + } + } + } +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) + { + FLEXCAN_TransferFDAbortReceive(base, handle, (uint8_t)result); + } + else +#endif + { + FLEXCAN_TransferAbortReceive(base, handle, (uint8_t)result); + } + break; + + /* Sove Rx Remote Frame. User need to Read the frame in Mail box in time by Read from MB API. */ + case (uint8_t)kFLEXCAN_StateRxRemote: + status = kStatus_FLEXCAN_RxRemote; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) + { + FLEXCAN_TransferFDAbortReceive(base, handle, (uint8_t)result); + } + else +#endif + { + FLEXCAN_TransferAbortReceive(base, handle, (uint8_t)result); + } + break; + + /* Solve Tx Data Frame. */ + case (uint8_t)kFLEXCAN_StateTxData: + status = kStatus_FLEXCAN_TxIdle; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) + { + FLEXCAN_TransferFDAbortSend(base, handle, (uint8_t)result); + } + else +#endif + { + FLEXCAN_TransferAbortSend(base, handle, (uint8_t)result); + } + break; + + /* Solve Tx Remote Frame. */ + case (uint8_t)kFLEXCAN_StateTxRemote: + handle->mbState[result] = (uint8_t)kFLEXCAN_StateRxRemote; + status = kStatus_FLEXCAN_TxSwitchToRx; + break; + + default: + status = kStatus_FLEXCAN_UnHandled; + break; + } + + return status; +} + +/*! + * brief Sub Handler Data Trasfered Events + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param pResult Pointer to the Handle result. + * + * return the status after handle each data transfered event. + */ +static status_t FLEXCAN_SubHandlerForDataTransfered(CAN_Type *base, flexcan_handle_t *handle, uint32_t *pResult) +{ + status_t status = kStatus_FLEXCAN_UnHandled; + uint32_t result = 0xFFU; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint32_t intflag[4] = {(base->IMASK1 & base->IFLAG1), (base->IMASK2 & base->IFLAG2), 0U, 0U}; +#if defined(CAN_IMASK3_BUF95TO64M_MASK) + intflag[2] = base->IMASK3 & base->IFLAG3; +#endif +#if defined(CAN_IMASK4_BUF127TO96M_MASK) + intflag[3] = base->IMASK4 & base->IFLAG4; +#endif +#else + uint32_t intflag = base->IMASK1 & base->IFLAG1; +#endif + + /* For this implementation, we solve the Message with lowest MB index first. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + for (uint32_t i = 0U; i < 4U; i++) + { + if (intflag[i] != 0U) + { + for (uint32_t j = 0U; j < 32U; j++) + { + if (0UL != (intflag[i] & ((uint32_t)1UL << j))) + { + result = i * 32U + j; + break; + } + } + break; + } + } +#else + for (result = 0U; result < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); result++) + { + if (0UL != (intflag & ((uint32_t)1UL << result))) + { + break; + } + } +#endif + + /* find Message to deal with. */ + if (result < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)) + { + /* Solve Legacy Rx FIFO interrupt. */ + if (((uint8_t)kFLEXCAN_StateIdle != handle->rxFifoState) && (result <= (uint32_t)CAN_IFLAG1_BUF7I_SHIFT) && + ((base->MCR & CAN_MCR_RFEN_MASK) != 0U)) + { + status = FLEXCAN_SubHandlerForLegacyRxFIFO(base, handle, result); + /* + * $Branch Coverage Justification$ + * (status == kStatus_FLEXCAN_RxFifoDisabled) not covered. $ref flexcan_c_ref_1$. + */ + if (status == kStatus_FLEXCAN_RxFifoDisabled) + { + /* + * $Line Coverage Justification$ + * $ref flexcan_c_ref_1$. + */ + return status; + } + } + else + { + status = FLEXCAN_SubHandlerForMB(base, handle, result); + } + + /* Clear resolved Message Buffer IRQ. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) + if (result >= 64U) + { + FLEXCAN_ClearHigh64MbStatusFlags(base, (uint64_t)1U << (result - 64U)); + } + else + { + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << result); + } +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_ClearMbStatusFlags(base, (uint64_t)1U << result); +#else + FLEXCAN_ClearMbStatusFlags(base, (uint32_t)1U << result); +#endif + } + + *pResult = result; + + return status; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * brief Sub Handler Ehanced Rx FIFO event + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param flags FlexCAN interrupt flags. + * + * return the status after handle Ehanced Rx FIFO event. + */ +static status_t FLEXCAN_SubHandlerForEhancedRxFifo(CAN_Type *base, flexcan_handle_t *handle, uint64_t flags) +{ + uint32_t watermark = ((base->ERFCR & CAN_ERFCR_ERFWM_MASK) >> CAN_ERFCR_ERFWM_SHIFT) + 1U; + uint32_t transferFrames; + + status_t status; + /* Solve Ehanced Rx FIFO interrupt. */ + if ((0u != (flags & (uint64_t)kFLEXCAN_ERxFifoUnderflowIntFlag)) && + (0u != (base->ERFIER & CAN_ERFIER_ERFUFWIE_MASK))) + { + status = kStatus_FLEXCAN_RxFifoUnderflow; + FLEXCAN_ClearStatusFlags(base, (uint64_t)kFLEXCAN_ERxFifoUnderflowIntFlag); + } + else if ((0u != (flags & (uint64_t)kFLEXCAN_ERxFifoOverflowIntFlag)) && + (0u != (base->ERFIER & CAN_ERFIER_ERFOVFIE_MASK))) + { + status = kStatus_FLEXCAN_RxFifoOverflow; + FLEXCAN_ClearStatusFlags(base, (uint64_t)kFLEXCAN_ERxFifoOverflowIntFlag); + } + else if ((0u != (flags & (uint64_t)kFLEXCAN_ERxFifoWatermarkIntFlag)) && + (0u != (base->ERFIER & CAN_ERFIER_ERFWMIIE_MASK))) + { + /* Whether the number of CAN messages remaining to be received is greater than the watermark. */ + transferFrames = (handle->rxFifoFrameNum > watermark) ? watermark : handle->rxFifoFrameNum; + + for (uint32_t i = 0; i < transferFrames; i++) + { + status = FLEXCAN_ReadEnhancedRxFifo(base, handle->rxFifoFDFrameBuf); + + if (kStatus_Success == status) + { + handle->rxFifoFDFrameBuf++; + handle->rxFifoFrameNum--; + /* Clear data Watermark flag due to has read back one frame. */ + base->ERFSR = CAN_ERFSR_ERFWMI_MASK; + } + else + { + return kStatus_FLEXCAN_RxFifoDisabled; + } + } + if (handle->rxFifoFrameNum == 0U) + { + /* Stop receiving Ehanced Rx FIFO when the transmission is over. */ + FLEXCAN_TransferAbortReceiveEnhancedFifo(base, handle); + status = kStatus_FLEXCAN_RxFifoIdle; + } + else if (handle->rxFifoFrameNum < watermark) + { + /* Disable watermark interrupt and enable data avaliable interrupt. */ + FLEXCAN_DisableInterrupts(base, (uint64_t)kFLEXCAN_ERxFifoWatermarkInterruptEnable); + FLEXCAN_EnableInterrupts(base, (uint64_t)kFLEXCAN_ERxFifoDataAvlInterruptEnable); + status = kStatus_FLEXCAN_RxFifoBusy; + } + else + { + /* Continue use watermark interrupt. */ + status = kStatus_FLEXCAN_RxFifoBusy; + } + } + else + { + /* Data available status, check Whether still has CAN messages remaining to be received. */ + if (handle->rxFifoFrameNum > 0U) + { + status = FLEXCAN_ReadEnhancedRxFifo(base, handle->rxFifoFDFrameBuf); + + if (kStatus_Success == status) + { + handle->rxFifoFDFrameBuf++; + handle->rxFifoFrameNum--; + } + else + { + return kStatus_FLEXCAN_RxFifoDisabled; + } + } + if (handle->rxFifoFrameNum == 0U) + { + /* Stop receiving Ehanced Rx FIFO when the transmission is over. */ + FLEXCAN_TransferAbortReceiveEnhancedFifo(base, handle); + status = kStatus_FLEXCAN_RxFifoIdle; + } + else + { + /* Continue use data avaliable interrupt. */ + status = kStatus_FLEXCAN_RxFifoBusy; + } + } + return status; +} +#endif + +/*! + * brief FlexCAN IRQ handle function. + * + * This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) +{ + /* Assertion. */ + assert(NULL != handle); + + status_t status; + uint32_t mbNum = 0xFFU; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + uint64_t result = 0U; +#else + uint32_t result = 0U; +#endif + do + { + /* Get Current FlexCAN Module Error and Status. */ + result = FLEXCAN_GetStatusFlags(base); + + /* To handle FlexCAN Error and Status Interrupt first. */ + if (0U != (result & FLEXCAN_ERROR_AND_STATUS_INIT_FLAG)) + { + status = kStatus_FLEXCAN_ErrorStatus; + /* Clear FlexCAN Error and Status Interrupt. */ + FLEXCAN_ClearStatusFlags(base, FLEXCAN_ERROR_AND_STATUS_INIT_FLAG); + } + else if (0U != (result & FLEXCAN_WAKE_UP_FLAG)) + { + status = kStatus_FLEXCAN_WakeUp; + FLEXCAN_ClearStatusFlags(base, FLEXCAN_WAKE_UP_FLAG); + } +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + else if (0U != (FLEXCAN_EFIFO_STATUS_UNMASK(result & FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG) & base->ERFIER)) + { + status = FLEXCAN_SubHandlerForEhancedRxFifo(base, handle, result); + } +#endif + else + { + /* To handle Message Buffer or Legacy Rx FIFO transfer. */ + status = FLEXCAN_SubHandlerForDataTransfered(base, handle, &mbNum); + result = mbNum; + } + + /* Calling Callback Function if has one. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, status, result, handle->userData); + } + } while (FLEXCAN_CheckUnhandleInterruptEvents(base)); +} + +#if defined(CAN0) +void CAN0_DriverIRQHandler(void); +void CAN0_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[0]); + + s_flexcanIsr(CAN0, s_flexcanHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CAN1) +void CAN1_DriverIRQHandler(void); +void CAN1_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[1]); + + s_flexcanIsr(CAN1, s_flexcanHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CAN2) +void CAN2_DriverIRQHandler(void); +void CAN2_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[2]); + + s_flexcanIsr(CAN2, s_flexcanHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CAN3) +void CAN3_DriverIRQHandler(void); +void CAN3_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[3]); + + s_flexcanIsr(CAN3, s_flexcanHandle[3]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CAN4) +void CAN4_DriverIRQHandler(void); +void CAN4_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[4]); + + s_flexcanIsr(CAN4, s_flexcanHandle[4]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__CAN0) +void DMA_FLEXCAN0_INT_DriverIRQHandler(void); +void DMA_FLEXCAN0_INT_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN0)]); + + s_flexcanIsr(DMA__CAN0, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN0)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__CAN1) +void DMA_FLEXCAN1_INT_DriverIRQHandler(void); +void DMA_FLEXCAN1_INT_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN1)]); + + s_flexcanIsr(DMA__CAN1, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN1)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__CAN2) +void DMA_FLEXCAN2_INT_DriverIRQHandler(void); +void DMA_FLEXCAN2_INT_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN2)]); + + s_flexcanIsr(DMA__CAN2, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN2)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__CAN0) +void ADMA_FLEXCAN0_INT_DriverIRQHandler(void); +void ADMA_FLEXCAN0_INT_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN0)]); + + s_flexcanIsr(ADMA__CAN0, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN0)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__CAN1) +void ADMA_FLEXCAN1_INT_DriverIRQHandler(void); +void ADMA_FLEXCAN1_INT_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN1)]); + + s_flexcanIsr(ADMA__CAN1, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN1)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__CAN2) +void ADMA_FLEXCAN2_INT_DriverIRQHandler(void); +void ADMA_FLEXCAN2_INT_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN2)]); + + s_flexcanIsr(ADMA__CAN2, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN2)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCAN1) +void CAN_FD1_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[1]); + + s_flexcanIsr(FLEXCAN1, s_flexcanHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCAN2) +void CAN_FD2_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[2]); + + s_flexcanIsr(FLEXCAN2, s_flexcanHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexcan.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexcan.h new file mode 100644 index 00000000000..9170938afe5 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexcan.h @@ -0,0 +1,2360 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_FLEXCAN_H_ +#define FSL_FLEXCAN_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexcan_driver + * @{ + */ + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief FlexCAN driver version. */ +#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 11, 6)) +/*! @} */ + +#if !(defined(FLEXCAN_WAIT_TIMEOUT) && FLEXCAN_WAIT_TIMEOUT) +/* Define to 1000 means keep waiting 1000 times until the flag is assert/deassert. */ +#define FLEXCAN_WAIT_TIMEOUT (1000U) +#endif + +/*! @brief FlexCAN frame length helper macro. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +#define DLC_LENGTH_DECODE(dlc) (((dlc) <= 8U) ? (dlc) : (((dlc) <= 12U) ? (((dlc)-6U) * 4U) : (((dlc)-11U) * 16U))) +#endif + +/*! @brief FlexCAN Frame ID helper macro. */ +#define FLEXCAN_ID_STD(id) \ + (((uint32_t)(((uint32_t)(id)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) /*!< Standard Frame ID helper macro. */ +#define FLEXCAN_ID_EXT(id) \ + (((uint32_t)(((uint32_t)(id)) << CAN_ID_EXT_SHIFT)) & \ + (CAN_ID_EXT_MASK | CAN_ID_STD_MASK)) /*!< Extend Frame ID helper macro. */ + +/*! @brief FlexCAN Rx Message Buffer Mask helper macro. */ +#define FLEXCAN_RX_MB_STD_MASK(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + FLEXCAN_ID_STD(id)) /*!< Standard Rx Message Buffer Mask helper macro. */ +#define FLEXCAN_RX_MB_EXT_MASK(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + FLEXCAN_ID_EXT(id)) /*!< Extend Rx Message Buffer Mask helper macro. */ + +/*! @brief FlexCAN Legacy Rx FIFO Mask helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + (FLEXCAN_ID_STD(id) << 1)) /*!< Standard Rx FIFO Mask helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + (((uint32_t)(id)&0x7FF) << 19)) /*!< Standard Rx FIFO Mask helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ + (((uint32_t)(id)&0x7FF) << 3)) /*!< Standard Rx FIFO Mask helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(id) \ + (((uint32_t)(id)&0x7F8) << 21) /*!< Standard Rx FIFO Mask helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id) \ + (((uint32_t)(id)&0x7F8) << 13) /*!< Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(id) \ + (((uint32_t)(id)&0x7F8) << 5) /*!< Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) \ + (((uint32_t)(id)&0x7F8) >> 3) /*!< Standard Rx FIFO Mask helper macro Type C lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + (FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide) \ + ( \ + ((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) \ + << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ + ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) >> \ + 15)) /*!< Extend Rx FIFO Mask helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) << 3) /*!< Extend Rx FIFO Mask helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> \ + 5) /*!< Extend Rx FIFO Mask helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> \ + 13) /*!< Extend Rx FIFO Mask helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> 21) /*!< Extend Rx FIFO Mask helper macro Type C lower part helper macro. */ + +/*! @brief FlexCAN Rx FIFO Filter helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(id, rtr, ide) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_HIGH(id, rtr, ide) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH( \ + id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_LOW(id, rtr, ide) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW( \ + id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_HIGH(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_HIGH(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH( \ + id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW( \ + id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH( \ + id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH( \ + id) /*!< Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_LOW(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW( \ + id) /*!< Extend Rx FIFO Filter helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_LOW(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id) /*!< Extend Rx FIFO Filter helper macro Type C lower part helper macro. */ + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! @brief FlexCAN Enhanced Rx FIFO Filter and Mask helper macro. */ +#define ENHANCED_RX_FIFO_FSCH(x) (((uint32_t)(((uint32_t)(x)) << 30)) & 0xC0000000U) +#define RTR_STD_HIGH(x) (((uint32_t)(((uint32_t)(x)) << 27)) & 0x08000000U) +#define RTR_STD_LOW(x) (((uint32_t)(((uint32_t)(x)) << 11)) & 0x00000800U) +#define RTR_EXT(x) (((uint32_t)(((uint32_t)(x)) << 29)) & 0x40000000U) +#define ID_STD_LOW(id) (((uint32_t)id) & 0x7FFU) +#define ID_STD_HIGH(id) (((uint32_t)(((uint32_t)(id)) << 16)) & 0x07FF0000U) +#define ID_EXT(id) (((uint32_t)id) & 0x1FFFFFFFU) + +/*! Standard ID filter element with filter + mask scheme. */ +#define FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(id, rtr, id_mask, rtr_mask) \ + (ENHANCED_RX_FIFO_FSCH(0x0) | RTR_STD_HIGH(rtr) | ID_STD_HIGH(id) | RTR_STD_LOW(rtr_mask) | ID_STD_LOW(id_mask)) +/*! Standard ID filter element with filter range. */ +#define FLEXCAN_ENHANCED_RX_FIFO_STD_FILTER_WITH_RANGE(id_upper, rtr, id_lower, rtr_mask) \ + (ENHANCED_RX_FIFO_FSCH(0x1) | RTR_STD_HIGH(rtr) | ID_STD_HIGH(id_upper) | RTR_STD_LOW(rtr_mask) | \ + ID_STD_LOW(id_lower)) +/*! Standard ID filter element with two filters without masks. */ +#define FLEXCAN_ENHANCED_RX_FIFO_STD_TWO_FILTERS(id1, rtr1, id2, rtr2) \ + (ENHANCED_RX_FIFO_FSCH(0x2) | RTR_STD_HIGH(rtr1) | ID_STD_HIGH(id1) | RTR_STD_LOW(rtr2) | ID_STD_LOW(id2)) +/*! Extended ID filter element with filter + mask scheme low word. */ +#define FLEXCAN_ENHANCED_RX_FIFO_EXT_MASK_AND_FILTER_LOW(id, rtr) \ + (ENHANCED_RX_FIFO_FSCH(0x0) | RTR_EXT(rtr) | ID_EXT(id)) +/*! Extended ID filter element with filter + mask scheme high word. */ +#define FLEXCAN_ENHANCED_RX_FIFO_EXT_MASK_AND_FILTER_HIGH(id_mask, rtr_mask) \ + (ENHANCED_RX_FIFO_FSCH(0x0) | RTR_EXT(rtr_mask) | ID_EXT(id_mask)) +/*! Extended ID filter element with range scheme low word. */ +#define FLEXCAN_ENHANCED_RX_FIFO_EXT_FILTER_WITH_RANGE_LOW(id_upper, rtr) \ + (ENHANCED_RX_FIFO_FSCH(0x1) | RTR_EXT(rtr) | ID_EXT(id_upper)) +/*! Extended ID filter element with range scheme high word. */ +#define FLEXCAN_ENHANCED_RX_FIFO_EXT_FILTER_WITH_RANGE_HIGH(id_lower, rtr_mask) \ + (ENHANCED_RX_FIFO_FSCH(0x1) | RTR_EXT(rtr_mask) | ID_EXT(id_lower)) +/*! Extended ID filter element with two filters without masks low word. */ +#define FLEXCAN_ENHANCED_RX_FIFO_EXT_TWO_FILTERS_LOW(id2, rtr2) \ + (ENHANCED_RX_FIFO_FSCH(0x2) | RTR_EXT(rtr2) | ID_EXT(id2)) +/*! Extended ID filter element with two filters without masks high word. */ +#define FLEXCAN_ENHANCED_RX_FIFO_EXT_TWO_FILTERS_HIGH(id1, rtr1) \ + (ENHANCED_RX_FIFO_FSCH(0x2) | RTR_EXT(rtr1) | ID_EXT(id1)) +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) +/*! @brief FlexCAN Pretended Networking ID Mask helper macro. */ +#define FLEXCAN_PN_STD_MASK(id, rtr) \ + ((uint32_t)((uint32_t)(rtr) << CAN_FLT_ID1_FLT_RTR_SHIFT) | \ + FLEXCAN_ID_STD(id)) /*!< Standard Rx Message Buffer Mask helper macro. */ +#define FLEXCAN_PN_EXT_MASK(id, rtr) \ + ((uint32_t)CAN_FLT_ID1_FLT_IDE_MASK | (uint32_t)((uint32_t)(rtr) << CAN_FLT_ID1_FLT_RTR_SHIFT) | \ + FLEXCAN_ID_EXT(id)) /*!< Extend Rx Message Buffer Mask helper macro. */ +#endif + +/*! @brief FlexCAN interrupt/status flag helper macro. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) +#define FLEXCAN_PN_INT_MASK(x) (((uint64_t)(((uint64_t)(x)) << 32)) & 0x3000000000000U) +#define FLEXCAN_PN_INT_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 32)) & 0x00030000U) +#define FLEXCAN_PN_STATUS_MASK(x) (((uint64_t)(((uint64_t)(x)) << 16)) & 0x300000000U) +#define FLEXCAN_PN_STATUS_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 16)) & 0x00030000U) +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +#define FLEXCAN_EFIFO_INT_MASK(x) (((uint64_t)(((uint64_t)(x)) << 32)) & 0xF000000000000000U) +#define FLEXCAN_EFIFO_INT_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 32)) & 0xF0000000U) +#define FLEXCAN_EFIFO_STATUS_MASK(x) (((uint64_t)(((uint64_t)(x)) << 32)) & 0xF003000000000000U) +#define FLEXCAN_EFIFO_STATUS_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 32)) & 0xF0030000U) +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +#define FLEXCAN_MECR_INT_MASK(x) (((uint64_t)(((uint64_t)(x)) << 16)) & 0xD00000000U) +#define FLEXCAN_MECR_INT_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 16)) & 0x000D0000U) +#define FLEXCAN_MECR_STATUS_MASK(x) (((uint64_t)(((uint64_t)(x)) << 34)) & 0x34003400000000U) +#define FLEXCAN_MECR_STATUS_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 34)) & 0x000D000DU) +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +#define FLEXCAN_ERROR_AND_STATUS_INIT_FLAG \ + ((uint32_t)kFLEXCAN_ErrorOverrunFlag | (uint32_t)kFLEXCAN_FDErrorIntFlag | (uint32_t)kFLEXCAN_BusoffDoneIntFlag | \ + (uint32_t)kFLEXCAN_TxWarningIntFlag | (uint32_t)kFLEXCAN_RxWarningIntFlag | (uint32_t)kFLEXCAN_BusOffIntFlag | \ + (uint32_t)kFLEXCAN_ErrorIntFlag | FLEXCAN_MEMORY_ERROR_INIT_FLAG) +#else +#define FLEXCAN_ERROR_AND_STATUS_INIT_FLAG \ + ((uint32_t)kFLEXCAN_TxWarningIntFlag | (uint32_t)kFLEXCAN_RxWarningIntFlag | (uint32_t)kFLEXCAN_BusOffIntFlag | \ + (uint32_t)kFLEXCAN_ErrorIntFlag | FLEXCAN_MEMORY_ERROR_INIT_FLAG) +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) +#define FLEXCAN_WAKE_UP_FLAG \ + ((uint32_t)kFLEXCAN_WakeUpIntFlag | (uint64_t)kFLEXCAN_PNMatchIntFlag | (uint64_t)kFLEXCAN_PNTimeoutIntFlag) +#else +#define FLEXCAN_WAKE_UP_FLAG ((uint32_t)kFLEXCAN_WakeUpIntFlag) +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +#define FLEXCAN_MEMORY_ERROR_INIT_FLAG ((uint64_t)kFLEXCAN_AllMemoryErrorFlag) +#else +#define FLEXCAN_MEMORY_ERROR_INIT_FLAG (0U) +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +#define FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG \ + ((uint64_t)kFLEXCAN_ERxFifoUnderflowIntFlag | (uint64_t)kFLEXCAN_ERxFifoOverflowIntFlag | \ + (uint64_t)kFLEXCAN_ERxFifoWatermarkIntFlag | (uint64_t)kFLEXCAN_ERxFifoDataAvlIntFlag) +#endif +/*! @brief FlexCAN Enhanced Rx FIFO base address helper macro. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +#define E_RX_FIFO(base) ((uintptr_t)(base) + 0x2000U) +#else +#define FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG (0U) +#endif +/*! @brief FlexCAN transfer status. */ +enum +{ + kStatus_FLEXCAN_TxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 0), /*!< Tx Message Buffer is Busy. */ + kStatus_FLEXCAN_TxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 1), /*!< Tx Message Buffer is Idle. */ + kStatus_FLEXCAN_TxSwitchToRx = MAKE_STATUS( + kStatusGroup_FLEXCAN, 2), /*!< Remote Message is send out and Message buffer changed to Receive one. */ + kStatus_FLEXCAN_RxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 3), /*!< Rx Message Buffer is Busy. */ + kStatus_FLEXCAN_RxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 4), /*!< Rx Message Buffer is Idle. */ + kStatus_FLEXCAN_RxOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 5), /*!< Rx Message Buffer is Overflowed. */ + kStatus_FLEXCAN_RxFifoBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 6), /*!< Rx Message FIFO is Busy. */ + kStatus_FLEXCAN_RxFifoIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 7), /*!< Rx Message FIFO is Idle. */ + kStatus_FLEXCAN_RxFifoOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 8), /*!< Rx Message FIFO is overflowed. */ + kStatus_FLEXCAN_RxFifoWarning = MAKE_STATUS(kStatusGroup_FLEXCAN, 9), /*!< Rx Message FIFO is almost overflowed. */ + kStatus_FLEXCAN_RxFifoDisabled = + MAKE_STATUS(kStatusGroup_FLEXCAN, 10), /*!< Rx Message FIFO is disabled during reading. */ + kStatus_FLEXCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_FLEXCAN, 11), /*!< FlexCAN Module Error and Status. */ + kStatus_FLEXCAN_WakeUp = MAKE_STATUS(kStatusGroup_FLEXCAN, 12), /*!< FlexCAN is waken up from STOP mode. */ + kStatus_FLEXCAN_UnHandled = MAKE_STATUS(kStatusGroup_FLEXCAN, 13), /*!< UnHadled Interrupt asserted. */ + kStatus_FLEXCAN_RxRemote = MAKE_STATUS(kStatusGroup_FLEXCAN, 14), /*!< Rx Remote Message Received in Mail box. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + kStatus_FLEXCAN_RxFifoUnderflow = + MAKE_STATUS(kStatusGroup_FLEXCAN, 15), /*!< Enhanced Rx Message FIFO is underflow. */ +#endif +}; + +/*! @brief FlexCAN frame format. */ +typedef enum _flexcan_frame_format +{ + kFLEXCAN_FrameFormatStandard = 0x0U, /*!< Standard frame format attribute. */ + kFLEXCAN_FrameFormatExtend = 0x1U, /*!< Extend frame format attribute. */ +} flexcan_frame_format_t; + +/*! @brief FlexCAN frame type. */ +typedef enum _flexcan_frame_type +{ + kFLEXCAN_FrameTypeData = 0x0U, /*!< Data frame type attribute. */ + kFLEXCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */ +} flexcan_frame_type_t; + +/*! @brief FlexCAN clock source. + * @deprecated Do not use the kFLEXCAN_ClkSrcOs. It has been superceded kFLEXCAN_ClkSrc0 + * @deprecated Do not use the kFLEXCAN_ClkSrcPeri. It has been superceded kFLEXCAN_ClkSrc1 + */ +typedef enum _flexcan_clock_source +{ + kFLEXCAN_ClkSrcOsc = 0x0U, /*!< FlexCAN Protocol Engine clock from Oscillator. */ + kFLEXCAN_ClkSrcPeri = 0x1U, /*!< FlexCAN Protocol Engine clock from Peripheral Clock. */ + kFLEXCAN_ClkSrc0 = 0x0U, /*!< FlexCAN Protocol Engine clock selected by user as SRC == 0. */ + kFLEXCAN_ClkSrc1 = 0x1U, /*!< FlexCAN Protocol Engine clock selected by user as SRC == 1. */ +} flexcan_clock_source_t; + +/*! @brief FlexCAN wake up source. */ +typedef enum _flexcan_wake_up_source +{ + kFLEXCAN_WakeupSrcUnfiltered = 0x0U, /*!< FlexCAN uses unfiltered Rx input to detect edge. */ + kFLEXCAN_WakeupSrcFiltered = 0x1U, /*!< FlexCAN uses filtered Rx input to detect edge. */ +} flexcan_wake_up_source_t; + +/*! @brief FlexCAN Rx Fifo Filter type. */ +typedef enum _flexcan_rx_fifo_filter_type +{ + kFLEXCAN_RxFifoFilterTypeA = 0x0U, /*!< One full ID (standard and extended) per ID Filter element. */ + kFLEXCAN_RxFifoFilterTypeB = + 0x1U, /*!< Two full standard IDs or two partial 14-bit ID slices per ID Filter Table element. */ + kFLEXCAN_RxFifoFilterTypeC = + 0x2U, /*!< Four partial 8-bit Standard or extended ID slices per ID Filter Table element. */ + kFLEXCAN_RxFifoFilterTypeD = 0x3U, /*!< All frames rejected. */ +} flexcan_rx_fifo_filter_type_t; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief FlexCAN Message Buffer Payload size. + */ +typedef enum _flexcan_mb_size +{ + kFLEXCAN_8BperMB = 0x0U, /*!< Selects 8 bytes per Message Buffer. */ + kFLEXCAN_16BperMB = 0x1U, /*!< Selects 16 bytes per Message Buffer. */ + kFLEXCAN_32BperMB = 0x2U, /*!< Selects 32 bytes per Message Buffer. */ + kFLEXCAN_64BperMB = 0x3U, /*!< Selects 64 bytes per Message Buffer. */ +} flexcan_mb_size_t; + +/*! + * @brief FlexCAN CAN FD frame supporting data length (available DLC values). + * + * For Tx, when the Data size corresponding to DLC value stored in the MB selected for transmission is larger than the + * MB Payload size, FlexCAN adds the necessary number of bytes with constant 0xCC pattern to complete the expected DLC. + * For Rx, when the Data size corresponding to DLC value received from the CAN bus is larger than the MB Payload size, + * the high order bytes that do not fit the Payload size will lose. + */ +enum _flexcan_fd_frame_length +{ + kFLEXCAN_0BperFrame = 0x0U, /*!< Frame contains 0 valid data bytes. */ + kFLEXCAN_1BperFrame, /*!< Frame contains 1 valid data bytes. */ + kFLEXCAN_2BperFrame, /*!< Frame contains 2 valid data bytes. */ + kFLEXCAN_3BperFrame, /*!< Frame contains 3 valid data bytes. */ + kFLEXCAN_4BperFrame, /*!< Frame contains 4 valid data bytes. */ + kFLEXCAN_5BperFrame, /*!< Frame contains 5 valid data bytes. */ + kFLEXCAN_6BperFrame, /*!< Frame contains 6 valid data bytes. */ + kFLEXCAN_7BperFrame, /*!< Frame contains 7 valid data bytes. */ + kFLEXCAN_8BperFrame, /*!< Frame contains 8 valid data bytes. */ + kFLEXCAN_12BperFrame, /*!< Frame contains 12 valid data bytes. */ + kFLEXCAN_16BperFrame, /*!< Frame contains 16 valid data bytes. */ + kFLEXCAN_20BperFrame, /*!< Frame contains 20 valid data bytes. */ + kFLEXCAN_24BperFrame, /*!< Frame contains 24 valid data bytes. */ + kFLEXCAN_32BperFrame, /*!< Frame contains 32 valid data bytes. */ + kFLEXCAN_48BperFrame, /*!< Frame contains 48 valid data bytes. */ + kFLEXCAN_64BperFrame, /*!< Frame contains 64 valid data bytes. */ +}; +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! @brief FlexCAN Enhanced Rx Fifo DMA transfer per read length enumerations. */ +typedef enum _flexcan_efifo_dma_per_read_length +{ + kFLEXCAN_1WordPerRead = 0x0U, /*!< Transfer 1 32-bit words (CS).*/ + kFLEXCAN_2WordPerRead, /*!< Transfer 2 32-bit words (CS + ID).*/ + kFLEXCAN_3WordPerRead, /*!< Transfer 3 32-bit words (CS + ID + 1~4 bytes data).*/ + kFLEXCAN_4WordPerRead, /*!< Transfer 4 32-bit words (CS + ID + 5~8 bytes data).*/ + kFLEXCAN_5WordPerRead, /*!< Transfer 5 32-bit words (CS + ID + 9~12 bytes data).*/ + kFLEXCAN_6WordPerRead, /*!< Transfer 6 32-bit words (CS + ID + 13~16 bytes data).*/ + kFLEXCAN_7WordPerRead, /*!< Transfer 7 32-bit words (CS + ID + 17~20 bytes data).*/ + kFLEXCAN_8WordPerRead, /*!< Transfer 8 32-bit words (CS + ID + 21~24 bytes data).*/ + kFLEXCAN_9WordPerRead, /*!< Transfer 9 32-bit words (CS + ID + 25~28 bytes data).*/ + kFLEXCAN_10WordPerRead, /*!< Transfer 10 32-bit words (CS + ID + 29~32 bytes data).*/ + kFLEXCAN_11WordPerRead, /*!< Transfer 11 32-bit words (CS + ID + 33~36 bytes data).*/ + kFLEXCAN_12WordPerRead, /*!< Transfer 12 32-bit words (CS + ID + 37~40 bytes data).*/ + kFLEXCAN_13WordPerRead, /*!< Transfer 13 32-bit words (CS + ID + 41~44 bytes data).*/ + kFLEXCAN_14WordPerRead, /*!< Transfer 14 32-bit words (CS + ID + 45~48 bytes data).*/ + kFLEXCAN_15WordPerRead, /*!< Transfer 15 32-bit words (CS + ID + 49~52 bytes data).*/ + kFLEXCAN_16WordPerRead, /*!< Transfer 16 32-bit words (CS + ID + 53~56 bytes data).*/ + kFLEXCAN_17WordPerRead, /*!< Transfer 17 32-bit words (CS + ID + 57~60 bytes data).*/ + kFLEXCAN_18WordPerRead, /*!< Transfer 18 32-bit words (CS + ID + 61~64 bytes data).*/ + kFLEXCAN_19WordPerRead /*!< Transfer 19 32-bit words (CS + ID + 64 bytes data + ID HIT).*/ +} flexcan_efifo_dma_per_read_length_t; +#endif + +/*! + * @brief FlexCAN Enhanced/Legacy Rx FIFO priority. + * + * The matching process starts from the Rx MB(or Enhanced/Legacy Rx FIFO) with higher priority. + * If no MB(or Enhanced/Legacy Rx FIFO filter) is satisfied, the matching process goes on with + * the Enhanced/Legacy Rx FIFO(or Rx MB) with lower priority. + */ +typedef enum _flexcan_rx_fifo_priority +{ + kFLEXCAN_RxFifoPrioLow = 0x0U, /*!< Matching process start from Rx Message Buffer first. */ + kFLEXCAN_RxFifoPrioHigh = 0x1U, /*!< Matching process start from Enhanced/Legacy Rx FIFO first. */ +} flexcan_rx_fifo_priority_t; + +/*! + * @brief FlexCAN interrupt enable enumerations. + * + * This provides constants for the FlexCAN interrupt enable enumerations for use in the FlexCAN functions. + * @note FlexCAN Message Buffers and Legacy Rx FIFO interrupts not included in. + */ +enum _flexcan_interrupt_enable +{ + kFLEXCAN_BusOffInterruptEnable = CAN_CTRL1_BOFFMSK_MASK, /*!< Bus Off interrupt, use bit 15. */ + kFLEXCAN_ErrorInterruptEnable = CAN_CTRL1_ERRMSK_MASK, /*!< CAN Error interrupt, use bit 14. */ + kFLEXCAN_TxWarningInterruptEnable = CAN_CTRL1_TWRNMSK_MASK, /*!< Tx Warning interrupt, use bit 11. */ + kFLEXCAN_RxWarningInterruptEnable = CAN_CTRL1_RWRNMSK_MASK, /*!< Rx Warning interrupt, use bit 10. */ + kFLEXCAN_WakeUpInterruptEnable = CAN_MCR_WAKMSK_MASK, /*!< Self Wake Up interrupt, use bit 26. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + kFLEXCAN_FDErrorInterruptEnable = CAN_CTRL2_ERRMSK_FAST_MASK, /*!< CAN FD Error interrupt, use bit 31. */ +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + /*! PN Match Wake Up interrupt, use high word bit 17. */ + kFLEXCAN_PNMatchWakeUpInterruptEnable = FLEXCAN_PN_INT_MASK(CAN_CTRL1_PN_WTOF_MSK_MASK), + /*! PN Timeout Wake Up interrupt, use high word bit 16. */ + kFLEXCAN_PNTimeoutWakeUpInterruptEnable = FLEXCAN_PN_INT_MASK(CAN_CTRL1_PN_WUMF_MSK_MASK), +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + /*!< Enhanced Rx FIFO Underflow interrupt, use high word bit 31. */ + kFLEXCAN_ERxFifoUnderflowInterruptEnable = FLEXCAN_EFIFO_INT_MASK(CAN_ERFIER_ERFUFWIE_MASK), + /*!< Enhanced Rx FIFO Overflow interrupt, use high word bit 30. */ + kFLEXCAN_ERxFifoOverflowInterruptEnable = FLEXCAN_EFIFO_INT_MASK(CAN_ERFIER_ERFOVFIE_MASK), + /*!< Enhanced Rx FIFO Watermark interrupt, use high word bit 29. */ + kFLEXCAN_ERxFifoWatermarkInterruptEnable = FLEXCAN_EFIFO_INT_MASK(CAN_ERFIER_ERFWMIIE_MASK), + /*!< Enhanced Rx FIFO Data Avilable interrupt, use high word bit 28. */ + kFLEXCAN_ERxFifoDataAvlInterruptEnable = FLEXCAN_EFIFO_INT_MASK(CAN_ERFIER_ERFDAIE_MASK), +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /*! Host Access With Non-Correctable Errors interrupt, use high word bit 0. */ + kFLEXCAN_HostAccessNCErrorInterruptEnable = FLEXCAN_MECR_INT_MASK(CAN_MECR_HANCEI_MSK_MASK), + /*! FlexCAN Access With Non-Correctable Errors interrupt, use high word bit 2. */ + kFLEXCAN_FlexCanAccessNCErrorInterruptEnable = FLEXCAN_MECR_INT_MASK(CAN_MECR_FANCEI_MSK_MASK), + /*! Host or FlexCAN Access With Correctable Errors interrupt, use high word bit 3. */ + kFLEXCAN_HostOrFlexCanCErrorInterruptEnable = FLEXCAN_MECR_INT_MASK(CAN_MECR_CEI_MSK_MASK), +#endif +}; + +/*! + * @brief FlexCAN status flags. + * + * This provides constants for the FlexCAN status flags for use in the FlexCAN functions. + * @note The CPU read action clears the bits corresponding to the FlEXCAN_ErrorFlag macro, therefore user need to + * read status flags and distinguish which error is occur using @ref _flexcan_error_flags enumerations. + */ +enum _flexcan_flags +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + kFLEXCAN_ErrorOverrunFlag = CAN_ESR1_ERROVR_MASK, /*!< Error Overrun Status. */ + kFLEXCAN_FDErrorIntFlag = CAN_ESR1_ERRINT_FAST_MASK, /*!< CAN FD Error Interrupt Flag. */ + kFLEXCAN_BusoffDoneIntFlag = CAN_ESR1_BOFFDONEINT_MASK, /*!< Bus Off process completed Interrupt Flag. */ +#endif + kFLEXCAN_SynchFlag = CAN_ESR1_SYNCH_MASK, /*!< CAN Synchronization Status. */ + kFLEXCAN_TxWarningIntFlag = CAN_ESR1_TWRNINT_MASK, /*!< Tx Warning Interrupt Flag. */ + kFLEXCAN_RxWarningIntFlag = CAN_ESR1_RWRNINT_MASK, /*!< Rx Warning Interrupt Flag. */ + kFLEXCAN_IdleFlag = CAN_ESR1_IDLE_MASK, /*!< FlexCAN In IDLE Status. */ + kFLEXCAN_FaultConfinementFlag = CAN_ESR1_FLTCONF_MASK, /*!< FlexCAN Fault Confinement State. */ + kFLEXCAN_TransmittingFlag = CAN_ESR1_TX_MASK, /*!< FlexCAN In Transmission Status. */ + kFLEXCAN_ReceivingFlag = CAN_ESR1_RX_MASK, /*!< FlexCAN In Reception Status. */ + kFLEXCAN_BusOffIntFlag = CAN_ESR1_BOFFINT_MASK, /*!< Bus Off Interrupt Flag. */ + kFLEXCAN_ErrorIntFlag = CAN_ESR1_ERRINT_MASK, /*!< CAN Error Interrupt Flag. */ + kFLEXCAN_WakeUpIntFlag = CAN_ESR1_WAKINT_MASK, /*!< Self Wake-Up Interrupt Flag. */ + kFLEXCAN_ErrorFlag = + (uint32_t)(/*!< All FlexCAN Read Clear Error Status. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + CAN_ESR1_STFERR_FAST_MASK | CAN_ESR1_FRMERR_FAST_MASK | CAN_ESR1_CRCERR_FAST_MASK | + CAN_ESR1_BIT0ERR_FAST_MASK | CAN_ESR1_BIT1ERR_FAST_MASK | CAN_ESR1_ERROVR_MASK | +#endif + CAN_ESR1_TXWRN_MASK | CAN_ESR1_RXWRN_MASK | CAN_ESR1_BIT1ERR_MASK | CAN_ESR1_BIT0ERR_MASK | + CAN_ESR1_ACKERR_MASK | CAN_ESR1_CRCERR_MASK | CAN_ESR1_FRMERR_MASK | CAN_ESR1_STFERR_MASK), +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + kFLEXCAN_PNMatchIntFlag = FLEXCAN_PN_STATUS_MASK(CAN_WU_MTC_WUMF_MASK), /*!< PN Matching Event Interrupt Flag. */ + kFLEXCAN_PNTimeoutIntFlag = FLEXCAN_PN_STATUS_MASK(CAN_WU_MTC_WTOF_MASK), /*!< PN Timeout Event Interrupt Flag. */ +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + kFLEXCAN_ERxFifoUnderflowIntFlag = + FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFUFW_MASK), /*!< Enhanced Rx FIFO underflow Interrupt Flag. */ + kFLEXCAN_ERxFifoOverflowIntFlag = + FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFOVF_MASK), /*!< Enhanced Rx FIFO overflow Interrupt Flag. */ + kFLEXCAN_ERxFifoWatermarkIntFlag = + FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFWMI_MASK), /*!< Enhanced Rx FIFO watermark Interrupt Flag. */ + kFLEXCAN_ERxFifoDataAvlIntFlag = + FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFDA_MASK), /*!< Enhanced Rx FIFO data available Interrupt Flag. */ + kFLEXCAN_ERxFifoEmptyFlag = FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFE_MASK), /*!< Enhanced Rx FIFO empty status. */ + kFLEXCAN_ERxFifoFullFlag = FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFF_MASK), /*!< Enhanced Rx FIFO full status. */ +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /*! Host Access With Non-Correctable Error Interrupt Flag. */ + kFLEXCAN_HostAccessNonCorrectableErrorIntFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_HANCEIF_MASK), + /*! FlexCAN Access With Non-Correctable Error Interrupt Flag. */ + kFLEXCAN_FlexCanAccessNonCorrectableErrorIntFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_FANCEIF_MASK), + /*! Correctable Error Interrupt Flag. */ + kFLEXCAN_CorrectableErrorIntFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_CEIF_MASK), + /*! Host Access With Non-Correctable Error Interrupt Overrun Flag. */ + kFLEXCAN_HostAccessNonCorrectableErrorOverrunFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_HANCEIOF_MASK), + /*! FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag. */ + kFLEXCAN_FlexCanAccessNonCorrectableErrorOverrunFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_FANCEIOF_MASK), + /*! Correctable Error Interrupt Overrun Flag. */ + kFLEXCAN_CorrectableErrorOverrunFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_CEIOF_MASK), + /*! All Memory Error Flags. */ + kFLEXCAN_AllMemoryErrorFlag = + (kFLEXCAN_HostAccessNonCorrectableErrorIntFlag | kFLEXCAN_FlexCanAccessNonCorrectableErrorIntFlag | + kFLEXCAN_CorrectableErrorIntFlag | kFLEXCAN_HostAccessNonCorrectableErrorOverrunFlag | + kFLEXCAN_FlexCanAccessNonCorrectableErrorOverrunFlag | kFLEXCAN_CorrectableErrorOverrunFlag) +#endif +}; + +/*! + * @brief FlexCAN error status flags. + * + * The FlexCAN Error Status enumerations is used to report current error of the FlexCAN bus. + * This enumerations should be used with KFLEXCAN_ErrorFlag in @ref _flexcan_flags enumerations + * to ditermine which error is generated. + */ +enum _flexcan_error_flags +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + kFLEXCAN_FDStuffingError = CAN_ESR1_STFERR_FAST_MASK, /*!< Stuffing Error. */ + kFLEXCAN_FDFormError = CAN_ESR1_FRMERR_FAST_MASK, /*!< Form Error. */ + kFLEXCAN_FDCrcError = CAN_ESR1_CRCERR_FAST_MASK, /*!< Cyclic Redundancy Check Error. */ + kFLEXCAN_FDBit0Error = CAN_ESR1_BIT0ERR_FAST_MASK, /*!< Unable to send dominant bit. */ + kFLEXCAN_FDBit1Error = (int)CAN_ESR1_BIT1ERR_FAST_MASK, /*!< Unable to send recessive bit. */ +#endif + kFLEXCAN_TxErrorWarningFlag = CAN_ESR1_TXWRN_MASK, /*!< Tx Error Warning Status. */ + kFLEXCAN_RxErrorWarningFlag = CAN_ESR1_RXWRN_MASK, /*!< Rx Error Warning Status. */ + kFLEXCAN_StuffingError = CAN_ESR1_STFERR_MASK, /*!< Stuffing Error. */ + kFLEXCAN_FormError = CAN_ESR1_FRMERR_MASK, /*!< Form Error. */ + kFLEXCAN_CrcError = CAN_ESR1_CRCERR_MASK, /*!< Cyclic Redundancy Check Error. */ + kFLEXCAN_AckError = CAN_ESR1_ACKERR_MASK, /*!< Received no ACK on transmission. */ + kFLEXCAN_Bit0Error = CAN_ESR1_BIT0ERR_MASK, /*!< Unable to send dominant bit. */ + kFLEXCAN_Bit1Error = CAN_ESR1_BIT1ERR_MASK, /*!< Unable to send recessive bit. */ +}; + +/*! + * @brief FlexCAN Legacy Rx FIFO status flags. + * + * The FlexCAN Legacy Rx FIFO Status enumerations are used to determine the status of the + * Rx FIFO. Because Rx FIFO occupy the MB0 ~ MB7 (Rx Fifo filter also occupies + * more Message Buffer space), Rx FIFO status flags are mapped to the corresponding + * Message Buffer status flags. + */ +enum +{ + kFLEXCAN_RxFifoOverflowFlag = CAN_IFLAG1_BUF7I_MASK, /*!< Rx FIFO overflow flag. */ + kFLEXCAN_RxFifoWarningFlag = CAN_IFLAG1_BUF6I_MASK, /*!< Rx FIFO almost full flag. */ + kFLEXCAN_RxFifoFrameAvlFlag = CAN_IFLAG1_BUF5I_MASK, /*!< Frames available in Rx FIFO flag. */ +}; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +/*! + * @brief FlexCAN Memory Error Type. + */ +typedef enum _flexcan_memory_error_type +{ + kFLEXCAN_CorrectableError = 0U, /*!< The memory error is correctable which means on bit error. */ + kFLEXCAN_NonCorrectableError /*!< The memory error is non-correctable which means two bit errors. */ +} flexcan_memory_error_type_t; + +/*! + * @brief FlexCAN Memory Access Type. + */ +typedef enum _flexcan_memory_access_type +{ + kFLEXCAN_MoveOutFlexCanAccess = 0U, /*!< The memory error was detected during move-out FlexCAN access. */ + kFLEXCAN_MoveInAccess, /*!< The memory error was detected during move-in FlexCAN access. */ + kFLEXCAN_TxArbitrationAccess, /*!< The memory error was detected during Tx Arbitration FlexCAN access. */ + kFLEXCAN_RxMatchingAccess, /*!< The memory error was detected during Rx Matching FlexCAN access. */ + kFLEXCAN_MoveOutHostAccess /*!< The memory error was detected during Rx Matching Host (CPU) access. */ +} flexcan_memory_access_type_t; + +/*! + * @brief FlexCAN Memory Error Byte Syndrome. + */ +typedef enum _flexcan_byte_error_syndrome +{ + kFLEXCAN_NoError = 0U, /*!< No bit error in this byte. */ + kFLEXCAN_ParityBits0Error = 1U, /*!< Parity bit 0 error in this byte. */ + kFLEXCAN_ParityBits1Error = 2U, /*!< Parity bit 1 error in this byte. */ + kFLEXCAN_ParityBits2Error = 4U, /*!< Parity bit 2 error in this byte. */ + kFLEXCAN_ParityBits3Error = 8U, /*!< Parity bit 3 error in this byte. */ + kFLEXCAN_ParityBits4Error = 16U, /*!< Parity bit 4 error in this byte. */ + kFLEXCAN_DataBits0Error = 28U, /*!< Data bit 0 error in this byte. */ + kFLEXCAN_DataBits1Error = 22U, /*!< Data bit 1 error in this byte. */ + kFLEXCAN_DataBits2Error = 19U, /*!< Data bit 2 error in this byte. */ + kFLEXCAN_DataBits3Error = 25U, /*!< Data bit 3 error in this byte. */ + kFLEXCAN_DataBits4Error = 26U, /*!< Data bit 4 error in this byte. */ + kFLEXCAN_DataBits5Error = 7U, /*!< Data bit 5 error in this byte. */ + kFLEXCAN_DataBits6Error = 21U, /*!< Data bit 6 error in this byte. */ + kFLEXCAN_DataBits7Error = 14U, /*!< Data bit 7 error in this byte. */ + kFLEXCAN_AllZeroError = 6U, /*!< All-zeros non-correctable error in this byte. */ + kFLEXCAN_AllOneError = 31U, /*!< All-ones non-correctable error in this byte. */ + kFLEXCAN_NonCorrectableErrors /*!< Non-correctable error in this byte. */ +} flexcan_byte_error_syndrome_t; + +/*! + * @brief FlexCAN memory error register status structure + * + * This structure contains the memory access properties that caused a memory error access. + * It is used as the parameter of FLEXCAN_GetMemoryErrorReportStatus() function. And user can + * use FLEXCAN_GetMemoryErrorReportStatus to get the status of the last memory error access. + */ +typedef struct _flexcan_memory_error_report_status +{ + flexcan_memory_error_type_t errorType; /*!< The type of memory error that giving rise to the report. */ + flexcan_memory_access_type_t accessType; /*!< The type of memory access that giving rise to the memory error. */ + uint16_t accessAddress; /*!< The address where memory error detected. */ + uint32_t errorData; /*!< The raw data word read from memory with error. */ + struct + { + bool byteIsRead; /*!< The byte n (0~3) was read or not. */ + /*!< The type of error and which bit in byte (n) is affected by the error. */ + flexcan_byte_error_syndrome_t bitAffected; + } byteStatus[4]; +} flexcan_memory_error_report_status_t; +#endif + +#if defined(__CC_ARM) +#pragma anon_unions +#endif +/*! @brief FlexCAN message frame structure. */ +typedef struct _flexcan_frame +{ + struct + { + uint32_t timestamp : 16; /*!< FlexCAN internal Free-Running Counter Time Stamp. */ + uint32_t length : 4; /*!< CAN frame data length in bytes (Range: 0~8). */ + uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */ + uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */ + uint32_t : 1; /*!< Reserved. */ + uint32_t idhit : 9; /*!< CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode). */ + }; + struct + { + uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ + uint32_t : 3; /*!< Reserved. */ + }; + union + { + struct + { + uint32_t dataWord0; /*!< CAN Frame payload word0. */ + uint32_t dataWord1; /*!< CAN Frame payload word1. */ + }; + struct + { + uint8_t dataByte3; /*!< CAN Frame payload byte3. */ + uint8_t dataByte2; /*!< CAN Frame payload byte2. */ + uint8_t dataByte1; /*!< CAN Frame payload byte1. */ + uint8_t dataByte0; /*!< CAN Frame payload byte0. */ + uint8_t dataByte7; /*!< CAN Frame payload byte7. */ + uint8_t dataByte6; /*!< CAN Frame payload byte6. */ + uint8_t dataByte5; /*!< CAN Frame payload byte5. */ + uint8_t dataByte4; /*!< CAN Frame payload byte4. */ + }; + }; +} flexcan_frame_t; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! @brief CAN FD message frame structure. + * + * The CAN FD message supporting up to sixty four bytes can be used for a data frame, depending on the length + * selected for the message buffers. The length should be a enumeration member, see @ref _flexcan_fd_frame_length. + */ +typedef struct _flexcan_fd_frame +{ + struct + { + uint32_t timestamp : 16; /*!< FlexCAN internal Free-Running Counter Time Stamp. */ + uint32_t length : 4; /*!< CAN FD frame data length code (DLC), range see @ref _flexcan_fd_frame_length, When the + length <= 8, it equal to the data length, otherwise the number of valid frame data is + not equal to the length value. user can + use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes. */ + uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */ + uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */ + uint32_t srr : 1; /*!< Substitute Remote request. */ + uint32_t : 6; + uint32_t esi : 1; /*!< Error State Indicator. */ + uint32_t brs : 1; /*!< Bit Rate Switch. */ + uint32_t edl : 1; /*!< Extended Data Length. */ + }; + struct + { + uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ + uint32_t : 3; /*!< Reserved. */ + }; + union + { + struct + { + uint32_t dataWord[16]; /*!< CAN FD Frame payload, 16 double word maximum. */ + }; + /* Note: the maximum databyte* below is actually 64, user can add them if needed, + or just use dataWord[*] instead. */ + struct + { + uint8_t dataByte3; /*!< CAN Frame payload byte3. */ + uint8_t dataByte2; /*!< CAN Frame payload byte2. */ + uint8_t dataByte1; /*!< CAN Frame payload byte1. */ + uint8_t dataByte0; /*!< CAN Frame payload byte0. */ + uint8_t dataByte7; /*!< CAN Frame payload byte7. */ + uint8_t dataByte6; /*!< CAN Frame payload byte6. */ + uint8_t dataByte5; /*!< CAN Frame payload byte5. */ + uint8_t dataByte4; /*!< CAN Frame payload byte4. */ + }; + }; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + /*! @note ID HIT offset is changed dynamically according to data length code (DLC), when DLC is 15, they will be + * located below. Using FLEXCAN_FixEnhancedRxFifoFrameIdHit API is recommended to ensure this idhit value is + * correct.*/ + uint32_t idhit; /*!< CAN Enhanced Rx FIFO filter hit id (This value is only used in Enhanced Rx FIFO receive + mode). */ +#endif +} flexcan_fd_frame_t; +#endif + +/*! @brief FlexCAN protocol timing characteristic configuration structure. */ +typedef struct _flexcan_timing_config +{ + uint16_t preDivider; /*!< Classic CAN or CAN FD nominal phase bit rate prescaler. */ + uint8_t rJumpwidth; /*!< Classic CAN or CAN FD nominal phase Re-sync Jump Width. */ + uint8_t phaseSeg1; /*!< Classic CAN or CAN FD nominal phase Segment 1. */ + uint8_t phaseSeg2; /*!< Classic CAN or CAN FD nominal phase Segment 2. */ + uint8_t propSeg; /*!< Classic CAN or CAN FD nominal phase Propagation Segment. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + uint16_t fpreDivider; /*!< CAN FD data phase bit rate prescaler. */ + uint8_t frJumpwidth; /*!< CAN FD data phase Re-sync Jump Width. */ + uint8_t fphaseSeg1; /*!< CAN FD data phase Phase Segment 1. */ + uint8_t fphaseSeg2; /*!< CAN FD data phase Phase Segment 2. */ + uint8_t fpropSeg; /*!< CAN FD data phase Propagation Segment. */ +#endif +} flexcan_timing_config_t; + +/*! @brief FlexCAN module configuration structure. + * @deprecated Do not use the baudRate. It has been superceded bitRate + * @deprecated Do not use the baudRateFD. It has been superceded bitRateFD + */ +typedef struct _flexcan_config +{ + union + { + struct + { + uint32_t baudRate; /*!< FlexCAN bit rate in bps, for classical CAN or CANFD nominal phase. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + uint32_t baudRateFD; /*!< FlexCAN FD bit rate in bps, for CANFD data phase. */ +#endif + }; + struct + { + uint32_t bitRate; /*!< FlexCAN bit rate in bps, for classical CAN or CANFD nominal phase. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + uint32_t bitRateFD; /*!< FlexCAN FD bit rate in bps, for CANFD data phase. */ +#endif + }; + }; + flexcan_clock_source_t clkSrc; /*!< Clock source for FlexCAN Protocol Engine. */ + flexcan_wake_up_source_t wakeupSrc; /*!< Wake up source selection. */ + uint8_t maxMbNum; /*!< The maximum number of Message Buffers used by user. */ + bool enableLoopBack; /*!< Enable or Disable Loop Back Self Test Mode. */ + bool enableTimerSync; /*!< Enable or Disable Timer Synchronization. */ + bool enableSelfWakeup; /*!< Enable or Disable Self Wakeup Mode. */ + bool enableIndividMask; /*!< Enable or Disable Rx Individual Mask and Queue feature. */ + bool disableSelfReception; /*!< Enable or Disable Self Reflection. */ + bool enableListenOnlyMode; /*!< Enable or Disable Listen Only Mode. */ +#if !(defined(FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT) + bool enableSupervisorMode; /*!< Enable or Disable Supervisor Mode, enable this mode will make registers allow only + Supervisor access. */ +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + bool enableDoze; /*!< Enable or Disable Doze Mode. */ +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + bool enablePretendedeNetworking; /*!< Enable or Disable the Pretended Networking mode. */ +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + bool enableMemoryErrorControl; /*!< Enable or Disable the memory errors detection and correction mechanism. */ + bool enableNonCorrectableErrorEnterFreeze; /*!< Enable or Disable Non-Correctable Errors In FlexCAN Access Put + Device In Freeze Mode. */ +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + bool enableTransceiverDelayMeasure; /*!< Enable or Disable the transceiver delay measurement, when it is enabled, + then the secondary sample point position is determined by the sum of the + transceiver delay measurement plus the enhanced TDC offset. */ +#endif + flexcan_timing_config_t timingConfig; /* Protocol timing . */ +} flexcan_config_t; + +/*! + * @brief FlexCAN Receive Message Buffer configuration structure + * + * This structure is used as the parameter of FLEXCAN_SetRxMbConfig() function. + * The FLEXCAN_SetRxMbConfig() function is used to configure FlexCAN Receive + * Message Buffer. The function abort previous receiving process, clean the + * Message Buffer and activate the Rx Message Buffer using given Message Buffer + * setting. + */ +typedef struct _flexcan_rx_mb_config +{ + uint32_t id; /*!< CAN Message Buffer Frame Identifier, should be set using + FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ + flexcan_frame_format_t format; /*!< CAN Frame Identifier format(Standard of Extend). */ + flexcan_frame_type_t type; /*!< CAN Frame Type(Data or Remote). */ +} flexcan_rx_mb_config_t; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) +/*! @brief FlexCAN Pretended Networking match source selection. */ +typedef enum _flexcan_pn_match_source +{ + kFLEXCAN_PNMatSrcID = 0U, /*!< Message match with ID filtering. */ + kFLEXCAN_PNMatSrcIDAndData, /*!< Message match with ID filtering and payload filtering. */ +} flexcan_pn_match_source_t; + +/*! @brief FlexCAN Pretended Networking mode match type. */ +typedef enum _flexcan_pn_match_mode +{ + kFLEXCAN_PNMatModeEqual = 0x0U, /*!< Match upon ID/Payload contents against an exact target value. */ + kFLEXCAN_PNMatModeGreater, /*!< Match upon an ID/Payload value greater than or equal to a specified target value. + */ + kFLEXCAN_PNMatModeSmaller, /*!< Match upon an ID/Payload value smaller than or equal to a specified target value. + */ + kFLEXCAN_PNMatModeRange, /*!< Match upon an ID/Payload value inside a range, greater than or equal to a specified + lower limit, and smaller than or equal to a specified upper limit */ +} flexcan_pn_match_mode_t; + +/*! + * @brief FlexCAN Pretended Networking configuration structure + * + * This structure is used as the parameter of FLEXCAN_SetPNConfig() function. + * The FLEXCAN_SetPNConfig() function is used to configure FlexCAN Networking work mode. + */ +typedef struct _flexcan_pn_config +{ + bool enableTimeout; /*!< Enable or Disable timeout event trigger wakeup.*/ + uint16_t timeoutValue; /*!< The timeout value that generates a wakeup event, the counter timer is incremented based + on 64 times the CAN Bit Time unit. */ + bool enableMatch; /*!< Enable or Disable match event trigger wakeup.*/ + flexcan_pn_match_source_t matchSrc; /*!< Selects the match source (ID and/or data match) to trigger wakeup. */ + uint8_t matchNum; /*!< The number of times a given message must match the predefined ID and/or data before + generating a wakeup event, range in 0x1 ~ 0xFF. */ + flexcan_pn_match_mode_t idMatchMode; /*!< The ID match type. */ + flexcan_pn_match_mode_t dataMatchMode; /*!< The data match type. */ + uint32_t idLower; /*!< The ID target values 1 which used either for ID match "equal to", "smaller than", + "greater than" comparisons, or as the lower limit value in ID match "range detection". */ + uint32_t idUpper; /*!< The ID target values 2 which used only as the upper limit value in ID match "range + detection" or used to store the ID mask in "equal to". */ + uint8_t lengthLower; /*!< The lower limit for length of data bytes which used only in data match "range + detection". Range in 0x0 ~ 0x8.*/ + uint8_t lengthUpper; /*!< The upper limit for length of data bytes which used only in data match "range + detection". Range in 0x0 ~ 0x8.*/ + union + { + /*!< The data target values 1 which used either for data match "equal to", "smaller than", + "greater than" comparisons, or as the lower limit value in data match "range + detection". */ + struct + { + uint32_t lowerWord0; /*!< CAN Frame payload word0. */ + uint32_t lowerWord1; /*!< CAN Frame payload word1. */ + }; + struct + { + uint8_t lowerByte3; /*!< CAN Frame payload byte3. */ + uint8_t lowerByte2; /*!< CAN Frame payload byte2. */ + uint8_t lowerByte1; /*!< CAN Frame payload byte1. */ + uint8_t lowerByte0; /*!< CAN Frame payload byte0. */ + uint8_t lowerByte7; /*!< CAN Frame payload byte7. */ + uint8_t lowerByte6; /*!< CAN Frame payload byte6. */ + uint8_t lowerByte5; /*!< CAN Frame payload byte5. */ + uint8_t lowerByte4; /*!< CAN Frame payload byte4. */ + }; + }; + union + { + /*!< The data target values 2 which used only as the upper limit value in data match "range + detection" or used to store the data mask in "equal to". */ + struct + { + uint32_t upperWord0; /*!< CAN Frame payload word0. */ + uint32_t upperWord1; /*!< CAN Frame payload word1. */ + }; + struct + { + uint8_t upperByte3; /*!< CAN Frame payload byte3. */ + uint8_t upperByte2; /*!< CAN Frame payload byte2. */ + uint8_t upperByte1; /*!< CAN Frame payload byte1. */ + uint8_t upperByte0; /*!< CAN Frame payload byte0. */ + uint8_t upperByte7; /*!< CAN Frame payload byte7. */ + uint8_t upperByte6; /*!< CAN Frame payload byte6. */ + uint8_t upperByte5; /*!< CAN Frame payload byte5. */ + uint8_t upperByte4; /*!< CAN Frame payload byte4. */ + }; + }; +} flexcan_pn_config_t; +#endif + +/*! @brief FlexCAN Legacy Rx FIFO configuration structure. */ +typedef struct _flexcan_rx_fifo_config +{ + uint32_t *idFilterTable; /*!< Pointer to the FlexCAN Legacy Rx FIFO identifier filter table. */ + uint8_t idFilterNum; /*!< The FlexCAN Legacy Rx FIFO Filter elements quantity. */ + flexcan_rx_fifo_filter_type_t idFilterType; /*!< The FlexCAN Legacy Rx FIFO Filter type. */ + flexcan_rx_fifo_priority_t priority; /*!< The FlexCAN Legacy Rx FIFO receive priority. */ +} flexcan_rx_fifo_config_t; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! @brief FlexCAN Enhanced Rx FIFO Standard ID filter element structure. */ +typedef struct _flexcan_enhanced_rx_fifo_std_id_filter +{ + uint32_t filterType : 2; /*!< FlexCAN internal Free-Running Counter Time Stamp. */ + uint32_t : 2; + uint32_t rtr1 : 1; /*!< CAN FD frame data length code (DLC), range see @ref _flexcan_fd_frame_length, When the + length <= 8, it equal to the data length, otherwise the number of valid frame data is + not equal to the length value. user can + use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes. */ + uint32_t std1 : 11; /*!< CAN Frame Type(DATA or REMOTE). */ + uint32_t : 4; + uint32_t rtr2 : 1; /*!< CAN Frame Identifier(STD or EXT format). */ + uint32_t std2 : 11; /*!< Substitute Remote request. */ +} flexcan_enhanced_rx_fifo_std_id_filter_t; + +/*! @brief FlexCAN Enhanced Rx FIFO Extended ID filter element structure. */ +typedef struct _flexcan_enhanced_rx_fifo_ext_id_filter +{ + uint32_t filterType : 2; /*!< FlexCAN internal Free-Running Counter Time Stamp. */ + uint32_t rtr1 : 1; /*!< CAN FD frame data length code (DLC), range see @ref _flexcan_fd_frame_length, When the + length <= 8, it equal to the data length, otherwise the number of valid frame data is + not equal to the length value. user can + use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes. */ + uint32_t std1 : 29; /*!< CAN Frame Type(DATA or REMOTE). */ + uint32_t : 2; + uint32_t rtr2 : 1; /*!< CAN Frame Identifier(STD or EXT format). */ + uint32_t std2 : 29; /*!< Substitute Remote request. */ +} flexcan_enhanced_rx_fifo_ext_id_filter_t; +/*! @brief FlexCAN Enhanced Rx FIFO configuration structure. */ +typedef struct _flexcan_enhanced_rx_fifo_config +{ + uint32_t *idFilterTable; /*!< Pointer to the FlexCAN Enhanced Rx FIFO identifier filter table, each table member + occupies 32 bit word, table size should be equal to idFilterNum. There are two types of + Enhanced Rx FIFO filter elements that can be stored in table : extended-ID filter element + (1 word, occupie 1 table members) and standard-ID filter element (2 words, occupies 2 table + members), the extended-ID filter element needs to be placed in front of the table. */ + uint8_t idFilterPairNum; /*!< idFilterPairNum is the Enhanced Rx FIFO identifier filter element pair numbers, + each pair of filter elements occupies 2 words and can consist of one extended ID filter + element or two standard ID filter elements. */ + uint8_t extendIdFilterNum; /*!< The number of extended ID filter element items in the FlexCAN enhanced Rx FIFO + identifier filter table, each extended-ID filter element occupies 2 words, + extendIdFilterNum need less than or equal to idFilterPairNum. */ + uint8_t fifoWatermark; /*!< (fifoWatermark + 1) is the minimum number of CAN messages stored in the Enhanced RX FIFO + which can trigger FIFO watermark interrupt or a DMA request. */ + flexcan_efifo_dma_per_read_length_t dmaPerReadLength; /*!< Define the length of each read of the Enhanced RX FIFO + element by the DAM, see @ref _flexcan_fd_frame_length. */ + flexcan_rx_fifo_priority_t priority; /*!< The FlexCAN Enhanced Rx FIFO receive priority. */ +} flexcan_enhanced_rx_fifo_config_t; +#endif + +/*! @brief FlexCAN Message Buffer transfer. */ +typedef struct _flexcan_mb_transfer +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + flexcan_fd_frame_t *framefd; +#endif + flexcan_frame_t *frame; /*!< The buffer of CAN Message to be transfer. */ + uint8_t mbIdx; /*!< The index of Message buffer used to transfer Message. */ +} flexcan_mb_transfer_t; + +/*! @brief FlexCAN Rx FIFO transfer. */ +typedef struct _flexcan_fifo_transfer +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + flexcan_fd_frame_t *framefd; /*!< The buffer of CAN Message to be received from Enhanced Rx FIFO. */ +#endif + flexcan_frame_t *frame; /*!< The buffer of CAN Message to be received from Legacy Rx FIFO. */ + size_t frameNum; /*!< Number of CAN Message need to be received from Legacy or Ehanced Rx FIFO. */ +} flexcan_fifo_transfer_t; + +/*! @brief FlexCAN handle structure definition. */ +typedef struct _flexcan_handle flexcan_handle_t; + +/*! @brief FlexCAN transfer callback function. + * + * The FlexCAN transfer callback returns a value from the underlying layer. + * If the status equals to kStatus_FLEXCAN_ErrorStatus, the result parameter is the Content of + * FlexCAN status register which can be used to get the working status(or error status) of FlexCAN module. + * If the status equals to other FlexCAN Message Buffer transfer status, the result is the index of + * Message Buffer that generate transfer event. + * If the status equals to other FlexCAN Message Buffer transfer status, the result is meaningless and should be + * Ignored. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +#define FLEXCAN_CALLBACK(x) \ + void(x)(CAN_Type * base, flexcan_handle_t * handle, status_t status, uint64_t result, void *userData) +typedef void (*flexcan_transfer_callback_t)( + CAN_Type *base, flexcan_handle_t *handle, status_t status, uint64_t result, void *userData); +#else +#define FLEXCAN_CALLBACK(x) \ + void(x)(CAN_Type * base, flexcan_handle_t * handle, status_t status, uint32_t result, void *userData) +typedef void (*flexcan_transfer_callback_t)( + CAN_Type *base, flexcan_handle_t *handle, status_t status, uint32_t result, void *userData); +#endif + +/*! @brief FlexCAN handle structure. */ +struct _flexcan_handle +{ + flexcan_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< FlexCAN callback function parameter.*/ + flexcan_frame_t + *volatile mbFrameBuf[CAN_WORD1_COUNT]; /*!< The buffer for received CAN data from Message Buffers. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + flexcan_fd_frame_t + *volatile mbFDFrameBuf[CAN_WORD1_COUNT]; /*!< The buffer for received CAN FD data from Message Buffers. */ +#endif + flexcan_frame_t *volatile rxFifoFrameBuf; /*!< The buffer for received CAN data from Legacy Rx FIFO. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + flexcan_fd_frame_t *volatile rxFifoFDFrameBuf; /*!< The buffer for received CAN FD data from Ehanced Rx FIFO. */ +#endif + size_t rxFifoFrameNum; /*!< The number of CAN messages remaining to be received from Legacy or Ehanced Rx FIFO. */ + size_t rxFifoTransferTotalNum; /*!< Total CAN Message number need to be received from Legacy or Ehanced Rx FIFO. */ + volatile uint8_t mbState[CAN_WORD1_COUNT]; /*!< Message Buffer transfer state. */ + volatile uint8_t rxFifoState; /*!< Rx FIFO transfer state. */ + volatile uint32_t timestamp[CAN_WORD1_COUNT]; /*!< Mailbox transfer timestamp. */ +}; + +/****************************************************************************** + * API + *****************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Determine whether the FlexCAN instance support CAN FD mode at run time. + * + * @note Use this API only if different soc parts share the SOC part name macro define. Otherwise, a different SOC part + * name can be used to determine at compile time whether the FlexCAN instance supports CAN FD mode or not. + * If need use this API to determine if CAN FD mode is supported, the FLEXCAN_Init function needs to be + * executed first, and then call this API and use the return to value determines whether to supports CAN FD mode, + * if return true, continue calling FLEXCAN_FDInit to enable CAN FD mode. + * + * @param base FlexCAN peripheral base address. + * @return return TRUE if instance support CAN FD mode, FALSE if instance only support classic CAN (2.0) mode. + */ +bool FLEXCAN_IsInstanceHasFDMode(CAN_Type *base); +#endif + +/*! + * @brief Enter FlexCAN Freeze Mode. + * + * This function makes the FlexCAN work under Freeze Mode. + * + * @param base FlexCAN peripheral base address. + */ +void FLEXCAN_EnterFreezeMode(CAN_Type *base); + +/*! + * @brief Exit FlexCAN Freeze Mode. + * + * This function makes the FlexCAN leave Freeze Mode. + * + * @param base FlexCAN peripheral base address. + */ +void FLEXCAN_ExitFreezeMode(CAN_Type *base); + +/*! + * @brief Get the FlexCAN instance from peripheral base address. + * + * @param base FlexCAN peripheral base address. + * @return FlexCAN instance. + */ +uint32_t FLEXCAN_GetInstance(CAN_Type *base); + +/*! + * @brief Calculates the improved timing values by specific bit Rates for classical CAN. + * + * This function use to calculates the Classical CAN timing values according to the given bit rate. The Calculated + * timing values will be set in CTRL1/CBT/ENCBT register. The calculation is based on the recommendation of the CiA 301 + * v4.2.0 and previous version document. + * + * @param base FlexCAN peripheral base address. + * @param bitRate The classical CAN speed in bps defined by user, should be less than or equal to 1Mbps. + * @param sourceClock_Hz The Source clock frequency in Hz. + * @param pTimingConfig Pointer to the FlexCAN timing configuration structure. + * + * @return TRUE if timing configuration found, FALSE if failed to find configuration. + */ +bool FLEXCAN_CalculateImprovedTimingValues(CAN_Type *base, + uint32_t bitRate, + uint32_t sourceClock_Hz, + flexcan_timing_config_t *pTimingConfig); + +/*! + * @brief Initializes a FlexCAN instance. + * + * This function initializes the FlexCAN module with user-defined settings. + * This example shows how to set up the flexcan_config_t parameters and how + * to call the FLEXCAN_Init function by passing in these parameters. + * @code + * flexcan_config_t flexcanConfig; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrc0; + * flexcanConfig.bitRate = 1000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.enableDoze = false; + * flexcanConfig.disableSelfReception = false; + * flexcanConfig.enableListenOnlyMode = false; + * flexcanConfig.timingConfig = timingConfig; + * FLEXCAN_Init(CAN0, &flexcanConfig, 40000000UL); + * @endcode + * + * @param base FlexCAN peripheral base address. + * @param pConfig Pointer to the user-defined configuration structure. + * @param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. + */ +void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Calculates the improved timing values by specific bit rates for CANFD. + * + * This function use to calculates the CANFD timing values according to the given nominal phase bit rate and data phase + * bit rate. The Calculated timing values will be set in CBT/ENCBT and FDCBT/EDCBT registers. The calculation is based + * on the recommendation of the CiA 1301 v1.0.0 document. + * + * @param base FlexCAN peripheral base address. + * @param bitRate The CANFD bus control speed in bps defined by user. + * @param bitRateFD The CAN FD data phase speed in bps defined by user. Equal to bitRate means disable bit rate + * switching. + * @param sourceClock_Hz The Source clock frequency in Hz. + * @param pTimingConfig Pointer to the FlexCAN timing configuration structure. + * + * @return TRUE if timing configuration found, FALSE if failed to find configuration + */ +bool FLEXCAN_FDCalculateImprovedTimingValues(CAN_Type *base, + uint32_t bitRate, + uint32_t bitRateFD, + uint32_t sourceClock_Hz, + flexcan_timing_config_t *pTimingConfig); +/*! + * @brief Initializes a FlexCAN instance. + * + * This function initializes the FlexCAN module with user-defined settings. + * This example shows how to set up the flexcan_config_t parameters and how + * to call the FLEXCAN_FDInit function by passing in these parameters. + * @code + * flexcan_config_t flexcanConfig; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrc0; + * flexcanConfig.bitRate = 1000000U; + * flexcanConfig.bitRateFD = 2000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.disableSelfReception = false; + * flexcanConfig.enableListenOnlyMode = false; + * flexcanConfig.enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; + * FLEXCAN_FDInit(CAN0, &flexcanConfig, 80000000UL, kFLEXCAN_16BperMB, true); + * @endcode + * + * @param base FlexCAN peripheral base address. + * @param pConfig Pointer to the user-defined configuration structure. + * @param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. + * @param dataSize FlexCAN Message Buffer payload size. The actual transmitted or received CAN FD frame data size needs + * to be less than or equal to this value. + * @param brs True if bit rate switch is enabled in FD mode. + */ +void FLEXCAN_FDInit( + CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs); +#endif + +/*! + * @brief De-initializes a FlexCAN instance. + * + * This function disables the FlexCAN module clock and sets all register values + * to the reset value. + * + * @param base FlexCAN peripheral base address. + */ +void FLEXCAN_Deinit(CAN_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the FlexCAN configuration structure to default values. The default + * values are as follows. + * flexcanConfig->clkSrc = kFLEXCAN_ClkSrc0; + * flexcanConfig->bitRate = 1000000U; + * flexcanConfig->bitRateFD = 2000000U; + * flexcanConfig->maxMbNum = 16; + * flexcanConfig->enableLoopBack = false; + * flexcanConfig->enableSelfWakeup = false; + * flexcanConfig->enableIndividMask = false; + * flexcanConfig->disableSelfReception = false; + * flexcanConfig->enableListenOnlyMode = false; + * flexcanConfig->enableDoze = false; + * flexcanConfig->enableMemoryErrorControl = true; + * flexcanConfig->enableNonCorrectableErrorEnterFreeze = true; + * flexcanConfig.timingConfig = timingConfig; + * + * @param pConfig Pointer to the FlexCAN configuration structure. + */ +void FLEXCAN_GetDefaultConfig(flexcan_config_t *pConfig); + +/*! @} */ + +/*! + * @name Configuration. + * @{ + */ + +/*! + * @brief Sets the FlexCAN classical CAN protocol timing characteristic. + * + * This function gives user settings to classical CAN or CAN FD nominal phase timing characteristic. + * The function is for an experienced user. For less experienced users, call the FLEXCAN_SetBitRate() instead. + * + * @note Calling FLEXCAN_SetTimingConfig() overrides the bit rate set in FLEXCAN_Init() or FLEXCAN_SetBitRate(). + * + * @param base FlexCAN peripheral base address. + * @param pConfig Pointer to the timing configuration structure. + */ +void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig); + +/*! + * @brief Set bit rate of FlexCAN classical CAN frame or CAN FD frame nominal phase. + * + * This function set the bit rate of classical CAN frame or CAN FD frame nominal phase base on + * FLEXCAN_CalculateImprovedTimingValues() API calculated timing values. + * + * @note Calling FLEXCAN_SetBitRate() overrides the bit rate set in FLEXCAN_Init(). + * + * @param base FlexCAN peripheral base address. + * @param sourceClock_Hz Source Clock in Hz. + * @param bitRate_Bps Bit rate in Bps. + * @return kStatus_Success - Set CAN baud rate (only Nominal phase) successfully. + */ +status_t FLEXCAN_SetBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRate_Bps); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Sets the FlexCAN CANFD data phase timing characteristic. + * + * This function gives user settings to CANFD data phase timing characteristic. + * The function is for an experienced user. For less experienced users, call the FLEXCAN_SetFDBitRate() + * to set both Nominal/Data bit Rate instead. + * + * @note Calling FLEXCAN_SetFDTimingConfig() overrides the data phase bit rate set in + * FLEXCAN_FDInit()/FLEXCAN_SetFDBitRate(). + * + * @param base FlexCAN peripheral base address. + * @param pConfig Pointer to the timing configuration structure. + */ +void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig); + +/*! + * @brief Set bit rate of FlexCAN FD frame. + * + * This function set the baud rate of FLEXCAN FD base on FLEXCAN_FDCalculateImprovedTimingValues() API calculated timing + * values. + * + * @param base FlexCAN peripheral base address. + * @param sourceClock_Hz Source Clock in Hz. + * @param bitRateN_Bps Nominal bit Rate in Bps. + * @param bitRateD_Bps Data bit Rate in Bps. + * @return kStatus_Success - Set CAN FD bit rate (include Nominal and Data phase) successfully. + */ +status_t FLEXCAN_SetFDBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRateN_Bps, uint32_t bitRateD_Bps); +#endif + +/*! + * @brief Sets the FlexCAN receive message buffer global mask. + * + * This function sets the global mask for the FlexCAN message buffer in a matching process. + * The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init(). + * + * @param base FlexCAN peripheral base address. + * @param mask Rx Message Buffer Global Mask value. + */ +void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask); + +/*! + * @brief Sets the FlexCAN receive FIFO global mask. + * + * This function sets the global mask for FlexCAN FIFO in a matching process. + * + * @param base FlexCAN peripheral base address. + * @param mask Rx Fifo Global Mask value. + */ +void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask); + +/*! + * @brief Sets the FlexCAN receive individual mask. + * + * This function sets the individual mask for the FlexCAN matching process. + * The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init(). + * If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer. + * If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to + * the Rx Filter with the same index. Note that only the first 32 + * individual masks can be used as the Rx FIFO filter mask. + * + * @param base FlexCAN peripheral base address. + * @param maskIdx The Index of individual Mask. + * @param mask Rx Individual Mask value. + */ +void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask); + +/*! + * @brief Configures a FlexCAN transmit message buffer. + * + * This function aborts the previous transmission, cleans the Message Buffer, and + * configures it as a Transmit Message Buffer. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The Message Buffer index. + * @param enable Enable/disable Tx Message Buffer. + * - true: Enable Tx Message Buffer. + * - false: Disable Tx Message Buffer. + */ +void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Configures a FlexCAN transmit message buffer. + * + * This function aborts the previous transmission, cleans the Message Buffer, and + * configures it as a Transmit Message Buffer. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The Message Buffer index. + * @param enable Enable/disable Tx Message Buffer. + * - true: Enable Tx Message Buffer. + * - false: Disable Tx Message Buffer. + */ +void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable); +#endif + +/*! + * @brief Configures a FlexCAN Receive Message Buffer. + * + * This function cleans a FlexCAN build-in Message Buffer and configures it + * as a Receive Message Buffer. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The Message Buffer index. + * @param pRxMbConfig Pointer to the FlexCAN Message Buffer configuration structure. + * @param enable Enable/disable Rx Message Buffer. + * - true: Enable Rx Message Buffer. + * - false: Disable Rx Message Buffer. + */ +void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Configures a FlexCAN Receive Message Buffer. + * + * This function cleans a FlexCAN build-in Message Buffer and configures it + * as a Receive Message Buffer. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The Message Buffer index. + * @param pRxMbConfig Pointer to the FlexCAN Message Buffer configuration structure. + * @param enable Enable/disable Rx Message Buffer. + * - true: Enable Rx Message Buffer. + * - false: Disable Rx Message Buffer. + */ +void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable); +#endif + +/*! + * @brief Configures the FlexCAN Legacy Rx FIFO. + * + * This function configures the FlexCAN Rx FIFO with given configuration. + * @note Legacy Rx FIFO only can receive classic CAN message. + * + * @param base FlexCAN peripheral base address. + * @param pRxFifoConfig Pointer to the FlexCAN Legacy Rx FIFO configuration structure. Can be NULL when enable parameter + * is false. + * @param enable Enable/disable Legacy Rx FIFO. + * - true: Enable Legacy Rx FIFO. + * - false: Disable Legacy Rx FIFO. + */ +void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *pRxFifoConfig, bool enable); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Configures the FlexCAN Enhanced Rx FIFO. + * + * This function configures the Enhanced Rx FIFO with given configuration. + * @note Enhanced Rx FIFO support receive classic CAN or CAN FD messages, Legacy Rx FIFO and Enhanced Rx FIFO + * cannot be enabled at the same time. + * + * @param base FlexCAN peripheral base address. + * @param pConfig Pointer to the FlexCAN Enhanced Rx FIFO configuration structure. Can be NULL when enable parameter + * is false. + * @param enable Enable/disable Enhanced Rx FIFO. + * - true: Enable Enhanced Rx FIFO. + * - false: Disable Enhanced Rx FIFO. + */ +void FLEXCAN_SetEnhancedRxFifoConfig(CAN_Type *base, const flexcan_enhanced_rx_fifo_config_t *pConfig, bool enable); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) +/*! + * @brief Configures the FlexCAN Pretended Networking mode. + * + * This function configures the FlexCAN Pretended Networking mode with given configuration. + * + * @param base FlexCAN peripheral base address. + * @param pConfig Pointer to the FlexCAN Rx FIFO configuration structure. + */ +void FLEXCAN_SetPNConfig(CAN_Type *base, const flexcan_pn_config_t *pConfig); +#endif +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the FlexCAN module interrupt flags. + * + * This function gets all FlexCAN status flags. The flags are returned as the logical + * OR value of the enumerators @ref _flexcan_flags. To check the specific status, + * compare the return value with enumerators in @ref _flexcan_flags. + * + * @param base FlexCAN peripheral base address. + * @return FlexCAN status flags which are ORed by the enumerators in the _flexcan_flags. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +static inline uint64_t FLEXCAN_GetStatusFlags(CAN_Type *base) +{ + uint64_t tempflag = (uint64_t)base->ESR1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + /* Get PN Wake Up status. */ + tempflag |= FLEXCAN_PN_STATUS_MASK(base->WU_MTC); +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + /* Get Enhanced Rx FIFO status. */ + tempflag |= FLEXCAN_EFIFO_STATUS_MASK(base->ERFSR); +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /* Get Memory Error status. */ + tempflag |= FLEXCAN_MECR_STATUS_MASK(base->ERRSR); +#endif + return tempflag; +} +#else +static inline uint32_t FLEXCAN_GetStatusFlags(CAN_Type *base) +{ + return base->ESR1; +} +#endif +/*! + * @brief Clears status flags with the provided mask. + * + * This function clears the FlexCAN status flags with a provided mask. An automatically cleared flag + * can't be cleared by this function. + * + * @param base FlexCAN peripheral base address. + * @param mask The status flags to be cleared, it is logical OR value of @ref _flexcan_flags. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint64_t mask) +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + /* Clear PN Wake Up status. */ + base->WU_MTC = FLEXCAN_PN_STATUS_UNMASK(mask); +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + /* Clear Enhanced Rx FIFO status. */ + base->ERFSR = FLEXCAN_EFIFO_STATUS_UNMASK(mask); +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /* Clear Memory Error status. */ + base->ERRSR = FLEXCAN_MECR_STATUS_UNMASK(mask); +#endif + base->ESR1 = (uint32_t)(mask & 0xFFFFFFFFU); +} +#else +static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint32_t mask) +{ + /* Write 1 to clear status flag. */ + base->ESR1 = mask; +} +#endif +/*! + * @brief Gets the FlexCAN Bus Error Counter value. + * + * This function gets the FlexCAN Bus Error Counter value for both Tx and + * Rx direction. These values may be needed in the upper layer error handling. + * + * @param base FlexCAN peripheral base address. + * @param txErrBuf Buffer to store Tx Error Counter value. + * @param rxErrBuf Buffer to store Rx Error Counter value. + */ +static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf) +{ + if (NULL != txErrBuf) + { + *txErrBuf = (uint8_t)((base->ECR & CAN_ECR_TXERRCNT_MASK) >> CAN_ECR_TXERRCNT_SHIFT); + } + + if (NULL != rxErrBuf) + { + *rxErrBuf = (uint8_t)((base->ECR & CAN_ECR_RXERRCNT_MASK) >> CAN_ECR_RXERRCNT_SHIFT); + } +} + +/*! + * @brief Gets the FlexCAN Message Buffer interrupt flags. + * + * This function gets the interrupt flags of a given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + * @return The status of given Message Buffers. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline uint64_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint64_t mask) +#else +static inline uint32_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint32_t mask) +#endif +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t tempflag = (uint64_t)base->IFLAG1; + return (tempflag | (((uint64_t)base->IFLAG2) << 32)) & mask; +#else + return (base->IFLAG1 & mask); +#endif +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) +/*! + * @brief Gets the FlexCAN High 64 Message Buffer interrupt flags. + * + * Valid only if the number of available MBs exceeds 64. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + * @return The status of given Message Buffers. + */ +static inline uint64_t FLEXCAN_GetHigh64MbStatusFlags(CAN_Type *base, uint64_t mask) +{ + uint64_t tempflag = 0U; +#if defined(CAN_IFLAG3_BUF95TO64_MASK) + tempflag |= (uint64_t)base->IFLAG3; +#endif +#if defined(CAN_IFLAG4_BUF127TO96_MASK) + tempflag |= (uint64_t)base->IFLAG4; +#endif + return (tempflag & mask); +} +#endif + +/*! + * @brief Clears the FlexCAN Message Buffer interrupt flags. + * + * This function clears the interrupt flags of a given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint32_t mask) +#endif +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IFLAG1 = (uint32_t)(mask & 0xFFFFFFFFU); + base->IFLAG2 = (uint32_t)(mask >> 32); +#else + base->IFLAG1 = mask; +#endif +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) +/*! + * @brief Clears the FlexCAN High 64 Message Buffer interrupt flags. + * + * Valid only if the number of available MBs exceeds 64. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +static inline void FLEXCAN_ClearHigh64MbStatusFlags(CAN_Type *base, uint64_t mask) +{ +#if defined(CAN_IFLAG3_BUF95TO64_MASK) + base->IFLAG3 = (uint32_t)(mask & 0xFFFFFFFFU); +#endif +#if defined(CAN_IFLAG4_BUF127TO96_MASK) + base->IFLAG4 = (uint32_t)(mask >> 32U); +#endif +} +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +/*! + * @brief Gets the FlexCAN Memory Error Report registers status. + * + * This function gets the FlexCAN Memory Error Report registers status. + * + * @param base FlexCAN peripheral base address. + * @param errorStatus Pointer to FlexCAN Memory Error Report registers status structure. + */ +void FLEXCAN_GetMemoryErrorReportStatus(CAN_Type *base, flexcan_memory_error_report_status_t *errorStatus); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) +/*! + * @brief Gets the FlexCAN Number of Matches when in Pretended Networking. + * + * This function gets the number of times a given message has matched the predefined filtering criteria for ID and/or PL + * before a wakeup event. + * + * @param base FlexCAN peripheral base address. + * @return The number of received wake up msessages. + */ +static inline uint8_t FLEXCAN_GetPNMatchCount(CAN_Type *base) +{ + return (uint8_t)((base->WU_MTC & CAN_WU_MTC_MCOUNTER_MASK) >> CAN_WU_MTC_MCOUNTER_SHIFT); +} +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Gets the number of FlexCAN Enhanced Rx FIFO available frames. + * + * This function gets the number of CAN messages stored in the Enhanced Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @return The number of available CAN messages stored in the Enhanced Rx FIFO. + */ +static inline uint32_t FLEXCAN_GetEnhancedFifoDataCount(CAN_Type *base) +{ + return (base->ERFSR & CAN_ERFSR_ERFEL_MASK); +} +#endif +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables FlexCAN interrupts according to the provided mask. + * + * This function enables the FlexCAN interrupts according to the provided mask. The mask + * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable. + * + * @param base FlexCAN peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _flexcan_interrupt_enable. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask) +#endif +{ + uint32_t primask = DisableGlobalIRQ(); + + /* Solve Self Wake Up interrupt. */ + base->MCR |= (uint32_t)(mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { + /* Solve CAN FD frames data phase error interrupt. */ + base->CTRL2 |= (uint32_t)(mask & (uint32_t)kFLEXCAN_FDErrorInterruptEnable); + } +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + /* Solve PN Wake Up interrupt. */ + base->CTRL1_PN |= FLEXCAN_PN_INT_UNMASK(mask); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + /* Solve Enhanced Rx FIFO interrupt. */ + base->ERFIER |= FLEXCAN_EFIFO_INT_UNMASK(mask); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /* Solve Memory Error interrupt. */ + base->MECR |= FLEXCAN_MECR_INT_UNMASK(mask); +#endif + + /* Solve interrupt enable bits in CTRL1 register. */ + base->CTRL1 |= + (uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable | + (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable)); + + EnableGlobalIRQ(primask); +} + +/*! + * @brief Disables FlexCAN interrupts according to the provided mask. + * + * This function disables the FlexCAN interrupts according to the provided mask. The mask + * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable. + * + * @param base FlexCAN peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _flexcan_interrupt_enable. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask) +#endif +{ + uint32_t primask = DisableGlobalIRQ(); + + /* Solve Wake Up Interrupt. */ + base->MCR &= ~(uint32_t)(mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { + /* Solve CAN FD frames data phase error interrupt. */ + base->CTRL2 &= ~(uint32_t)(mask & (uint32_t)kFLEXCAN_FDErrorInterruptEnable); + } +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + /* Solve PN Wake Up Interrupt. */ + base->CTRL1_PN &= ~FLEXCAN_PN_STATUS_UNMASK(mask); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + /* Solve Enhanced Rx FIFO interrupt. */ + base->ERFIER &= ~FLEXCAN_EFIFO_INT_UNMASK(mask); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /* Solve Memory Error Interrupt. */ + base->MECR &= ~FLEXCAN_MECR_STATUS_UNMASK(mask); +#endif + + /* Solve interrupt enable bits in CTRL1 register. */ + base->CTRL1 &= + ~(uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable | + (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable)); + + EnableGlobalIRQ(primask); +} + +/*! + * @brief Enables FlexCAN Message Buffer interrupts. + * + * This function enables the interrupts of given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint32_t mask) +#endif +{ + uint32_t primask = DisableGlobalIRQ(); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK1 |= (uint32_t)(mask & 0xFFFFFFFFU); + base->IMASK2 |= (uint32_t)(mask >> 32); +#else + base->IMASK1 |= mask; +#endif + EnableGlobalIRQ(primask); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) +/*! + * @brief Enables FlexCAN high 64 Message Buffer interrupts. + * + * Valid only if the number of available MBs exceeds 64. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +static inline void FLEXCAN_EnableHigh64MbInterrupts(CAN_Type *base, uint64_t mask) +{ + uint32_t primask = DisableGlobalIRQ(); + +#if defined(CAN_IMASK3_BUF95TO64M_MASK) + base->IMASK3 |= (uint32_t)(mask & 0xFFFFFFFFU); +#endif +#if defined(CAN_IMASK4_BUF127TO96_MASK) + base->IMASK4 |= (uint32_t)(mask >> 32U); +#endif + EnableGlobalIRQ(primask); +} +#endif + +/*! + * @brief Disables FlexCAN Message Buffer interrupts. + * + * This function disables the interrupts of given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint32_t mask) +#endif +{ + uint32_t primask = DisableGlobalIRQ(); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK1 &= ~((uint32_t)(mask & 0xFFFFFFFFU)); + base->IMASK2 &= ~((uint32_t)(mask >> 32)); +#else + base->IMASK1 &= ~mask; +#endif + EnableGlobalIRQ(primask); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) +/*! + * @brief Disables FlexCAN high 64 Message Buffer interrupts. + * + * Valid only if the number of available MBs exceeds 64. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +static inline void FLEXCAN_DisableHigh64MbInterrupts(CAN_Type *base, uint64_t mask) +{ + uint32_t primask = DisableGlobalIRQ(); + +#if defined(CAN_IMASK3_BUF95TO64M_MASK) + base->IMASK3 &= ~((uint32_t)(mask & 0xFFFFFFFFU)); +#endif +#if defined(CAN_IMASK4_BUF127TO96_MASK) + base->IMASK4 &= ~((uint32_t)(mask >> 32U)); +#endif + EnableGlobalIRQ(primask); +} +#endif + +/*! @} */ + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables or disables the FlexCAN Rx FIFO DMA request. + * + * This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @param enable true to enable, false to disable. + */ +void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable); + +/*! + * @brief Gets the Rx FIFO Head address. + * + * This function returns the FlexCAN Rx FIFO Head address, which is mainly used for the DMA/eDMA use case. + * + * @param base FlexCAN peripheral base address. + * @return FlexCAN Rx FIFO Head address. + */ +static inline uintptr_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base) +{ + return (uintptr_t) & (base->MB[0].CS); +} + +/*! @} */ +#endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables or disables the FlexCAN module operation. + * + * This function enables or disables the FlexCAN module. + * + * @param base FlexCAN base pointer. + * @param enable true to enable, false to disable. + */ +static inline void FLEXCAN_Enable(CAN_Type *base, bool enable) +{ + if (enable) + { + base->MCR &= ~CAN_MCR_MDIS_MASK; + + /* Wait FlexCAN exit from low-power mode. */ + while (0U != (base->MCR & CAN_MCR_LPMACK_MASK)) + { + } + } + else + { + base->MCR |= CAN_MCR_MDIS_MASK; + + /* Wait FlexCAN enter low-power mode. */ + while (0U == (base->MCR & CAN_MCR_LPMACK_MASK)) + { + } + } +} + +/*! + * @brief Writes a FlexCAN Message to the Transmit Message Buffer. + * + * This function writes a CAN Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN Message transmit. After + * that the function returns immediately. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + * @param pTxFrame Pointer to CAN message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *pTxFrame); + +/*! + * @brief Reads a FlexCAN Message from Receive Message Buffer. + * + * This function reads a CAN message from a specified Receive Message Buffer. + * The function fills a receive CAN message frame structure with + * just received data and activates the Message Buffer again. + * The function returns immediately. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + * @param pRxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * @retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Writes a FlexCAN FD Message to the Transmit Message Buffer. + * + * This function writes a CAN FD Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN FD Message transmit. After + * that the function returns immediately. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN FD Message Buffer index. + * @param pTxFrame Pointer to CAN FD message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *pTxFrame); + +/*! + * @brief Reads a FlexCAN FD Message from Receive Message Buffer. + * + * This function reads a CAN FD message from a specified Receive Message Buffer. + * The function fills a receive CAN FD message frame structure with + * just received data and activates the Message Buffer again. + * The function returns immediately. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN FD Message Buffer index. + * @param pRxFrame Pointer to CAN FD message frame structure for reception. + * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * @retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame); +#endif + +/*! + * @brief Reads a FlexCAN Message from Legacy Rx FIFO. + * + * This function reads a CAN message from the FlexCAN Legacy Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @param pRxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx FIFO successfully. + * @retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *pRxFrame); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Reads a FlexCAN Message from Enhanced Rx FIFO. + * + * This function reads a CAN or CAN FD message from the FlexCAN Enhanced Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @param pRxFrame Pointer to CAN FD message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx FIFO successfully. + * @retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_ReadEnhancedRxFifo(CAN_Type *base, flexcan_fd_frame_t *pRxFrame); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) +/*! + * @brief Reads a FlexCAN Message from Wake Up MB. + * + * This function reads a CAN message from the FlexCAN Wake up Message Buffers. There are four Wake up Message Buffers + * (WMBs) used to store incoming messages in Pretended Networking mode. The WMB index indicates the arrival order. The + * last message is stored in WMB3. + * + * @param base FlexCAN peripheral base address. + * @param pRxFrame Pointer to CAN message frame structure for reception. + * @param mbIdx The FlexCAN Wake up Message Buffer index. Range in 0x0 ~ 0x3. + * @retval kStatus_Success - Read Message from Wake up Message Buffer successfully. + * @retval kStatus_Fail - Wake up Message Buffer has no valid content. + */ +status_t FLEXCAN_ReadPNWakeUpMB(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame); +#endif +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Performs a polling send transaction on the CAN bus. + * + * @note A transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param mbIdx The FlexCAN FD Message Buffer index. + * @param pTxFrame Pointer to CAN FD message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pTxFrame); + +/*! + * @brief Performs a polling receive transaction on the CAN bus. + * + * @note A transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param mbIdx The FlexCAN FD Message Buffer index. + * @param pRxFrame Pointer to CAN FD message frame structure for reception. + * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * @retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame); + +/*! + * @brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param pMbXfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * @retval kStatus_Success Start Tx Message Buffer sending process successfully. + * @retval kStatus_Fail Write Tx Message Buffer failed. + * @retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. + */ +status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer); + +/*! + * @brief Receives a message using IRQ. + * + * This function receives a message using IRQ. This is non-blocking function, which returns + * right away. When the message has been received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param pMbXfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * @retval kStatus_Success - Start Rx Message Buffer receiving process successfully. + * @retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. + */ +status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer); + +/*! + * @brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN FD Message Buffer index. + */ +void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); + +/*! + * @brief Aborts the interrupt driven message receive process. + * + * This function aborts the interrupt driven message receive process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN FD Message Buffer index. + */ +void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); +#endif + +/*! + * @brief Performs a polling send transaction on the CAN bus. + * + * @note A transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param mbIdx The FlexCAN Message Buffer index. + * @param pTxFrame Pointer to CAN message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pTxFrame); + +/*! + * @brief Performs a polling receive transaction on the CAN bus. + * + * @note A transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param mbIdx The FlexCAN Message Buffer index. + * @param pRxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * @retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame); + +/*! + * @brief Performs a polling receive transaction from Legacy Rx FIFO on the CAN bus. + * + * @note A transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param pRxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx FIFO successfully. + * @retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *pRxFrame); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Performs a polling receive transaction from Enhanced Rx FIFO on the CAN bus. + * + * @note A transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param pRxFrame Pointer to CAN FD message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx FIFO successfully. + * @retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_TransferReceiveEnhancedFifoBlocking(CAN_Type *base, flexcan_fd_frame_t *pRxFrame); +#endif + +/*! + * @brief Initializes the FlexCAN handle. + * + * This function initializes the FlexCAN handle, which can be used for other FlexCAN + * transactional APIs. Usually, for a specified FlexCAN instance, + * call this API once to get the initialized handle. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +void FLEXCAN_TransferCreateHandle(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_transfer_callback_t callback, + void *userData); + +/*! + * @brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param pMbXfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * @retval kStatus_Success Start Tx Message Buffer sending process successfully. + * @retval kStatus_Fail Write Tx Message Buffer failed. + * @retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. + */ +status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer); + +/*! + * @brief Receives a message using IRQ. + * + * This function receives a message using IRQ. This is non-blocking function, which returns + * right away. When the message has been received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param pMbXfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * @retval kStatus_Success - Start Rx Message Buffer receiving process successfully. + * @retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. + */ +status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer); + +/*! + * @brief Receives a message from Rx FIFO using IRQ. + * + * This function receives a message using IRQ. This is a non-blocking function, which returns + * right away. When all messages have been received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param pFifoXfer FlexCAN Rx FIFO transfer structure. See the @ref flexcan_fifo_transfer_t. + * @retval kStatus_Success - Start Rx FIFO receiving process successfully. + * @retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use. + */ +status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer); + +/*! + * @brief Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param count Number of CAN messages receive so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ + +status_t FLEXCAN_TransferGetReceiveFifoCount(CAN_Type *base, flexcan_handle_t *handle, size_t *count); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Receives a message from Enhanced Rx FIFO using IRQ. + * + * This function receives a message using IRQ. This is a non-blocking function, which returns + * right away. When all messages have been received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param pFifoXfer FlexCAN Rx FIFO transfer structure. See the ref flexcan_fifo_transfer_t.@ + * @retval kStatus_Success - Start Rx FIFO receiving process successfully. + * @retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use. + */ +status_t FLEXCAN_TransferReceiveEnhancedFifoNonBlocking(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer); + +/*! + * @brief Gets the Enhanced Rx Fifo transfer status during a interrupt non-blocking receive. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param count Number of CAN messages receive so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ + +static inline status_t FLEXCAN_TransferGetReceiveEnhancedFifoCount(CAN_Type *base, + flexcan_handle_t *handle, + size_t *count) +{ + return FLEXCAN_TransferGetReceiveFifoCount(base, handle, count); +} +#endif + +/*! + * @brief Gets the detail index of Mailbox's Timestamp by handle. + * + * Then function can only be used when calling non-blocking Data transfer (TX/RX) API, + * After TX/RX data transfer done (User can get the status by handler's callback function), + * we can get the detail index of Mailbox's timestamp by handle, + * Detail non-blocking data transfer API (TX/RX) contain. + * -FLEXCAN_TransferSendNonBlocking + * -FLEXCAN_TransferFDSendNonBlocking + * -FLEXCAN_TransferReceiveNonBlocking + * -FLEXCAN_TransferFDReceiveNonBlocking + * -FLEXCAN_TransferReceiveFifoNonBlocking + * + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN Message Buffer index. + * @retval the index of mailbox 's timestamp stored in the handle. + * + */ +uint32_t FLEXCAN_GetTimeStamp(flexcan_handle_t *handle, uint8_t mbIdx); + +/*! + * @brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN Message Buffer index. + */ +void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); + +/*! + * @brief Aborts the interrupt driven message receive process. + * + * This function aborts the interrupt driven message receive process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN Message Buffer index. + */ +void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); + +/*! + * @brief Aborts the interrupt driven message receive from Rx FIFO process. + * + * This function aborts the interrupt driven message receive from Rx FIFO process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Aborts the interrupt driven message receive from Enhanced Rx FIFO process. + * + * This function aborts the interrupt driven message receive from Enhanced Rx FIFO process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferAbortReceiveEnhancedFifo(CAN_Type *base, flexcan_handle_t *handle); +#endif + +/*! + * @brief FlexCAN IRQ handle function. + * + * This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_FLEXCAN_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexcan_edma.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexcan_edma.c new file mode 100644 index 00000000000..a5f68487f31 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexcan_edma.c @@ -0,0 +1,381 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexcan_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcan_edma" +#endif + +/*base->ERFCR & CAN_ERFCR_ERFEN_MASK)) + { + framefd = flexcanPrivateHandle->handle->framefd; + for (uint32_t i = 0; i < flexcanPrivateHandle->handle->frameNum; i++) + { + /* Enhanced Rx FIFO ID HIT offset is changed dynamically according to data length code (DLC) . */ + idHitIndex = (DLC_LENGTH_DECODE(framefd->length) + 3U) / 4U; + framefd->idhit = framefd->dataWord[idHitIndex]; + /* Clear the unused frame data. */ + for (uint32_t j = idHitIndex; j < 16U; j++) + { + framefd->dataWord[j] = 0x0U; + } + framefd++; + } + } +#endif + /* Disable transfer. */ + FLEXCAN_TransferAbortReceiveFifoEDMA(flexcanPrivateHandle->base, flexcanPrivateHandle->handle); + + if (NULL != flexcanPrivateHandle->handle->callback) + { + flexcanPrivateHandle->handle->callback(flexcanPrivateHandle->base, flexcanPrivateHandle->handle, + kStatus_FLEXCAN_RxFifoIdle, flexcanPrivateHandle->handle->userData); + } + } +} + +/*! + * brief Initializes the FlexCAN handle, which is used in transactional functions. + * + * param base FlexCAN peripheral base address. + * param handle Pointer to flexcan_edma_handle_t structure. + * param callback The callback function. + * param userData The parameter of the callback function. + * param rxFifoEdmaHandle User-requested DMA handle for Rx FIFO DMA transfer. + */ +void FLEXCAN_TransferCreateHandleEDMA(CAN_Type *base, + flexcan_edma_handle_t *handle, + flexcan_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *rxFifoEdmaHandle) +{ + assert(NULL != handle); + + uint32_t instance = FLEXCAN_GetInstance(base); + s_flexcanEdmaPrivateHandle[instance].base = base; + s_flexcanEdmaPrivateHandle[instance].handle = handle; + + (void)memset(handle, 0, sizeof(flexcan_edma_handle_t)); + + handle->rxFifoState = (uint8_t)KFLEXCAN_RxFifoIdle; + handle->rxFifoEdmaHandle = rxFifoEdmaHandle; + + /* Register Callback. */ + handle->callback = callback; + handle->userData = userData; + + /* Configure Legacy/Enhanced Rx FIFO DMA callback. */ + EDMA_SetCallback(handle->rxFifoEdmaHandle, FLEXCAN_ReceiveFifoEDMACallback, &s_flexcanEdmaPrivateHandle[instance]); +} + +/*! + * brief Prepares the eDMA transfer configuration for FLEXCAN Legacy RX FIFO. + * + * This function prepares the eDMA transfer configuration structure according to FLEXCAN Legacy RX FIFO. + * + * param base FlexCAN peripheral base address. + * param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t. + * param pEdmaConfig The user configuration structure of type edma_transfer_t. + * + */ +void FLEXCAN_PrepareTransfConfiguration(CAN_Type *base, + flexcan_fifo_transfer_t *pFifoXfer, + edma_transfer_config_t *pEdmaConfig) +{ + assert(NULL != pFifoXfer); + assert(NULL != pFifoXfer->frame); + assert(NULL != pEdmaConfig); + + flexcan_frame_t *fifoAddr = (flexcan_frame_t *)FLEXCAN_GetRxFifoHeadAddr(base); + +#if (defined(FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) + EDMA_PrepareTransfer(pEdmaConfig, (void *)fifoAddr, sizeof(flexcan_frame_t), (void *)pFifoXfer->frame, + sizeof(uint32_t), sizeof(flexcan_frame_t), sizeof(flexcan_frame_t) * pFifoXfer->frameNum, + kEDMA_PeripheralToMemory); +#else + /* The Data Size of FLEXCAN Legacy RX FIFO output port is 16 Bytes, but lots of chips not support 16Bytes width DMA + * transfer. These chips always support 4Byte width memory transfer, so we need prepare Memory to Memory mode by 4 + * Bytes width mode. + */ + EDMA_PrepareTransfer(pEdmaConfig, (void *)fifoAddr, 4U, (void *)pFifoXfer->frame, sizeof(uint32_t), + sizeof(flexcan_frame_t), sizeof(flexcan_frame_t) * pFifoXfer->frameNum, kEDMA_MemoryToMemory); +#endif +} + +/*! + * brief Start Transfer Data from the FLEXCAN Legacy Rx FIFO using eDMA. + * + * This function to Update edma transfer confiugration and Start eDMA transfer + * + * param base FlexCAN peripheral base address. + * param handle Pointer to flexcan_edma_handle_t structure. + * param pEdmaConfig The user configuration structure of type edma_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing. + */ +status_t FLEXCAN_StartTransferDatafromRxFIFO(CAN_Type *base, + flexcan_edma_handle_t *handle, + edma_transfer_config_t *pEdmaConfig) +{ + assert(NULL != handle->rxFifoEdmaHandle); + assert(NULL != pEdmaConfig); + status_t status; + + /* If previous Rx FIFO receive not finished. */ + if ((uint8_t)KFLEXCAN_RxFifoBusy == handle->rxFifoState) + { + status = kStatus_FLEXCAN_RxFifoBusy; + } + else + { + handle->rxFifoState = (uint8_t)KFLEXCAN_RxFifoBusy; + + /* Enable FlexCAN Rx FIFO EDMA. */ + FLEXCAN_EnableRxFifoDMA(base, true); + + /* Submit configuration. */ + (void)EDMA_SubmitTransfer(handle->rxFifoEdmaHandle, (const edma_transfer_config_t *)pEdmaConfig); + EDMA_SetModulo(handle->rxFifoEdmaHandle->base, handle->rxFifoEdmaHandle->channel, kEDMA_Modulo16bytes, + kEDMA_ModuloDisable); + /* Start transfer. */ + EDMA_StartTransfer(handle->rxFifoEdmaHandle); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Receives the CAN Messages from the Legacy Rx FIFO using eDMA. + * + * This function receives the CAN Message using eDMA. This is a non-blocking function, which returns + * right away. After the CAN Message is received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle Pointer to flexcan_edma_handle_t structure. + * param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing. + */ +status_t FLEXCAN_TransferReceiveFifoEDMA(CAN_Type *base, + flexcan_edma_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer) +{ + assert(NULL != handle->rxFifoEdmaHandle); + assert(NULL != pFifoXfer->frame); + + edma_transfer_config_t dmaXferConfig = {0}; + status_t status; + + handle->frameNum = pFifoXfer->frameNum; + /* Prepare transfer. */ + FLEXCAN_PrepareTransfConfiguration(base, pFifoXfer, &dmaXferConfig); + + /* Submit configuration and start edma transfer. */ + status = FLEXCAN_StartTransferDatafromRxFIFO(base, handle, &dmaXferConfig); + + return status; +} + +/*! + * brief Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param count Number of CAN messages receive so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ + +status_t FLEXCAN_TransferGetReceiveFifoCountEMDA(CAN_Type *base, flexcan_edma_handle_t *handle, size_t *count) +{ + assert(NULL != handle); + + status_t result = kStatus_Success; + + if (handle->rxFifoState == (uint32_t)KFLEXCAN_RxFifoIdle) + { + result = kStatus_NoTransferInProgress; + } + else + { + *count = handle->frameNum - + EDMA_GetRemainingMajorLoopCount(handle->rxFifoEdmaHandle->base, handle->rxFifoEdmaHandle->channel); + } + + return result; +} + +/*! + * brief Aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA. + * + * This function aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA. + * + * param base FlexCAN peripheral base address. + * param handle Pointer to flexcan_edma_handle_t structure. + */ +void FLEXCAN_TransferAbortReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle) +{ + assert(NULL != handle->rxFifoEdmaHandle); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->rxFifoEdmaHandle); + + handle->rxFifoState = (uint8_t)KFLEXCAN_RxFifoIdle; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + handle->framefd = NULL; +#endif + handle->frameNum = 0U; + /* Disable FlexCAN Legacy/Enhanced Rx FIFO EDMA. */ + FLEXCAN_EnableRxFifoDMA(base, false); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * brief Receives the CAN FD Message from the Enhanced Rx FIFO using eDMA. + * + * This function receives the CAN FD Message using eDMA. This is a non-blocking function, which returns + * right away. After the CAN Message is received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle Pointer to flexcan_edma_handle_t structure. + * param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing. + * retval kStatus_InvalidArgument The watermark configuration is invalid, the watermark need be set to + 1 to do successfully EDMA transfer with this API. + */ +status_t FLEXCAN_TransferReceiveEnhancedFifoEDMA(CAN_Type *base, + flexcan_edma_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer) +{ + assert(NULL != handle->rxFifoEdmaHandle); + assert(NULL != pFifoXfer->framefd); + + edma_transfer_config_t dmaXferConfig; + edma_minor_offset_config_t dmaMinorOffsetConfig; + status_t status; + flexcan_fd_frame_t *fifoAddr = (flexcan_fd_frame_t *)E_RX_FIFO(base); + uint32_t perReadWords = ((base->ERFCR & CAN_ERFCR_DMALW_MASK) >> CAN_ERFCR_DMALW_SHIFT) + 1U; + uint32_t watermark = ((base->ERFCR & CAN_ERFCR_ERFWM_MASK) >> CAN_ERFCR_ERFWM_SHIFT) + 1U; + + /* If previous Rx FIFO receive not finished. */ + if ((uint8_t)KFLEXCAN_RxFifoBusy == handle->rxFifoState) + { + status = kStatus_FLEXCAN_RxFifoBusy; + } + else + { + handle->frameNum = pFifoXfer->frameNum; + handle->framefd = pFifoXfer->framefd; + /*!< To reduce the complexity of DMA software configuration, need to set watermark to 1 to make that each DMA + request read once Rx FIFO. Because a DMA transfer cannot be dynamically changed, Number of words read per + transfer (ERFCR[DMALW] + 1) should be programmed so that the Enhanced Rx FIFO element can store the largest + CAN message present on the CAN bus. */ + if ((watermark != 1U) || ((sizeof(uint32_t) * perReadWords) != sizeof(flexcan_fd_frame_t))) + { + return kStatus_InvalidArgument; + } + + /* Prepare transfer. */ + EDMA_PrepareTransfer( + &dmaXferConfig, (void *)fifoAddr, sizeof(uint32_t), (void *)pFifoXfer->framefd, sizeof(uint32_t), + sizeof(uint32_t) * perReadWords, /* minor loop bytes : 4* perReadWords */ + sizeof(uint32_t) * perReadWords * handle->frameNum, /* major loop counts : handle->frameNum */ + kEDMA_MemoryToMemory); + /* Submit configuration. */ + (void)EDMA_SubmitTransfer(handle->rxFifoEdmaHandle, &dmaXferConfig); + + dmaMinorOffsetConfig.enableDestMinorOffset = false; + dmaMinorOffsetConfig.enableSrcMinorOffset = true; + dmaMinorOffsetConfig.minorOffset = 128U - sizeof(uint32_t) * perReadWords; + EDMA_SetMinorOffsetConfig(handle->rxFifoEdmaHandle->base, handle->rxFifoEdmaHandle->channel, + &dmaMinorOffsetConfig); + + EDMA_SetModulo(handle->rxFifoEdmaHandle->base, handle->rxFifoEdmaHandle->channel, kEDMA_Modulo128bytes, + kEDMA_ModuloDisable); + + handle->rxFifoState = (uint8_t)KFLEXCAN_RxFifoBusy; + + /* Enable FlexCAN Rx FIFO EDMA. */ + FLEXCAN_EnableRxFifoDMA(base, true); + /* Start transfer. */ + EDMA_StartTransfer(handle->rxFifoEdmaHandle); + + status = kStatus_Success; + } + + return status; +} +#endif diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexcan_edma.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexcan_edma.h new file mode 100644 index 00000000000..90d78ef6690 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexcan_edma.h @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_FLEXCAN_EDMA_H_ +#define FSL_FLEXCAN_EDMA_H_ + +#include "fsl_flexcan.h" +#include "fsl_edma.h" + +/*! + * @addtogroup flexcan_edma_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief FlexCAN EDMA driver version. */ +#define FSL_FLEXCAN_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 11, 3)) +/*! @} */ + +/* Forward declaration of the handle typedef. */ +typedef struct _flexcan_edma_handle flexcan_edma_handle_t; + +/*! @brief FlexCAN transfer callback function. */ +typedef void (*flexcan_edma_transfer_callback_t)(CAN_Type *base, + flexcan_edma_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief FlexCAN eDMA handle + */ +struct _flexcan_edma_handle +{ + flexcan_edma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< FlexCAN callback function parameter.*/ + edma_handle_t *rxFifoEdmaHandle; /*!< The EDMA handler for Rx FIFO. */ + volatile uint8_t rxFifoState; /*!< Rx FIFO transfer state. */ + size_t frameNum; /*!< The number of messages that need to be received. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + flexcan_fd_frame_t *framefd; /*!< Point to the buffer of CAN Message to be received from Enhanced Rx FIFO. */ +#endif +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA transactional + * @{ + */ + +/*! + * @brief Initializes the FlexCAN handle, which is used in transactional functions. + * + * @param base FlexCAN peripheral base address. + * @param handle Pointer to flexcan_edma_handle_t structure. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @param rxFifoEdmaHandle User-requested DMA handle for Rx FIFO DMA transfer. + */ +void FLEXCAN_TransferCreateHandleEDMA(CAN_Type *base, + flexcan_edma_handle_t *handle, + flexcan_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *rxFifoEdmaHandle); + +/*! + * @brief Prepares the eDMA transfer configuration for FLEXCAN Legacy RX FIFO. + * + * This function prepares the eDMA transfer configuration structure according to FLEXCAN Legacy RX FIFO. + * + * @param base FlexCAN peripheral base address. + * @param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t. + * @param pEdmaConfig The user configuration structure of type edma_transfer_t. + * + */ +void FLEXCAN_PrepareTransfConfiguration(CAN_Type *base, + flexcan_fifo_transfer_t *pFifoXfer, + edma_transfer_config_t *pEdmaConfig); + +/*! + * @brief Start Transfer Data from the FLEXCAN Legacy Rx FIFO using eDMA. + * + * This function to Update edma transfer confiugration and Start eDMA transfer + * + * @param base FlexCAN peripheral base address. + * @param handle Pointer to flexcan_edma_handle_t structure. + * @param pEdmaConfig The user configuration structure of type edma_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing. + */ +status_t FLEXCAN_StartTransferDatafromRxFIFO(CAN_Type *base, + flexcan_edma_handle_t *handle, + edma_transfer_config_t *pEdmaConfig); + +/*! + * @brief Receives the CAN Message from the Legacy Rx FIFO using eDMA. + * + * This function receives the CAN Message using eDMA. This is a non-blocking function, which returns + * right away. After the CAN Message is received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle Pointer to flexcan_edma_handle_t structure. + * @param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing. + */ +status_t FLEXCAN_TransferReceiveFifoEDMA(CAN_Type *base, + flexcan_edma_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer); +/*! + * @brief Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param count Number of CAN messages receive so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ + +status_t FLEXCAN_TransferGetReceiveFifoCountEMDA(CAN_Type *base, flexcan_edma_handle_t *handle, size_t *count); +/*! + * @brief Aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA. + * + * This function aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA. + * + * @param base FlexCAN peripheral base address. + * @param handle Pointer to flexcan_edma_handle_t structure. + */ +void FLEXCAN_TransferAbortReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Receives the CAN FD Message from the Enhanced Rx FIFO using eDMA. + * + * This function receives the CAN FD Message using eDMA. This is a non-blocking function, which returns + * right away. After the CAN Message is received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle Pointer to flexcan_edma_handle_t structure. + * @param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing. + */ +status_t FLEXCAN_TransferReceiveEnhancedFifoEDMA(CAN_Type *base, + flexcan_edma_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer); +/*! + * @brief Gets the Enhanced Rx Fifo transfer status during a interrupt non-blocking receive. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param count Number of CAN messages receive so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ + +static inline status_t FLEXCAN_TransferGetReceiveEnhancedFifoCountEMDA(CAN_Type *base, + flexcan_edma_handle_t *handle, + size_t *count) +{ + return FLEXCAN_TransferGetReceiveFifoCountEMDA(base, handle, count); +} +#endif + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_FLEXCAN_EDMA_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio.c new file mode 100644 index 00000000000..52741f2a4de --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio.c @@ -0,0 +1,511 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio" +#endif + +/*< @brief user configurable flexio handle count. */ +#define FLEXIO_HANDLE_COUNT 2 + +#if defined(FLEXIO_RSTS) +#define FLEXIO_RESETS_ARRAY FLEXIO_RSTS +#elif defined(FLEXIO_RSTS_N) +#define FLEXIO_RESETS_ARRAY FLEXIO_RSTS_N +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to flexio bases for each instance. */ +FLEXIO_Type *const s_flexioBases[] = FLEXIO_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to flexio clocks for each instance. */ +const clock_ip_name_t s_flexioClocks[] = FLEXIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*< @brief pointer to array of FLEXIO handle. */ +static void *s_flexioHandle[FLEXIO_HANDLE_COUNT]; + +/*< @brief pointer to array of FLEXIO IP types. */ +static void *s_flexioType[FLEXIO_HANDLE_COUNT]; + +/*< @brief pointer to array of FLEXIO Isr. */ +static flexio_isr_t s_flexioIsr[FLEXIO_HANDLE_COUNT]; + +/* FlexIO common IRQ Handler. */ +static void FLEXIO_CommonIRQHandler(void); + +#if defined(FLEXIO_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_flexioResets[] = FLEXIO_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Codes + ******************************************************************************/ + +/*! + * brief Get instance number for FLEXIO module. + * + * param base FLEXIO peripheral base address. + */ +uint32_t FLEXIO_GetInstance(FLEXIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_flexioBases); instance++) + { + if (s_flexioBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_flexioBases)); + + return instance; +} + +/*! + * brief Configures the FlexIO with a FlexIO configuration. The configuration structure + * can be filled by the user or be set with default values by FLEXIO_GetDefaultConfig(). + * + * Example + code + flexio_config_t config = { + .enableFlexio = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false + }; + FLEXIO_Configure(base, &config); + endcode + * + * param base FlexIO peripheral base address + * param userConfig pointer to flexio_config_t structure +*/ +void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig) +{ + uint32_t ctrlReg = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_EnableClock(s_flexioClocks[FLEXIO_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FLEXIO_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_flexioResets[FLEXIO_GetInstance(base)]); +#endif + + FLEXIO_Reset(base); + + ctrlReg = base->CTRL; + ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + ctrlReg |= (FLEXIO_CTRL_DBGE(userConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(userConfig->enableFastAccess) | + FLEXIO_CTRL_FLEXEN(userConfig->enableFlexio)); + if (!userConfig->enableInDoze) + { + ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; + } + + base->CTRL = ctrlReg; +} + +/*! + * brief Gates the FlexIO clock. Call this API to stop the FlexIO clock. + * + * note After calling this API, call the FLEXO_Init to use the FlexIO module. + * + * param base FlexIO peripheral base address + */ +void FLEXIO_Deinit(FLEXIO_Type *base) +{ + FLEXIO_Enable(base, false); +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + CLOCK_DisableClock(s_flexioClocks[FLEXIO_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Gets the default configuration to configure the FlexIO module. The configuration + * can used directly to call the FLEXIO_Configure(). + * + * Example: + code + flexio_config_t config; + FLEXIO_GetDefaultConfig(&config); + endcode + * + * param userConfig pointer to flexio_config_t structure +*/ +void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig) +{ + assert(userConfig != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(userConfig, 0, sizeof(*userConfig)); + + userConfig->enableFlexio = true; + userConfig->enableInDoze = false; + userConfig->enableInDebug = true; + userConfig->enableFastAccess = false; +} + +/*! + * brief Resets the FlexIO module. + * + * param base FlexIO peripheral base address + */ +void FLEXIO_Reset(FLEXIO_Type *base) +{ + /*do software reset, software reset operation affect all other FLEXIO registers except CTRL*/ + base->CTRL |= FLEXIO_CTRL_SWRST_MASK; + base->CTRL = 0; +} + +/*! + * brief Gets the shifter buffer address for the DMA transfer usage. + * + * param base FlexIO peripheral base address + * param type Shifter type of flexio_shifter_buffer_type_t + * param index Shifter index + * return Corresponding shifter buffer index + */ +uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index) +{ + assert(index < FLEXIO_SHIFTBUF_COUNT); + + uint32_t address = 0; + + switch (type) + { + case kFLEXIO_ShifterBuffer: + address = (uint32_t) & (base->SHIFTBUF[index]); + break; + + case kFLEXIO_ShifterBufferBitSwapped: + address = (uint32_t) & (base->SHIFTBUFBIS[index]); + break; + + case kFLEXIO_ShifterBufferByteSwapped: + address = (uint32_t) & (base->SHIFTBUFBYS[index]); + break; + + case kFLEXIO_ShifterBufferBitByteSwapped: + address = (uint32_t) & (base->SHIFTBUFBBS[index]); + break; + +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP + case kFLEXIO_ShifterBufferNibbleByteSwapped: + address = (uint32_t) & (base->SHIFTBUFNBS[index]); + break; + +#endif +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP + case kFLEXIO_ShifterBufferHalfWordSwapped: + address = (uint32_t) & (base->SHIFTBUFHWS[index]); + break; + +#endif +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP + case kFLEXIO_ShifterBufferNibbleSwapped: + address = (uint32_t) & (base->SHIFTBUFNIS[index]); + break; + +#endif + default: + address = (uint32_t) & (base->SHIFTBUF[index]); + break; + } + return address; +} + +/*! + * brief Configures the shifter with the shifter configuration. The configuration structure + * covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper + * mode, select which timer controls the shifter to shift, whether to generate start bit/stop + * bit, and the polarity of start bit and stop bit. + * + * Example + code + flexio_shifter_config_t config = { + .timerSelect = 0, + .timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive, + .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, + .pinPolarity = kFLEXIO_PinActiveLow, + .shifterMode = kFLEXIO_ShifterModeTransmit, + .inputSource = kFLEXIO_ShifterInputFromPin, + .shifterStop = kFLEXIO_ShifterStopBitHigh, + .shifterStart = kFLEXIO_ShifterStartBitLow + }; + FLEXIO_SetShifterConfig(base, &config); + endcode + * + * param base FlexIO peripheral base address + * param index Shifter index + * param shifterConfig Pointer to flexio_shifter_config_t structure +*/ +void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig) +{ + base->SHIFTCFG[index] = FLEXIO_SHIFTCFG_INSRC(shifterConfig->inputSource) +#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH + | FLEXIO_SHIFTCFG_PWIDTH(shifterConfig->parallelWidth) +#endif /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */ + | FLEXIO_SHIFTCFG_SSTOP(shifterConfig->shifterStop) | + FLEXIO_SHIFTCFG_SSTART(shifterConfig->shifterStart); + + base->SHIFTCTL[index] = + FLEXIO_SHIFTCTL_TIMSEL(shifterConfig->timerSelect) | FLEXIO_SHIFTCTL_TIMPOL(shifterConfig->timerPolarity) | + FLEXIO_SHIFTCTL_PINCFG(shifterConfig->pinConfig) | FLEXIO_SHIFTCTL_PINSEL(shifterConfig->pinSelect) | + FLEXIO_SHIFTCTL_PINPOL(shifterConfig->pinPolarity) | FLEXIO_SHIFTCTL_SMOD(shifterConfig->shifterMode); +} + +/*! + * brief Configures the timer with the timer configuration. The configuration structure + * covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper + * mode, select trigger source for timer and the timer pin output and the timing for timer. + * + * Example + code + flexio_timer_config_t config = { + .triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0), + .triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow, + .triggerSource = kFLEXIO_TimerTriggerSourceInternal, + .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, + .pinSelect = 0, + .pinPolarity = kFLEXIO_PinActiveHigh, + .timerMode = kFLEXIO_TimerModeDual8BitBaudBit, + .timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset, + .timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput, + .timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput, + .timerDisable = kFLEXIO_TimerDisableOnTimerCompare, + .timerEnable = kFLEXIO_TimerEnableOnTriggerHigh, + .timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable, + .timerStart = kFLEXIO_TimerStartBitEnabled + }; + FLEXIO_SetTimerConfig(base, &config); + endcode + * + * param base FlexIO peripheral base address + * param index Timer index + * param timerConfig Pointer to the flexio_timer_config_t structure +*/ +void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig) +{ + base->TIMCFG[index] = + FLEXIO_TIMCFG_TIMOUT(timerConfig->timerOutput) | FLEXIO_TIMCFG_TIMDEC(timerConfig->timerDecrement) | + FLEXIO_TIMCFG_TIMRST(timerConfig->timerReset) | FLEXIO_TIMCFG_TIMDIS(timerConfig->timerDisable) | + FLEXIO_TIMCFG_TIMENA(timerConfig->timerEnable) | FLEXIO_TIMCFG_TSTOP(timerConfig->timerStop) | + FLEXIO_TIMCFG_TSTART(timerConfig->timerStart); + + base->TIMCMP[index] = FLEXIO_TIMCMP_CMP(timerConfig->timerCompare); + + base->TIMCTL[index] = FLEXIO_TIMCTL_TRGSEL(timerConfig->triggerSelect) | + FLEXIO_TIMCTL_TRGPOL(timerConfig->triggerPolarity) | + FLEXIO_TIMCTL_TRGSRC(timerConfig->triggerSource) | + FLEXIO_TIMCTL_PINCFG(timerConfig->pinConfig) | FLEXIO_TIMCTL_PINSEL(timerConfig->pinSelect) | + FLEXIO_TIMCTL_PINPOL(timerConfig->pinPolarity) | FLEXIO_TIMCTL_TIMOD(timerConfig->timerMode); +} + +/*! + * brief Registers the handle and the interrupt handler for the FlexIO-simulated peripheral. + * + * param base Pointer to the FlexIO simulated peripheral type. + * param handle Pointer to the handler for FlexIO simulated peripheral. + * param isr FlexIO simulated peripheral interrupt handler. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr) +{ + assert(base != NULL); + assert(handle != NULL); + assert(isr != NULL); + + uint8_t index; + + /* Find the an empty handle pointer to store the handle. */ + for (index = 0U; index < (uint8_t)FLEXIO_HANDLE_COUNT; index++) + { + if (s_flexioHandle[index] == NULL) + { + /* Register FLEXIO simulated driver base, handle and isr. */ + s_flexioType[index] = base; + s_flexioHandle[index] = handle; + s_flexioIsr[index] = isr; + break; + } + } + + if (index == (uint8_t)FLEXIO_HANDLE_COUNT) + { + return kStatus_OutOfRange; + } + else + { + return kStatus_Success; + } +} + +/*! + * brief Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral. + * + * param base Pointer to the FlexIO simulated peripheral type. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_UnregisterHandleIRQ(void *base) +{ + assert(base != NULL); + + uint8_t index; + + /* Find the index from base address mappings. */ + for (index = 0U; index < (uint8_t)FLEXIO_HANDLE_COUNT; index++) + { + if (s_flexioType[index] == base) + { + /* Unregister FLEXIO simulated driver handle and isr. */ + s_flexioType[index] = NULL; + s_flexioHandle[index] = NULL; + s_flexioIsr[index] = NULL; + break; + } + } + + if (index == (uint8_t)FLEXIO_HANDLE_COUNT) + { + return kStatus_OutOfRange; + } + else + { + return kStatus_Success; + } +} + +static void FLEXIO_CommonIRQHandler(void) +{ + uint8_t index; + + for (index = 0U; index < (uint8_t)FLEXIO_HANDLE_COUNT; index++) + { + if (s_flexioHandle[index] != NULL) + { + s_flexioIsr[index](s_flexioType[index], s_flexioHandle[index]); + } + } + SDK_ISR_EXIT_BARRIER; +} + +#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER) && FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER +/*! + * brief Configure a FLEXIO pin used by the board. + * + * To Config the FLEXIO PIN, define a pin configuration, as either input or output, in the user file. + * Then, call the FLEXIO_SetPinConfig() function. + * + * This is an example to define an input pin or an output pin configuration. + * code + * Define a digital input pin configuration, + * flexio_gpio_config_t config = + * { + * kFLEXIO_DigitalInput, + * 0U, + * kFLEXIO_FlagRisingEdgeEnable | kFLEXIO_InputInterruptEnable, + * } + * Define a digital output pin configuration, + * flexio_gpio_config_t config = + * { + * kFLEXIO_DigitalOutput, + * 0U, + * 0U + * } + * endcode + * param base FlexIO peripheral base address + * param pin FLEXIO pin number. + * param config FLEXIO pin configuration pointer. + */ +void FLEXIO_SetPinConfig(FLEXIO_Type *base, uint32_t pin, flexio_gpio_config_t *config) +{ + assert(NULL != config); + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + if (config->pinDirection == kFLEXIO_DigitalInput) + { + base->PINOUTE &= ~(1UL << pin); + if (0U != (config->inputConfig & (uint8_t)kFLEXIO_InputInterruptEnable)) + { + base->PINIEN = 1UL << pin; + /* Clear pending NVIC IRQ before enable NVIC IRQ. */ + NVIC_ClearPendingIRQ(flexio_irqs[FLEXIO_GetInstance(base)]); + /* Enable interrupt in NVIC. */ + (void)EnableIRQ(flexio_irqs[FLEXIO_GetInstance(base)]); + } + + if (0U != (config->inputConfig & (uint8_t)kFLEXIO_FlagRisingEdgeEnable)) + { + base->PINREN = 1UL << pin; + } + + if (0U != (config->inputConfig & (uint8_t)kFLEXIO_FlagFallingEdgeEnable)) + { + base->PINFEN = 1UL << pin; + } + } + else + { + FLEXIO_EnablePinOutput(base, pin); + FLEXIO_PinWrite(base, pin, config->outputLogic); + } +} +#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER*/ + +void FLEXIO_DriverIRQHandler(void); +void FLEXIO_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void FLEXIO0_DriverIRQHandler(void); +void FLEXIO0_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void FLEXIO1_DriverIRQHandler(void); +void FLEXIO1_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void UART2_FLEXIO_DriverIRQHandler(void); +void UART2_FLEXIO_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void FLEXIO2_DriverIRQHandler(void); +void FLEXIO2_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} + +void FLEXIO3_DriverIRQHandler(void); +void FLEXIO3_DriverIRQHandler(void) +{ + FLEXIO_CommonIRQHandler(); +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio.h new file mode 100644 index 00000000000..1e1bc6278d0 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio.h @@ -0,0 +1,917 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020, 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_FLEXIO_H_ +#define FSL_FLEXIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexio_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief FlexIO driver version. */ +#define FSL_FLEXIO_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) +/*! @} */ + +/*! @brief Calculate FlexIO timer trigger.*/ +#define FLEXIO_TIMER_TRIGGER_SEL_PININPUT(x) ((uint32_t)(x) << 1U) +#define FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(x) (((uint32_t)(x) << 2U) | 0x1U) +#define FLEXIO_TIMER_TRIGGER_SEL_TIMn(x) (((uint32_t)(x) << 2U) | 0x3U) + +/*! @brief Define time of timer trigger polarity.*/ +typedef enum _flexio_timer_trigger_polarity +{ + kFLEXIO_TimerTriggerPolarityActiveHigh = 0x0U, /*!< Active high. */ + kFLEXIO_TimerTriggerPolarityActiveLow = 0x1U, /*!< Active low. */ +} flexio_timer_trigger_polarity_t; + +/*! @brief Define type of timer trigger source.*/ +typedef enum _flexio_timer_trigger_source +{ + kFLEXIO_TimerTriggerSourceExternal = 0x0U, /*!< External trigger selected. */ + kFLEXIO_TimerTriggerSourceInternal = 0x1U, /*!< Internal trigger selected. */ +} flexio_timer_trigger_source_t; + +/*! @brief Define type of timer/shifter pin configuration.*/ +typedef enum _flexio_pin_config +{ + kFLEXIO_PinConfigOutputDisabled = 0x0U, /*!< Pin output disabled. */ + kFLEXIO_PinConfigOpenDrainOrBidirection = 0x1U, /*!< Pin open drain or bidirectional output enable. */ + kFLEXIO_PinConfigBidirectionOutputData = 0x2U, /*!< Pin bidirectional output data. */ + kFLEXIO_PinConfigOutput = 0x3U, /*!< Pin output. */ +} flexio_pin_config_t; + +/*! @brief Definition of pin polarity.*/ +typedef enum _flexio_pin_polarity +{ + kFLEXIO_PinActiveHigh = 0x0U, /*!< Active high. */ + kFLEXIO_PinActiveLow = 0x1U, /*!< Active low. */ +} flexio_pin_polarity_t; + +/*! @brief Define type of timer work mode.*/ +typedef enum _flexio_timer_mode +{ + kFLEXIO_TimerModeDisabled = 0x0U, /*!< Timer Disabled. */ + kFLEXIO_TimerModeDual8BitBaudBit = 0x1U, /*!< Dual 8-bit counters baud/bit mode. */ + kFLEXIO_TimerModeDual8BitPWM = 0x2U, /*!< Dual 8-bit counters PWM mode. */ + kFLEXIO_TimerModeSingle16Bit = 0x3U, /*!< Single 16-bit counter mode. */ +} flexio_timer_mode_t; + +/*! @brief Define type of timer initial output or timer reset condition.*/ +typedef enum _flexio_timer_output +{ + kFLEXIO_TimerOutputOneNotAffectedByReset = 0x0U, /*!< Logic one when enabled and is not affected by timer + reset. */ + kFLEXIO_TimerOutputZeroNotAffectedByReset = 0x1U, /*!< Logic zero when enabled and is not affected by timer + reset. */ + kFLEXIO_TimerOutputOneAffectedByReset = 0x2U, /*!< Logic one when enabled and on timer reset. */ + kFLEXIO_TimerOutputZeroAffectedByReset = 0x3U, /*!< Logic zero when enabled and on timer reset. */ +} flexio_timer_output_t; + +/*! @brief Define type of timer decrement.*/ +typedef enum _flexio_timer_decrement_source +{ + kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput = 0x0U, /*!< Decrement counter on FlexIO clock, Shift clock + equals Timer output. */ + kFLEXIO_TimerDecSrcOnTriggerInputShiftTimerOutput, /*!< Decrement counter on Trigger input (both edges), + Shift clock equals Timer output. */ + kFLEXIO_TimerDecSrcOnPinInputShiftPinInput, /*!< Decrement counter on Pin input (both edges), + Shift clock equals Pin input. */ + kFLEXIO_TimerDecSrcOnTriggerInputShiftTriggerInput /*!< Decrement counter on Trigger input (both edges), + Shift clock equals Trigger input. */ +#if (defined(FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH) && (FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH == 3)) + , + kFLEXIO_TimerDecSrcDiv16OnFlexIOClockShiftTimerOutput, /*!< Decrement counter on FlexIO clock divided by 16, + Shift clock equals Timer output. */ + kFLEXIO_TimerDecSrcDiv256OnFlexIOClockShiftTimerOutput, /*!< Decrement counter on FlexIO clock divided by 256, + Shift clock equals Timer output. */ + kFLEXIO_TimerRisSrcOnPinInputShiftPinInput, /*!< Decrement counter on Pin input (rising edges), + Shift clock equals Pin input. */ + kFLEXIO_TimerRisSrcOnTriggerInputShiftTriggerInput /*!< Decrement counter on Trigger input (rising edges), Shift + clock equals Trigger input. */ +#endif /* FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH */ +} flexio_timer_decrement_source_t; + +/*! @brief Define type of timer reset condition.*/ +typedef enum _flexio_timer_reset_condition +{ + kFLEXIO_TimerResetNever = 0x0U, /*!< Timer never reset. */ + kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput = 0x2U, /*!< Timer reset on Timer Pin equal to Timer Output. */ + kFLEXIO_TimerResetOnTimerTriggerEqualToTimerOutput = 0x3U, /*!< Timer reset on Timer Trigger equal to + Timer Output. */ + kFLEXIO_TimerResetOnTimerPinRisingEdge = 0x4U, /*!< Timer reset on Timer Pin rising edge. */ + kFLEXIO_TimerResetOnTimerTriggerRisingEdge = 0x6U, /*!< Timer reset on Trigger rising edge. */ + kFLEXIO_TimerResetOnTimerTriggerBothEdge = 0x7U, /*!< Timer reset on Trigger rising or falling edge. */ +} flexio_timer_reset_condition_t; + +/*! @brief Define type of timer disable condition.*/ +typedef enum _flexio_timer_disable_condition +{ + kFLEXIO_TimerDisableNever = 0x0U, /*!< Timer never disabled. */ + kFLEXIO_TimerDisableOnPreTimerDisable = 0x1U, /*!< Timer disabled on Timer N-1 disable. */ + kFLEXIO_TimerDisableOnTimerCompare = 0x2U, /*!< Timer disabled on Timer compare. */ + kFLEXIO_TimerDisableOnTimerCompareTriggerLow = 0x3U, /*!< Timer disabled on Timer compare and Trigger Low. */ + kFLEXIO_TimerDisableOnPinBothEdge = 0x4U, /*!< Timer disabled on Pin rising or falling edge. */ + kFLEXIO_TimerDisableOnPinBothEdgeTriggerHigh = 0x5U, /*!< Timer disabled on Pin rising or falling edge provided + Trigger is high. */ + kFLEXIO_TimerDisableOnTriggerFallingEdge = 0x6U, /*!< Timer disabled on Trigger falling edge. */ +} flexio_timer_disable_condition_t; + +/*! @brief Define type of timer enable condition.*/ +typedef enum _flexio_timer_enable_condition +{ + kFLEXIO_TimerEnabledAlways = 0x0U, /*!< Timer always enabled. */ + kFLEXIO_TimerEnableOnPrevTimerEnable = 0x1U, /*!< Timer enabled on Timer N-1 enable. */ + kFLEXIO_TimerEnableOnTriggerHigh = 0x2U, /*!< Timer enabled on Trigger high. */ + kFLEXIO_TimerEnableOnTriggerHighPinHigh = 0x3U, /*!< Timer enabled on Trigger high and Pin high. */ + kFLEXIO_TimerEnableOnPinRisingEdge = 0x4U, /*!< Timer enabled on Pin rising edge. */ + kFLEXIO_TimerEnableOnPinRisingEdgeTriggerHigh = 0x5U, /*!< Timer enabled on Pin rising edge and Trigger high. */ + kFLEXIO_TimerEnableOnTriggerRisingEdge = 0x6U, /*!< Timer enabled on Trigger rising edge. */ + kFLEXIO_TimerEnableOnTriggerBothEdge = 0x7U, /*!< Timer enabled on Trigger rising or falling edge. */ +} flexio_timer_enable_condition_t; + +/*! @brief Define type of timer stop bit generate condition.*/ +typedef enum _flexio_timer_stop_bit_condition +{ + kFLEXIO_TimerStopBitDisabled = 0x0U, /*!< Stop bit disabled. */ + kFLEXIO_TimerStopBitEnableOnTimerCompare = 0x1U, /*!< Stop bit is enabled on timer compare. */ + kFLEXIO_TimerStopBitEnableOnTimerDisable = 0x2U, /*!< Stop bit is enabled on timer disable. */ + kFLEXIO_TimerStopBitEnableOnTimerCompareDisable = 0x3U, /*!< Stop bit is enabled on timer compare and timer + disable. */ +} flexio_timer_stop_bit_condition_t; + +/*! @brief Define type of timer start bit generate condition.*/ +typedef enum _flexio_timer_start_bit_condition +{ + kFLEXIO_TimerStartBitDisabled = 0x0U, /*!< Start bit disabled. */ + kFLEXIO_TimerStartBitEnabled = 0x1U, /*!< Start bit enabled. */ +} flexio_timer_start_bit_condition_t; + +/*! @brief FlexIO as PWM channel output state */ +typedef enum _flexio_timer_output_state +{ + kFLEXIO_PwmLow = 0, /*!< The output state of PWM channel is low */ + kFLEXIO_PwmHigh, /*!< The output state of PWM channel is high */ +} flexio_timer_output_state_t; + +/*! @brief Define type of timer polarity for shifter control. */ +typedef enum _flexio_shifter_timer_polarity +{ + kFLEXIO_ShifterTimerPolarityOnPositive = 0x0U, /*!< Shift on positive edge of shift clock. */ + kFLEXIO_ShifterTimerPolarityOnNegitive = 0x1U, /*!< Shift on negative edge of shift clock. */ +} flexio_shifter_timer_polarity_t; + +/*! @brief Define type of shifter working mode.*/ +typedef enum _flexio_shifter_mode +{ + kFLEXIO_ShifterDisabled = 0x0U, /*!< Shifter is disabled. */ + kFLEXIO_ShifterModeReceive = 0x1U, /*!< Receive mode. */ + kFLEXIO_ShifterModeTransmit = 0x2U, /*!< Transmit mode. */ + kFLEXIO_ShifterModeMatchStore = 0x4U, /*!< Match store mode. */ + kFLEXIO_ShifterModeMatchContinuous = 0x5U, /*!< Match continuous mode. */ +#if FSL_FEATURE_FLEXIO_HAS_STATE_MODE + kFLEXIO_ShifterModeState = 0x6U, /*!< SHIFTBUF contents are used for storing + programmable state attributes. */ +#endif /* FSL_FEATURE_FLEXIO_HAS_STATE_MODE */ +#if FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE + kFLEXIO_ShifterModeLogic = 0x7U, /*!< SHIFTBUF contents are used for implementing + programmable logic look up table. */ +#endif /* FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE */ +} flexio_shifter_mode_t; + +/*! @brief Define type of shifter input source.*/ +typedef enum _flexio_shifter_input_source +{ + kFLEXIO_ShifterInputFromPin = 0x0U, /*!< Shifter input from pin. */ + kFLEXIO_ShifterInputFromNextShifterOutput = 0x1U, /*!< Shifter input from Shifter N+1. */ +} flexio_shifter_input_source_t; + +/*! @brief Define of STOP bit configuration.*/ +typedef enum _flexio_shifter_stop_bit +{ + kFLEXIO_ShifterStopBitDisable = 0x0U, /*!< Disable shifter stop bit. */ + kFLEXIO_ShifterStopBitLow = 0x2U, /*!< Set shifter stop bit to logic low level. */ + kFLEXIO_ShifterStopBitHigh = 0x3U, /*!< Set shifter stop bit to logic high level. */ +} flexio_shifter_stop_bit_t; + +/*! @brief Define type of START bit configuration.*/ +typedef enum _flexio_shifter_start_bit +{ + kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable = 0x0U, /*!< Disable shifter start bit, transmitter loads + data on enable. */ + kFLEXIO_ShifterStartBitDisabledLoadDataOnShift = 0x1U, /*!< Disable shifter start bit, transmitter loads + data on first shift. */ + kFLEXIO_ShifterStartBitLow = 0x2U, /*!< Set shifter start bit to logic low level. */ + kFLEXIO_ShifterStartBitHigh = 0x3U, /*!< Set shifter start bit to logic high level. */ +} flexio_shifter_start_bit_t; + +/*! @brief Define FlexIO shifter buffer type*/ +typedef enum _flexio_shifter_buffer_type +{ + kFLEXIO_ShifterBuffer = 0x0U, /*!< Shifter Buffer N Register. */ + kFLEXIO_ShifterBufferBitSwapped = 0x1U, /*!< Shifter Buffer N Bit Byte Swapped Register. */ + kFLEXIO_ShifterBufferByteSwapped = 0x2U, /*!< Shifter Buffer N Byte Swapped Register. */ + kFLEXIO_ShifterBufferBitByteSwapped = 0x3U, /*!< Shifter Buffer N Bit Swapped Register. */ +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP + kFLEXIO_ShifterBufferNibbleByteSwapped = 0x4U, /*!< Shifter Buffer N Nibble Byte Swapped Register. */ +#endif /*FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP*/ +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP + kFLEXIO_ShifterBufferHalfWordSwapped = 0x5U, /*!< Shifter Buffer N Half Word Swapped Register. */ +#endif +#if defined(FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP) && FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP + kFLEXIO_ShifterBufferNibbleSwapped = 0x6U, /*!< Shifter Buffer N Nibble Swapped Register. */ +#endif +} flexio_shifter_buffer_type_t; + +/*! @brief Define FlexIO user configuration structure. */ +typedef struct _flexio_config_ +{ + bool enableFlexio; /*!< Enable/disable FlexIO module */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode */ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode */ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, fast access requires + the FlexIO clock to be at least twice the frequency of the bus clock. */ +} flexio_config_t; + +/*! @brief Define FlexIO timer configuration structure. */ +typedef struct _flexio_timer_config +{ + /* Trigger. */ + uint32_t triggerSelect; /*!< The internal trigger selection number using MACROs. */ + flexio_timer_trigger_polarity_t triggerPolarity; /*!< Trigger Polarity. */ + flexio_timer_trigger_source_t triggerSource; /*!< Trigger Source, internal (see 'trgsel') or external. */ + /* Pin. */ + flexio_pin_config_t pinConfig; /*!< Timer Pin Configuration. */ + uint32_t pinSelect; /*!< Timer Pin number Select. */ + flexio_pin_polarity_t pinPolarity; /*!< Timer Pin Polarity. */ + /* Timer. */ + flexio_timer_mode_t timerMode; /*!< Timer work Mode. */ + flexio_timer_output_t timerOutput; /*!< Configures the initial state of the Timer Output and + whether it is affected by the Timer reset. */ + flexio_timer_decrement_source_t timerDecrement; /*!< Configures the source of the Timer decrement and the + source of the Shift clock. */ + flexio_timer_reset_condition_t timerReset; /*!< Configures the condition that causes the timer counter + (and optionally the timer output) to be reset. */ + flexio_timer_disable_condition_t timerDisable; /*!< Configures the condition that causes the Timer to be + disabled and stop decrementing. */ + flexio_timer_enable_condition_t timerEnable; /*!< Configures the condition that causes the Timer to be + enabled and start decrementing. */ + flexio_timer_stop_bit_condition_t timerStop; /*!< Timer STOP Bit generation. */ + flexio_timer_start_bit_condition_t timerStart; /*!< Timer STRAT Bit generation. */ + uint32_t timerCompare; /*!< Value for Timer Compare N Register. */ +} flexio_timer_config_t; + +/*! @brief Define FlexIO shifter configuration structure. */ +typedef struct _flexio_shifter_config +{ + /* Timer. */ + uint32_t timerSelect; /*!< Selects which Timer is used for controlling the + logic/shift register and generating the Shift clock. */ + flexio_shifter_timer_polarity_t timerPolarity; /*!< Timer Polarity. */ + /* Pin. */ + flexio_pin_config_t pinConfig; /*!< Shifter Pin Configuration. */ + uint32_t pinSelect; /*!< Shifter Pin number Select. */ + flexio_pin_polarity_t pinPolarity; /*!< Shifter Pin Polarity. */ + /* Shifter. */ + flexio_shifter_mode_t shifterMode; /*!< Configures the mode of the Shifter. */ +#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH + uint32_t parallelWidth; /*!< Configures the parallel width when using parallel mode.*/ +#endif /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */ + flexio_shifter_input_source_t inputSource; /*!< Selects the input source for the shifter. */ + flexio_shifter_stop_bit_t shifterStop; /*!< Shifter STOP bit. */ + flexio_shifter_start_bit_t shifterStart; /*!< Shifter START bit. */ +} flexio_shifter_config_t; + +#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER) && FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER +/*! @brief FLEXIO gpio direction definition */ +typedef enum _flexio_gpio_direction +{ + kFLEXIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ + kFLEXIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ +} flexio_gpio_direction_t; + +/*! @brief FLEXIO gpio input config */ +typedef enum _flexio_pin_input_config +{ + kFLEXIO_InputInterruptDisabled = 0x0U, /*!< Interrupt request is disabled. */ + kFLEXIO_InputInterruptEnable = 0x1U, /*!< Interrupt request is enable. */ + kFLEXIO_FlagRisingEdgeEnable = 0x2U, /*!< Input pin flag on rising edge. */ + kFLEXIO_FlagFallingEdgeEnable = 0x4U, /*!< Input pin flag on falling edge. */ +} flexio_pin_input_config_t; + +/*! + * @brief The FLEXIO pin configuration structure. + * + * Each pin can only be configured as either an output pin or an input pin at a time. + * If configured as an input pin, use inputConfig param. + * If configured as an output pin, use outputLogic. + */ +typedef struct _flexio_gpio_config +{ + flexio_gpio_direction_t pinDirection; /*!< FLEXIO pin direction, input or output */ + uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ + uint8_t inputConfig; /*!< Set an input config */ +} flexio_gpio_config_t; +#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER*/ + +/*! @brief typedef for FlexIO simulated driver interrupt handler.*/ +typedef void (*flexio_isr_t)(void *base, void *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to flexio bases for each instance. */ +extern FLEXIO_Type *const s_flexioBases[]; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to flexio clocks for each instance. */ +extern const clock_ip_name_t s_flexioClocks[]; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name FlexIO Initialization and De-initialization + * @{ + */ + +/*! + * @brief Gets the default configuration to configure the FlexIO module. The configuration + * can used directly to call the FLEXIO_Configure(). + * + * Example: + @code + flexio_config_t config; + FLEXIO_GetDefaultConfig(&config); + @endcode + * + * @param userConfig pointer to flexio_config_t structure +*/ +void FLEXIO_GetDefaultConfig(flexio_config_t *userConfig); + +/*! + * @brief Configures the FlexIO with a FlexIO configuration. The configuration structure + * can be filled by the user or be set with default values by FLEXIO_GetDefaultConfig(). + * + * Example + @code + flexio_config_t config = { + .enableFlexio = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false + }; + FLEXIO_Configure(base, &config); + @endcode + * + * @param base FlexIO peripheral base address + * @param userConfig pointer to flexio_config_t structure +*/ +void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig); + +/*! + * @brief Gates the FlexIO clock. Call this API to stop the FlexIO clock. + * + * @note After calling this API, call the FLEXO_Init to use the FlexIO module. + * + * @param base FlexIO peripheral base address + */ +void FLEXIO_Deinit(FLEXIO_Type *base); + +/*! + * @brief Get instance number for FLEXIO module. + * + * @param base FLEXIO peripheral base address. + */ +uint32_t FLEXIO_GetInstance(FLEXIO_Type *base); + +/*! @} */ + +/*! + * @name FlexIO Basic Operation + * @{ + */ + +/*! + * @brief Resets the FlexIO module. + * + * @param base FlexIO peripheral base address + */ +void FLEXIO_Reset(FLEXIO_Type *base); + +/*! + * @brief Enables the FlexIO module operation. + * + * @param base FlexIO peripheral base address + * @param enable true to enable, false to disable. + */ +static inline void FLEXIO_Enable(FLEXIO_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } + else + { + base->CTRL &= ~FLEXIO_CTRL_FLEXEN_MASK; + } +} + +#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_STATUS) && FSL_FEATURE_FLEXIO_HAS_PIN_STATUS +/*! + * @brief Reads the input data on each of the FlexIO pins. + * + * @param base FlexIO peripheral base address + * @return FlexIO pin input data + */ +static inline uint32_t FLEXIO_ReadPinInput(FLEXIO_Type *base) +{ + return base->PIN; +} +#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_STATUS*/ + +#if defined(FSL_FEATURE_FLEXIO_HAS_STATE_MODE) && FSL_FEATURE_FLEXIO_HAS_STATE_MODE +/*! + * @brief Gets the current state pointer for state mode use. + * + * @param base FlexIO peripheral base address + * @return current State pointer + */ +static inline uint8_t FLEXIO_GetShifterState(FLEXIO_Type *base) +{ + return ((uint8_t)(base->SHIFTSTATE) & FLEXIO_SHIFTSTATE_STATE_MASK); +} +#endif /*FSL_FEATURE_FLEXIO_HAS_STATE_MODE*/ + +/*! + * @brief Configures the shifter with the shifter configuration. The configuration structure + * covers both the SHIFTCTL and SHIFTCFG registers. To configure the shifter to the proper + * mode, select which timer controls the shifter to shift, whether to generate start bit/stop + * bit, and the polarity of start bit and stop bit. + * + * Example + @code + flexio_shifter_config_t config = { + .timerSelect = 0, + .timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive, + .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, + .pinPolarity = kFLEXIO_PinActiveLow, + .shifterMode = kFLEXIO_ShifterModeTransmit, + .inputSource = kFLEXIO_ShifterInputFromPin, + .shifterStop = kFLEXIO_ShifterStopBitHigh, + .shifterStart = kFLEXIO_ShifterStartBitLow + }; + FLEXIO_SetShifterConfig(base, &config); + @endcode + * + * @param base FlexIO peripheral base address + * @param index Shifter index + * @param shifterConfig Pointer to flexio_shifter_config_t structure +*/ +void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig); +/*! + * @brief Configures the timer with the timer configuration. The configuration structure + * covers both the TIMCTL and TIMCFG registers. To configure the timer to the proper + * mode, select trigger source for timer and the timer pin output and the timing for timer. + * + * Example + @code + flexio_timer_config_t config = { + .triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(0), + .triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow, + .triggerSource = kFLEXIO_TimerTriggerSourceInternal, + .pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection, + .pinSelect = 0, + .pinPolarity = kFLEXIO_PinActiveHigh, + .timerMode = kFLEXIO_TimerModeDual8BitBaudBit, + .timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset, + .timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput, + .timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput, + .timerDisable = kFLEXIO_TimerDisableOnTimerCompare, + .timerEnable = kFLEXIO_TimerEnableOnTriggerHigh, + .timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable, + .timerStart = kFLEXIO_TimerStartBitEnabled + }; + FLEXIO_SetTimerConfig(base, &config); + @endcode + * + * @param base FlexIO peripheral base address + * @param index Timer index + * @param timerConfig Pointer to the flexio_timer_config_t structure +*/ +void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_config_t *timerConfig); + +/*! + * @brief This function set the value of the prescaler on flexio channels + * + * @param base Pointer to the FlexIO simulated peripheral type. + * @param index Timer index + * @param clocksource Set clock value + */ +static inline void FLEXIO_SetClockMode(FLEXIO_Type *base, uint8_t index, flexio_timer_decrement_source_t clocksource) +{ + uint32_t reg = base->TIMCFG[index]; + + reg &= ~FLEXIO_TIMCFG_TIMDEC_MASK; + + reg |= FLEXIO_TIMCFG_TIMDEC(clocksource); + + base->TIMCFG[index] = reg; +} + +/*! @} */ + +/*! + * @name FlexIO Interrupt Operation + * @{ + */ + +/*! + * @brief Enables the shifter status interrupt. The interrupt generates when the corresponding SSF is set. + * + * @param base FlexIO peripheral base address + * @param mask The shifter status mask which can be calculated by (1 << shifter index) + * @note For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + */ +static inline void FLEXIO_EnableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTSIEN |= mask; +} + +/*! + * @brief Disables the shifter status interrupt. The interrupt won't generate when the corresponding SSF is set. + * + * @param base FlexIO peripheral base address + * @param mask The shifter status mask which can be calculated by (1 << shifter index) + * @note For multiple shifter status interrupt enable, for example, two shifter status enable, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + */ +static inline void FLEXIO_DisableShifterStatusInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTSIEN &= ~mask; +} + +/*! + * @brief Enables the shifter error interrupt. The interrupt generates when the corresponding SEF is set. + * + * @param base FlexIO peripheral base address + * @param mask The shifter error mask which can be calculated by (1 << shifter index) + * @note For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + */ +static inline void FLEXIO_EnableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTEIEN |= mask; +} + +/*! + * @brief Disables the shifter error interrupt. The interrupt won't generate when the corresponding SEF is set. + * + * @param base FlexIO peripheral base address + * @param mask The shifter error mask which can be calculated by (1 << shifter index) + * @note For multiple shifter error interrupt enable, for example, two shifter error enable, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + */ +static inline void FLEXIO_DisableShifterErrorInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTEIEN &= ~mask; +} + +/*! + * @brief Enables the timer status interrupt. The interrupt generates when the corresponding SSF is set. + * + * @param base FlexIO peripheral base address + * @param mask The timer status mask which can be calculated by (1 << timer index) + * @note For multiple timer status interrupt enable, for example, two timer status enable, can calculate + * the mask by using ((1 << timer index0) | (1 << timer index1)) + */ +static inline void FLEXIO_EnableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->TIMIEN |= mask; +} + +/*! + * @brief Disables the timer status interrupt. The interrupt won't generate when the corresponding SSF is set. + * + * @param base FlexIO peripheral base address + * @param mask The timer status mask which can be calculated by (1 << timer index) + * @note For multiple timer status interrupt enable, for example, two timer status enable, can calculate + * the mask by using ((1 << timer index0) | (1 << timer index1)) + */ +static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32_t mask) +{ + base->TIMIEN &= ~mask; +} + +/*! @} */ + +/*! + * @name FlexIO Status Operation + * @{ + */ + +/*! + * @brief Gets the shifter status flags. + * + * @param base FlexIO peripheral base address + * @return Shifter status flags + */ +static inline uint32_t FLEXIO_GetShifterStatusFlags(FLEXIO_Type *base) +{ + return ((base->SHIFTSTAT) & FLEXIO_SHIFTSTAT_SSF_MASK); +} + +/*! + * @brief Clears the shifter status flags. + * + * @param base FlexIO peripheral base address + * @param mask The shifter status mask which can be calculated by (1 << shifter index) + * @note For clearing multiple shifter status flags, for example, two shifter status flags, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + */ +static inline void FLEXIO_ClearShifterStatusFlags(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTSTAT = mask; +} + +/*! + * @brief Gets the shifter error flags. + * + * @param base FlexIO peripheral base address + * @return Shifter error flags + */ +static inline uint32_t FLEXIO_GetShifterErrorFlags(FLEXIO_Type *base) +{ + return ((base->SHIFTERR) & FLEXIO_SHIFTERR_SEF_MASK); +} + +/*! + * @brief Clears the shifter error flags. + * + * @param base FlexIO peripheral base address + * @param mask The shifter error mask which can be calculated by (1 << shifter index) + * @note For clearing multiple shifter error flags, for example, two shifter error flags, can calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + */ +static inline void FLEXIO_ClearShifterErrorFlags(FLEXIO_Type *base, uint32_t mask) +{ + base->SHIFTERR = mask; +} + +/*! + * @brief Gets the timer status flags. + * + * @param base FlexIO peripheral base address + * @return Timer status flags + */ +static inline uint32_t FLEXIO_GetTimerStatusFlags(FLEXIO_Type *base) +{ + return ((base->TIMSTAT) & FLEXIO_TIMSTAT_TSF_MASK); +} + +/*! + * @brief Clears the timer status flags. + * + * @param base FlexIO peripheral base address + * @param mask The timer status mask which can be calculated by (1 << timer index) + * @note For clearing multiple timer status flags, for example, two timer status flags, can calculate + * the mask by using ((1 << timer index0) | (1 << timer index1)) + */ +static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask) +{ + base->TIMSTAT = mask; +} + +/*! @} */ + +/*! + * @name FlexIO DMA Operation + * @{ + */ + +/*! + * @brief Enables/disables the shifter status DMA. The DMA request generates when the corresponding SSF is set. + * + * @note For multiple shifter status DMA enables, for example, calculate + * the mask by using ((1 << shifter index0) | (1 << shifter index1)) + * + * @param base FlexIO peripheral base address + * @param mask The shifter status mask which can be calculated by (1 << shifter index) + * @param enable True to enable, false to disable. + */ +static inline void FLEXIO_EnableShifterStatusDMA(FLEXIO_Type *base, uint32_t mask, bool enable) +{ + if (enable) + { + base->SHIFTSDEN |= mask; + } + else + { + base->SHIFTSDEN &= ~mask; + } +} + +/*! + * @brief Gets the shifter buffer address for the DMA transfer usage. + * + * @param base FlexIO peripheral base address + * @param type Shifter type of flexio_shifter_buffer_type_t + * @param index Shifter index + * @return Corresponding shifter buffer index + */ +uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer_type_t type, uint8_t index); + +/*! + * @brief Registers the handle and the interrupt handler for the FlexIO-simulated peripheral. + * + * @param base Pointer to the FlexIO simulated peripheral type. + * @param handle Pointer to the handler for FlexIO simulated peripheral. + * @param isr FlexIO simulated peripheral interrupt handler. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr); + +/*! + * @brief Unregisters the handle and the interrupt handler for the FlexIO-simulated peripheral. + * + * @param base Pointer to the FlexIO simulated peripheral type. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_UnregisterHandleIRQ(void *base); +/*! @} */ + +#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER) && FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER + +/*! + * @brief Configure a FLEXIO pin used by the board. + * + * To Config the FLEXIO PIN, define a pin configuration, as either input or output, in the user file. + * Then, call the FLEXIO_SetPinConfig() function. + * + * This is an example to define an input pin or an output pin configuration. + * @code + * Define a digital input pin configuration, + * flexio_gpio_config_t config = + * { + * kFLEXIO_DigitalInput, + * 0U, + * kFLEXIO_FlagRisingEdgeEnable | kFLEXIO_InputInterruptEnable, + * } + * Define a digital output pin configuration, + * flexio_gpio_config_t config = + * { + * kFLEXIO_DigitalOutput, + * 0U, + * 0U + * } + * @endcode + * @param base FlexIO peripheral base address + * @param pin FLEXIO pin number. + * @param config FLEXIO pin configuration pointer. + */ +void FLEXIO_SetPinConfig(FLEXIO_Type *base, uint32_t pin, flexio_gpio_config_t *config); + +/*! + * @name GPIO Output Operations + * @{ + */ + +/*! + * @brief Sets the output level of the multiple FLEXIO pins to the logic 0. + * + * @param base FlexIO peripheral base address + * @param mask FLEXIO pin number mask + */ +static inline void FLEXIO_ClearPortOutput(FLEXIO_Type *base, uint32_t mask) +{ + base->PINOUTCLR = mask; +} + +/*! + * @brief Sets the output level of the multiple FLEXIO pins to the logic 1. + * + * @param base FlexIO peripheral base address + * @param mask FLEXIO pin number mask + */ +static inline void FLEXIO_SetPortOutput(FLEXIO_Type *base, uint32_t mask) +{ + base->PINOUTSET = mask; +} + +/*! + * @brief Reverses the current output logic of the multiple FLEXIO pins. + * + * @param base FlexIO peripheral base address + * @param mask FLEXIO pin number mask + */ +static inline void FLEXIO_TogglePortOutput(FLEXIO_Type *base, uint32_t mask) +{ + base->PINOUTTOG = mask; +} + +/*! + * @brief Sets the output level of the FLEXIO pins to the logic 1 or 0. + * + * @param base FlexIO peripheral base address + * @param pin FLEXIO pin number. + * @param output FLEXIO pin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void FLEXIO_PinWrite(FLEXIO_Type *base, uint32_t pin, uint8_t output) +{ + if (output == 0U) + { + FLEXIO_ClearPortOutput(base, 1UL << pin); + } + else + { + FLEXIO_SetPortOutput(base, 1UL << pin); + } +} + +/*! + * @brief Enables the FLEXIO output pin function. + * + * @param base FlexIO peripheral base address + * @param pin FLEXIO pin number. + */ +static inline void FLEXIO_EnablePinOutput(FLEXIO_Type *base, uint32_t pin) +{ + base->PINOUTE |= (1UL << pin); +} +/*! @} */ + +/*! + * @name FLEXIO PIN Input Operations + * @{ + */ + +/*! + * @brief Reads the current input value of the FLEXIO pin. + * + * @param base FlexIO peripheral base address + * @param pin FLEXIO pin number. + * @retval FLEXIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t FLEXIO_PinRead(FLEXIO_Type *base, uint32_t pin) +{ + return (((base->PIN) >> pin) & 0x01U); +} + +/*! + * @brief Gets the FLEXIO input pin status. + * + * @param base FlexIO peripheral base address + * @param pin FLEXIO pin number. + * @retval FLEXIO port input status + * - 0: corresponding pin input capture no status. + * - 1: corresponding pin input capture rising or falling edge. + */ +static inline uint32_t FLEXIO_GetPinStatus(FLEXIO_Type *base, uint32_t pin) +{ + return (((base->PINSTAT) >> pin) & 0x01U); +} + +/*! + * @brief Clears the multiple FLEXIO input pins status. + * + * @param base FlexIO peripheral base address + * @param mask FLEXIO pin number mask + */ +static inline void FLEXIO_ClearPortStatus(FLEXIO_Type *base, uint32_t mask) +{ + base->PINSTAT = mask; +} +/*! @} */ + +#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*! @} */ + +#endif /*FSL_FLEXIO_H_*/ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_i2c_master.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_i2c_master.c new file mode 100644 index 00000000000..9239527c6fa --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_i2c_master.c @@ -0,0 +1,1377 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_i2c_master.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_i2c_master" +#endif + +/*! @brief FLEXIO I2C transfer state */ +enum _flexio_i2c_master_transfer_states +{ + kFLEXIO_I2C_Idle = 0x0U, /*!< I2C bus idle */ + kFLEXIO_I2C_Start = 0x1U, /*!< I2C start phase */ + kFLEXIO_I2C_SendCommand = 0x2U, /*!< Send command byte phase */ + kFLEXIO_I2C_SendData = 0x3U, /*!< Send data transfer phase*/ + kFLEXIO_I2C_ReceiveDataBegin = 0x4U, /*!< Receive data begin transfer phase*/ + kFLEXIO_I2C_ReceiveData = 0x5U, /*!< Receive data transfer phase*/ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Set up master transfer, send slave address and decide the initial + * transfer state. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param transfer pointer to flexio_i2c_master_transfer_t structure + */ +static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_t *xfer); + +/*! + * @brief Master run transfer state machine to perform a byte of transfer. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param statusFlags flexio i2c hardware status + * @retval kStatus_Success Successfully run state machine + * @retval kStatus_FLEXIO_I2C_Nak Receive Nak during transfer + */ +static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags); + +/*! + * @brief Complete transfer, disable interrupt and call callback. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param status flexio transfer status + */ +static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + status_t status); + +/*! + * @brief introduce function FLEXIO_I2C_MasterTransferStateMachineStart. + * This function was deal with Initial state, i2c start state. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + */ +static void FLEXIO_I2C_MasterTransferStateMachineStart(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle); + +/*! + * @brief introduce function FLEXIO_I2C_MasterTransferStateMachineSendCommand. + * This function was deal with Check address only needed for transfer with subaddress . + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param statusFlags flexio i2c hardware status + * + * @return default is true when No abnormality. + * @return false when time out. + */ +static bool FLEXIO_I2C_MasterTransferStateMachineSendCommand(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags); + +/*! + * @brief introduce function FLEXIO_I2C_MasterTransferStateMachineSendData. + * This function was deal with Send command byte. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param statusFlags flexio i2c hardware status + * + * @return default is true when No abnormality. + * @return false when time out. + */ +static bool FLEXIO_I2C_MasterTransferStateMachineSendData(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags); + +/*! + * @brief introduce function FLEXIO_I2C_MasterTransferStateMachineReceiveDataBegin. + * This function was deal with Receive Data Begin. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param statusFlags flexio i2c hardware status + * + * @return default is true when No abnormality. + * @return false when time out. + */ +static bool FLEXIO_I2C_MasterTransferStateMachineReceiveDataBegin(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags); + +/*! + * @brief introduce function Case_kFLEXIO_I2C_ReceiveDataBegin. + * This function was deal with Receive Data. + * + * @param base pointer to FLEXIO_I2C_Type structure + * @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param statusFlags flexio i2c hardware status + * + * @return default is kStatus_Success when No abnormality. + * @return kStatus_FLEXIO_I2C_Nak when ReceiveNakFlag is not set. + * @return kStatus_FLEXIO_I2C_Timeout when time out. + */ +static status_t FLEXIO_I2C_MasterTransferStateMachineReceiveData(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags); + +/******************************************************************************* + * Codes + ******************************************************************************/ + +static uint32_t FLEXIO_I2C_GetInstance(FLEXIO_I2C_Type *base) +{ + return FLEXIO_GetInstance(base->flexioBase); +} + +static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_t *xfer) +{ + bool needRestart; + uint32_t byteCount; + + /* Init the handle member. */ + handle->transfer.slaveAddress = xfer->slaveAddress; + handle->transfer.direction = xfer->direction; + handle->transfer.subaddress = xfer->subaddress; + handle->transfer.subaddressSize = xfer->subaddressSize; + handle->transfer.data = xfer->data; + handle->transfer.dataSize = xfer->dataSize; + handle->transfer.flags = xfer->flags; + handle->transferSize = xfer->dataSize; + + /* Initial state, i2c start state. */ + handle->state = (uint8_t)kFLEXIO_I2C_Start; + + /* Clear all status before transfer. */ + FLEXIO_I2C_MasterClearStatusFlags(base, (uint32_t)kFLEXIO_I2C_ReceiveNakFlag); + + /* Calculate whether need to send re-start. */ + needRestart = (handle->transfer.subaddressSize != 0U) && (handle->transfer.direction == kFLEXIO_I2C_Read); + handle->needRestart = needRestart; + + /* Calculate total byte count in a frame. */ + byteCount = 1U; + + if (!needRestart) + { + byteCount += handle->transfer.dataSize; + } + + if (handle->transfer.subaddressSize != 0U) + { + byteCount += handle->transfer.subaddressSize; + } + + /* Configure data count. */ + if (FLEXIO_I2C_MasterSetTransferCount(base, (uint16_t)byteCount) != kStatus_Success) + { + return kStatus_InvalidArgument; + } + + /* Configure timer1 disable condition. */ + uint32_t tmpConfig = base->flexioBase->TIMCFG[base->timerIndex[1]]; + tmpConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK; + tmpConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnPreTimerDisable); + base->flexioBase->TIMCFG[base->timerIndex[1]] = tmpConfig; + +#if I2C_RETRY_TIMES + uint32_t waitTimes = I2C_RETRY_TIMES; + while ((0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) && + (0U != --waitTimes)) + { + } + if (0U == waitTimes) + { + return kStatus_FLEXIO_I2C_Timeout; + } +#else + while (0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) + { + } +#endif + + return kStatus_Success; +} + +static void FLEXIO_I2C_MasterTransferStateMachineStart(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle) +{ + if (handle->needRestart) + { + FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, kFLEXIO_I2C_Write); + } + else + { + FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, handle->transfer.direction); + } + if (handle->transfer.subaddressSize == 0U) + { + if (handle->transfer.direction == kFLEXIO_I2C_Write) + { + /* Next state, send data. */ + handle->state = (uint8_t)kFLEXIO_I2C_SendData; + } + else + { + /* Next state, receive data begin. */ + handle->state = (uint8_t)kFLEXIO_I2C_ReceiveDataBegin; + } + } + else + { + /* Next state, send command byte. */ + handle->state = (uint8_t)kFLEXIO_I2C_SendCommand; + } +} + +static bool FLEXIO_I2C_MasterTransferStateMachineSendCommand(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags) +{ + if ((statusFlags & (uint32_t)kFLEXIO_I2C_TxEmptyFlag) != 0U) + { + if (handle->transfer.subaddressSize > 0U) + { + handle->transfer.subaddressSize--; + FLEXIO_I2C_MasterWriteByte(base, ((handle->transfer.subaddress) >> (8U * handle->transfer.subaddressSize))); + + if (handle->transfer.subaddressSize == 0U) + { + /* Load re-start in advance. */ + if (handle->transfer.direction == kFLEXIO_I2C_Read) + { +#if I2C_RETRY_TIMES + while ((0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) && + (0U != --waitTimes)) + { + } + if (0U == waitTimes) + { + return false; + } +#else + while (0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) + { + } +#endif + FLEXIO_I2C_MasterRepeatedStart(base); + } + } + } + else + { + if (handle->transfer.direction == kFLEXIO_I2C_Write) + { + /* Send first byte of data. */ + if (handle->transfer.dataSize > 0U) + { + /* Next state, send data. */ + handle->state = (uint8_t)kFLEXIO_I2C_SendData; + + FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data); + handle->transfer.data++; + handle->transfer.dataSize--; + } + else + { + FLEXIO_I2C_MasterStop(base); + +#if I2C_RETRY_TIMES + while ((0U == (FLEXIO_I2C_MasterGetStatusFlags(base) & (uint32_t)kFLEXIO_I2C_RxFullFlag)) && + (0U != --waitTimes)) + { + } + if (0U == waitTimes) + { + return false; + } +#else + while (0U == (FLEXIO_I2C_MasterGetStatusFlags(base) & (uint32_t)kFLEXIO_I2C_RxFullFlag)) + { + } +#endif + (void)FLEXIO_I2C_MasterReadByte(base); + + handle->state = (uint8_t)kFLEXIO_I2C_Idle; + } + } + else + { + (void)FLEXIO_I2C_MasterSetTransferCount(base, (uint16_t)(handle->transfer.dataSize + 1U)); + /* Delay at least one clock cycle so that the restart setup time is up to spec standard. */ + SDK_DelayAtLeastUs(1000000UL / base->baudrate, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, kFLEXIO_I2C_Read); + + /* Next state, receive data begin. */ + handle->state = (uint8_t)kFLEXIO_I2C_ReceiveDataBegin; + } + } + } + return true; +} + +static bool FLEXIO_I2C_MasterTransferStateMachineSendData(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags) +{ + if ((statusFlags & (uint32_t)kFLEXIO_I2C_TxEmptyFlag) != 0U) + { + /* Send one byte of data. */ + if (handle->transfer.dataSize > 0U) + { + FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data); + + handle->transfer.data++; + handle->transfer.dataSize--; + } + else + { + FLEXIO_I2C_MasterStop(base); + +#if I2C_RETRY_TIMES + while ((0U == (FLEXIO_I2C_MasterGetStatusFlags(base) & (uint32_t)kFLEXIO_I2C_RxFullFlag)) && + (0U != --waitTimes)) + { + } + if (0U == waitTimes) + { + return false; + } +#else + while (0U == (FLEXIO_I2C_MasterGetStatusFlags(base) & (uint32_t)kFLEXIO_I2C_RxFullFlag)) + { + } +#endif + (void)FLEXIO_I2C_MasterReadByte(base); + + handle->state = (uint8_t)kFLEXIO_I2C_Idle; + } + } + return true; +} + +static bool FLEXIO_I2C_MasterTransferStateMachineReceiveDataBegin(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags) +{ + if ((statusFlags & (uint32_t)kFLEXIO_I2C_RxFullFlag) != 0U) + { + handle->state = (uint8_t)kFLEXIO_I2C_ReceiveData; + /* Send nak at the last receive byte. */ + if (handle->transfer.dataSize == 1U) + { + FLEXIO_I2C_MasterEnableAck(base, false); +#if I2C_RETRY_TIMES + while ((0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) && + (0U != --waitTimes)) + { + } + if (0U == waitTimes) + { + return false; + } +#else + while (0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) + { + } +#endif + FLEXIO_I2C_MasterStop(base); + } + else + { + FLEXIO_I2C_MasterEnableAck(base, true); + } + } + else if ((statusFlags & (uint32_t)kFLEXIO_I2C_TxEmptyFlag) != 0U) + { + /* Read one byte of data. */ + FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU); + } + else + { + ; /* Avoid MISRA 2012 rule 15.7 */ + } + return true; +} + +static status_t FLEXIO_I2C_MasterTransferStateMachineReceiveData(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags) +{ + if ((statusFlags & (uint32_t)kFLEXIO_I2C_RxFullFlag) != 0U) + { + *handle->transfer.data = FLEXIO_I2C_MasterReadByte(base); + handle->transfer.data++; + if (0U != handle->transfer.dataSize--) + { + if (handle->transfer.dataSize == 0U) + { + FLEXIO_I2C_MasterDisableInterrupts(base, (uint32_t)kFLEXIO_I2C_RxFullInterruptEnable); + handle->state = (uint8_t)kFLEXIO_I2C_Idle; + /* Return nak if ReceiveNakFlag is not set */ + if ((statusFlags & (uint32_t)kFLEXIO_I2C_ReceiveNakFlag) == 0U) + { + return kStatus_FLEXIO_I2C_Nak; + } + } + + /* Send nak at the last receive byte. */ + if (handle->transfer.dataSize == 1U) + { + FLEXIO_I2C_MasterEnableAck(base, false); +#if I2C_RETRY_TIMES + while ((0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) && + (0U != --waitTimes)) + { + } + if (0U == waitTimes) + { + return kStatus_FLEXIO_I2C_Timeout; + } +#else + while (0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) + { + } +#endif + FLEXIO_I2C_MasterStop(base); + } + } + } + else if ((statusFlags & (uint32_t)kFLEXIO_I2C_TxEmptyFlag) != 0U) + { + if (handle->transfer.dataSize > 1U) + { + FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU); + } + } + else + { + ; /* Avoid MISRA 2012 rule 15.7 */ + } + return kStatus_Success; +} + +static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + uint32_t statusFlags) +{ + status_t status; +#if I2C_RETRY_TIMES + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + + if ((statusFlags & (uint32_t)kFLEXIO_I2C_ReceiveNakFlag) != 0U) + { + /* Clear receive nak flag. */ + FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1UL << base->shifterIndex[1]); + + if ((!((handle->state == (uint8_t)kFLEXIO_I2C_SendData) && (handle->transfer.dataSize == 0U))) && + (!(((handle->state == (uint8_t)kFLEXIO_I2C_ReceiveData) || + (handle->state == (uint8_t)kFLEXIO_I2C_ReceiveDataBegin)) && + (handle->transfer.dataSize == 1U)))) + { + (void)FLEXIO_I2C_MasterReadByte(base); + + FLEXIO_I2C_MasterAbortStop(base); + + /* Delay one clk cycle to ensure the bus is idle. */ + SDK_DelayAtLeastUs(1000000UL / base->baudrate, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + handle->state = (uint8_t)kFLEXIO_I2C_Idle; + + return kStatus_FLEXIO_I2C_Nak; + } + } + + if (((statusFlags & (uint8_t)kFLEXIO_I2C_RxFullFlag) != 0U) && (handle->state != (uint8_t)kFLEXIO_I2C_ReceiveData)) + { + (void)FLEXIO_I2C_MasterReadByte(base); + } + + switch (handle->state) + { + /* Initial state, i2c start state. */ + case (uint8_t)kFLEXIO_I2C_Start: + /* Send address byte first. */ + FLEXIO_I2C_MasterTransferStateMachineStart(base, handle); + break; + + /* Check address only needed for transfer with subaddress */ + case (uint8_t)kFLEXIO_I2C_SendCommand: + if (false == FLEXIO_I2C_MasterTransferStateMachineSendCommand(base, handle, statusFlags)) + { + return kStatus_FLEXIO_I2C_Timeout; + } + break; + + /* Send command byte. */ + case (uint8_t)kFLEXIO_I2C_SendData: + if (false == FLEXIO_I2C_MasterTransferStateMachineSendData(base, handle, statusFlags)) + { + return kStatus_FLEXIO_I2C_Timeout; + } + break; + + case (uint8_t)kFLEXIO_I2C_ReceiveDataBegin: + if (false == FLEXIO_I2C_MasterTransferStateMachineReceiveDataBegin(base, handle, statusFlags)) + { + return kStatus_FLEXIO_I2C_Timeout; + } + break; + + case (uint8_t)kFLEXIO_I2C_ReceiveData: + status = FLEXIO_I2C_MasterTransferStateMachineReceiveData(base, handle, statusFlags); + if (kStatus_Success != status) + { + return status; + } + break; + + default: + /* Add comment to avoid MISRA violation */ + break; + } + + return kStatus_Success; +} + +static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + status_t status) +{ + FLEXIO_I2C_MasterDisableInterrupts( + base, (uint32_t)kFLEXIO_I2C_TxEmptyInterruptEnable | (uint32_t)kFLEXIO_I2C_RxFullInterruptEnable); + + if (handle->completionCallback != NULL) + { + handle->completionCallback(base, handle, status, handle->userData); + } +} + +#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_STATUS) && FSL_FEATURE_FLEXIO_HAS_PIN_STATUS +/*! + * brief Make sure the bus isn't already pulled down. + * + * Check the FLEXIO pin status to see whether either of SDA and SCL pin is pulled down. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * retval kStatus_Success + * retval kStatus_FLEXIO_I2C_Busy + */ +status_t FLEXIO_I2C_CheckForBusyBus(FLEXIO_I2C_Type *base) +{ + uint32_t mask; + /* If in certain loops the SDA/SCL is continuously pulled down, then return bus busy status. */ + /* The loop count is determined by maximum CPU clock frequency */ + for (uint32_t i = 0U; i < SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY / 600000U; ++i) + { + mask = 1UL << base->SDAPinIndex | 1UL << base->SCLPinIndex; + if ((FLEXIO_ReadPinInput(base->flexioBase) & mask) == mask) + { + return kStatus_Success; + } + } + return kStatus_FLEXIO_I2C_Busy; +} +#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_STATUS*/ + +/*! + * brief Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO I2C + * hardware configuration. + * + * Example + code + FLEXIO_I2C_Type base = { + .flexioBase = FLEXIO, + .SDAPinIndex = 0, + .SCLPinIndex = 1, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_i2c_master_config_t config = { + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 100000 + }; + FLEXIO_I2C_MasterInit(base, &config, srcClock_Hz); + endcode + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param masterConfig Pointer to flexio_i2c_master_config_t structure. + * param srcClock_Hz FlexIO source clock in Hz. + * retval kStatus_Success Initialization successful + * retval kStatus_InvalidArgument The source clock exceed upper range limitation +*/ +status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + assert((base != NULL) && (masterConfig != NULL)); + + flexio_shifter_config_t shifterConfig; + flexio_timer_config_t timerConfig; + uint32_t controlVal = 0; + uint16_t timerDiv = 0; + status_t result = kStatus_Success; + + (void)memset(&shifterConfig, 0, sizeof(shifterConfig)); + (void)memset(&timerConfig, 0, sizeof(timerConfig)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate flexio clock. */ + CLOCK_EnableClock(s_flexioClocks[FLEXIO_I2C_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Do hardware configuration. */ + /* 1. Configure the shifter 0 for tx. */ + shifterConfig.timerSelect = base->timerIndex[2]; + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + shifterConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection; + shifterConfig.pinSelect = base->SDAPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveLow; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); + + /* 2. Configure the shifter 1 for rx. */ + shifterConfig.timerSelect = base->timerIndex[2]; + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->SDAPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); + + /*3. Configure the timer 0 and timer 1 for generating bit clock. */ + /* timer 1 is used to config baudrate */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection; + timerConfig.pinSelect = base->SCLPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + + /* Set TIMCMP = (baud rate divider / 2) - 1. */ + timerDiv = (uint16_t)(srcClock_Hz / masterConfig->baudRate_Bps) / 2U - 1U; + /* Calculate and assign the actual baudrate. */ + base->baudrate = srcClock_Hz / (2U * ((uint32_t)timerDiv + 1U)); + + timerConfig.timerCompare = timerDiv; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); + + /* timer 0 is used to config total shift clock edges */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->SCLPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + + /* Set TIMCMP when confinguring transfer bytes. */ + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); + + /* 4. Configure the timer 2 for controlling shifters. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->SCLPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveLow; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerCompare; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + + /* Set TIMCMP[15:0] = (number of bits x 2) - 1. */ + timerConfig.timerCompare = 8U * 2U - 1U; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[2], &timerConfig); + + /* Configure FLEXIO I2C Master. */ + controlVal = base->flexioBase->CTRL; + controlVal &= + ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + controlVal |= (FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) | + FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster)); + if (!masterConfig->enableInDoze) + { + controlVal |= FLEXIO_CTRL_DOZEN_MASK; + } + + base->flexioBase->CTRL = controlVal; + /* Disable internal IRQs. */ + FLEXIO_I2C_MasterDisableInterrupts( + base, (uint32_t)kFLEXIO_I2C_TxEmptyInterruptEnable | (uint32_t)kFLEXIO_I2C_RxFullInterruptEnable); + return result; +} + +/*! + * brief De-initializes the FlexIO I2C master peripheral. Calling this API Resets the FlexIO I2C master + * shifer and timer config, module can't work unless the FLEXIO_I2C_MasterInit is called. + * + * param base pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base) +{ + base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0; + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0; + base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0; + base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[0]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[0]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[0]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[1]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[1]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[1]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[2]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[2]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[2]] = 0; + /* Clear the shifter flag. */ + base->flexioBase->SHIFTSTAT = (1UL << base->shifterIndex[0]); + base->flexioBase->SHIFTSTAT = (1UL << base->shifterIndex[1]); + /* Clear the timer flag. */ + base->flexioBase->TIMSTAT = (1UL << base->timerIndex[0]); + base->flexioBase->TIMSTAT = (1UL << base->timerIndex[1]); + base->flexioBase->TIMSTAT = (1UL << base->timerIndex[2]); +} + +/*! + * brief Gets the default configuration to configure the FlexIO module. The configuration + * can be used directly for calling the FLEXIO_I2C_MasterInit(). + * + * Example: + code + flexio_i2c_master_config_t config; + FLEXIO_I2C_MasterGetDefaultConfig(&config); + endcode + * param masterConfig Pointer to flexio_i2c_master_config_t structure. +*/ +void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig) +{ + assert(masterConfig != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(masterConfig, 0, sizeof(*masterConfig)); + + masterConfig->enableMaster = true; + masterConfig->enableInDoze = false; + masterConfig->enableInDebug = true; + masterConfig->enableFastAccess = false; + + /* Default baud rate at 100kbps. */ + masterConfig->baudRate_Bps = 100000U; +} + +/*! + * brief Gets the FlexIO I2C master status flags. + * + * param base Pointer to FLEXIO_I2C_Type structure + * return Status flag, use status flag to AND #_flexio_i2c_master_status_flags can get the related status. + */ + +uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base) +{ + uint32_t status = 0; + + status = + ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0])) >> base->shifterIndex[0]); + status |= + (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[1])) >> (base->shifterIndex[1])) + << 1U); + status |= + (((FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1UL << base->shifterIndex[1])) >> (base->shifterIndex[1])) + << 2U); + + return status; +} + +/*! + * brief Clears the FlexIO I2C master status flags. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param mask Status flag. + * The parameter can be any combination of the following values: + * arg kFLEXIO_I2C_RxFullFlag + * arg kFLEXIO_I2C_ReceiveNakFlag + */ + +void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask) +{ + if ((mask & (uint32_t)kFLEXIO_I2C_TxEmptyFlag) != 0U) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1UL << base->shifterIndex[0]); + } + + if ((mask & (uint32_t)kFLEXIO_I2C_RxFullFlag) != 0U) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1UL << base->shifterIndex[1]); + } + + if ((mask & (uint32_t)kFLEXIO_I2C_ReceiveNakFlag) != 0U) + { + FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1UL << base->shifterIndex[1]); + } +} + +/*! + * brief Enables the FlexIO i2c master interrupt requests. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param mask Interrupt source. + * Currently only one interrupt request source: + * arg kFLEXIO_I2C_TransferCompleteInterruptEnable + */ +void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask) +{ + if ((mask & (uint32_t)kFLEXIO_I2C_TxEmptyInterruptEnable) != 0U) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[0]); + } + if ((mask & (uint32_t)kFLEXIO_I2C_RxFullInterruptEnable) != 0U) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[1]); + } +} + +/*! + * brief Disables the FlexIO I2C master interrupt requests. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param mask Interrupt source. + */ +void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask) +{ + if ((mask & (uint32_t)kFLEXIO_I2C_TxEmptyInterruptEnable) != 0U) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[0]); + } + if ((mask & (uint32_t)kFLEXIO_I2C_RxFullInterruptEnable) != 0U) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[1]); + } +} + +/*! + * brief Sets the FlexIO I2C master transfer baudrate. + * + * param base Pointer to FLEXIO_I2C_Type structure + * param baudRate_Bps the baud rate value in HZ + * param srcClock_Hz source clock in HZ + */ +void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint16_t timerDiv = 0; + FLEXIO_Type *flexioBase = base->flexioBase; + + /* Set TIMCMP = (baud rate divider / 2) - 1.*/ + timerDiv = (uint16_t)((srcClock_Hz / baudRate_Bps) / 2U - 1U); + + flexioBase->TIMCMP[base->timerIndex[1]] = timerDiv; + + /* Calculate and assign the actual baudrate. */ + base->baudrate = srcClock_Hz / (2U * ((uint32_t)timerDiv + 1U)); +} + +/*! + * brief Sets the number of bytes to be transferred from a start signal to a stop signal. + * + * note Call this API before a transfer begins because the timer generates a number of clocks according + * to the number of bytes that need to be transferred. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param count Number of bytes need to be transferred from a start signal to a re-start/stop signal + * retval kStatus_Success Successfully configured the count. + * retval kStatus_InvalidArgument Input argument is invalid. + */ +status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint16_t count) +{ + /* Calculate whether the transfer count is larger than the max value compare register can achieve */ + if (count > ((0xFFFFUL - 1UL) / (16UL + 1UL + 1UL))) + { + return kStatus_InvalidArgument; + } + + uint32_t timerConfig = 0U; + FLEXIO_Type *flexioBase = base->flexioBase; + + flexioBase->TIMCMP[base->timerIndex[0]] = (uint32_t)count * 18U + 1U; + timerConfig = flexioBase->TIMCFG[base->timerIndex[0]]; + timerConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK; + timerConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare); + flexioBase->TIMCFG[base->timerIndex[0]] = timerConfig; + + return kStatus_Success; +} + +/*! + * brief Sends START + 7-bit address to the bus. + * + * note This API should be called when the transfer configuration is ready to send a START signal + * and 7-bit address to the bus. This is a non-blocking API, which returns directly after the address + * is put into the data register but the address transfer is not finished on the bus. Ensure that + * the kFLEXIO_I2C_RxFullFlag status is asserted before calling this API. + * param base Pointer to FLEXIO_I2C_Type structure. + * param address 7-bit address. + * param direction transfer direction. + * This parameter is one of the values in flexio_i2c_direction_t: + * arg kFLEXIO_I2C_Write: Transmit + * arg kFLEXIO_I2C_Read: Receive + */ + +void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction) +{ + uint32_t data; + + data = ((uint32_t)address) << 1U | ((direction == kFLEXIO_I2C_Read) ? 1U : 0U); + + FLEXIO_I2C_MasterWriteByte(base, data); +} + +/*! + * brief Sends the repeated start signal on the bus. + * + * param base Pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base) +{ + /* Prepare for RESTART condition, no stop.*/ + FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU); +} + +/*! + * brief Sends the stop signal on the bus. + * + * param base Pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base) +{ + /* Prepare normal stop. */ + (void)FLEXIO_I2C_MasterSetTransferCount(base, 0x0U); + FLEXIO_I2C_MasterWriteByte(base, 0x0U); +} + +/*! + * brief Sends the stop signal when transfer is still on-going. + * + * param base Pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base) +{ + uint32_t tmpConfig; + + /* Prepare abort stop. */ + /* Disable timer 0. */ + tmpConfig = base->flexioBase->TIMCFG[base->timerIndex[0]]; + tmpConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK; + tmpConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnPinBothEdge); + base->flexioBase->TIMCFG[base->timerIndex[0]] = tmpConfig; + + /* Disable timer 1. */ + tmpConfig = base->flexioBase->TIMCFG[base->timerIndex[1]]; + tmpConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK; + tmpConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnPinBothEdge); + base->flexioBase->TIMCFG[base->timerIndex[1]] = tmpConfig; +} + +/*! + * brief Configures the sent ACK/NAK for the following byte. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param enable True to configure send ACK, false configure to send NAK. + */ +void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable) +{ + uint32_t tmpConfig = 0; + + tmpConfig = base->flexioBase->SHIFTCFG[base->shifterIndex[0]]; + tmpConfig &= ~FLEXIO_SHIFTCFG_SSTOP_MASK; + if (enable) + { + tmpConfig |= FLEXIO_SHIFTCFG_SSTOP(kFLEXIO_ShifterStopBitLow); + } + else + { + tmpConfig |= FLEXIO_SHIFTCFG_SSTOP(kFLEXIO_ShifterStopBitHigh); + } + base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = tmpConfig; +} + +/*! + * brief Sends a buffer of data in bytes. + * + * note This function blocks via polling until all bytes have been sent. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param txBuff The data bytes to send. + * param txSize The number of data bytes to send. + * retval kStatus_Success Successfully write data. + * retval kStatus_FLEXIO_I2C_Nak Receive NAK during writing data. + * retval kStatus_FLEXIO_I2C_Timeout Timeout polling status flags. + */ +status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize) +{ + assert(txBuff != NULL); + assert(txSize != 0U); + + uint32_t status; +#if I2C_RETRY_TIMES + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + + while (0U != txSize--) + { + FLEXIO_I2C_MasterWriteByte(base, *txBuff++); + + /* Wait until data transfer complete. */ +#if I2C_RETRY_TIMES + waitTimes = I2C_RETRY_TIMES; + while ((0U == ((status = FLEXIO_I2C_MasterGetStatusFlags(base)) & (uint32_t)kFLEXIO_I2C_RxFullFlag)) && + (0U != --waitTimes)) + { + } + if (0U == waitTimes) + { + return kStatus_FLEXIO_I2C_Timeout; + } +#else + while (0U == ((status = FLEXIO_I2C_MasterGetStatusFlags(base)) & (uint32_t)kFLEXIO_I2C_RxFullFlag)) + { + } +#endif + + if ((status & (uint32_t)kFLEXIO_I2C_ReceiveNakFlag) != 0U) + { + FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1UL << base->shifterIndex[1]); + return kStatus_FLEXIO_I2C_Nak; + } + } + return kStatus_Success; +} + +/*! + * brief Receives a buffer of bytes. + * + * note This function blocks via polling until all bytes have been received. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param rxBuff The buffer to store the received bytes. + * param rxSize The number of data bytes to be received. + * retval kStatus_Success Successfully read data. + * retval kStatus_FLEXIO_I2C_Timeout Timeout polling status flags. + */ +status_t FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize) +{ + assert(rxBuff != NULL); + assert(rxSize != 0U); + +#if I2C_RETRY_TIMES + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + + while (0U != rxSize--) + { + /* Wait until data transfer complete. */ +#if I2C_RETRY_TIMES + waitTimes = I2C_RETRY_TIMES; + while ((0U == (FLEXIO_I2C_MasterGetStatusFlags(base) & (uint32_t)kFLEXIO_I2C_RxFullFlag)) && + (0U != --waitTimes)) + { + } + if (0U == waitTimes) + { + return kStatus_FLEXIO_I2C_Timeout; + } +#else + while (0U == (FLEXIO_I2C_MasterGetStatusFlags(base) & (uint32_t)kFLEXIO_I2C_RxFullFlag)) + { + } +#endif + *rxBuff++ = FLEXIO_I2C_MasterReadByte(base); + } + return kStatus_Success; +} + +/*! + * brief Performs a master polling transfer on the I2C bus. + * + * note The API does not return until the transfer succeeds or fails due + * to receiving NAK. + * + * param base pointer to FLEXIO_I2C_Type structure. + * param xfer pointer to flexio_i2c_master_transfer_t structure. + * return status of status_t. + */ +status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer) +{ + assert(xfer != NULL); + +#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_STATUS) && FSL_FEATURE_FLEXIO_HAS_PIN_STATUS + /* Return an error if the bus is already in use not by us.*/ + status_t status = FLEXIO_I2C_CheckForBusyBus(base); + if (status != kStatus_Success) + { + return status; + } +#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_STATUS*/ + + flexio_i2c_master_handle_t tmpHandle; + uint32_t statusFlags; + status_t result = kStatus_Success; +#if I2C_RETRY_TIMES + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + + /* Zero the handle. */ + (void)memset(&tmpHandle, 0, sizeof(tmpHandle)); + + /* Set up transfer machine. */ + result = FLEXIO_I2C_MasterTransferInitStateMachine(base, &tmpHandle, xfer); + if (result != kStatus_Success) + { + return result; + } + + do + { + /* Wait either tx empty or rx full flag is asserted. */ +#if I2C_RETRY_TIMES + waitTimes = I2C_RETRY_TIMES; + while ((0U == ((statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base)) & + ((uint32_t)kFLEXIO_I2C_TxEmptyFlag | (uint32_t)kFLEXIO_I2C_RxFullFlag))) && + (0U != --waitTimes)) + { + } + if (0U == waitTimes) + { + return kStatus_FLEXIO_I2C_Timeout; + } +#else + while (0U == ((statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base)) & + ((uint32_t)kFLEXIO_I2C_TxEmptyFlag | (uint32_t)kFLEXIO_I2C_RxFullFlag))) + { + } +#endif + FLEXIO_ClearTimerStatusFlags(base->flexioBase, ((1UL << base->timerIndex[0]) | (1UL << base->timerIndex[1]))); + result = FLEXIO_I2C_MasterTransferRunStateMachine(base, &tmpHandle, statusFlags); + + } while ((tmpHandle.state != (uint8_t)kFLEXIO_I2C_Idle) && (result == kStatus_Success)); + + /* Timer disable on timer compare, wait until bit clock TSF set, which means timer disable and stop has been sent. + */ + while (0U == (FLEXIO_GetTimerStatusFlags(base->flexioBase) & (1UL << base->timerIndex[1]))) + { + } + + return result; +} + +/*! + * brief Initializes the I2C handle which is used in transactional functions. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param handle Pointer to flexio_i2c_master_handle_t structure to store the transfer state. + * param callback Pointer to user callback function. + * param userData User param passed to the callback function. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/isr table out of range. + */ +status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Register callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Clear pending NVIC IRQ before enable NVIC IRQ. */ + NVIC_ClearPendingIRQ(flexio_irqs[FLEXIO_I2C_GetInstance(base)]); + (void)EnableIRQ(flexio_irqs[FLEXIO_I2C_GetInstance(base)]); + + /* Save the context in global variables to support the double weak mechanism. */ + return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2C_MasterTransferHandleIRQ); +} + +/*! + * brief Performs a master interrupt non-blocking transfer on the I2C bus. + * + * note The API returns immediately after the transfer initiates. + * Call FLEXIO_I2C_MasterTransferGetCount to poll the transfer status to check whether + * the transfer is finished. If the return status is not kStatus_FLEXIO_I2C_Busy, the transfer + * is finished. + * + * param base Pointer to FLEXIO_I2C_Type structure + * param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * param xfer pointer to flexio_i2c_master_transfer_t structure + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_FLEXIO_I2C_Busy FlexIO I2C is not idle, is running another transfer. + */ +status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_t *xfer) +{ + assert(handle != NULL); + assert(xfer != NULL); + + status_t result = kStatus_Success; + +#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_STATUS) && FSL_FEATURE_FLEXIO_HAS_PIN_STATUS + /* Return an error if the bus is already in use not by us.*/ + result = FLEXIO_I2C_CheckForBusyBus(base); + if (result != kStatus_Success) + { + return result; + } +#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_STATUS*/ + + if (handle->state != (uint8_t)kFLEXIO_I2C_Idle) + { + return kStatus_FLEXIO_I2C_Busy; + } + else + { + /* Set up transfer machine. */ + result = FLEXIO_I2C_MasterTransferInitStateMachine(base, handle, xfer); + if (result != kStatus_Success) + { + return result; + } + + /* Enable both tx empty and rxfull interrupt. */ + FLEXIO_I2C_MasterEnableInterrupts( + base, (uint32_t)kFLEXIO_I2C_TxEmptyInterruptEnable | (uint32_t)kFLEXIO_I2C_RxFullInterruptEnable); + + return kStatus_Success; + } +} + +/*! + * brief Aborts an interrupt non-blocking transfer early. + * + * note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * param base Pointer to FLEXIO_I2C_Type structure + * param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state + */ +void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle) +{ + assert(handle != NULL); + + /* Disable interrupts. */ + FLEXIO_I2C_MasterDisableInterrupts( + base, (uint32_t)kFLEXIO_I2C_TxEmptyInterruptEnable | (uint32_t)kFLEXIO_I2C_RxFullInterruptEnable); + + /* Reset to idle state. */ + handle->state = (uint8_t)kFLEXIO_I2C_Idle; +} + +/*! + * brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * param base Pointer to FLEXIO_I2C_Type structure. + * param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + * retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count) +{ + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state == (uint8_t)kFLEXIO_I2C_Idle) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + *count = handle->transferSize - handle->transfer.dataSize; + + return kStatus_Success; +} + +/*! + * brief Master interrupt handler. + * + * param i2cType Pointer to FLEXIO_I2C_Type structure + * param i2cHandle Pointer to flexio_i2c_master_transfer_t structure + */ +void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle) +{ + FLEXIO_I2C_Type *base = (FLEXIO_I2C_Type *)i2cType; + flexio_i2c_master_handle_t *handle = (flexio_i2c_master_handle_t *)i2cHandle; + uint32_t statusFlags; + status_t result; + + statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base); + + result = FLEXIO_I2C_MasterTransferRunStateMachine(base, handle, statusFlags); + + if (handle->state == (uint8_t)kFLEXIO_I2C_Idle) + { + FLEXIO_I2C_MasterTransferComplete(base, handle, result); + } +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_i2c_master.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_i2c_master.h new file mode 100644 index 00000000000..6b33abe22ca --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_i2c_master.h @@ -0,0 +1,485 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_FLEXIO_I2C_MASTER_H_ +#define FSL_FLEXIO_I2C_MASTER_H_ + +#include "fsl_common.h" +#include "fsl_flexio.h" + +/*! + * @addtogroup flexio_i2c_master + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 5, 0)) +/*! @} */ + +/*! @brief Retry times for waiting flag. */ +#ifndef I2C_RETRY_TIMES +#define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +/*! @brief FlexIO I2C transfer status*/ +enum +{ + kStatus_FLEXIO_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 0), /*!< I2C is busy doing transfer. */ + kStatus_FLEXIO_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 1), /*!< I2C is busy doing transfer. */ + kStatus_FLEXIO_I2C_Nak = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 2), /*!< NAK received during transfer. */ + kStatus_FLEXIO_I2C_Timeout = MAKE_STATUS(kStatusGroup_FLEXIO_I2C, 3), /*!< Timeout polling status flags. */ +}; + +/*! @brief Define FlexIO I2C master interrupt mask. */ +enum _flexio_i2c_master_interrupt +{ + kFLEXIO_I2C_TxEmptyInterruptEnable = 0x1U, /*!< Tx buffer empty interrupt enable. */ + kFLEXIO_I2C_RxFullInterruptEnable = 0x2U, /*!< Rx buffer full interrupt enable. */ +}; + +/*! @brief Define FlexIO I2C master status mask. */ +enum _flexio_i2c_master_status_flags +{ + kFLEXIO_I2C_TxEmptyFlag = 0x1U, /*!< Tx shifter empty flag. */ + kFLEXIO_I2C_RxFullFlag = 0x2U, /*!< Rx shifter full/Transfer complete flag. */ + kFLEXIO_I2C_ReceiveNakFlag = 0x4U, /*!< Receive NAK flag. */ +}; + +/*! @brief Direction of master transfer.*/ +typedef enum _flexio_i2c_direction +{ + kFLEXIO_I2C_Write = 0x0U, /*!< Master send to slave. */ + kFLEXIO_I2C_Read = 0x1U, /*!< Master receive from slave. */ +} flexio_i2c_direction_t; + +/*! @brief Define FlexIO I2C master access structure typedef. */ +typedef struct _flexio_i2c_type +{ + FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ + uint8_t SDAPinIndex; /*!< Pin select for I2C SDA. */ + uint8_t SCLPinIndex; /*!< Pin select for I2C SCL. */ + uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO I2C. */ + uint8_t timerIndex[3]; /*!< Timer index used in FlexIO I2C. */ + uint32_t baudrate; /*!< Master transfer baudrate, used to calculate delay time. */ +} FLEXIO_I2C_Type; + +/*! @brief Define FlexIO I2C master user configuration structure. */ +typedef struct _flexio_i2c_master_config +{ + bool enableMaster; /*!< Enables the FlexIO I2C peripheral at initialization time. */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, fast access requires + the FlexIO clock to be at least twice the frequency of the bus clock. */ + uint32_t baudRate_Bps; /*!< Baud rate in Bps. */ +} flexio_i2c_master_config_t; + +/*! @brief Define FlexIO I2C master transfer structure. */ +typedef struct _flexio_i2c_master_transfer +{ + uint32_t flags; /*!< Transfer flag which controls the transfer, reserved for FlexIO I2C. */ + uint8_t slaveAddress; /*!< 7-bit slave address. */ + flexio_i2c_direction_t direction; /*!< Transfer direction, read or write. */ + uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ + uint8_t subaddressSize; /*!< Size of command buffer. */ + uint8_t volatile *data; /*!< Transfer buffer. */ + volatile size_t dataSize; /*!< Transfer size. */ +} flexio_i2c_master_transfer_t; + +/*! @brief FlexIO I2C master handle typedef. */ +typedef struct _flexio_i2c_master_handle flexio_i2c_master_handle_t; + +/*! @brief FlexIO I2C master transfer callback typedef. */ +typedef void (*flexio_i2c_master_transfer_callback_t)(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Define FlexIO I2C master handle structure. */ +struct _flexio_i2c_master_handle +{ + flexio_i2c_master_transfer_t transfer; /*!< FlexIO I2C master transfer copy. */ + size_t transferSize; /*!< Total bytes to be transferred. */ + uint8_t state; /*!< Transfer state maintained during transfer. */ + flexio_i2c_master_transfer_callback_t completionCallback; /*!< Callback function called at transfer event. */ + /*!< Callback function called at transfer event. */ + void *userData; /*!< Callback parameter passed to callback function. */ + bool needRestart; /*!< Whether master needs to send re-start signal. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_STATUS) && FSL_FEATURE_FLEXIO_HAS_PIN_STATUS +/*! + * @brief Make sure the bus isn't already pulled down. + * + * Check the FLEXIO pin status to see whether either of SDA and SCL pin is pulled down. + * + * @param base Pointer to FLEXIO_I2C_Type structure.. + * @retval kStatus_Success + * @retval kStatus_FLEXIO_I2C_Busy + */ +status_t FLEXIO_I2C_CheckForBusyBus(FLEXIO_I2C_Type *base); +#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_STATUS*/ + +/*! + * @brief Ungates the FlexIO clock, resets the FlexIO module, and configures the FlexIO I2C + * hardware configuration. + * + * Example + @code + FLEXIO_I2C_Type base = { + .flexioBase = FLEXIO, + .SDAPinIndex = 0, + .SCLPinIndex = 1, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_i2c_master_config_t config = { + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 100000 + }; + FLEXIO_I2C_MasterInit(base, &config, srcClock_Hz); + @endcode + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param masterConfig Pointer to flexio_i2c_master_config_t structure. + * @param srcClock_Hz FlexIO source clock in Hz. + * @retval kStatus_Success Initialization successful + * @retval kStatus_InvalidArgument The source clock exceed upper range limitation +*/ +status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief De-initializes the FlexIO I2C master peripheral. Calling this API Resets the FlexIO I2C master + * shifer and timer config, module can't work unless the FLEXIO_I2C_MasterInit is called. + * + * @param base pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base); + +/*! + * @brief Gets the default configuration to configure the FlexIO module. The configuration + * can be used directly for calling the FLEXIO_I2C_MasterInit(). + * + * Example: + @code + flexio_i2c_master_config_t config; + FLEXIO_I2C_MasterGetDefaultConfig(&config); + @endcode + * @param masterConfig Pointer to flexio_i2c_master_config_t structure. +*/ +void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig); + +/*! + * @brief Enables/disables the FlexIO module operation. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param enable Pass true to enable module, false does not have any effect. + */ +static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable) +{ + if (enable) + { + base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } +} + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the FlexIO I2C master status flags. + * + * @param base Pointer to FLEXIO_I2C_Type structure + * @return Status flag, use status flag to AND #_flexio_i2c_master_status_flags can get the related status. + */ + +uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base); + +/*! + * @brief Clears the FlexIO I2C master status flags. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param mask Status flag. + * The parameter can be any combination of the following values: + * @arg kFLEXIO_I2C_RxFullFlag + * @arg kFLEXIO_I2C_ReceiveNakFlag + */ + +void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask); + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the FlexIO i2c master interrupt requests. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param mask Interrupt source. + * Currently only one interrupt request source: + * @arg kFLEXIO_I2C_TransferCompleteInterruptEnable + */ +void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask); + +/*! + * @brief Disables the FlexIO I2C master interrupt requests. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param mask Interrupt source. + */ +void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask); + +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Sets the FlexIO I2C master transfer baudrate. + * + * @param base Pointer to FLEXIO_I2C_Type structure + * @param baudRate_Bps the baud rate value in HZ + * @param srcClock_Hz source clock in HZ + */ +void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Sends START + 7-bit address to the bus. + * + * @note This API should be called when the transfer configuration is ready to send a START signal + * and 7-bit address to the bus. This is a non-blocking API, which returns directly after the address + * is put into the data register but the address transfer is not finished on the bus. Ensure that + * the kFLEXIO_I2C_RxFullFlag status is asserted before calling this API. + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param address 7-bit address. + * @param direction transfer direction. + * This parameter is one of the values in flexio_i2c_direction_t: + * @arg kFLEXIO_I2C_Write: Transmit + * @arg kFLEXIO_I2C_Read: Receive + */ + +void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction); + +/*! + * @brief Sends the stop signal on the bus. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base); + +/*! + * @brief Sends the repeated start signal on the bus. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base); + +/*! + * @brief Sends the stop signal when transfer is still on-going. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + */ +void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base); + +/*! + * @brief Configures the sent ACK/NAK for the following byte. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param enable True to configure send ACK, false configure to send NAK. + */ +void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable); + +/*! + * @brief Sets the number of bytes to be transferred from a start signal to a stop signal. + * + * @note Call this API before a transfer begins because the timer generates a number of clocks according + * to the number of bytes that need to be transferred. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param count Number of bytes need to be transferred from a start signal to a re-start/stop signal + * @retval kStatus_Success Successfully configured the count. + * @retval kStatus_InvalidArgument Input argument is invalid. + */ +status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint16_t count); + +/*! + * @brief Writes one byte of data to the I2C bus. + * + * @note This is a non-blocking API, which returns directly after the data is put into the + * data register but the data transfer is not finished on the bus. Ensure that + * the TxEmptyFlag is asserted before calling this API. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param data a byte of data. + */ +static inline void FLEXIO_I2C_MasterWriteByte(FLEXIO_I2C_Type *base, uint32_t data) +{ + base->flexioBase->SHIFTBUFBBS[base->shifterIndex[0]] = data; +} + +/*! + * @brief Reads one byte of data from the I2C bus. + * + * @note This is a non-blocking API, which returns directly after the data is read from the + * data register. Ensure that the data is ready in the register. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @return data byte read. + */ +static inline uint8_t FLEXIO_I2C_MasterReadByte(FLEXIO_I2C_Type *base) +{ + return (uint8_t)(base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]); +} + +/*! + * @brief Sends a buffer of data in bytes. + * + * @note This function blocks via polling until all bytes have been sent. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param txBuff The data bytes to send. + * @param txSize The number of data bytes to send. + * @retval kStatus_Success Successfully write data. + * @retval kStatus_FLEXIO_I2C_Nak Receive NAK during writing data. + * @retval kStatus_FLEXIO_I2C_Timeout Timeout polling status flags. + */ +status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize); + +/*! + * @brief Receives a buffer of bytes. + * + * @note This function blocks via polling until all bytes have been received. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param rxBuff The buffer to store the received bytes. + * @param rxSize The number of data bytes to be received. + * @retval kStatus_Success Successfully read data. + * @retval kStatus_FLEXIO_I2C_Timeout Timeout polling status flags. + */ +status_t FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to receiving NAK. + * + * @param base pointer to FLEXIO_I2C_Type structure. + * @param xfer pointer to flexio_i2c_master_transfer_t structure. + * @return status of status_t. + */ +status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer); +/*! @} */ + +/*Transactional APIs*/ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the I2C handle which is used in transactional functions. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param handle Pointer to flexio_i2c_master_handle_t structure to store the transfer state. + * @param callback Pointer to user callback function. + * @param userData User param passed to the callback function. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/isr table out of range. + */ +status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a master interrupt non-blocking transfer on the I2C bus. + * + * @note The API returns immediately after the transfer initiates. + * Call FLEXIO_I2C_MasterTransferGetCount to poll the transfer status to check whether + * the transfer is finished. If the return status is not kStatus_FLEXIO_I2C_Busy, the transfer + * is finished. + * + * @param base Pointer to FLEXIO_I2C_Type structure + * @param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state + * @param xfer pointer to flexio_i2c_master_transfer_t structure + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_FLEXIO_I2C_Busy FlexIO I2C is not idle, is running another transfer. + */ +status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base, + flexio_i2c_master_handle_t *handle, + flexio_i2c_master_transfer_t *xfer); + +/*! + * @brief Gets the master transfer status during a interrupt non-blocking transfer. + * + * @param base Pointer to FLEXIO_I2C_Type structure. + * @param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Aborts an interrupt non-blocking transfer early. + * + * @note This API can be called at any time when an interrupt non-blocking transfer initiates + * to abort the transfer early. + * + * @param base Pointer to FLEXIO_I2C_Type structure + * @param handle Pointer to flexio_i2c_master_handle_t structure which stores the transfer state + */ +void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle); + +/*! + * @brief Master interrupt handler. + * + * @param i2cType Pointer to FLEXIO_I2C_Type structure + * @param i2cHandle Pointer to flexio_i2c_master_transfer_t structure + */ +void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*! @} */ + +#endif /*FSL_FLEXIO_I2C_MASTER_H_*/ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_mculcd.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_mculcd.c new file mode 100644 index 00000000000..217b6595a32 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_mculcd.c @@ -0,0 +1,1334 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_mculcd.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_mculcd" +#endif + +/******************************************************************************* + * Definitations + ******************************************************************************/ + +enum _mculcd_transfer_state +{ + kFLEXIO_MCULCD_StateIdle, /*!< No transfer in progress. */ + kFLEXIO_MCULCD_StateReadArray, /*!< Reading array in progress. */ + kFLEXIO_MCULCD_StateWriteArray, /*!< Writing array in progress. */ + kFLEXIO_MCULCD_StateWriteSameValue, /*!< Writing the same value in progress. */ +}; + +/* The TIMCFG[0:7] is used for baud rate divider in dual 8-bit counters baud/bit mode. */ +#define FLEXIO_BAUDRATE_DIV_MASK 0xFFU + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Ungates the FlexIO clock, resets the FlexIO module, configures the + * FlexIO MCULCD hardware, and configures the FlexIO MCULCD with FlexIO MCULCD + * configuration. + * The configuration structure can be filled by the user, or be set with default + * values + * by the ref FLEXIO_MCULCD_GetDefaultConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param config Pointer to the flexio_mculcd_config_t structure. + * param srcClock_Hz FlexIO source clock in Hz. + * retval kStatus_Success Initialization success. + * retval kStatus_InvalidArgument Initialization failed because of invalid + * argument. + */ +status_t FLEXIO_MCULCD_Init(FLEXIO_MCULCD_Type *base, flexio_mculcd_config_t *config, uint32_t srcClock_Hz) +{ + assert(NULL != config); + status_t status; + + flexio_config_t flexioConfig = {config->enable, config->enableInDoze, config->enableInDebug, + config->enableFastAccess}; + + FLEXIO_Init(base->flexioBase, &flexioConfig); + + status = FLEXIO_MCULCD_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); + + if (kStatus_Success == status) + { + base->setCSPin(true); + base->setRSPin(true); + } + + return status; +} + +/*! + * brief Resets the FLEXIO_MCULCD timer and shifter configuration. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + */ +void FLEXIO_MCULCD_Deinit(FLEXIO_MCULCD_Type *base) +{ + FLEXIO_MCULCD_ClearSingleBeatWriteConfig(base); + FLEXIO_MCULCD_ClearSingleBeatReadConfig(base); +} + +/*! + * brief Gets the default configuration to configure the FlexIO MCULCD. + * + * The default configuration value is: + * code + * config->enable = true; + * config->enableInDoze = false; + * config->enableInDebug = true; + * config->enableFastAccess = true; + * config->baudRate_Bps = 96000000U; + * endcode + * param Config Pointer to the flexio_mculcd_config_t structure. + */ +void FLEXIO_MCULCD_GetDefaultConfig(flexio_mculcd_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enable = true; + config->enableInDoze = false; + config->enableInDebug = true; + config->enableFastAccess = true; + config->baudRate_Bps = 96000000U; +} + +/*! + * brief Set desired baud rate. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param baudRate_Bps Desired baud rate in bit-per-second for all data lines combined. + * param srcClock_Hz FLEXIO clock frequency in Hz. + * retval kStatus_Success Set successfully. + * retval kStatus_InvalidArgument Could not set the baud rate. + */ +status_t FLEXIO_MCULCD_SetBaudRate(FLEXIO_MCULCD_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + uint32_t baudRateDiv; + uint32_t baudRatePerDataLine; + uint32_t timerCompare; + status_t status; + + baudRatePerDataLine = baudRate_Bps / (uint32_t)FLEXIO_MCULCD_DATA_BUS_WIDTH; + + baudRateDiv = (srcClock_Hz + baudRatePerDataLine) / (baudRatePerDataLine * 2U); + + if ((0U == baudRateDiv) || (baudRateDiv > (FLEXIO_BAUDRATE_DIV_MASK + 1U))) + { + status = kStatus_InvalidArgument; + } + else + { + baudRateDiv--; + + timerCompare = base->flexioBase->TIMCMP[base->timerIndex]; + + timerCompare = (timerCompare & ~FLEXIO_BAUDRATE_DIV_MASK) | baudRateDiv; + + base->flexioBase->TIMCMP[base->timerIndex] = timerCompare; + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Gets FlexIO MCULCD status flags. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * return status flag; OR'ed value or the ref _flexio_mculcd_status_flags. + * + * note Don't use this function with DMA APIs. + */ +uint32_t FLEXIO_MCULCD_GetStatusFlags(FLEXIO_MCULCD_Type *base) +{ + uint32_t ret = 0U; + uint32_t flags; + + /* Get shifter status. */ + flags = FLEXIO_GetShifterStatusFlags(base->flexioBase); + + if (0U != (flags & (1UL << base->rxShifterEndIndex))) + { + ret |= (uint32_t)kFLEXIO_MCULCD_RxFullFlag; + } + + if (0U != (flags & (1UL << base->txShifterStartIndex))) + { + ret |= (uint32_t)kFLEXIO_MCULCD_TxEmptyFlag; + } + + return ret; +} + +/*! + * brief Clears FlexIO MCULCD status flags. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param mask Status to clear, it is the OR'ed value of ref + * _flexio_mculcd_status_flags. + * + * note Don't use this function with DMA APIs. + */ +void FLEXIO_MCULCD_ClearStatusFlags(FLEXIO_MCULCD_Type *base, uint32_t mask) +{ + uint32_t flags = 0U; + + /* Clear the shifter flags. */ + if (0U != (mask & (uint32_t)kFLEXIO_MCULCD_RxFullFlag)) + { + flags |= (1UL << base->rxShifterEndIndex); + } + + if (0U != (mask & (uint32_t)kFLEXIO_MCULCD_TxEmptyFlag)) + { + flags |= (1UL << base->txShifterStartIndex); + } + + FLEXIO_ClearShifterStatusFlags(base->flexioBase, flags); +} + +/*! + * brief Enables the FlexIO MCULCD interrupt. + * + * This function enables the FlexIO MCULCD interrupt. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param mask Interrupts to enable, it is the OR'ed value of ref + * _flexio_mculcd_interrupt_enable. + */ +void FLEXIO_MCULCD_EnableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask) +{ + uint32_t interrupts = 0U; + + /* Enable shifter interrupts. */ + if (0U != (mask & (uint32_t)kFLEXIO_MCULCD_RxFullFlag)) + { + interrupts |= (1UL << base->rxShifterEndIndex); + } + + if (0U != (mask & (uint32_t)kFLEXIO_MCULCD_TxEmptyFlag)) + { + interrupts |= (1UL << base->txShifterStartIndex); + } + + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, interrupts); +} + +/*! + * brief Disables the FlexIO MCULCD interrupt. + * + * This function disables the FlexIO MCULCD interrupt. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param mask Interrupts to disable, it is the OR'ed value of ref + * _flexio_mculcd_interrupt_enable. + */ +void FLEXIO_MCULCD_DisableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask) +{ + uint32_t interrupts = 0U; + + /* Disable shifter interrupts. */ + if (0U != (mask & (uint32_t)kFLEXIO_MCULCD_RxFullFlag)) + { + interrupts |= (1UL << base->rxShifterEndIndex); + } + + if (0U != (mask & (uint32_t)kFLEXIO_MCULCD_TxEmptyFlag)) + { + interrupts |= (1UL << base->txShifterStartIndex); + } + + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, interrupts); +} + +/*! + * brief Read data from the FLEXIO MCULCD RX shifter buffer. + * + * Read data from the RX shift buffer directly, it does no check whether the + * buffer is empty or not. + * + * If the data bus width is 8-bit: + * code + * uint8_t value; + * value = (uint8_t)FLEXIO_MCULCD_ReadData(base); + * endcode + * + * If the data bus width is 16-bit: + * code + * uint16_t value; + * value = (uint16_t)FLEXIO_MCULCD_ReadData(base); + * endcode + * + * note This function returns the RX shifter buffer value (32-bit) directly. + * The return value should be converted according to data bus width. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * return The data read out. + * + * note Don't use this function with DMA APIs. + */ +uint32_t FLEXIO_MCULCD_ReadData(FLEXIO_MCULCD_Type *base) +{ +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + return base->flexioBase->SHIFTBUFBYS[base->rxShifterEndIndex]; +#else + return base->flexioBase->SHIFTBUFHWS[base->rxShifterEndIndex]; +#endif +} + +/*! + * brief Configures the FLEXIO MCULCD to single beats write mode. + * + * At the begining multiple beats write operation, the FLEXIO MCULCD is configured to + * multiple beats write mode using this function. After write operation, the configuration + * is cleared by ref FLEXIO_MCULCD_ClearSingleBeatWriteConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + * + * note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_SetSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base) +{ + /* + * This function will be called at the beginning of every data writing. For + * performance consideration, it access the FlexIO registers directly, but not + * call FlexIO driver APIs. + */ + + uint32_t timerCompare; + uint32_t timerControl; + + /* Enable the TX Shifter output. */ + base->flexioBase->SHIFTCFG[base->txShifterStartIndex] = + FLEXIO_SHIFTCFG_PWIDTH((uint32_t)FLEXIO_MCULCD_DATA_BUS_WIDTH - 1U) | + FLEXIO_SHIFTCFG_INSRC(kFLEXIO_ShifterInputFromNextShifterOutput); + + base->flexioBase->SHIFTCTL[base->txShifterStartIndex] = + FLEXIO_SHIFTCTL_TIMSEL(base->timerIndex) | FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnPositive) | + FLEXIO_SHIFTCTL_PINCFG(kFLEXIO_PinConfigOutput) | FLEXIO_SHIFTCTL_PINSEL(base->dataPinStartIndex) | + FLEXIO_SHIFTCTL_PINPOL(kFLEXIO_PinActiveHigh) | FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit); + + timerCompare = base->flexioBase->TIMCMP[base->timerIndex] & 0xFFU; + + /* + * TIMCMP[15:8] = (number of beats x 2) - 1. Because the number of beat is 1, + * so the TIMCMP[15:8] is 1. + */ + base->flexioBase->TIMCMP[base->timerIndex] = (1UL << 8U) | timerCompare; + + /* Use TX shifter flag as the inverted timer trigger. Timer output to WR/EN pin. */ + base->flexioBase->TIMCFG[base->timerIndex] = + FLEXIO_TIMCFG_TIMOUT(kFLEXIO_TimerOutputOneNotAffectedByReset) | + FLEXIO_TIMCFG_TIMDEC(kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput) | + FLEXIO_TIMCFG_TIMRST(kFLEXIO_TimerResetNever) | FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare) | + FLEXIO_TIMCFG_TIMENA(kFLEXIO_TimerEnableOnTriggerHigh) | FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled) | + FLEXIO_TIMCFG_TSTART(kFLEXIO_TimerStartBitDisabled); + + /* When initially configure the timer pin as output, the pin may be driven low causing glitch on bus. + Configure the pin as bidirection output first then perform a subsequent write to change to output to avoid the + issue. */ + timerControl = FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterStartIndex)) | + FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) | + FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | + FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData) | + FLEXIO_TIMCTL_PINSEL(base->ENWRPinIndex) | FLEXIO_TIMCTL_PINPOL(kFLEXIO_PinActiveLow) | + FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit); + + base->flexioBase->TIMCTL[base->timerIndex] = timerControl; + timerControl = (timerControl & ~FLEXIO_TIMCTL_PINCFG_MASK) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput); + base->flexioBase->TIMCTL[base->timerIndex] = timerControl; +} + +/*! + * brief Clear the FLEXIO MCULCD single beats write mode configuration. + * + * Clear the write configuration set by ref FLEXIO_MCULCD_SetSingleBeatWriteConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + * + * note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_ClearSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base) +{ + /* Disable the timer. */ + /* Set to bidirection output first then set to disable to avoid glitch on bus. */ + base->flexioBase->TIMCTL[base->timerIndex] = + (base->flexioBase->TIMCTL[base->timerIndex] & ~FLEXIO_TIMCTL_PINCFG_MASK) | + FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData); + base->flexioBase->TIMCTL[base->timerIndex] = 0U; + base->flexioBase->TIMCFG[base->timerIndex] = 0U; + /* Clear the timer flag. */ + base->flexioBase->TIMSTAT = (1UL << base->timerIndex); + /* Stop the TX shifter. */ + base->flexioBase->SHIFTCTL[base->txShifterStartIndex] = 0U; + base->flexioBase->SHIFTCFG[base->txShifterStartIndex] = 0U; + /* Clear the shifter flag. */ + base->flexioBase->SHIFTSTAT = (1UL << base->txShifterStartIndex); +} + +/*! + * brief Configures the FLEXIO MCULCD to single beats read mode. + * + * At the begining or multiple beats read operation, the FLEXIO MCULCD is configured + * to multiple beats read mode using this function. After read operation, the configuration + * is cleared by ref FLEXIO_MCULCD_ClearSingleBeatReadConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + * + * note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_SetSingleBeatReadConfig(FLEXIO_MCULCD_Type *base) +{ + /* + * This function will be called at the beginning of every data reading. For + * performance consideration, it access the FlexIO registers directly, but not + * call FlexIO driver APIs. + */ + + uint8_t timerPin; + uint32_t timerCompare; + flexio_pin_polarity_t timerPinPolarity; + + /* Timer output to RD pin (8080 mode), to WR/EN pin in 6800 mode. */ + if (kFLEXIO_MCULCD_8080 == base->busType) + { + timerPin = base->RDPinIndex; + timerPinPolarity = kFLEXIO_PinActiveLow; + } + else + { + timerPin = base->ENWRPinIndex; + timerPinPolarity = kFLEXIO_PinActiveHigh; + } + + /* Enable the RX Shifter input. */ + base->flexioBase->SHIFTCFG[base->rxShifterEndIndex] = + FLEXIO_SHIFTCFG_PWIDTH((uint32_t)FLEXIO_MCULCD_DATA_BUS_WIDTH - 1U); + + base->flexioBase->SHIFTCTL[base->rxShifterEndIndex] = + FLEXIO_SHIFTCTL_TIMSEL(base->timerIndex) | FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive) | + FLEXIO_SHIFTCTL_PINCFG(kFLEXIO_PinConfigOutputDisabled) | FLEXIO_SHIFTCTL_PINSEL(base->dataPinStartIndex) | + FLEXIO_SHIFTCTL_PINPOL(kFLEXIO_PinActiveHigh) | FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeReceive); + + /* Use RX shifter flag as the inverted timer trigger. */ + base->flexioBase->TIMCFG[base->timerIndex] = + FLEXIO_TIMCFG_TIMOUT(kFLEXIO_TimerOutputOneNotAffectedByReset) | + FLEXIO_TIMCFG_TIMDEC(kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput) | + FLEXIO_TIMCFG_TIMRST(kFLEXIO_TimerResetNever) | FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare) | + FLEXIO_TIMCFG_TIMENA(kFLEXIO_TimerEnableOnTriggerHigh) | + FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable) | + FLEXIO_TIMCFG_TSTART(kFLEXIO_TimerStartBitDisabled); + + timerCompare = base->flexioBase->TIMCMP[base->timerIndex] & 0xFFU; + + /* + * TIMCMP[15:8] = (number of beats x 2) - 1. Because the number of beat is 1, + * so the TIMCMP[15:8] is 1. + */ + base->flexioBase->TIMCMP[base->timerIndex] = (1UL << 8U) | timerCompare; + + base->flexioBase->TIMCTL[base->timerIndex] |= + FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->rxShifterEndIndex)) | + FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) | + FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput) | + FLEXIO_TIMCTL_PINSEL(timerPin) | FLEXIO_TIMCTL_PINPOL(timerPinPolarity) | + FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit); +} + +/*! + * brief Clear the FLEXIO MCULCD single beats read mode configuration. + * + * Clear the read configuration set by ref FLEXIO_MCULCD_SetSingleBeatReadConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + * + * note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_ClearSingleBeatReadConfig(FLEXIO_MCULCD_Type *base) +{ + /* Disable the timer. */ + /* Set to bidirection output first then set to disable to avoid glitch on bus. */ + base->flexioBase->TIMCTL[base->timerIndex] = + (base->flexioBase->TIMCTL[base->timerIndex] & ~FLEXIO_TIMCTL_PINCFG_MASK) | + FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData); + base->flexioBase->TIMCTL[base->timerIndex] = 0U; + base->flexioBase->TIMCFG[base->timerIndex] = 0U; + /* Clear the timer flag. */ + base->flexioBase->TIMSTAT = (1UL << base->timerIndex); + /* Stop the RX shifter. */ + base->flexioBase->SHIFTCTL[base->rxShifterEndIndex] = 0U; + base->flexioBase->SHIFTCFG[base->rxShifterEndIndex] = 0U; + /* Clear the shifter flag. */ + base->flexioBase->SHIFTSTAT = (1UL << base->rxShifterEndIndex); +} + +/*! + * brief Configures the FLEXIO MCULCD to multiple beats write mode. + * + * At the begining multiple beats write operation, the FLEXIO MCULCD is configured to + * multiple beats write mode using this function. After write operation, the configuration + * is cleared by ref FLEXIO_MCULCD_ClearMultBeatsWriteConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + * + * note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_SetMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base) +{ + /* + * This function will be called at the beginning of every data writing. For + * performance consideration, it access the FlexIO registers directly, but not + * call FlexIO driver APIs. + */ + + uint32_t timerCompare; + uint32_t timerControl; + uint8_t beats; + uint8_t i; + + /* Enable the TX Shifter output. */ + base->flexioBase->SHIFTCFG[base->txShifterStartIndex] = + FLEXIO_SHIFTCFG_PWIDTH((uint32_t)FLEXIO_MCULCD_DATA_BUS_WIDTH - 1U) | + FLEXIO_SHIFTCFG_INSRC(kFLEXIO_ShifterInputFromNextShifterOutput); + + base->flexioBase->SHIFTCTL[base->txShifterStartIndex] = + FLEXIO_SHIFTCTL_TIMSEL(base->timerIndex) | FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnPositive) | + FLEXIO_SHIFTCTL_PINCFG(kFLEXIO_PinConfigOutput) | FLEXIO_SHIFTCTL_PINSEL(base->dataPinStartIndex) | + FLEXIO_SHIFTCTL_PINPOL(kFLEXIO_PinActiveHigh) | FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit); + + for (i = base->txShifterStartIndex + 1U; i <= base->txShifterEndIndex; i++) + { + base->flexioBase->SHIFTCFG[i] = FLEXIO_SHIFTCFG_PWIDTH((uint32_t)FLEXIO_MCULCD_DATA_BUS_WIDTH - 1U) | + FLEXIO_SHIFTCFG_INSRC(kFLEXIO_ShifterInputFromNextShifterOutput); + + base->flexioBase->SHIFTCTL[i] = + FLEXIO_SHIFTCTL_TIMSEL(base->timerIndex) | FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnPositive) | + FLEXIO_SHIFTCTL_PINCFG(kFLEXIO_PinConfigOutputDisabled) | FLEXIO_SHIFTCTL_PINSEL(0) | + FLEXIO_SHIFTCTL_PINPOL(kFLEXIO_PinActiveHigh) | FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit); + } + + timerCompare = base->flexioBase->TIMCMP[base->timerIndex] & 0xFFU; + +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + beats = 4U * (base->txShifterEndIndex - base->txShifterStartIndex + 1U); +#else + beats = 2U * (base->txShifterEndIndex - base->txShifterStartIndex + 1U); +#endif + + /* + * TIMCMP[15:8] = (number of beats x 2) - 1. + */ + base->flexioBase->TIMCMP[base->timerIndex] = ((beats * 2UL - 1UL) << 8U) | timerCompare; + + /* Use TX shifter flag as the inverted timer trigger. Timer output to WR/EN pin. */ + base->flexioBase->TIMCFG[base->timerIndex] = + FLEXIO_TIMCFG_TIMOUT(kFLEXIO_TimerOutputOneNotAffectedByReset) | + FLEXIO_TIMCFG_TIMDEC(kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput) | + FLEXIO_TIMCFG_TIMRST(kFLEXIO_TimerResetNever) | FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare) | + FLEXIO_TIMCFG_TIMENA(kFLEXIO_TimerEnableOnTriggerHigh) | FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled) | + FLEXIO_TIMCFG_TSTART(kFLEXIO_TimerStartBitDisabled); + + /* When initially configure the timer pin as output, the pin may be driven low causing glitch on bus. + Configure the pin as bidirection output first then perform a subsequent write to change to output to avoid the + issue. */ + timerControl = FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterEndIndex)) | + FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) | + FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | + FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData) | + FLEXIO_TIMCTL_PINSEL(base->ENWRPinIndex) | FLEXIO_TIMCTL_PINPOL(kFLEXIO_PinActiveLow) | + FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit); + + base->flexioBase->TIMCTL[base->timerIndex] = timerControl; + timerControl = (timerControl & ~FLEXIO_TIMCTL_PINCFG_MASK) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput); + base->flexioBase->TIMCTL[base->timerIndex] = timerControl; +} + +/*! + * brief Clear the FLEXIO MCULCD multiple beats write mode configuration. + * + * Clear the write configuration set by ref FLEXIO_MCULCD_SetMultBeatsWriteConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + * + * note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_ClearMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base) +{ + uint8_t i; + uint32_t statusFlags = 0U; + + /* Disable the timer. */ + /* Set to bidirection output first then set to disable to avoid glitch on bus. */ + base->flexioBase->TIMCTL[base->timerIndex] = + (base->flexioBase->TIMCTL[base->timerIndex] & ~FLEXIO_TIMCTL_PINCFG_MASK) | + FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData); + base->flexioBase->TIMCTL[base->timerIndex] = 0U; + base->flexioBase->TIMCFG[base->timerIndex] = 0U; + /* Clear the timer flag. */ + base->flexioBase->TIMSTAT = (1UL << base->timerIndex); + + /* Stop the TX shifter. */ + for (i = base->txShifterStartIndex; i <= base->txShifterEndIndex; i++) + { + base->flexioBase->SHIFTCFG[i] = 0U; + base->flexioBase->SHIFTCTL[i] = 0U; + statusFlags |= (1UL << i); + } + /* Clear the shifter flag. */ + base->flexioBase->SHIFTSTAT = statusFlags; +} + +/*! + * brief Configures the FLEXIO MCULCD to multiple beats read mode. + * + * At the begining or multiple beats read operation, the FLEXIO MCULCD is configured + * to multiple beats read mode using this function. After read operation, the configuration + * is cleared by ref FLEXIO_MCULCD_ClearMultBeatsReadConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + * + * note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_SetMultiBeatsReadConfig(FLEXIO_MCULCD_Type *base) +{ + /* + * This function will be called at the beginning of every data reading. For + * performance consideration, it access the FlexIO registers directly, but not + * call FlexIO driver APIs. + */ + + uint8_t timerPin; + uint8_t beats; + uint8_t i; + uint32_t timerCompare; + flexio_pin_polarity_t timerPinPolarity; + + /* Timer output to RD pin (8080 mode), to WR/EN pin in 6800 mode. */ + if (kFLEXIO_MCULCD_8080 == base->busType) + { + timerPin = base->RDPinIndex; + timerPinPolarity = kFLEXIO_PinActiveLow; + } + else + { + timerPin = base->ENWRPinIndex; + timerPinPolarity = kFLEXIO_PinActiveHigh; + } + + /* Enable the RX Shifter input. */ + for (i = base->rxShifterStartIndex; i < base->rxShifterEndIndex; i++) + { + base->flexioBase->SHIFTCFG[i] = FLEXIO_SHIFTCFG_PWIDTH((uint32_t)FLEXIO_MCULCD_DATA_BUS_WIDTH - 1U) | + FLEXIO_SHIFTCFG_INSRC(kFLEXIO_ShifterInputFromNextShifterOutput); + + base->flexioBase->SHIFTCTL[i] = + FLEXIO_SHIFTCTL_TIMSEL(base->timerIndex) | FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive) | + FLEXIO_SHIFTCTL_PINCFG(kFLEXIO_PinConfigOutputDisabled) | FLEXIO_SHIFTCTL_PINSEL(base->dataPinStartIndex) | + FLEXIO_SHIFTCTL_PINPOL(kFLEXIO_PinActiveHigh) | FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeReceive); + } + + base->flexioBase->SHIFTCFG[base->rxShifterEndIndex] = + FLEXIO_SHIFTCFG_PWIDTH((uint32_t)FLEXIO_MCULCD_DATA_BUS_WIDTH - 1U); + base->flexioBase->SHIFTCTL[base->rxShifterEndIndex] = + FLEXIO_SHIFTCTL_TIMSEL(base->timerIndex) | FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive) | + FLEXIO_SHIFTCTL_PINCFG(kFLEXIO_PinConfigOutputDisabled) | FLEXIO_SHIFTCTL_PINSEL(base->dataPinStartIndex) | + FLEXIO_SHIFTCTL_PINPOL(kFLEXIO_PinActiveHigh) | FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeReceive); + + timerCompare = base->flexioBase->TIMCMP[base->timerIndex] & 0xFFU; + +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + beats = 4U * (base->rxShifterEndIndex - base->rxShifterStartIndex + 1U); +#else + beats = 2U * (base->rxShifterEndIndex - base->rxShifterStartIndex + 1U); +#endif + + /* + * TIMCMP[15:8] = (number of beats x 2) - 1. + */ + base->flexioBase->TIMCMP[base->timerIndex] = ((beats * 2UL - 1UL) << 8U) | timerCompare; + + /* Use RX shifter flag as the inverted timer trigger. */ + base->flexioBase->TIMCFG[base->timerIndex] = + FLEXIO_TIMCFG_TIMOUT(kFLEXIO_TimerOutputOneNotAffectedByReset) | + FLEXIO_TIMCFG_TIMDEC(kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput) | + FLEXIO_TIMCFG_TIMRST(kFLEXIO_TimerResetNever) | FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare) | + FLEXIO_TIMCFG_TIMENA(kFLEXIO_TimerEnableOnTriggerHigh) | + FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable) | + FLEXIO_TIMCFG_TSTART(kFLEXIO_TimerStartBitDisabled); + + base->flexioBase->TIMCTL[base->timerIndex] |= + FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->rxShifterEndIndex)) | + FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) | + FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput) | + FLEXIO_TIMCTL_PINSEL(timerPin) | FLEXIO_TIMCTL_PINPOL(timerPinPolarity) | + FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit); +} + +/*! + * brief Clear the FLEXIO MCULCD multiple beats read mode configuration. + * + * Clear the read configuration set by ref FLEXIO_MCULCD_SetMultBeatsReadConfig. + * + * param base Pointer to the FLEXIO_MCULCD_Type. + * + * note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_ClearMultiBeatsReadConfig(FLEXIO_MCULCD_Type *base) +{ + uint8_t i; + uint32_t statusFlags = 0U; + + /* Disable the timer. */ + /* Set to bidirection output first then set to disable to avoid glitch on bus. */ + base->flexioBase->TIMCTL[base->timerIndex] = + (base->flexioBase->TIMCTL[base->timerIndex] & ~FLEXIO_TIMCTL_PINCFG_MASK) | + FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData); + base->flexioBase->TIMCTL[base->timerIndex] = 0U; + base->flexioBase->TIMCFG[base->timerIndex] = 0U; + /* Clear the timer flag. */ + base->flexioBase->TIMSTAT = (1UL << base->timerIndex); + /* Stop the RX shifter. */ + for (i = base->rxShifterStartIndex; i <= base->rxShifterEndIndex; i++) + { + base->flexioBase->SHIFTCTL[i] = 0U; + base->flexioBase->SHIFTCFG[i] = 0U; + statusFlags |= (1UL << i); + } + /* Clear the shifter flag. */ + base->flexioBase->SHIFTSTAT = statusFlags; +} + +/*! + * brief Wait for transmit data send out finished. + * + * Currently there is no effective method to wait for the data send out + * from the shiter, so here use a while loop to wait. + * + * note This is an internal used function. + */ +void FLEXIO_MCULCD_WaitTransmitComplete(void) +{ + uint32_t i = FLEXIO_MCULCD_WAIT_COMPLETE_TIME; + + while (0U != (i--)) + { + __NOP(); + } +} + +/*! + * brief Send command in blocking way. + * + * This function sends the command and returns when the command has been sent + * out. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param command The command to send. + */ +void FLEXIO_MCULCD_WriteCommandBlocking(FLEXIO_MCULCD_Type *base, uint32_t command) +{ + FLEXIO_Type *flexioBase = base->flexioBase; + + /* De-assert the RS pin. */ + base->setRSPin(false); + + /* For 6800, de-assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(false); + } + + /* Configure the timer and TX shifter. */ + FLEXIO_MCULCD_SetSingleBeatWriteConfig(base); + + /* Write command to shifter buffer. */ + flexioBase->SHIFTBUF[base->txShifterStartIndex] = command; + + /* Wait for command send out. */ + while (0U == ((1UL << base->timerIndex) & FLEXIO_GetTimerStatusFlags(flexioBase))) + { + } + + /* Stop the timer and TX shifter. */ + FLEXIO_MCULCD_ClearSingleBeatWriteConfig(base); + + /* Assert the RS pin. */ + base->setRSPin(true); + /* For 6800, assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(true); + } +} + +/*! + * brief Send data array in blocking way. + * + * This function sends the data array and returns when the data sent out. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param data The data array to send. + * param size How many bytes to write. + */ +void FLEXIO_MCULCD_WriteDataArrayBlocking(FLEXIO_MCULCD_Type *base, const void *data, size_t size) +{ + assert(size > 0U); + + uint32_t i; +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + const uint8_t *data8Bit; +#else + const uint16_t *data16Bit; +#endif + FLEXIO_Type *flexioBase = base->flexioBase; + + /* Assert the RS pin. */ + base->setRSPin(true); + /* For 6800, de-assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(false); + } + + /* Configure the timer and TX shifter. */ + FLEXIO_MCULCD_SetSingleBeatWriteConfig(base); + +/* If data bus width is 8. */ +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + data8Bit = (const uint8_t *)data; + + for (i = 0; i < size; i++) + { + flexioBase->SHIFTBUF[base->txShifterStartIndex] = data8Bit[i]; + + /* Wait for the data send out. */ + while (0U == ((1UL << base->timerIndex) & flexioBase->TIMSTAT)) + { + } + + /* Clear the timer stat. */ + flexioBase->TIMSTAT = 1UL << base->timerIndex; + } +#else + data16Bit = (const uint16_t *)data; + size /= 2U; + + for (i = 0; i < size; i++) + { + flexioBase->SHIFTBUF[base->txShifterStartIndex] = data16Bit[i]; + + /* Wait for the data send out. */ + while (0U == ((1UL << base->timerIndex) & flexioBase->TIMSTAT)) + { + } + + /* Clear the timer stat. */ + flexioBase->TIMSTAT = 1UL << base->timerIndex; + } +#endif + + /* Stop the timer and TX shifter. */ + FLEXIO_MCULCD_ClearSingleBeatWriteConfig(base); +} + +/*! + * brief Read data into array in blocking way. + * + * This function reads the data into array and returns when the data read + * finished. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param data The array to save the data. + * param size How many bytes to read. + */ +void FLEXIO_MCULCD_ReadDataArrayBlocking(FLEXIO_MCULCD_Type *base, void *data, size_t size) +{ + assert(size > 0U); + + uint32_t i; + +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + uint8_t *data8Bit = (uint8_t *)data; +#else + uint16_t *data16Bit = (uint16_t *)data; +#endif + FLEXIO_Type *flexioBase = base->flexioBase; + + /* Assert the RS pin. */ + base->setRSPin(true); + /* For 6800, de-assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(false); + } + + /* Enable the timer and RX shifter. */ + FLEXIO_MCULCD_SetSingleBeatReadConfig(base); + +/* If data bus width is 8. */ +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + for (i = 0; i < (size - 1U); i++) + { + /* Wait for shifter buffer full. */ + while (0U == ((1UL << base->rxShifterEndIndex) & FLEXIO_GetShifterStatusFlags(flexioBase))) + { + } + + data8Bit[i] = (uint8_t)flexioBase->SHIFTBUFBYS[base->rxShifterEndIndex]; + } +#else + /* Data bus width is 16. */ + size /= 2U; + + for (i = 0; i < (size - 1U); i++) + { + /* Wait for shifter buffer full. */ + while (0U == ((1UL << base->rxShifterEndIndex) & FLEXIO_GetShifterStatusFlags(flexioBase))) + { + } + + data16Bit[i] = (uint16_t)flexioBase->SHIFTBUFHWS[base->rxShifterEndIndex]; + } +#endif + + /* Wait for shifter buffer full. */ + while (0U == ((1UL << base->rxShifterEndIndex) & FLEXIO_GetShifterStatusFlags(flexioBase))) + { + } + + /* Stop the timer and disable the RX shifter. */ + FLEXIO_MCULCD_ClearSingleBeatReadConfig(base); + +/* Read out the last data. */ +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + data8Bit[i] = (uint8_t)flexioBase->SHIFTBUFBYS[base->rxShifterEndIndex]; +#else + data16Bit[i] = (uint16_t)flexioBase->SHIFTBUFHWS[base->rxShifterEndIndex]; +#endif +} + +/*! + * brief Send the same value many times in blocking way. + * + * This function sends the same value many times. It could be used to clear the + * LCD screen. If the data bus width is 8, this function will send LSB 8 bits of + * p sameValue for p size times. If the data bus is 16, this function will send + * LSB 16 bits of p sameValue for p size / 2 times. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param sameValue The same value to send. + * param size How many bytes to send. + */ +void FLEXIO_MCULCD_WriteSameValueBlocking(FLEXIO_MCULCD_Type *base, uint32_t sameValue, size_t size) +{ + assert(size > 0U); + + uint32_t i; + FLEXIO_Type *flexioBase = base->flexioBase; + +#if (16 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + size /= 2U; +#endif + + /* Assert the RS pin. */ + base->setRSPin(true); + /* For 6800, de-assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(false); + } + + /* Configure the timer and TX shifter. */ + FLEXIO_MCULCD_SetSingleBeatWriteConfig(base); + + for (i = 0; i < size; i++) + { + flexioBase->SHIFTBUF[base->txShifterStartIndex] = sameValue; + + /* Wait for the data send out. */ + while (0U == ((1UL << base->timerIndex) & flexioBase->TIMSTAT)) + { + } + + /* Clear the timer stat. */ + flexioBase->TIMSTAT = 1UL << base->timerIndex; + } + + /* Stop the timer and TX shifter. */ + FLEXIO_MCULCD_ClearSingleBeatWriteConfig(base); +} + +/*! + * brief Performs a polling transfer. + * + * note The API does not return until the transfer finished. + * + * param base pointer to FLEXIO_MCULCD_Type structure. + * param xfer pointer to flexio_mculcd_transfer_t structure. + */ +void FLEXIO_MCULCD_TransferBlocking(FLEXIO_MCULCD_Type *base, flexio_mculcd_transfer_t *xfer) +{ + FLEXIO_MCULCD_StartTransfer(base); + + if (!xfer->dataOnly) + { + FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + } + + if (xfer->dataSize > 0U) + { + if (kFLEXIO_MCULCD_ReadArray == xfer->mode) + { + FLEXIO_MCULCD_ReadDataArrayBlocking(base, (uint8_t *)(xfer->dataAddrOrSameValue), xfer->dataSize); + } + else if (kFLEXIO_MCULCD_WriteArray == xfer->mode) + { + FLEXIO_MCULCD_WriteDataArrayBlocking(base, (uint8_t *)(xfer->dataAddrOrSameValue), xfer->dataSize); + } + else + { + FLEXIO_MCULCD_WriteSameValueBlocking(base, xfer->dataAddrOrSameValue, xfer->dataSize); + } + } + + FLEXIO_MCULCD_StopTransfer(base); +} + +/*! + * brief Initializes the FlexIO MCULCD handle, which is used in transactional + * functions. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + * param callback The callback function. + * param userData The parameter of the callback function. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_MCULCD_TransferCreateHandle(FLEXIO_MCULCD_Type *base, + flexio_mculcd_handle_t *handle, + flexio_mculcd_transfer_callback_t callback, + void *userData) +{ + assert(NULL != handle); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + + /* Register callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Enable interrupt in NVIC. */ + (void)EnableIRQ(flexio_irqs[FLEXIO_GetInstance(base->flexioBase)]); + + /* Save the context in global variables to support the double weak mechanism. + */ + return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_MCULCD_TransferHandleIRQ); +} + +/*! + * brief Transfer data using IRQ. + * + * This function sends data using IRQ. This is a non-blocking function, which + * returns right away. When all data is sent out/received, the callback + * function is called. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + * param xfer FlexIO MCULCD transfer structure. See #flexio_mculcd_transfer_t. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_FLEXIO_MCULCD_Busy MCULCD is busy with another transfer. + */ +status_t FLEXIO_MCULCD_TransferNonBlocking(FLEXIO_MCULCD_Type *base, + flexio_mculcd_handle_t *handle, + flexio_mculcd_transfer_t *xfer) +{ + /* If previous transfer is in progress. */ + if ((uint32_t)kFLEXIO_MCULCD_StateIdle != handle->state) + { + return kStatus_FLEXIO_MCULCD_Busy; + } + + /* Set the state in handle. */ + if (kFLEXIO_MCULCD_ReadArray == xfer->mode) + { + handle->state = (uint32_t)kFLEXIO_MCULCD_StateReadArray; + } + else if (kFLEXIO_MCULCD_WriteArray == xfer->mode) + { + handle->state = (uint32_t)kFLEXIO_MCULCD_StateWriteArray; + } + else + { + handle->state = (uint32_t)kFLEXIO_MCULCD_StateWriteSameValue; + } + + /* Assert the nCS. */ + FLEXIO_MCULCD_StartTransfer(base); + + if (!xfer->dataOnly) + { + /* Send the command. */ + FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + } + + /* If transfer count is 0 (only to send command), return directly. */ + if (0U == xfer->dataSize) + { + handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + + /* De-assert the nCS. */ + FLEXIO_MCULCD_StopTransfer(base); + + if (NULL != handle->completionCallback) + { + handle->completionCallback(base, handle, kStatus_FLEXIO_MCULCD_Idle, handle->userData); + } + } + else + { +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + handle->dataCount = xfer->dataSize; +#else + handle->dataCount = xfer->dataSize / 2U; +#endif + + handle->remainingCount = handle->dataCount; + + handle->dataAddrOrSameValue = xfer->dataAddrOrSameValue; + + /* Enable interrupt. */ + if (kFLEXIO_MCULCD_ReadArray == xfer->mode) + { + /* For 6800, assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(true); + } + FLEXIO_MCULCD_SetSingleBeatReadConfig(base); + FLEXIO_MCULCD_EnableInterrupts(base, (uint32_t)kFLEXIO_MCULCD_RxFullInterruptEnable); + } + else + { + /* For 6800, de-assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(false); + } + FLEXIO_MCULCD_SetSingleBeatWriteConfig(base); + FLEXIO_MCULCD_EnableInterrupts(base, (uint32_t)kFLEXIO_MCULCD_TxEmptyInterruptEnable); + } + } + + return kStatus_Success; +} + +/*! + * brief Aborts the data transfer, which used IRQ. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + */ +void FLEXIO_MCULCD_TransferAbort(FLEXIO_MCULCD_Type *base, flexio_mculcd_handle_t *handle) +{ + /* If no transfer in process, return directly. */ + if ((uint32_t)kFLEXIO_MCULCD_StateIdle == handle->state) + { + return; + } + + /* Disable the interrupt. */ + FLEXIO_MCULCD_DisableInterrupts( + base, (uint32_t)kFLEXIO_MCULCD_RxFullInterruptEnable | (uint32_t)kFLEXIO_MCULCD_TxEmptyInterruptEnable); + + if ((uint32_t)kFLEXIO_MCULCD_StateReadArray == handle->state) + { + /* Stop the timer and disable the RX shifter. */ + FLEXIO_MCULCD_ClearSingleBeatReadConfig(base); + } + else + { + /* Stop the timer and disable the TX shifter. */ + FLEXIO_MCULCD_ClearSingleBeatWriteConfig(base); + } + + /* Clean the flags. */ + FLEXIO_MCULCD_ClearStatusFlags(base, (uint32_t)kFLEXIO_MCULCD_TxEmptyFlag | (uint32_t)kFLEXIO_MCULCD_RxFullFlag); + + /* De-assert the nCS. */ + FLEXIO_MCULCD_StopTransfer(base); + + handle->dataCount = 0; + handle->remainingCount = 0; + handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; +} + +/*! + * brief Gets the data transfer status which used IRQ. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + * param count How many bytes transferred so far by the non-blocking transaction. + * retval kStatus_Success Get the transferred count Successfully. + * retval kStatus_NoTransferInProgress No transfer in process. + */ +status_t FLEXIO_MCULCD_TransferGetCount(FLEXIO_MCULCD_Type *base, flexio_mculcd_handle_t *handle, size_t *count) +{ + assert(NULL != count); + + if ((uint32_t)kFLEXIO_MCULCD_StateIdle == handle->state) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->dataCount - handle->remainingCount; + +#if (16 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + *count *= 2U; +#endif + + return kStatus_Success; +} + +/*! + * brief FlexIO MCULCD IRQ handler function. + * + * param base Pointer to the FLEXIO_MCULCD_Type structure. + * param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + */ +void FLEXIO_MCULCD_TransferHandleIRQ(void *base, void *handle) +{ + FLEXIO_MCULCD_Type *flexioLcdMcuBase = (FLEXIO_MCULCD_Type *)base; + flexio_mculcd_handle_t *flexioLcdMcuHandle = (flexio_mculcd_handle_t *)handle; + uint32_t statusFlags = FLEXIO_MCULCD_GetStatusFlags(flexioLcdMcuBase); + uint32_t data; + + if ((uint32_t)kFLEXIO_MCULCD_StateReadArray == flexioLcdMcuHandle->state) + { + /* Handle the reading process. */ + while ((0U != ((uint32_t)kFLEXIO_MCULCD_RxFullFlag & statusFlags)) && (flexioLcdMcuHandle->remainingCount > 0U)) + { + if (1U == flexioLcdMcuHandle->remainingCount) + { + /* If this is the last data, stop the RX shifter and timer. */ + FLEXIO_MCULCD_DisableInterrupts(flexioLcdMcuBase, (uint32_t)kFLEXIO_MCULCD_RxFullInterruptEnable); + FLEXIO_MCULCD_ClearSingleBeatReadConfig(flexioLcdMcuBase); + FLEXIO_MCULCD_StopTransfer(flexioLcdMcuBase); + } + + /* Read out the data. */ + data = FLEXIO_MCULCD_ReadData(flexioLcdMcuBase); + +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + *(uint8_t *)(flexioLcdMcuHandle->dataAddrOrSameValue) = (uint8_t)data; + flexioLcdMcuHandle->dataAddrOrSameValue++; +#else + *(uint16_t *)(flexioLcdMcuHandle->dataAddrOrSameValue) = (uint16_t)data; + flexioLcdMcuHandle->dataAddrOrSameValue += 2U; +#endif + + flexioLcdMcuHandle->remainingCount--; + + /* Transfer finished, call the callback. */ + if (0U == flexioLcdMcuHandle->remainingCount) + { + flexioLcdMcuHandle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + + if (NULL != flexioLcdMcuHandle->completionCallback) + { + flexioLcdMcuHandle->completionCallback(flexioLcdMcuBase, flexioLcdMcuHandle, + kStatus_FLEXIO_MCULCD_Idle, flexioLcdMcuHandle->userData); + } + } + + /* Is the shifter buffer ready to send the next data? */ + statusFlags = FLEXIO_MCULCD_GetStatusFlags(flexioLcdMcuBase); + } + } + else + { + /* Handle the writing process. */ + while ((0U != ((uint32_t)kFLEXIO_MCULCD_TxEmptyFlag & statusFlags)) && + (flexioLcdMcuHandle->remainingCount > 0U)) + { + /* Send the data. */ + if ((uint32_t)kFLEXIO_MCULCD_StateWriteSameValue == flexioLcdMcuHandle->state) + { + data = flexioLcdMcuHandle->dataAddrOrSameValue; + } + else + { +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + data = *(uint8_t *)(flexioLcdMcuHandle->dataAddrOrSameValue); + flexioLcdMcuHandle->dataAddrOrSameValue++; +#else + data = *(uint16_t *)(flexioLcdMcuHandle->dataAddrOrSameValue); + flexioLcdMcuHandle->dataAddrOrSameValue += 2U; +#endif + } + + /* If this is the last data to send, delay to wait for the data shift out. */ + if (1U == flexioLcdMcuHandle->remainingCount) + { + FLEXIO_MCULCD_DisableInterrupts(flexioLcdMcuBase, (uint32_t)kFLEXIO_MCULCD_TxEmptyInterruptEnable); + + /* Write the last data. */ + FLEXIO_MCULCD_WriteData(flexioLcdMcuBase, data); + + /* Wait for the last data send finished. */ + FLEXIO_MCULCD_WaitTransmitComplete(); + flexioLcdMcuHandle->remainingCount = 0; + + FLEXIO_MCULCD_ClearSingleBeatWriteConfig(flexioLcdMcuBase); + FLEXIO_MCULCD_StopTransfer(flexioLcdMcuBase); + flexioLcdMcuHandle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + + if (NULL != flexioLcdMcuHandle->completionCallback) + { + flexioLcdMcuHandle->completionCallback(flexioLcdMcuBase, flexioLcdMcuHandle, + kStatus_FLEXIO_MCULCD_Idle, flexioLcdMcuHandle->userData); + } + } + else + { + FLEXIO_MCULCD_WriteData(flexioLcdMcuBase, data); + flexioLcdMcuHandle->remainingCount--; + } + /* Is the shifter buffer ready to send the next data? */ + statusFlags = FLEXIO_MCULCD_GetStatusFlags(flexioLcdMcuBase); + } + } +} \ No newline at end of file diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_mculcd.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_mculcd.h new file mode 100644 index 00000000000..298287b48da --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_mculcd.h @@ -0,0 +1,686 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_FLEXIO_MCULCD_H_ +#define FSL_FLEXIO_MCULCD_H_ + +#include "fsl_common.h" +#include "fsl_flexio.h" + +/*! + * @addtogroup flexio_mculcd + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief FlexIO MCULCD driver version. */ +#define FSL_FLEXIO_MCULCD_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*! @} */ + +#ifndef FLEXIO_MCULCD_WAIT_COMPLETE_TIME +/*! + * @brief The delay time to wait for FLEXIO transmit complete. + * + * Currently there is no method to detect whether the data has been + * sent out from the shifter, so the driver use a software delay for this. When + * the data is written to shifter buffer, the driver call the delay + * function to wait for the data shift out. + * If this value is too small, then the last few bytes might be lost when writing + * data using interrupt method or DMA method. + */ +#define FLEXIO_MCULCD_WAIT_COMPLETE_TIME 512 +#endif + +#ifndef FLEXIO_MCULCD_DATA_BUS_WIDTH +/*! + * @brief The data bus width, must be 8 or 16. + */ +#define FLEXIO_MCULCD_DATA_BUS_WIDTH 16UL +#endif + +#if (16UL != FLEXIO_MCULCD_DATA_BUS_WIDTH) && (8UL != FLEXIO_MCULCD_DATA_BUS_WIDTH) +#error Only support data bus 8-bit or 16-bit +#endif + +/*! @brief FlexIO LCD transfer status */ +enum +{ + kStatus_FLEXIO_MCULCD_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_MCULCD, 0), /*!< FlexIO LCD is idle. */ + kStatus_FLEXIO_MCULCD_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_MCULCD, 1), /*!< FlexIO LCD is busy */ + kStatus_FLEXIO_MCULCD_Error = MAKE_STATUS(kStatusGroup_FLEXIO_MCULCD, 2), /*!< FlexIO LCD error occurred */ +}; + +/*! @brief Define FlexIO MCULCD pixel format. */ +typedef enum _flexio_mculcd_pixel_format +{ + kFLEXIO_MCULCD_RGB565 = 0, /*!< RGB565, 16-bit. */ + kFLEXIO_MCULCD_BGR565, /*!< BGR565, 16-bit. */ + kFLEXIO_MCULCD_RGB888, /*!< RGB888, 24-bit. */ + kFLEXIO_MCULCD_BGR888, /*!< BGR888, 24-bit. */ +} flexio_mculcd_pixel_format_t; + +/*! @brief Define FlexIO MCULCD bus type. */ +typedef enum _flexio_mculcd_bus +{ + kFLEXIO_MCULCD_8080, /*!< Using Intel 8080 bus. */ + kFLEXIO_MCULCD_6800, /*!< Using Motorola 6800 bus. */ +} flexio_mculcd_bus_t; + +/*! @brief Define FlexIO MCULCD interrupt mask. */ +enum _flexio_mculcd_interrupt_enable +{ + kFLEXIO_MCULCD_TxEmptyInterruptEnable = (1U << 0U), /*!< Transmit buffer empty interrupt enable. */ + kFLEXIO_MCULCD_RxFullInterruptEnable = (1U << 1U), /*!< Receive buffer full interrupt enable. */ +}; + +/*! @brief Define FlexIO MCULCD status mask. */ +enum _flexio_mculcd_status_flags +{ + kFLEXIO_MCULCD_TxEmptyFlag = (1U << 0U), /*!< Transmit buffer empty flag. */ + kFLEXIO_MCULCD_RxFullFlag = (1U << 1U), /*!< Receive buffer full flag. */ +}; + +/*! @brief Define FlexIO MCULCD DMA mask. */ +enum _flexio_mculcd_dma_enable +{ + kFLEXIO_MCULCD_TxDmaEnable = 0x1U, /*!< Tx DMA request source */ + kFLEXIO_MCULCD_RxDmaEnable = 0x2U, /*!< Rx DMA request source */ +}; + +/*! @brief Function to set or clear the CS and RS pin. */ +typedef void (*flexio_mculcd_pin_func_t)(bool set); + +/*! @brief Define FlexIO MCULCD access structure typedef. */ +typedef struct _flexio_mculcd_type +{ + FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ + flexio_mculcd_bus_t busType; /*!< The bus type, 8080 or 6800. */ + uint8_t dataPinStartIndex; /*!< Start index of the data pin, the FlexIO pin dataPinStartIndex + to (dataPinStartIndex + FLEXIO_MCULCD_DATA_BUS_WIDTH -1) + will be used for data transfer. Only support data bus width 8 and 16. */ + uint8_t ENWRPinIndex; /*!< Pin select for WR(8080 mode), EN(6800 mode). */ + uint8_t RDPinIndex; /*!< Pin select for RD(8080 mode), not used in 6800 mode. */ + uint8_t txShifterStartIndex; /*!< Start index of shifters used for data write, it must be 0 or 4. */ + uint8_t txShifterEndIndex; /*!< End index of shifters used for data write. */ + uint8_t rxShifterStartIndex; /*!< Start index of shifters used for data read. */ + uint8_t rxShifterEndIndex; /*!< End index of shifters used for data read, it must be 3 or 7. */ + uint8_t timerIndex; /*!< Timer index used in FlexIO MCULCD. */ + flexio_mculcd_pin_func_t setCSPin; /*!< Function to set or clear the CS pin. */ + flexio_mculcd_pin_func_t setRSPin; /*!< Function to set or clear the RS pin. */ + flexio_mculcd_pin_func_t setRDWRPin; /*!< Function to set or clear the RD/WR pin, only used in 6800 mode. */ +} FLEXIO_MCULCD_Type; + +/*! @brief Define FlexIO MCULCD configuration structure. */ +typedef struct _flexio_mculcd_config +{ + bool enable; /*!< Enable/disable FlexIO MCULCD after configuration. */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, + fast access requires the FlexIO clock to be at least + twice the frequency of the bus clock. */ + uint32_t baudRate_Bps; /*!< Baud rate in bit-per-second for all data lines combined. */ +} flexio_mculcd_config_t; + +/*! @brief Transfer mode.*/ +typedef enum _flexio_mculcd_transfer_mode +{ + kFLEXIO_MCULCD_ReadArray, /*!< Read data into an array. */ + kFLEXIO_MCULCD_WriteArray, /*!< Write data from an array. */ + kFLEXIO_MCULCD_WriteSameValue, /*!< Write the same value many times. */ +} flexio_mculcd_transfer_mode_t; + +/*! @brief Define FlexIO MCULCD transfer structure. */ +typedef struct _flexio_mculcd_transfer +{ + uint32_t command; /*!< Command to send. */ + uint32_t dataAddrOrSameValue; /*!< When sending the same value for many times, + this is the value to send. When writing or reading array, + this is the address of the data array. */ + size_t dataSize; /*!< How many bytes to transfer. */ + flexio_mculcd_transfer_mode_t mode; /*!< Transfer mode. */ + bool dataOnly; /*!< Send data only when tx without the command. */ +} flexio_mculcd_transfer_t; + +/*! @brief typedef for flexio_mculcd_handle_t in advance. */ +typedef struct _flexio_mculcd_handle flexio_mculcd_handle_t; + +/*! @brief FlexIO MCULCD callback for finished transfer. + * + * When transfer finished, the callback function is called and returns the + * @p status as kStatus_FLEXIO_MCULCD_Idle. + */ +typedef void (*flexio_mculcd_transfer_callback_t)(FLEXIO_MCULCD_Type *base, + flexio_mculcd_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Define FlexIO MCULCD handle structure. */ +struct _flexio_mculcd_handle +{ + uint32_t dataAddrOrSameValue; /*!< When sending the same value for many times, + this is the value to send. When writing or reading array, + this is the address of the data array. */ + size_t dataCount; /*!< Total count to be transferred. */ + volatile size_t remainingCount; /*!< Remaining count to transfer. */ + volatile uint32_t state; /*!< FlexIO MCULCD internal state. */ + flexio_mculcd_transfer_callback_t completionCallback; /*!< FlexIO MCULCD transfer completed callback. */ + void *userData; /*!< Callback parameter. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name FlexIO MCULCD Configuration + * @{ + */ + +/*! + * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the + * FlexIO MCULCD hardware, and configures the FlexIO MCULCD with FlexIO MCULCD + * configuration. + * The configuration structure can be filled by the user, or be set with default + * values + * by the @ref FLEXIO_MCULCD_GetDefaultConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param config Pointer to the flexio_mculcd_config_t structure. + * @param srcClock_Hz FlexIO source clock in Hz. + * @retval kStatus_Success Initialization success. + * @retval kStatus_InvalidArgument Initialization failed because of invalid + * argument. + */ +status_t FLEXIO_MCULCD_Init(FLEXIO_MCULCD_Type *base, flexio_mculcd_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Resets the FLEXIO_MCULCD timer and shifter configuration. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + */ +void FLEXIO_MCULCD_Deinit(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Gets the default configuration to configure the FlexIO MCULCD. + * + * The default configuration value is: + * @code + * config->enable = true; + * config->enableInDoze = false; + * config->enableInDebug = true; + * config->enableFastAccess = true; + * config->baudRate_Bps = 96000000U; + * @endcode + * @param config Pointer to the flexio_mculcd_config_t structure. + */ +void FLEXIO_MCULCD_GetDefaultConfig(flexio_mculcd_config_t *config); + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets FlexIO MCULCD status flags. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @return status flag; OR'ed value or the @ref _flexio_mculcd_status_flags. + * + * @note Don't use this function with DMA APIs. + */ +uint32_t FLEXIO_MCULCD_GetStatusFlags(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Clears FlexIO MCULCD status flags. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param mask Status to clear, it is the OR'ed value of @ref + * _flexio_mculcd_status_flags. + * + * @note Don't use this function with DMA APIs. + */ +void FLEXIO_MCULCD_ClearStatusFlags(FLEXIO_MCULCD_Type *base, uint32_t mask); + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the FlexIO MCULCD interrupt. + * + * This function enables the FlexIO MCULCD interrupt. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param mask Interrupts to enable, it is the OR'ed value of @ref + * _flexio_mculcd_interrupt_enable. + */ +void FLEXIO_MCULCD_EnableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask); + +/*! + * @brief Disables the FlexIO MCULCD interrupt. + * + * This function disables the FlexIO MCULCD interrupt. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param mask Interrupts to disable, it is the OR'ed value of @ref + * _flexio_mculcd_interrupt_enable. + */ +void FLEXIO_MCULCD_DisableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask); + +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables/disables the FlexIO MCULCD transmit DMA. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void FLEXIO_MCULCD_EnableTxDMA(FLEXIO_MCULCD_Type *base, bool enable) +{ + FLEXIO_EnableShifterStatusDMA(base->flexioBase, (1UL << base->txShifterStartIndex), enable); +} + +/*! + * @brief Enables/disables the FlexIO MCULCD receive DMA. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param enable True means enable DMA, false means disable DMA. + */ +static inline void FLEXIO_MCULCD_EnableRxDMA(FLEXIO_MCULCD_Type *base, bool enable) +{ + FLEXIO_EnableShifterStatusDMA(base->flexioBase, (1UL << base->rxShifterEndIndex), enable); +} + +/*! + * @brief Gets the FlexIO MCULCD transmit data register address. + * + * This function returns the MCULCD data register address, which is mainly used + * by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @return FlexIO MCULCD transmit data register address. + */ +static inline uint32_t FLEXIO_MCULCD_GetTxDataRegisterAddress(FLEXIO_MCULCD_Type *base) +{ + return (uint32_t) & (base->flexioBase->SHIFTBUF[base->txShifterStartIndex]); +} + +/*! + * @brief Gets the FlexIO MCULCD receive data register address. + * + * This function returns the MCULCD data register address, which is mainly used + * by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @return FlexIO MCULCD receive data register address. + */ +static inline uint32_t FLEXIO_MCULCD_GetRxDataRegisterAddress(FLEXIO_MCULCD_Type *base) +{ + return (uint32_t) & (base->flexioBase->SHIFTBUF[base->rxShifterStartIndex]); +} + +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Set desired baud rate. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param baudRate_Bps Desired baud rate in bit-per-second for all data lines combined. + * @param srcClock_Hz FLEXIO clock frequency in Hz. + * @retval kStatus_Success Set successfully. + * @retval kStatus_InvalidArgument Could not set the baud rate. + */ +status_t FLEXIO_MCULCD_SetBaudRate(FLEXIO_MCULCD_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Configures the FLEXIO MCULCD to multiple beats write mode. + * + * At the begining multiple beats write operation, the FLEXIO MCULCD is configured to + * multiple beats write mode using this function. After write operation, the configuration + * is cleared by @ref FLEXIO_MCULCD_ClearSingleBeatWriteConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * + * @note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_SetSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Clear the FLEXIO MCULCD multiple beats write mode configuration. + * + * Clear the write configuration set by @ref FLEXIO_MCULCD_SetSingleBeatWriteConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * + * @note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_ClearSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Configures the FLEXIO MCULCD to multiple beats read mode. + * + * At the begining or multiple beats read operation, the FLEXIO MCULCD is configured + * to multiple beats read mode using this function. After read operation, the configuration + * is cleared by @ref FLEXIO_MCULCD_ClearSingleBeatReadConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * + * @note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_SetSingleBeatReadConfig(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Clear the FLEXIO MCULCD multiple beats read mode configuration. + * + * Clear the read configuration set by @ref FLEXIO_MCULCD_SetSingleBeatReadConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * + * @note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_ClearSingleBeatReadConfig(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Configures the FLEXIO MCULCD to multiple beats write mode. + * + * At the begining multiple beats write operation, the FLEXIO MCULCD is configured to + * multiple beats write mode using this function. After write operation, the configuration + * is cleared by FLEXIO_MCULCD_ClearMultBeatsWriteConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * + * @note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_SetMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Clear the FLEXIO MCULCD multiple beats write mode configuration. + * + * Clear the write configuration set by FLEXIO_MCULCD_SetMultBeatsWriteConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * + * @note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_ClearMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Configures the FLEXIO MCULCD to multiple beats read mode. + * + * At the begining or multiple beats read operation, the FLEXIO MCULCD is configured + * to multiple beats read mode using this function. After read operation, the configuration + * is cleared by FLEXIO_MCULCD_ClearMultBeatsReadConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * + * @note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_SetMultiBeatsReadConfig(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Clear the FLEXIO MCULCD multiple beats read mode configuration. + * + * Clear the read configuration set by FLEXIO_MCULCD_SetMultBeatsReadConfig. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * + * @note This is an internal used function, upper layer should not use. + */ +void FLEXIO_MCULCD_ClearMultiBeatsReadConfig(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Enables/disables the FlexIO MCULCD module operation. + * + * @param base Pointer to the FLEXIO_MCULCD_Type. + * @param enable True to enable, false does not have any effect. + */ +static inline void FLEXIO_MCULCD_Enable(FLEXIO_MCULCD_Type *base, bool enable) +{ + if (enable) + { + FLEXIO_Enable(base->flexioBase, enable); + } +} + +/*! + * @brief Read data from the FLEXIO MCULCD RX shifter buffer. + * + * Read data from the RX shift buffer directly, it does no check whether the + * buffer is empty or not. + * + * If the data bus width is 8-bit: + * @code + * uint8_t value; + * value = (uint8_t)FLEXIO_MCULCD_ReadData(base); + * @endcode + * + * If the data bus width is 16-bit: + * @code + * uint16_t value; + * value = (uint16_t)FLEXIO_MCULCD_ReadData(base); + * @endcode + * + * @note This function returns the RX shifter buffer value (32-bit) directly. + * The return value should be converted according to data bus width. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @return The data read out. + * + * @note Don't use this function with DMA APIs. + */ +uint32_t FLEXIO_MCULCD_ReadData(FLEXIO_MCULCD_Type *base); + +/*! + * @brief Write data into the FLEXIO MCULCD TX shifter buffer. + * + * Write data into the TX shift buffer directly, it does no check whether the + * buffer is full or not. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param data The data to write. + * + * @note Don't use this function with DMA APIs. + */ +static inline void FLEXIO_MCULCD_WriteData(FLEXIO_MCULCD_Type *base, uint32_t data) +{ + base->flexioBase->SHIFTBUF[base->txShifterStartIndex] = data; +} + +/*! + * @brief Assert the nCS to start transfer. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + */ +static inline void FLEXIO_MCULCD_StartTransfer(FLEXIO_MCULCD_Type *base) +{ + base->setCSPin(false); +} + +/*! + * @brief De-assert the nCS to stop transfer. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + */ +static inline void FLEXIO_MCULCD_StopTransfer(FLEXIO_MCULCD_Type *base) +{ + base->setCSPin(true); +} + +/*! + * @brief Wait for transmit data send out finished. + * + * Currently there is no effective method to wait for the data send out + * from the shiter, so here use a while loop to wait. + * + * @note This is an internal used function. + */ +void FLEXIO_MCULCD_WaitTransmitComplete(void); + +/*! + * @brief Send command in blocking way. + * + * This function sends the command and returns when the command has been sent + * out. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param command The command to send. + */ +void FLEXIO_MCULCD_WriteCommandBlocking(FLEXIO_MCULCD_Type *base, uint32_t command); + +/*! + * @brief Send data array in blocking way. + * + * This function sends the data array and returns when the data sent out. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param data The data array to send. + * @param size How many bytes to write. + */ +void FLEXIO_MCULCD_WriteDataArrayBlocking(FLEXIO_MCULCD_Type *base, const void *data, size_t size); + +/*! + * @brief Read data into array in blocking way. + * + * This function reads the data into array and returns when the data read + * finished. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param data The array to save the data. + * @param size How many bytes to read. + */ +void FLEXIO_MCULCD_ReadDataArrayBlocking(FLEXIO_MCULCD_Type *base, void *data, size_t size); + +/*! + * @brief Send the same value many times in blocking way. + * + * This function sends the same value many times. It could be used to clear the + * LCD screen. If the data bus width is 8, this function will send LSB 8 bits of + * @p sameValue for @p size times. If the data bus is 16, this function will send + * LSB 16 bits of @p sameValue for @p size / 2 times. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param sameValue The same value to send. + * @param size How many bytes to send. + */ +void FLEXIO_MCULCD_WriteSameValueBlocking(FLEXIO_MCULCD_Type *base, uint32_t sameValue, size_t size); + +/*! + * @brief Performs a polling transfer. + * + * @note The API does not return until the transfer finished. + * + * @param base pointer to FLEXIO_MCULCD_Type structure. + * @param xfer pointer to flexio_mculcd_transfer_t structure. + */ +void FLEXIO_MCULCD_TransferBlocking(FLEXIO_MCULCD_Type *base, flexio_mculcd_transfer_t *xfer); +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the FlexIO MCULCD handle, which is used in transactional + * functions. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_MCULCD_TransferCreateHandle(FLEXIO_MCULCD_Type *base, + flexio_mculcd_handle_t *handle, + flexio_mculcd_transfer_callback_t callback, + void *userData); + +/*! + * @brief Transfer data using IRQ. + * + * This function sends data using IRQ. This is a non-blocking function, which + * returns right away. When all data is sent out/received, the callback + * function is called. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + * @param xfer FlexIO MCULCD transfer structure. See #flexio_mculcd_transfer_t. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_MCULCD_Busy MCULCD is busy with another transfer. + */ +status_t FLEXIO_MCULCD_TransferNonBlocking(FLEXIO_MCULCD_Type *base, + flexio_mculcd_handle_t *handle, + flexio_mculcd_transfer_t *xfer); + +/*! + * @brief Aborts the data transfer, which used IRQ. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + */ +void FLEXIO_MCULCD_TransferAbort(FLEXIO_MCULCD_Type *base, flexio_mculcd_handle_t *handle); + +/*! + * @brief Gets the data transfer status which used IRQ. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + * @param count How many bytes transferred so far by the non-blocking transaction. + * @retval kStatus_Success Get the transferred count Successfully. + * @retval kStatus_NoTransferInProgress No transfer in process. + */ +status_t FLEXIO_MCULCD_TransferGetCount(FLEXIO_MCULCD_Type *base, flexio_mculcd_handle_t *handle, size_t *count); + +/*! + * @brief FlexIO MCULCD IRQ handler function. + * + * @param base Pointer to the FLEXIO_MCULCD_Type structure. + * @param handle Pointer to the flexio_mculcd_handle_t structure to store the + * transfer state. + */ +void FLEXIO_MCULCD_TransferHandleIRQ(void *base, void *handle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*! @} */ + +#endif /*FSL_FLEXIO_MCULCD_H_*/ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_mculcd_edma.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_mculcd_edma.c new file mode 100644 index 00000000000..0c52c4e8c08 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_mculcd_edma.c @@ -0,0 +1,568 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019,2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_mculcd_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_mculcd_edma" +#endif + +#define EDMA_MAX_MAJOR_COUNT (DMA_CITER_ELINKNO_CITER_MASK >> DMA_CITER_ELINKNO_CITER_SHIFT) + +enum +{ + kFLEXIO_MCULCD_StateIdle, /*!< No transfer in progress. */ + kFLEXIO_MCULCD_StateReadArray, /*!< Reading array in progress. */ + kFLEXIO_MCULCD_StateWriteArray, /*!< Writing array in progress. */ + kFLEXIO_MCULCD_StateWriteSameValue, /*!< Writing the same value in progress. + */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief EDMA callback function for FLEXIO MCULCD TX. + * + * For details, see @ref edma_callback. + */ +static void FLEXIO_MCULCD_TxEDMACallback(edma_handle_t *DmaHandle, void *param, bool transferDone, uint32_t tcds); + +/*! + * @brief EDMA callback function for FLEXIO MCULCD RX. + * + * For details, see @ref edma_callback. + */ +static void FLEXIO_MCULCD_RxEDMACallback(edma_handle_t *DmaHandle, void *param, bool transferDone, uint32_t tcds); + +/*! + * @brief Set EDMA config for FLEXIO MCULCD transfer. + * + * @param base pointer to FLEXIO_MCULCD_Type structure. + * @param handle pointer to flexio_mculcd_edma_handle_t structure to store the + * transfer state. + */ +static void FLEXIO_MCULCD_EDMAConfig(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle); + +/*! + * @brief Convert the FlexIO shifter number to eDMA modulo. + * + * @param shifterNum The FlexIO shifter number. + * @param modulo The modulo number. + * @retval Get the modulo successfully. + * @retval Could not get the modulo for the shifter number. + */ +static bool FLEXIO_MCULCD_GetEDMAModulo(uint8_t shifterNum, edma_modulo_t *modulo); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void FLEXIO_MCULCD_TxEDMACallback(edma_handle_t *DmaHandle, void *param, bool transferDone, uint32_t tcds) +{ + tcds = tcds; + flexio_mculcd_edma_handle_t *flexioLcdMcuHandle = (flexio_mculcd_edma_handle_t *)param; + FLEXIO_MCULCD_Type *flexioLcdMcuBase = flexioLcdMcuHandle->base; + + if (transferDone) + { + if (flexioLcdMcuHandle->remainingCount >= flexioLcdMcuHandle->minorLoopBytes) + { + FLEXIO_MCULCD_EDMAConfig(flexioLcdMcuBase, flexioLcdMcuHandle); + EDMA_StartTransfer(flexioLcdMcuHandle->txDmaHandle); + } + else + { + FLEXIO_MCULCD_EnableTxDMA(flexioLcdMcuBase, false); + + /* Now the data are in shifter, wait for the data send out from the shifter. */ + FLEXIO_MCULCD_WaitTransmitComplete(); + + /* Disable the TX shifter and the timer. */ + FLEXIO_MCULCD_ClearMultiBeatsWriteConfig(flexioLcdMcuBase); + + /* Send the remaining data. */ + if (0U != flexioLcdMcuHandle->remainingCount) + { + if ((uint32_t)kFLEXIO_MCULCD_StateWriteSameValue == flexioLcdMcuHandle->state) + { + FLEXIO_MCULCD_WriteSameValueBlocking(flexioLcdMcuBase, flexioLcdMcuHandle->dataAddrOrSameValue, + flexioLcdMcuHandle->remainingCount); + } + else + { + FLEXIO_MCULCD_WriteDataArrayBlocking(flexioLcdMcuBase, + (uint8_t *)flexioLcdMcuHandle->dataAddrOrSameValue, + flexioLcdMcuHandle->remainingCount); + } + } + + /* De-assert nCS. */ + FLEXIO_MCULCD_StopTransfer(flexioLcdMcuBase); + + /* Change the state. */ + flexioLcdMcuHandle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + flexioLcdMcuHandle->dataCount = 0; + flexioLcdMcuHandle->remainingCount = 0; + + /* Callback to inform upper layer. */ + if (NULL != flexioLcdMcuHandle->completionCallback) + { + flexioLcdMcuHandle->completionCallback(flexioLcdMcuBase, flexioLcdMcuHandle, kStatus_FLEXIO_MCULCD_Idle, + flexioLcdMcuHandle->userData); + } + } + } +} + +static void FLEXIO_MCULCD_RxEDMACallback(edma_handle_t *DmaHandle, void *param, bool transferDone, uint32_t tcds) +{ + tcds = tcds; + uint32_t i; + uint32_t rxBufAddr; + flexio_mculcd_edma_handle_t *flexioLcdMcuHandle = (flexio_mculcd_edma_handle_t *)param; + FLEXIO_MCULCD_Type *flexioLcdMcuBase = flexioLcdMcuHandle->base; + FLEXIO_Type *flexioBase = flexioLcdMcuBase->flexioBase; + + if (transferDone) + { + if (flexioLcdMcuHandle->remainingCount >= (2U * flexioLcdMcuHandle->minorLoopBytes)) + { + FLEXIO_MCULCD_EDMAConfig(flexioLcdMcuBase, flexioLcdMcuHandle); + EDMA_StartTransfer(flexioLcdMcuHandle->rxDmaHandle); + } + else + { + FLEXIO_MCULCD_EnableRxDMA(flexioLcdMcuBase, false); + + /* Wait the data saved to the shifter buffer. */ + while (0U == ((1UL << flexioLcdMcuBase->rxShifterEndIndex) & FLEXIO_GetShifterStatusFlags(flexioBase))) + { + } + + /* Disable the RX shifter and the timer. */ + FLEXIO_MCULCD_ClearMultiBeatsReadConfig(flexioLcdMcuBase); + + rxBufAddr = FLEXIO_MCULCD_GetRxDataRegisterAddress(flexioLcdMcuBase); + +/* Read out the data. */ +#if (defined(__CORTEX_M) && (__CORTEX_M == 0)) + /* Cortex M0 and M0+ only support aligned access. */ + for (i = 0; i < flexioLcdMcuHandle->rxShifterNum * 4; i++) + { + ((uint8_t *)(flexioLcdMcuHandle->dataAddrOrSameValue))[i] = ((volatile uint8_t *)rxBufAddr)[i]; + } +#else + for (i = 0; i < flexioLcdMcuHandle->rxShifterNum; i++) + { + ((uint32_t *)(flexioLcdMcuHandle->dataAddrOrSameValue))[i] = ((volatile uint32_t *)rxBufAddr)[i]; + } +#endif + flexioLcdMcuHandle->remainingCount -= flexioLcdMcuHandle->minorLoopBytes; + + if (0U != flexioLcdMcuHandle->remainingCount) + { + FLEXIO_MCULCD_ReadDataArrayBlocking( + flexioLcdMcuBase, + (uint8_t *)(flexioLcdMcuHandle->dataAddrOrSameValue + flexioLcdMcuHandle->minorLoopBytes), + flexioLcdMcuHandle->remainingCount); + } + + /* De-assert nCS. */ + FLEXIO_MCULCD_StopTransfer(flexioLcdMcuBase); + + /* Change the state. */ + flexioLcdMcuHandle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + flexioLcdMcuHandle->dataCount = 0; + flexioLcdMcuHandle->remainingCount = 0; + + /* Callback to inform upper layer. */ + if (NULL != flexioLcdMcuHandle->completionCallback) + { + flexioLcdMcuHandle->completionCallback(flexioLcdMcuBase, flexioLcdMcuHandle, kStatus_FLEXIO_MCULCD_Idle, + flexioLcdMcuHandle->userData); + } + } + } +} + +static void FLEXIO_MCULCD_EDMAConfig(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle) +{ + edma_transfer_config_t xferConfig = {0}; + edma_transfer_size_t transferSize = kEDMA_TransferSize1Bytes; + int16_t offset; + uint32_t majorLoopCounts; + uint32_t transferCount; + +#if (8 == FLEXIO_MCULCD_DATA_BUS_WIDTH) + transferSize = kEDMA_TransferSize1Bytes; + offset = 1; +#else + transferSize = kEDMA_TransferSize2Bytes; + offset = 2; +#endif + + majorLoopCounts = handle->remainingCount / handle->minorLoopBytes; + + /* For reading, the last minor loop data is not tranfered by DMA. */ + if ((uint32_t)kFLEXIO_MCULCD_StateReadArray == handle->state) + { + majorLoopCounts--; + } + + if (majorLoopCounts > EDMA_MAX_MAJOR_COUNT) + { + majorLoopCounts = EDMA_MAX_MAJOR_COUNT; + } + + transferCount = majorLoopCounts * handle->minorLoopBytes; + + if ((uint32_t)kFLEXIO_MCULCD_StateReadArray == handle->state) + { + xferConfig.srcAddr = FLEXIO_MCULCD_GetRxDataRegisterAddress(base); + xferConfig.destAddr = handle->dataAddrOrSameValue; + xferConfig.srcTransferSize = kEDMA_TransferSize4Bytes; + xferConfig.destTransferSize = transferSize; + xferConfig.srcOffset = 4; + xferConfig.destOffset = offset; + xferConfig.minorLoopBytes = handle->minorLoopBytes; + xferConfig.majorLoopCounts = majorLoopCounts; + handle->remainingCount -= transferCount; + handle->dataAddrOrSameValue += transferCount; + (void)EDMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); + EDMA_SetModulo(handle->rxDmaHandle->base, handle->rxDmaHandle->channel, handle->rxEdmaModulo, + kEDMA_ModuloDisable); + } + else + { + if ((uint32_t)kFLEXIO_MCULCD_StateWriteArray == handle->state) + { + xferConfig.srcAddr = handle->dataAddrOrSameValue; + xferConfig.srcOffset = offset; + handle->dataAddrOrSameValue += transferCount; + } + else + { + xferConfig.srcAddr = (uint32_t)(&(handle->dataAddrOrSameValue)); + xferConfig.srcOffset = 0; + } + xferConfig.destAddr = FLEXIO_MCULCD_GetTxDataRegisterAddress(base); + xferConfig.srcTransferSize = transferSize; + xferConfig.destTransferSize = kEDMA_TransferSize4Bytes; + xferConfig.destOffset = 4; + xferConfig.minorLoopBytes = handle->minorLoopBytes; + xferConfig.majorLoopCounts = majorLoopCounts; + handle->remainingCount -= transferCount; + (void)EDMA_SubmitTransfer(handle->txDmaHandle, &xferConfig); + EDMA_SetModulo(handle->txDmaHandle->base, handle->txDmaHandle->channel, kEDMA_ModuloDisable, + handle->txEdmaModulo); + } +} + +static bool FLEXIO_MCULCD_GetEDMAModulo(uint8_t shifterNum, edma_modulo_t *modulo) +{ + bool ret = true; + + switch (shifterNum) + { + case 1U: + *modulo = kEDMA_Modulo4bytes; + break; + case 2U: + *modulo = kEDMA_Modulo8bytes; + break; + case 4U: + *modulo = kEDMA_Modulo16bytes; + break; + case 8U: + *modulo = kEDMA_Modulo32bytes; + break; + default: + ret = false; + break; + } + + return ret; +} + +/*! + * brief Initializes the FLEXO MCULCD master eDMA handle. + * + * This function initializes the FLEXO MCULCD master eDMA handle which can be + * used for other FLEXO MCULCD transactional APIs. For a specified FLEXO MCULCD + * instance, call this API once to get the initialized handle. + * + * param base Pointer to FLEXIO_MCULCD_Type structure. + * param handle Pointer to flexio_mculcd_edma_handle_t structure to store the + * transfer state. + * param callback MCULCD transfer complete callback, NULL means no callback. + * param userData callback function parameter. + * param txDmaHandle User requested eDMA handle for FlexIO MCULCD eDMA TX, + * the DMA request source of this handle should be the first of TX shifters. + * param rxDmaHandle User requested eDMA handle for FlexIO MCULCD eDMA RX, + * the DMA request source of this handle should be the last of RX shifters. + * retval kStatus_Success Successfully create the handle. + */ +status_t FLEXIO_MCULCD_TransferCreateHandleEDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_edma_handle_t *handle, + flexio_mculcd_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txDmaHandle, + edma_handle_t *rxDmaHandle) +{ + assert(NULL != handle); + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Initialize the state. */ + handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + + /* Register callback and userData. */ + handle->completionCallback = callback; + handle->userData = userData; + + handle->base = base; + handle->txShifterNum = base->txShifterEndIndex - base->txShifterStartIndex + 1U; + handle->rxShifterNum = base->rxShifterEndIndex - base->rxShifterStartIndex + 1U; + + if (NULL != rxDmaHandle) + { + if (!FLEXIO_MCULCD_GetEDMAModulo(handle->rxShifterNum, &handle->rxEdmaModulo)) + { + return kStatus_InvalidArgument; + } + + handle->rxDmaHandle = rxDmaHandle; + EDMA_SetCallback(rxDmaHandle, FLEXIO_MCULCD_RxEDMACallback, handle); + } + + if (NULL != txDmaHandle) + { + if (!FLEXIO_MCULCD_GetEDMAModulo(handle->txShifterNum, &handle->txEdmaModulo)) + { + return kStatus_InvalidArgument; + } + + handle->txDmaHandle = txDmaHandle; + EDMA_SetCallback(txDmaHandle, FLEXIO_MCULCD_TxEDMACallback, handle); + } + + return kStatus_Success; +} + +/*! + * brief Performs a non-blocking FlexIO MCULCD transfer using eDMA. + * + * This function returns immediately after transfer initiates. To check whether + * the transfer is completed, user could: + * 1. Use the transfer completed callback; + * 2. Polling function ref FLEXIO_MCULCD_GetTransferCountEDMA + * + * param base pointer to FLEXIO_MCULCD_Type structure. + * param handle pointer to flexio_mculcd_edma_handle_t structure to store the + * transfer state. + * param xfer Pointer to FlexIO MCULCD transfer structure. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another + * transfer. + */ +status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_edma_handle_t *handle, + flexio_mculcd_transfer_t *xfer) +{ + assert(NULL != handle); + assert(NULL != xfer); + + /* + * The data transfer mechanism: + * + * Read: + * Assume the data length is Lr = (n1 * minorLoopBytes + n2), where + * n2 < minorLoopBytes. + * If (n1 <= 1), then all data are sent using blocking method. + * If (n1 > 1), then the beginning ((n1-1) * minorLoopBytes) are read + * using DMA, the left (minorLoopBytes + n2) are read using blocking method. + * + * Write: + * Assume the data length is Lw = (n1 * minorLoopBytes + n2), where + * n2 < minorLoopBytes. + * If (n1 = 0), then all data are sent using blocking method. + * If (n1 >= 1), then the beginning (n1 * minorLoopBytes) are sent + * using DMA, the left n2 are sent using blocking method. + */ + + /* Check if the device is busy. */ + if ((uint32_t)kFLEXIO_MCULCD_StateIdle != handle->state) + { + return kStatus_FLEXIO_MCULCD_Busy; + } + + /* Set the state in handle. */ + if (kFLEXIO_MCULCD_ReadArray == xfer->mode) + { + handle->state = (uint32_t)kFLEXIO_MCULCD_StateReadArray; + handle->minorLoopBytes = handle->rxShifterNum * 4UL; + } + else + { + handle->minorLoopBytes = handle->txShifterNum * 4UL; + + if (kFLEXIO_MCULCD_WriteArray == xfer->mode) + { + handle->state = (uint32_t)kFLEXIO_MCULCD_StateWriteArray; + } + else + { + handle->state = (uint32_t)kFLEXIO_MCULCD_StateWriteSameValue; + } + } + + /* + * For TX, if data is less than one minor loop, then use polling method. + * For RX, if data is less than two minor loop, then use polling method. + */ + if ((xfer->dataSize < handle->minorLoopBytes) || + ((kFLEXIO_MCULCD_ReadArray == xfer->mode) && (xfer->dataSize < 2U * (handle->minorLoopBytes)))) + { + FLEXIO_MCULCD_TransferBlocking(base, xfer); + + handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + + /* Callback to inform upper layer. */ + if (NULL != handle->completionCallback) + { + handle->completionCallback(base, handle, kStatus_FLEXIO_MCULCD_Idle, handle->userData); + } + } + else + { + handle->dataCount = xfer->dataSize; + handle->remainingCount = xfer->dataSize; + handle->dataAddrOrSameValue = xfer->dataAddrOrSameValue; + + /* Setup DMA to transfer data. */ + /* Assert the nCS. */ + FLEXIO_MCULCD_StartTransfer(base); + + if (!xfer->dataOnly) + { + /* Send the command. */ + FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command); + } + + /* Setup the DMA configuration. */ + FLEXIO_MCULCD_EDMAConfig(base, handle); + + /* Start the transfer. */ + if (kFLEXIO_MCULCD_ReadArray == xfer->mode) + { + /* For 6800, assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(true); + } + FLEXIO_MCULCD_SetMultiBeatsReadConfig(base); + FLEXIO_MCULCD_EnableRxDMA(base, true); + EDMA_StartTransfer(handle->rxDmaHandle); + } + else + { + /* For 6800, de-assert the RDWR pin. */ + if (kFLEXIO_MCULCD_6800 == base->busType) + { + base->setRDWRPin(false); + } + FLEXIO_MCULCD_SetMultiBeatsWriteConfig(base); + FLEXIO_MCULCD_EnableTxDMA(base, true); + EDMA_StartTransfer(handle->txDmaHandle); + } + } + + return kStatus_Success; +} + +/*! + * brief Aborts a FlexIO MCULCD transfer using eDMA. + * + * param base pointer to FLEXIO_MCULCD_Type structure. + * param handle FlexIO MCULCD eDMA handle pointer. + */ +void FLEXIO_MCULCD_TransferAbortEDMA(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle) +{ + assert(NULL != handle); + + /* Disable dma. */ + if (NULL != handle->txDmaHandle) + { + EDMA_AbortTransfer(handle->txDmaHandle); + } + if (NULL != handle->rxDmaHandle) + { + EDMA_AbortTransfer(handle->rxDmaHandle); + } + + /* Disable DMA enable bit. */ + FLEXIO_MCULCD_EnableTxDMA(handle->base, false); + FLEXIO_MCULCD_EnableRxDMA(handle->base, false); + + /* Set the handle state. */ + handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle; + handle->dataCount = 0; +} + +/*! + * brief Gets the remaining bytes for FlexIO MCULCD eDMA transfer. + * + * param base pointer to FLEXIO_MCULCD_Type structure. + * param handle FlexIO MCULCD eDMA handle pointer. + * param count Number of count transferred so far by the eDMA transaction. + * retval kStatus_Success Get the transferred count Successfully. + * retval kStatus_NoTransferInProgress No transfer in process. + */ +status_t FLEXIO_MCULCD_TransferGetCountEDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_edma_handle_t *handle, + size_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + uint32_t state = handle->state; + + if ((uint32_t)kFLEXIO_MCULCD_StateIdle == state) + { + return kStatus_NoTransferInProgress; + } + else + { + *count = handle->dataCount - handle->remainingCount; + + if ((uint32_t)kFLEXIO_MCULCD_StateReadArray == state) + { + *count -= handle->minorLoopBytes * + EDMA_GetRemainingMajorLoopCount(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); + } + else + { + *count -= handle->minorLoopBytes * + EDMA_GetRemainingMajorLoopCount(handle->txDmaHandle->base, handle->txDmaHandle->channel); + } + } + + return kStatus_Success; +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_mculcd_edma.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_mculcd_edma.h new file mode 100644 index 00000000000..98da16eef92 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_mculcd_edma.h @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020,2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_FLEXIO_MCULCD_EDMA_H_ +#define FSL_FLEXIO_MCULCD_EDMA_H_ + +#include "fsl_edma.h" +#include "fsl_flexio_mculcd.h" + +/*! + * @addtogroup flexio_edma_mculcd + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @{ */ +/*! @brief FlexIO MCULCD EDMA driver version. */ +#define FSL_FLEXIO_MCULCD_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) +/*! @} */ + +/*! @brief typedef for flexio_mculcd_edma_handle_t in advance. */ +typedef struct _flexio_mculcd_edma_handle flexio_mculcd_edma_handle_t; + +/*! @brief FlexIO MCULCD master callback for transfer complete. + * + * When transfer finished, the callback function is called and returns the + * @p status as kStatus_FLEXIO_MCULCD_Idle. + */ +typedef void (*flexio_mculcd_edma_transfer_callback_t)(FLEXIO_MCULCD_Type *base, + flexio_mculcd_edma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief FlexIO MCULCD eDMA transfer handle, users should not touch the + * content of the handle.*/ +struct _flexio_mculcd_edma_handle +{ + FLEXIO_MCULCD_Type *base; /*!< Pointer to the FLEXIO_MCULCD_Type. */ + uint8_t txShifterNum; /*!< Number of shifters used for TX. */ + uint8_t rxShifterNum; /*!< Number of shifters used for RX. */ + uint32_t minorLoopBytes; /*!< eDMA transfer minor loop bytes. */ + edma_modulo_t txEdmaModulo; /*!< Modulo value for the FlexIO shifter buffer access. */ + edma_modulo_t rxEdmaModulo; /*!< Modulo value for the FlexIO shifter buffer access. */ + uint32_t dataAddrOrSameValue; /*!< When sending the same value for many times, + this is the value to send. When writing or + reading array, this is the address of the + data array. */ + size_t dataCount; /*!< Total count to be transferred. */ + volatile size_t remainingCount; /*!< Remaining count still not transfered. */ + volatile uint32_t state; /*!< FlexIO MCULCD driver internal state. */ + edma_handle_t *txDmaHandle; /*!< DMA handle for MCULCD TX */ + edma_handle_t *rxDmaHandle; /*!< DMA handle for MCULCD RX */ + flexio_mculcd_edma_transfer_callback_t completionCallback; /*!< Callback for MCULCD DMA transfer */ + void *userData; /*!< User Data for MCULCD DMA callback */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA Transactional + * @{ + */ + +/*! + * @brief Initializes the FLEXO MCULCD master eDMA handle. + * + * This function initializes the FLEXO MCULCD master eDMA handle which can be + * used for other FLEXO MCULCD transactional APIs. For a specified FLEXO MCULCD + * instance, call this API once to get the initialized handle. + * + * @param base Pointer to FLEXIO_MCULCD_Type structure. + * @param handle Pointer to flexio_mculcd_edma_handle_t structure to store the + * transfer state. + * @param callback MCULCD transfer complete callback, NULL means no callback. + * @param userData callback function parameter. + * @param txDmaHandle User requested eDMA handle for FlexIO MCULCD eDMA TX, + * the DMA request source of this handle should be the first of TX shifters. + * @param rxDmaHandle User requested eDMA handle for FlexIO MCULCD eDMA RX, + * the DMA request source of this handle should be the last of RX shifters. + * @retval kStatus_Success Successfully create the handle. + */ +status_t FLEXIO_MCULCD_TransferCreateHandleEDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_edma_handle_t *handle, + flexio_mculcd_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txDmaHandle, + edma_handle_t *rxDmaHandle); + +/*! + * @brief Performs a non-blocking FlexIO MCULCD transfer using eDMA. + * + * This function returns immediately after transfer initiates. To check whether + * the transfer is completed, user could: + * 1. Use the transfer completed callback; + * 2. Polling function FLEXIO_MCULCD_GetTransferCountEDMA + * + * @param base pointer to FLEXIO_MCULCD_Type structure. + * @param handle pointer to flexio_mculcd_edma_handle_t structure to store the + * transfer state. + * @param xfer Pointer to FlexIO MCULCD transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another + * transfer. + */ +status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_edma_handle_t *handle, + flexio_mculcd_transfer_t *xfer); + +/*! + * @brief Aborts a FlexIO MCULCD transfer using eDMA. + * + * @param base pointer to FLEXIO_MCULCD_Type structure. + * @param handle FlexIO MCULCD eDMA handle pointer. + */ +void FLEXIO_MCULCD_TransferAbortEDMA(FLEXIO_MCULCD_Type *base, flexio_mculcd_edma_handle_t *handle); + +/*! + * @brief Gets the remaining bytes for FlexIO MCULCD eDMA transfer. + * + * @param base pointer to FLEXIO_MCULCD_Type structure. + * @param handle FlexIO MCULCD eDMA handle pointer. + * @param count Number of count transferred so far by the eDMA transaction. + * @retval kStatus_Success Get the transferred count Successfully. + * @retval kStatus_NoTransferInProgress No transfer in process. + */ +status_t FLEXIO_MCULCD_TransferGetCountEDMA(FLEXIO_MCULCD_Type *base, + flexio_mculcd_edma_handle_t *handle, + size_t *count); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* FSL_FLEXIO_MCULCD_EDMA_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_spi.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_spi.c new file mode 100644 index 00000000000..96c9a7c0acc --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_spi.c @@ -0,0 +1,1565 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020, 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_spi.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_spi" +#endif + +/*! @brief FLEXIO SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */ +enum _flexio_spi_transfer_states +{ + kFLEXIO_SPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver's queue. */ + kFLEXIO_SPI_Busy, /*!< Transmiter/Receive's queue is not finished. */ +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Send a piece of data for SPI. + * + * This function computes the number of data to be written into D register or Tx FIFO, + * and write the data into it. At the same time, this function updates the values in + * master handle structure. + * + * @param base pointer to FLEXIO_SPI_Type structure + * @param handle Pointer to SPI master handle structure. + */ +static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle); + +/*! + * @brief Receive a piece of data for SPI master. + * + * This function computes the number of data to receive from D register or Rx FIFO, + * and write the data to destination address. At the same time, this function updates + * the values in master handle structure. + * + * @param base pointer to FLEXIO_SPI_Type structure + * @param handle Pointer to SPI master handle structure. + */ +static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Codes + ******************************************************************************/ + +static uint32_t FLEXIO_SPI_GetInstance(FLEXIO_SPI_Type *base) +{ + return FLEXIO_GetInstance(base->flexioBase); +} + +static void FLEXIO_SPI_TransferSendTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle) +{ + uint32_t tmpData = FLEXIO_SPI_DUMMYDATA; + + if (handle->txData != NULL) + { + /* Transmit data and update tx size/buff. */ + if (handle->bytePerFrame == 1U) + { + tmpData = (uint32_t) * (handle->txData); + handle->txData++; + } + else if (handle->bytePerFrame == 2U) + { + if (handle->direction == kFLEXIO_SPI_MsbFirst) + { + tmpData = (uint32_t)(handle->txData[0]) << 8U; + tmpData += (uint32_t)handle->txData[1]; + } + else + { + tmpData = (uint32_t)(handle->txData[1]) << 8U; + tmpData += (uint32_t)handle->txData[0]; + } + handle->txData += 2U; + } + else + { + if (handle->direction == kFLEXIO_SPI_MsbFirst) + { + tmpData = (uint32_t)(handle->txData[0]) << 24U; + tmpData += (uint32_t)(handle->txData[1]) << 16U; + tmpData += (uint32_t)(handle->txData[2]) << 8U; + tmpData += (uint32_t)handle->txData[3]; + } + else + { + tmpData = (uint32_t)(handle->txData[3]) << 24U; + tmpData += (uint32_t)(handle->txData[2]) << 16U; + tmpData += (uint32_t)(handle->txData[1]) << 8U; + tmpData += (uint32_t)handle->txData[0]; + } + handle->txData += 4U; + } + } + else + { + tmpData = FLEXIO_SPI_DUMMYDATA; + } + + handle->txRemainingBytes -= handle->bytePerFrame; + + FLEXIO_SPI_WriteData(base, handle->direction, tmpData); + + if (0U == handle->txRemainingBytes) + { + FLEXIO_SPI_DisableInterrupts(base, (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable); + } +} + +static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle) +{ + uint32_t tmpData; + + tmpData = FLEXIO_SPI_ReadData(base, handle->direction); + + if (handle->rxData != NULL) + { + if (handle->bytePerFrame == 1U) + { + *handle->rxData = (uint8_t)tmpData; + } + else if (handle->bytePerFrame == 2U) + { + if (handle->direction == kFLEXIO_SPI_LsbFirst) + { + *handle->rxData = (uint8_t)(tmpData >> 8); + handle->rxData++; + *handle->rxData = (uint8_t)tmpData; + } + else + { + *handle->rxData = (uint8_t)tmpData; + handle->rxData++; + *handle->rxData = (uint8_t)(tmpData >> 8); + } + } + else + { + if (handle->direction == kFLEXIO_SPI_LsbFirst) + { + *handle->rxData = (uint8_t)(tmpData >> 24U); + handle->rxData++; + *handle->rxData = (uint8_t)(tmpData >> 16U); + handle->rxData++; + *handle->rxData = (uint8_t)(tmpData >> 8U); + handle->rxData++; + *handle->rxData = (uint8_t)tmpData; + } + else + { + *handle->rxData = (uint8_t)tmpData; + handle->rxData++; + *handle->rxData = (uint8_t)(tmpData >> 8U); + handle->rxData++; + *handle->rxData = (uint8_t)(tmpData >> 16U); + handle->rxData++; + *handle->rxData = (uint8_t)(tmpData >> 24U); + } + } + handle->rxData++; + } + handle->rxRemainingBytes -= handle->bytePerFrame; +} + +/*! + * brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI master hardware, + * and configures the FlexIO SPI with FlexIO SPI master configuration. The + * configuration structure can be filled by the user, or be set with default values + * by the FLEXIO_SPI_MasterGetDefaultConfig(). + * + * note 1.FlexIO SPI master only support CPOL = 0, which means clock inactive low. + * 2.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time + * is 2.5 clock cycles. So if FlexIO SPI master communicates with other spi IPs, the maximum baud + * rate is FlexIO clock frequency divided by 2*2=4. If FlexIO SPI master communicates with FlexIO + * SPI slave, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8. + * + * Example + code + FLEXIO_SPI_Type spiDev = { + .flexioBase = FLEXIO, + .SDOPinIndex = 0, + .SDIPinIndex = 1, + .SCKPinIndex = 2, + .CSnPinIndex = 3, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_spi_master_config_t config = { + .enableMaster = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 500000, + .phase = kFLEXIO_SPI_ClockPhaseFirstEdge, + .direction = kFLEXIO_SPI_MsbFirst, + .dataMode = kFLEXIO_SPI_8BitMode + }; + FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz); + endcode + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param masterConfig Pointer to the flexio_spi_master_config_t structure. + * param srcClock_Hz FlexIO source clock in Hz. +*/ +void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz) +{ + assert(base != NULL); + assert(masterConfig != NULL); + + flexio_shifter_config_t shifterConfig; + flexio_timer_config_t timerConfig; + uint32_t ctrlReg = 0; + uint16_t timerDiv = 0; + uint16_t timerCmp = 0; + + /* Clear the shifterConfig & timerConfig struct. */ + (void)memset(&shifterConfig, 0, sizeof(shifterConfig)); + (void)memset(&timerConfig, 0, sizeof(timerConfig)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate flexio clock. */ + CLOCK_EnableClock(s_flexioClocks[FLEXIO_SPI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Configure FLEXIO SPI Master */ + ctrlReg = base->flexioBase->CTRL; + ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + ctrlReg |= (FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) | + FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster)); + if (!masterConfig->enableInDoze) + { + ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; + } + + base->flexioBase->CTRL = ctrlReg; + + /* Do hardware configuration. */ + /* 1. Configure the shifter 0 for tx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; + shifterConfig.pinSelect = base->SDOPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + } + else + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); + + /* 2. Configure the shifter 1 for rx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->SDIPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + if (masterConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + } + else + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); + + /*3. Configure the timer 0 for SCK. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutput; + timerConfig.pinSelect = base->SCKPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + /* Low 8-bits are used to configure baudrate. */ + timerDiv = (uint16_t)(srcClock_Hz / masterConfig->baudRate_Bps); + timerDiv = timerDiv / 2U - 1U; + /* High 8-bits are used to configure shift clock edges(transfer width). */ + timerCmp = ((uint16_t)masterConfig->dataMode * 2U - 1U) << 8U; + timerCmp |= timerDiv; + + timerConfig.timerCompare = timerCmp; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); + + /* 4. Configure the timer 1 for CSn. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_TIMn(base->timerIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutput; + timerConfig.pinSelect = base->CSnPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveLow; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + + timerConfig.timerCompare = 0xFFFFU; /* Never compare. */ + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); +} + +/*! + * brief Resets the FlexIO SPI timer and shifter config. + * + * param base Pointer to the FLEXIO_SPI_Type. + */ +void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base) +{ + base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0; + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0; + base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0; + base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[0]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[0]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[0]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[1]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[1]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[1]] = 0; +} + +/*! + * brief Gets the default configuration to configure the FlexIO SPI master. The configuration + * can be used directly by calling the FLEXIO_SPI_MasterConfigure(). + * Example: + code + flexio_spi_master_config_t masterConfig; + FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig); + endcode + * param masterConfig Pointer to the flexio_spi_master_config_t structure. +*/ +void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig) +{ + assert(masterConfig != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(masterConfig, 0, sizeof(*masterConfig)); + + masterConfig->enableMaster = true; + masterConfig->enableInDoze = false; + masterConfig->enableInDebug = true; + masterConfig->enableFastAccess = false; + /* Default baud rate 500kbps. */ + masterConfig->baudRate_Bps = 500000U; + /* Default CPHA = 0. */ + masterConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge; + /* Default bit count at 8. */ + masterConfig->dataMode = kFLEXIO_SPI_8BitMode; +} + +/*! + * brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware + * configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The + * configuration structure can be filled by the user, or be set with default values + * by the FLEXIO_SPI_SlaveGetDefaultConfig(). + * + * note 1.Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored. + * 2.FlexIO SPI slave only support CPOL = 0, which means clock inactive low. + * 3.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time + * is 2.5 clock cycles. So if FlexIO SPI slave communicates with other spi IPs, the maximum baud + * rate is FlexIO clock frequency divided by 3*2=6. If FlexIO SPI slave communicates with FlexIO + * SPI master, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8. + * Example + code + FLEXIO_SPI_Type spiDev = { + .flexioBase = FLEXIO, + .SDOPinIndex = 0, + .SDIPinIndex = 1, + .SCKPinIndex = 2, + .CSnPinIndex = 3, + .shifterIndex = {0,1}, + .timerIndex = {0} + }; + flexio_spi_slave_config_t config = { + .enableSlave = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .phase = kFLEXIO_SPI_ClockPhaseFirstEdge, + .direction = kFLEXIO_SPI_MsbFirst, + .dataMode = kFLEXIO_SPI_8BitMode + }; + FLEXIO_SPI_SlaveInit(&spiDev, &config); + endcode + * param base Pointer to the FLEXIO_SPI_Type structure. + * param slaveConfig Pointer to the flexio_spi_slave_config_t structure. +*/ +void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig) +{ + assert((base != NULL) && (slaveConfig != NULL)); + + flexio_shifter_config_t shifterConfig; + flexio_timer_config_t timerConfig; + uint32_t ctrlReg = 0; + + /* Clear the shifterConfig & timerConfig struct. */ + (void)memset(&shifterConfig, 0, sizeof(shifterConfig)); + (void)memset(&timerConfig, 0, sizeof(timerConfig)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate flexio clock. */ + CLOCK_EnableClock(s_flexioClocks[FLEXIO_SPI_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Configure FLEXIO SPI Slave */ + ctrlReg = base->flexioBase->CTRL; + ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + ctrlReg |= (FLEXIO_CTRL_DBGE(slaveConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(slaveConfig->enableFastAccess) | + FLEXIO_CTRL_FLEXEN(slaveConfig->enableSlave)); + if (!slaveConfig->enableInDoze) + { + ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; + } + + base->flexioBase->CTRL = ctrlReg; + + /* Do hardware configuration. */ + /* 1. Configure the shifter 0 for tx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; + shifterConfig.pinSelect = base->SDOPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + } + else + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnShift; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); + + /* 2. Configure the shifter 1 for rx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->SDIPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitDisable; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable; + if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + } + else + { + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + } + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); + + /*3. Configure the timer 0 for shift clock. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->CSnPinIndex); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->SCKPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit; + timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerRisingEdge; + timerConfig.timerStop = kFLEXIO_TimerStopBitDisabled; + if (slaveConfig->phase == kFLEXIO_SPI_ClockPhaseFirstEdge) + { + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerStart = kFLEXIO_TimerStartBitDisabled; + } + else + { + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTriggerFallingEdge; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + } + + timerConfig.timerCompare = (uint32_t)slaveConfig->dataMode * 2U - 1U; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); +} + +/*! + * brief Gates the FlexIO clock. + * + * param base Pointer to the FLEXIO_SPI_Type. + */ +void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base) +{ + FLEXIO_SPI_MasterDeinit(base); +} + +/*! + * brief Gets the default configuration to configure the FlexIO SPI slave. The configuration + * can be used directly for calling the FLEXIO_SPI_SlaveConfigure(). + * Example: + code + flexio_spi_slave_config_t slaveConfig; + FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig); + endcode + * param slaveConfig Pointer to the flexio_spi_slave_config_t structure. +*/ +void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig) +{ + assert(slaveConfig != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(slaveConfig, 0, sizeof(*slaveConfig)); + + slaveConfig->enableSlave = true; + slaveConfig->enableInDoze = false; + slaveConfig->enableInDebug = true; + slaveConfig->enableFastAccess = false; + /* Default CPHA = 0. */ + slaveConfig->phase = kFLEXIO_SPI_ClockPhaseFirstEdge; + /* Default bit count at 8. */ + slaveConfig->dataMode = kFLEXIO_SPI_8BitMode; +} + +/*! + * brief Enables the FlexIO SPI interrupt. + * + * This function enables the FlexIO SPI interrupt. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param mask interrupt source. The parameter can be any combination of the following values: + * arg kFLEXIO_SPI_RxFullInterruptEnable + * arg kFLEXIO_SPI_TxEmptyInterruptEnable + */ +void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask) +{ + if ((mask & (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable) != 0U) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[0]); + } + if ((mask & (uint32_t)kFLEXIO_SPI_RxFullInterruptEnable) != 0U) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[1]); + } +} + +/*! + * brief Disables the FlexIO SPI interrupt. + * + * This function disables the FlexIO SPI interrupt. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param mask interrupt source The parameter can be any combination of the following values: + * arg kFLEXIO_SPI_RxFullInterruptEnable + * arg kFLEXIO_SPI_TxEmptyInterruptEnable + */ +void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask) +{ + if ((mask & (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable) != 0U) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[0]); + } + if ((mask & (uint32_t)kFLEXIO_SPI_RxFullInterruptEnable) != 0U) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[1]); + } +} + +/*! + * brief Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA, + * which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn't trigger the DMA request. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param mask SPI DMA source. + * param enable True means enable DMA, false means disable DMA. + */ +void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable) +{ + if ((mask & (uint32_t)kFLEXIO_SPI_TxDmaEnable) != 0U) + { + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL << base->shifterIndex[0], enable); + } + + if ((mask & (uint32_t)kFLEXIO_SPI_RxDmaEnable) != 0U) + { + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL << base->shifterIndex[1], enable); + } +} + +/*! + * brief Gets FlexIO SPI status flags. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * return status flag; Use the status flag to AND the following flag mask and get the status. + * arg kFLEXIO_SPI_TxEmptyFlag + * arg kFLEXIO_SPI_RxEmptyFlag + */ + +uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base) +{ + uint32_t shifterStatus = FLEXIO_GetShifterStatusFlags(base->flexioBase); + uint32_t status = 0; + + status = ((shifterStatus & (1UL << base->shifterIndex[0])) >> base->shifterIndex[0]); + status |= (((shifterStatus & (1UL << base->shifterIndex[1])) >> (base->shifterIndex[1])) << 1U); + + return status; +} + +/*! + * brief Clears FlexIO SPI status flags. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param mask status flag + * The parameter can be any combination of the following values: + * arg kFLEXIO_SPI_TxEmptyFlag + * arg kFLEXIO_SPI_RxEmptyFlag + */ + +void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask) +{ + if ((mask & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag) != 0U) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1UL << base->shifterIndex[0]); + } + if ((mask & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag) != 0U) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1UL << base->shifterIndex[1]); + } +} + +/*! + * brief Sets baud rate for the FlexIO SPI transfer, which is only used for the master. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param baudRate_Bps Baud Rate needed in Hz. + * param srcClockHz SPI source clock frequency in Hz. + */ +void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz) +{ + uint16_t timerDiv = 0; + uint16_t timerCmp = 0; + FLEXIO_Type *flexioBase = base->flexioBase; + + /* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/ + timerDiv = (uint16_t)(srcClockHz / baudRate_Bps); + timerDiv = timerDiv / 2U - 1U; + + timerCmp = (uint16_t)(flexioBase->TIMCMP[base->timerIndex[0]]); + timerCmp &= 0xFF00U; + timerCmp |= timerDiv; + + flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp; +} + +/*! + * brief Sends a buffer of data bytes. + * + * note This function blocks using the polling method until all bytes have been sent. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param direction Shift direction of MSB first or LSB first. + * param buffer The data bytes to send. + * param size The number of data bytes to send. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted. + */ +status_t FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction, + const uint8_t *buffer, + size_t size) +{ + assert(buffer != NULL); + assert(size != 0U); + +#if SPI_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != size--) + { + /* Wait until data transfer complete. */ +#if SPI_RETRY_TIMES + waitTimes = SPI_RETRY_TIMES; + while ((0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag)) && + (0U != --waitTimes)) +#else + while (0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag)) +#endif + { + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return kStatus_FLEXIO_SPI_Timeout; + } +#endif + FLEXIO_SPI_WriteData(base, direction, *buffer++); + } + + return kStatus_Success; +} + +/*! + * brief Receives a buffer of bytes. + * + * note This function blocks using the polling method until all bytes have been received. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param direction Shift direction of MSB first or LSB first. + * param buffer The buffer to store the received bytes. + * param size The number of data bytes to be received. + * param direction Shift direction of MSB first or LSB first. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted. + */ +status_t FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction, + uint8_t *buffer, + size_t size) +{ + assert(buffer != NULL); + assert(size != 0U); + +#if SPI_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != size--) + { + /* Wait until data transfer complete. */ +#if SPI_RETRY_TIMES + waitTimes = SPI_RETRY_TIMES; + while ((0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag)) && + (0U != --waitTimes)) +#else + while (0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag)) +#endif + { + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return kStatus_FLEXIO_SPI_Timeout; + } +#endif + *buffer++ = (uint8_t)FLEXIO_SPI_ReadData(base, direction); + } + + return kStatus_Success; +} + +/*! + * brief Receives a buffer of bytes. + * + * note This function blocks via polling until all bytes have been received. + * + * param base pointer to FLEXIO_SPI_Type structure + * param xfer FlexIO SPI transfer structure, see #flexio_spi_transfer_t. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted. + */ +status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer) +{ + flexio_spi_shift_direction_t direction; + uint8_t bytesPerFrame; + uint32_t dataMode = 0; + uint16_t timerCmp = (uint16_t)(base->flexioBase->TIMCMP[base->timerIndex[0]]); + uint32_t tmpData = FLEXIO_SPI_DUMMYDATA; + uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags); +#if SPI_RETRY_TIMES + uint32_t waitTimes; +#endif + + timerCmp &= 0x00FFU; + + if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U) + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) | + FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled); + } + else + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) | + FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable); + } + + /* Configure the values in handle. */ + switch (dataFormat) + { + case (uint8_t)kFLEXIO_SPI_8bitMsb: + dataMode = (8UL * 2UL - 1UL) << 8U; + bytesPerFrame = 1U; + direction = kFLEXIO_SPI_MsbFirst; + break; + + case (uint8_t)kFLEXIO_SPI_8bitLsb: + dataMode = (8UL * 2UL - 1UL) << 8U; + bytesPerFrame = 1U; + direction = kFLEXIO_SPI_LsbFirst; + break; + + case (uint8_t)kFLEXIO_SPI_16bitMsb: + dataMode = (16UL * 2UL - 1UL) << 8U; + bytesPerFrame = 2U; + direction = kFLEXIO_SPI_MsbFirst; + break; + + case (uint8_t)kFLEXIO_SPI_16bitLsb: + dataMode = (16UL * 2UL - 1UL) << 8U; + bytesPerFrame = 2U; + direction = kFLEXIO_SPI_LsbFirst; + break; + + case (uint8_t)kFLEXIO_SPI_32bitMsb: + dataMode = (32UL * 2UL - 1UL) << 8U; + bytesPerFrame = 4U; + direction = kFLEXIO_SPI_MsbFirst; + break; + + case (uint8_t)kFLEXIO_SPI_32bitLsb: + dataMode = (32UL * 2UL - 1UL) << 8U; + bytesPerFrame = 4U; + direction = kFLEXIO_SPI_LsbFirst; + break; + + default: + dataMode = (8UL * 2UL - 1UL) << 8U; + bytesPerFrame = 1U; + direction = kFLEXIO_SPI_MsbFirst; + assert(true); + break; + } + + dataMode |= timerCmp; + + /* Transfer size should be bytesPerFrame divisible. */ + if ((xfer->dataSize % bytesPerFrame) != 0U) + { + return kStatus_InvalidArgument; + } + + /* Configure transfer size. */ + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + while (xfer->dataSize != 0U) + { + /* Wait until data transfer complete. */ +#if SPI_RETRY_TIMES + waitTimes = SPI_RETRY_TIMES; + while ((0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag)) && + (0U != --waitTimes)) +#else + while (0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag)) +#endif + { + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return kStatus_FLEXIO_SPI_Timeout; + } +#endif + if (xfer->txData != NULL) + { + /* Transmit data and update tx size/buff. */ + if (bytesPerFrame == 1U) + { + tmpData = (uint32_t) * (xfer->txData); + xfer->txData++; + } + else if (bytesPerFrame == 2U) + { + if (direction == kFLEXIO_SPI_MsbFirst) + { + tmpData = (uint32_t)(xfer->txData[0]) << 8U; + tmpData += (uint32_t)xfer->txData[1]; + } + else + { + tmpData = (uint32_t)(xfer->txData[1]) << 8U; + tmpData += (uint32_t)xfer->txData[0]; + } + xfer->txData += 2U; + } + else + { + if (direction == kFLEXIO_SPI_MsbFirst) + { + tmpData = (uint32_t)(xfer->txData[0]) << 24U; + tmpData += (uint32_t)(xfer->txData[1]) << 16U; + tmpData += (uint32_t)(xfer->txData[2]) << 8U; + tmpData += (uint32_t)xfer->txData[3]; + } + else + { + tmpData = (uint32_t)(xfer->txData[3]) << 24U; + tmpData += (uint32_t)(xfer->txData[2]) << 16U; + tmpData += (uint32_t)(xfer->txData[1]) << 8U; + tmpData += (uint32_t)xfer->txData[0]; + } + xfer->txData += 4U; + } + } + else + { + tmpData = FLEXIO_SPI_DUMMYDATA; + } + + xfer->dataSize -= bytesPerFrame; + + FLEXIO_SPI_WriteData(base, direction, tmpData); + +#if SPI_RETRY_TIMES + waitTimes = SPI_RETRY_TIMES; + while ((0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag)) && + (0U != --waitTimes)) +#else + while (0U == (FLEXIO_SPI_GetStatusFlags(base) & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag)) +#endif + { + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return kStatus_FLEXIO_SPI_Timeout; + } +#endif + tmpData = FLEXIO_SPI_ReadData(base, direction); + + if (xfer->rxData != NULL) + { + if (bytesPerFrame == 1U) + { + *xfer->rxData = (uint8_t)tmpData; + } + else if (bytesPerFrame == 2U) + { + if (direction == kFLEXIO_SPI_LsbFirst) + { + *xfer->rxData = (uint8_t)(tmpData >> 8); + xfer->rxData++; + *xfer->rxData = (uint8_t)tmpData; + } + else + { + *xfer->rxData = (uint8_t)tmpData; + xfer->rxData++; + *xfer->rxData = (uint8_t)(tmpData >> 8); + } + } + else + { + if (direction == kFLEXIO_SPI_LsbFirst) + { + *xfer->rxData = (uint8_t)(tmpData >> 24U); + xfer->rxData++; + *xfer->rxData = (uint8_t)(tmpData >> 16U); + xfer->rxData++; + *xfer->rxData = (uint8_t)(tmpData >> 8U); + xfer->rxData++; + *xfer->rxData = (uint8_t)tmpData; + } + else + { + *xfer->rxData = (uint8_t)tmpData; + xfer->rxData++; + *xfer->rxData = (uint8_t)(tmpData >> 8U); + xfer->rxData++; + *xfer->rxData = (uint8_t)(tmpData >> 16U); + xfer->rxData++; + *xfer->rxData = (uint8_t)(tmpData >> 24U); + } + } + xfer->rxData++; + } + } + + return kStatus_Success; +} + +/*! + * brief Initializes the FlexIO SPI Master handle, which is used in transactional functions. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * param callback The callback function. + * param userData The parameter of the callback function. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + flexio_spi_master_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Register callback and userData. */ + handle->callback = callback; + handle->userData = userData; + + /* Clear pending NVIC IRQ before enable NVIC IRQ. */ + NVIC_ClearPendingIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]); + /* Enable interrupt in NVIC. */ + (void)EnableIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]); + + /* Save the context in global variables to support the double weak mechanism. */ + return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_MasterTransferHandleIRQ); +} + +/*! + * brief Master transfer data using IRQ. + * + * This function sends data using IRQ. This is a non-blocking function, which returns + * right away. When all data is sent out/received, the callback function is called. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_FLEXIO_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + assert(handle != NULL); + assert(xfer != NULL); + + uint32_t dataMode = 0; + uint16_t timerCmp = (uint16_t)base->flexioBase->TIMCMP[base->timerIndex[0]]; + uint32_t tmpData = FLEXIO_SPI_DUMMYDATA; + uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags); + + timerCmp &= 0x00FFU; + + /* Check if SPI is busy. */ + if (handle->state == (uint32_t)kFLEXIO_SPI_Busy) + { + return kStatus_FLEXIO_SPI_Busy; + } + + /* Check if the argument is legal. */ + if ((xfer->txData == NULL) && (xfer->rxData == NULL)) + { + return kStatus_InvalidArgument; + } + + /* Timer1 controls the CS signal which enables/disables(asserts/deasserts) when timer0 enable/disable. Timer0 + enables when tx shifter is written and disables when timer compare. The timer compare event causes the + transmit shift registers to load which generates a tx register empty event. Since when timer stop bit is + disabled, a timer enable condition can be detected in the same cycle as a timer disable condition, so if + software writes the tx register upon the detection of tx register empty event, the timer enable condition + is triggered again, then the CS signal can remain low until software no longer writes the tx register. */ + if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U) + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) | + FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled); + } + else + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) | + FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable); + } + + /* Configure the values in handle */ + switch (dataFormat) + { + case (uint8_t)kFLEXIO_SPI_8bitMsb: + dataMode = (8UL * 2UL - 1UL) << 8U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_8bitLsb: + dataMode = (8UL * 2UL - 1UL) << 8U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_16bitMsb: + dataMode = (16UL * 2UL - 1UL) << 8U; + handle->bytePerFrame = 2U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_16bitLsb: + dataMode = (16UL * 2UL - 1UL) << 8U; + handle->bytePerFrame = 2U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_32bitMsb: + dataMode = (32UL * 2UL - 1UL) << 8U; + handle->bytePerFrame = 4U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_32bitLsb: + dataMode = (32UL * 2UL - 1UL) << 8U; + handle->bytePerFrame = 4U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; + default: + dataMode = (8UL * 2UL - 1UL) << 8U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_MsbFirst; + assert(true); + break; + } + + dataMode |= timerCmp; + + /* Transfer size should be bytesPerFrame divisible. */ + if ((xfer->dataSize % handle->bytePerFrame) != 0U) + { + return kStatus_InvalidArgument; + } + + /* Configure transfer size. */ + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + handle->state = (uint32_t)kFLEXIO_SPI_Busy; + handle->txData = xfer->txData; + handle->rxData = xfer->rxData; + handle->rxRemainingBytes = xfer->dataSize; + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + /* Send first byte of data to trigger the rx interrupt. */ + if (handle->txData != NULL) + { + /* Transmit data and update tx size/buff. */ + if (handle->bytePerFrame == 1U) + { + tmpData = (uint32_t) * (handle->txData); + handle->txData++; + } + else if (handle->bytePerFrame == 2U) + { + if (handle->direction == kFLEXIO_SPI_MsbFirst) + { + tmpData = (uint32_t)(handle->txData[0]) << 8U; + tmpData += (uint32_t)handle->txData[1]; + } + else + { + tmpData = (uint32_t)(handle->txData[1]) << 8U; + tmpData += (uint32_t)handle->txData[0]; + } + handle->txData += 2U; + } + else + { + if (handle->direction == kFLEXIO_SPI_MsbFirst) + { + tmpData = (uint32_t)(handle->txData[0]) << 24U; + tmpData += (uint32_t)(handle->txData[1]) << 16U; + tmpData += (uint32_t)(handle->txData[2]) << 8U; + tmpData += (uint32_t)handle->txData[3]; + } + else + { + tmpData = (uint32_t)(handle->txData[3]) << 24U; + tmpData += (uint32_t)(handle->txData[2]) << 16U; + tmpData += (uint32_t)(handle->txData[1]) << 8U; + tmpData += (uint32_t)handle->txData[0]; + } + handle->txData += 4U; + } + } + else + { + tmpData = FLEXIO_SPI_DUMMYDATA; + } + + handle->txRemainingBytes = xfer->dataSize - handle->bytePerFrame; + + FLEXIO_SPI_WriteData(base, handle->direction, tmpData); + + /* Enable transmit and receive interrupt to handle rx. */ + FLEXIO_SPI_EnableInterrupts(base, (uint32_t)kFLEXIO_SPI_RxFullInterruptEnable); + + if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U) + { + FLEXIO_SPI_EnableInterrupts(base, (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable); + } + + return kStatus_Success; +} + +/*! + * brief Gets the data transfer status which used IRQ. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * param count Number of bytes transferred so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Return remaing bytes in different cases. */ + if (handle->rxData != NULL) + { + *count = handle->transferSize - handle->rxRemainingBytes; + } + else + { + *count = handle->transferSize - handle->txRemainingBytes; + } + + return kStatus_Success; +} + +/*! + * brief Aborts the master data transfer, which used IRQ. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + */ +void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle) +{ + assert(handle != NULL); + + FLEXIO_SPI_DisableInterrupts(base, (uint32_t)kFLEXIO_SPI_RxFullInterruptEnable); + FLEXIO_SPI_DisableInterrupts(base, (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable); + + /* Transfer finished, set the state to idle. */ + handle->state = (uint32_t)kFLEXIO_SPI_Idle; + + /* Clear the internal state. */ + handle->rxRemainingBytes = 0; + handle->txRemainingBytes = 0; +} + +/*! + * brief FlexIO SPI master IRQ handler function. + * + * param spiType Pointer to the FLEXIO_SPI_Type structure. + * param spiHandle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + */ +void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle) +{ + assert(spiHandle != NULL); + + flexio_spi_master_handle_t *handle = (flexio_spi_master_handle_t *)spiHandle; + FLEXIO_SPI_Type *base; + uint32_t status; + + if (handle->state == (uint32_t)kFLEXIO_SPI_Idle) + { + return; + } + + base = (FLEXIO_SPI_Type *)spiType; + status = FLEXIO_SPI_GetStatusFlags(base); + + /* Receive interrupt. */ + if ((status & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag) == 0U) + { + FLEXIO_SPI_TransferSendTransaction(base, handle); + return; + } + + /* Handle rx. */ + if (handle->rxRemainingBytes != 0U) + { + FLEXIO_SPI_TransferReceiveTransaction(base, handle); + } + + /* Handle tx. */ + if (((status & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag) != 0U) && (handle->txRemainingBytes != 0U)) + { + FLEXIO_SPI_TransferSendTransaction(base, handle); + } + + /* All the transfer finished. */ + if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U)) + { + FLEXIO_SPI_MasterTransferAbort(base, handle); + if (handle->callback != NULL) + { + (handle->callback)(base, handle, kStatus_FLEXIO_SPI_Idle, handle->userData); + } + } +} + +/*! + * brief Initializes the FlexIO SPI Slave handle, which is used in transactional functions. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + * param callback The callback function. + * param userData The parameter of the callback function. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + flexio_spi_slave_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Register callback and userData. */ + handle->callback = callback; + handle->userData = userData; + + /* Clear pending NVIC IRQ before enable NVIC IRQ. */ + NVIC_ClearPendingIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]); + /* Enable interrupt in NVIC. */ + (void)EnableIRQ(flexio_irqs[FLEXIO_SPI_GetInstance(base)]); + + /* Save the context in global variables to support the double weak mechanism. */ + return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_SPI_SlaveTransferHandleIRQ); +} + +/*! + * brief Slave transfer data using IRQ. + * + * This function sends data using IRQ. This is a non-blocking function, which returns + * right away. When all data is sent out/received, the callback function is called. + * param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + * param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_FLEXIO_SPI_Busy SPI is not idle; it is running another transfer. + */ +status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + assert(handle != NULL); + assert(xfer != NULL); + + uint32_t dataMode = 0; + uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags); + + /* Check if SPI is busy. */ + if (handle->state == (uint32_t)kFLEXIO_SPI_Busy) + { + return kStatus_FLEXIO_SPI_Busy; + } + + /* Check if the argument is legal. */ + if ((xfer->txData == NULL) && (xfer->rxData == NULL)) + { + return kStatus_InvalidArgument; + } + + /* SCK timer use CS pin as inverted trigger so timer should be disbaled on trigger falling edge(CS re-asserts). */ + /* However if CPHA is first edge mode, timer will restart each time right after timer compare event occur and + before CS pin re-asserts, which triggers another shifter load. To avoid this, when in CS dis-continuous mode, + timer should disable in timer compare rather than trigger falling edge(CS re-asserts), and in CS continuous mode, + tx/rx shifters should be flushed after transfer finishes and before next transfer starts. */ + FLEXIO_SPI_FlushShifters(base); + if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U) + { + base->flexioBase->TIMCFG[base->timerIndex[0]] |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge); + } + else + { + if ((base->flexioBase->SHIFTCTL[base->shifterIndex[0]] & FLEXIO_SHIFTCTL_TIMPOL_MASK) == + FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive)) + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) | + FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare); + } + else + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) | + FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge); + } + } + + /* Configure the values in handle */ + switch (dataFormat) + { + case (uint8_t)kFLEXIO_SPI_8bitMsb: + dataMode = 8U * 2U - 1U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_8bitLsb: + dataMode = 8U * 2U - 1U; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_16bitMsb: + dataMode = 16U * 2U - 1U; + handle->bytePerFrame = 2U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_16bitLsb: + dataMode = 16U * 2U - 1U; + handle->bytePerFrame = 2U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_32bitMsb: + dataMode = 32UL * 2UL - 1UL; + handle->bytePerFrame = 4U; + handle->direction = kFLEXIO_SPI_MsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_32bitLsb: + dataMode = 32UL * 2UL - 1UL; + handle->bytePerFrame = 4U; + handle->direction = kFLEXIO_SPI_LsbFirst; + break; + default: + dataMode = 8UL * 2UL - 1UL; + handle->bytePerFrame = 1U; + handle->direction = kFLEXIO_SPI_MsbFirst; + assert(true); + break; + } + + /* Transfer size should be bytesPerFrame divisible. */ + if ((xfer->dataSize % handle->bytePerFrame) != 0U) + { + return kStatus_InvalidArgument; + } + + /* Configure transfer size. */ + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + handle->state = (uint32_t)kFLEXIO_SPI_Busy; + handle->txData = xfer->txData; + handle->rxData = xfer->rxData; + handle->txRemainingBytes = xfer->dataSize; + handle->rxRemainingBytes = xfer->dataSize; + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + /* Enable transmit and receive interrupt to handle tx and rx. */ + FLEXIO_SPI_EnableInterrupts(base, (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable); + FLEXIO_SPI_EnableInterrupts(base, (uint32_t)kFLEXIO_SPI_RxFullInterruptEnable); + + return kStatus_Success; +} + +/*! + * brief FlexIO SPI slave IRQ handler function. + * + * param spiType Pointer to the FLEXIO_SPI_Type structure. + * param spiHandle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + */ +void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle) +{ + assert(spiHandle != NULL); + + flexio_spi_master_handle_t *handle = (flexio_spi_master_handle_t *)spiHandle; + FLEXIO_SPI_Type *base; + uint32_t status; + + if (handle->state == (uint32_t)kFLEXIO_SPI_Idle) + { + return; + } + + base = (FLEXIO_SPI_Type *)spiType; + status = FLEXIO_SPI_GetStatusFlags(base); + + /* Handle tx. */ + if (((status & (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag) != 0U) && (handle->txRemainingBytes != 0U)) + { + FLEXIO_SPI_TransferSendTransaction(base, handle); + } + + /* Handle rx. */ + if (((status & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag) != 0U) && (handle->rxRemainingBytes != 0U)) + { + FLEXIO_SPI_TransferReceiveTransaction(base, handle); + } + + /* All the transfer finished. */ + if ((handle->txRemainingBytes == 0U) && (handle->rxRemainingBytes == 0U)) + { + FLEXIO_SPI_SlaveTransferAbort(base, handle); + if (handle->callback != NULL) + { + (handle->callback)(base, handle, kStatus_FLEXIO_SPI_Idle, handle->userData); + } + } +} + +/*! + * brief Flush tx/rx shifters. + * + * param base Pointer to the FLEXIO_SPI_Type structure. + */ +void FLEXIO_SPI_FlushShifters(FLEXIO_SPI_Type *base) +{ + /* Disable then re-enable to flush the tx shifter. */ + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] &= ~FLEXIO_SHIFTCTL_SMOD_MASK; + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] |= FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit); + /* Read to flush the rx shifter. */ + (void)base->flexioBase->SHIFTBUF[base->shifterIndex[1]]; +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_spi.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_spi.h new file mode 100644 index 00000000000..cae17a802c9 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_spi.h @@ -0,0 +1,718 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020, 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_FLEXIO_SPI_H_ +#define FSL_FLEXIO_SPI_H_ + +#include "fsl_common.h" +#include "fsl_flexio.h" + +/*! + * @addtogroup flexio_spi + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief FlexIO SPI driver version. */ +#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 4)) +/*! @} */ + +#ifndef FLEXIO_SPI_DUMMYDATA +/*! @brief FlexIO SPI dummy transfer data, the data is sent while txData is NULL. */ +#define FLEXIO_SPI_DUMMYDATA (0x00U) +#endif + +/*! @brief Retry times for waiting flag. */ +#ifndef SPI_RETRY_TIMES +#define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +/*! @brief Get the transfer data format of width and bit order. */ +#define FLEXIO_SPI_XFER_DATA_FORMAT(flag) ((flag) & (0x7U)) + +/*! @brief Error codes for the FlexIO SPI driver. */ +enum +{ + kStatus_FLEXIO_SPI_Busy = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 1), /*!< FlexIO SPI is busy. */ + kStatus_FLEXIO_SPI_Idle = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 2), /*!< SPI is idle */ + kStatus_FLEXIO_SPI_Error = MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 3), /*!< FlexIO SPI error. */ + kStatus_FLEXIO_SPI_Timeout = + MAKE_STATUS(kStatusGroup_FLEXIO_SPI, 4), /*!< FlexIO SPI timeout polling status flags. */ +}; + +/*! @brief FlexIO SPI clock phase configuration. */ +typedef enum _flexio_spi_clock_phase +{ + kFLEXIO_SPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SPSCK occurs at the middle of the first + * cycle of a data transfer. */ + kFLEXIO_SPI_ClockPhaseSecondEdge = 0x1U, /*!< First edge on SPSCK occurs at the start of the + * first cycle of a data transfer. */ +} flexio_spi_clock_phase_t; + +/*! @brief FlexIO SPI data shifter direction options. */ +typedef enum _flexio_spi_shift_direction +{ + kFLEXIO_SPI_MsbFirst = 0, /*!< Data transfers start with most significant bit. */ + kFLEXIO_SPI_LsbFirst = 1, /*!< Data transfers start with least significant bit. */ +} flexio_spi_shift_direction_t; + +/*! @brief FlexIO SPI data length mode options. */ +typedef enum _flexio_spi_data_bitcount_mode +{ + kFLEXIO_SPI_8BitMode = 0x08U, /*!< 8-bit data transmission mode. */ + kFLEXIO_SPI_16BitMode = 0x10U, /*!< 16-bit data transmission mode. */ + kFLEXIO_SPI_32BitMode = 0x20U, /*!< 32-bit data transmission mode. */ +} flexio_spi_data_bitcount_mode_t; + +/*! @brief Define FlexIO SPI interrupt mask. */ +enum _flexio_spi_interrupt_enable +{ + kFLEXIO_SPI_TxEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */ + kFLEXIO_SPI_RxFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */ +}; + +/*! @brief Define FlexIO SPI status mask. */ +enum _flexio_spi_status_flags +{ + kFLEXIO_SPI_TxBufferEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */ + kFLEXIO_SPI_RxBufferFullFlag = 0x2U, /*!< Receive buffer full flag. */ +}; + +/*! @brief Define FlexIO SPI DMA mask. */ +enum _flexio_spi_dma_enable +{ + kFLEXIO_SPI_TxDmaEnable = 0x1U, /*!< Tx DMA request source */ + kFLEXIO_SPI_RxDmaEnable = 0x2U, /*!< Rx DMA request source */ + kFLEXIO_SPI_DmaAllEnable = 0x3U, /*!< All DMA request source*/ +}; + +/*! @brief Define FlexIO SPI transfer flags. + * @note Use kFLEXIO_SPI_csContinuous and one of the other flags to OR together to form the transfer flag. */ +enum _flexio_spi_transfer_flags +{ + kFLEXIO_SPI_8bitMsb = 0x0U, /*!< FlexIO SPI 8-bit MSB first */ + kFLEXIO_SPI_8bitLsb = 0x1U, /*!< FlexIO SPI 8-bit LSB first */ + kFLEXIO_SPI_16bitMsb = 0x2U, /*!< FlexIO SPI 16-bit MSB first */ + kFLEXIO_SPI_16bitLsb = 0x3U, /*!< FlexIO SPI 16-bit LSB first */ + kFLEXIO_SPI_32bitMsb = 0x4U, /*!< FlexIO SPI 32-bit MSB first */ + kFLEXIO_SPI_32bitLsb = 0x5U, /*!< FlexIO SPI 32-bit LSB first */ + kFLEXIO_SPI_csContinuous = 0x8U, /*!< Enable the CS signal continuous mode */ +}; + +/*! @brief Define FlexIO SPI access structure typedef. */ +typedef struct _flexio_spi_type +{ + FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ + uint8_t SDOPinIndex; /*!< Pin select for data output. To set SDO pin in Hi-Z state, user needs to mux the pin as + GPIO input and disable all pull up/down in application. */ + uint8_t SDIPinIndex; /*!< Pin select for data input. */ + uint8_t SCKPinIndex; /*!< Pin select for clock. */ + uint8_t CSnPinIndex; /*!< Pin select for enable. */ + uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO SPI. */ + uint8_t timerIndex[2]; /*!< Timer index used in FlexIO SPI. */ +} FLEXIO_SPI_Type; + +/*! @brief Define FlexIO SPI master configuration structure. */ +typedef struct _flexio_spi_master_config +{ + bool enableMaster; /*!< Enable/disable FlexIO SPI master after configuration. */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, + fast access requires the FlexIO clock to be at least + twice the frequency of the bus clock. */ + uint32_t baudRate_Bps; /*!< Baud rate in Bps. */ + flexio_spi_clock_phase_t phase; /*!< Clock phase. */ + flexio_spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode. */ +} flexio_spi_master_config_t; + +/*! @brief Define FlexIO SPI slave configuration structure. */ +typedef struct _flexio_spi_slave_config +{ + bool enableSlave; /*!< Enable/disable FlexIO SPI slave after configuration. */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode. */ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode. */ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, + fast access requires the FlexIO clock to be at least + twice the frequency of the bus clock. */ + flexio_spi_clock_phase_t phase; /*!< Clock phase. */ + flexio_spi_data_bitcount_mode_t dataMode; /*!< 8bit or 16bit mode. */ +} flexio_spi_slave_config_t; + +/*! @brief Define FlexIO SPI transfer structure. */ +typedef struct _flexio_spi_transfer +{ + const uint8_t *txData; /*!< Send buffer. */ + uint8_t *rxData; /*!< Receive buffer. */ + size_t dataSize; /*!< Transfer bytes. */ + uint8_t flags; /*!< FlexIO SPI control flag, MSB first or LSB first. */ +} flexio_spi_transfer_t; + +/*! @brief typedef for flexio_spi_master_handle_t in advance. */ +typedef struct _flexio_spi_master_handle flexio_spi_master_handle_t; + +/*! @brief Slave handle is the same with master handle. */ +typedef flexio_spi_master_handle_t flexio_spi_slave_handle_t; + +/*! @brief FlexIO SPI master callback for finished transmit */ +typedef void (*flexio_spi_master_transfer_callback_t)(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + status_t status, + void *userData); + +/*! @brief FlexIO SPI slave callback for finished transmit */ +typedef void (*flexio_spi_slave_transfer_callback_t)(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Define FlexIO SPI handle structure. */ +struct _flexio_spi_master_handle +{ + const uint8_t *txData; /*!< Transfer buffer. */ + uint8_t *rxData; /*!< Receive buffer. */ + size_t transferSize; /*!< Total bytes to be transferred. */ + volatile size_t txRemainingBytes; /*!< Send data remaining in bytes. */ + volatile size_t rxRemainingBytes; /*!< Receive data remaining in bytes. */ + volatile uint32_t state; /*!< FlexIO SPI internal state. */ + uint8_t bytePerFrame; /*!< SPI mode, 2bytes or 1byte in a frame */ + flexio_spi_shift_direction_t direction; /*!< Shift direction. */ + flexio_spi_master_transfer_callback_t callback; /*!< FlexIO SPI callback. */ + void *userData; /*!< Callback parameter. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name FlexIO SPI Configuration + * @{ + */ + +/*! + * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI master hardware, + * and configures the FlexIO SPI with FlexIO SPI master configuration. The + * configuration structure can be filled by the user, or be set with default values + * by the FLEXIO_SPI_MasterGetDefaultConfig(). + * + * @note 1.FlexIO SPI master only support CPOL = 0, which means clock inactive low. + * 2.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time + * is 2.5 clock cycles. So if FlexIO SPI master communicates with other spi IPs, the maximum baud + * rate is FlexIO clock frequency divided by 2*2=4. If FlexIO SPI master communicates with FlexIO + * SPI slave, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8. + * + * Example + @code + FLEXIO_SPI_Type spiDev = { + .flexioBase = FLEXIO, + .SDOPinIndex = 0, + .SDIPinIndex = 1, + .SCKPinIndex = 2, + .CSnPinIndex = 3, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_spi_master_config_t config = { + .enableMaster = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 500000, + .phase = kFLEXIO_SPI_ClockPhaseFirstEdge, + .direction = kFLEXIO_SPI_MsbFirst, + .dataMode = kFLEXIO_SPI_8BitMode + }; + FLEXIO_SPI_MasterInit(&spiDev, &config, srcClock_Hz); + @endcode + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param masterConfig Pointer to the flexio_spi_master_config_t structure. + * @param srcClock_Hz FlexIO source clock in Hz. +*/ +void FLEXIO_SPI_MasterInit(FLEXIO_SPI_Type *base, flexio_spi_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief Resets the FlexIO SPI timer and shifter config. + * + * @param base Pointer to the FLEXIO_SPI_Type. + */ +void FLEXIO_SPI_MasterDeinit(FLEXIO_SPI_Type *base); + +/*! + * @brief Gets the default configuration to configure the FlexIO SPI master. The configuration + * can be used directly by calling the FLEXIO_SPI_MasterConfigure(). + * Example: + @code + flexio_spi_master_config_t masterConfig; + FLEXIO_SPI_MasterGetDefaultConfig(&masterConfig); + @endcode + * @param masterConfig Pointer to the flexio_spi_master_config_t structure. +*/ +void FLEXIO_SPI_MasterGetDefaultConfig(flexio_spi_master_config_t *masterConfig); + +/*! + * @brief Ungates the FlexIO clock, resets the FlexIO module, configures the FlexIO SPI slave hardware + * configuration, and configures the FlexIO SPI with FlexIO SPI slave configuration. The + * configuration structure can be filled by the user, or be set with default values + * by the FLEXIO_SPI_SlaveGetDefaultConfig(). + * + * @note 1.Only one timer is needed in the FlexIO SPI slave. As a result, the second timer index is ignored. + * 2.FlexIO SPI slave only support CPOL = 0, which means clock inactive low. + * 3.For FlexIO SPI master, the input valid time is 1.5 clock cycles, for slave the output valid time + * is 2.5 clock cycles. So if FlexIO SPI slave communicates with other spi IPs, the maximum baud + * rate is FlexIO clock frequency divided by 3*2=6. If FlexIO SPI slave communicates with FlexIO + * SPI master, the maximum baud rate is FlexIO clock frequency divided by (1.5+2.5)*2=8. + * Example + @code + FLEXIO_SPI_Type spiDev = { + .flexioBase = FLEXIO, + .SDOPinIndex = 0, + .SDIPinIndex = 1, + .SCKPinIndex = 2, + .CSnPinIndex = 3, + .shifterIndex = {0,1}, + .timerIndex = {0} + }; + flexio_spi_slave_config_t config = { + .enableSlave = true, + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .phase = kFLEXIO_SPI_ClockPhaseFirstEdge, + .direction = kFLEXIO_SPI_MsbFirst, + .dataMode = kFLEXIO_SPI_8BitMode + }; + FLEXIO_SPI_SlaveInit(&spiDev, &config); + @endcode + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param slaveConfig Pointer to the flexio_spi_slave_config_t structure. +*/ +void FLEXIO_SPI_SlaveInit(FLEXIO_SPI_Type *base, flexio_spi_slave_config_t *slaveConfig); + +/*! + * @brief Gates the FlexIO clock. + * + * @param base Pointer to the FLEXIO_SPI_Type. + */ +void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base); + +/*! + * @brief Gets the default configuration to configure the FlexIO SPI slave. The configuration + * can be used directly for calling the FLEXIO_SPI_SlaveConfigure(). + * Example: + @code + flexio_spi_slave_config_t slaveConfig; + FLEXIO_SPI_SlaveGetDefaultConfig(&slaveConfig); + @endcode + * @param slaveConfig Pointer to the flexio_spi_slave_config_t structure. +*/ +void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig); + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets FlexIO SPI status flags. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @return status flag; Use the status flag to AND the following flag mask and get the status. + * @arg kFLEXIO_SPI_TxEmptyFlag + * @arg kFLEXIO_SPI_RxEmptyFlag + */ + +uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base); + +/*! + * @brief Clears FlexIO SPI status flags. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param mask status flag + * The parameter can be any combination of the following values: + * @arg kFLEXIO_SPI_TxEmptyFlag + * @arg kFLEXIO_SPI_RxEmptyFlag + */ + +void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask); + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the FlexIO SPI interrupt. + * + * This function enables the FlexIO SPI interrupt. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param mask interrupt source. The parameter can be any combination of the following values: + * @arg kFLEXIO_SPI_RxFullInterruptEnable + * @arg kFLEXIO_SPI_TxEmptyInterruptEnable + */ +void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask); + +/*! + * @brief Disables the FlexIO SPI interrupt. + * + * This function disables the FlexIO SPI interrupt. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param mask interrupt source The parameter can be any combination of the following values: + * @arg kFLEXIO_SPI_RxFullInterruptEnable + * @arg kFLEXIO_SPI_TxEmptyInterruptEnable + */ +void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask); + +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables/disables the FlexIO SPI transmit DMA. This function enables/disables the FlexIO SPI Tx DMA, + * which means that asserting the kFLEXIO_SPI_TxEmptyFlag does/doesn't trigger the DMA request. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param mask SPI DMA source. + * @param enable True means enable DMA, false means disable DMA. + */ +void FLEXIO_SPI_EnableDMA(FLEXIO_SPI_Type *base, uint32_t mask, bool enable); + +/*! + * @brief Gets the FlexIO SPI transmit data register address for MSB first transfer. + * + * This function returns the SPI data register address, which is mainly used by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @return FlexIO SPI transmit data register address. + */ +static inline uint32_t FLEXIO_SPI_GetTxDataRegisterAddress(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction) +{ + if (direction == kFLEXIO_SPI_MsbFirst) + { + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, + base->shifterIndex[0]) + + 3U; + } + else + { + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[0]); + } +} + +/*! + * @brief Gets the FlexIO SPI receive data register address for the MSB first transfer. + * + * This function returns the SPI data register address, which is mainly used by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @return FlexIO SPI receive data register address. + */ +static inline uint32_t FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction) +{ + if (direction == kFLEXIO_SPI_MsbFirst) + { + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferBitSwapped, base->shifterIndex[1]); + } + else + { + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[1]) + 3U; + } +} + +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables/disables the FlexIO SPI module operation. + * + * @param base Pointer to the FLEXIO_SPI_Type. + * @param enable True to enable, false does not have any effect. + */ +static inline void FLEXIO_SPI_Enable(FLEXIO_SPI_Type *base, bool enable) +{ + if (enable) + { + base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } +} + +/*! + * @brief Sets baud rate for the FlexIO SPI transfer, which is only used for the master. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param baudRate_Bps Baud Rate needed in Hz. + * @param srcClockHz SPI source clock frequency in Hz. + */ +void FLEXIO_SPI_MasterSetBaudRate(FLEXIO_SPI_Type *base, uint32_t baudRate_Bps, uint32_t srcClockHz); + +/*! + * @brief Writes one byte of data, which is sent using the MSB method. + * + * @note This is a non-blocking API, which returns directly after the data is put into the + * data register but the data transfer is not finished on the bus. Ensure that + * the TxEmptyFlag is asserted before calling this API. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @param data 8/16/32 bit data. + */ +static inline void FLEXIO_SPI_WriteData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction, uint32_t data) +{ + if (direction == kFLEXIO_SPI_MsbFirst) + { + base->flexioBase->SHIFTBUFBBS[base->shifterIndex[0]] = data; + } + else + { + base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = data; + } +} + +/*! + * @brief Reads 8 bit/16 bit data. + * + * @note This is a non-blocking API, which returns directly after the data is read from the + * data register. Ensure that the RxFullFlag is asserted before calling this API. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @return 8 bit/16 bit data received. + */ +static inline uint32_t FLEXIO_SPI_ReadData(FLEXIO_SPI_Type *base, flexio_spi_shift_direction_t direction) +{ + if (direction == kFLEXIO_SPI_MsbFirst) + { + return (uint32_t)(base->flexioBase->SHIFTBUFBIS[base->shifterIndex[1]]); + } + else + { + return (uint32_t)(base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]); + } +} + +/*! + * @brief Sends a buffer of data bytes. + * + * @note This function blocks using the polling method until all bytes have been sent. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @param buffer The data bytes to send. + * @param size The number of data bytes to send. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted. + */ +status_t FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction, + const uint8_t *buffer, + size_t size); + +/*! + * @brief Receives a buffer of bytes. + * + * @note This function blocks using the polling method until all bytes have been received. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param direction Shift direction of MSB first or LSB first. + * @param buffer The buffer to store the received bytes. + * @param size The number of data bytes to be received. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted. + */ +status_t FLEXIO_SPI_ReadBlocking(FLEXIO_SPI_Type *base, + flexio_spi_shift_direction_t direction, + uint8_t *buffer, + size_t size); + +/*! + * @brief Receives a buffer of bytes. + * + * @note This function blocks via polling until all bytes have been received. + * + * @param base pointer to FLEXIO_SPI_Type structure + * @param xfer FlexIO SPI transfer structure, see #flexio_spi_transfer_t. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted. + */ +status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_transfer_t *xfer); + +/*! + * @brief Flush tx/rx shifters. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + */ +void FLEXIO_SPI_FlushShifters(FLEXIO_SPI_Type *base); +/*! @} */ + +/*Transactional APIs*/ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the FlexIO SPI Master handle, which is used in transactional functions. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_SPI_MasterTransferCreateHandle(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + flexio_spi_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Master transfer data using IRQ. + * + * This function sends data using IRQ. This is a non-blocking function, which returns + * right away. When all data is sent out/received, the callback function is called. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * @param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_SPI_Busy SPI is not idle, is running another transfer. + */ +status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base, + flexio_spi_master_handle_t *handle, + flexio_spi_transfer_t *xfer); + +/*! + * @brief Aborts the master data transfer, which used IRQ. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + */ +void FLEXIO_SPI_MasterTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle); + +/*! + * @brief Gets the data transfer status which used IRQ. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_SPI_MasterTransferGetCount(FLEXIO_SPI_Type *base, flexio_spi_master_handle_t *handle, size_t *count); + +/*! + * @brief FlexIO SPI master IRQ handler function. + * + * @param spiType Pointer to the FLEXIO_SPI_Type structure. + * @param spiHandle Pointer to the flexio_spi_master_handle_t structure to store the transfer state. + */ +void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle); + +/*! + * @brief Initializes the FlexIO SPI Slave handle, which is used in transactional functions. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_SPI_SlaveTransferCreateHandle(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + flexio_spi_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Slave transfer data using IRQ. + * + * This function sends data using IRQ. This is a non-blocking function, which returns + * right away. When all data is sent out/received, the callback function is called. + * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param xfer FlexIO SPI transfer structure. See #flexio_spi_transfer_t. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_SPI_Busy SPI is not idle; it is running another transfer. + */ +status_t FLEXIO_SPI_SlaveTransferNonBlocking(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + flexio_spi_transfer_t *xfer); + +/*! + * @brief Aborts the slave data transfer which used IRQ, share same API with master. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + */ +static inline void FLEXIO_SPI_SlaveTransferAbort(FLEXIO_SPI_Type *base, flexio_spi_slave_handle_t *handle) +{ + FLEXIO_SPI_MasterTransferAbort(base, handle); +} +/*! + * @brief Gets the data transfer status which used IRQ, share same API with master. + * + * @param base Pointer to the FLEXIO_SPI_Type structure. + * @param handle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ +static inline status_t FLEXIO_SPI_SlaveTransferGetCount(FLEXIO_SPI_Type *base, + flexio_spi_slave_handle_t *handle, + size_t *count) +{ + return FLEXIO_SPI_MasterTransferGetCount(base, handle, count); +} + +/*! + * @brief FlexIO SPI slave IRQ handler function. + * + * @param spiType Pointer to the FLEXIO_SPI_Type structure. + * @param spiHandle Pointer to the flexio_spi_slave_handle_t structure to store the transfer state. + */ +void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*! @} */ + +#endif /*FSL_FLEXIO_SPI_H_*/ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_spi_edma.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_spi_edma.c new file mode 100644 index 00000000000..c1feba0f001 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_spi_edma.c @@ -0,0 +1,565 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020, 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_spi_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_spi_edma" +#endif + +/*base, (uint32_t)kFLEXIO_SPI_TxDmaEnable, false); + + /* change the state */ + spiPrivateHandle->handle->txInProgress = false; + + /* All finished, call the callback */ + if ((spiPrivateHandle->handle->txInProgress == false) && (spiPrivateHandle->handle->rxInProgress == false)) + { + if (spiPrivateHandle->handle->callback != NULL) + { + (spiPrivateHandle->handle->callback)(spiPrivateHandle->base, spiPrivateHandle->handle, kStatus_Success, + spiPrivateHandle->handle->userData); + } + } + } +} + +static void FLEXIO_SPI_RxEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) +{ + tcds = tcds; + flexio_spi_master_edma_private_handle_t *spiPrivateHandle = (flexio_spi_master_edma_private_handle_t *)param; + + if (transferDone) + { + /* Disable Rx dma */ + FLEXIO_SPI_EnableDMA(spiPrivateHandle->base, (uint32_t)kFLEXIO_SPI_RxDmaEnable, false); + + /* change the state */ + spiPrivateHandle->handle->rxInProgress = false; + + /* All finished, call the callback */ + if ((spiPrivateHandle->handle->txInProgress == false) && (spiPrivateHandle->handle->rxInProgress == false)) + { + if (spiPrivateHandle->handle->callback != NULL) + { + (spiPrivateHandle->handle->callback)(spiPrivateHandle->base, spiPrivateHandle->handle, kStatus_Success, + spiPrivateHandle->handle->userData); + } + } + } +} + +static status_t FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + edma_transfer_config_t xferConfig = {0}; + flexio_spi_shift_direction_t direction = kFLEXIO_SPI_MsbFirst; + uint8_t bytesPerFrame; + uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags); + + /* Configure the values in handle. */ + switch (dataFormat) + { + case (uint8_t)kFLEXIO_SPI_8bitMsb: + bytesPerFrame = 1U; + direction = kFLEXIO_SPI_MsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_8bitLsb: + bytesPerFrame = 1U; + direction = kFLEXIO_SPI_LsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_16bitMsb: + bytesPerFrame = 2U; + direction = kFLEXIO_SPI_MsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_16bitLsb: + bytesPerFrame = 2U; + direction = kFLEXIO_SPI_LsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_32bitMsb: + bytesPerFrame = 4U; + direction = kFLEXIO_SPI_MsbFirst; + break; + case (uint8_t)kFLEXIO_SPI_32bitLsb: + bytesPerFrame = 4U; + direction = kFLEXIO_SPI_LsbFirst; + break; + default: + bytesPerFrame = 1U; + direction = kFLEXIO_SPI_MsbFirst; + assert(true); + break; + } + + /* Transfer size should be bytesPerFrame divisible. */ + if ((xfer->dataSize % bytesPerFrame) != 0U) + { + return kStatus_InvalidArgument; + } + + /* Save total transfer size. */ + handle->transferSize = xfer->dataSize; + + /* Configure tx transfer EDMA. */ + xferConfig.destAddr = FLEXIO_SPI_GetTxDataRegisterAddress(base, direction); + xferConfig.destOffset = 0; + if (bytesPerFrame == 1U) + { + xferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; + xferConfig.destTransferSize = kEDMA_TransferSize1Bytes; + xferConfig.minorLoopBytes = 1U; + } + else if (bytesPerFrame == 2U) + { + if (direction == kFLEXIO_SPI_MsbFirst) + { + xferConfig.destAddr -= 1U; + } + xferConfig.srcTransferSize = kEDMA_TransferSize2Bytes; + xferConfig.destTransferSize = kEDMA_TransferSize2Bytes; + xferConfig.minorLoopBytes = 2U; + } + else + { + if (direction == kFLEXIO_SPI_MsbFirst) + { + xferConfig.destAddr -= 3U; + } + xferConfig.srcTransferSize = kEDMA_TransferSize4Bytes; + xferConfig.destTransferSize = kEDMA_TransferSize4Bytes; + xferConfig.minorLoopBytes = 4U; + } + + /* Configure DMA channel. */ + if (xfer->txData != NULL) + { + xferConfig.srcOffset = (int16_t)bytesPerFrame; + xferConfig.srcAddr = (uint32_t)(xfer->txData); + } + else + { + /* Disable the source increasement and source set to dummyData. */ + xferConfig.srcOffset = 0; + xferConfig.srcAddr = (uint32_t)(&s_dummyData); + } + + xferConfig.majorLoopCounts = (xfer->dataSize / xferConfig.minorLoopBytes); + + /* Store the initially configured eDMA minor byte transfer count into the FLEXIO SPI handle */ + handle->nbytes = (uint8_t)xferConfig.minorLoopBytes; + + if (handle->txHandle != NULL) + { + (void)EDMA_SubmitTransfer(handle->txHandle, &xferConfig); + } + + /* Configure rx transfer EDMA. */ + if (xfer->rxData != NULL) + { + xferConfig.srcAddr = FLEXIO_SPI_GetRxDataRegisterAddress(base, direction); + if (bytesPerFrame == 2U) + { + if (direction == kFLEXIO_SPI_LsbFirst) + { + xferConfig.srcAddr -= 1U; + } + } + else if (bytesPerFrame == 4U) + { + if (direction == kFLEXIO_SPI_LsbFirst) + { + xferConfig.srcAddr -= 3U; + } + } + else + { + } + xferConfig.srcOffset = 0; + xferConfig.destAddr = (uint32_t)(xfer->rxData); + xferConfig.destOffset = (int16_t)bytesPerFrame; + (void)EDMA_SubmitTransfer(handle->rxHandle, &xferConfig); + handle->rxInProgress = true; + FLEXIO_SPI_EnableDMA(base, (uint32_t)kFLEXIO_SPI_RxDmaEnable, true); + EDMA_StartTransfer(handle->rxHandle); + } + + /* Always start tx transfer. */ + if (handle->txHandle != NULL) + { + handle->txInProgress = true; + FLEXIO_SPI_EnableDMA(base, (uint32_t)kFLEXIO_SPI_TxDmaEnable, true); + EDMA_StartTransfer(handle->txHandle); + } + + return kStatus_Success; +} + +/*! + * brief Initializes the FlexIO SPI master eDMA handle. + * + * This function initializes the FlexIO SPI master eDMA handle which can be used for other FlexIO SPI master + * transactional + * APIs. + * For a specified FlexIO SPI instance, call this API once to get the initialized handle. + * + * param base Pointer to FLEXIO_SPI_Type structure. + * param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state. + * param callback SPI callback, NULL means no callback. + * param userData callback function parameter. + * param txHandle User requested eDMA handle for FlexIO SPI RX eDMA transfer. + * param rxHandle User requested eDMA handle for FlexIO SPI TX eDMA transfer. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range. + */ +status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + flexio_spi_master_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txHandle, + edma_handle_t *rxHandle) +{ + assert(handle != NULL); + + uint8_t index = 0; + + /* Find the an empty handle pointer to store the handle. */ + for (index = 0U; index < (uint8_t)FLEXIO_SPI_HANDLE_COUNT; index++) + { + if (s_edmaPrivateHandle[index].base == NULL) + { + s_edmaPrivateHandle[index].base = base; + s_edmaPrivateHandle[index].handle = handle; + break; + } + } + + if (index == (uint16_t)FLEXIO_SPI_HANDLE_COUNT) + { + return kStatus_OutOfRange; + } + + /* Set spi base to handle. */ + handle->txHandle = txHandle; + handle->rxHandle = rxHandle; + + /* Register callback and userData. */ + handle->callback = callback; + handle->userData = userData; + + /* Set SPI state to idle. */ + handle->txInProgress = false; + handle->rxInProgress = false; + + /* Install callback for Tx/Rx dma channel. */ + if (handle->txHandle != NULL) + { + EDMA_SetCallback(handle->txHandle, FLEXIO_SPI_TxEDMACallback, &s_edmaPrivateHandle[index]); + } + if (handle->rxHandle != NULL) + { + EDMA_SetCallback(handle->rxHandle, FLEXIO_SPI_RxEDMACallback, &s_edmaPrivateHandle[index]); + } + + return kStatus_Success; +} + +/*! + * brief Performs a non-blocking FlexIO SPI transfer using eDMA. + * + * note This interface returns immediately after transfer initiates. Call + * FLEXIO_SPI_MasterGetTransferCountEDMA to poll the transfer status and check + * whether the FlexIO SPI transfer is finished. + * + * param base Pointer to FLEXIO_SPI_Type structure. + * param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state. + * param xfer Pointer to FlexIO SPI transfer structure. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer. + */ +status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + assert(handle != NULL); + assert(xfer != NULL); + + uint32_t dataMode = 0; + uint16_t timerCmp = (uint16_t)base->flexioBase->TIMCMP[base->timerIndex[0]]; + uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags); + + timerCmp &= 0x00FFU; + + /* Check if the device is busy. */ + if ((handle->txInProgress) || (handle->rxInProgress)) + { + return kStatus_FLEXIO_SPI_Busy; + } + + /* Check if input parameter invalid. */ + if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + /* Timer1 controls the CS signal which enables/disables(asserts/deasserts) when timer0 enable/disable. Timer0 + enables when tx shifter is written and disables when timer compare. The timer compare event causes the + transmit shift registers to load which generates a tx register empty event. Since when timer stop bit is + disabled, a timer enable condition can be detected in the same cycle as a timer disable condition, so if + software writes the tx register upon the detection of tx register empty event, the timer enable condition + is triggered again, then the CS signal can remain low until software no longer writes the tx register. */ + if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U) + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) | + FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled); + } + else + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TSTOP_MASK) | + FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitEnableOnTimerDisable); + } + + /* configure data mode. */ + if ((dataFormat == (uint8_t)kFLEXIO_SPI_8bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_8bitLsb)) + { + dataMode = (8UL * 2UL - 1UL) << 8U; + } + else if ((dataFormat == (uint8_t)kFLEXIO_SPI_16bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_16bitLsb)) + { + dataMode = (16UL * 2UL - 1UL) << 8U; + } + else if ((dataFormat == (uint8_t)kFLEXIO_SPI_32bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_32bitLsb)) + { + dataMode = (32UL * 2UL - 1UL) << 8U; + } + else + { + dataMode = (8UL * 2UL - 1UL) << 8U; + } + + dataMode |= timerCmp; + + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + return FLEXIO_SPI_EDMAConfig(base, handle, xfer); +} + +/*! + * brief Gets the remaining bytes for FlexIO SPI eDMA transfer. + * + * param base Pointer to FLEXIO_SPI_Type structure. + * param handle FlexIO SPI eDMA handle pointer. + * param count Number of bytes transferred so far by the non-blocking transaction. + */ +status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + if (handle->rxInProgress) + { + *count = + (handle->transferSize - (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount( + handle->rxHandle->base, handle->rxHandle->channel)); + } + else + { + *count = + (handle->transferSize - (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount( + handle->txHandle->base, handle->txHandle->channel)); + } + + return kStatus_Success; +} + +/*! + * brief Aborts a FlexIO SPI transfer using eDMA. + * + * param base Pointer to FLEXIO_SPI_Type structure. + * param handle FlexIO SPI eDMA handle pointer. + */ +void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle) +{ + assert(handle != NULL); + + /* Disable dma. */ + EDMA_AbortTransfer(handle->txHandle); + EDMA_AbortTransfer(handle->rxHandle); + + /* Disable DMA enable bit. */ + FLEXIO_SPI_EnableDMA(base, (uint32_t)kFLEXIO_SPI_DmaAllEnable, false); + + /* Set the handle state. */ + handle->txInProgress = false; + handle->rxInProgress = false; +} + +/*! + * brief Performs a non-blocking FlexIO SPI transfer using eDMA. + * + * note This interface returns immediately after transfer initiates. Call + * FLEXIO_SPI_SlaveGetTransferCountEDMA to poll the transfer status and + * check whether the FlexIO SPI transfer is finished. + * + * param base Pointer to FLEXIO_SPI_Type structure. + * param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state. + * param xfer Pointer to FlexIO SPI transfer structure. + * retval kStatus_Success Successfully start a transfer. + * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer. + */ +status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base, + flexio_spi_slave_edma_handle_t *handle, + flexio_spi_transfer_t *xfer) +{ + assert(handle != NULL); + assert(xfer != NULL); + + uint32_t dataMode = 0U; + uint8_t dataFormat = FLEXIO_SPI_XFER_DATA_FORMAT(xfer->flags); + + /* Check if the device is busy. */ + if ((handle->txInProgress) || (handle->rxInProgress)) + { + return kStatus_FLEXIO_SPI_Busy; + } + + /* SCK timer use CS pin as inverted trigger so timer should be disbaled on trigger falling edge(CS re-asserts). */ + /* However if CPHA is first edge mode, timer will restart each time right after timer compare event occur and + before CS pin re-asserts, which triggers another shifter load. To avoid this, when in CS dis-continuous mode, + timer should disable in timer compare rather than trigger falling edge(CS re-asserts), and in CS continuous mode, + tx/rx shifters should be flushed after transfer finishes and before next transfer starts. */ + FLEXIO_SPI_FlushShifters(base); + if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U) + { + base->flexioBase->TIMCFG[base->timerIndex[0]] |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge); + } + else + { + if ((base->flexioBase->SHIFTCTL[base->shifterIndex[0]] & FLEXIO_SHIFTCTL_TIMPOL_MASK) == + FLEXIO_SHIFTCTL_TIMPOL(kFLEXIO_ShifterTimerPolarityOnNegitive)) + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) | + FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare); + } + else + { + base->flexioBase->TIMCFG[base->timerIndex[0]] = + (base->flexioBase->TIMCFG[base->timerIndex[0]] & ~FLEXIO_TIMCFG_TIMDIS_MASK) | + FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTriggerFallingEdge); + } + } + + /* Check if input parameter invalid. */ + if (((xfer->txData == NULL) && (xfer->rxData == NULL)) || (xfer->dataSize == 0U)) + { + return kStatus_InvalidArgument; + } + + /* configure data mode. */ + if ((dataFormat == (uint8_t)kFLEXIO_SPI_8bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_8bitLsb)) + { + dataMode = 8U * 2U - 1U; + } + else if ((dataFormat == (uint8_t)kFLEXIO_SPI_16bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_16bitLsb)) + { + dataMode = 16U * 2U - 1U; + } + else if ((dataFormat == (uint8_t)kFLEXIO_SPI_32bitMsb) || (dataFormat == (uint8_t)kFLEXIO_SPI_32bitLsb)) + { + dataMode = 32UL * 2UL - 1UL; + } + else + { + dataMode = 8U * 2U - 1U; + } + + base->flexioBase->TIMCMP[base->timerIndex[0]] = dataMode; + + return FLEXIO_SPI_EDMAConfig(base, handle, xfer); +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_spi_edma.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_spi_edma.h new file mode 100644 index 00000000000..7e98f199105 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_spi_edma.h @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020, 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_FLEXIO_SPI_EDMA_H_ +#define FSL_FLEXIO_SPI_EDMA_H_ + +#include "fsl_flexio_spi.h" +#include "fsl_edma.h" + +/*! + * @addtogroup flexio_edma_spi + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief FlexIO SPI EDMA driver version. */ +#define FSL_FLEXIO_SPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) +/*! @} */ + +/*! @brief typedef for flexio_spi_master_edma_handle_t in advance. */ +typedef struct _flexio_spi_master_edma_handle flexio_spi_master_edma_handle_t; + +/*! @brief Slave handle is the same with master handle. */ +typedef flexio_spi_master_edma_handle_t flexio_spi_slave_edma_handle_t; + +/*! @brief FlexIO SPI master callback for finished transmit */ +typedef void (*flexio_spi_master_edma_transfer_callback_t)(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief FlexIO SPI slave callback for finished transmit */ +typedef void (*flexio_spi_slave_edma_transfer_callback_t)(FLEXIO_SPI_Type *base, + flexio_spi_slave_edma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief FlexIO SPI eDMA transfer handle, users should not touch the content of the handle.*/ +struct _flexio_spi_master_edma_handle +{ + size_t transferSize; /*!< Total bytes to be transferred. */ + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + bool txInProgress; /*!< Send transfer in progress */ + bool rxInProgress; /*!< Receive transfer in progress */ + edma_handle_t *txHandle; /*!< DMA handler for SPI send */ + edma_handle_t *rxHandle; /*!< DMA handler for SPI receive */ + flexio_spi_master_edma_transfer_callback_t callback; /*!< Callback for SPI DMA transfer */ + void *userData; /*!< User Data for SPI DMA callback */ +}; + +/******************************************************************************* + * APIs + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA Transactional + * @{ + */ + +/*! + * @brief Initializes the FlexIO SPI master eDMA handle. + * + * This function initializes the FlexIO SPI master eDMA handle which can be used for other FlexIO SPI master + * transactional + * APIs. + * For a specified FlexIO SPI instance, call this API once to get the initialized handle. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state. + * @param callback SPI callback, NULL means no callback. + * @param userData callback function parameter. + * @param txHandle User requested eDMA handle for FlexIO SPI RX eDMA transfer. + * @param rxHandle User requested eDMA handle for FlexIO SPI TX eDMA transfer. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range. + */ +status_t FLEXIO_SPI_MasterTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + flexio_spi_master_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txHandle, + edma_handle_t *rxHandle); + +/*! + * @brief Performs a non-blocking FlexIO SPI transfer using eDMA. + * + * @note This interface returns immediately after transfer initiates. Call + * FLEXIO_SPI_MasterGetTransferCountEDMA to poll the transfer status and check + * whether the FlexIO SPI transfer is finished. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle Pointer to flexio_spi_master_edma_handle_t structure to store the transfer state. + * @param xfer Pointer to FlexIO SPI transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer. + */ +status_t FLEXIO_SPI_MasterTransferEDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + flexio_spi_transfer_t *xfer); + +/*! + * @brief Aborts a FlexIO SPI transfer using eDMA. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle FlexIO SPI eDMA handle pointer. + */ +void FLEXIO_SPI_MasterTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_master_edma_handle_t *handle); + +/*! + * @brief Gets the number of bytes transferred so far using FlexIO SPI master eDMA. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle FlexIO SPI eDMA handle pointer. + * @param count Number of bytes transferred so far by the non-blocking transaction. + */ +status_t FLEXIO_SPI_MasterTransferGetCountEDMA(FLEXIO_SPI_Type *base, + flexio_spi_master_edma_handle_t *handle, + size_t *count); + +/*! + * @brief Initializes the FlexIO SPI slave eDMA handle. + * + * This function initializes the FlexIO SPI slave eDMA handle. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state. + * @param callback SPI callback, NULL means no callback. + * @param userData callback function parameter. + * @param txHandle User requested eDMA handle for FlexIO SPI TX eDMA transfer. + * @param rxHandle User requested eDMA handle for FlexIO SPI RX eDMA transfer. + */ +static inline void FLEXIO_SPI_SlaveTransferCreateHandleEDMA(FLEXIO_SPI_Type *base, + flexio_spi_slave_edma_handle_t *handle, + flexio_spi_slave_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txHandle, + edma_handle_t *rxHandle) +{ + (void)FLEXIO_SPI_MasterTransferCreateHandleEDMA(base, handle, callback, userData, txHandle, rxHandle); +} + +/*! + * @brief Performs a non-blocking FlexIO SPI transfer using eDMA. + * + * @note This interface returns immediately after transfer initiates. Call + * FLEXIO_SPI_SlaveGetTransferCountEDMA to poll the transfer status and + * check whether the FlexIO SPI transfer is finished. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state. + * @param xfer Pointer to FlexIO SPI transfer structure. + * @retval kStatus_Success Successfully start a transfer. + * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_FLEXIO_SPI_Busy FlexIO SPI is not idle, is running another transfer. + */ +status_t FLEXIO_SPI_SlaveTransferEDMA(FLEXIO_SPI_Type *base, + flexio_spi_slave_edma_handle_t *handle, + flexio_spi_transfer_t *xfer); + +/*! + * @brief Aborts a FlexIO SPI transfer using eDMA. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle Pointer to flexio_spi_slave_edma_handle_t structure to store the transfer state. + */ +static inline void FLEXIO_SPI_SlaveTransferAbortEDMA(FLEXIO_SPI_Type *base, flexio_spi_slave_edma_handle_t *handle) +{ + FLEXIO_SPI_MasterTransferAbortEDMA(base, handle); +} + +/*! + * @brief Gets the number of bytes transferred so far using FlexIO SPI slave eDMA. + * + * @param base Pointer to FLEXIO_SPI_Type structure. + * @param handle FlexIO SPI eDMA handle pointer. + * @param count Number of bytes transferred so far by the non-blocking transaction. + */ +static inline status_t FLEXIO_SPI_SlaveTransferGetCountEDMA(FLEXIO_SPI_Type *base, + flexio_spi_slave_edma_handle_t *handle, + size_t *count) +{ + return FLEXIO_SPI_MasterTransferGetCountEDMA(base, handle, count); +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_uart.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_uart.c new file mode 100644 index 00000000000..13890caee7d --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_uart.c @@ -0,0 +1,1023 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_uart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_uart" +#endif + +/*flexioBase); +} + +static size_t FLEXIO_UART_TransferGetRxRingBufferLength(flexio_uart_handle_t *handle) +{ + size_t size; + uint16_t rxRingBufferHead = handle->rxRingBufferHead; + uint16_t rxRingBufferTail = handle->rxRingBufferTail; + + if (rxRingBufferTail > rxRingBufferHead) + { + size = (size_t)rxRingBufferHead + handle->rxRingBufferSize - (size_t)rxRingBufferTail; + } + else + { + size = (size_t)rxRingBufferHead - (size_t)rxRingBufferTail; + } + + return size; +} + +static bool FLEXIO_UART_TransferIsRxRingBufferFull(flexio_uart_handle_t *handle) +{ + bool full; + + if (FLEXIO_UART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + + return full; +} + +/*! + * brief Ungates the FlexIO clock, resets the FlexIO module, configures FlexIO UART + * hardware, and configures the FlexIO UART with FlexIO UART configuration. + * The configuration structure can be filled by the user or be set with + * default values by FLEXIO_UART_GetDefaultConfig(). + * + * Example + code + FLEXIO_UART_Type base = { + .flexioBase = FLEXIO, + .TxPinIndex = 0, + .RxPinIndex = 1, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_uart_config_t config = { + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 115200U, + .bitCountPerChar = 8 + }; + FLEXIO_UART_Init(base, &config, srcClock_Hz); + endcode + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param userConfig Pointer to the flexio_uart_config_t structure. + * param srcClock_Hz FlexIO source clock in Hz. + * retval kStatus_Success Configuration success. + * retval kStatus_FLEXIO_UART_BaudrateNotSupport Baudrate is not supported for current clock source frequency. +*/ +status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz) +{ + assert((base != NULL) && (userConfig != NULL)); + + flexio_shifter_config_t shifterConfig; + flexio_timer_config_t timerConfig; + uint32_t ctrlReg = 0; + uint16_t timerDiv = 0; + uint16_t timerCmp = 0; + uint32_t calculatedBaud; + uint32_t diff; + status_t result = kStatus_Success; + + /* Clear the shifterConfig & timerConfig struct. */ + (void)memset(&shifterConfig, 0, sizeof(shifterConfig)); + (void)memset(&timerConfig, 0, sizeof(timerConfig)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate flexio clock. */ + CLOCK_EnableClock(s_flexioClocks[FLEXIO_UART_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Configure FLEXIO UART */ + ctrlReg = base->flexioBase->CTRL; + ctrlReg &= ~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK); + ctrlReg |= (FLEXIO_CTRL_DBGE(userConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(userConfig->enableFastAccess) | + FLEXIO_CTRL_FLEXEN(userConfig->enableUart)); + if (!userConfig->enableInDoze) + { + ctrlReg |= FLEXIO_CTRL_DOZEN_MASK; + } + + base->flexioBase->CTRL = ctrlReg; + + /* Do hardware configuration. */ + /* 1. Configure the shifter 0 for tx. */ + shifterConfig.timerSelect = base->timerIndex[0]; + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutput; + shifterConfig.pinSelect = base->TxPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig); + + /*2. Configure the timer 0 for tx. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->TxPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveHigh; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetNever; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + + timerDiv = (uint16_t)(srcClock_Hz / userConfig->baudRate_Bps); + timerDiv = timerDiv / 2U - 1U; + + if (timerDiv > 0xFFU) + { + /* Check whether the calculated timerDiv is within allowed range. */ + return kStatus_FLEXIO_UART_BaudrateNotSupport; + } + else + { + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculated timerDiv value */ + calculatedBaud = srcClock_Hz / (((uint32_t)timerDiv + 1U) * 2U); + /* timerDiv cannot be larger than the ideal divider, so calculatedBaud is definitely larger + than configured baud */ + diff = calculatedBaud - userConfig->baudRate_Bps; + if (diff > ((userConfig->baudRate_Bps / 100U) * 3U)) + { + return kStatus_FLEXIO_UART_BaudrateNotSupport; + } + } + + timerCmp = ((uint16_t)userConfig->bitCountPerChar * 2U - 1U) << 8U; + timerCmp |= timerDiv; + + timerConfig.timerCompare = timerCmp; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig); + + /* 3. Configure the shifter 1 for rx. */ + shifterConfig.timerSelect = base->timerIndex[1]; + shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive; + shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + shifterConfig.pinSelect = base->RxPinIndex; + shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh; + shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive; + shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin; + shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh; + shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow; + + FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig); + + /* 4. Configure the timer 1 for rx. */ + timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_PININPUT(base->RxPinIndex); + timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveHigh; + timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceExternal; + timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled; + timerConfig.pinSelect = base->RxPinIndex; + timerConfig.pinPolarity = kFLEXIO_PinActiveLow; + timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit; + timerConfig.timerOutput = kFLEXIO_TimerOutputOneAffectedByReset; + timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput; + timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinRisingEdge; + timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare; + timerConfig.timerEnable = kFLEXIO_TimerEnableOnPinRisingEdge; + timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable; + timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled; + + timerConfig.timerCompare = timerCmp; + + FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig); + + return result; +} + +/*! + * brief Resets the FlexIO UART shifter and timer config. + * + * note After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module. + * + * param base Pointer to FLEXIO_UART_Type structure + */ +void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base) +{ + base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0; + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0; + base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0; + base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[0]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[0]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[0]] = 0; + base->flexioBase->TIMCFG[base->timerIndex[1]] = 0; + base->flexioBase->TIMCMP[base->timerIndex[1]] = 0; + base->flexioBase->TIMCTL[base->timerIndex[1]] = 0; + /* Clear the shifter flag. */ + base->flexioBase->SHIFTSTAT = (1UL << base->shifterIndex[0]); + base->flexioBase->SHIFTSTAT = (1UL << base->shifterIndex[1]); + /* Clear the timer flag. */ + base->flexioBase->TIMSTAT = (1UL << base->timerIndex[0]); + base->flexioBase->TIMSTAT = (1UL << base->timerIndex[1]); +} + +/*! + * brief Gets the default configuration to configure the FlexIO UART. The configuration + * can be used directly for calling the FLEXIO_UART_Init(). + * Example: + code + flexio_uart_config_t config; + FLEXIO_UART_GetDefaultConfig(&userConfig); + endcode + * param userConfig Pointer to the flexio_uart_config_t structure. +*/ +void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig) +{ + assert(userConfig != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(userConfig, 0, sizeof(*userConfig)); + + userConfig->enableUart = true; + userConfig->enableInDoze = false; + userConfig->enableInDebug = true; + userConfig->enableFastAccess = false; + /* Default baud rate 115200. */ + userConfig->baudRate_Bps = 115200U; + /* Default bit count at 8. */ + userConfig->bitCountPerChar = kFLEXIO_UART_8BitsPerChar; +} + +/*! + * brief Enables the FlexIO UART interrupt. + * + * This function enables the FlexIO UART interrupt. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param mask Interrupt source. + */ +void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask) +{ + if ((mask & (uint32_t)kFLEXIO_UART_TxDataRegEmptyInterruptEnable) != 0U) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[0]); + } + if ((mask & (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable) != 0U) + { + FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[1]); + } +} + +/*! + * brief Disables the FlexIO UART interrupt. + * + * This function disables the FlexIO UART interrupt. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param mask Interrupt source. + */ +void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask) +{ + if ((mask & (uint32_t)kFLEXIO_UART_TxDataRegEmptyInterruptEnable) != 0U) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[0]); + } + if ((mask & (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable) != 0U) + { + FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1UL << base->shifterIndex[1]); + } +} + +/*! + * brief Gets the FlexIO UART status flags. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * return FlexIO UART status flags. + */ + +uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base) +{ + uint32_t status = 0U; + status = + ((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0])) >> base->shifterIndex[0]); + status |= + (((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[1])) >> (base->shifterIndex[1])) + << 1U); + status |= + (((FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1UL << base->shifterIndex[1])) >> (base->shifterIndex[1])) + << 2U); + return status; +} + +/*! + * brief Gets the FlexIO UART status flags. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param mask Status flag. + * The parameter can be any combination of the following values: + * arg kFLEXIO_UART_TxDataRegEmptyFlag + * arg kFLEXIO_UART_RxEmptyFlag + * arg kFLEXIO_UART_RxOverRunFlag + */ + +void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask) +{ + if ((mask & (uint32_t)kFLEXIO_UART_TxDataRegEmptyFlag) != 0U) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1UL << base->shifterIndex[0]); + } + if ((mask & (uint32_t)kFLEXIO_UART_RxDataRegFullFlag) != 0U) + { + FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1UL << base->shifterIndex[1]); + } + if ((mask & (uint32_t)kFLEXIO_UART_RxOverRunFlag) != 0U) + { + FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1UL << base->shifterIndex[1]); + } +} + +/*! + * brief Sends a buffer of data bytes. + * + * note This function blocks using the polling method until all bytes have been sent. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param txData The data bytes to send. + * param txSize The number of data bytes to send. + * retval kStatus_FLEXIO_UART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully wrote all data. + */ +status_t FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize) +{ + assert(txData != NULL); + assert(txSize != 0U); +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != txSize--) + { + /* Wait until data transfer complete. */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) && + (0U != --waitTimes)) +#else + while (0U == (FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1UL << base->shifterIndex[0]))) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_FLEXIO_UART_Timeout; + } +#endif + + base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = *txData++; + } + return kStatus_Success; +} + +/*! + * brief Receives a buffer of bytes. + * + * note This function blocks using the polling method until all bytes have been received. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param rxData The buffer to store the received bytes. + * param rxSize The number of data bytes to be received. + * retval kStatus_FLEXIO_UART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully received all data. + */ +status_t FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize) +{ + assert(rxData != NULL); + assert(rxSize != 0U); +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != rxSize--) + { + /* Wait until data transfer complete. */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (FLEXIO_UART_GetStatusFlags(base) & (uint32_t)kFLEXIO_UART_RxDataRegFullFlag)) && + (0U != --waitTimes)) +#else + while (0U == (FLEXIO_UART_GetStatusFlags(base) & (uint32_t)kFLEXIO_UART_RxDataRegFullFlag)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_FLEXIO_UART_Timeout; + } +#endif + + *rxData++ = (uint8_t)(base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]); + } + return kStatus_Success; +} + +/*! + * brief Initializes the UART handle. + * + * This function initializes the FlexIO UART handle, which can be used for other FlexIO + * UART transactional APIs. Call this API once to get the + * initialized handle. + * + * The UART driver supports the "background" receiving, which means that users can set up + * a RX ring buffer optionally. Data received is stored into the ring buffer even when + * the user doesn't call the FLEXIO_UART_TransferReceiveNonBlocking() API. If there is already data + * received in the ring buffer, users can get the received data from the ring buffer + * directly. The ring buffer is disabled if passing NULL as p ringBuffer. + * + * param base to FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * param callback The callback function. + * param userData The parameter of the callback function. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + IRQn_Type flexio_irqs[] = FLEXIO_IRQS; + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Set the TX/RX state. */ + handle->rxState = (uint8_t)kFLEXIO_UART_RxIdle; + handle->txState = (uint8_t)kFLEXIO_UART_TxIdle; + + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + + /* Clear pending NVIC IRQ before enable NVIC IRQ. */ + NVIC_ClearPendingIRQ(flexio_irqs[FLEXIO_UART_GetInstance(base)]); + /* Enable interrupt in NVIC. */ + (void)EnableIRQ(flexio_irqs[FLEXIO_UART_GetInstance(base)]); + + /* Save the context in global variables to support the double weak mechanism. */ + return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_UART_TransferHandleIRQ); +} + +/*! + * brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_ReceiveNonBlocking() API. If there is already data received + * in the ring buffer, users can get the received data from the ring buffer directly. + * + * note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if p ringBufferSize is 32, only 31 bytes are used for saving data. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * param ringBufferSize Size of the ring buffer. + */ +void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize) +{ + assert(handle != NULL); + + /* Setup the ringbuffer address */ + if (ringBuffer != NULL) + { + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + + /* Enable the interrupt to accept the data when user need the ring buffer. */ + FLEXIO_UART_EnableInterrupts(base, (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable); + } +} + +/*! + * brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle) +{ + assert(handle != NULL); + + if (handle->rxState == (uint8_t)kFLEXIO_UART_RxIdle) + { + FLEXIO_UART_DisableInterrupts(base, (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable); + } + + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +/*! + * brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, + * which returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in ISR, the FlexIO UART driver calls the callback + * function and passes the ref kStatus_FLEXIO_UART_TxIdle as status parameter. + * + * note The kStatus_FLEXIO_UART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However, it does not ensure that all data is sent out. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * param xfer FlexIO UART transfer structure. See #flexio_uart_transfer_t. + * retval kStatus_Success Successfully starts the data transmission. + * retval kStatus_UART_TxBusy Previous transmission still not finished, data not written to the TX register. + */ +status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_t *xfer) +{ + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->txData)) + { + return kStatus_InvalidArgument; + } + + /* Return error if current TX busy. */ + if ((uint8_t)kFLEXIO_UART_TxBusy == handle->txState) + { + status = kStatus_FLEXIO_UART_TxBusy; + } + else + { + handle->txData = xfer->txData; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = (uint8_t)kFLEXIO_UART_TxBusy; + + /* Enable transmiter interrupt. */ + FLEXIO_UART_EnableInterrupts(base, (uint32_t)kFLEXIO_UART_TxDataRegEmptyInterruptEnable); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt-driven data sending. Get the remainBytes to find out + * how many bytes are still not sent out. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle) +{ + /* Disable the transmitter and disable the interrupt. */ + FLEXIO_UART_DisableInterrupts(base, (uint32_t)kFLEXIO_UART_TxDataRegEmptyInterruptEnable); + + handle->txDataSize = 0U; + handle->txState = (uint8_t)kFLEXIO_UART_TxIdle; +} + +/*! + * brief Gets the number of bytes sent. + * + * This function gets the number of bytes sent driven by interrupt. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * param count Number of bytes sent so far by the non-blocking transaction. + * retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + assert(count != NULL); + + if ((uint8_t)kFLEXIO_UART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - handle->txDataSize; + + return kStatus_Success; +} + +/*! + * brief Receives a buffer of data using the interrupt method. + * + * This function receives data using the interrupt method. This is a non-blocking function, + * which returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in ring buffer is copied and + * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in ring buffer is not enough to read, the receive + * request is saved by the UART driver. When new data arrives, the receive request + * is serviced first. When all data is received, the UART driver notifies the upper layer + * through a callback function and passes the status parameter ref kStatus_UART_RxIdle. + * For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer, + * the 5 bytes are copied to xfer->data. This function returns with the + * parameter p receivedBytes set to 5. For the last 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * param xfer UART transfer structure. See #flexio_uart_transfer_t. + * param receivedBytes Bytes received from the ring buffer directly. + * retval kStatus_Success Successfully queue the transfer into the transmit queue. + * retval kStatus_FLEXIO_UART_RxBusy Previous receive request is not finished. + */ +status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_t *xfer, + size_t *receivedBytes) +{ + uint32_t i; + status_t status; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->rxData)) + { + return kStatus_InvalidArgument; + } + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to uart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to uart handle, receive data + to this empty space and trigger callback when finished. */ + + if ((uint8_t)kFLEXIO_UART_RxBusy == handle->rxState) + { + status = kStatus_FLEXIO_UART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0U; + + /* If RX ring buffer is used. */ + if (handle->rxRingBuffer != NULL) + { + /* Disable FLEXIO_UART RX IRQ, protect ring buffer. */ + FLEXIO_UART_DisableInterrupts(base, (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = FLEXIO_UART_TransferGetRxRingBufferLength(handle); + + if (bytesToCopy != 0U) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + + bytesToReceive -= bytesToCopy; + + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->rxData[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if ((uint32_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + + /* If ring buffer does not have enough data, still need to read more data. */ + if (bytesToReceive != 0U) + { + /* No data in ring buffer, save the request to UART handle. */ + handle->rxData = xfer->rxData + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = xfer->dataSize; + handle->rxState = (uint8_t)kFLEXIO_UART_RxBusy; + } + + /* Enable FLEXIO_UART RX IRQ if previously enabled. */ + FLEXIO_UART_EnableInterrupts(base, (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable); + + /* Call user callback since all data are received. */ + if (0U == bytesToReceive) + { + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_FLEXIO_UART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + handle->rxData = xfer->rxData + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = (uint8_t)kFLEXIO_UART_RxBusy; + + /* Enable RX interrupt. */ + FLEXIO_UART_EnableInterrupts(base, (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable); + } + + /* Return the how many bytes have read. */ + if (receivedBytes != NULL) + { + *receivedBytes = bytesCurrentReceived; + } + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the receive data which was using IRQ. + * + * This function aborts the receive data which was using IRQ. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle) +{ + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (NULL == handle->rxRingBuffer) + { + /* Disable RX interrupt. */ + FLEXIO_UART_DisableInterrupts(base, (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable); + } + + handle->rxDataSize = 0U; + handle->rxState = (uint8_t)kFLEXIO_UART_RxIdle; +} + +/*! + * brief Gets the number of bytes received. + * + * This function gets the number of bytes received driven by interrupt. + * + * param base Pointer to the FLEXIO_UART_Type structure. + * param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * param count Number of bytes received so far by the non-blocking transaction. + * retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + assert(count != NULL); + + if ((uint8_t)kFLEXIO_UART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - handle->rxDataSize; + + return kStatus_Success; +} + +/*! + * brief FlexIO UART IRQ handler function. + * + * This function processes the FlexIO UART transmit and receives the IRQ request. + * + * param uartType Pointer to the FLEXIO_UART_Type structure. + * param uartHandle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle) +{ + uint8_t count = 1; + FLEXIO_UART_Type *base = (FLEXIO_UART_Type *)uartType; + flexio_uart_handle_t *handle = (flexio_uart_handle_t *)uartHandle; + uint16_t rxRingBufferHead; + + /* Read the status back. */ + uint32_t status = FLEXIO_UART_GetStatusFlags(base); + + /* If RX overrun. */ + if (((uint32_t)kFLEXIO_UART_RxOverRunFlag & status) != 0U) + { + /* Clear Overrun flag. */ + FLEXIO_UART_ClearStatusFlags(base, (uint32_t)kFLEXIO_UART_RxOverRunFlag); + + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_FLEXIO_UART_RxHardwareOverrun, handle->userData); + } + } + + /* Receive data register full */ + if ((((uint32_t)kFLEXIO_UART_RxDataRegFullFlag & status) != 0U) && + ((base->flexioBase->SHIFTSIEN & (1UL << base->shifterIndex[1])) != 0U)) + { + /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ + if (handle->rxDataSize != 0U) + { + /* Using non block API to read the data from the registers. */ + FLEXIO_UART_ReadByte(base, handle->rxData); + handle->rxDataSize--; + handle->rxData++; + count--; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (0U == handle->rxDataSize) + { + handle->rxState = (uint8_t)kFLEXIO_UART_RxIdle; + + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_FLEXIO_UART_RxIdle, handle->userData); + } + } + } + + if (handle->rxRingBuffer != NULL) + { + if (count != 0U) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (FLEXIO_UART_TransferIsRxRingBufferFull(handle)) + { + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_FLEXIO_UART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overridden. */ + if (FLEXIO_UART_TransferIsRxRingBufferFull(handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if ((uint32_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + + /* Read data. */ + rxRingBufferHead = handle->rxRingBufferHead; + handle->rxRingBuffer[rxRingBufferHead] = + (uint8_t)(base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]); + + /* Increase handle->rxRingBufferHead. */ + if ((uint32_t)handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + /* If no receive requst pending, stop RX interrupt. */ + else if (0U == handle->rxDataSize) + { + FLEXIO_UART_DisableInterrupts(base, (uint32_t)kFLEXIO_UART_RxDataRegFullInterruptEnable); + } + else + { + } + } + + /* Send data register empty and the interrupt is enabled. */ + if ((((uint32_t)kFLEXIO_UART_TxDataRegEmptyFlag & status) != 0U) && + ((base->flexioBase->SHIFTSIEN & (1UL << base->shifterIndex[0])) != 0U)) + { + if (handle->txDataSize != 0U) + { + /* Using non block API to write the data to the registers. */ + FLEXIO_UART_WriteByte(base, handle->txData); + handle->txData++; + handle->txDataSize--; + + /* If all the data are written to data register, TX finished. */ + if (0U == handle->txDataSize) + { + handle->txState = (uint8_t)kFLEXIO_UART_TxIdle; + + /* Disable TX register empty interrupt. */ + FLEXIO_UART_DisableInterrupts(base, (uint32_t)kFLEXIO_UART_TxDataRegEmptyInterruptEnable); + + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_FLEXIO_UART_TxIdle, handle->userData); + } + } + } + } +} + +/*! + * brief Flush tx/rx shifters. + * + * param base Pointer to the FLEXIO_UART_Type structure. + */ +void FLEXIO_UART_FlushShifters(FLEXIO_UART_Type *base) +{ + /* Disable then re-enable to flush the tx shifter. */ + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] &= ~FLEXIO_SHIFTCTL_SMOD_MASK; + base->flexioBase->SHIFTCTL[base->shifterIndex[0]] |= FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit); + /* Read to flush the rx shifter. */ + (void)base->flexioBase->SHIFTBUF[base->shifterIndex[1]]; +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_uart.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_uart.h new file mode 100644 index 00000000000..d6f36bf3235 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_uart.h @@ -0,0 +1,588 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_FLEXIO_UART_H_ +#define FSL_FLEXIO_UART_H_ + +#include "fsl_common.h" +#include "fsl_flexio.h" + +/*! + * @addtogroup flexio_uart + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief FlexIO UART driver version. */ +#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 5, 0)) +/*! @} */ + +/*! @brief Retry times for waiting flag. */ +#ifndef UART_RETRY_TIMES +#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */ +#endif + +/*! @brief Error codes for the UART driver. */ +enum +{ + kStatus_FLEXIO_UART_TxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 0), /*!< Transmitter is busy. */ + kStatus_FLEXIO_UART_RxBusy = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 1), /*!< Receiver is busy. */ + kStatus_FLEXIO_UART_TxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 2), /*!< UART transmitter is idle. */ + kStatus_FLEXIO_UART_RxIdle = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 3), /*!< UART receiver is idle. */ + kStatus_FLEXIO_UART_ERROR = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 4), /*!< ERROR happens on UART. */ + kStatus_FLEXIO_UART_RxRingBufferOverrun = + MAKE_STATUS(kStatusGroup_FLEXIO_UART, 5), /*!< UART RX software ring buffer overrun. */ + kStatus_FLEXIO_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 6), /*!< UART RX receiver overrun. */ + kStatus_FLEXIO_UART_Timeout = MAKE_STATUS(kStatusGroup_FLEXIO_UART, 7), /*!< UART times out. */ + kStatus_FLEXIO_UART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_FLEXIO_UART, 8) /*!< Baudrate is not supported in current clock source */ +}; + +/*! @brief FlexIO UART bit count per char. */ +typedef enum _flexio_uart_bit_count_per_char +{ + kFLEXIO_UART_7BitsPerChar = 7U, /*!< 7-bit data characters */ + kFLEXIO_UART_8BitsPerChar = 8U, /*!< 8-bit data characters */ + kFLEXIO_UART_9BitsPerChar = 9U, /*!< 9-bit data characters */ +} flexio_uart_bit_count_per_char_t; + +/*! @brief Define FlexIO UART interrupt mask. */ +enum _flexio_uart_interrupt_enable +{ + kFLEXIO_UART_TxDataRegEmptyInterruptEnable = 0x1U, /*!< Transmit buffer empty interrupt enable. */ + kFLEXIO_UART_RxDataRegFullInterruptEnable = 0x2U, /*!< Receive buffer full interrupt enable. */ +}; + +/*! @brief Define FlexIO UART status mask. */ +enum _flexio_uart_status_flags +{ + kFLEXIO_UART_TxDataRegEmptyFlag = 0x1U, /*!< Transmit buffer empty flag. */ + kFLEXIO_UART_RxDataRegFullFlag = 0x2U, /*!< Receive buffer full flag. */ + kFLEXIO_UART_RxOverRunFlag = 0x4U, /*!< Receive buffer over run flag. */ +}; + +/*! @brief Define FlexIO UART access structure typedef. */ +typedef struct _flexio_uart_type +{ + FLEXIO_Type *flexioBase; /*!< FlexIO base pointer. */ + uint8_t TxPinIndex; /*!< Pin select for UART_Tx. */ + uint8_t RxPinIndex; /*!< Pin select for UART_Rx. */ + uint8_t shifterIndex[2]; /*!< Shifter index used in FlexIO UART. */ + uint8_t timerIndex[2]; /*!< Timer index used in FlexIO UART. */ +} FLEXIO_UART_Type; + +/*! @brief Define FlexIO UART user configuration structure. */ +typedef struct _flexio_uart_config +{ + bool enableUart; /*!< Enable/disable FlexIO UART TX & RX. */ + bool enableInDoze; /*!< Enable/disable FlexIO operation in doze mode*/ + bool enableInDebug; /*!< Enable/disable FlexIO operation in debug mode*/ + bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers, + fast access requires the FlexIO clock to be at least + twice the frequency of the bus clock. */ + uint32_t baudRate_Bps; /*!< Baud rate in Bps. */ + flexio_uart_bit_count_per_char_t bitCountPerChar; /*!< number of bits, 7/8/9 -bit */ +} flexio_uart_config_t; + +/*! @brief Define FlexIO UART transfer structure. */ +typedef struct _flexio_uart_transfer +{ + /* + * Use separate TX and RX data pointer, because TX data is const data. + * The member data is kept for backward compatibility. + */ + union + { + uint8_t *data; /*!< The buffer of data to be transfer.*/ + uint8_t *rxData; /*!< The buffer to receive data. */ + const uint8_t *txData; /*!< The buffer of data to be sent. */ + }; + size_t dataSize; /*!< Transfer size*/ +} flexio_uart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _flexio_uart_handle flexio_uart_handle_t; + +/*! @brief FlexIO UART transfer callback function. */ +typedef void (*flexio_uart_transfer_callback_t)(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + status_t status, + void *userData); + +/*! @brief Define FLEXIO UART handle structure*/ +struct _flexio_uart_handle +{ + const uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t txDataSizeAll; /*!< Total bytes to be sent. */ + size_t rxDataSizeAll; /*!< Total bytes to be received. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + flexio_uart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the FlexIO clock, resets the FlexIO module, configures FlexIO UART + * hardware, and configures the FlexIO UART with FlexIO UART configuration. + * The configuration structure can be filled by the user or be set with + * default values by FLEXIO_UART_GetDefaultConfig(). + * + * Example + @code + FLEXIO_UART_Type base = { + .flexioBase = FLEXIO, + .TxPinIndex = 0, + .RxPinIndex = 1, + .shifterIndex = {0,1}, + .timerIndex = {0,1} + }; + flexio_uart_config_t config = { + .enableInDoze = false, + .enableInDebug = true, + .enableFastAccess = false, + .baudRate_Bps = 115200U, + .bitCountPerChar = 8 + }; + FLEXIO_UART_Init(base, &config, srcClock_Hz); + @endcode + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param userConfig Pointer to the flexio_uart_config_t structure. + * @param srcClock_Hz FlexIO source clock in Hz. + * @retval kStatus_Success Configuration success. + * @retval kStatus_FLEXIO_UART_BaudrateNotSupport Baudrate is not supported for current clock source frequency. +*/ +status_t FLEXIO_UART_Init(FLEXIO_UART_Type *base, const flexio_uart_config_t *userConfig, uint32_t srcClock_Hz); + +/*! + * @brief Resets the FlexIO UART shifter and timer config. + * + * @note After calling this API, call the FLEXO_UART_Init to use the FlexIO UART module. + * + * @param base Pointer to FLEXIO_UART_Type structure + */ +void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base); + +/*! + * @brief Gets the default configuration to configure the FlexIO UART. The configuration + * can be used directly for calling the FLEXIO_UART_Init(). + * Example: + @code + flexio_uart_config_t config; + FLEXIO_UART_GetDefaultConfig(&userConfig); + @endcode + * @param userConfig Pointer to the flexio_uart_config_t structure. +*/ +void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig); + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the FlexIO UART status flags. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @return FlexIO UART status flags. + */ + +uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base); + +/*! + * @brief Gets the FlexIO UART status flags. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param mask Status flag. + * The parameter can be any combination of the following values: + * @arg kFLEXIO_UART_TxDataRegEmptyFlag + * @arg kFLEXIO_UART_RxEmptyFlag + * @arg kFLEXIO_UART_RxOverRunFlag + */ + +void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask); + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the FlexIO UART interrupt. + * + * This function enables the FlexIO UART interrupt. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param mask Interrupt source. + */ +void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask); + +/*! + * @brief Disables the FlexIO UART interrupt. + * + * This function disables the FlexIO UART interrupt. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param mask Interrupt source. + */ +void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask); + +/*! @} */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Gets the FlexIO UARt transmit data register address. + * + * This function returns the UART data register address, which is mainly used by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @return FlexIO UART transmit data register address. + */ +static inline uint32_t FLEXIO_UART_GetTxDataRegisterAddress(FLEXIO_UART_Type *base) +{ + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBuffer, base->shifterIndex[0]); +} + +/*! + * @brief Gets the FlexIO UART receive data register address. + * + * This function returns the UART data register address, which is mainly used by DMA/eDMA. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @return FlexIO UART receive data register address. + */ +static inline uint32_t FLEXIO_UART_GetRxDataRegisterAddress(FLEXIO_UART_Type *base) +{ + return FLEXIO_GetShifterBufferAddress(base->flexioBase, kFLEXIO_ShifterBufferByteSwapped, base->shifterIndex[1]); +} + +/*! + * @brief Enables/disables the FlexIO UART transmit DMA. + * This function enables/disables the FlexIO UART Tx DMA, + * which means asserting the kFLEXIO_UART_TxDataRegEmptyFlag does/doesn't trigger the DMA request. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param enable True to enable, false to disable. + */ +static inline void FLEXIO_UART_EnableTxDMA(FLEXIO_UART_Type *base, bool enable) +{ + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL << base->shifterIndex[0], enable); +} + +/*! + * @brief Enables/disables the FlexIO UART receive DMA. + * This function enables/disables the FlexIO UART Rx DMA, + * which means asserting kFLEXIO_UART_RxDataRegFullFlag does/doesn't trigger the DMA request. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param enable True to enable, false to disable. + */ +static inline void FLEXIO_UART_EnableRxDMA(FLEXIO_UART_Type *base, bool enable) +{ + FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL << base->shifterIndex[1], enable); +} + +/*! @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables/disables the FlexIO UART module operation. + * + * @param base Pointer to the FLEXIO_UART_Type. + * @param enable True to enable, false does not have any effect. + */ +static inline void FLEXIO_UART_Enable(FLEXIO_UART_Type *base, bool enable) +{ + if (enable) + { + base->flexioBase->CTRL |= FLEXIO_CTRL_FLEXEN_MASK; + } +} + +/*! + * @brief Writes one byte of data. + * + * @note This is a non-blocking API, which returns directly after the data is put into the + * data register. Ensure that the TxEmptyFlag is asserted before calling + * this API. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param buffer The data bytes to send. + */ +static inline void FLEXIO_UART_WriteByte(FLEXIO_UART_Type *base, const uint8_t *buffer) +{ + base->flexioBase->SHIFTBUF[base->shifterIndex[0]] = *buffer; +} + +/*! + * @brief Reads one byte of data. + * + * @note This is a non-blocking API, which returns directly after the data is read from the + * data register. Ensure that the RxFullFlag is asserted before calling this API. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param buffer The buffer to store the received bytes. + */ +static inline void FLEXIO_UART_ReadByte(FLEXIO_UART_Type *base, uint8_t *buffer) +{ + *buffer = (uint8_t)(base->flexioBase->SHIFTBUFBYS[base->shifterIndex[1]]); +} + +/*! + * @brief Sends a buffer of data bytes. + * + * @note This function blocks using the polling method until all bytes have been sent. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param txData The data bytes to send. + * @param txSize The number of data bytes to send. + * @retval kStatus_FLEXIO_UART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully wrote all data. + */ +status_t FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData, size_t txSize); + +/*! + * @brief Receives a buffer of bytes. + * + * @note This function blocks using the polling method until all bytes have been received. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param rxData The buffer to store the received bytes. + * @param rxSize The number of data bytes to be received. + * @retval kStatus_FLEXIO_UART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully received all data. + */ +status_t FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize); + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the UART handle. + * + * This function initializes the FlexIO UART handle, which can be used for other FlexIO + * UART transactional APIs. Call this API once to get the + * initialized handle. + * + * The UART driver supports the "background" receiving, which means that users can set up + * a RX ring buffer optionally. Data received is stored into the ring buffer even when + * the user doesn't call the FLEXIO_UART_TransferReceiveNonBlocking() API. If there is already data + * received in the ring buffer, users can get the received data from the ring buffer + * directly. The ring buffer is disabled if passing NULL as @p ringBuffer. + * + * @param base to FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range. + */ +status_t FLEXIO_UART_TransferCreateHandle(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_callback_t callback, + void *userData); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_ReceiveNonBlocking() API. If there is already data received + * in the ring buffer, users can get the received data from the ring buffer directly. + * + * @note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, only 31 bytes are used for saving data. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize Size of the ring buffer. + */ +void FLEXIO_UART_TransferStartRingBuffer(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferStopRingBuffer(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, + * which returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in ISR, the FlexIO UART driver calls the callback + * function and passes the @ref kStatus_FLEXIO_UART_TxIdle as status parameter. + * + * @note The kStatus_FLEXIO_UART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However, it does not ensure that all data is sent out. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param xfer FlexIO UART transfer structure. See #flexio_uart_transfer_t. + * @retval kStatus_Success Successfully starts the data transmission. + * @retval kStatus_UART_TxBusy Previous transmission still not finished, data not written to the TX register. + */ +status_t FLEXIO_UART_TransferSendNonBlocking(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_t *xfer); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt-driven data sending. Get the remainBytes to find out + * how many bytes are still not sent out. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferAbortSend(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle); + +/*! + * @brief Gets the number of bytes sent. + * + * This function gets the number of bytes sent driven by interrupt. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param count Number of bytes sent so far by the non-blocking transaction. + * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetSendCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count); + +/*! + * @brief Receives a buffer of data using the interrupt method. + * + * This function receives data using the interrupt method. This is a non-blocking function, + * which returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in ring buffer is not enough to read, the receive + * request is saved by the UART driver. When new data arrives, the receive request + * is serviced first. When all data is received, the UART driver notifies the upper layer + * through a callback function and passes the status parameter kStatus_UART_RxIdle. + * For example, if the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer, + * the 5 bytes are copied to xfer->data. This function returns with the + * parameter @p receivedBytes set to 5. For the last 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param xfer UART transfer structure. See #flexio_uart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into the transmit queue. + * @retval kStatus_FLEXIO_UART_RxBusy Previous receive request is not finished. + */ +status_t FLEXIO_UART_TransferReceiveNonBlocking(FLEXIO_UART_Type *base, + flexio_uart_handle_t *handle, + flexio_uart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the receive data which was using IRQ. + * + * This function aborts the receive data which was using IRQ. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferAbortReceive(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle); + +/*! + * @brief Gets the number of bytes received. + * + * This function gets the number of bytes received driven by interrupt. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + * @param handle Pointer to the flexio_uart_handle_t structure to store the transfer state. + * @param count Number of bytes received so far by the non-blocking transaction. + * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart_handle_t *handle, size_t *count); + +/*! + * @brief FlexIO UART IRQ handler function. + * + * This function processes the FlexIO UART transmit and receives the IRQ request. + * + * @param uartType Pointer to the FLEXIO_UART_Type structure. + * @param uartHandle Pointer to the flexio_uart_handle_t structure to store the transfer state. + */ +void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle); + +/*! + * @brief Flush tx/rx shifters. + * + * @param base Pointer to the FLEXIO_UART_Type structure. + */ +void FLEXIO_UART_FlushShifters(FLEXIO_UART_Type *base); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /*_cplusplus*/ +/*! @} */ + +#endif /*FSL_FLEXIO_UART_H_*/ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_uart_edma.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_uart_edma.c new file mode 100644 index 00000000000..f2502c9df20 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_uart_edma.c @@ -0,0 +1,407 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexio_uart_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexio_uart_edma" +#endif + +/*handle != NULL); + + /* Avoid the warning for unused variables. */ + handle = handle; + tcds = tcds; + + if (transferDone) + { + FLEXIO_UART_TransferAbortSendEDMA(uartPrivateHandle->base, uartPrivateHandle->handle); + + if (uartPrivateHandle->handle->callback != NULL) + { + uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, + kStatus_FLEXIO_UART_TxIdle, uartPrivateHandle->handle->userData); + } + } +} + +static void FLEXIO_UART_TransferReceiveEDMACallback(edma_handle_t *handle, + void *param, + bool transferDone, + uint32_t tcds) +{ + flexio_uart_edma_private_handle_t *uartPrivateHandle = (flexio_uart_edma_private_handle_t *)param; + + assert(uartPrivateHandle->handle != NULL); + + /* Avoid the warning for unused variables. */ + handle = handle; + tcds = tcds; + + if (transferDone) + { + /* Disable transfer. */ + FLEXIO_UART_TransferAbortReceiveEDMA(uartPrivateHandle->base, uartPrivateHandle->handle); + + if (uartPrivateHandle->handle->callback != NULL) + { + uartPrivateHandle->handle->callback(uartPrivateHandle->base, uartPrivateHandle->handle, + kStatus_FLEXIO_UART_RxIdle, uartPrivateHandle->handle->userData); + } + } +} + +/*! + * brief Initializes the UART handle which is used in transactional functions. + * + * param base Pointer to FLEXIO_UART_Type. + * param handle Pointer to flexio_uart_edma_handle_t structure. + * param callback The callback function. + * param userData The parameter of the callback function. + * param rxEdmaHandle User requested DMA handle for RX DMA transfer. + * param txEdmaHandle User requested DMA handle for TX DMA transfer. + * retval kStatus_Success Successfully create the handle. + * retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range. + */ +status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + flexio_uart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle) +{ + assert(handle != NULL); + + uint8_t index = 0U; + + /* Find the an empty handle pointer to store the handle. */ + for (index = 0U; index < (uint8_t)FLEXIO_UART_HANDLE_COUNT; index++) + { + if (s_edmaPrivateHandle[index].base == NULL) + { + s_edmaPrivateHandle[index].base = base; + s_edmaPrivateHandle[index].handle = handle; + break; + } + } + + if (index == (uint8_t)FLEXIO_UART_HANDLE_COUNT) + { + return kStatus_OutOfRange; + } + + (void)memset(handle, 0, sizeof(*handle)); + + handle->rxState = (uint8_t)kFLEXIO_UART_RxIdle; + handle->txState = (uint8_t)kFLEXIO_UART_TxIdle; + + handle->rxEdmaHandle = rxEdmaHandle; + handle->txEdmaHandle = txEdmaHandle; + + handle->callback = callback; + handle->userData = userData; + + /* Configure TX. */ + if (txEdmaHandle != NULL) + { + EDMA_SetCallback(handle->txEdmaHandle, FLEXIO_UART_TransferSendEDMACallback, &s_edmaPrivateHandle); + } + + /* Configure RX. */ + if (rxEdmaHandle != NULL) + { + EDMA_SetCallback(handle->rxEdmaHandle, FLEXIO_UART_TransferReceiveEDMACallback, &s_edmaPrivateHandle); + } + + return kStatus_Success; +} + +/*! + * brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent out, the send callback function is called. + * + * param base Pointer to FLEXIO_UART_Type + * param handle UART handle pointer. + * param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_FLEXIO_UART_TxBusy Previous transfer on going. + */ +status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + flexio_uart_transfer_t *xfer) +{ + assert(handle->txEdmaHandle != NULL); + + edma_transfer_config_t xferConfig; + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* If previous TX not finished. */ + if ((uint8_t)kFLEXIO_UART_TxBusy == handle->txState) + { + status = kStatus_FLEXIO_UART_TxBusy; + } + else + { + handle->txState = (uint8_t)kFLEXIO_UART_TxBusy; + handle->txDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), + (uint32_t *)FLEXIO_UART_GetTxDataRegisterAddress(base), sizeof(uint8_t), sizeof(uint8_t), + xfer->dataSize, kEDMA_MemoryToPeripheral); + + /* Store the initially configured eDMA minor byte transfer count into the FLEXIO UART handle */ + handle->nbytes = 1U; + + /* Submit transfer. */ + (void)EDMA_SubmitTransfer(handle->txEdmaHandle, &xferConfig); + EDMA_StartTransfer(handle->txEdmaHandle); + + /* Enable UART TX EDMA. */ + FLEXIO_UART_EnableTxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Receives data using eDMA. + * + * This function receives data using eDMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * param base Pointer to FLEXIO_UART_Type + * param handle Pointer to flexio_uart_edma_handle_t structure + * param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_UART_RxBusy Previous transfer on going. + */ +status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + flexio_uart_transfer_t *xfer) +{ + assert(handle->rxEdmaHandle != NULL); + + edma_transfer_config_t xferConfig; + status_t status; + + /* Return error if xfer invalid. */ + if ((0U == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* If previous RX not finished. */ + if ((uint8_t)kFLEXIO_UART_RxBusy == handle->rxState) + { + status = kStatus_FLEXIO_UART_RxBusy; + } + else + { + handle->rxState = (uint8_t)kFLEXIO_UART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, (uint32_t *)FLEXIO_UART_GetRxDataRegisterAddress(base), sizeof(uint8_t), + xfer->data, sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory); + + /* Store the initially configured eDMA minor byte transfer count into the FLEXIO UART handle */ + handle->nbytes = (uint8_t)sizeof(uint8_t); + + /* Submit transfer. */ + (void)EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig); + EDMA_StartTransfer(handle->rxEdmaHandle); + + /* Enable UART RX EDMA. */ + FLEXIO_UART_EnableRxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the sent data which using eDMA. + * + * This function aborts sent data which using eDMA. + * + * param base Pointer to FLEXIO_UART_Type + * param handle Pointer to flexio_uart_edma_handle_t structure + */ +void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle) +{ + assert(handle->txEdmaHandle != NULL); + + /* Disable UART TX EDMA. */ + FLEXIO_UART_EnableTxDMA(base, false); + + /* Stop transfer. */ + EDMA_StopTransfer(handle->txEdmaHandle); + + handle->txState = (uint8_t)kFLEXIO_UART_TxIdle; +} + +/*! + * brief Aborts the receive data which using eDMA. + * + * This function aborts the receive data which using eDMA. + * + * param base Pointer to FLEXIO_UART_Type + * param handle Pointer to flexio_uart_edma_handle_t structure + */ +void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle) +{ + assert(handle->rxEdmaHandle != NULL); + + /* Disable UART RX EDMA. */ + FLEXIO_UART_EnableRxDMA(base, false); + + /* Stop transfer. */ + EDMA_StopTransfer(handle->rxEdmaHandle); + + handle->rxState = (uint8_t)kFLEXIO_UART_RxIdle; +} + +/*! + * brief Gets the number of bytes received. + * + * This function gets the number of bytes received. + * + * param base Pointer to FLEXIO_UART_Type + * param handle Pointer to flexio_uart_edma_handle_t structure + * param count Number of bytes received so far by the non-blocking transaction. + * retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + size_t *count) +{ + assert(handle != NULL); + assert(handle->rxEdmaHandle != NULL); + assert(count != NULL); + + if ((uint8_t)kFLEXIO_UART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel); + + return kStatus_Success; +} + +/*! + * brief Gets the number of bytes sent out. + * + * This function gets the number of bytes sent out. + * + * param base Pointer to FLEXIO_UART_Type + * param handle Pointer to flexio_uart_edma_handle_t structure + * param count Number of bytes sent so far by the non-blocking transaction. + * retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + assert(handle->txEdmaHandle != NULL); + assert(count != NULL); + + if ((uint8_t)kFLEXIO_UART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - + (uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel); + + return kStatus_Success; +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_uart_edma.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_uart_edma.h new file mode 100644 index 00000000000..c8d0a04369b --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_flexio_uart_edma.h @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_FLEXIO_UART_EDMA_H_ +#define FSL_FLEXIO_UART_EDMA_H_ + +#include "fsl_flexio_uart.h" +#include "fsl_edma.h" + +/*! + * @addtogroup flexio_edma_uart + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief FlexIO UART EDMA driver version. */ +#define FSL_FLEXIO_UART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 1)) +/*! @} */ + +/* Forward declaration of the handle typedef. */ +typedef struct _flexio_uart_edma_handle flexio_uart_edma_handle_t; + +/*! @brief UART transfer callback function. */ +typedef void (*flexio_uart_edma_transfer_callback_t)(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief UART eDMA handle + */ +struct _flexio_uart_edma_handle +{ + flexio_uart_edma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< UART callback function parameter.*/ + + size_t txDataSizeAll; /*!< Total bytes to be sent. */ + size_t rxDataSizeAll; /*!< Total bytes to be received. */ + + edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */ + edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */ + + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA transactional + * @{ + */ + +/*! + * @brief Initializes the UART handle which is used in transactional functions. + * + * @param base Pointer to FLEXIO_UART_Type. + * @param handle Pointer to flexio_uart_edma_handle_t structure. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @param rxEdmaHandle User requested DMA handle for RX DMA transfer. + * @param txEdmaHandle User requested DMA handle for TX DMA transfer. + * @retval kStatus_Success Successfully create the handle. + * @retval kStatus_OutOfRange The FlexIO SPI eDMA type/handle table out of range. + */ +status_t FLEXIO_UART_TransferCreateHandleEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + flexio_uart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle); + +/*! + * @brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent out, the send callback function is called. + * + * @param base Pointer to FLEXIO_UART_Type + * @param handle UART handle pointer. + * @param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_FLEXIO_UART_TxBusy Previous transfer on going. + */ +status_t FLEXIO_UART_TransferSendEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + flexio_uart_transfer_t *xfer); + +/*! + * @brief Receives data using eDMA. + * + * This function receives data using eDMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base Pointer to FLEXIO_UART_Type + * @param handle Pointer to flexio_uart_edma_handle_t structure + * @param xfer UART eDMA transfer structure, see #flexio_uart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_UART_RxBusy Previous transfer on going. + */ +status_t FLEXIO_UART_TransferReceiveEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + flexio_uart_transfer_t *xfer); + +/*! + * @brief Aborts the sent data which using eDMA. + * + * This function aborts sent data which using eDMA. + * + * @param base Pointer to FLEXIO_UART_Type + * @param handle Pointer to flexio_uart_edma_handle_t structure + */ +void FLEXIO_UART_TransferAbortSendEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle); + +/*! + * @brief Aborts the receive data which using eDMA. + * + * This function aborts the receive data which using eDMA. + * + * @param base Pointer to FLEXIO_UART_Type + * @param handle Pointer to flexio_uart_edma_handle_t structure + */ +void FLEXIO_UART_TransferAbortReceiveEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle); + +/*! + * @brief Gets the number of bytes sent out. + * + * This function gets the number of bytes sent out. + * + * @param base Pointer to FLEXIO_UART_Type + * @param handle Pointer to flexio_uart_edma_handle_t structure + * @param count Number of bytes sent so far by the non-blocking transaction. + * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetSendCountEDMA(FLEXIO_UART_Type *base, flexio_uart_edma_handle_t *handle, size_t *count); + +/*! + * @brief Gets the number of bytes received. + * + * This function gets the number of bytes received. + * + * @param base Pointer to FLEXIO_UART_Type + * @param handle Pointer to flexio_uart_edma_handle_t structure + * @param count Number of bytes received so far by the non-blocking transaction. + * @retval kStatus_NoTransferInProgress transfer has finished or no transfer in progress. + * @retval kStatus_Success Successfully return the count. + */ +status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base, + flexio_uart_edma_handle_t *handle, + size_t *count); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_UART_EDMA_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_freqme.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_freqme.c new file mode 100644 index 00000000000..459bbb6f3a0 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_freqme.c @@ -0,0 +1,155 @@ +/* + * Copyright 2021-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_freqme.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_freqme" +#endif + +#if defined(FREQME_RSTS_N) +#define FREQME_RESETS_ARRAY FREQME_RSTS_N +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static uint32_t FREQME_GetInstance(FREQME_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Array to map freqme instance number to base address. */ +static FREQME_Type *const s_freqmeBases[] = FREQME_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to FREQME clocks for each instance. */ +static const clock_ip_name_t s_freqmeClocks[] = FREQME_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FREQME_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_freqmeResets[] = FREQME_RESETS_ARRAY; +#endif +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t FREQME_GetInstance(FREQME_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0U; instance < ARRAY_SIZE(s_freqmeBases); instance++) + { + if (s_freqmeBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_freqmeBases)); + + return instance; +} + +/*! + * brief Initialize freqme module, set operate mode, operate mode attribute and initialize measurement cycle. + * + * param base FREQME peripheral base address. + * param config The pointer to module basic configuration, please refer to freq_measure_config_t. + */ +void FREQME_Init(FREQME_Type *base, const freq_measure_config_t *config) +{ + assert(config); + + uint32_t tmp32 = 0UL; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable FREQME clock. */ + CLOCK_EnableClock(s_freqmeClocks[FREQME_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(FREQME_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_freqmeResets[FREQME_GetInstance(base)]); +#endif + + if (config->startMeasurement) + { + tmp32 |= FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK; + } + tmp32 |= FREQME_CTRL_W_CONTINUOUS_MODE_EN(config->enableContinuousMode) | + FREQME_CTRL_W_PULSE_MODE(config->operateMode); + if (config->operateMode == kFREQME_FreqMeasurementMode) + { + tmp32 |= FREQME_CTRL_W_REF_SCALE(config->operateModeAttribute.refClkScaleFactor); + } + else + { + tmp32 |= FREQME_CTRL_W_PULSE_POL(config->operateModeAttribute.pulsePolarity); + } + + base->CTRL_W = tmp32; +} + +/*! + * brief Get default configuration. + * + * code + * config->operateMode = kFREQME_FreqMeasurementMode; + * config->operateModeAttribute.refClkScaleFactor = 0U; + * config->enableContinuousMode = false; + * config->startMeasurement = false; + * endcode + * + * param config The pointer to module basic configuration, please refer to freq_measure_config_t. + */ +void FREQME_GetDefaultConfig(freq_measure_config_t *config) +{ + assert(config); + + (void)memset(config, 0, sizeof(*config)); + + config->operateMode = kFREQME_FreqMeasurementMode; + config->operateModeAttribute.refClkScaleFactor = 0U; + config->enableContinuousMode = false; + config->startMeasurement = false; +} + +/*! + * brief Calculate the frequency of selected target clock. + * + * note The formula: Ftarget = (RESULT - 2) * Freference / 2 ^ REF_SCALE. + * + * note This function only useful when the operate mode is selected as frequency measurement mode. + * + * param base FREQME peripheral base address. + * param refClkFrequency The frequency of reference clock. + * return The frequency of target clock, if the output result is 0, please check the module's operate mode. + */ +uint32_t FREQME_CalculateTargetClkFreq(FREQME_Type *base, uint32_t refClkFrequency) +{ + uint32_t measureResult = 0UL; + uint32_t targetFreq = 0UL; + uint64_t tmp64 = 0ULL; + + while ((base->CTRL_R & FREQME_CTRL_R_MEASURE_IN_PROGRESS_MASK) != 0UL) + { + } + + if (!FREQME_CheckOperateMode(base)) + { + measureResult = base->CTRL_R & FREQME_CTRL_R_RESULT_MASK; + tmp64 = ((uint64_t)measureResult - 2ULL) * (uint64_t)refClkFrequency; + targetFreq = (uint32_t)(tmp64 / (1ULL << (uint64_t)FREQME_GetReferenceClkScaleValue(base))); + } + + return targetFreq; +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_freqme.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_freqme.h new file mode 100644 index 00000000000..dd1ee29d668 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_freqme.h @@ -0,0 +1,441 @@ +/* + * Copyright 2021-2022 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_FREQME_H_ +#define FSL_FREQME_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpc_freqme + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief FREQME driver version 2.1.2. */ +#define FSL_FREQME_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) +/*! @} */ + +/*! + * @brief The enumeration of interrupt status flags. + * @anchor _freqme_interrupt_status_flags + */ +enum _freqme_interrupt_status_flags +{ + kFREQME_UnderflowInterruptStatusFlag = FREQME_CTRLSTAT_LT_MIN_STAT_MASK, /*!< Indicate the measurement is + just done and the result is less + than minimun value. */ + kFREQME_OverflowInterruptStatusFlag = FREQME_CTRLSTAT_GT_MAX_STAT_MASK, /*!< Indicate the measurement is + just done and the result is greater + than maximum value. */ + kFREQME_ReadyInterruptStatusFlag = FREQME_CTRLSTAT_RESULT_READY_STAT_MASK, /*!< Indicate the measurement is + just done and the result is ready to + read. */ + kFREQME_AllInterruptStatusFlags = FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_GT_MAX_STAT_MASK | + FREQME_CTRLSTAT_RESULT_READY_STAT_MASK, /*!< All interrupt + status flags. */ +}; + +/*! + * @brief The enumeration of interrupts, including underflow interrupt, overflow interrupt, + * and result ready interrupt. + * @anchor _freqme_interrupt_enable + */ +enum _freqme_interrupt_enable +{ + kFREQME_UnderflowInterruptEnable = FREQME_CTRL_W_LT_MIN_INT_EN_MASK, /*!< Enable interrupt when the result is + less than minimum value. */ + kFREQME_OverflowInterruptEnable = FREQME_CTRL_W_GT_MAX_INT_EN_MASK, /*!< Enable interrupt when the result is + greater than maximum value. */ + kFREQME_ReadyInterruptEnable = FREQME_CTRL_W_RESULT_READY_INT_EN_MASK, /*!< Enable interrupt when a + measurement completes and the result + is ready. */ +}; + +/*! + * @brief FREQME module operate mode enumeration, including frequency measurement mode + * and pulse width measurement mode. + */ +typedef enum _freqme_operate_mode +{ + kFREQME_FreqMeasurementMode = 0U, /*!< The module works in the frequency measurement mode. */ + kFREOME_PulseWidthMeasurementMode, /*!< The module works in the pulse width measurement mode. */ +} freqme_operate_mode_t; + +/*! + * @brief The enumeration of pulse polarity. + */ +typedef enum _freqme_pulse_polarity +{ + kFREQME_PulseHighPeriod = 0U, /*!< Select high period of the reference clock. */ + kFREQME_PulseLowPeriod, /*!< Select low period of the reference clock. */ +} freqme_pulse_polarity_t; + +/*! + * @brief The union of operate mode attribute. + * @note If the operate mode is selected as frequency measurement mode the member \b refClkScaleFactor should be used, + * if the operate mode is selected as pulse width measurement mode the member \b pulsePolarity should be used. + */ +typedef union _freqme_mode_attribute +{ + uint8_t refClkScaleFactor; /*!< Only useful in frequency measurement operate mode, + used to set the reference clock counter scaling factor. */ + freqme_pulse_polarity_t pulsePolarity; /*!< Only Useful in pulse width measurement operate mode, + used to set period polarity. */ +} freqme_mode_attribute_t; + +/*! + * @brief The structure of freqme module basic configuration, + * including operate mode, operate mode attribute and so on. + */ +typedef struct _freq_measure_config +{ + freqme_operate_mode_t operateMode; /*!< Select operate mode, please refer to @ref freqme_operate_mode_t. */ + freqme_mode_attribute_t operateModeAttribute; /*!< Used to set the attribute of the selected operate mode, if + the operate mode is selected as @ref kFREQME_FreqMeasurementMode + set freqme_mode_attribute_t::refClkScaleFactor, if operate mode is + selected as @ref kFREOME_PulseWidthMeasurementMode, please set + freqme_mode_attribute_t::pulsePolarity. */ + + bool enableContinuousMode; /*!< Enable/disable continuous mode, if continuous mode is enable, + the measurement is performed continuously and the result for the + last completed measurement is available in the result register. */ + bool startMeasurement; +} freq_measure_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Basic Control APIs + * @{ + */ +/*! + * @brief Initialize freqme module, set operate mode, operate mode attribute and initialize measurement cycle. + * + * @param base FREQME peripheral base address. + * @param config The pointer to module basic configuration, please refer to @ref freq_measure_config_t. + */ +void FREQME_Init(FREQME_Type *base, const freq_measure_config_t *config); + +/*! + * @brief Get default configuration. + * + * @code + * config->operateMode = kFREQME_FreqMeasurementMode; + * config->operateModeAttribute.refClkScaleFactor = 0U; + * config->enableContinuousMode = false; + * config->startMeasurement = false; + * @endcode + * + * @param config The pointer to module basic configuration, please refer to @ref freq_measure_config_t. + */ +void FREQME_GetDefaultConfig(freq_measure_config_t *config); + +/*! + * @brief Start frequency or pulse width measurement process. + * + * @param base FREQME peripheral base address. + */ +static inline void FREQME_StartMeasurementCycle(FREQME_Type *base) +{ + uint32_t tmp32; + + tmp32 = base->CTRLSTAT; + tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK | + FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK); + tmp32 |= FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK; + base->CTRL_W = tmp32; +} + +/*! + * @brief Force the termination of any measurement cycle currently in progress and resets RESULT or just reset + * RESULT if the module in idle state. + * + * @param base FREQME peripheral base address. + */ +static inline void FREQME_TerminateMeasurementCycle(FREQME_Type *base) +{ + uint32_t tmp32; + + tmp32 = base->CTRLSTAT; + tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_MEASURE_IN_PROGRESS_MASK | + FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK); + base->CTRL_W = tmp32; +} + +/*! + * @brief Enable/disable Continuous mode. + * + * @param base FREQME peripheral base address. + * @param enable Used to enable/disable continuous mode, + * - \b true Enable Continuous mode. + * - \b false Disable Continuous mode. + */ +static inline void FREQME_EnableContinuousMode(FREQME_Type *base, bool enable) +{ + uint32_t tmp32; + + tmp32 = base->CTRLSTAT; + tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK | + FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK); + if (enable) + { + tmp32 |= FREQME_CTRL_W_CONTINUOUS_MODE_EN_MASK; + } + + base->CTRL_W = tmp32; +} + +/*! + * @brief Check whether continuous mode is enabled. + * + * @param base FREQME peripheral base address. + * @retval True Continuous mode is enabled, the measurement is performed continuously. + * @retval False Continuous mode is disabled. + */ +static inline bool FREQME_CheckContinuousMode(FREQME_Type *base) +{ + return (bool)((base->CTRLSTAT & FREQME_CTRLSTAT_CONTINUOUS_MODE_EN_MASK) != 0UL); +} + +/*! + * @brief Set operate mode of freqme module. + * + * @param base FREQME peripheral base address. + * @param operateMode The operate mode to be set, please refer to @ref freqme_operate_mode_t. + */ +static inline void FREQME_SetOperateMode(FREQME_Type *base, freqme_operate_mode_t operateMode) +{ + uint32_t tmp32; + + tmp32 = base->CTRLSTAT; + tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_PULSE_MODE_MASK | + FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK); + if (operateMode == kFREOME_PulseWidthMeasurementMode) + { + tmp32 |= FREQME_CTRL_W_PULSE_MODE_MASK; + } + + base->CTRL_W = tmp32; +} + +/*! + * @brief Check module's operate mode. + * + * @param base FREQME peripheral base address. + * @retval True Pulse width measurement mode. + * @retval False Frequency measurement mode. + */ +static inline bool FREQME_CheckOperateMode(FREQME_Type *base) +{ + return (bool)((base->CTRLSTAT & FREQME_CTRLSTAT_PULSE_MODE_MASK) != 0UL); + +} + +/*! + * @brief Set the minimum expected value for the measurement result. + * + * @param base FREQME peripheral base address. + * @param minValue The minimum value to set, please note that this value is 31 bits width. + */ +static inline void FREQME_SetMinExpectedValue(FREQME_Type *base, uint32_t minValue) +{ + base->MIN = minValue; +} + +/*! + * @brief Set the maximum expected value for the measurement result. + * + * @param base FREQME peripheral base address. + * @param maxValue The maximum value to set, please note that this value is 31 bits width. + */ +static inline void FREQME_SetMaxExpectedValue(FREQME_Type *base, uint32_t maxValue) +{ + base->MAX = maxValue; +} + +/*! @} */ + +/*! + * @name Frequency Measurement Mode Control APIs + * @{ + */ + +/*! + * @brief Calculate the frequency of selected target clock。 + * + * @note The formula: Ftarget = (RESULT - 2) * Freference / 2 ^ REF_SCALE. + * + * @note This function only useful when the operate mode is selected as frequency measurement mode. + * + * @param base FREQME peripheral base address. + * @param refClkFrequency The frequency of reference clock. + * @return The frequency of target clock the unit is Hz, if the output result is 0, please check the module's + * operate mode. + */ +uint32_t FREQME_CalculateTargetClkFreq(FREQME_Type *base, uint32_t refClkFrequency); + +/*! + * @brief Get reference clock scaling factor. + * + * @param base FREQME peripheral base address. + * @return Reference clock scaling factor, the reference count cycle is 2 ^ ref_scale. + */ +static inline uint8_t FREQME_GetReferenceClkScaleValue(FREQME_Type *base) +{ + return (uint8_t)(base->CTRLSTAT & FREQME_CTRLSTAT_REF_SCALE_MASK); +} + +/*! @} */ + +/*! + * @name Pulse Width Measurement Mode Control APIs + * @{ + */ + +/*! + * @brief Set pulse polarity when operate mode is selected as Pulse Width Measurement mode. + * + * @param base FREQME peripheral base address. + * @param pulsePolarity The pulse polarity to be set, please refer to @ref freqme_pulse_polarity_t. + */ +static inline void FREQME_SetPulsePolarity(FREQME_Type *base, freqme_pulse_polarity_t pulsePolarity) +{ + uint32_t tmp32; + + tmp32 = base->CTRLSTAT; + tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_PULSE_POL_MASK | + FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK); + + if (pulsePolarity != kFREQME_PulseHighPeriod) + { + tmp32 |= FREQME_CTRL_W_PULSE_POL_MASK; + } + + base->CTRL_W = tmp32; +} + +/*! + * @brief Check pulse polarity when the operate mode is selected as pulse width measurement mode. + * + * @param base FREQME peripheral base address. + * @retval True Low period. + * @retval False High period. + */ +static inline bool FREQME_CheckPulsePolarity(FREQME_Type *base) +{ + return (bool)((base->CTRLSTAT & FREQME_CTRLSTAT_PULSE_POL_MASK) != 0UL); +} + +/*! + * @brief Get measurement result, if operate mode is selected as pulse width measurement mode this function can + * be used to calculate pulse width. + * + * @note Pulse width = counter result / Frequency of target clock. + * + * @param base FREQME peripheral base address. + * @return Measurement result. + */ +static inline uint32_t FREQME_GetMeasurementResult(FREQME_Type *base) +{ + return base->CTRL_R & FREQME_CTRL_R_RESULT_MASK; +} + +/*! @} */ + +/*! + * @name Status Control APIs + * @{ + */ + +/*! + * @brief Get interrupt status flags, such as overflow interrupt status flag, + * underflow interrupt status flag, and so on. + * + * @param base FREQME peripheral base address. + * @return Current interrupt status flags, should be the OR'ed value of @ref _freqme_interrupt_status_flags. + */ +static inline uint32_t FREQME_GetInterruptStatusFlags(FREQME_Type *base) +{ + return (base->CTRLSTAT & (uint32_t)kFREQME_AllInterruptStatusFlags); +} + +/*! + * @brief Clear interrupt status flags. + * + * @param base FREQME peripheral base address. + * @param statusFlags The combination of interrupt status flags to clear, + * should be the OR'ed value of @ref _freqme_interrupt_status_flags. + */ +static inline void FREQME_ClearInterruptStatusFlags(FREQME_Type *base, uint32_t statusFlags) +{ + base->CTRLSTAT |= statusFlags; +} + +/*! @} */ + +/*! + * @name Interrupt Control APIs + * @{ + */ + +/*! + * @brief Enable interrupts, such as result ready interrupt, overflow interrupt and so on. + * + * @param base FREQME peripheral base address. + * @param masks The mask of interrupts to enable, should be the OR'ed value of @ref _freqme_interrupt_enable. + */ +static inline void FREQME_EnableInterrupts(FREQME_Type *base, uint32_t masks) +{ + uint32_t tmp32; + + tmp32 = base->CTRLSTAT; + tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_LT_MIN_INT_EN_MASK | + FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_GT_MAX_INT_EN_MASK | + FREQME_CTRLSTAT_RESULT_READY_INT_EN_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK); + + tmp32 |= masks; + base->CTRL_W = tmp32; +} + +/*! + * @brief Disable interrupts, such as result ready interrupt, overflow interrupt and so on. + * + * @param base FREQME peripheral base address. + * @param masks The mask of interrupts to disable, should be the OR'ed value of @ref _freqme_interrupt_enable. + */ +static inline void FREQME_DisableInterrupts(FREQME_Type *base, uint32_t masks) +{ + uint32_t tmp32; + + tmp32 = base->CTRLSTAT; + tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_GT_MAX_STAT_MASK | + FREQME_CTRLSTAT_RESULT_READY_STAT_MASK | masks); + + base->CTRL_W = tmp32; +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* FSL_FREQME_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_glikey.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_glikey.c new file mode 100644 index 00000000000..ee585b8077d --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_glikey.c @@ -0,0 +1,403 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_glikey.h" + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.glikey" +#endif + +#define GLIKEY_SFR_LOCK 0x05u +#define GLIKEY_SFR_UNLOCK 0x0Au + +/* Define to select between write to CTRL0_WR_0 or CTRL1_WR_1 */ +#define WR_EN0 (0x0Fu) +#define WR_EN1 (0xF0u) + +#define WR_EN0_VALUE_SHIFT (0u) +#define WR_EN1_VALUE_SHIFT (16u) + +#define CTRL_SEL_CODEWORD_SHIFT (24u) + +#define WR_0_INIT (0x2u) +#define WR_1_INIT (0x0u) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static inline void Glikey_Internal_Set_WR_0(GLIKEY_Type *base, uint32_t value); +static inline void Glikey_Internal_Set_WR_1(GLIKEY_Type *base, uint32_t value); +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * Weak implementation of GLIKEY IRQ, should be re-defined by user when using GLIKEY IRQ + +__WEAK void GLIKEY0_DriverIRQHandler(void) +{ + GLIKEY generates IRQ until corresponding bit in STATUS is cleared by calling + GLIKEY_ClearStatusFlags(); +} +*/ + +static inline void Glikey_Internal_Set_WR_0(GLIKEY_Type *base, uint32_t value) +{ + uint32_t ctrl0 = ((GLIKEY_Type *)base)->CTRL_0; + + /* Clear WR_0 */ + ctrl0 = ctrl0 & (~GLIKEY_CTRL_0_WR_EN_0_MASK); + + /* Assign value */ + ((GLIKEY_Type *)base)->CTRL_0 = ctrl0 | GLIKEY_CTRL_0_WR_EN_0(value); +} + +static inline void Glikey_Internal_Set_WR_1(GLIKEY_Type *base, uint32_t value) +{ + uint32_t ctrl1 = ((GLIKEY_Type *)base)->CTRL_1; + + /* Clear WR_1 */ + ctrl1 = ctrl1 & (~GLIKEY_CTRL_1_WR_EN_1_MASK); + + /* Assign value */ + ((GLIKEY_Type *)base)->CTRL_1 = ctrl1 | GLIKEY_CTRL_1_WR_EN_1(value); +} + +uint32_t GLIKEY_GetStatus(GLIKEY_Type *base) +{ + return ((GLIKEY_Type *)base)->STATUS; +} + +status_t GLIKEY_IsLocked(GLIKEY_Type *base) +{ + status_t retCode = GLIKEY_CheckLock(base); + if (kStatus_GLIKEY_NotLocked == retCode) + { + return kStatus_GLIKEY_NotLocked; + } + else + { + return kStatus_GLIKEY_Locked; + } +} + +status_t GLIKEY_CheckLock(GLIKEY_Type *base) +{ + uint32_t sfrLock = (((GLIKEY_Type *)base)->CTRL_1 & GLIKEY_CTRL_1_SFR_LOCK_MASK) >> GLIKEY_CTRL_1_SFR_LOCK_SHIFT; + + if (GLIKEY_SFR_UNLOCK != sfrLock) /* Locked */ + { + return kStatus_GLIKEY_LockedError; + } + + return kStatus_GLIKEY_NotLocked; +} + +#if defined(GLIKEY_VERSION_FSM_CONFIG) +status_t GLIKEY_GetVersion(GLIKEY_Type *base, uint32_t *result) +{ + *result = ((GLIKEY_Type *)base)->VERSION; + + return kStatus_Success; +} +#endif + +status_t GLIKEY_SyncReset(GLIKEY_Type *base) +{ + status_t retCode = GLIKEY_CheckLock(base); + if (kStatus_GLIKEY_NotLocked != retCode) + { + return retCode; + } + + /* Set CTRL_0.SFT_RST = 1 */ + ((GLIKEY_Type *)base)->CTRL_0 |= GLIKEY_CTRL_0_SFT_RST_MASK; + + return kStatus_Success; +} + +status_t GLIKEY_SetIntEnable(GLIKEY_Type *base, uint32_t value) +{ + status_t retCode = GLIKEY_CheckLock(base); + if (kStatus_GLIKEY_NotLocked != retCode) + { + return retCode; + } + + ((GLIKEY_Type *)base)->INTR_CTRL = GLIKEY_INTR_CTRL_INT_EN(value); + + return kStatus_Success; +} + +status_t GLIKEY_GetIntEnable(GLIKEY_Type *base, uint32_t *value) +{ + *value = ((GLIKEY_Type *)base)->INTR_CTRL & GLIKEY_INTR_CTRL_INT_EN_MASK; + + return kStatus_Success; +} + +status_t GLIKEY_ClearIntStatus(GLIKEY_Type *base) +{ + status_t retCode = GLIKEY_CheckLock(base); + if (kStatus_GLIKEY_NotLocked != retCode) + { + return retCode; + } + + ((GLIKEY_Type *)base)->INTR_CTRL |= GLIKEY_INTR_CTRL_INT_CLR_MASK; + + return kStatus_Success; +} + +status_t GLIKEY_SetIntStatus(GLIKEY_Type *base) +{ + status_t retCode = GLIKEY_CheckLock(base); + if (kStatus_GLIKEY_NotLocked != retCode) + { + return retCode; + } + + ((GLIKEY_Type *)base)->INTR_CTRL |= GLIKEY_INTR_CTRL_INT_SET_MASK; + + return kStatus_Success; +} + +status_t GLIKEY_Lock(GLIKEY_Type *base) +{ + /* Check if SFR_LOCK is locked */ + status_t retCode = GLIKEY_CheckLock(base); + if (kStatus_GLIKEY_NotLocked != retCode) /* Glikey is not locked -> lock */ + { + uint32_t ctrl1 = ((GLIKEY_Type *)base)->CTRL_1; + /* Clear SFR_LOCK */ + ctrl1 = ctrl1 & (~GLIKEY_CTRL_1_SFR_LOCK_MASK); + /* Lock Gliekey */ + ((GLIKEY_Type *)base)->CTRL_1 = ctrl1 | GLIKEY_CTRL_1_SFR_LOCK(GLIKEY_SFR_LOCK); + } + + return kStatus_Success; +} + +status_t GLIKEY_IsIndexLocked(GLIKEY_Type *base, uint32_t index) +{ + /* Set CTRL_1.READ_INDEX = index */ + uint32_t ctr1Val = ((GLIKEY_Type *)base)->CTRL_1; + /* Clear READ_INDEX */ + ctr1Val = ctr1Val & (~GLIKEY_CTRL_1_READ_INDEX_MASK); + /* Set index value */ + ((GLIKEY_Type *)base)->CTRL_1 = ctr1Val | GLIKEY_CTRL_1_READ_INDEX(index); + + /* Check ERROR_STATUS */ + if (0u != (GLIKEY_GetStatus(base) & GLIKEY_STATUS_ERROR_STATUS_MASK)) + { + return kStatus_Fail; + } + + /* Check if STATUS.LOCK_STATUS is 0 */ + if (0u == (GLIKEY_GetStatus(base) & GLIKEY_STATUS_LOCK_STATUS_MASK)) + { + return kStatus_GLIKEY_NotLocked; + } + else + { + return kStatus_GLIKEY_Locked; + } +} + +status_t GLIKEY_LockIndex(GLIKEY_Type *base) +{ + /* Check if Glikey SFR locked */ + status_t retCode = GLIKEY_CheckLock(base); + if (kStatus_GLIKEY_NotLocked != retCode) + { + return retCode; + } + + /* Check if FSM is in WR_EN state */ + uint32_t state = (GLIKEY_GetStatus(base) & GLIKEY_STATUS_FSM_STATE_MASK) >> GLIKEY_STATUS_FSM_STATE_SHIFT; + if (GLIKEY_FSM_WR_EN == state) + { + /* Set WR_EN0 = b11 */ + ((GLIKEY_Type *)base)->CTRL_0 |= GLIKEY_CTRL_0_WR_EN_0(0x3u); + return kStatus_GLIKEY_Locked; + } + else + { + return kStatus_GLIKEY_DisabledError; + } +} + +status_t GLIKEY_StartEnable(GLIKEY_Type *base, uint32_t index) +{ + /* Check if Glikey SFR locked */ + status_t retCode = GLIKEY_CheckLock(base); + if (kStatus_GLIKEY_NotLocked != retCode) + { + return retCode; + } + + /* Check if index is locked */ + retCode = GLIKEY_IsIndexLocked(base, index); + if (kStatus_GLIKEY_NotLocked != retCode) + { + return retCode; + } + + /* CTRL0 */ + uint32_t ctrl0 = ((GLIKEY_Type *)base)->CTRL_0; + /* Clear old index */ + ctrl0 = ctrl0 & (~GLIKEY_CTRL_0_WRITE_INDEX_MASK); + /* Clear old CTRL0.WR_EN_0 */ + ctrl0 = ctrl0 & (~GLIKEY_CTRL_0_WR_EN_0_MASK); + /* Set new index */ + ctrl0 |= GLIKEY_CTRL_0_WRITE_INDEX(index); + + /* Start the enable process by writting 0x01 to CTRL0.WR_EN_0 */ + ctrl0 = ctrl0 | ((uint32_t)0x01u << GLIKEY_CTRL_0_WR_EN_0_SHIFT); + + /* Write to CTRL0 (new index and WR_EN_0 = 0x01) */ + ((GLIKEY_Type *)base)->CTRL_0 = ctrl0; + + /* CTRL1 */ + uint32_t ctrl1 = ((GLIKEY_Type *)base)->CTRL_1; + /* Clear CTRL1.WR_EN_1 */ + ctrl1 &= ~GLIKEY_CTRL_1_WR_EN_1_MASK; + ((GLIKEY_Type*)base)->CTRL_1 = ctrl1; + + return kStatus_Success; +} + +status_t GLIKEY_ContinueEnable(GLIKEY_Type *base, uint32_t codeword) +{ + /* Check if Glikey SFR locked */ + status_t retCode = GLIKEY_CheckLock(base); + if (kStatus_GLIKEY_NotLocked != retCode) + { + return retCode; + } + + /* Set correctly we_en0 and wr_en1 according to codeword */ + /* Select between CTRL0/CTRL1 */ + if (WR_EN1 == (codeword >> CTRL_SEL_CODEWORD_SHIFT)) + { + Glikey_Internal_Set_WR_1(base, codeword >> WR_EN1_VALUE_SHIFT); + } + else if (WR_EN0 == (codeword >> CTRL_SEL_CODEWORD_SHIFT)) + { + Glikey_Internal_Set_WR_0(base, codeword >> WR_EN0_VALUE_SHIFT); + } + else + { + return kStatus_Fail; + } + + if (0u != (GLIKEY_GetStatus(base) & GLIKEY_STATUS_ERROR_STATUS_MASK)) + { + return kStatus_GLIKEY_DisabledError; + } + + /* Validate codeword - check if XXYZ^UUVW == 0xFFFF */ + if (0xFFFFu != (((codeword) ^ (codeword >> 16u)) & 0xFFFFu)) + { + return kStatus_Fail; + } + + return kStatus_Success; +} + +status_t GLIKEY_EndOperation(GLIKEY_Type *base) +{ + /* Check if Glikey SFR locked */ + status_t retCode = GLIKEY_CheckLock(base); + if (kStatus_GLIKEY_NotLocked != retCode) + { + return retCode; + } + + // check state + uint32_t state = (GLIKEY_GetStatus(base) & GLIKEY_STATUS_FSM_STATE_MASK) >> GLIKEY_STATUS_FSM_STATE_SHIFT; + + switch (state) + { + case GLIKEY_FSM_LOCKED: + { + /* If locked -> try to go to init with wr_en0 = WR_0_INIT (0x02); wr_en1 = WR_1_INIT (0x00) */ + Glikey_Internal_Set_WR_0(base, WR_0_INIT); + Glikey_Internal_Set_WR_1(base, WR_1_INIT); + + /* if still locked return locked - need to change index */ + if (GLIKEY_FSM_LOCKED == + (GLIKEY_GetStatus(base) & GLIKEY_STATUS_FSM_STATE_MASK) >> GLIKEY_STATUS_FSM_STATE_SHIFT) + { + return kStatus_GLIKEY_Locked; + } + + retCode = kStatus_Success; + break; + } + + case GLIKEY_FSM_SSR_RESET: + case GLIKEY_FSM_WR_EN: + { + /* If FSM in RESET -> wr_en0 = WR_0_INIT; wr_en1 = WR_1_INIT */ + /* If FSM in WR_EN -> wr_en0 = WR_0_INIT; wr_en1 = WR_1_INIT */ + Glikey_Internal_Set_WR_0(base, WR_0_INIT); + Glikey_Internal_Set_WR_1(base, WR_1_INIT); + + retCode = kStatus_Success; + break; + } + + default: + /* Disabled error */ + retCode = kStatus_GLIKEY_DisabledError; + break; + } + + return retCode; +} + +status_t GLIKEY_ResetIndex(GLIKEY_Type *base, uint32_t index) +{ + /* Check if Glikey SFR locked */ + status_t retCode = GLIKEY_CheckLock(base); + if (kStatus_GLIKEY_NotLocked != retCode) + { + return retCode; + } + + /* Check if index is locked */ + retCode = GLIKEY_IsIndexLocked(base, index); + if (kStatus_GLIKEY_NotLocked != retCode) + { + return retCode; + } + + /* Check if FSM is in INIT state */ + uint32_t state = (GLIKEY_GetStatus(base) & GLIKEY_STATUS_FSM_STATE_MASK) >> GLIKEY_STATUS_FSM_STATE_SHIFT; + if (GLIKEY_FSM_INIT == state) + { + /* CTRL0.WRITE_INDEX = index */ + uint32_t ctrl0 = ((GLIKEY_Type *)base)->CTRL_0; + /* Clear index */ + ctrl0 = ctrl0 & (~GLIKEY_CTRL_0_WRITE_INDEX_MASK); + /* Write new value */ + ((GLIKEY_Type *)base)->CTRL_0 = ctrl0 | GLIKEY_CTRL_0_WRITE_INDEX(index); + + return kStatus_Success; + } + else + { + return kStatus_GLIKEY_DisabledError; + } +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_glikey.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_glikey.h new file mode 100644 index 00000000000..795d6d56ce9 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_glikey.h @@ -0,0 +1,311 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_GLIKEY_H_ +#define _FSL_GLIKEY_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup GLIKEY + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Defines GLIKEY driver version 2.0.0. + * + * Change log: + * - Version 2.0.0 + * - Initial version + */ +#define FSL_GLIKEY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) + +enum +{ + kStatus_GLIKEY_LockedError = + MAKE_STATUS(kStatusGroup_GLIKEY, 0x1u), /*!< GLIKEY status for locked SFR registers (unexpected) . */ + kStatus_GLIKEY_NotLocked = MAKE_STATUS(kStatusGroup_GLIKEY, 0x2u), /*!< GLIKEY status for unlocked SFR registers. */ + kStatus_GLIKEY_Locked = MAKE_STATUS(kStatusGroup_GLIKEY, 0x3u), /*!< GLIKEY status for locked SFR registers. */ + kStatus_GLIKEY_DisabledError = MAKE_STATUS(kStatusGroup_GLIKEY, 0x4u), /*!< GLIKEY status for disabled error. */ +}; + +/* [Design] + Value: XX YZ UU VW + - XX: F0: write to WR_EN1, 0F: do not write to WR_EN1 + - UU: F0: write to WR_EN0, 0F: do not write to WR_EN0 + - Y: equal to ^ W + - Z: value to write to WR_EN1 or equal to ~W + - V: equal to ^ Z + - W: value to write to WR_EN0 or equal to ~Z + Invariant: XXYZ ^ UUVW == 0xFFFF +*/ +#define GLIKEY_CODEWORD_STEP1 ((uint32_t)0xF0C10F3EU) /*< Codeword for transition from STEP1 --> STEP2 */ +#define GLIKEY_CODEWORD_STEP2 ((uint32_t)0x0F1DF0E2U) /*< Codeword for transition from STEP2 --> STEP3 */ +#define GLIKEY_CODEWORD_STEP3 ((uint32_t)0xF0B00F4FU) /*< Codeword for transition from STEP3 --> STEP4 */ +#define GLIKEY_CODEWORD_STEP4 ((uint32_t)0x0F4EF0B1U) /*< Codeword for transition from STEP4 --> STEP5 */ +#define GLIKEY_CODEWORD_STEP5 ((uint32_t)0xF0810F7EU) /*< Codeword for transition from STEP5 --> STEP6 */ +#define GLIKEY_CODEWORD_STEP6 ((uint32_t)0x0F5DF0A2U) /*< Codeword for transition from STEP6 --> STEP7 */ +#define GLIKEY_CODEWORD_STEP7 ((uint32_t)0xF0700F8FU) /*< Codeword for transition from STEP7 --> STEP8 */ +#define GLIKEY_CODEWORD_STEP_EN ((uint32_t)0x0FFFF000U) /*< Codeword for transition from STEP 4/8 --> WR_EN */ + +#define GLIKEY_FSM_WR_DIS 0x0Bu +#define GLIKEY_FSM_INIT 0x16u +#define GLIKEY_FSM_STEP1 0x2Cu +#define GLIKEY_FSM_STEP2 0x58u +#define GLIKEY_FSM_STEP3 0xB0u +#define GLIKEY_FSM_STEP4 0x160u +#define GLIKEY_FSM_LOCKED 0xC01u +#define GLIKEY_FSM_WR_EN 0x1802u +#define GLIKEY_FSM_SSR_RESET 0x1005u + +/*@}*/ + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name GLIKEY Functional Operation + * @{ + */ + +/*! + * @brief Retreives the current status of Glikey. + * + * @param[in] base The base address of the Glikey instance + * + * @return Glikey status information + */ +uint32_t GLIKEY_GetStatus(GLIKEY_Type *base); + +/*! + * @brief Get if Glikey is locked + * + * This operation returns the locking status of Glikey. + * + * @return Status + * @retval kStatus_GLIKEY_Locked if locked + * @retval kStatus_GLIKEY_NotLocked if unlocked + */ +status_t GLIKEY_IsLocked(GLIKEY_Type *base); + +/*! + * @brief Check if Glikey is locked + * + * This operation returns the locking status of Glikey. + * + * @return Status kStatus_Success if success + * @retval kStatus_GLIKEY_LockedError if locked + * @retval kStatus_GLIKEY_NotLocked if unlocked + */ +status_t GLIKEY_CheckLock(GLIKEY_Type *base); + +/*! + * @brief Retreives the version and configuration of Glikey. + * + * + * @param[in] base The base address of the Glikey instance + * @param[out] result Pointer which will be filled with the Glikey hardware version + * + * @return Status kStatus_Success if success + */ +status_t GLIKEY_GetVersion(GLIKEY_Type *base, uint32_t *result); + +/*! + * @brief Perform a synchronous reset of Glikey. + * + * This function performs a synchrounous reset of the Glikey. This results in: + * - Glikey will return to the INIT state, unless it is in the LOCK state + * + * @param[in] base The base address of the Glikey instance + * + * @return Status kStatus_Success if success + * Possible errors: kStatus_GLIKEY_LockedError + */ +status_t GLIKEY_SyncReset(GLIKEY_Type *base); + +/*! + * @brief Set interrupt enable flag of Glikey. + * + * @param[in] base The base address of the Glikey instance + * @param[in] value Value to set the interrupt enable flag to, see #[TODO: add reference to constants] + * + * @return Status kStatus_Success if success + * Possible errors: kStatus_GLIKEY_LockedError + */ +status_t GLIKEY_SetIntEnable(GLIKEY_Type *base, uint32_t value); + +/*! + * @brief Get interrupt enable flag of Glikey. + * + * @param[in] base The base address of the Glikey instance + * @param[out] value Pointer which will be filled with the interrupt enable status, see #[TODO: add reference to + * constants] + * + * @return Status kStatus_Success if success + */ +status_t GLIKEY_GetIntEnable(GLIKEY_Type *base, uint32_t *value); + +/*! + * @brief Clear the interrupt status flag of Glikey. + * + * @param[in] base The base address of the Glikey instance + * + * @return Status kStatus_Success if success + * Possible errors: kStatus_GLIKEY_LockedError + */ +status_t GLIKEY_ClearIntStatus(GLIKEY_Type *base); + +/*! + * @brief Set the interrupt status flag of Glikey. + * + * @param[in] base The base address of the Glikey instance + * + * @return Status kStatus_Success if success + * Possible errors: kStatus_GLIKEY_LockedError + */ +status_t GLIKEY_SetIntStatus(GLIKEY_Type *base); + +/*! + * @brief Lock Glikey SFR (Special Function Registers) interface + * + * This operation locks the Glikey SFR interface if it is not locked yet. + * + * @param[in] base The base address of the Glikey instance + * + * @return Status kStatus_Success if success + */ +status_t GLIKEY_Lock(GLIKEY_Type *base); + +/*! + * @brief Lock Glikey index + * + * This operation is used to lock a Glikey index. It can only be executed from the WR_EN state, + * executing it from any other state will result in Glikey entering WR_DIS state. When this happens + * Glikey requires a reset (synchrous or asynchronous) to go back to INIT state. + * If the Glikey SFR lock is active this operation will return an error. + * + * @param[in] base The base address of the Glikey instance + * + * @return Status kStatus_Success if success + * Possible errors: kStatus_GLIKEY_LockedError, kStatus_GLIKEY_DisabledError + */ +status_t GLIKEY_LockIndex(GLIKEY_Type *base); + +/*! + * @brief Check if Glikey index is locked + * + * This operation returns the locking status of Glikey index. + * + * @param[in] base The base address of the Glikey instance + * @param[in] index The index of the Glikey instance + * + * @return kStatus_GLIKEY_Locked if locked, kStatus_GLIKEY_NotLocked if unlocked + * Possible errors: kStatus_Fail + */ +status_t GLIKEY_IsIndexLocked(GLIKEY_Type *base, uint32_t index); + +/** + * @brief Start Glikey enable + * + * This operation is used to set a new index and start a the sequence to enable it. It needs to be + * started from the INIT state. If the new index is already locked Glikey will go to LOCKED state, + * otherwise it will go to STEP1 state. + * If this operation is used when Glikey is in any state other than INIT Glikey will go to WR_DIS + * state. It can only recover from this state through a reset (synchrounous or asyncrhonous). + * If the Glikey SFR lock is active this operation will return an error. + * + * @param[in] base The base address of the Glikey instance + * @param[in] index The index of the Glikey instance + * + * @return Status kStatus_Success if success + * Possible errors: kStatus_GLIKEY_LockedError, kStatus_Fail + */ +status_t GLIKEY_StartEnable(GLIKEY_Type *base, uint32_t index); + +/** + * @brief Continue Glikey enable + * + * This operation is used to progress through the different states of the state machine, starting + * from STEP1 until the state WR_EN is reached. Each next state of the state machine can only be + * reached by providing the right codeword to this function. If anything goes wrong the state machine + * will go to WR_DIS state and can only recover from it through a reset (synchrous or asynchronous). + * If the Glikey SFR lock is active this operation will return an error. + * + * @param[in] base The base address of the Glikey instance + * @param[in] codeword Encoded word for progressing to next FSM state (see GLIKEY_CODEWORD_STEPx/EN) + * + * @return Status kStatus_Success if success + * Possible errors: kStatus_GLIKEY_LockedError, kStatus_Fail, kStatus_GLIKEY_DisabledError + */ +/* [Design] + - Check if Glikey is locked + if ( GLIKEY_LOCKED == GLIKEY_GET_SFR_LOCK(base) ) return NXPCLGLIKEY_STATUS_LOCKED_ERROR + - Decode the codeword and write to Glikey CTRL[] + Write GLIKEY_CTRL(base, EnableSelect, EnableValue) + - Check if an error occured + - the only possible error here is FSM error which results in a transition to WR_DIS state + - alternatively this can be confirmed by checking FSM state value + - Only now we will check if the codeword itself is valid + - this is done in this order to assure that the state machine reaches WR_DIS state when needed + - check if XXYZ^UUVW == 0xFFFF and return kStatus_Fail when it fails + - Return kStatus_Success +*/ +status_t GLIKEY_ContinueEnable(GLIKEY_Type *base, uint32_t codeword); + +/** + * @brief End Glikey operation + * + * This operation is used to end a Glikey operation. It can only be executed from the WR_EN, LOCKED + * and RESET states. Executing it from any other state will result in Glikey entering WR_DIS state. + * When this happens Glikey requires a reset (synchrous or asynchronous) to go back to INIT state. + * After this operation Glikey will go to INIT state or stay in LOCKED state when the index was locked. + * If the Glikey SFR lock is active this operation will return an error. + * + * @return A code-flow protected error code (see @ref nxpCsslFlowProtection) + * + * @param[in] base The base address of the Glikey instance + * + * @return Status kStatus_Success if success, kStatus_GLIKEY_Locked if index is still locked + * Possible errors: kStatus_GLIKEY_LockedError, kStatus_GLIKEY_DisabledError + */ +status_t GLIKEY_EndOperation(GLIKEY_Type *base); + +/** + * @brief Reset Glikey index + * + * This operation is used to reset a Glikey index. It can only be executed from the INIT state, + * executing it from any other state will result in Glikey entering WR_DIS state. When this happens + * Glikey requires a reset (synchrous or asynchronous) to go back to INIT state. + * If the Glikey SFR lock is active or the index is locked this operation will return an error. + * + * @return A code-flow protected error code (see @ref nxpCsslFlowProtection) + * + * @return Status kStatus_Success if success, kStatus_GLIKEY_Locked if index is still locked + * Possible errors: kStatus_GLIKEY_LockedError, kStatus_GLIKEY_DisabledError + */ +status_t GLIKEY_ResetIndex(GLIKEY_Type *base, uint32_t index); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ /* end of group glikey */ + +#endif /* _FSL_GLIKEY_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_gpio.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_gpio.c new file mode 100644 index 00000000000..3e32730d1cd --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_gpio.c @@ -0,0 +1,444 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019, 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_gpio.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.gpio" +#endif + +#if defined(GPIO_RSTS) +#define GPIO_RESETS_ARRAY GPIO_RSTS +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) +static PORT_Type *const s_portBases[] = PORT_BASE_PTRS; +static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS; +#else +#if defined(GPIO_RESETS_ARRAY) +static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS; +#endif +#endif + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map FGPIO instance number to clock name. */ +static const clock_ip_name_t s_fgpioClockName[] = FGPIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */ + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ + +#if defined(GPIO_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_gpioResets[] = GPIO_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) +/*! + * @brief Gets the GPIO instance according to the GPIO base + * + * @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.) + * @retval GPIO instance + */ +static uint32_t GPIO_GetInstance(GPIO_Type *base); +#endif +/******************************************************************************* + * Code + ******************************************************************************/ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) || defined(GPIO_RESETS_ARRAY) +static uint32_t GPIO_GetInstance(GPIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++) + { + if (s_gpioBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_gpioBases)); + + return instance; +} +#endif +/*! + * brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, as either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration. + * code + * Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * endcode + * + * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * param pin GPIO port pin number + * param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) +{ + assert(NULL != config); + +#if defined(GPIO_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_gpioResets[GPIO_GetInstance(base)]); +#endif + + if (config->pinDirection == kGPIO_DigitalInput) + { + base->PDDR &= GPIO_FIT_REG(~(1UL << pin)); + } + else + { + GPIO_PinWrite(base, pin, config->outputLogic); + base->PDDR |= GPIO_FIT_REG((1UL << pin)); + } +} + +#if defined(FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER +void GPIO_GetVersionInfo(GPIO_Type *base, gpio_version_info_t *info) +{ + info->feature = (uint16_t)base->VERID; + info->minor = (uint8_t)(base->VERID >> GPIO_VERID_MINOR_SHIFT); + info->major = (uint8_t)(base->VERID >> GPIO_VERID_MAJOR_SHIFT); +} +#endif /* FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER */ + +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) +/*! + * brief Reads the GPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * retval The current GPIO port interrupt status flag, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base) +{ + uint8_t instance; + PORT_Type *portBase; + instance = (uint8_t)GPIO_GetInstance(base); + portBase = s_portBases[instance]; + return portBase->ISFR; +} +#else +/*! + * brief Read the GPIO interrupt status flags. + * + * param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.) + * return The current GPIO's interrupt status flag. + * '1' means the related pin's flag is set, '0' means the related pin's flag not set. + * For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending. + */ +uint32_t GPIO_GpioGetInterruptFlags(GPIO_Type *base) +{ + return base->ISFR[0]; +} +#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) +/*! + * brief Read the GPIO interrupt status flags based on selected interrupt channel(IRQS). + * param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.) + * param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1. + * + * return The current GPIO's interrupt status flag based on the selected interrupt channel. + * '1' means the related pin's flag is set, '0' means the related pin's flag not set. + * For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending. + */ +uint32_t GPIO_GpioGetInterruptChannelFlags(GPIO_Type *base, uint32_t channel) +{ + assert(channel < 2U); + return base->ISFR[channel]; +} +#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT */ +/*! + * brief Read individual pin's interrupt status flag. + * + * param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on) + * param pin GPIO specific pin number. + * return The current selected pin's interrupt status flag. + */ +uint8_t GPIO_PinGetInterruptFlag(GPIO_Type *base, uint32_t pin) +{ + return (uint8_t)((base->ICR[pin] & GPIO_ICR_ISF_MASK) >> GPIO_ICR_ISF_SHIFT); +} +#endif /* FSL_FEATURE_PORT_HAS_NO_INTERRUPT */ + +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) +/*! + * brief Clears multiple GPIO pin interrupt status flags. + * + * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * param mask GPIO pin number macro + */ +void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask) +{ + uint8_t instance; + PORT_Type *portBase; + instance = (uint8_t)GPIO_GetInstance(base); + portBase = s_portBases[instance]; + portBase->ISFR = mask; +} +#else +/*! + * brief Clears GPIO pin interrupt status flags. + * + * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * param mask GPIO pin number macro + */ +void GPIO_GpioClearInterruptFlags(GPIO_Type *base, uint32_t mask) +{ + base->ISFR[0] = GPIO_FIT_REG(mask); +} +#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) +/*! + * brief Clears GPIO pin interrupt status flags based on selected interrupt channel(IRQS). + * + * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * param mask GPIO pin number macro + * param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1. + */ +void GPIO_GpioClearInterruptChannelFlags(GPIO_Type *base, uint32_t mask, uint32_t channel) +{ + assert(channel < 2U); + base->ISFR[channel] = GPIO_FIT_REG(mask); +} +#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT */ +/*! + * brief Clear GPIO individual pin's interrupt status flag. + * + * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on). + * param pin GPIO specific pin number. + */ +void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t pin) +{ + base->ICR[pin] |= GPIO_FIT_REG(GPIO_ICR_ISF(1U)); +} +#endif /* FSL_FEATURE_PORT_HAS_NO_INTERRUPT */ + +#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER +/*! + * brief The GPIO module supports a device-specific number of data ports, organized as 32-bit + * words/8-bit Bytes. Each 32-bit/8-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the GPIO programming model. If the GPIO module's GACR register + * organized as 32-bit words, the attribute controls for the 4 data bytes in the GACR follow a standard little + * endian data convention. + * + * param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * param attribute GPIO checker attribute + */ +void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute) +{ +#if defined(FSL_FEATURE_GPIO_REGISTERS_WIDTH) && (FSL_FEATURE_GPIO_REGISTERS_WIDTH == 8U) + base->GACR = ((uint8_t)attribute << GPIO_GACR_ACB_SHIFT); +#else + base->GACR = ((uint32_t)attribute << GPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB1_SHIFT) | + ((uint32_t)attribute << GPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB3_SHIFT); +#endif /* FSL_FEATURE_GPIO_REGISTERS_WIDTH */ +} +#endif + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) +static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS; +#endif +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) +/*! + * @brief Gets the FGPIO instance according to the GPIO base + * + * @param base FGPIO peripheral base pointer(PTA, PTB, PTC, etc.) + * @retval FGPIO instance + */ +static uint32_t FGPIO_GetInstance(FGPIO_Type *base); +#endif +/******************************************************************************* + * Code + ******************************************************************************/ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) +static uint32_t FGPIO_GetInstance(FGPIO_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_fgpioBases); instance++) + { + if (s_fgpioBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_fgpioBases)); + + return instance; +} +#endif +#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL +/*! + * brief Initializes the FGPIO peripheral. + * + * This function ungates the FGPIO clock. + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + */ +void FGPIO_PortInit(FGPIO_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate FGPIO periphral clock */ + CLOCK_EnableClock(s_fgpioClockName[FGPIO_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} +#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */ + +/*! + * brief Initializes a FGPIO pin used by the board. + * + * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file. + * Then, call the FGPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration: + * code + * Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * endcode + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * param pin FGPIO port pin number + * param config FGPIO pin configuration pointer + */ +void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) +{ + assert(NULL != config); + + if (config->pinDirection == kGPIO_DigitalInput) + { + base->PDDR &= ~(1UL << pin); + } + else + { + FGPIO_PinWrite(base, pin, config->outputLogic); + base->PDDR |= (1UL << pin); + } +} +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) +/*! + * brief Reads the FGPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level-sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t FGPIO_PortGetInterruptFlags(FGPIO_Type *base) +{ + uint8_t instance; + instance = (uint8_t)FGPIO_GetInstance(base); + PORT_Type *portBase; + portBase = s_portBases[instance]; + return portBase->ISFR; +} + +/*! + * brief Clears the multiple FGPIO pin interrupt status flag. + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * param mask FGPIO pin number macro + */ +void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask) +{ + uint8_t instance; + instance = (uint8_t)FGPIO_GetInstance(base); + PORT_Type *portBase; + portBase = s_portBases[instance]; + portBase->ISFR = mask; +} +#endif +#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER +/*! + * brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit + * words. Each 32-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data + * bytes in the GACR follow a standard little endian + * data convention. + * + * param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * param attribute FGPIO checker attribute + */ +void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute) +{ + base->GACR = ((uint32_t)attribute << FGPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << FGPIO_GACR_ACB1_SHIFT) | + ((uint32_t)attribute << FGPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << FGPIO_GACR_ACB3_SHIFT); +} +#endif + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_gpio.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_gpio.h new file mode 100644 index 00000000000..a91fa403efd --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_gpio.h @@ -0,0 +1,799 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_GPIO_H_ +#define FSL_GPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gpio + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief GPIO driver version. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 7, 3)) +/*! @} */ + +#if defined(FSL_FEATURE_GPIO_REGISTERS_WIDTH) && (FSL_FEATURE_GPIO_REGISTERS_WIDTH == 8U) +#define GPIO_FIT_REG(value) \ + ((uint8_t)(value)) /*!< For some platforms with 8-bit register width, cast the type to uint8_t */ +#else +#define GPIO_FIT_REG(value) ((uint32_t)(value)) +#endif /*FSL_FEATURE_GPIO_REGISTERS_WIDTH*/ + +/*! @brief GPIO direction definition */ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ + kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ +} gpio_pin_direction_t; + +#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER +/*! @brief GPIO checker attribute */ +typedef enum _gpio_checker_attribute +{ + kGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW = + 0x00U, /*!< User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write */ + kGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW = + 0x01U, /*!< User nonsecure:Read; User Secure:Read+Write; Privileged Secure:Read+Write */ + kGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW = + 0x02U, /*!< User nonsecure:None; User Secure:Read+Write; Privileged Secure:Read+Write */ + kGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW = + 0x03U, /*!< User nonsecure:Read; User Secure:Read; Privileged Secure:Read+Write */ + kGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW = + 0x04U, /*!< User nonsecure:None; User Secure:Read; Privileged Secure:Read+Write */ + kGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW = + 0x05U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read+Write */ + kGPIO_UsernonsecureNUsersecureNPrivilegedsecureR = + 0x06U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read */ + kGPIO_UsernonsecureNUsersecureNPrivilegedsecureN = + 0x07U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:None */ + kGPIO_IgnoreAttributeCheck = 0x80U, /*!< Ignores the attribute check */ +} gpio_checker_attribute_t; +#endif + +/*! + * @brief The GPIO pin configuration structure. + * + * Each pin can only be configured as either an output pin or an input pin at a time. + * If configured as an input pin, leave the outputConfig unused. + * Note that in some use cases, the corresponding port property should be configured in advance + * with the PORT_SetPinConfig(). + */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ + /* Output configurations; ignore if configured as an input pin */ + uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */ +} gpio_pin_config_t; + +#if (defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) || \ + !(defined(FSL_FEATURE_SOC_PORT_COUNT)) +/*! @brief Configures the interrupt generation condition. */ +typedef enum _gpio_interrupt_config +{ + kGPIO_InterruptStatusFlagDisabled = 0x0U, /*!< Interrupt status flag is disabled. */ + kGPIO_DMARisingEdge = 0x1U, /*!< ISF flag and DMA request on rising edge. */ + kGPIO_DMAFallingEdge = 0x2U, /*!< ISF flag and DMA request on falling edge. */ + kGPIO_DMAEitherEdge = 0x3U, /*!< ISF flag and DMA request on either edge. */ + kGPIO_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */ + kGPIO_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */ + kGPIO_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */ + kGPIO_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */ + kGPIO_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */ + kGPIO_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */ + kGPIO_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */ + kGPIO_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */ + kGPIO_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */ + kGPIO_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */ +} gpio_interrupt_config_t; +#endif + +#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) +/*! @brief Configures the selection of interrupt/DMA request/trigger output. */ +typedef enum _gpio_interrupt_selection +{ + kGPIO_InterruptOutput0 = 0x0U, /*!< Interrupt/DMA request/trigger output 0. */ + kGPIO_InterruptOutput1 = 0x1U, /*!< Interrupt/DMA request/trigger output 1. */ +} gpio_interrupt_selection_t; +#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT */ + +#if defined(FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER +/*! @brief GPIO version information. */ +typedef struct _gpio_version_info +{ + uint16_t feature; /*!< Feature Specification Number. */ + uint8_t minor; /*!< Minor Version Number. */ + uint8_t major; /*!< Major Version Number. */ +} gpio_version_info_t; +#endif /* FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER */ + +#if defined(FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL) && FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL +/*! @brief GPIO pin and interrupt control. */ +typedef enum +{ + kGPIO_PinControlNonSecure = 0x01U, /*!< Pin Control Non-Secure. */ + kGPIO_InterruptControlNonSecure = 0x02U, /*!< Interrupt Control Non-Secure. */ + kGPIO_PinControlNonPrivilege = 0x04U, /*!< Pin Control Non-Privilege. */ + kGPIO_InterruptControlNonPrivilege = 0x08U, /*!< Interrupt Control Non-Privilege. */ +} gpio_pin_interrupt_control_t; +#endif /* FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL */ + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup gpio_driver + * @{ + */ + +/*! @name GPIO Configuration */ +/*! @{ */ + +/*! + * @brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, as either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration. + * @code + * Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param pin GPIO port pin number + * @param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); + +#if defined(FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER +/*! + * @brief Get GPIO version information. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param info GPIO version information + */ +void GPIO_GetVersionInfo(GPIO_Type *base, gpio_version_info_t *info); +#endif /* FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER */ + +#if defined(FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL) && FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL +/*! + * @brief lock or unlock secure privilege. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask pin or interrupt macro + */ +static inline void GPIO_SecurePrivilegeLock(GPIO_Type *base, gpio_pin_interrupt_control_t mask) +{ + base->LOCK |= GPIO_FIT_REG(mask); +} + +/*! + * @brief Enable Pin Control Non-Secure. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_EnablePinControlNonSecure(GPIO_Type *base, uint32_t mask) +{ + base->PCNS |= GPIO_FIT_REG(mask); +} + +/*! + * @brief Disable Pin Control Non-Secure. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_DisablePinControlNonSecure(GPIO_Type *base, uint32_t mask) +{ + base->PCNS &= GPIO_FIT_REG(~mask); +} + +/*! + * @brief Enable Pin Control Non-Privilege. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_EnablePinControlNonPrivilege(GPIO_Type *base, uint32_t mask) +{ + base->PCNP |= GPIO_FIT_REG(mask); +} + +/*! + * @brief Disable Pin Control Non-Privilege. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_DisablePinControlNonPrivilege(GPIO_Type *base, uint32_t mask) +{ + base->PCNP &= GPIO_FIT_REG(~mask); +} + +/*! + * @brief Enable Interrupt Control Non-Secure. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_EnableInterruptControlNonSecure(GPIO_Type *base, uint32_t mask) +{ + base->ICNS |= GPIO_FIT_REG(mask); +} + +/*! + * @brief Disable Interrupt Control Non-Secure. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_DisableInterruptControlNonSecure(GPIO_Type *base, uint32_t mask) +{ + base->ICNS &= GPIO_FIT_REG(~mask); +} + +/*! + * @brief Enable Interrupt Control Non-Privilege. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_EnableInterruptControlNonPrivilege(GPIO_Type *base, uint32_t mask) +{ + base->ICNP |= GPIO_FIT_REG(mask); +} + +/*! + * @brief Disable Interrupt Control Non-Privilege. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_DisableInterruptControlNonPrivilege(GPIO_Type *base, uint32_t mask) +{ + base->ICNP &= GPIO_FIT_REG(~mask); +} +#endif /* FSL_FEATURE_GPIO_HAS_SECURE_PRIVILEGE_CONTROL */ + +#if defined(FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL +/*! + * @brief Enable port input. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortInputEnable(GPIO_Type *base, uint32_t mask) +{ + base->PIDR &= GPIO_FIT_REG(~mask); +} + +/*! + * @brief Disable port input. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortInputDisable(GPIO_Type *base, uint32_t mask) +{ + base->PIDR |= GPIO_FIT_REG(mask); +} +#endif /* FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL */ + +/*! @} */ + +/*! @name GPIO Output Operations */ +/*! @{ */ + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param pin GPIO pin number + * @param output GPIO pin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output) +{ +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) + if (output == 0U) + { + base->PCOR = GPIO_FIT_REG(1UL << pin); + } + else + { + base->PSOR = GPIO_FIT_REG(1UL << pin); + } +#else + if (output == 0U) + { + base->PDOR |= GPIO_FIT_REG(1UL << pin); + } + else + { + base->PDOR &= ~GPIO_FIT_REG(1UL << pin); + } +#endif +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask) +{ +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) + base->PSOR = GPIO_FIT_REG(mask); +#else + base->PDOR |= GPIO_FIT_REG(mask); +#endif +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask) +{ +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) + base->PCOR = GPIO_FIT_REG(mask); +#else + base->PDOR &= ~GPIO_FIT_REG(mask); +#endif +} + +/*! + * @brief Reverses the current output logic of the multiple GPIO pins. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask) +{ +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) && FSL_FEATURE_GPIO_HAS_NO_INDEP_OUTPUT_CONTROL) + base->PTOR = GPIO_FIT_REG(mask); +#else + base->PDOR ^= GPIO_FIT_REG(mask); +#endif +} + +/*! @} */ + +/*! @name GPIO Input Operations */ +/*! @{ */ + +/*! + * @brief Reads the current input value of the GPIO port. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param pin GPIO pin number + * @retval GPIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin) +{ + return (((uint32_t)(base->PDIR) >> pin) & 0x01UL); +} + +/*! @} */ + +/*! @name GPIO Interrupt */ +/*! @{ */ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) +/*! + * @brief Reads the GPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @retval The current GPIO port interrupt status flag, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base); + +/*! + * @brief Clears multiple GPIO pin interrupt status flags. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask); +#else +/*! + * @brief Configures the gpio pin interrupt/DMA request. + * + * @param base GPIO peripheral base pointer. + * @param pin GPIO pin number. + * @param config GPIO pin interrupt configuration. + * - #kGPIO_InterruptStatusFlagDisabled: Interrupt/DMA request disabled. + * - #kGPIO_DMARisingEdge : DMA request on rising edge(if the DMA requests exit). + * - #kGPIO_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit). + * - #kGPIO_DMAEitherEdge : DMA request on either edge(if the DMA requests exit). + * - #kGPIO_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit). + * - #kGPIO_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit). + * - #kGPIO_FlagEitherEdge : Flag sets on either edge(if the Flag states exit). + * - #kGPIO_InterruptLogicZero : Interrupt when logic zero. + * - #kGPIO_InterruptRisingEdge : Interrupt on rising edge. + * - #kGPIO_InterruptFallingEdge: Interrupt on falling edge. + * - #kGPIO_InterruptEitherEdge : Interrupt on either edge. + * - #kGPIO_InterruptLogicOne : Interrupt when logic one. + * - #kGPIO_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit). + * - #kGPIO_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit). + */ +static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_config_t config) +{ + assert(base); + + base->ICR[pin] = GPIO_FIT_REG((base->ICR[pin] & ~GPIO_ICR_IRQC_MASK) | GPIO_ICR_IRQC(config)); +} + +#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) +/*! + * @brief Configures the gpio pin interrupt/DMA request/trigger output channel selection. + * + * @param base GPIO peripheral base pointer. + * @param pin GPIO pin number. + * @param selection GPIO pin interrupt output selection. + * - #kGPIO_InterruptOutput0: Interrupt/DMA request/trigger output 0. + * - #kGPIO_InterruptOutput1 : Interrupt/DMA request/trigger output 1. + */ +static inline void GPIO_SetPinInterruptChannel(GPIO_Type *base, uint32_t pin, gpio_interrupt_selection_t selection) +{ + assert(base); + + base->ICR[pin] = GPIO_FIT_REG((base->ICR[pin] & ~GPIO_ICR_IRQS_MASK) | GPIO_ICR_IRQS(selection)); +} +#endif +/*! + * @brief Read the GPIO interrupt status flags. + * + * @param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.) + * @return The current GPIO's interrupt status flag. + * '1' means the related pin's flag is set, '0' means the related pin's flag not set. + * For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending. + */ +uint32_t GPIO_GpioGetInterruptFlags(GPIO_Type *base); +#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) +/*! + * @brief Read the GPIO interrupt status flags based on selected interrupt channel(IRQS). + * + * @param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on.) + * @param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1. + * @return The current GPIO's interrupt status flag based on the selected interrupt channel. + * '1' means the related pin's flag is set, '0' means the related pin's flag not set. + * For example, the return value 0x00010001 means the pin 0 and 17 have the interrupt pending. + */ +uint32_t GPIO_GpioGetInterruptChannelFlags(GPIO_Type *base, uint32_t channel); +#endif +/*! + * @brief Read individual pin's interrupt status flag. + * + * @param base GPIO peripheral base pointer. (GPIOA, GPIOB, GPIOC, and so on) + * @param pin GPIO specific pin number. + * @return The current selected pin's interrupt status flag. + */ +uint8_t GPIO_PinGetInterruptFlag(GPIO_Type *base, uint32_t pin); + +/*! + * @brief Clears GPIO pin interrupt status flags. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + */ +void GPIO_GpioClearInterruptFlags(GPIO_Type *base, uint32_t mask); +#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) +/*! + * @brief Clears GPIO pin interrupt status flags based on selected interrupt channel(IRQS). + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param mask GPIO pin number macro + * @param channel '0' means selete interrupt channel 0, '1' means selete interrupt channel 1. + */ +void GPIO_GpioClearInterruptChannelFlags(GPIO_Type *base, uint32_t mask, uint32_t channel); +#endif +/*! + * @brief Clear GPIO individual pin's interrupt status flag. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on). + * @param pin GPIO specific pin number. + */ +void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t pin); + +/*! + * @brief Reads the GPIO DMA request flags. + * The corresponding flag will be cleared automatically at the completion of the requested + * DMA transfer + */ +static inline uint32_t GPIO_GetPinsDMARequestFlags(GPIO_Type *base) +{ + assert(base); + return (base->ISFR[1]); +} + +/*! + * @brief Sets the GPIO interrupt configuration in PCR register for multiple pins. + * + * @param base GPIO peripheral base pointer. + * @param mask GPIO pin number macro. + * @param config GPIO pin interrupt configuration. + * - #kGPIO_InterruptStatusFlagDisabled: Interrupt disabled. + * - #kGPIO_DMARisingEdge : DMA request on rising edge(if the DMA requests exit). + * - #kGPIO_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit). + * - #kGPIO_DMAEitherEdge : DMA request on either edge(if the DMA requests exit). + * - #kGPIO_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit). + * - #kGPIO_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit). + * - #kGPIO_FlagEitherEdge : Flag sets on either edge(if the Flag states exit). + * - #kGPIO_InterruptLogicZero : Interrupt when logic zero. + * - #kGPIO_InterruptRisingEdge : Interrupt on rising edge. + * - #kGPIO_InterruptFallingEdge: Interrupt on falling edge. + * - #kGPIO_InterruptEitherEdge : Interrupt on either edge. + * - #kGPIO_InterruptLogicOne : Interrupt when logic one. + * - #kGPIO_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit). + * - #kGPIO_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit).. + */ +static inline void GPIO_SetMultipleInterruptPinsConfig(GPIO_Type *base, uint32_t mask, gpio_interrupt_config_t config) +{ + assert(base); + + if (0UL != (mask & 0xffffUL)) + { + base->GICLR = GPIO_FIT_REG((GPIO_ICR_IRQC(config)) | (mask & 0xffffU)); + } + mask = mask >> 16U; + if (mask != 0UL) + { + base->GICHR = GPIO_FIT_REG((GPIO_ICR_IRQC(config)) | (mask & 0xffffU)); + } +} +#endif + +#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER +/*! + * brief The GPIO module supports a device-specific number of data ports, organized as 32-bit + * words/8-bit Bytes. Each 32-bit/8-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the GPIO programming model. If the GPIO module's GACR register + * organized as 32-bit words, the attribute controls for the 4 data bytes in the GACR follow a standard little + * endian data convention. + * + * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.) + * @param attribute GPIO checker attribute + */ +void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute); +#endif + +/*! @} */ +/*! @} */ + +/*! + * @addtogroup fgpio_driver + * @{ + */ + +/* + * Introduces the FGPIO feature. + * + * The FGPIO features are only support on some Kinetis MCUs. The FGPIO registers are aliased to the IOPORT + * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and + * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO. + */ + +#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT + +/*! @name FGPIO Configuration */ +/*! @{ */ + +#if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL +/*! + * @brief Initializes the FGPIO peripheral. + * + * This function ungates the FGPIO clock. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + */ +void FGPIO_PortInit(FGPIO_Type *base); +#endif /* FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL */ + +/*! + * @brief Initializes a FGPIO pin used by the board. + * + * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file. + * Then, call the FGPIO_PinInit() function. + * + * This is an example to define an input pin or an output pin configuration: + * @code + * Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param pin FGPIO port pin number + * @param config FGPIO pin configuration pointer + */ +void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config); + +/*! @} */ + +/*! @name FGPIO Output Operations */ +/*! @{ */ + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param pin FGPIO pin number + * @param output FGPIOpin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void FGPIO_PinWrite(FGPIO_Type *base, uint32_t pin, uint8_t output) +{ + if (output == 0U) + { + base->PCOR = 1UL << pin; + } + else + { + base->PSOR = 1UL << pin; + } +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 1. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +static inline void FGPIO_PortSet(FGPIO_Type *base, uint32_t mask) +{ + base->PSOR = mask; +} + +/*! + * @brief Sets the output level of the multiple FGPIO pins to the logic 0. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +static inline void FGPIO_PortClear(FGPIO_Type *base, uint32_t mask) +{ + base->PCOR = mask; +} + +/*! + * @brief Reverses the current output logic of the multiple FGPIO pins. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +static inline void FGPIO_PortToggle(FGPIO_Type *base, uint32_t mask) +{ + base->PTOR = mask; +} +/*! @} */ + +/*! @name FGPIO Input Operations */ +/*! @{ */ + +/*! + * @brief Reads the current input value of the FGPIO port. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param pin FGPIO pin number + * @retval FGPIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t FGPIO_PinRead(FGPIO_Type *base, uint32_t pin) +{ + return (((base->PDIR) >> pin) & 0x01U); +} +/*! @} */ + +/*! @name FGPIO Interrupt */ +/*! @{ */ +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \ + defined(FSL_FEATURE_SOC_PORT_COUNT) + +/*! + * @brief Reads the FGPIO port interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level-sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the + * pin 0 and 17 have the interrupt. + */ +uint32_t FGPIO_PortGetInterruptFlags(FGPIO_Type *base); + +/*! + * @brief Clears the multiple FGPIO pin interrupt status flag. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param mask FGPIO pin number macro + */ +void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask); +#endif +#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER +/*! + * @brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit + * words. Each 32-bit data port includes a GACR register, which defines the byte-level + * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data + * bytes in the GACR follow a standard little endian + * data convention. + * + * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.) + * @param attribute FGPIO checker attribute + */ +void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute); +#endif /* FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER */ + +/*! @} */ + +#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* FSL_GPIO_H_*/ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_i3c.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_i3c.c new file mode 100644 index 00000000000..dc10970b5af --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_i3c.c @@ -0,0 +1,3572 @@ +/* + * Copyright 2018-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_i3c.h" +#if !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) +#include "fsl_reset.h" +#endif +#include +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.i3c" +#endif + +#define I3C_BROADCASE_ADDR (0x7EU) + +#define NSEC_PER_SEC (1000000000UL) +#define FSL_I3C_ERROR_RATE_MAX (10U) +#define FSL_I3C_PPBAUD_DIV_MAX ((I3C_MCONFIG_PPBAUD_MASK >> I3C_MCONFIG_PPBAUD_SHIFT) + 1U) +#define FSL_I3C_ODBAUD_DIV_MAX ((I3C_MCONFIG_ODBAUD_MASK >> I3C_MCONFIG_ODBAUD_SHIFT) + 1U) +#define FSL_I3C_I2CBAUD_DIV_MAX (((I3C_MCONFIG_I2CBAUD_MASK >> I3C_MCONFIG_I2CBAUD_SHIFT) + 1U) / 2U) + +/*! @brief Common sets of flags used by the driver. */ +enum _i3c_flag_constants +{ + /*! All flags which are cleared by the driver upon starting a transfer. */ + kMasterClearFlags = kI3C_MasterSlaveStartFlag | kI3C_MasterControlDoneFlag | kI3C_MasterCompleteFlag | + kI3C_MasterArbitrationWonFlag | kI3C_MasterSlave2MasterFlag | kI3C_MasterErrorFlag, + + /*! IRQ sources enabled by the non-blocking transactional API. */ + kMasterIrqFlags = kI3C_MasterSlaveStartFlag | kI3C_MasterControlDoneFlag | kI3C_MasterCompleteFlag | + kI3C_MasterRxReadyFlag /* | kI3C_MasterTxReadyFlag */ | kI3C_MasterArbitrationWonFlag | + kI3C_MasterErrorFlag | kI3C_MasterSlave2MasterFlag, + + /*! Errors to check for. */ + kMasterErrorFlags = kI3C_MasterErrorNackFlag | kI3C_MasterErrorWriteAbortFlag | +#if !defined(FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) || (!FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) + kI3C_MasterErrorTermFlag | +#endif + kI3C_MasterErrorParityFlag | kI3C_MasterErrorCrcFlag | kI3C_MasterErrorReadFlag | + kI3C_MasterErrorWriteFlag | kI3C_MasterErrorMsgFlag | kI3C_MasterErrorInvalidReqFlag | + kI3C_MasterErrorTimeoutFlag, + /*! All flags which are cleared by the driver upon starting a transfer. */ + kSlaveClearFlags = kI3C_SlaveBusStartFlag | kI3C_SlaveMatchedFlag | kI3C_SlaveBusStopFlag, + + /*! IRQ sources enabled by the non-blocking transactional API. */ + kSlaveIrqFlags = kI3C_SlaveBusStartFlag | kI3C_SlaveMatchedFlag | kI3C_SlaveBusStopFlag | kI3C_SlaveRxReadyFlag | + kI3C_SlaveDynamicAddrChangedFlag | kI3C_SlaveReceivedCCCFlag | kI3C_SlaveErrorFlag | + kI3C_SlaveHDRCommandMatchFlag | kI3C_SlaveCCCHandledFlag | kI3C_SlaveEventSentFlag, + + /*! Errors to check for. */ + kSlaveErrorFlags = kI3C_SlaveErrorOverrunFlag | kI3C_SlaveErrorUnderrunFlag | kI3C_SlaveErrorUnderrunNakFlag | + kI3C_SlaveErrorTermFlag | kI3C_SlaveErrorInvalidStartFlag | kI3C_SlaveErrorSdrParityFlag | + kI3C_SlaveErrorHdrParityFlag | kI3C_SlaveErrorHdrCRCFlag | kI3C_SlaveErrorS0S1Flag | + kI3C_SlaveErrorOverreadFlag | kI3C_SlaveErrorOverwriteFlag, +}; + +/*! @brief States for the state machine used by transactional APIs. */ +enum _i3c_transfer_states +{ + kIdleState = 0, + kIBIWonState, + kSlaveStartState, + kSendCommandState, + kWaitRepeatedStartCompleteState, + kTransferDataState, + kStopState, + kWaitForCompletionState, +}; + +/*! + * @brief Used for conversion between `uint8_t*` and `uint32_t`. + */ +typedef union i3c_puint8_to_u32 +{ + uint8_t *puint8; + uint32_t u32; + const uint8_t *cpuint8; +} i3c_puint8_to_u32_t; + +/* + * MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + } + + return result; +} + +status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle) +{ + status_t result = kStatus_Success; + uint32_t status, errStatus; +#if I3C_RETRY_TIMES + uint32_t waitTimes = I3C_RETRY_TIMES; +#endif + +#if I3C_RETRY_TIMES + while ((result == kStatus_Success) && (--waitTimes)) +#else + while (result == kStatus_Success) +#endif + { + status = I3C_MasterGetStatusFlags(base); + errStatus = I3C_MasterGetErrorStatusFlags(base); + /* Check for error flags. */ + result = I3C_MasterCheckAndClearError(base, errStatus); + /* Check if the control finishes. */ + if (0UL != (status & (uint32_t)kI3C_MasterControlDoneFlag)) + { + I3C_MasterClearStatusFlags(base, (uint32_t)kI3C_MasterControlDoneFlag); + if (!waitIdle) + { + break; + } + } + /* kI3C_MasterControlDoneFlag only indicates ACK got, need to wait for SDA high. */ + if (waitIdle && I3C_MasterGetState(base) == kI3C_MasterStateIdle) + { + break; + } + } + +#if I3C_RETRY_TIMES + if (waitTimes == 0) + { + return kStatus_I3C_Timeout; + } +#endif + + return result; +} + +static status_t I3C_MasterWaitForTxReady(I3C_Type *base, uint8_t byteCounts) +{ + uint32_t errStatus; + status_t result; + size_t txCount; + size_t txFifoSize = + 2UL << ((base->SCAPABILITIES & I3C_SCAPABILITIES_FIFOTX_MASK) >> I3C_SCAPABILITIES_FIFOTX_SHIFT); + +#if I3C_RETRY_TIMES + uint32_t waitTimes = I3C_RETRY_TIMES; +#endif + do + { + /* Get the number of words in the tx fifo and compute empty slots. */ + I3C_MasterGetFifoCounts(base, NULL, &txCount); + txCount = txFifoSize - txCount; + + /* Check for error flags. */ + errStatus = I3C_MasterGetErrorStatusFlags(base); + result = I3C_MasterCheckAndClearError(base, errStatus); + if (kStatus_Success != result) + { + return result; + } +#if I3C_RETRY_TIMES + } while ((txCount < byteCounts) && (--waitTimes)); + + if (waitTimes == 0) + { + return kStatus_I3C_Timeout; + } +#else + } while (txCount < byteCounts); +#endif + + return kStatus_Success; +} + +static status_t I3C_MasterWaitForComplete(I3C_Type *base, bool waitIdle) +{ + uint32_t status, errStatus; + status_t result = kStatus_Success; +#if I3C_RETRY_TIMES + uint32_t waitTimes = I3C_RETRY_TIMES; +#endif + do + { + status = I3C_MasterGetStatusFlags(base); + errStatus = I3C_MasterGetErrorStatusFlags(base); + result = I3C_MasterCheckAndClearError(base, errStatus); +#if I3C_RETRY_TIMES + } while (((status & (uint32_t)kI3C_MasterCompleteFlag) != (uint32_t)kI3C_MasterCompleteFlag) && + (result == kStatus_Success) && --waitTimes); +#else + } while (((status & (uint32_t)kI3C_MasterCompleteFlag) != (uint32_t)kI3C_MasterCompleteFlag) && + (result == kStatus_Success)); +#endif + + I3C_MasterClearStatusFlags(base, (uint32_t)kI3C_MasterCompleteFlag); + +#if I3C_RETRY_TIMES + if (waitTimes == 0UL) + { + return kStatus_I3C_Timeout; + } +#endif + + if (waitIdle) + { +#if I3C_RETRY_TIMES + while ((I3C_MasterGetState(base) != kI3C_MasterStateIdle) && --waitTimes) +#else + while (I3C_MasterGetState(base) != kI3C_MasterStateIdle) +#endif + { + } + } + + return result; +} + +/*! + * @brief Convert provided flags to status code, and clear any errors if present. + * @param base The I3C peripheral base address. + * @param status Current status flags value that will be checked. + * @retval #kStatus_Success + * @retval #kStatus_I3C_OverrunError + * @retval #kStatus_I3C_UnderrunError + * @retval #kStatus_I3C_UnderrunNak + * @retval #kStatus_I3C_Term + * @retval #kStatus_I3C_InvalidStart + * @retval #kStatus_I3C_SdrParityError + * @retval #kStatus_I3C_HdrParityError + * @retval #kStatus_I3C_CrcError + * @retval #kStatus_I3C_S0S1Error + * @retval #kStatus_I3C_ReadFifoError + * @retval #kStatus_I3C_WriteFifoError + */ +status_t I3C_SlaveCheckAndClearError(I3C_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check for error. These errors cause a stop to automatically be sent. We must */ + /* clear the errors before a new transfer can start. */ + status &= (uint32_t)kSlaveErrorFlags; + +#if defined(I3C_DMA_IGNORE_FIFO_ERROR) + status &= ~((uint32_t)kI3C_SlaveErrorUnderrunFlag | (uint32_t)kI3C_SlaveErrorOverwriteFlag); + I3C_SlaveClearErrorStatusFlags(base, + ((uint32_t)kI3C_SlaveErrorUnderrunFlag | (uint32_t)kI3C_SlaveErrorOverwriteFlag)); +#endif + + if (0UL != status) + { + /* Select the correct error code. Ordered by severity, with bus issues first. */ + if (0UL != (status & (uint32_t)kI3C_SlaveErrorOverrunFlag)) + { + result = kStatus_I3C_OverrunError; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorUnderrunFlag)) + { + result = kStatus_I3C_UnderrunError; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorUnderrunNakFlag)) + { + result = kStatus_I3C_UnderrunNak; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorTermFlag)) + { + result = kStatus_I3C_Term; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorInvalidStartFlag)) + { + result = kStatus_I3C_InvalidStart; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorSdrParityFlag)) + { + result = kStatus_I3C_SdrParityError; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorHdrParityFlag)) + { + result = kStatus_I3C_HdrParityError; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorHdrCRCFlag)) + { + result = kStatus_I3C_CrcError; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorS0S1Flag)) + { + result = kStatus_I3C_S0S1Error; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorOverreadFlag)) + { + result = kStatus_I3C_ReadFifoError; + } + else if (0UL != (status & (uint32_t)kI3C_SlaveErrorOverwriteFlag)) + { + result = kStatus_I3C_WriteFifoError; + } + else + { + assert(false); + } + + /* Clear the flags. */ + I3C_SlaveClearErrorStatusFlags(base, status); + + /* Reset fifos. These flags clear automatically. */ + base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK | I3C_SDATACTRL_FLUSHFB_MASK; + } + + return result; +} + +static status_t I3C_SlaveWaitForTxReady(I3C_Type *base) +{ + uint32_t errStatus; + status_t result; + size_t txCount; + size_t txFifoSize = + 2UL << ((base->SCAPABILITIES & I3C_SCAPABILITIES_FIFOTX_MASK) >> I3C_SCAPABILITIES_FIFOTX_SHIFT); + +#if I3C_RETRY_TIMES + uint32_t waitTimes = I3C_RETRY_TIMES; +#endif + do + { + /* Get the number of words in the tx fifo and compute empty slots. */ + I3C_SlaveGetFifoCounts(base, NULL, &txCount); + txCount = txFifoSize - txCount; + + /* Check for error flags. */ + errStatus = I3C_SlaveGetErrorStatusFlags(base); + result = I3C_SlaveCheckAndClearError(base, errStatus); + if (kStatus_Success != result) + { + return result; + } +#if I3C_RETRY_TIMES + } while ((txCount == 0UL) && (--waitTimes)); + + if (waitTimes == 0) + { + return kStatus_I3C_Timeout; + } +#else + } while (txCount == 0UL); +#endif + + return kStatus_Success; +} + +static status_t I3C_MasterEmitStop(I3C_Type *base, bool waitIdle) +{ + status_t result = kStatus_Success; + + /* Return an error if the bus is not in transaction. */ + if (I3C_MasterGetState(base) != kI3C_MasterStateNormAct) + { + return kStatus_I3C_InvalidReq; + } + + /* Send the STOP signal */ + base->MCTRL = (base->MCTRL & ~(I3C_MCTRL_REQUEST_MASK | I3C_MCTRL_DIR_MASK | I3C_MCTRL_RDTERM_MASK)) | + I3C_MCTRL_REQUEST(kI3C_RequestEmitStop); + + /* Wait for the stop operation finishes. */ + /* Also check for errors while waiting. */ + result = I3C_MasterWaitForCtrlDone(base, waitIdle); + + return result; +} + +/*! + * brief I3C master get IBI Type. + * + * param base The I3C peripheral base address. + * param i3c_ibi_type_t Type of #i3c_ibi_type_t. + */ +i3c_ibi_type_t I3C_GetIBIType(I3C_Type *base) +{ + uint32_t ibiValue = (base->MSTATUS & I3C_MSTATUS_IBITYPE_MASK) >> I3C_MSTATUS_IBITYPE_SHIFT; + i3c_ibi_type_t ibiType = kI3C_IbiNormal; + + switch (ibiValue) + { + case 3L: + ibiType = kI3C_IbiHotJoin; + break; + case 2L: + ibiType = kI3C_IbiMasterRequest; + break; + default: + ibiType = kI3C_IbiNormal; + break; + } + + return ibiType; +} + +/*! + * @brief Make sure the bus isn't already busy. + * + * A busy bus is allowed if we are the one driving it. + * + * @param base The I3C peripheral base address. + * @retval #kStatus_Success + * @retval #kStatus_I3C_Busy + */ +/* Not static so it can be used from fsl_i3c_edma.c. */ +status_t I3C_CheckForBusyBus(I3C_Type *base) +{ + return (I3C_MasterGetBusIdleState(base) == true) ? kStatus_Success : kStatus_I3C_Busy; +} + +/* brief Provides a default configuration for the I3C peripheral. + * + */ +void I3C_GetDefaultConfig(i3c_config_t *config) +{ + assert(NULL != config); + + (void)memset(config, 0, sizeof(*config)); + + config->enableMaster = kI3C_MasterCapable; + config->disableTimeout = false; + config->hKeep = kI3C_MasterHighKeeperNone; + config->enableOpenDrainStop = true; + config->enableOpenDrainHigh = true; + config->baudRate_Hz.i2cBaud = 400000U; + config->baudRate_Hz.i3cPushPullBaud = 12500000U; + config->baudRate_Hz.i3cOpenDrainBaud = 2500000U; + config->masterDynamicAddress = 0x0AU; /* Default master dynamic address. */ +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) + config->slowClock_Hz = 0; /* Not update the Soc default setting. */ +#endif + config->enableSlave = true; + config->vendorID = 0x11BU; +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) + config->enableRandomPart = false; +#endif + config->partNumber = 0; + config->dcr = 0; /* Generic device. */ + config->bcr = 0; /* BCR[7:6]: device role, I3C slave(2b'00), BCR[5]: SDR Only / SDR and HDR Capable, SDR and HDR + Capable(1b'1), BCR[4]: Bridge Identifier, Not a bridge device(1b'0), BCR[3]: Offline Capable, + device is offline capable(1b'1), BCR[2]: IBI Payload, No data byte following(1b'0), BCR[1]: IBI + Request Capable, capable(1b'1), BCR[0]: Max Data Speed Limitation, has limitation(1b'1). */ + config->hdrMode = (uint8_t)kI3C_HDRModeDDR; + config->nakAllRequest = false; + config->ignoreS0S1Error = false; + config->offline = false; + config->matchSlaveStartStop = false; + config->maxWriteLength = 256U; + config->maxReadLength = 256U; +} + +/*! + * @brief Initializes the I3C peripheral. + * + */ +void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_Hz) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) || \ + !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) + uint32_t instance = I3C_GetInstance(base); +#endif + uint32_t configValue; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the clock. */ + CLOCK_EnableClock(kI3cClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) + /* Reset the I3C module */ + RESET_PeripheralReset(kI3cResets[instance]); +#endif + + if ((config->masterDynamicAddress != 0U) && (config->enableMaster == kI3C_MasterOn)) + { + base->MDYNADDR &= ~I3C_MDYNADDR_DADDR_MASK; + base->MDYNADDR |= I3C_MDYNADDR_DADDR(config->masterDynamicAddress) | I3C_MDYNADDR_DAVALID_MASK; + } + + base->MCONFIG = I3C_MCONFIG_MSTENA(config->enableMaster) | I3C_MCONFIG_DISTO(config->disableTimeout) | + I3C_MCONFIG_HKEEP(config->hKeep) | I3C_MCONFIG_ODSTOP(config->enableOpenDrainStop) | + I3C_MCONFIG_ODHPP(config->enableOpenDrainHigh); + +#if defined(FSL_FEATURE_I3C_HAS_START_SCL_DELAY) && FSL_FEATURE_I3C_HAS_START_SCL_DELAY + base->MCONFIG_EXT = I3C_MCONFIG_EXT_I3C_CAS_DEL(config->startSclDelay) | I3C_MCONFIG_EXT_I3C_CASR_DEL(config->restartSclDelay); +#endif + + I3C_MasterSetWatermarks(base, kI3C_TxTriggerUntilOneLessThanFull, kI3C_RxTriggerOnNotEmpty, true, true); + + I3C_MasterSetBaudRate(base, &config->baudRate_Hz, sourceClock_Hz); + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) + assert((config->slowClock_Hz >= 1000000U) || (config->slowClock_Hz == 0U)); + + uint8_t matchCount; + /* Set as (slowClk(MHz) - 1) to generate 1us clock cycle. Controller uses it to count 100us timeout. Target uses it as IBI request to drive SDA low. + Note: Use BAMATCH = 1 to generate 1us clock cycle if slow clock is 1MHz. The value of 0 would not give a correct match indication. */ + if (config->slowClock_Hz != 0U) + { + matchCount = (uint8_t)(config->slowClock_Hz / 1000000UL) - 1U; + matchCount = (matchCount == 0U) ? 1U : matchCount; + } + else + { + /* BAMATCH has default value based on Soc default slow clock after reset, using this default value when slowClock_Hz is 0. */ + matchCount = (uint8_t)((base->SCONFIG & I3C_SCONFIG_BAMATCH_MASK) >> I3C_SCONFIG_BAMATCH_SHIFT); + } +#endif + + configValue = base->SCONFIG; + + configValue &= + ~(I3C_SCONFIG_SADDR_MASK | +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) + I3C_SCONFIG_BAMATCH_MASK | +#endif + I3C_SCONFIG_OFFLINE_MASK | +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) + I3C_SCONFIG_IDRAND_MASK | +#endif +#if defined(FSL_FEATURE_I3C_HAS_HDROK) && FSL_FEATURE_I3C_HAS_HDROK + I3C_SCONFIG_HDROK_MASK | +#else + I3C_SCONFIG_DDROK_MASK | +#endif + I3C_SCONFIG_S0IGNORE_MASK | I3C_SCONFIG_MATCHSS_MASK | I3C_SCONFIG_NACK_MASK | I3C_SCONFIG_SLVENA_MASK); + + configValue |= I3C_SCONFIG_SADDR(config->staticAddr) | +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) + I3C_SCONFIG_BAMATCH(matchCount) | +#endif + I3C_SCONFIG_OFFLINE(config->offline) | +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) + I3C_SCONFIG_IDRAND(config->enableRandomPart) | +#endif +#if defined(FSL_FEATURE_I3C_HAS_HDROK) && FSL_FEATURE_I3C_HAS_HDROK + I3C_SCONFIG_HDROK((0U != (config->hdrMode & (uint8_t)kI3C_HDRModeDDR)) ? 1U : 0U) | +#else + I3C_SCONFIG_DDROK((0U != (config->hdrMode & (uint8_t)kI3C_HDRModeDDR)) ? 1U : 0U) | +#endif + I3C_SCONFIG_S0IGNORE(config->ignoreS0S1Error) | I3C_SCONFIG_MATCHSS(config->matchSlaveStartStop) | + I3C_SCONFIG_NACK(config->nakAllRequest) | I3C_SCONFIG_SLVENA(config->enableSlave); + + base->SVENDORID &= ~I3C_SVENDORID_VID_MASK; + base->SVENDORID |= I3C_SVENDORID_VID(config->vendorID); + +#if defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND + base->SIDPARTNO = config->partNumber; +#else + if (!config->enableRandomPart) + { + base->SIDPARTNO = config->partNumber; + } +#endif + + base->SIDEXT &= ~(I3C_SIDEXT_BCR_MASK | I3C_SIDEXT_DCR_MASK); + base->SIDEXT |= I3C_SIDEXT_BCR(config->bcr) | I3C_SIDEXT_DCR(config->dcr); + + base->SMAXLIMITS &= ~(I3C_SMAXLIMITS_MAXRD_MASK | I3C_SMAXLIMITS_MAXWR_MASK); + base->SMAXLIMITS |= (I3C_SMAXLIMITS_MAXRD(config->maxReadLength) | I3C_SMAXLIMITS_MAXWR(config->maxWriteLength)); + + base->SCONFIG = configValue; +} + +/*! + * brief Provides a default configuration for the I3C master peripheral. + * + * This function provides the following default configuration for the I3C master peripheral: + * code + * masterConfig->enableMaster = kI3C_MasterOn; + * masterConfig->disableTimeout = false; + * masterConfig->hKeep = kI3C_MasterHighKeeperNone; + * masterConfig->enableOpenDrainStop = true; + * masterConfig->enableOpenDrainHigh = true; + * masterConfig->baudRate_Hz = 100000U; + * masterConfig->busType = kI3C_TypeI2C; + * endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with I3C_MasterInit(). + * + * param[out] masterConfig User provided configuration structure for default values. Refer to #i3c_master_config_t. + */ +void I3C_MasterGetDefaultConfig(i3c_master_config_t *masterConfig) +{ + (void)memset(masterConfig, 0, sizeof(*masterConfig)); + + masterConfig->enableMaster = kI3C_MasterOn; + masterConfig->disableTimeout = false; + masterConfig->hKeep = kI3C_MasterHighKeeperNone; + masterConfig->enableOpenDrainStop = true; + masterConfig->enableOpenDrainHigh = true; + masterConfig->baudRate_Hz.i2cBaud = 400000U; + masterConfig->baudRate_Hz.i3cPushPullBaud = 12500000U; + masterConfig->baudRate_Hz.i3cOpenDrainBaud = 2500000U; +} + +/*! + * brief Initializes the I3C master peripheral. + * + * This function enables the peripheral clock and initializes the I3C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * param base The I3C peripheral base address. + * param masterConfig User provided peripheral configuration. Use I3C_MasterGetDefaultConfig() to get a set of + * defaults that you can override. + * param sourceClock_Hz Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void I3C_MasterInit(I3C_Type *base, const i3c_master_config_t *masterConfig, uint32_t sourceClock_Hz) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) || \ + !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) + uint32_t instance = I3C_GetInstance(base); +#endif + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the clock. */ + CLOCK_EnableClock(kI3cClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) + /* Reset the I3C module */ + RESET_PeripheralReset(kI3cResets[instance]); +#endif + base->MCONFIG = I3C_MCONFIG_MSTENA(masterConfig->enableMaster) | I3C_MCONFIG_DISTO(masterConfig->disableTimeout) | + I3C_MCONFIG_HKEEP(masterConfig->hKeep) | I3C_MCONFIG_ODSTOP(masterConfig->enableOpenDrainStop) | + I3C_MCONFIG_ODHPP(masterConfig->enableOpenDrainHigh); + +#if defined(FSL_FEATURE_I3C_HAS_START_SCL_DELAY) && FSL_FEATURE_I3C_HAS_START_SCL_DELAY + base->MCONFIG_EXT = I3C_MCONFIG_EXT_I3C_CAS_DEL(masterConfig->startSclDelay) | I3C_MCONFIG_EXT_I3C_CASR_DEL(masterConfig->restartSclDelay); +#endif + + I3C_MasterSetWatermarks(base, kI3C_TxTriggerUntilOneLessThanFull, kI3C_RxTriggerOnNotEmpty, true, true); + + I3C_MasterSetBaudRate(base, &masterConfig->baudRate_Hz, sourceClock_Hz); + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) + assert((masterConfig->slowClock_Hz >= 1000000U) || (masterConfig->slowClock_Hz == 0U)); + + uint32_t configValue; + uint8_t matchCount; + + /* BAMATCH has default value based on Soc default slow clock after reset, using this default value when slowClock_Hz is 0. */ + if (masterConfig->slowClock_Hz != 0U) + { + /* Set as (slowClk(MHz) - 1) to generate 1us clock cycle for 100us timeout. Note: Use BAMATCH = 1 to generate 1us clock cycle + if slow clock is 1MHz. The value of 0 would not give a correct match indication. */ + matchCount = (uint8_t)(masterConfig->slowClock_Hz / 1000000UL) - 1U; + matchCount = (matchCount == 0U) ? 1U : matchCount; + + configValue = base->SCONFIG & I3C_SCONFIG_BAMATCH_MASK; + configValue |= I3C_SCONFIG_BAMATCH(matchCount); + base->SCONFIG = configValue; + } +#endif +} + +/*! + * @brief Gets the I3C master state. + * + * @param base The I3C peripheral base address. + * @return I3C master state. + */ +i3c_master_state_t I3C_MasterGetState(I3C_Type *base) +{ + uint32_t masterState = (base->MSTATUS & I3C_MSTATUS_STATE_MASK) >> I3C_MSTATUS_STATE_SHIFT; + i3c_master_state_t returnCode; + + switch (masterState) + { + case (uint32_t)kI3C_MasterStateIdle: + returnCode = kI3C_MasterStateIdle; + break; + case (uint32_t)kI3C_MasterStateSlvReq: + returnCode = kI3C_MasterStateSlvReq; + break; + case (uint32_t)kI3C_MasterStateMsgSdr: + returnCode = kI3C_MasterStateMsgSdr; + break; + case (uint32_t)kI3C_MasterStateNormAct: + returnCode = kI3C_MasterStateNormAct; + break; + case (uint32_t)kI3C_MasterStateDdr: + returnCode = kI3C_MasterStateDdr; + break; + case (uint32_t)kI3C_MasterStateDaa: + returnCode = kI3C_MasterStateDaa; + break; + case (uint32_t)kI3C_MasterStateIbiAck: + returnCode = kI3C_MasterStateIbiAck; + break; + case (uint32_t)kI3C_MasterStateIbiRcv: + returnCode = kI3C_MasterStateIbiRcv; + break; + default: + returnCode = kI3C_MasterStateIdle; + break; + } + + return returnCode; +} + +/*! + * brief Deinitializes the I3C master peripheral. + * + * This function disables the I3C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The I3C peripheral base address. + */ +void I3C_MasterDeinit(I3C_Type *base) +{ + uint32_t idx = I3C_GetInstance(base); + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) + /* Reset the I3C module */ + RESET_PeripheralReset(kI3cResets[idx]); +#endif + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate clock. */ + CLOCK_DisableClock(kI3cClocks[idx]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset handle pointer. */ + s_i3cMasterHandle[idx] = NULL; +} + +static uint32_t I3C_CalcErrorRatio(uint32_t curFreq, uint32_t desiredFreq) +{ + if (curFreq > desiredFreq) + { + return (curFreq - desiredFreq) * 100UL / desiredFreq; + } + else + { + return (desiredFreq - curFreq) * 100UL / desiredFreq; + } +} + +/*! + * brief Sets the I3C bus frequency for master transactions. + * + * The I3C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * param base The I3C peripheral base address. + * param baudRate_Hz Pointer to structure of requested bus frequency in Hertz. + * param sourceClock_Hz I3C functional clock frequency in Hertz. + */ +void I3C_MasterSetBaudRate(I3C_Type *base, const i3c_baudrate_hz_t *baudRate_Hz, uint32_t sourceClock_Hz) +{ + uint32_t div, freq; + uint32_t divEven, divOdd; + uint32_t ppBaud, odBaud, i2cBaud; + uint32_t errRate0, errRate1; + uint32_t i3cPPBaud_HZ = baudRate_Hz->i3cPushPullBaud; + uint32_t i3cPPBaudMax_HZ = i3cPPBaud_HZ / 10U + i3cPPBaud_HZ; /* max is 1.1*i3cPPBaud_HZ */ + uint32_t i3cODBaud_HZ = baudRate_Hz->i3cOpenDrainBaud; + uint32_t i3cODBaudMax_HZ = i3cODBaud_HZ / 10U + i3cODBaud_HZ; /* max is 1.1*i3cODBaud_HZ */ + uint32_t i2cBaud_HZ = baudRate_Hz->i2cBaud; + uint32_t i3cPPLow_Ns, i3cOdLow_Ns; + bool isODHigh = (0U != (base->MCONFIG & I3C_MCONFIG_ODHPP_MASK)) ? true : false; + + /* Find out the div to generate target freq */ + freq = sourceClock_Hz / 2UL; + /* ppFreq = FCLK / 2 / (PPBAUD + 1)), 0 <= PPBAUD <= 15 */ + /* We need PPBAUD generate 12.5MHz or so. */ + div = freq / i3cPPBaud_HZ; + div = (div == 0UL) ? 1UL : div; + if (freq / div > i3cPPBaudMax_HZ) + { + div++; + } + assert(div <= FSL_I3C_PPBAUD_DIV_MAX); + ppBaud = div - 1UL; + freq /= div; + + i3cPPLow_Ns = (uint32_t)(NSEC_PER_SEC / (2UL * freq)); + + /* We need ODBAUD generate 2.5MHz or so. */ + if (isODHigh) + { + /* odFreq = (2*freq) / (ODBAUD + 2), 1 <= ODBAUD <= 255 */ + div = (2UL * freq) / i3cODBaud_HZ; + div = div < 2UL ? 2UL : div; + if ((2UL * freq / div) > i3cODBaudMax_HZ) + { + div++; + } + odBaud = div - 2UL; + freq = (2UL * freq) / div; + } + else + { + /* odFreq = ppFreq / (ODBAUD + 1), 1 <= ODBAUD <= 255 */ + div = freq / i3cODBaud_HZ; + div = div < 1UL ? 1UL : div; + if (freq / div > i3cODBaudMax_HZ) + { + div++; + } + odBaud = div - 1UL; + freq /= div; + } + + i3cOdLow_Ns = (odBaud + 1UL) * i3cPPLow_Ns; + + /* i2cFreq = odFreq / (I2CBAUD + 1), 0 <= I2CBAUD <= 7 (I2CBAUD need << 1 in register) */ + /* i2cFreq = NSEC_PER_SEC / (I2CBAUD + 1)*i3cOdLow_Ns */ + divEven = (sourceClock_Hz / i2cBaud_HZ) / (2UL * (ppBaud + 1UL) * (odBaud + 1UL)); + divEven = divEven == 0UL ? 1UL : divEven; + errRate0 = I3C_CalcErrorRatio((uint32_t)(NSEC_PER_SEC / (2UL * divEven * i3cOdLow_Ns)), i2cBaud_HZ); + + divOdd = ((sourceClock_Hz / i2cBaud_HZ) / ((ppBaud + 1UL) * (odBaud + 1UL) - 1UL)) / 2UL; + divOdd = divOdd == 0UL ? 1UL : divOdd; + errRate1 = I3C_CalcErrorRatio((uint32_t)(NSEC_PER_SEC / ((2UL * divOdd + 1UL) * i3cOdLow_Ns)), i2cBaud_HZ); + + if (errRate0 < FSL_I3C_ERROR_RATE_MAX || errRate1 < FSL_I3C_ERROR_RATE_MAX) + { + /* Use this div */ + i2cBaud = errRate0 < errRate1 ? (divEven - 1UL) * 2UL : (divOdd - 1UL) * 2UL + 1UL; + } + else + { + /* Use div + 1, unless current freq is already lower than desired. */ + i2cBaud = freq / divEven < i2cBaud_HZ ? (divEven - 1UL) * 2UL : divEven * 2UL; + } + + base->MCONFIG = (base->MCONFIG & ~(I3C_MCONFIG_PPBAUD_MASK | I3C_MCONFIG_PPLOW_MASK | I3C_MCONFIG_ODBAUD_MASK | + I3C_MCONFIG_I2CBAUD_MASK)) | + I3C_MCONFIG_PPBAUD(ppBaud) | I3C_MCONFIG_ODBAUD(odBaud) | I3C_MCONFIG_I2CBAUD(i2cBaud); +} + +/*! + * brief Sends a START signal and slave address on the I2C/I3C bus, receive size is also specified + * in the call. + * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure + * that another master is not occupying the bus. Then a START signal is transmitted, followed by the + * 7-bit address specified in the a address parameter. Note that this function does not actually wait + * until the START and address are successfully sent on the bus before returning. + * + * param base The I3C peripheral base address. + * param type The bus type to use in this transaction. + * param address 7-bit slave device address, in bits [6:0]. + * param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * param rxSize Read terminate size for the followed read transfer, limit to 255 bytes. + * retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. + * retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + */ +status_t I3C_MasterStartWithRxSize( + I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize) +{ + i3c_master_state_t masterState = I3C_MasterGetState(base); + bool checkDdrState = (type == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true; + if ((masterState != kI3C_MasterStateIdle) && (masterState != kI3C_MasterStateNormAct) && checkDdrState) + { + return kStatus_I3C_Busy; + } + + return I3C_MasterRepeatedStartWithRxSize(base, type, address, dir, rxSize); +} + +/*! + * brief Sends a START signal and slave address on the I2C/I3C bus. + * + * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure + * that another master is not occupying the bus. Then a START signal is transmitted, followed by the + * 7-bit address specified in the a address parameter. Note that this function does not actually wait + * until the START and address are successfully sent on the bus before returning. + * + * param base The I3C peripheral base address. + * param type The bus type to use in this transaction. + * param address 7-bit slave device address, in bits [6:0]. + * param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. + * retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + */ +status_t I3C_MasterStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir) +{ + i3c_master_state_t masterState = I3C_MasterGetState(base); + bool checkDdrState = (type == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true; + if ((masterState != kI3C_MasterStateIdle) && (masterState != kI3C_MasterStateNormAct) && checkDdrState) + { + return kStatus_I3C_Busy; + } + + return I3C_MasterStartWithRxSize(base, type, address, dir, 0); +} + +/*! + * brief Sends a repeated START signal and slave address on the I2C/I3C bus, receive size is also specified + * in the call. + * + * This function is used to send a Repeated START signal when a transfer is already in progress. Like + * I3C_MasterStart(), it also sends the specified 7-bit address. Call this API also configures the read + * terminate size for the following read transfer. For example, set the rxSize = 2, the following read transfer + * will be terminated after two bytes of data received. Write transfer will not be affected by the rxSize + * configuration. + * + * note This function exists primarily to maintain compatible APIs between I3C and I2C drivers, + * as well as to better document the intent of code that uses these APIs. + * + * param base The I3C peripheral base address. + * param type The bus type to use in this transaction. + * param address 7-bit slave device address, in bits [6:0]. + * param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * param rxSize Read terminate size for the followed read transfer, limit to 255 bytes. + * retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. + */ +status_t I3C_MasterRepeatedStartWithRxSize( + I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize) +{ + uint32_t mctrlVal; + + /* Clear all flags. */ + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + +#if defined(FSL_FEATURE_I3C_HAS_ERRATA_051617) && (FSL_FEATURE_I3C_HAS_ERRATA_051617) + /* ERRATA051617: When used as I2C controller generates repeated START randomly before the STOP under PVT condition. + This issue is caused by a glitch at the output of an internal clock MUX. The glitch when generates acts as a clock + pulse which causes the SDA line to fall early during SCL high period and creates the unintended Repeated START before + actual STOP. */ + if (type == kI3C_TypeI2C) + { + base->MCONFIG |= I3C_MCONFIG_SKEW(1); + } + else + { + base->MCONFIG &= ~I3C_MCONFIG_SKEW_MASK; + } +#endif + + /* Issue start command. */ + mctrlVal = base->MCTRL; + mctrlVal &= ~(I3C_MCTRL_TYPE_MASK | I3C_MCTRL_REQUEST_MASK | I3C_MCTRL_DIR_MASK | I3C_MCTRL_ADDR_MASK | + I3C_MCTRL_RDTERM_MASK); + mctrlVal |= I3C_MCTRL_TYPE(type) | I3C_MCTRL_REQUEST(kI3C_RequestEmitStartAddr) | I3C_MCTRL_DIR(dir) | + I3C_MCTRL_ADDR(address) | I3C_MCTRL_RDTERM(rxSize); + + base->MCTRL = mctrlVal; + + return kStatus_Success; +} +/*! + * brief Sends a STOP signal on the I2C/I3C bus. + * + * This function does not return until the STOP signal is seen on the bus, or an error occurs. + * + * param base The I3C peripheral base address. + * retval #kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated. + * retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + * retval #kStatus_I3C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_I3C_FifoError FIFO under run or overrun. + * retval #kStatus_I3C_ArbitrationLost Arbitration lost error. + * retval #kStatus_I3C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t I3C_MasterStop(I3C_Type *base) +{ + return I3C_MasterEmitStop(base, true); +} + +/*! + * brief I3C master emit request. + * + * param base The I3C peripheral base address. + * param masterReq I3C master request of type #i3c_bus_request_t + */ +void I3C_MasterEmitRequest(I3C_Type *base, i3c_bus_request_t masterReq) +{ + uint32_t mctrlReg = base->MCTRL; + + mctrlReg &= ~I3C_MCTRL_REQUEST_MASK; + + if (masterReq == kI3C_RequestProcessDAA) + { + mctrlReg &= ~I3C_MCTRL_TYPE_MASK; + } + + mctrlReg |= I3C_MCTRL_REQUEST(masterReq); + + base->MCTRL = mctrlReg; +} + +/*! + * brief I3C master register IBI rule. + * + * param base The I3C peripheral base address. + * param ibiRule Pointer to ibi rule description of type #i3c_register_ibi_addr_t + */ +void I3C_MasterRegisterIBI(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule) +{ + assert(NULL != ibiRule); + uint32_t ruleValue = I3C_MIBIRULES_MSB0_MASK; + + for (uint32_t count = 0; count < ARRAY_SIZE(ibiRule->address); count++) + { + ruleValue |= ((uint32_t)ibiRule->address[count]) << (count * I3C_MIBIRULES_ADDR1_SHIFT); + } + + ruleValue &= ~I3C_MIBIRULES_NOBYTE_MASK; + + if (!ibiRule->ibiHasPayload) + { + ruleValue |= I3C_MIBIRULES_NOBYTE_MASK; + } + + base->MIBIRULES = ruleValue; +} + +/*! + * brief I3C master get IBI rule. + * + * param base The I3C peripheral base address. + * param ibiRule Pointer to store the read out ibi rule description. + */ +void I3C_MasterGetIBIRules(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule) +{ + assert(NULL != ibiRule); + + uint32_t ruleValue = base->MIBIRULES; + + for (uint32_t count = 0; count < ARRAY_SIZE(ibiRule->address); count++) + { + ibiRule->address[count] = + (uint8_t)(ruleValue >> (count * I3C_MIBIRULES_ADDR1_SHIFT)) & I3C_MIBIRULES_ADDR0_MASK; + } + + ibiRule->ibiHasPayload = (0U == (ruleValue & I3C_MIBIRULES_NOBYTE_MASK)); +} + +/*! + * brief Performs a polling receive transfer on the I2C/I3C bus. + * + * param base The I3C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * param flags Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available options. + * retval #kStatus_Success Data was received successfully. + * retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + * retval #kStatus_I3C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_I3C_FifoError FIFO under run or overrun. + * retval #kStatus_I3C_ArbitrationLost Arbitration lost error. + * retval #kStatus_I3C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t I3C_MasterReceive(I3C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags) +{ + status_t result = kStatus_Success; + bool isRxAutoTerm = ((flags & (uint32_t)kI3C_TransferRxAutoTermFlag) != 0UL); + bool completed = false; + uint32_t status; + uint8_t *buf; + + assert(NULL != rxBuff); + + /* Handle empty read. */ + if (rxSize == 0UL) + { + return kStatus_Success; + } + +#if I3C_RETRY_TIMES + uint32_t waitTimes = I3C_RETRY_TIMES; +#endif + + /* Receive data */ + buf = (uint8_t *)rxBuff; + + while ((rxSize != 0UL) || !completed) + { +#if I3C_RETRY_TIMES + if (--waitTimes == 0) + { + return kStatus_I3C_Timeout; + } +#endif + /* Check for errors. */ + result = I3C_MasterCheckAndClearError(base, I3C_MasterGetErrorStatusFlags(base)); + if (kStatus_Success != result) + { + return result; + } + + /* Check complete flag */ + if (!completed) + { + status = I3C_MasterGetStatusFlags(base) & (uint32_t)kI3C_MasterCompleteFlag; + if (0UL != status) + { + completed = true; + /* Clear complete flag */ + I3C_MasterClearStatusFlags(base, (uint32_t)kI3C_MasterCompleteFlag); + /* Send stop if needed */ + if ((flags & (uint32_t)kI3C_TransferNoStopFlag) == 0UL) + { + if (I3C_MasterGetState(base) == kI3C_MasterStateDdr) + { + I3C_MasterEmitRequest(base, kI3C_RequestForceExit); + result = I3C_MasterWaitForCtrlDone(base, false); + } + else + { + result = I3C_MasterEmitStop(base, false); + } + if (kStatus_Success != result) + { + return result; + } + } + } + } + + /* Check RX data */ + if ((0UL != rxSize) && (0UL != (base->MDATACTRL & I3C_MDATACTRL_RXCOUNT_MASK))) + { + *buf++ = (uint8_t)(base->MRDATAB & I3C_MRDATAB_VALUE_MASK); + rxSize--; + if ((flags & (uint32_t)kI3C_TransferDisableRxTermFlag) == 0UL) + { + if ((!isRxAutoTerm) && (rxSize == 1U)) + { + base->MCTRL |= I3C_MCTRL_RDTERM(1U); + } + } + } + } + + /* Wait idle if stop is sent. */ + if ((flags & (uint32_t)kI3C_TransferNoStopFlag) == 0UL) + { +#if I3C_RETRY_TIMES + while ((I3C_MasterGetState(base) != kI3C_MasterStateIdle) && --waitTimes) +#else + while (I3C_MasterGetState(base) != kI3C_MasterStateIdle) +#endif + { + } + } + return result; +} + +/*! + * brief Performs a polling send transfer on the I2C/I3C bus. + * + * Sends up to a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_I3C_Nak. + * + * param base The I3C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * param flags Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available options. + * retval #kStatus_Success Data was sent successfully. + * retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + * retval #kStatus_I3C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_I3C_FifoError FIFO under run or over run. + * retval #kStatus_I3C_ArbitrationLost Arbitration lost error. + * retval #kStatus_I3C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t I3C_MasterSend(I3C_Type *base, const void *txBuff, size_t txSize, uint32_t flags) +{ + i3c_puint8_to_u32_t buf; + buf.cpuint8 = (const uint8_t *)((const void *)txBuff); + status_t result = kStatus_Success; + bool enableWord = ((flags & (uint32_t)kI3C_TransferWordsFlag) == (uint32_t)kI3C_TransferWordsFlag) ? true : false; + uint8_t byteCounts = enableWord ? 2U : 1U; + + assert(NULL != txBuff); + if (enableWord) + { + assert(txSize % 2UL == 0UL); + } + + /* Send data buffer */ + while (0UL != txSize) + { + /* Wait until there is room in the fifo. This also checks for errors. */ + result = I3C_MasterWaitForTxReady(base, byteCounts); + if (kStatus_Success != result) + { + return result; + } + + /* Write byte into I3C master data register. */ + if (txSize > byteCounts) + { + if (enableWord) + { + base->MWDATAH = (uint32_t)buf.cpuint8[1] << 8UL | (uint32_t)buf.cpuint8[0]; + } + else + { + base->MWDATAB = *buf.cpuint8; + } + } + else + { + if (enableWord) + { + base->MWDATAHE = (uint32_t)buf.cpuint8[1] << 8UL | (uint32_t)buf.cpuint8[0]; + } + else + { + base->MWDATABE = *buf.cpuint8; + } + } + + buf.u32 = buf.u32 + byteCounts; + txSize = txSize - byteCounts; + } + + result = I3C_MasterWaitForComplete(base, false); + if ((result == kStatus_Success) && ((flags & (uint32_t)kI3C_TransferNoStopFlag) == 0UL)) + { + if (I3C_MasterGetState(base) == kI3C_MasterStateDdr) + { + I3C_MasterEmitRequest(base, kI3C_RequestForceExit); + result = I3C_MasterWaitForCtrlDone(base, false); + } + else + { + result = I3C_MasterEmitStop(base, true); + } + } + + return result; +} + +/*! + * brief Performs a DAA in the i3c bus with specified temporary baud rate. + * + * param base The I3C peripheral base address. + * param addressList The pointer for address list which is used to do DAA. + * param count The address count in the address list. + * param daaBaudRate The temporary baud rate in DAA process, NULL for using initial setting. + * The initial setting is set back between the completion of the DAA and the return of this function. + * retval #kStatus_Success The transaction was started successfully. + * retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + * retval #kStatus_I3C_SlaveCountExceed The I3C slave count has exceed the definition in I3C_MAX_DEVCNT. + */ +status_t I3C_MasterProcessDAASpecifiedBaudrate(I3C_Type *base, + uint8_t *addressList, + uint32_t count, + i3c_master_daa_baudrate_t *daaBaudRate) +{ + assert(addressList != NULL); + assert(count != 0U); + + status_t result = kStatus_Success; + uint8_t rxBuffer[8] = {0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU}; + uint32_t masterConfig = 0; + uint32_t devCount = 0; + uint8_t rxSize = 0; + bool mctrlDone = false; + i3c_baudrate_hz_t baudRate_Hz; + uint32_t errStatus; + uint32_t status; + size_t rxCount; + + /* Return an error if the bus is already in use not by us. */ + result = I3C_CheckForBusyBus(base); + if (kStatus_Success != result) + { + return result; + } + + /* Clear all flags. */ + I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + + /* Disable I3C IRQ sources while we configure stuff. */ + uint32_t enabledInts = I3C_MasterGetEnabledInterrupts(base); + I3C_MasterDisableInterrupts(base, enabledInts); + + /* Temporarily adjust baud rate before DAA. */ + if (daaBaudRate != NULL) + { + masterConfig = base->MCONFIG; + /* Set non-zero value for I2C baud rate which is useless here. */ + baudRate_Hz.i2cBaud = 1; + baudRate_Hz.i3cOpenDrainBaud = daaBaudRate->i3cOpenDrainBaud; + baudRate_Hz.i3cPushPullBaud = daaBaudRate->i3cPushPullBaud; + I3C_MasterSetBaudRate(base, &baudRate_Hz, daaBaudRate->sourceClock_Hz); + } + + /* Emit process DAA */ + I3C_MasterEmitRequest(base, kI3C_RequestProcessDAA); + + do + { + status = I3C_MasterGetStatusFlags(base); + + /* Check for error flags. */ + errStatus = I3C_MasterGetErrorStatusFlags(base); + result = I3C_MasterCheckAndClearError(base, errStatus); + if (kStatus_Success != result) + { + break; + } + + if ((!mctrlDone) || (rxSize < 8U)) + { + I3C_MasterGetFifoCounts(base, &rxCount, NULL); + + if (rxCount != 0U) + { + rxBuffer[rxSize++] = (uint8_t)(base->MRDATAB & I3C_MRDATAB_VALUE_MASK); + } + + if ((status & (uint32_t)kI3C_MasterControlDoneFlag) != 0U) + { + I3C_MasterClearStatusFlags(base, (uint32_t)kI3C_MasterControlDoneFlag); + mctrlDone = true; + } + } + else if ((I3C_MasterGetState(base) == kI3C_MasterStateDaa) && + (0UL != (I3C_MasterGetStatusFlags(base) & (uint32_t)kI3C_MasterBetweenFlag))) + { + if (((devCount + 1UL) > count) || ((devCount + 1UL) > I3C_MAX_DEVCNT)) + { + result = kStatus_I3C_SlaveCountExceed; + break; + } + + /* Assign the dynamic address from address list. */ + devList[devCount].dynamicAddr = *addressList++; + base->MWDATAB = devList[devCount].dynamicAddr; + + /* Emit process DAA again. */ + I3C_MasterEmitRequest(base, kI3C_RequestProcessDAA); + + devList[devCount].vendorID = (((uint16_t)rxBuffer[0] << 8U | (uint16_t)rxBuffer[1]) & 0xFFFEU) >> 1U; + devList[devCount].partNumber = ((uint32_t)rxBuffer[2] << 24U | (uint32_t)rxBuffer[3] << 16U | + (uint32_t)rxBuffer[4] << 8U | (uint32_t)rxBuffer[5]); + devList[devCount].bcr = rxBuffer[6]; + devList[devCount].dcr = rxBuffer[7]; + devCount++; + usedDevCount++; + + /* Ready to handle next device. */ + mctrlDone = false; + rxSize = 0; + } + else + { + /* Intentional empty */ + } + } while ((status & (uint32_t)kI3C_MasterCompleteFlag) != (uint32_t)kI3C_MasterCompleteFlag); + + /* Master stops DAA if slave device number exceeds the prepared address number. */ + if (result == kStatus_I3C_SlaveCountExceed) + { + /* Send the STOP signal */ + base->MCTRL = (base->MCTRL & ~(I3C_MCTRL_REQUEST_MASK | I3C_MCTRL_DIR_MASK | I3C_MCTRL_RDTERM_MASK)) | + I3C_MCTRL_REQUEST(kI3C_RequestEmitStop); + } + + /* Set back initial baud rate after DAA is over. */ + if (daaBaudRate != NULL) + { + base->MCONFIG = masterConfig; + } + + /* Clear all flags. */ + I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + + /* Enable I3C IRQ sources while we configure stuff. */ + I3C_MasterEnableInterrupts(base, enabledInts); + + return result; +} + +/*! + * brief Get device information list after DAA process is done. + * + * param base The I3C peripheral base address. + * param[out] count The pointer to store the available device count. + * return Pointer to the i3c_device_info_t array. + */ +i3c_device_info_t *I3C_MasterGetDeviceListAfterDAA(I3C_Type *base, uint8_t *count) +{ + assert(NULL != count); + + *count = usedDevCount; + + return devList; +} + +/*! + * @brief introduce function I3C_MasterClearFlagsAndEnableIRQ. + * + * This function was used of Clear all flags and Enable I3C IRQ sources for @param *base. + * + * @param base The I3C peripheral base address. + */ +static void I3C_MasterClearFlagsAndEnableIRQ(I3C_Type *base) +{ + /* Clear all flags. */ + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + /* Enable I3C IRQ sources. */ + I3C_MasterEnableInterrupts(base, (uint32_t)kMasterIrqFlags); +} + +/*! + * @brief introduce function I3C_MasterTransferNoStartFlag. + * + * This function was used of Check if device request wins arbitration. + * + * @param base The I3C peripheral base address. + * @param transfer Pointer to the transfer structure. + * @retval #true if the device wins arbitration. + * @retval #false if the device not wins arbitration. + */ +static bool I3C_MasterTransferNoStartFlag(I3C_Type *base, i3c_master_transfer_t *transfer) +{ + /* Wait tx fifo empty. */ + size_t txCount = 0xFFUL; + + while (txCount != 0U) + { + I3C_MasterGetFifoCounts(base, NULL, &txCount); + } + + /* Check if device request wins arbitration. */ + if (0UL != (I3C_MasterGetStatusFlags(base) & (uint32_t)kI3C_MasterArbitrationWonFlag)) + { + I3C_MasterClearFlagsAndEnableIRQ(base); + return true; + } + return false; +} + +/*! + * brief Performs a master polling transfer on the I2C/I3C bus. + * + * note The API does not return until the transfer succeeds or fails due + * to error happens during transfer. + * + * param base The I3C peripheral base address. + * param transfer Pointer to the transfer structure. + * retval #kStatus_Success Data was received successfully. + * retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + * retval #kStatus_I3C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_I3C_FifoError FIFO under run or overrun. + * retval #kStatus_I3C_ArbitrationLost Arbitration lost error. + * retval #kStatus_I3C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *transfer) +{ + assert(NULL != transfer); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + + status_t result = kStatus_Success; + i3c_direction_t direction = transfer->direction; + i3c_master_state_t masterState = I3C_MasterGetState(base); + bool checkDdrState = false; + i3c_rx_term_ops_t rxTermOps; + + /* Return an error if the bus is already in use not by us. */ + checkDdrState = (transfer->busType == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true; + + if ((masterState != kI3C_MasterStateIdle) && (masterState != kI3C_MasterStateNormAct) && checkDdrState) + { + return kStatus_I3C_Busy; + } + + /* Clear all flags. */ + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + + /* Disable I3C IRQ sources while we configure stuff. */ + I3C_MasterDisableInterrupts(base, (uint32_t)kMasterIrqFlags); + + if (transfer->busType != kI3C_TypeI3CDdr) + { + direction = (0UL != transfer->subaddressSize) ? kI3C_Write : transfer->direction; + } + + /* True: Set Rx termination bytes at start point, False: Set Rx termination one bytes in advance. */ + if ((transfer->flags & (uint32_t)kI3C_TransferDisableRxTermFlag) != 0U) + { + rxTermOps = kI3C_RxTermDisable; + } + else if (transfer->dataSize <= 255U) + { + rxTermOps = kI3C_RxAutoTerm; + } + else + { + rxTermOps = kI3C_RxTermLastByte; + } + + if (0UL != (transfer->flags & (uint32_t)kI3C_TransferStartWithBroadcastAddr)) + { + if (0UL != (transfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) + { + return kStatus_InvalidArgument; + } + + if (0UL != (transfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag)) + { + return kStatus_InvalidArgument; + } + + /* Issue 0x7E as start. */ + result = I3C_MasterStart(base, transfer->busType, 0x7E, kI3C_Write); + if (result != kStatus_Success) + { + return result; + } + + result = I3C_MasterWaitForCtrlDone(base, false); + if (result != kStatus_Success) + { + return result; + } + } + + if (0UL == (transfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) + { + if ((direction == kI3C_Read) && (rxTermOps == kI3C_RxAutoTerm)) + { + result = I3C_MasterStartWithRxSize(base, transfer->busType, transfer->slaveAddress, direction, + (uint8_t)transfer->dataSize); + } + else + { + result = I3C_MasterStart(base, transfer->busType, transfer->slaveAddress, direction); + } + if (result != kStatus_Success) + { + return result; + } + + result = I3C_MasterWaitForCtrlDone(base, false); + if (result != kStatus_Success) + { + return result; + } + + if (true == I3C_MasterTransferNoStartFlag(base, transfer)) + { + return kStatus_I3C_IBIWon; + } + } + else + { + if ((direction == kI3C_Read) && (rxTermOps != kI3C_RxTermDisable)) + { + /* Can't set Rx termination more than one bytes in advance without START. */ + rxTermOps = kI3C_RxTermLastByte; + } + } + + /* Subaddress, MSB first. */ + if (0U != transfer->subaddressSize) + { + uint32_t subaddressRemaining = transfer->subaddressSize; + while (0UL != subaddressRemaining--) + { + uint8_t subaddressByte = (uint8_t)((transfer->subaddress >> (8UL * subaddressRemaining)) & 0xFFUL); + + result = I3C_MasterWaitForTxReady(base, 1U); + + if ((0UL == subaddressRemaining) && ((transfer->direction == kI3C_Read) || (0UL == transfer->dataSize)) && + (transfer->busType != kI3C_TypeI3CDdr)) + { + base->MWDATABE = subaddressByte; + result = I3C_MasterWaitForComplete(base, false); + if (kStatus_Success != result) + { + if (result == kStatus_I3C_Nak) + { + (void)I3C_MasterEmitStop(base, true); + } + I3C_MasterClearFlagsAndEnableIRQ(base); + return result; + } + } + else + { + base->MWDATAB = subaddressByte; + } + } + /* Need to send repeated start if switching directions to read. */ + if ((transfer->busType != kI3C_TypeI3CDdr) && (0UL != transfer->dataSize) && (transfer->direction == kI3C_Read)) + { + if (rxTermOps == kI3C_RxAutoTerm) + { + result = I3C_MasterRepeatedStartWithRxSize(base, transfer->busType, transfer->slaveAddress, kI3C_Read, + (uint8_t)transfer->dataSize); + } + else + { + result = I3C_MasterRepeatedStart(base, transfer->busType, transfer->slaveAddress, kI3C_Read); + } + + if (kStatus_Success != result) + { + I3C_MasterClearFlagsAndEnableIRQ(base); + return result; + } + + result = I3C_MasterWaitForCtrlDone(base, false); + if (result != kStatus_Success) + { + return result; + } + } + } + + if (rxTermOps == kI3C_RxAutoTerm) + { + transfer->flags |= (uint32_t)kI3C_TransferRxAutoTermFlag; + } + else + { + transfer->flags &= ~(uint32_t)kI3C_TransferRxAutoTermFlag; + } + + /* Transmit data. */ + if ((transfer->direction == kI3C_Write) && (transfer->dataSize > 0UL)) + { + /* Send Data. */ + result = I3C_MasterSend(base, transfer->data, transfer->dataSize, transfer->flags); + } + /* Receive Data. */ + else if ((transfer->direction == kI3C_Read) && (transfer->dataSize > 0UL)) + { + result = I3C_MasterReceive(base, transfer->data, transfer->dataSize, transfer->flags); + } + else + { + if ((transfer->flags & (uint32_t)kI3C_TransferNoStopFlag) == 0UL) + { + result = I3C_MasterEmitStop(base, true); + } + } + + if (result == kStatus_I3C_Nak) + { + (void)I3C_MasterEmitStop(base, true); + } + + I3C_MasterClearFlagsAndEnableIRQ(base); + + return result; +} + +/*! + * brief Creates a new handle for the I3C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I3C_MasterTransferAbort() API shall be called. + * + * + * note The function also enables the NVIC IRQ for the input I3C. Need to notice + * that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + * + * param base The I3C peripheral base address. + * param[out] handle Pointer to the I3C master driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void I3C_MasterTransferCreateHandle(I3C_Type *base, + i3c_master_handle_t *handle, + const i3c_master_transfer_callback_t *callback, + void *userData) +{ + uint32_t instance; + + assert(NULL != handle); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I3C_GetInstance(base); + + /* Save base and instance. */ + handle->callback = *callback; + handle->userData = userData; + + /* Save this handle for IRQ use. */ + s_i3cMasterHandle[instance] = handle; + + /* Set irq handler. */ + s_i3cMasterIsr = I3C_MasterTransferHandleIRQ; + + /* Clear all flags. */ + I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + + /* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC. + In some cases the I3C IRQ is configured through INTMUX, user needs to enable + INTMUX IRQ in application code. */ + (void)EnableIRQ(kI3cIrqs[instance]); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I3C_MasterEnableInterrupts(base, (uint32_t)kMasterIrqFlags); +} + +static void I3C_TransferStateMachineIBIWonState(I3C_Type *base, + i3c_master_handle_t *handle, + i3c_master_state_machine_param_t *stateParams) +{ + assert(NULL != base && NULL != handle && NULL != stateParams); + if (stateParams->masterState == kI3C_MasterStateIbiAck) + { + handle->ibiType = I3C_GetIBIType(base); + if (handle->callback.ibiCallback != NULL) + { + handle->callback.ibiCallback(base, handle, handle->ibiType, kI3C_IbiAckNackPending); + } + else + { + I3C_MasterEmitIBIResponse(base, kI3C_IbiRespNack); + } + } + + /* Make sure there is data in the rx fifo. */ + if (0UL != stateParams->rxCount) + { + if ((handle->ibiBuff == NULL) && (handle->callback.ibiCallback != NULL)) + { + handle->callback.ibiCallback(base, handle, kI3C_IbiNormal, kI3C_IbiDataBuffNeed); + } + uint8_t tempData = (uint8_t)base->MRDATAB; + if (handle->ibiBuff != NULL) + { + handle->ibiBuff[handle->ibiPayloadSize++] = tempData; + } + (stateParams->rxCount)--; + return; + } + else if (0UL != (stateParams->status & (uint32_t)kI3C_MasterCompleteFlag)) + { + handle->ibiType = I3C_GetIBIType(base); + handle->ibiAddress = I3C_GetIBIAddress(base); + stateParams->state_complete = true; + stateParams->result = kStatus_I3C_IBIWon; + } + else + { + stateParams->state_complete = true; + } +} + +static void I3C_TransferStateMachineSendCommandState(I3C_Type *base, + i3c_master_handle_t *handle, + i3c_master_state_machine_param_t *stateParams) +{ + assert(NULL != base && NULL != handle && NULL != stateParams); + I3C_MasterEnableInterrupts(base, (uint32_t)kI3C_MasterTxReadyFlag); + /* Make sure there is room in the tx fifo for the next command. */ + if (0UL == (stateParams->txCount)--) + { + stateParams->state_complete = true; + return; + } + if (handle->transfer.subaddressSize > 1U) + { + handle->transfer.subaddressSize--; + base->MWDATAB = (uint8_t)((handle->transfer.subaddress) >> (8U * handle->transfer.subaddressSize)); + } + else if (handle->transfer.subaddressSize == 1U) + { + handle->transfer.subaddressSize--; + + if ((handle->transfer.direction == kI3C_Read) || (0UL == handle->transfer.dataSize)) + { + base->MWDATABE = (uint8_t)((handle->transfer.subaddress) >> (8U * handle->transfer.subaddressSize)); + + if (handle->transfer.busType != kI3C_TypeI3CDdr) + { + if (0UL == handle->transfer.dataSize) + { + handle->state = (uint8_t)kWaitForCompletionState; + } + else + { + /* xfer->dataSize != 0U, xfer->direction = kI3C_Read */ + handle->state = (uint8_t)kWaitRepeatedStartCompleteState; + } + } + else + { + handle->state = (uint8_t)kTransferDataState; + } + } + else + { + /* Next state, transfer data. */ + handle->state = (uint8_t)kTransferDataState; + base->MWDATAB = (uint8_t)((handle->transfer.subaddress) >> (8U * handle->transfer.subaddressSize)); + } + } + else + { + /* Eliminate misra 15.7*/ + } +} + +static void I3C_TransferStateMachineWaitRepeatedStartCompleteState(I3C_Type *base, + i3c_master_handle_t *handle, + i3c_master_state_machine_param_t *stateParams) +{ + assert(NULL != base && NULL != handle && NULL != stateParams); + /* We stay in this state until the master complete. */ + if (0UL != (stateParams->status & (uint32_t)kI3C_MasterCompleteFlag)) + { + handle->state = (uint8_t)kTransferDataState; + I3C_MasterDisableInterrupts(base, (uint32_t)kI3C_MasterTxReadyFlag); + + if (handle->remainingBytes < 256U) + { + handle->rxTermOps = (handle->rxTermOps == kI3C_RxTermDisable) ? handle->rxTermOps : kI3C_RxAutoTerm; + stateParams->result = + I3C_MasterRepeatedStartWithRxSize(base, handle->transfer.busType, handle->transfer.slaveAddress, + kI3C_Read, (uint8_t)handle->remainingBytes); + } + else + { + stateParams->result = + I3C_MasterRepeatedStart(base, handle->transfer.busType, handle->transfer.slaveAddress, kI3C_Read); + } + } + + stateParams->state_complete = true; +} + +static void I3C_TransferStateMachineTransferDataState(I3C_Type *base, + i3c_master_handle_t *handle, + i3c_master_state_machine_param_t *stateParams) +{ + assert(NULL != base && NULL != handle && NULL != stateParams); + + i3c_puint8_to_u32_t dataBuff; + if (handle->transfer.direction == kI3C_Write) + { + /* Make sure there is room in the tx fifo. */ + if (0UL == (stateParams->txCount)--) + { + stateParams->state_complete = true; + return; + } + + /* Put byte to send in fifo. */ + dataBuff.puint8 = (uint8_t *)handle->transfer.data; + if (handle->transfer.dataSize > 1U) + { + base->MWDATAB = *dataBuff.puint8; + } + else + { + base->MWDATABE = *dataBuff.puint8; + } + dataBuff.u32 = dataBuff.u32 + 1U; + (handle->transfer.dataSize)--; + handle->transfer.data = (void *)(dataBuff.puint8); + + /* Move to stop when the transfer is done. */ + if (--handle->remainingBytes == 0UL) + { + handle->state = (uint8_t)kWaitForCompletionState; + } + } + else + { + /* Make sure there is data in the rx fifo. */ + if (0UL == (stateParams->rxCount)--) + { + stateParams->state_complete = true; + return; + } + + /* Read byte from fifo. */ + dataBuff.puint8 = (uint8_t *)handle->transfer.data; + *dataBuff.puint8 = (uint8_t)base->MRDATAB; + dataBuff.u32 = dataBuff.u32 + 1U; + handle->transfer.data = (void *)(dataBuff.puint8); + + /* Move to stop when the transfer is done. */ + if (--handle->remainingBytes == 0UL) + { + handle->state = (uint8_t)kWaitForCompletionState; + } + + if ((handle->rxTermOps == kI3C_RxTermLastByte) && (handle->remainingBytes == 1UL)) + { + base->MCTRL |= I3C_MCTRL_RDTERM(1UL); + } + } +} + +static void I3C_TransferStateMachineWaitForCompletionState(i3c_master_handle_t *handle, + i3c_master_state_machine_param_t *stateParams) +{ + /* We stay in this state until the maste complete. */ + if (0UL != (stateParams->status & (uint32_t)kI3C_MasterCompleteFlag)) + { + handle->state = (uint8_t)kStopState; + } + else + { + stateParams->state_complete = true; + } +} + +static void I3C_TransferStateMachineStopState(I3C_Type *base, + i3c_master_handle_t *handle, + i3c_master_state_machine_param_t *stateParams) +{ + /* Only issue a stop transition if the caller requested it. */ + if (0UL == (handle->transfer.flags & (uint32_t)kI3C_TransferNoStopFlag)) + { + /* Make sure there is room in the tx fifo for the stop command. */ + if (0UL == (stateParams->txCount)--) + { + stateParams->state_complete = true; + return; + } + if (handle->transfer.busType == kI3C_TypeI3CDdr) + { + I3C_MasterEmitRequest(base, kI3C_RequestForceExit); + } + else + { + (void)I3C_MasterEmitStop(base, false); + } + } + stateParams->state_complete = true; +} + +static status_t I3C_RunTransferStateMachine(I3C_Type *base, i3c_master_handle_t *handle, bool *isDone) +{ + i3c_master_state_machine_param_t stateParams; + (void)memset(&stateParams, 0, sizeof(stateParams)); + + stateParams.result = kStatus_Success; + stateParams.state_complete = false; + + /* Set default isDone return value. */ + *isDone = false; + + uint32_t errStatus; + size_t txFifoSize = + 2UL << ((base->SCAPABILITIES & I3C_SCAPABILITIES_FIFOTX_MASK) >> I3C_SCAPABILITIES_FIFOTX_SHIFT); + + /* Check for errors. */ + stateParams.status = (uint32_t)I3C_MasterGetPendingInterrupts(base); + I3C_MasterClearStatusFlags(base, stateParams.status); + + stateParams.masterState = I3C_MasterGetState(base); + errStatus = I3C_MasterGetErrorStatusFlags(base); + stateParams.result = I3C_MasterCheckAndClearError(base, errStatus); + if (kStatus_Success != stateParams.result) + { + return stateParams.result; + } + + if (0UL != (stateParams.status & (uint32_t)kI3C_MasterSlave2MasterFlag)) + { + if (handle->callback.slave2Master != NULL) + { + handle->callback.slave2Master(base, handle->userData); + } + } + + if ((0UL != (stateParams.status & (uint32_t)kI3C_MasterSlaveStartFlag)) && + (handle->transfer.busType != kI3C_TypeI2C)) + { + handle->state = (uint8_t)kSlaveStartState; + } + + if ((stateParams.masterState == kI3C_MasterStateIbiRcv) || (stateParams.masterState == kI3C_MasterStateIbiAck)) + { + handle->state = (uint8_t)kIBIWonState; + } + + if (handle->state == (uint8_t)kIdleState) + { + return stateParams.result; + } + + /* Get fifo counts and compute room in tx fifo. */ + I3C_MasterGetFifoCounts(base, &stateParams.rxCount, &stateParams.txCount); + stateParams.txCount = txFifoSize - stateParams.txCount; + + while (!stateParams.state_complete) + { + /* Execute the state. */ + switch (handle->state) + { + case (uint8_t)kSlaveStartState: + /* Emit start + 0x7E */ + I3C_MasterEmitRequest(base, kI3C_RequestAutoIbi); + handle->state = (uint8_t)kIBIWonState; + stateParams.state_complete = true; + break; + + case (uint8_t)kIBIWonState: + I3C_TransferStateMachineIBIWonState(base, handle, &stateParams); + break; + + case (uint8_t)kSendCommandState: + I3C_TransferStateMachineSendCommandState(base, handle, &stateParams); + break; + + case (uint8_t)kWaitRepeatedStartCompleteState: + I3C_TransferStateMachineWaitRepeatedStartCompleteState(base, handle, &stateParams); + break; + + case (uint8_t)kTransferDataState: + I3C_TransferStateMachineTransferDataState(base, handle, &stateParams); + break; + + case (uint8_t)kWaitForCompletionState: + I3C_TransferStateMachineWaitForCompletionState(handle, &stateParams); + break; + + case (uint8_t)kStopState: + I3C_TransferStateMachineStopState(base, handle, &stateParams); + *isDone = true; + break; + + default: + assert(false); + break; + } + } + return stateParams.result; +} + +static status_t I3C_InitTransferStateMachine(I3C_Type *base, i3c_master_handle_t *handle) +{ + i3c_master_transfer_t *xfer = &handle->transfer; + status_t result = kStatus_Success; + i3c_direction_t direction = xfer->direction; + + if (xfer->busType != kI3C_TypeI3CDdr) + { + direction = (0UL != xfer->subaddressSize) ? kI3C_Write : xfer->direction; + } + + if (0UL != (xfer->flags & (uint32_t)kI3C_TransferStartWithBroadcastAddr)) + { + if (0UL != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) + { + return kStatus_InvalidArgument; + } + + if (0UL != (xfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag)) + { + return kStatus_InvalidArgument; + } + + /* Issue 0x7E as start. */ + result = I3C_MasterStart(base, xfer->busType, 0x7E, kI3C_Write); + if (result != kStatus_Success) + { + return result; + } + + result = I3C_MasterWaitForCtrlDone(base, false); + if (result != kStatus_Success) + { + return result; + } + } + + /* Handle no start option. */ + if (0U != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) + { + /* No need to send start flag, directly go to send command or data */ + if (xfer->subaddressSize > 0UL) + { + handle->state = (uint8_t)kSendCommandState; + } + else + { + if (direction == kI3C_Write) + { + /* Next state, send data. */ + handle->state = (uint8_t)kTransferDataState; + } + else + { + /* Only support write with no stop signal. */ + return kStatus_InvalidArgument; + } + } + I3C_MasterTransferHandleIRQ(base, handle); + return result; + } + /* If repeated start is requested, send repeated start. */ + else if (0U != (xfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag)) + { + result = I3C_MasterRepeatedStart(base, xfer->busType, xfer->slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I3C_MasterStart(base, xfer->busType, xfer->slaveAddress, direction); + } + + if (xfer->subaddressSize > 0U) + { + handle->state = (uint8_t)kSendCommandState; + } + else if (xfer->dataSize != 0U) + { + handle->state = (uint8_t)kTransferDataState; + } + else + { + handle->state = (uint8_t)kStopState; + } + + if ((handle->remainingBytes < 256U) && (direction == kI3C_Read)) + { + handle->rxTermOps = (handle->rxTermOps == kI3C_RxTermDisable) ? handle->rxTermOps : kI3C_RxAutoTerm; + base->MCTRL |= I3C_MCTRL_RDTERM(handle->remainingBytes); + } + + return result; +} + +/*! + * brief Performs a non-blocking transaction on the I2C/I3C bus. + * + * param base The I3C peripheral base address. + * param handle Pointer to the I3C master driver handle. + * param transfer The pointer to the transfer descriptor. + * retval #kStatus_Success The transaction was started successfully. + * retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t I3C_MasterTransferNonBlocking(I3C_Type *base, i3c_master_handle_t *handle, i3c_master_transfer_t *transfer) +{ + assert(NULL != handle); + assert(NULL != transfer); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + i3c_master_state_t masterState = I3C_MasterGetState(base); + bool checkDdrState = false; + + /* Return busy if another transaction is in progress. */ + if (handle->state != (uint8_t)kIdleState) + { + return kStatus_I3C_Busy; + } + + /* Return an error if the bus is already in use not by us. */ + checkDdrState = (transfer->busType == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true; + if ((masterState != kI3C_MasterStateIdle) && (masterState != kI3C_MasterStateNormAct) && checkDdrState) + { + return kStatus_I3C_Busy; + } + + /* Disable I3C IRQ sources while we configure stuff. */ + I3C_MasterDisableInterrupts(base, (uint32_t)kMasterIrqFlags); + + /* Save transfer into handle. */ + handle->transfer = *transfer; + handle->remainingBytes = transfer->dataSize; + + /* Configure IBI response type. */ + base->MCTRL &= ~I3C_MCTRL_IBIRESP_MASK; + base->MCTRL |= I3C_MCTRL_IBIRESP(transfer->ibiResponse); + + /* Clear all flags. */ + I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + + if ((transfer->flags & (uint32_t)kI3C_TransferDisableRxTermFlag) != 0U) + { + handle->rxTermOps = kI3C_RxTermDisable; + } + else if (transfer->dataSize <= 255U) + { + handle->rxTermOps = kI3C_RxAutoTerm; + } + else + { + handle->rxTermOps = kI3C_RxTermLastByte; + } + + /* Generate commands to send. */ + (void)I3C_InitTransferStateMachine(base, handle); + + /* Enable I3C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + I3C_MasterEnableInterrupts(base, (uint32_t)kMasterIrqFlags); + + if (transfer->direction == kI3C_Write) + { + I3C_MasterEnableInterrupts(base, (uint32_t)kI3C_MasterTxReadyFlag); + } + + return kStatus_Success; +} + +/*! + * brief Returns number of bytes transferred so far. + * param base The I3C peripheral base address. + * param handle Pointer to the I3C master driver handle. + * param[out] count Number of bytes transferred so far by the non-blocking transaction. + * retval #kStatus_Success + * retval #kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t I3C_MasterTransferGetCount(I3C_Type *base, i3c_master_handle_t *handle, size_t *count) +{ + assert(NULL != handle); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state == (uint8_t)kIdleState) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + uint8_t state; + uint32_t remainingBytes; + uint32_t dataSize; + + /* Cache some fields with IRQs disabled. This ensures all field values */ + /* are synchronized with each other during an ongoing transfer. */ + uint32_t irqs = I3C_MasterGetEnabledInterrupts(base); + I3C_MasterDisableInterrupts(base, irqs); + state = handle->state; + remainingBytes = handle->remainingBytes; + dataSize = handle->transfer.dataSize; + I3C_MasterEnableInterrupts(base, irqs); + + /* Get transfer count based on current transfer state. */ + switch (state) + { + case (uint8_t)kIdleState: + case (uint8_t)kSendCommandState: + *count = 0; + break; + + case (uint8_t)kTransferDataState: + *count = dataSize - remainingBytes; + break; + + case (uint8_t)kStopState: + case (uint8_t)kWaitForCompletionState: + default: + *count = dataSize; + break; + } + + return kStatus_Success; +} + +/*! + * brief Terminates a non-blocking I3C master transmission early. + * + * note It is not safe to call this function from an IRQ handler that has a higher priority than the + * I3C peripheral's IRQ priority. + * + * param base The I3C peripheral base address. + * param handle Pointer to the I3C master driver handle. + * retval #kStatus_Success A transaction was successfully aborted. + * retval #kStatus_I3C_Idle There is not a non-blocking transaction currently in progress. + */ +void I3C_MasterTransferAbort(I3C_Type *base, i3c_master_handle_t *handle) +{ + if (handle->state != (uint8_t)kIdleState) + { + /* Disable internal IRQ enables. */ + I3C_MasterDisableInterrupts(base, (uint32_t)kMasterIrqFlags); + + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + + /* Send a stop command to finalize the transfer. */ + (void)I3C_MasterStop(base); + + /* Reset handle. */ + handle->state = (uint8_t)kIdleState; + } +} + +/*! + * brief Reusable routine to handle master interrupts. + * note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * param base The I3C peripheral base address. + * param intHandle Pointer to the I3C master driver handle. + */ +void I3C_MasterTransferHandleIRQ(I3C_Type *base, void *intHandle) +{ + i3c_master_handle_t *handle = (i3c_master_handle_t *)intHandle; + status_t result; + bool isDone; + + /* Don't do anything if we don't have a valid handle. */ + if (NULL == handle) + { + return; + } + + result = I3C_RunTransferStateMachine(base, handle, &isDone); + + if (handle->state == (uint8_t)kIdleState) + { + I3C_MasterDisableInterrupts(base, (uint32_t)kI3C_MasterTxReadyFlag); + return; + } + + if (isDone || (result != kStatus_Success)) + { + /* XXX need to handle data that may be in rx fifo below watermark level? */ + + /* XXX handle error, terminate xfer */ + if ((result == kStatus_I3C_Nak) || (result == kStatus_I3C_IBIWon)) + { + (void)I3C_MasterEmitStop(base, false); + } + + /* Disable internal IRQ enables. */ + I3C_MasterDisableInterrupts(base, (uint32_t)kI3C_MasterTxReadyFlag); + + /* Set handle to idle state. */ + handle->state = (uint8_t)kIdleState; + + /* Invoke IBI user callback. */ + if ((result == kStatus_I3C_IBIWon) && (handle->callback.ibiCallback != NULL)) + { + handle->callback.ibiCallback(base, handle, handle->ibiType, kI3C_IbiReady); + handle->ibiPayloadSize = 0; + } + + /* Invoke callback. */ + if (NULL != handle->callback.transferComplete) + { + handle->callback.transferComplete(base, handle, result, handle->userData); + } + } +} + +/*! + * brief Provides a default configuration for the I3C slave peripheral. + * + * This function provides the following default configuration for the I3C slave peripheral: + * code + * slaveConfig->enableslave = true; + * endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the slave driver with I3C_SlaveInit(). + * + * param[out] slaveConfig User provided configuration structure for default values. Refer to #i3c_slave_config_t. + */ +void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig) +{ + assert(NULL != slaveConfig); + + (void)memset(slaveConfig, 0, sizeof(*slaveConfig)); + + slaveConfig->enableSlave = true; +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) + slaveConfig->isHotJoin = false; +#endif + slaveConfig->vendorID = 0x11BU; +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) + slaveConfig->enableRandomPart = false; +#endif + slaveConfig->partNumber = 0; + slaveConfig->dcr = 0; /* Generic device. */ + slaveConfig->bcr = + 0; /* BCR[7:6]: device role, I3C slave(2b'00), BCR[5]: SDR Only / SDR and HDR Capable, SDR and HDR + Capable(1b'1), BCR[4]: Bridge Identifier, Not a bridge device(1b'0), BCR[3]: Offline Capable, device is + offline capable(1b'1), BCR[2]: IBI Payload, No data byte following(1b'0), BCR[1]: IBI Request Capable, + capable(1b'1), BCR[0]: Max Data Speed Limitation, has limitation(1b'1). */ + slaveConfig->hdrMode = (uint8_t)kI3C_HDRModeDDR; + slaveConfig->nakAllRequest = false; + slaveConfig->ignoreS0S1Error = true; + slaveConfig->offline = false; + slaveConfig->matchSlaveStartStop = false; + slaveConfig->maxWriteLength = 256U; + slaveConfig->maxReadLength = 256U; +} + +/*! + * brief Initializes the I3C slave peripheral. + * + * This function enables the peripheral clock and initializes the I3C slave peripheral as described by the user + * provided configuration. + * + * param base The I3C peripheral base address. + * param slaveConfig User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of + * defaults that you can override. + * param slowClock_Hz Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values. + * If FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH defines as 1, this parameter is useless. + */ +void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz) +{ + assert(NULL != slaveConfig); + assert((slowClock_Hz >= 1000000U) || (slowClock_Hz == 0U)); + + uint32_t configValue; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) || \ + !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) + uint32_t instance = I3C_GetInstance(base); +#endif + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the clock. */ + CLOCK_EnableClock(kI3cClocks[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) + /* Reset the I3C module */ + RESET_PeripheralReset(kI3cResets[instance]); +#endif + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) + uint8_t matchCount; + /* Set as (slowClk(MHz) - 1) to generate 1us clock cycle for IBI request to drive SDA low. Note: Use BAMATCH = 1 to + generate 1us clock cycle if slow clock is 1MHz. The value of 0 would not give a correct match indication. */ + if (slowClock_Hz != 0U) + { + matchCount = (uint8_t)(slowClock_Hz / 1000000UL) - 1U; + matchCount = (matchCount == 0U) ? 1U : matchCount; + } + else + { + /* BAMATCH has default value based on Soc default slow clock after reset, using this default value when slowClock_Hz is 0. */ + matchCount = (uint8_t)((base->SCONFIG & I3C_SCONFIG_BAMATCH_MASK) >> I3C_SCONFIG_BAMATCH_SHIFT); + } +#endif + + configValue = base->SCONFIG; + configValue &= + ~(I3C_SCONFIG_SADDR_MASK | +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) + I3C_SCONFIG_BAMATCH_MASK | +#endif + I3C_SCONFIG_OFFLINE_MASK | +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) + I3C_SCONFIG_IDRAND_MASK | +#endif +#if defined(FSL_FEATURE_I3C_HAS_HDROK) && FSL_FEATURE_I3C_HAS_HDROK + I3C_SCONFIG_HDROK_MASK | +#else + I3C_SCONFIG_DDROK_MASK | +#endif + I3C_SCONFIG_S0IGNORE_MASK | I3C_SCONFIG_MATCHSS_MASK | I3C_SCONFIG_NACK_MASK | I3C_SCONFIG_SLVENA_MASK); + configValue |= I3C_SCONFIG_SADDR(slaveConfig->staticAddr) | +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) + I3C_SCONFIG_BAMATCH(matchCount) | +#endif + I3C_SCONFIG_OFFLINE(slaveConfig->offline) | +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) + I3C_SCONFIG_IDRAND(slaveConfig->enableRandomPart) | +#endif +#if defined(FSL_FEATURE_I3C_HAS_HDROK) && FSL_FEATURE_I3C_HAS_HDROK + I3C_SCONFIG_HDROK((0U != (slaveConfig->hdrMode & (uint8_t)kI3C_HDRModeDDR)) ? 1U : 0U) | +#else + I3C_SCONFIG_DDROK((0U != (slaveConfig->hdrMode & (uint8_t)kI3C_HDRModeDDR)) ? 1U : 0U) | +#endif + I3C_SCONFIG_S0IGNORE(slaveConfig->ignoreS0S1Error) | + I3C_SCONFIG_MATCHSS(slaveConfig->matchSlaveStartStop) | + I3C_SCONFIG_NACK(slaveConfig->nakAllRequest) | I3C_SCONFIG_SLVENA(slaveConfig->enableSlave); + + base->SVENDORID &= ~I3C_SVENDORID_VID_MASK; + base->SVENDORID |= I3C_SVENDORID_VID(slaveConfig->vendorID); + +#if defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND + base->SIDPARTNO = slaveConfig->partNumber; +#else + if (!slaveConfig->enableRandomPart) + { + base->SIDPARTNO = slaveConfig->partNumber; + } +#endif + + base->SIDEXT &= ~(I3C_SIDEXT_BCR_MASK | I3C_SIDEXT_DCR_MASK); + base->SIDEXT |= I3C_SIDEXT_BCR(slaveConfig->bcr) | I3C_SIDEXT_DCR(slaveConfig->dcr); + + base->SMAXLIMITS &= ~(I3C_SMAXLIMITS_MAXRD_MASK | I3C_SMAXLIMITS_MAXWR_MASK); + base->SMAXLIMITS |= + (I3C_SMAXLIMITS_MAXRD(slaveConfig->maxReadLength) | I3C_SMAXLIMITS_MAXWR(slaveConfig->maxWriteLength)); + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) + if (slaveConfig->isHotJoin) + { + I3C_SlaveRequestEvent(base, kI3C_SlaveEventHotJoinReq); + } +#endif + base->SCONFIG = configValue; +} + +/*! + * brief Deinitializes the I3C master peripheral. + * + * This function disables the I3C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The I3C peripheral base address. + */ +void I3C_SlaveDeinit(I3C_Type *base) +{ + uint32_t idx = I3C_GetInstance(base); + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET) + /* Reset the I3C module */ + RESET_PeripheralReset(kI3cResets[idx]); +#endif + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate clock. */ + CLOCK_DisableClock(kI3cClocks[idx]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Reset handle pointer */ + s_i3cSlaveHandle[idx] = NULL; +} + +/*! + * @brief Gets the I3C slave state. + * + * @param base The I3C peripheral base address. + * @return I3C slave activity state, refer #i3c_slave_activity_state_t. + */ +i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base) +{ + uint8_t activeState = (uint8_t)((base->SSTATUS & I3C_SSTATUS_ACTSTATE_MASK) >> I3C_SSTATUS_ACTSTATE_SHIFT); + i3c_slave_activity_state_t returnCode; + switch (activeState) + { + case (uint8_t)kI3C_SlaveNoLatency: + returnCode = kI3C_SlaveNoLatency; + break; + case (uint8_t)kI3C_SlaveLatency1Ms: + returnCode = kI3C_SlaveLatency1Ms; + break; + case (uint8_t)kI3C_SlaveLatency100Ms: + returnCode = kI3C_SlaveLatency100Ms; + break; + case (uint8_t)kI3C_SlaveLatency10S: + returnCode = kI3C_SlaveLatency10S; + break; + default: + returnCode = kI3C_SlaveNoLatency; + break; + } + + return returnCode; +} + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) +/*! + * brief I3C slave request event. + * + * param base The I3C peripheral base address. + * param event I3C slave event of type #i3c_slave_event_t + * param data IBI data if In-band interrupt has data, only applicable for event type #kI3C_SlaveEventIBI + */ +void I3C_SlaveRequestEvent(I3C_Type *base, i3c_slave_event_t event) +{ + uint32_t ctrlValue = base->SCTRL; + + ctrlValue &= ~I3C_SCTRL_EVENT_MASK; + ctrlValue |= I3C_SCTRL_EVENT(event); + + base->SCTRL = ctrlValue; +} + +/*! + * brief I3C slave request event. + * deprecated Do not use this function. It has been superseded by @ref I3C_SlaveRequestIBIWithData. + * + * param base The I3C peripheral base address. + * param data IBI data + * param dataSize IBI data size. + */ +void I3C_SlaveRequestIBIWithSingleData(I3C_Type *base, uint8_t data, size_t dataSize) +{ + uint32_t ctrlValue = base->SCTRL; + + ctrlValue &= ~(I3C_SCTRL_EVENT_MASK | I3C_SCTRL_IBIDATA_MASK); + ctrlValue |= I3C_SCTRL_EVENT(1U) | I3C_SCTRL_IBIDATA(data); + + base->SCTRL = ctrlValue; +} + +/*! + * brief I3C slave request IBI event with data payload(mandatory and extended). + * + * param base The I3C peripheral base address. + * param data Pointer to IBI data to be sent in the request. + * param dataSize IBI data size. + */ +void I3C_SlaveRequestIBIWithData(I3C_Type *base, uint8_t *data, size_t dataSize) +{ + assert((dataSize > 0U) && (dataSize <= 8U)); + + uint32_t ctrlValue; + +#if (defined(I3C_IBIEXT1_MAX_MASK) && I3C_IBIEXT1_MAX_MASK) + if (dataSize > 1U) + { + ctrlValue = I3C_IBIEXT1_EXT1(data[1]); + if (dataSize > 2U) + { + ctrlValue |= I3C_IBIEXT1_EXT2(data[2]); + } + if (dataSize > 3U) + { + ctrlValue |= I3C_IBIEXT1_EXT3(data[3]); + } + ctrlValue |= I3C_IBIEXT1_CNT(dataSize - 1U); + base->IBIEXT1 = ctrlValue; + } + + if (dataSize > 4U) + { + ctrlValue = I3C_IBIEXT2_EXT4(data[4]); + if (dataSize > 5U) + { + ctrlValue |= I3C_IBIEXT2_EXT5(data[5]); + } + if (dataSize > 6U) + { + ctrlValue |= I3C_IBIEXT2_EXT6(data[6]); + } + if (dataSize > 7U) + { + ctrlValue |= I3C_IBIEXT2_EXT7(data[7]); + } + base->IBIEXT2 = ctrlValue; + } +#endif + + ctrlValue = base->SCTRL; +#if (defined(I3C_IBIEXT1_MAX_MASK) && I3C_IBIEXT1_MAX_MASK) + ctrlValue &= ~(I3C_SCTRL_EVENT_MASK | I3C_SCTRL_IBIDATA_MASK | I3C_SCTRL_EXTDATA_MASK); + ctrlValue |= I3C_SCTRL_EVENT(1U) | I3C_SCTRL_IBIDATA(data[0]) | I3C_SCTRL_EXTDATA(dataSize > 1U); +#else + ctrlValue &= ~(I3C_SCTRL_EVENT_MASK | I3C_SCTRL_IBIDATA_MASK); + ctrlValue |= I3C_SCTRL_EVENT(1U) | I3C_SCTRL_IBIDATA(data[0]); +#endif + base->SCTRL = ctrlValue; +} +#endif /* !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) */ + +/*! + * brief Performs a polling send transfer on the I3C bus. + * + * param base The I3C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * return Error or success status returned by API. + */ +status_t I3C_SlaveSend(I3C_Type *base, const void *txBuff, size_t txSize) +{ + const uint8_t *buf = (const uint8_t *)((const void *)txBuff); + status_t result = kStatus_Success; + + assert(NULL != txBuff); + + /* Send data buffer */ + while (0UL != txSize--) + { + /* Wait until there is room in the fifo. This also checks for errors. */ + result = I3C_SlaveWaitForTxReady(base); + if (kStatus_Success != result) + { + return result; + } + + /* Write byte into I3C slave data register. */ + if (0UL != txSize) + { + base->SWDATAB = *buf++; + } + else + { + base->SWDATABE = *buf++; + } + } + + return result; +} + +/*! + * brief Performs a polling receive transfer on the I3C bus. + * + * param base The I3C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * return Error or success status returned by API. + */ +status_t I3C_SlaveReceive(I3C_Type *base, void *rxBuff, size_t rxSize) +{ + status_t result = kStatus_Success; + uint8_t *buf; + + assert(NULL != rxBuff); + + /* Handle empty read. */ + if (0UL == rxSize) + { + return kStatus_Success; + } + +#if I3C_RETRY_TIMES + uint32_t waitTimes = I3C_RETRY_TIMES; +#endif + + /* Receive data */ + buf = (uint8_t *)rxBuff; + while (0UL != rxSize) + { +#if I3C_RETRY_TIMES + if (--waitTimes == 0) + { + return kStatus_I3C_Timeout; + } +#endif + /* Check for errors. */ + result = I3C_SlaveCheckAndClearError(base, I3C_SlaveGetErrorStatusFlags(base)); + if (kStatus_Success != result) + { + return result; + } + + /* Check RX data */ + if (0UL != (base->SDATACTRL & I3C_SDATACTRL_RXCOUNT_MASK)) + { + *buf++ = (uint8_t)(base->SRDATAB & I3C_SRDATAB_DATA0_MASK); + rxSize--; + } + } + + return result; +} + +/*! + * brief Creates a new handle for the I3C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I3C_SlaveTransferAbort() API shall be called. + * + * note The function also enables the NVIC IRQ for the input I3C. Need to notice + * that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + + * param base The I3C peripheral base address. + * param[out] handle Pointer to the I3C slave driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void I3C_SlaveTransferCreateHandle(I3C_Type *base, + i3c_slave_handle_t *handle, + i3c_slave_transfer_callback_t callback, + void *userData) +{ + uint32_t instance; + + assert(NULL != handle); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I3C_GetInstance(base); + + /* Save base and instance. */ + handle->callback = callback; + handle->userData = userData; + + /* Save Tx FIFO Size. */ + handle->txFifoSize = + 2U << ((base->SCAPABILITIES & I3C_SCAPABILITIES_FIFOTX_MASK) >> I3C_SCAPABILITIES_FIFOTX_SHIFT); + + /* Save this handle for IRQ use. */ + s_i3cSlaveHandle[instance] = handle; + + /* Set irq handler. */ + s_i3cSlaveIsr = I3C_SlaveTransferHandleIRQ; + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I3C_SlaveDisableInterrupts(base, (uint32_t)kSlaveIrqFlags); + (void)EnableIRQ(kI3cIrqs[instance]); +} + +/*! + * brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and I3C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to I3C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #i3c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI3C_SlaveTransmitEvent and #kI3C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI3C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The I3C peripheral base address. + * param handle Pointer to #i3c_slave_handle_t structure which stores the transfer state. + * param eventMask Bit mask formed by OR'ing together #i3c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI3C_SlaveAllEvents to enable all events. + * + * retval #kStatus_Success Slave transfers were successfully started. + * retval #kStatus_I3C_Busy Slave transfers have already been started on this handle. + */ +status_t I3C_SlaveTransferNonBlocking(I3C_Type *base, i3c_slave_handle_t *handle, uint32_t eventMask) +{ + assert(NULL != handle); + + /* Return busy if another transaction is in progress. */ + if (handle->isBusy) + { + return kStatus_I3C_Busy; + } + + /* Disable I3C IRQ sources while we configure stuff. */ + I3C_SlaveDisableInterrupts(base, (uint32_t)kSlaveIrqFlags); + + /* Clear transfer in handle. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Set up event mask. tx and rx are always enabled. */ + handle->eventMask = eventMask | (uint32_t)kI3C_SlaveTransmitEvent | (uint32_t)kI3C_SlaveReceiveEvent; + + /* Clear all flags. */ + I3C_SlaveClearStatusFlags(base, (uint32_t)kSlaveClearFlags); + + /* Enable I3C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + I3C_SlaveEnableInterrupts(base, (uint32_t)kSlaveIrqFlags); + + return kStatus_Success; +} + +/*! + * brief Gets the slave transfer status during a non-blocking transfer. + * param base The I3C peripheral base address. + * param handle Pointer to i2c_slave_handle_t structure. + * param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not + * required. + * retval #kStatus_Success + * retval #kStatus_NoTransferInProgress + */ +status_t I3C_SlaveTransferGetCount(I3C_Type *base, i3c_slave_handle_t *handle, size_t *count) +{ + assert(NULL != handle); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (!handle->isBusy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* For an active transfer, just return the count from the handle. */ + *count = handle->transferredCount; + + return kStatus_Success; +} + +/*! + * brief Aborts the slave non-blocking transfers. + * note This API could be called at any time to stop slave for handling the bus events. + * param base The I3C peripheral base address. + * param handle Pointer to #i3c_slave_handle_t structure which stores the transfer state. + * retval #kStatus_Success + * retval #kStatus_I3C_Idle + */ +void I3C_SlaveTransferAbort(I3C_Type *base, i3c_slave_handle_t *handle) +{ + assert(NULL != handle); + + /* Return idle if no transaction is in progress. */ + if (handle->isBusy) + { + /* Disable I3C IRQ sources. */ + I3C_SlaveDisableInterrupts(base, (uint32_t)kSlaveIrqFlags); + + /* Reset transfer info. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* We're no longer busy. */ + handle->isBusy = false; + } +} + +static bool I3C_SlaveTransferHandleGetStatusFlags(I3C_Type *base, + i3c_slave_handle_t *handle, + i3c_slave_handleIrq_param_t *stateParams) +{ + assert(NULL != base && NULL != handle && NULL != stateParams); + /* Check for a valid handle in case of a spurious interrupt. */ + uint32_t errFlags; + stateParams->flags = I3C_SlaveGetStatusFlags(base); + errFlags = I3C_SlaveGetErrorStatusFlags(base); + + stateParams->pendingInts = I3C_SlaveGetPendingInterrupts(base); + stateParams->enabledInts = I3C_SlaveGetEnabledInterrupts(base); + + if (0UL != (errFlags & (uint32_t)kSlaveErrorFlags)) + { + handle->transfer.event = (uint32_t)kI3C_SlaveCompletionEvent; + handle->transfer.completionStatus = I3C_SlaveCheckAndClearError(base, errFlags); + + if ((0UL != (handle->eventMask & (uint32_t)kI3C_SlaveCompletionEvent)) && (NULL != handle->callback)) + { + handle->callback(base, &handle->transfer, handle->userData); + } + return false; + } + return true; +} + +static void I3C_SlaveTransferHandleBusStart(I3C_Type *base, i3c_slave_transfer_t *xfer, uint32_t *pendingInts) +{ + base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK; + xfer->txDataSize = 0; + I3C_SlaveEnableInterrupts(base, (uint32_t)kI3C_SlaveTxReadyFlag); + (*pendingInts) |= (uint32_t)kI3C_SlaveTxReadyFlag; +} + +static void I3C_SlaveTransferHandleEventSent(I3C_Type *base, i3c_slave_handle_t *handle, i3c_slave_transfer_t *xfer) +{ + xfer->event = (uint32_t)kI3C_SlaveRequestSentEvent; + if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } +} + +static void I3C_SlaveTransferHandleReceivedCCC(I3C_Type *base, i3c_slave_handle_t *handle, i3c_slave_transfer_t *xfer) +{ + handle->isBusy = true; + xfer->event = (uint32_t)kI3C_SlaveReceivedCCCEvent; + if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } +} + +static void I3C_SlaveTransferHandleBusStop(I3C_Type *base, + i3c_slave_handle_t *handle, + i3c_slave_handleIrq_param_t *stateParams) +{ + assert(NULL != base && NULL != handle && NULL != stateParams); + I3C_SlaveDisableInterrupts(base, (uint32_t)kI3C_SlaveTxReadyFlag); + stateParams->pendingInts &= ~(uint32_t)kI3C_SlaveTxReadyFlag; + base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK | I3C_SDATACTRL_FLUSHFB_MASK; + if (handle->isBusy) + { + handle->transfer.event = (uint32_t)kI3C_SlaveCompletionEvent; + handle->transfer.completionStatus = kStatus_Success; + handle->transfer.transferredCount = handle->transferredCount; + handle->isBusy = false; + + if (handle->wasTransmit) + { + /* Subtract one from the transmit count to offset the fact that I3C asserts the */ + /* tx flag before it sees the nack from the master-receiver, thus causing one more */ + /* count that the master actually receives. */ + --handle->transfer.transferredCount; + handle->wasTransmit = false; + } + + if ((0UL != (handle->eventMask & handle->transfer.event)) && (NULL != handle->callback)) + { + handle->callback(base, &handle->transfer, handle->userData); + } + + /* Clean up transfer info on completion, after the callback has been invoked. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + } +} + +static void I3C_SlaveTransferHandleMatched(I3C_Type *base, i3c_slave_handle_t *handle, i3c_slave_transfer_t *xfer) +{ + assert(NULL != base && NULL != handle && NULL != xfer); + xfer->event = (uint32_t)kI3C_SlaveAddressMatchEvent; + handle->isBusy = true; + if ((0UL != (handle->eventMask & (uint32_t)kI3C_SlaveAddressMatchEvent)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } +} + +static void I3C_SlaveTransferHandleTxReady(I3C_Type *base, + i3c_slave_handle_t *handle, + i3c_slave_handleIrq_param_t *stateParams) +{ + assert(NULL != base && NULL != handle && NULL != stateParams); + handle->wasTransmit = true; + + /* If we're out of data, invoke callback to get more. */ + if ((NULL == handle->transfer.txData) || (0UL == handle->transfer.txDataSize)) + { + handle->transfer.event = (uint32_t)kI3C_SlaveTransmitEvent; + if (0UL != (stateParams->flags & (uint32_t)kI3C_SlaveBusHDRModeFlag)) + { + handle->transfer.event |= (uint32_t)kI3C_SlaveHDRCommandMatchEvent; + handle->isBusy = true; + } + if (NULL != handle->callback) + { + handle->callback(base, &handle->transfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + handle->transferredCount = 0; + } + + if ((NULL == handle->transfer.txData) || (0UL == handle->transfer.txDataSize)) + { + I3C_SlaveDisableInterrupts(base, (uint32_t)kI3C_SlaveTxReadyFlag); + (stateParams->pendingInts) &= ~(uint32_t)kI3C_SlaveTxReadyFlag; + } + + /* Transmit a byte. */ + while ((handle->transfer.txDataSize != 0UL) && ((stateParams->txCount) != 0U)) + { + if (handle->transfer.txDataSize > 1UL) + { + base->SWDATAB = *handle->transfer.txData++; + } + else + { + base->SWDATABE = *handle->transfer.txData++; + I3C_SlaveDisableInterrupts(base, (uint32_t)kI3C_SlaveTxReadyFlag); + } + --(handle->transfer.txDataSize); + ++(handle->transferredCount); + (stateParams->txCount)--; + } +} + +static void I3C_SlaveTransferHandleRxReady(I3C_Type *base, + i3c_slave_handle_t *handle, + i3c_slave_handleIrq_param_t *stateParams) +{ + assert(NULL != base && NULL != handle && NULL != stateParams); + /* If we're out of room in the buffer, invoke callback to get another. */ + if ((NULL == handle->transfer.rxData) || (0UL == handle->transfer.rxDataSize)) + { + handle->transfer.event = (uint32_t)kI3C_SlaveReceiveEvent; + if (0UL != (stateParams->flags & (uint32_t)kI3C_SlaveBusHDRModeFlag)) + { + handle->transfer.event |= (uint32_t)kI3C_SlaveHDRCommandMatchEvent; + handle->isBusy = true; + } + if (NULL != handle->callback) + { + handle->callback(base, &handle->transfer, handle->userData); + } + handle->transferredCount = 0; + } + /* Receive a byte. */ + while ((stateParams->rxCount != 0U) && ((handle->transfer.rxData != NULL) && (handle->transfer.rxDataSize != 0UL))) + { + *(handle->transfer.rxData++) = (uint8_t)base->SRDATAB; + --(handle->transfer.rxDataSize); + ++(handle->transferredCount); + (stateParams->rxCount)--; + } +} + +/*! + * brief Reusable routine to handle slave interrupts. + * note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * param base The I3C peripheral base address. + * param intHandle Pointer to #i3c_slave_handle_t structure which stores the transfer state. + */ +void I3C_SlaveTransferHandleIRQ(I3C_Type *base, void *intHandle) +{ + i3c_slave_handleIrq_param_t stateParams; + + (void)memset(&stateParams, 0, sizeof(stateParams)); + i3c_slave_handle_t *handle = (i3c_slave_handle_t *)intHandle; + + /* Check for a valid handle in case of a spurious interrupt. */ + if (NULL == handle) + { + return; + } + + /* Get status flags. */ + if (false == I3C_SlaveTransferHandleGetStatusFlags(base, handle, &stateParams)) + { + return; + } + + /* Clear status flags. */ + I3C_SlaveClearStatusFlags(base, stateParams.flags); + + if (0UL != (stateParams.flags & (uint32_t)kI3C_SlaveBusStartFlag)) + { + I3C_SlaveTransferHandleBusStart(base, &handle->transfer, &stateParams.pendingInts); + } + + if (0UL != (stateParams.flags & (uint32_t)kI3C_SlaveEventSentFlag)) + { + I3C_SlaveTransferHandleEventSent(base, handle, &handle->transfer); + } + + if (0UL != (stateParams.flags & (uint32_t)kI3C_SlaveReceivedCCCFlag)) + { + I3C_SlaveTransferHandleReceivedCCC(base, handle, &handle->transfer); + } + + if (0UL != (stateParams.flags & (uint32_t)kI3C_SlaveMatchedFlag)) + { + I3C_SlaveTransferHandleMatched(base, handle, &handle->transfer); + } + + /* Get fifo counts and compute room in tx fifo. */ + I3C_SlaveGetFifoCounts(base, &stateParams.rxCount, &stateParams.txCount); + stateParams.txCount = handle->txFifoSize - stateParams.txCount; + + /* Handle transmit and receive. */ + if ((0UL != (stateParams.flags & (uint32_t)kI3C_SlaveTxReadyFlag)) && + (0UL != (stateParams.pendingInts & (uint32_t)kI3C_SlaveTxReadyFlag))) + { + I3C_SlaveTransferHandleTxReady(base, handle, &stateParams); + } + + if ((0UL != (stateParams.flags & (uint32_t)kI3C_SlaveRxReadyFlag)) && + (0UL != (stateParams.enabledInts & (uint32_t)kI3C_SlaveRxReadyFlag))) + { + I3C_SlaveTransferHandleRxReady(base, handle, &stateParams); + } + + /* Handle stop event. */ + if (0UL != (stateParams.flags & (uint32_t)kI3C_SlaveBusStopFlag)) + { + I3C_SlaveTransferHandleBusStop(base, handle, &stateParams); + } +} + +static void I3C_CommonIRQHandler(I3C_Type *base, uint32_t instance) +{ + /* Check for master IRQ. */ + if (((uint32_t)kI3C_MasterOn == (base->MCONFIG & I3C_MCONFIG_MSTENA_MASK)) && (NULL != s_i3cMasterIsr)) + { + /* Master mode. */ + s_i3cMasterIsr(base, s_i3cMasterHandle[instance]); + } + + /* Check for slave IRQ. */ + if ((I3C_SCONFIG_SLVENA_MASK == (base->SCONFIG & I3C_SCONFIG_SLVENA_MASK)) && (NULL != s_i3cSlaveIsr)) + { + /* Slave mode. */ + s_i3cSlaveIsr(base, s_i3cSlaveHandle[instance]); + } + SDK_ISR_EXIT_BARRIER; +} + +#if defined(I3C) +/* Implementation of I3C handler named in startup code. */ +void I3C0_DriverIRQHandler(void); +void I3C0_DriverIRQHandler(void) +{ + I3C_CommonIRQHandler(I3C, 0); +} +#endif + +#if defined(I3C0) +/* Implementation of I3C0 handler named in startup code. */ +void I3C0_DriverIRQHandler(void); +void I3C0_DriverIRQHandler(void) +{ + I3C_CommonIRQHandler(I3C0, 0); +} +#endif + +#if defined(I3C1) +/* Implementation of I3C1 handler named in startup code. */ +void I3C1_DriverIRQHandler(void); +void I3C1_DriverIRQHandler(void) +{ + I3C_CommonIRQHandler(I3C1, 1); +} +#endif + +#if defined(I3C2) +/* Implementation of I3C2 handler named in startup code. */ +void I3C2_DriverIRQHandler(void); +void I3C2_DriverIRQHandler(void) +{ + I3C_CommonIRQHandler(I3C2, 2); +} +#endif + +#if defined(I3C3) +/* Implementation of I3C3 handler named in startup code. */ +void I3C3_DriverIRQHandler(void); +void I3C3_DriverIRQHandler(void) +{ + I3C_CommonIRQHandler(I3C3, 3); +} +#endif diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_i3c.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_i3c.h new file mode 100644 index 00000000000..2a3b5dae82f --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_i3c.h @@ -0,0 +1,1899 @@ +/* + * Copyright 2018-2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_I3C_H_ +#define FSL_I3C_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup i3c + * @{ + */ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief I3C driver version */ +#define FSL_I3C_DRIVER_VERSION (MAKE_VERSION(2, 12, 0)) +/*! @} */ + +/*! @brief Timeout times for waiting flag. */ +#ifndef I3C_RETRY_TIMES +#define I3C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +#define I3C_MAX_DEVCNT 10U + +#ifndef I3C_IBI_BUFF_SIZE +#define I3C_IBI_BUFF_SIZE 10U +#endif + +/*! @brief I3C status return codes. */ +enum +{ + kStatus_I3C_Busy = MAKE_STATUS(kStatusGroup_I3C, 0), /*!< The master is already performing a transfer. */ + kStatus_I3C_Idle = MAKE_STATUS(kStatusGroup_I3C, 1), /*!< The slave driver is idle. */ + kStatus_I3C_Nak = MAKE_STATUS(kStatusGroup_I3C, 2), /*!< The slave device sent a NAK in response to an address. */ + kStatus_I3C_WriteAbort = + MAKE_STATUS(kStatusGroup_I3C, 3), /*!< The slave device sent a NAK in response to a write. */ + kStatus_I3C_Term = MAKE_STATUS(kStatusGroup_I3C, 4), /*!< The master terminates slave read. */ + kStatus_I3C_HdrParityError = MAKE_STATUS(kStatusGroup_I3C, 5), /*!< Parity error from DDR read. */ + kStatus_I3C_CrcError = MAKE_STATUS(kStatusGroup_I3C, 6), /*!< CRC error from DDR read. */ + kStatus_I3C_ReadFifoError = MAKE_STATUS(kStatusGroup_I3C, 7), /*!< Read from M/SRDATAB register when FIFO empty. */ + kStatus_I3C_WriteFifoError = MAKE_STATUS(kStatusGroup_I3C, 8), /*!< Write to M/SWDATAB register when FIFO full. */ + kStatus_I3C_MsgError = + MAKE_STATUS(kStatusGroup_I3C, 9), /*!< Message SDR/DDR mismatch or read/write message in wrong state */ + kStatus_I3C_InvalidReq = MAKE_STATUS(kStatusGroup_I3C, 10), /*!< Invalid use of request. */ + kStatus_I3C_Timeout = MAKE_STATUS(kStatusGroup_I3C, 11), /*!< The module has stalled too long in a frame. */ + kStatus_I3C_SlaveCountExceed = + MAKE_STATUS(kStatusGroup_I3C, 12), /*!< The I3C slave count has exceed the definition in I3C_MAX_DEVCNT. */ + kStatus_I3C_IBIWon = MAKE_STATUS( + kStatusGroup_I3C, 13), /*!< The I3C slave event IBI or MR or HJ won the arbitration on a header address. */ + kStatus_I3C_OverrunError = MAKE_STATUS(kStatusGroup_I3C, 14), /*!< Slave internal from-bus buffer/FIFO overrun. */ + kStatus_I3C_UnderrunError = MAKE_STATUS(kStatusGroup_I3C, 15), /*!< Slave internal to-bus buffer/FIFO underrun */ + kStatus_I3C_UnderrunNak = + MAKE_STATUS(kStatusGroup_I3C, 16), /*!< Slave internal from-bus buffer/FIFO underrun and NACK error */ + kStatus_I3C_InvalidStart = MAKE_STATUS(kStatusGroup_I3C, 17), /*!< Slave invalid start flag */ + kStatus_I3C_SdrParityError = MAKE_STATUS(kStatusGroup_I3C, 18), /*!< SDR parity error */ + kStatus_I3C_S0S1Error = MAKE_STATUS(kStatusGroup_I3C, 19), /*!< S0 or S1 error */ +}; + +/*! @brief I3C HDR modes. */ +typedef enum _i3c_hdr_mode +{ + kI3C_HDRModeNone = 0x00U, /* Do not support HDR mode. */ + kI3C_HDRModeDDR = 0x01U, /* HDR-DDR Mode. */ + kI3C_HDRModeTSP = 0x02U, /* HDR-TSP Mode. */ + kI3C_HDRModeTSL = 0x04U, /* HDR-TSL Mode. */ +} i3c_hdr_mode_t; + +/*! @brief I3C device information. */ +typedef struct _i3c_device_info +{ + uint8_t dynamicAddr; /*!< Device dynamic address. */ + uint8_t staticAddr; /*!< Static address. */ + uint8_t dcr; /*!< Device characteristics register information. */ + uint8_t bcr; /*!< Bus characteristics register information. */ + uint16_t vendorID; /*!< Device vendor ID(manufacture ID). */ + uint32_t partNumber; /*!< Device part number info */ + uint16_t maxReadLength; /*!< Maximum read length. */ + uint16_t maxWriteLength; /*!< Maximum write length. */ + uint8_t hdrMode; /*!< Support hdr mode, could be OR logic in i3c_hdr_mode. */ +} i3c_device_info_t; + +/*! @} */ + +/*! + * @addtogroup i3c_master_driver + * @{ + */ + +/*! + * @brief I3C master peripheral flags. + * + * The following status register flags can be cleared: + * - #kI3C_MasterSlaveStartFlag + * - #kI3C_MasterControlDoneFlag + * - #kI3C_MasterCompleteFlag + * - #kI3C_MasterArbitrationWonFlag + * - #kI3C_MasterSlave2MasterFlag + * + * All flags except #kI3C_MasterBetweenFlag and #kI3C_MasterNackDetectFlag can be enabled as + * interrupts. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _i3c_master_flags +{ + kI3C_MasterBetweenFlag = I3C_MSTATUS_BETWEEN_MASK, /*!< Between messages/DAAs flag */ + kI3C_MasterNackDetectFlag = I3C_MSTATUS_NACKED_MASK, /*!< NACK detected flag */ + kI3C_MasterSlaveStartFlag = I3C_MSTATUS_SLVSTART_MASK, /*!< Slave request start flag */ + kI3C_MasterControlDoneFlag = I3C_MSTATUS_MCTRLDONE_MASK, /*!< Master request complete flag */ + kI3C_MasterCompleteFlag = I3C_MSTATUS_COMPLETE_MASK, /*!< Transfer complete flag */ + kI3C_MasterRxReadyFlag = I3C_MSTATUS_RXPEND_MASK, /*!< Rx data ready in Rx buffer flag */ + kI3C_MasterTxReadyFlag = I3C_MSTATUS_TXNOTFULL_MASK, /*!< Tx buffer ready for Tx data flag */ + kI3C_MasterArbitrationWonFlag = I3C_MSTATUS_IBIWON_MASK, /*!< Header address won arbitration flag */ + kI3C_MasterErrorFlag = I3C_MSTATUS_ERRWARN_MASK, /*!< Error occurred flag */ + kI3C_MasterSlave2MasterFlag = I3C_MSTATUS_NOWMASTER_MASK, /*!< Switch from slave to master flag */ + kI3C_MasterClearFlags = kI3C_MasterSlaveStartFlag | kI3C_MasterControlDoneFlag | kI3C_MasterCompleteFlag | + kI3C_MasterArbitrationWonFlag | kI3C_MasterSlave2MasterFlag | kI3C_MasterErrorFlag, +}; + +/*! + * @brief I3C master error flags to indicate the causes. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _i3c_master_error_flags +{ + kI3C_MasterErrorNackFlag = I3C_MERRWARN_NACK_MASK, /*!< Slave NACKed the last address */ + kI3C_MasterErrorWriteAbortFlag = I3C_MERRWARN_WRABT_MASK, /*!< Slave NACKed the write data */ +#if !defined(FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) || (!FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) + kI3C_MasterErrorTermFlag = I3C_MERRWARN_TERM_MASK, /*!< Master terminates slave read */ +#endif + kI3C_MasterErrorParityFlag = I3C_MERRWARN_HPAR_MASK, /*!< Parity error from DDR read */ + kI3C_MasterErrorCrcFlag = I3C_MERRWARN_HCRC_MASK, /*!< CRC error from DDR read */ + kI3C_MasterErrorReadFlag = I3C_MERRWARN_OREAD_MASK, /*!< Read from MRDATAB register when FIFO empty */ + kI3C_MasterErrorWriteFlag = I3C_MERRWARN_OWRITE_MASK, /*!< Write to MWDATAB register when FIFO full */ + kI3C_MasterErrorMsgFlag = I3C_MERRWARN_MSGERR_MASK, /*!< Message SDR/DDR mismatch or + read/write message in wrong state */ + kI3C_MasterErrorInvalidReqFlag = I3C_MERRWARN_INVREQ_MASK, /*!< Invalid use of request */ + kI3C_MasterErrorTimeoutFlag = I3C_MERRWARN_TIMEOUT_MASK, /*!< The module has stalled too long in a frame */ + kI3C_MasterAllErrorFlags = kI3C_MasterErrorNackFlag | kI3C_MasterErrorWriteAbortFlag | +#if !defined(FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) || (!FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) + kI3C_MasterErrorTermFlag | +#endif + kI3C_MasterErrorParityFlag | kI3C_MasterErrorCrcFlag | kI3C_MasterErrorReadFlag | + kI3C_MasterErrorWriteFlag | kI3C_MasterErrorMsgFlag | kI3C_MasterErrorInvalidReqFlag | + kI3C_MasterErrorTimeoutFlag, /*!< All error flags */ +}; + +/*! @brief I3C working master state. */ +typedef enum _i3c_master_state +{ + kI3C_MasterStateIdle = 0U, /*!< Bus stopped. */ + kI3C_MasterStateSlvReq = 1U, /*!< Bus stopped but slave holding SDA low. */ + kI3C_MasterStateMsgSdr = 2U, /*!< In SDR Message mode from using MWMSG_SDR. */ + kI3C_MasterStateNormAct = 3U, /*!< In normal active SDR mode. */ + kI3C_MasterStateDdr = 4U, /*!< In DDR Message mode. */ + kI3C_MasterStateDaa = 5U, /*!< In ENTDAA mode. */ + kI3C_MasterStateIbiAck = 6U, /*!< Waiting on IBI ACK/NACK decision. */ + kI3C_MasterStateIbiRcv = 7U, /*!< receiving IBI. */ +} i3c_master_state_t; + +/*! @brief I3C master enable configuration. */ +typedef enum _i3c_master_enable +{ + kI3C_MasterOff = 0U, /*!< Master off. */ + kI3C_MasterOn = 1U, /*!< Master on. */ + kI3C_MasterCapable = 2U /*!< Master capable. */ +} i3c_master_enable_t; + +/*! @brief I3C high keeper configuration. */ +typedef enum _i3c_master_hkeep +{ + kI3C_MasterHighKeeperNone = 0U, /*!< Use PUR to hold SCL high. */ + kI3C_MasterHighKeeperWiredIn = 1U, /*!< Use pin_HK controls. */ + kI3C_MasterPassiveSDA = 2U, /*!< Hi-Z for Bus Free and hold SDA. */ + kI3C_MasterPassiveSDASCL = 3U /*!< Hi-Z both for Bus Free, and can Hi-Z SDA for hold. */ +} i3c_master_hkeep_t; + +/*! @brief Emits the requested operation when doing in pieces vs. by message. */ +typedef enum _i3c_bus_request +{ + kI3C_RequestNone = 0U, /*!< No request. */ + kI3C_RequestEmitStartAddr = 1U, /*!< Request to emit start and address on bus. */ + kI3C_RequestEmitStop = 2U, /*!< Request to emit stop on bus. */ + kI3C_RequestIbiAckNack = 3U, /*!< Manual IBI ACK or NACK. */ + kI3C_RequestProcessDAA = 4U, /*!< Process DAA. */ + kI3C_RequestForceExit = 6U, /*!< Request to force exit. */ + kI3C_RequestAutoIbi = 7U, /*!< Hold in stopped state, but Auto-emit START,7E. */ +} i3c_bus_request_t; + +/*! @brief Bus type with EmitStartAddr. */ +typedef enum _i3c_bus_type +{ + kI3C_TypeI3CSdr = 0U, /*!< SDR mode of I3C. */ + kI3C_TypeI2C = 1U, /*!< Standard i2c protocol. */ + kI3C_TypeI3CDdr = 2U, /*!< HDR-DDR mode of I3C. */ +} i3c_bus_type_t; + +/*! @brief IBI response. */ +typedef enum _i3c_ibi_response +{ + kI3C_IbiRespAck = 0U, /*!< ACK with no mandatory byte. */ + kI3C_IbiRespNack = 1U, /*!< NACK. */ + kI3C_IbiRespAckMandatory = 2U, /*!< ACK with mandatory byte. */ + kI3C_IbiRespManual = 3U, /*!< Reserved. */ +} i3c_ibi_response_t; + +/*! @brief IBI type. */ +typedef enum _i3c_ibi_type +{ + kI3C_IbiNormal = 0U, /*!< In-band interrupt. */ + kI3C_IbiHotJoin = 1U, /*!< slave hot join. */ + kI3C_IbiMasterRequest = 2U, /*!< slave master ship request. */ +} i3c_ibi_type_t; + +/*! @brief IBI state. */ +typedef enum _i3c_ibi_state +{ + kI3C_IbiReady = 0U, /*!< In-band interrupt ready state, ready for user to handle. */ + kI3C_IbiDataBuffNeed = 1U, /*!< In-band interrupt need data buffer for data receive. */ + kI3C_IbiAckNackPending = 2U, /*!< In-band interrupt Ack/Nack pending for decision. */ +} i3c_ibi_state_t; + +/*! @brief Direction of master and slave transfers. */ +typedef enum _i3c_direction +{ + kI3C_Write = 0U, /*!< Master transmit. */ + kI3C_Read = 1U /*!< Master receive. */ +} i3c_direction_t; + +/*! @brief Watermark of TX int/dma trigger level. */ +typedef enum _i3c_tx_trigger_level +{ + kI3C_TxTriggerOnEmpty = 0U, /*!< Trigger on empty. */ + kI3C_TxTriggerUntilOneQuarterOrLess = 1U, /*!< Trigger on 1/4 full or less. */ + kI3C_TxTriggerUntilOneHalfOrLess = 2U, /*!< Trigger on 1/2 full or less. */ + kI3C_TxTriggerUntilOneLessThanFull = 3U, /*!< Trigger on 1 less than full or less. */ +} i3c_tx_trigger_level_t; + +/*! @brief Watermark of RX int/dma trigger level. */ +typedef enum _i3c_rx_trigger_level +{ + kI3C_RxTriggerOnNotEmpty = 0U, /*!< Trigger on not empty. */ + kI3C_RxTriggerUntilOneQuarterOrMore = 1U, /*!< Trigger on 1/4 full or more. */ + kI3C_RxTriggerUntilOneHalfOrMore = 2U, /*!< Trigger on 1/2 full or more. */ + kI3C_RxTriggerUntilThreeQuarterOrMore = 3U, /*!< Trigger on 3/4 full or more. */ +} i3c_rx_trigger_level_t; + +/*! @brief I3C master read termination operations. */ +typedef enum _i3c_rx_term_ops +{ + kI3C_RxTermDisable = 0U, /*!< Master doesn't terminate read, used for CCC transfer. */ + kI3C_RxAutoTerm = 1U, /*!< Master auto terminate read after receiving specified bytes(<=255). */ + kI3C_RxTermLastByte = 2U, /*!< Master terminates read at any time after START, no length limitation. */ +} i3c_rx_term_ops_t; + +/*! @brief I3C start SCL delay options. */ +typedef enum _i3c_start_scl_delay +{ + kI3C_NoDelay = 0U, /*!< No delay. */ + kI3C_IncreaseSclHalfPeriod = 1U, /*!< Increases SCL clock period by 1/2. */ + kI3C_IncreaseSclOnePeriod = 2U, /*!< Increases SCL clock period by 1. */ + kI3C_IncreaseSclOneAndHalfPeriod = 3U, /*!< Increases SCL clock period by 1 1/2 */ +} i3c_start_scl_delay_t; + +/*! @brief Structure with setting master IBI rules and slave registry. */ +typedef struct _i3c_register_ibi_addr +{ + uint8_t address[5]; /*!< Address array for registry. */ + bool ibiHasPayload; /*!< Whether the address array has mandatory IBI byte. */ +} i3c_register_ibi_addr_t; + +/*! @brief Structure with I3C baudrate settings. */ +typedef struct _i3c_baudrate +{ + uint32_t i2cBaud; /*!< Desired I2C baud rate in Hertz. */ + uint32_t i3cPushPullBaud; /*!< Desired I3C push-pull baud rate in Hertz. */ + uint32_t i3cOpenDrainBaud; /*!< Desired I3C open-drain baud rate in Hertz. */ +} i3c_baudrate_hz_t; + +/*! @brief I3C DAA baud rate configuration. */ +typedef struct _i3c_master_daa_baudrate +{ + uint32_t sourceClock_Hz; /*!< FCLK, function clock in Hertz. */ + uint32_t i3cPushPullBaud; /*!< Desired I3C push-pull baud rate in Hertz. */ + uint32_t i3cOpenDrainBaud; /*!< Desired I3C open-drain baud rate in Hertz. */ +} i3c_master_daa_baudrate_t; + +/*! + * @brief Structure with settings to initialize the I3C master module. + * + * This structure holds configuration settings for the I3C peripheral. To initialize this + * structure to reasonable defaults, call the I3C_MasterGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _i3c_master_config +{ + i3c_master_enable_t enableMaster; /*!< Enable master mode. */ + bool disableTimeout; /*!< Whether to disable timeout to prevent the ERRWARN. */ + i3c_master_hkeep_t hKeep; /*!< High keeper mode setting. */ + bool enableOpenDrainStop; /*!< Whether to emit open-drain speed STOP. */ + bool enableOpenDrainHigh; /*!< Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD. */ + i3c_baudrate_hz_t baudRate_Hz; /*!< Desired baud rate settings. */ +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) + uint32_t slowClock_Hz; /*!< Slow clock frequency. */ +#endif +#if defined(FSL_FEATURE_I3C_HAS_START_SCL_DELAY) && FSL_FEATURE_I3C_HAS_START_SCL_DELAY + i3c_start_scl_delay_t startSclDelay; /*!< I3C SCL delay after START. */ + i3c_start_scl_delay_t restartSclDelay; /*!< I3C SCL delay after Repeated START. */ +#endif +} i3c_master_config_t; + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +typedef struct _i3c_master_transfer i3c_master_transfer_t; +typedef struct _i3c_master_handle i3c_master_handle_t; + +/*! @brief i3c master callback functions. */ +typedef struct _i3c_master_transfer_callback +{ + void (*slave2Master)(I3C_Type *base, void *userData); /*!< Transfer complete callback */ + void (*ibiCallback)(I3C_Type *base, + i3c_master_handle_t *handle, + i3c_ibi_type_t ibiType, + i3c_ibi_state_t ibiState); /*!< IBI event callback */ + void (*transferComplete)(I3C_Type *base, + i3c_master_handle_t *handle, + status_t completionStatus, + void *userData); /*!< Transfer complete callback */ +} i3c_master_transfer_callback_t; +/*! + * @brief Transfer option flags. + * + * @note These enumerations are intended to be OR'd together to form a bit mask of options for + * the #_i3c_master_transfer::flags field. + */ +enum _i3c_master_transfer_flags +{ + kI3C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ + kI3C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ + kI3C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ + kI3C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ + kI3C_TransferWordsFlag = 0x08U, /*!< Transfer in words, else transfer in bytes. */ + kI3C_TransferDisableRxTermFlag = 0x10U, /*!< Disable Rx termination. Note: It's for I3C CCC transfer. */ + kI3C_TransferRxAutoTermFlag = + 0x20U, /*!< Set Rx auto-termination. Note: It's adaptive based on Rx size(<=255 bytes) except in I3C_MasterReceive. */ + kI3C_TransferStartWithBroadcastAddr = 0x40U, /*!< Start transfer with 0x7E, then read/write data with device address. */ +}; + +/*! + * @brief Non-blocking transfer descriptor structure. + * + * This structure is used to pass transaction parameters to the I3C_MasterTransferNonBlocking() API. + */ +struct _i3c_master_transfer +{ + uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available + options. Set to 0 or #kI3C_TransferDefaultFlag for normal transfers. */ + uint8_t slaveAddress; /*!< The 7-bit slave address. */ + i3c_direction_t direction; /*!< Either #kI3C_Read or #kI3C_Write. */ + uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ + size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ + void *data; /*!< Pointer to data to transfer. */ + size_t dataSize; /*!< Number of bytes to transfer. */ + i3c_bus_type_t busType; /*!< bus type. */ + i3c_ibi_response_t ibiResponse; /*!< ibi response during transfer. */ +}; + +/*! + * @brief Driver handle for master non-blocking APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _i3c_master_handle +{ + uint8_t state; /*!< Transfer state machine current state. */ + uint32_t remainingBytes; /*!< Remaining byte count in current state. */ + i3c_rx_term_ops_t rxTermOps; /*!< Read termination operation. */ + i3c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + uint8_t ibiAddress; /*!< Slave address which request IBI. */ + uint8_t *ibiBuff; /*!< Pointer to IBI buffer to keep ibi bytes. */ + size_t ibiPayloadSize; /*!< IBI payload size. */ + i3c_ibi_type_t ibiType; /*!< IBI type. */ + i3c_master_transfer_callback_t callback; /*!< Callback functions pointer. */ + void *userData; /*!< Application data passed to callback. */ +}; + +/*! @brief Typedef for master interrupt handler. */ +typedef void (*i3c_master_isr_t)(I3C_Type *base, void *handle); + +/*! @} */ + +/*! + * @addtogroup i3c_slave_driver + * @{ + */ + +/*! + * @brief I3C slave peripheral flags. + * + * The following status register flags can be cleared: + * - #kI3C_SlaveBusStartFlag + * - #kI3C_SlaveMatchedFlag + * - #kI3C_SlaveBusStopFlag + * + * Only below flags can be enabled as interrupts. + * - #kI3C_SlaveBusStartFlag + * - #kI3C_SlaveMatchedFlag + * - #kI3C_SlaveBusStopFlag + * - #kI3C_SlaveRxReadyFlag + * - #kI3C_SlaveTxReadyFlag + * - #kI3C_SlaveDynamicAddrChangedFlag + * - #kI3C_SlaveReceivedCCCFlag + * - #kI3C_SlaveErrorFlag + * - #kI3C_SlaveHDRCommandMatchFlag + * - #kI3C_SlaveCCCHandledFlag + * - #kI3C_SlaveEventSentFlag + + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _i3c_slave_flags +{ + kI3C_SlaveNotStopFlag = I3C_SSTATUS_STNOTSTOP_MASK, /*!< Slave status not stop flag */ + kI3C_SlaveMessageFlag = I3C_SSTATUS_STMSG_MASK, /*!< Slave status message, indicating slave is + listening to the bus traffic or responding */ + kI3C_SlaveRequiredReadFlag = I3C_SSTATUS_STREQRD_MASK, /*!< Slave status required, either is master doing SDR + read from slave, or is IBI pushing out. */ + kI3C_SlaveRequiredWriteFlag = I3C_SSTATUS_STREQWR_MASK, /*!< Slave status request write, master is doing SDR + write to slave, except slave in ENTDAA mode */ + kI3C_SlaveBusDAAFlag = I3C_SSTATUS_STDAA_MASK, /*!< I3C bus is in ENTDAA mode */ + kI3C_SlaveBusHDRModeFlag = I3C_SSTATUS_STHDR_MASK, /*!< I3C bus is in HDR mode */ + kI3C_SlaveBusStartFlag = I3C_SSTATUS_START_MASK, /*!< Start/Re-start event is seen since the bus was last cleared */ + kI3C_SlaveMatchedFlag = I3C_SSTATUS_MATCHED_MASK, /*!< Slave address(dynamic/static) matched since last cleared */ + kI3C_SlaveBusStopFlag = I3C_SSTATUS_STOP_MASK, /*!enableMaster = kI3C_MasterCapable; + * config->disableTimeout = false; + * config->hKeep = kI3C_MasterHighKeeperNone; + * config->enableOpenDrainStop = true; + * config->enableOpenDrainHigh = true; + * config->baudRate_Hz.i2cBaud = 400000U; + * config->baudRate_Hz.i3cPushPullBaud = 12500000U; + * config->baudRate_Hz.i3cOpenDrainBaud = 2500000U; + * config->masterDynamicAddress = 0x0AU; + * config->slowClock_Hz = 1000000U; + * config->enableSlave = true; + * config->vendorID = 0x11BU; + * config->enableRandomPart = false; + * config->partNumber = 0; + * config->dcr = 0; + * config->bcr = 0; + * config->hdrMode = (uint8_t)kI3C_HDRModeDDR; + * config->nakAllRequest = false; + * config->ignoreS0S1Error = false; + * config->offline = false; + * config->matchSlaveStartStop = false; + * @endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the common I3C driver with I3C_Init(). + * + * @param[out] config User provided configuration structure for default values. Refer to #i3c_config_t. + */ +void I3C_GetDefaultConfig(i3c_config_t *config); + +/*! + * @brief Initializes the I3C peripheral. + * This function enables the peripheral clock and initializes the I3C peripheral as described by the user + * provided configuration. This will initialize both the master peripheral and slave peripheral so that I3C + * module could work as pure master, pure slave or secondary master, etc. + * A software reset is performed prior to configuration. + * + * @param base The I3C peripheral base address. + * @param config User provided peripheral configuration. Use I3C_GetDefaultConfig() to get a set of + * defaults that you can override. + * @param sourceClock_Hz Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_Hz); + +/*! @} */ + +/*! + * @addtogroup i3c_master_driver + * @{ + */ + +/*! @name Initialization and deinitialization */ +/*! @{ */ + +/*! + * @brief Provides a default configuration for the I3C master peripheral. + * + * This function provides the following default configuration for the I3C master peripheral: + * @code + * masterConfig->enableMaster = kI3C_MasterOn; + * masterConfig->disableTimeout = false; + * masterConfig->hKeep = kI3C_MasterHighKeeperNone; + * masterConfig->enableOpenDrainStop = true; + * masterConfig->enableOpenDrainHigh = true; + * masterConfig->baudRate_Hz = 100000U; + * masterConfig->busType = kI3C_TypeI2C; + * @endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with I3C_MasterInit(). + * + * @param[out] masterConfig User provided configuration structure for default values. Refer to #i3c_master_config_t. + */ +void I3C_MasterGetDefaultConfig(i3c_master_config_t *masterConfig); + +/*! + * @brief Initializes the I3C master peripheral. + * + * This function enables the peripheral clock and initializes the I3C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * @param base The I3C peripheral base address. + * @param masterConfig User provided peripheral configuration. Use I3C_MasterGetDefaultConfig() to get a set of + * defaults that you can override. + * @param sourceClock_Hz Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void I3C_MasterInit(I3C_Type *base, const i3c_master_config_t *masterConfig, uint32_t sourceClock_Hz); + +/*! + * @brief Deinitializes the I3C master peripheral. + * + * This function disables the I3C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The I3C peripheral base address. + */ +void I3C_MasterDeinit(I3C_Type *base); + +/* Not static so it can be used from fsl_i3c_dma.c. */ +status_t I3C_MasterCheckAndClearError(I3C_Type *base, uint32_t status); + +/* Not static so it can be used from fsl_i3c_dma.c. */ +status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle); + +/* Not static so it can be used from fsl_i3c_dma.c. */ +status_t I3C_CheckForBusyBus(I3C_Type *base); + +/*! + * @brief Set I3C module master mode. + * + * @param base The I3C peripheral base address. + * @param enable Enable master mode. + */ +static inline void I3C_MasterEnable(I3C_Type *base, i3c_master_enable_t enable) +{ + base->MCONFIG = (base->MCONFIG & ~I3C_MCONFIG_MSTENA_MASK) | I3C_MCONFIG_MSTENA(enable); +} + +/*! @} */ + +/*! @name Status */ +/*! @{ */ + +/*! + * @brief Gets the I3C master status flags. + * + * A bit mask with the state of all I3C master status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The I3C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _i3c_master_flags + */ +static inline uint32_t I3C_MasterGetStatusFlags(I3C_Type *base) +{ + return base->MSTATUS & ~(I3C_MSTATUS_STATE_MASK | I3C_MSTATUS_IBITYPE_MASK); +} + +/*! + * @brief Clears the I3C master status flag state. + * + * The following status register flags can be cleared: + * - #kI3C_MasterSlaveStartFlag + * - #kI3C_MasterControlDoneFlag + * - #kI3C_MasterCompleteFlag + * - #kI3C_MasterArbitrationWonFlag + * - #kI3C_MasterSlave2MasterFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The I3C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * #_i3c_master_flags enumerators OR'd together. You may pass the result of a previous call to + * I3C_MasterGetStatusFlags(). + * @see _i3c_master_flags. + */ +static inline void I3C_MasterClearStatusFlags(I3C_Type *base, uint32_t statusMask) +{ + base->MSTATUS = statusMask; +} + +/*! + * @brief Gets the I3C master error status flags. + * + * A bit mask with the state of all I3C master error status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The I3C peripheral base address. + * @return State of the error status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _i3c_master_error_flags + */ +static inline uint32_t I3C_MasterGetErrorStatusFlags(I3C_Type *base) +{ + return base->MERRWARN; +} + +/*! + * @brief Clears the I3C master error status flag state. + * + * @param base The I3C peripheral base address. + * @param statusMask A bitmask of error status flags that are to be cleared. The mask is composed of + * #_i3c_master_error_flags enumerators OR'd together. You may pass the result of a previous call to + * I3C_MasterGetStatusFlags(). + * @see _i3c_master_error_flags. + */ +static inline void I3C_MasterClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask) +{ + while ((base->MERRWARN & statusMask) != 0U) + { + base->MERRWARN = statusMask; + } +} + +/*! + * @brief Gets the I3C master state. + * + * @param base The I3C peripheral base address. + * @return I3C master state. + */ +i3c_master_state_t I3C_MasterGetState(I3C_Type *base); + +/*! @} */ + +/*! @name Interrupts */ +/*! @{ */ + +/*! + * @brief Enables the I3C master interrupt requests. + * + * All flags except #kI3C_MasterBetweenFlag and #kI3C_MasterNackDetectFlag can be enabled as + * interrupts. + * + * @param base The I3C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See #_i3c_master_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I3C_MasterEnableInterrupts(I3C_Type *base, uint32_t interruptMask) +{ + base->MINTSET |= interruptMask; +} + +/*! + * @brief Disables the I3C master interrupt requests. + * + * All flags except #kI3C_MasterBetweenFlag and #kI3C_MasterNackDetectFlag can be enabled as + * interrupts. + * + * @param base The I3C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See #_i3c_master_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I3C_MasterDisableInterrupts(I3C_Type *base, uint32_t interruptMask) +{ + base->MINTCLR = interruptMask; +} + +/*! + * @brief Returns the set of currently enabled I3C master interrupt requests. + * + * @param base The I3C peripheral base address. + * @return A bitmask composed of #_i3c_master_flags enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t I3C_MasterGetEnabledInterrupts(I3C_Type *base) +{ + return base->MINTSET; +} + +/*! + * @brief Returns the set of pending I3C master interrupt requests. + * + * @param base The I3C peripheral base address. + * @return A bitmask composed of #_i3c_master_flags enumerators OR'd together to indicate the + * set of pending interrupts. + */ +static inline uint32_t I3C_MasterGetPendingInterrupts(I3C_Type *base) +{ + return base->MINTMASKED; +} + +/*! @} */ + +/*! @name DMA control */ +/*! @{ */ + +/*! + * @brief Enables or disables I3C master DMA requests. + * + * @param base The I3C peripheral base address. + * @param enableTx Enable flag for transmit DMA request. Pass true for enable, false for disable. + * @param enableRx Enable flag for receive DMA request. Pass true for enable, false for disable. + * @param width DMA read/write unit in bytes. + */ +static inline void I3C_MasterEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width) +{ + assert(width <= 2U); + base->MDMACTRL = + I3C_MDMACTRL_DMAFB(enableRx ? 2U : 0U) | I3C_MDMACTRL_DMATB(enableTx ? 2U : 0U) | I3C_MDMACTRL_DMAWIDTH(width); +} + +/*! + * @brief Gets I3C master transmit data register address for DMA transfer. + * + * @param base The I3C peripheral base address. + * @param width DMA read/write unit in bytes. + * @return The I3C Master Transmit Data Register address. + */ +static inline uint32_t I3C_MasterGetTxFifoAddress(I3C_Type *base, uint32_t width) +{ + assert(width <= 2U); + return (uint32_t)((width == 2U) ? &base->MWDATAH : &base->MWDATAB); +} + +/*! + * @brief Gets I3C master receive data register address for DMA transfer. + * + * @param base The I3C peripheral base address. + * @param width DMA read/write unit in bytes. + * @return The I3C Master Receive Data Register address. + */ +static inline uint32_t I3C_MasterGetRxFifoAddress(I3C_Type *base, uint32_t width) +{ + assert(width <= 2U); + return (uint32_t)((width == 2U) ? &base->MRDATAH : &base->MRDATAB); +} + +/*! @} */ + +/*! @name FIFO control */ +/*! @{ */ + +/*! + * @brief Sets the watermarks for I3C master FIFOs. + * + * @param base The I3C peripheral base address. + * @param txLvl Transmit FIFO watermark level. The #kI3C_MasterTxReadyFlag flag is set whenever + * the number of words in the transmit FIFO reaches @a txLvl. + * @param rxLvl Receive FIFO watermark level. The #kI3C_MasterRxReadyFlag flag is set whenever + * the number of words in the receive FIFO reaches @a rxLvl. + * @param flushTx true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged. + * @param flushRx true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged. + */ +static inline void I3C_MasterSetWatermarks( + I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx) +{ + base->MDATACTRL = I3C_MDATACTRL_UNLOCK_MASK | I3C_MDATACTRL_TXTRIG(txLvl) | I3C_MDATACTRL_RXTRIG(rxLvl) | + (flushTx ? I3C_MDATACTRL_FLUSHTB_MASK : 0U) | (flushRx ? I3C_MDATACTRL_FLUSHFB_MASK : 0U); +} + +/*! + * @brief Gets the current number of bytes in the I3C master FIFOs. + * + * @param base The I3C peripheral base address. + * @param[out] txCount Pointer through which the current number of bytes in the transmit FIFO is returned. + * Pass NULL if this value is not required. + * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned. + * Pass NULL if this value is not required. + */ +static inline void I3C_MasterGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount) +{ + if (NULL != txCount) + { + *txCount = (base->MDATACTRL & I3C_MDATACTRL_TXCOUNT_MASK) >> I3C_MDATACTRL_TXCOUNT_SHIFT; + } + if (NULL != rxCount) + { + *rxCount = (base->MDATACTRL & I3C_MDATACTRL_RXCOUNT_MASK) >> I3C_MDATACTRL_RXCOUNT_SHIFT; + } +} + +/*! @} */ + +/*! @name Bus operations */ +/*! @{ */ + +/*! + * @brief Sets the I3C bus frequency for master transactions. + * + * The I3C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * @param base The I3C peripheral base address. + * @param baudRate_Hz Pointer to structure of requested bus frequency in Hertz. + * @param sourceClock_Hz I3C functional clock frequency in Hertz. + */ +void I3C_MasterSetBaudRate(I3C_Type *base, const i3c_baudrate_hz_t *baudRate_Hz, uint32_t sourceClock_Hz); + +/*! + * @brief Returns whether the bus is idle. + * + * Requires the master mode to be enabled. + * + * @param base The I3C peripheral base address. + * @retval true Bus is busy. + * @retval false Bus is idle. + */ +static inline bool I3C_MasterGetBusIdleState(I3C_Type *base) +{ + return ((base->MSTATUS & I3C_MSTATUS_STATE_MASK) == (uint32_t)kI3C_MasterStateIdle ? true : false); +} + +/*! + * @brief Sends a START signal and slave address on the I2C/I3C bus, receive size is also specified + * in the call. + * + * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure + * that another master is not occupying the bus. Then a START signal is transmitted, followed by the + * 7-bit address specified in the a address parameter. Note that this function does not actually wait + * until the START and address are successfully sent on the bus before returning. + * + * @param base The I3C peripheral base address. + * @param type The bus type to use in this transaction. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @param rxSize Read terminate size for the followed read transfer, limit to 255 bytes. + * @retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. + * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + */ +status_t I3C_MasterStartWithRxSize( + I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize); + +/*! + * @brief Sends a START signal and slave address on the I2C/I3C bus. + * + * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure + * that another master is not occupying the bus. Then a START signal is transmitted, followed by the + * 7-bit address specified in the @a address parameter. Note that this function does not actually wait + * until the START and address are successfully sent on the bus before returning. + * + * @param base The I3C peripheral base address. + * @param type The bus type to use in this transaction. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. + * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + */ +status_t I3C_MasterStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir); + +/*! + * @brief Sends a repeated START signal and slave address on the I2C/I3C bus, receive size is also specified + * in the call. + * + * This function is used to send a Repeated START signal when a transfer is already in progress. Like + * I3C_MasterStart(), it also sends the specified 7-bit address. Call this API also configures the read + * terminate size for the following read transfer. For example, set the rxSize = 2, the following read transfer + * will be terminated after two bytes of data received. Write transfer will not be affected by the rxSize + * configuration. + * + * @note This function exists primarily to maintain compatible APIs between I3C and I2C drivers, + * as well as to better document the intent of code that uses these APIs. + * + * @param base The I3C peripheral base address. + * @param type The bus type to use in this transaction. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @param rxSize Read terminate size for the followed read transfer, limit to 255 bytes. + * @retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. + */ +status_t I3C_MasterRepeatedStartWithRxSize( + I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize); + +/*! + * @brief Sends a repeated START signal and slave address on the I2C/I3C bus. + * + * This function is used to send a Repeated START signal when a transfer is already in progress. Like + * I3C_MasterStart(), it also sends the specified 7-bit address. + * + * @note This function exists primarily to maintain compatible APIs between I3C and I2C drivers, + * as well as to better document the intent of code that uses these APIs. + * + * @param base The I3C peripheral base address. + * @param type The bus type to use in this transaction. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. + */ +static inline status_t I3C_MasterRepeatedStart(I3C_Type *base, + i3c_bus_type_t type, + uint8_t address, + i3c_direction_t dir) +{ + return I3C_MasterRepeatedStartWithRxSize(base, type, address, dir, 0); +} + +/*! + * @brief Performs a polling send transfer on the I2C/I3C bus. + * + * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_I3C_Nak. + * + * @param base The I3C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @param flags Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available options. + * @retval #kStatus_Success Data was sent successfully. + * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_I3C_Timeout The module has stalled too long in a frame. + * @retval #kStatus_I3C_Nak The slave device sent a NAK in response to an address. + * @retval #kStatus_I3C_WriteAbort The slave device sent a NAK in response to a write. + * @retval #kStatus_I3C_MsgError Message SDR/DDR mismatch or read/write message in wrong state. + * @retval #kStatus_I3C_WriteFifoError Write to M/SWDATAB register when FIFO full. + * @retval #kStatus_I3C_InvalidReq Invalid use of request. + */ +status_t I3C_MasterSend(I3C_Type *base, const void *txBuff, size_t txSize, uint32_t flags); + +/*! + * @brief Performs a polling receive transfer on the I2C/I3C bus. + * + * @param base The I3C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @param flags Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available options. + * @retval #kStatus_Success Data was received successfully. + * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_I3C_Timeout The module has stalled too long in a frame. + * @retval #kStatus_I3C_Term The master terminates slave read. + * @retval #kStatus_I3C_HdrParityError Parity error from DDR read. + * @retval #kStatus_I3C_CrcError CRC error from DDR read. + * @retval #kStatus_I3C_MsgError Message SDR/DDR mismatch or read/write message in wrong state. + * @retval #kStatus_I3C_ReadFifoError Read from M/SRDATAB register when FIFO empty. + * @retval #kStatus_I3C_InvalidReq Invalid use of request. + */ +status_t I3C_MasterReceive(I3C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags); + +/*! + * @brief Sends a STOP signal on the I2C/I3C bus. + * + * This function does not return until the STOP signal is seen on the bus, or an error occurs. + * + * @param base The I3C peripheral base address. + * @retval #kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated. + * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_I3C_Timeout The module has stalled too long in a frame. + * @retval #kStatus_I3C_InvalidReq Invalid use of request. + */ +status_t I3C_MasterStop(I3C_Type *base); + +/*! + * @brief I3C master emit request. + * + * @param base The I3C peripheral base address. + * @param masterReq I3C master request of type #i3c_bus_request_t + */ +void I3C_MasterEmitRequest(I3C_Type *base, i3c_bus_request_t masterReq); + +/*! + * @brief I3C master emit request. + * + * @param base The I3C peripheral base address. + * @param ibiResponse I3C master emit IBI response of type #i3c_ibi_response_t + */ +static inline void I3C_MasterEmitIBIResponse(I3C_Type *base, i3c_ibi_response_t ibiResponse) +{ + uint32_t ctrlVal = base->MCTRL; + ctrlVal &= ~(I3C_MCTRL_IBIRESP_MASK | I3C_MCTRL_REQUEST_MASK); + ctrlVal |= I3C_MCTRL_IBIRESP((uint32_t)ibiResponse) | I3C_MCTRL_REQUEST(kI3C_RequestIbiAckNack); + base->MCTRL = ctrlVal; +} + +/*! + * @brief I3C master register IBI rule. + * + * @param base The I3C peripheral base address. + * @param ibiRule Pointer to ibi rule description of type #i3c_register_ibi_addr_t + */ +void I3C_MasterRegisterIBI(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule); + +/*! + * @brief I3C master get IBI rule. + * + * @param base The I3C peripheral base address. + * @param ibiRule Pointer to store the read out ibi rule description. + */ +void I3C_MasterGetIBIRules(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule); + +/*! + * @brief I3C master get IBI Type. + * + * @param base The I3C peripheral base address. + * @retval i3c_ibi_type_t Type of #i3c_ibi_type_t. + */ +i3c_ibi_type_t I3C_GetIBIType(I3C_Type *base); + +/*! + * @brief I3C master get IBI Address. + * + * @param base The I3C peripheral base address. + * @retval The 8-bit IBI address. + */ +static inline uint8_t I3C_GetIBIAddress(I3C_Type *base) +{ + return (uint8_t)((base->MSTATUS & I3C_MSTATUS_IBIADDR_MASK) >> I3C_MSTATUS_IBIADDR_SHIFT); +} + +/*! + * @brief Performs a DAA in the i3c bus with specified temporary baud rate. + * + * @param base The I3C peripheral base address. + * @param addressList The pointer for address list which is used to do DAA. + * @param count The address count in the address list. + * @param daaBaudRate The temporary baud rate in DAA process, NULL for using initial setting. + * The initial setting is set back between the completion of the DAA and the return of this function. + * @retval #kStatus_Success The transaction was started successfully. + * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + * @retval #kStatus_I3C_SlaveCountExceed The I3C slave count has exceed the definition in I3C_MAX_DEVCNT. + */ +status_t I3C_MasterProcessDAASpecifiedBaudrate(I3C_Type *base, + uint8_t *addressList, + uint32_t count, + i3c_master_daa_baudrate_t *daaBaudRate); + +/*! + * @brief Performs a DAA in the i3c bus. + * + * @param base The I3C peripheral base address. + * @param addressList The pointer for address list which is used to do DAA. + * @param count The address count in the address list. + * The initial setting is set back between the completion of the DAA and the return of this function. + * @retval #kStatus_Success The transaction was started successfully. + * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + * @retval #kStatus_I3C_SlaveCountExceed The I3C slave count has exceed the definition in I3C_MAX_DEVCNT. + */ +static inline status_t I3C_MasterProcessDAA(I3C_Type *base, uint8_t *addressList, uint32_t count) +{ + return I3C_MasterProcessDAASpecifiedBaudrate(base, addressList, count, NULL); +} + +/*! + * @brief Get device information list after DAA process is done. + * + * @param base The I3C peripheral base address. + * @param[out] count The pointer to store the available device count. + * @return Pointer to the i3c_device_info_t array. + */ +i3c_device_info_t *I3C_MasterGetDeviceListAfterDAA(I3C_Type *base, uint8_t *count); +/*! + * @brief Performs a master polling transfer on the I2C/I3C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to error happens during transfer. + * + * @param base The I3C peripheral base address. + * @param transfer Pointer to the transfer structure. + * @retval #kStatus_Success Data was received successfully. + * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_I3C_IBIWon The I3C slave event IBI or MR or HJ won the arbitration on a header address. + * @retval #kStatus_I3C_Timeout The module has stalled too long in a frame. + * @retval #kStatus_I3C_Nak The slave device sent a NAK in response to an address. + * @retval #kStatus_I3C_WriteAbort The slave device sent a NAK in response to a write. + * @retval #kStatus_I3C_Term The master terminates slave read. + * @retval #kStatus_I3C_HdrParityError Parity error from DDR read. + * @retval #kStatus_I3C_CrcError CRC error from DDR read. + * @retval #kStatus_I3C_MsgError Message SDR/DDR mismatch or read/write message in wrong state. + * @retval #kStatus_I3C_ReadFifoError Read from M/SRDATAB register when FIFO empty. + * @retval #kStatus_I3C_WriteFifoError Write to M/SWDATAB register when FIFO full. + * @retval #kStatus_I3C_InvalidReq Invalid use of request. + */ +status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *transfer); + +/*! @} */ + +/*! @name Non-blocking */ +/*! @{ */ + +/*! + * @brief Creates a new handle for the I3C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I3C_MasterTransferAbort() API shall be called. + * + * + * @note The function also enables the NVIC IRQ for the input I3C. Need to notice + * that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + * + * @param base The I3C peripheral base address. + * @param[out] handle Pointer to the I3C master driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void I3C_MasterTransferCreateHandle(I3C_Type *base, + i3c_master_handle_t *handle, + const i3c_master_transfer_callback_t *callback, + void *userData); + +/*! + * @brief Performs a non-blocking transaction on the I2C/I3C bus. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + * @param transfer The pointer to the transfer descriptor. + * @retval #kStatus_Success The transaction was started successfully. + * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t I3C_MasterTransferNonBlocking(I3C_Type *base, i3c_master_handle_t *handle, i3c_master_transfer_t *transfer); + +/*! + * @brief Returns number of bytes transferred so far. + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + * @param[out] count Number of bytes transferred so far by the non-blocking transaction. + * @retval #kStatus_Success + * @retval #kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t I3C_MasterTransferGetCount(I3C_Type *base, i3c_master_handle_t *handle, size_t *count); + +/*! + * @brief Terminates a non-blocking I3C master transmission early. + * + * @note It is not safe to call this function from an IRQ handler that has a higher priority than the + * I3C peripheral's IRQ priority. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + * @retval #kStatus_Success A transaction was successfully aborted. + * @retval #kStatus_I3C_Idle There is not a non-blocking transaction currently in progress. + */ +void I3C_MasterTransferAbort(I3C_Type *base, i3c_master_handle_t *handle); + +/*! @} */ + +/*! @name IRQ handler */ +/*! @{ */ + +/*! + * @brief Reusable routine to handle master interrupts. + * @note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * @param base The I3C peripheral base address. + * @param intHandle Pointer to the I3C master driver handle. + */ +void I3C_MasterTransferHandleIRQ(I3C_Type *base, void *intHandle); + +/*! @} */ + +/*! @} */ + +/*! + * @addtogroup i3c_slave_driver + * @{ + */ + +/*! @name Initialization and deinitialization */ +/*! @{ */ + +/*! + * @brief Provides a default configuration for the I3C slave peripheral. + * + * This function provides the following default configuration for the I3C slave peripheral: + * @code + * slaveConfig->enableslave = true; + * @endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the slave driver with I3C_SlaveInit(). + * + * @param[out] slaveConfig User provided configuration structure for default values. Refer to #i3c_slave_config_t. + */ +void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig); + +/*! + * @brief Initializes the I3C slave peripheral. + * + * This function enables the peripheral clock and initializes the I3C slave peripheral as described by the user + * provided configuration. + * + * @param base The I3C peripheral base address. + * @param slaveConfig User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of + * defaults that you can override. + * @param slowClock_Hz Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values. + * If FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH defines as 1, this parameter is useless. + */ +void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz); + +/*! + * @brief Deinitializes the I3C slave peripheral. + * + * This function disables the I3C slave peripheral and gates the clock. + * + * @param base The I3C peripheral base address. + */ +void I3C_SlaveDeinit(I3C_Type *base); + +/*! + * @brief Enable/Disable Slave. + * + * @param base The I3C peripheral base address. + * @param isEnable Enable or disable. + */ +static inline void I3C_SlaveEnable(I3C_Type *base, bool isEnable) +{ + base->SCONFIG = (base->SCONFIG & ~I3C_SCONFIG_SLVENA_MASK) | I3C_SCONFIG_SLVENA(isEnable); +} + +/*! @} */ + +/*! @name Status */ +/*! @{ */ + +/*! + * @brief Gets the I3C slave status flags. + * + * A bit mask with the state of all I3C slave status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The I3C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _i3c_slave_flags + */ +static inline uint32_t I3C_SlaveGetStatusFlags(I3C_Type *base) +{ + return base->SSTATUS & ~(I3C_SSTATUS_EVDET_MASK | I3C_SSTATUS_ACTSTATE_MASK | I3C_SSTATUS_TIMECTRL_MASK); +} + +/*! + * @brief Clears the I3C slave status flag state. + * + * The following status register flags can be cleared: + * - #kI3C_SlaveBusStartFlag + * - #kI3C_SlaveMatchedFlag + * - #kI3C_SlaveBusStopFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The I3C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * #_i3c_slave_flags enumerators OR'd together. You may pass the result of a previous call to + * I3C_SlaveGetStatusFlags(). + * @see _i3c_slave_flags. + */ +static inline void I3C_SlaveClearStatusFlags(I3C_Type *base, uint32_t statusMask) +{ + base->SSTATUS = statusMask; +} + +/*! + * @brief Gets the I3C slave error status flags. + * + * A bit mask with the state of all I3C slave error status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The I3C peripheral base address. + * @return State of the error status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _i3c_slave_error_flags + */ +static inline uint32_t I3C_SlaveGetErrorStatusFlags(I3C_Type *base) +{ + return base->SERRWARN; +} + +/*! + * @brief Clears the I3C slave error status flag state. + * + * @param base The I3C peripheral base address. + * @param statusMask A bitmask of error status flags that are to be cleared. The mask is composed of + * #_i3c_slave_error_flags enumerators OR'd together. You may pass the result of a previous call to + * I3C_SlaveGetErrorStatusFlags(). + * @see _i3c_slave_error_flags. + */ +static inline void I3C_SlaveClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask) +{ + base->SERRWARN = statusMask; +} + +/*! + * @brief Gets the I3C slave state. + * + * @param base The I3C peripheral base address. + * @return I3C slave activity state, refer #i3c_slave_activity_state_t. + */ +i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base); + +/* Not static so it can be used from fsl_i3c_dma.c. */ +status_t I3C_SlaveCheckAndClearError(I3C_Type *base, uint32_t status); +/*! @} */ + +/*! @name Interrupts */ +/*! @{ */ + +/*! + * @brief Enables the I3C slave interrupt requests. + * + * Only below flags can be enabled as interrupts. + * - #kI3C_SlaveBusStartFlag + * - #kI3C_SlaveMatchedFlag + * - #kI3C_SlaveBusStopFlag + * - #kI3C_SlaveRxReadyFlag + * - #kI3C_SlaveTxReadyFlag + * - #kI3C_SlaveDynamicAddrChangedFlag + * - #kI3C_SlaveReceivedCCCFlag + * - #kI3C_SlaveErrorFlag + * - #kI3C_SlaveHDRCommandMatchFlag + * - #kI3C_SlaveCCCHandledFlag + * - #kI3C_SlaveEventSentFlag + * + * @param base The I3C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See #_i3c_slave_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I3C_SlaveEnableInterrupts(I3C_Type *base, uint32_t interruptMask) +{ + base->SINTSET |= interruptMask; +} + +/*! + * @brief Disables the I3C slave interrupt requests. + * + * Only below flags can be disabled as interrupts. + * - #kI3C_SlaveBusStartFlag + * - #kI3C_SlaveMatchedFlag + * - #kI3C_SlaveBusStopFlag + * - #kI3C_SlaveRxReadyFlag + * - #kI3C_SlaveTxReadyFlag + * - #kI3C_SlaveDynamicAddrChangedFlag + * - #kI3C_SlaveReceivedCCCFlag + * - #kI3C_SlaveErrorFlag + * - #kI3C_SlaveHDRCommandMatchFlag + * - #kI3C_SlaveCCCHandledFlag + * - #kI3C_SlaveEventSentFlag + * + * @param base The I3C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See #_i3c_slave_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void I3C_SlaveDisableInterrupts(I3C_Type *base, uint32_t interruptMask) +{ + base->SINTCLR = interruptMask; +} + +/*! + * @brief Returns the set of currently enabled I3C slave interrupt requests. + * + * @param base The I3C peripheral base address. + * @return A bitmask composed of #_i3c_slave_flags enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t I3C_SlaveGetEnabledInterrupts(I3C_Type *base) +{ + return base->SINTSET; +} + +/*! + * @brief Returns the set of pending I3C slave interrupt requests. + * + * @param base The I3C peripheral base address. + * @return A bitmask composed of #_i3c_slave_flags enumerators OR'd together to indicate the + * set of pending interrupts. + */ +static inline uint32_t I3C_SlaveGetPendingInterrupts(I3C_Type *base) +{ + return base->SINTMASKED; +} + +/*! @} */ + +/*! @name DMA control */ +/*! @{ */ + +/*! + * @brief Enables or disables I3C slave DMA requests. + * + * @param base The I3C peripheral base address. + * @param enableTx Enable flag for transmit DMA request. Pass true for enable, false for disable. + * @param enableRx Enable flag for receive DMA request. Pass true for enable, false for disable. + * @param width DMA read/write unit in bytes. + */ +static inline void I3C_SlaveEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width) +{ + assert(width <= 2U); + base->SDMACTRL = + I3C_SDMACTRL_DMAFB(enableRx ? 2U : 0U) | I3C_SDMACTRL_DMATB(enableTx ? 2U : 0U) | I3C_SDMACTRL_DMAWIDTH(width); +} + +/*! + * @brief Gets I3C slave transmit data register address for DMA transfer. + * + * @param base The I3C peripheral base address. + * @param width DMA read/write unit in bytes. + * @return The I3C Slave Transmit Data Register address. + */ +static inline uint32_t I3C_SlaveGetTxFifoAddress(I3C_Type *base, uint32_t width) +{ + assert(width <= 2U); + return (uint32_t)((width == 2U) ? &base->SWDATAH : &base->SWDATAB); +} + +/*! + * @brief Gets I3C slave receive data register address for DMA transfer. + * + * @param base The I3C peripheral base address. + * @param width DMA read/write unit in bytes. + * @return The I3C Slave Receive Data Register address. + */ +static inline uint32_t I3C_SlaveGetRxFifoAddress(I3C_Type *base, uint32_t width) +{ + assert(width <= 2U); + return (uint32_t)((width == 2U) ? &base->SRDATAH : &base->SRDATAB); +} + +/*! @} */ + +/*! @name FIFO control */ +/*! @{ */ + +/*! + * @brief Sets the watermarks for I3C slave FIFOs. + * + * @param base The I3C peripheral base address. + * @param txLvl Transmit FIFO watermark level. The #kI3C_SlaveTxReadyFlag flag is set whenever + * the number of words in the transmit FIFO reaches @a txLvl. + * @param rxLvl Receive FIFO watermark level. The #kI3C_SlaveRxReadyFlag flag is set whenever + * the number of words in the receive FIFO reaches @a rxLvl. + * @param flushTx true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged. + * @param flushRx true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged. + */ +static inline void I3C_SlaveSetWatermarks( + I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx) +{ + base->SDATACTRL = I3C_SDATACTRL_UNLOCK_MASK | I3C_SDATACTRL_TXTRIG(txLvl) | I3C_SDATACTRL_RXTRIG(rxLvl) | + (flushTx ? I3C_SDATACTRL_FLUSHTB_MASK : 0U) | (flushRx ? I3C_SDATACTRL_FLUSHFB_MASK : 0U); +} + +/*! + * @brief Gets the current number of bytes in the I3C slave FIFOs. + * + * @param base The I3C peripheral base address. + * @param[out] txCount Pointer through which the current number of bytes in the transmit FIFO is returned. + * Pass NULL if this value is not required. + * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned. + * Pass NULL if this value is not required. + */ +static inline void I3C_SlaveGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount) +{ + if (NULL != txCount) + { + *txCount = (base->SDATACTRL & I3C_SDATACTRL_TXCOUNT_MASK) >> I3C_SDATACTRL_TXCOUNT_SHIFT; + } + if (NULL != rxCount) + { + *rxCount = (base->SDATACTRL & I3C_SDATACTRL_RXCOUNT_MASK) >> I3C_SDATACTRL_RXCOUNT_SHIFT; + } +} + +/*! @} */ + +/*! @name Bus operations */ +/*! @{ */ + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) +/*! + * @brief I3C slave request event. + * + * @param base The I3C peripheral base address. + * @param event I3C slave event of type #i3c_slave_event_t + */ +void I3C_SlaveRequestEvent(I3C_Type *base, i3c_slave_event_t event); +#endif + +/*! + * @brief Performs a polling send transfer on the I3C bus. + * + * @param base The I3C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @return Error or success status returned by API. + */ +status_t I3C_SlaveSend(I3C_Type *base, const void *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transfer on the I3C bus. + * + * @param base The I3C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @return Error or success status returned by API. + */ +status_t I3C_SlaveReceive(I3C_Type *base, void *rxBuff, size_t rxSize); + +/*! @} */ + +/*! @name Slave non-blocking */ +/*! @{ */ + +/*! + * @brief Creates a new handle for the I3C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I3C_SlaveTransferAbort() API shall be called. + * + * @note The function also enables the NVIC IRQ for the input I3C. Need to notice + * that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + + * @param base The I3C peripheral base address. + * @param[out] handle Pointer to the I3C slave driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void I3C_SlaveTransferCreateHandle(I3C_Type *base, + i3c_slave_handle_t *handle, + i3c_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and I3C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to I3C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #i3c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kI3C_SlaveTransmitEvent and #kI3C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kI3C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to struct: _i3c_slave_handle structure which stores the transfer state. + * @param eventMask Bit mask formed by OR'ing together #i3c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kI3C_SlaveAllEvents to enable all events. + * + * @retval #kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I3C_Busy Slave transfers have already been started on this handle. + */ +status_t I3C_SlaveTransferNonBlocking(I3C_Type *base, i3c_slave_handle_t *handle, uint32_t eventMask); + +/*! + * @brief Gets the slave transfer status during a non-blocking transfer. + * @param base The I3C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure. + * @param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not + * required. + * @retval #kStatus_Success + * @retval #kStatus_NoTransferInProgress + */ +status_t I3C_SlaveTransferGetCount(I3C_Type *base, i3c_slave_handle_t *handle, size_t *count); + +/*! + * @brief Aborts the slave non-blocking transfers. + * @note This API could be called at any time to stop slave for handling the bus events. + * @param base The I3C peripheral base address. + * @param handle Pointer to struct: _i3c_slave_handle structure which stores the transfer state. + * @retval #kStatus_Success + * @retval #kStatus_I3C_Idle + */ +void I3C_SlaveTransferAbort(I3C_Type *base, i3c_slave_handle_t *handle); + +/*! @} */ + +/*! @name Slave IRQ handler */ +/*! @{ */ + +/*! + * @brief Reusable routine to handle slave interrupts. + * @note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * @param base The I3C peripheral base address. + * @param intHandle Pointer to struct: _i3c_slave_handle structure which stores the transfer state. + */ +void I3C_SlaveTransferHandleIRQ(I3C_Type *base, void *intHandle); + +#if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) +/*! + * @brief I3C slave request IBI event with data payload(mandatory and extended). + * + * @param base The I3C peripheral base address. + * @param data Pointer to IBI data to be sent in the request. + * @param dataSize IBI data size. + */ +void I3C_SlaveRequestIBIWithData(I3C_Type *base, uint8_t *data, size_t dataSize); + +/*! + * @brief I3C slave request IBI event with single data. + * @deprecated Do not use this function. It has been superseded by @ref I3C_SlaveRequestIBIWithData. + * + * @param base The I3C peripheral base address. + * @param data IBI data to be sent in the request. + * @param dataSize IBI data size. + */ +void I3C_SlaveRequestIBIWithSingleData(I3C_Type *base, uint8_t data, size_t dataSize); +#endif /* !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) */ + +/*! @} */ +/*! @} */ +#if defined(__cplusplus) +} +#endif + +#endif /* FSL_I3C_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_i3c_edma.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_i3c_edma.c new file mode 100644 index 00000000000..7ff5e8a6d04 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_i3c_edma.c @@ -0,0 +1,1057 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_i3c_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.i3c_edma" +#endif + +/*! @brief States for the state machine used by transactional APIs. */ +enum _i3c_edma_transfer_states +{ + kIdleState = 0, + kIBIWonState, + kSlaveStartState, + kSendCommandState, + kWaitRepeatedStartCompleteState, + kTransmitDataState, + kReceiveDataState, + kStopState, + kWaitForCompletionState, + kAddressMatchState, +}; + +/*! @brief Common sets of flags used by the driver. */ +enum _i3c_edma_flag_constants +{ + /*! All flags which are cleared by the driver upon starting a transfer. */ + kMasterClearFlags = kI3C_MasterSlaveStartFlag | kI3C_MasterControlDoneFlag | kI3C_MasterCompleteFlag | + kI3C_MasterArbitrationWonFlag | kI3C_MasterSlave2MasterFlag | kI3C_MasterErrorFlag, + + /*! IRQ sources enabled by the non-blocking transactional API. */ + kMasterDMAIrqFlags = kI3C_MasterSlaveStartFlag | kI3C_MasterControlDoneFlag | kI3C_MasterCompleteFlag | + kI3C_MasterArbitrationWonFlag | kI3C_MasterErrorFlag | kI3C_MasterSlave2MasterFlag, + + /*! Errors to check for. */ + kMasterErrorFlags = kI3C_MasterErrorNackFlag | kI3C_MasterErrorWriteAbortFlag | +#if !defined(FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) || (!FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) + kI3C_MasterErrorTermFlag | +#endif + kI3C_MasterErrorParityFlag | kI3C_MasterErrorCrcFlag | kI3C_MasterErrorReadFlag | + kI3C_MasterErrorWriteFlag | kI3C_MasterErrorMsgFlag | kI3C_MasterErrorInvalidReqFlag | + kI3C_MasterErrorTimeoutFlag, + /*! All flags which are cleared by the driver upon starting a transfer. */ + kSlaveClearFlags = kI3C_SlaveBusStartFlag | kI3C_SlaveMatchedFlag | kI3C_SlaveBusStopFlag, + + /*! IRQ sources enabled by the non-blocking transactional API. */ + kSlaveDMAIrqFlags = kI3C_SlaveBusStartFlag | kI3C_SlaveMatchedFlag | + kI3C_SlaveBusStopFlag | /*kI3C_SlaveRxReadyFlag |*/ + kI3C_SlaveDynamicAddrChangedFlag | kI3C_SlaveReceivedCCCFlag | kI3C_SlaveErrorFlag | + kI3C_SlaveHDRCommandMatchFlag | kI3C_SlaveCCCHandledFlag | kI3C_SlaveEventSentFlag, + + /*! Errors to check for. */ + kSlaveErrorFlags = kI3C_SlaveErrorOverrunFlag | kI3C_SlaveErrorUnderrunFlag | kI3C_SlaveErrorUnderrunNakFlag | + kI3C_SlaveErrorTermFlag | kI3C_SlaveErrorInvalidStartFlag | kI3C_SlaveErrorSdrParityFlag | + kI3C_SlaveErrorHdrParityFlag | kI3C_SlaveErrorHdrCRCFlag | kI3C_SlaveErrorS0S1Flag | + kI3C_SlaveErrorOverreadFlag | kI3C_SlaveErrorOverwriteFlag, +}; +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Array to map I3C instance number to base pointer. */ +static I3C_Type *const kI3cBases[] = I3C_BASE_PTRS; + +/*! @brief Array to store the END byte of I3C teransfer. */ +static uint8_t i3cEndByte[ARRAY_SIZE(kI3cBases)] = {0}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void I3C_MasterRunEDMATransfer( + I3C_Type *base, i3c_master_edma_handle_t *handle, void *data, size_t dataSize, i3c_direction_t direction); + +/******************************************************************************* + * Code + ******************************************************************************/ +static void I3C_MasterTransferEDMACallbackRx(edma_handle_t *dmaHandle, void *param, bool transferDone, uint32_t tcds) +{ + i3c_master_edma_handle_t *i3cHandle = (i3c_master_edma_handle_t *)param; + + if (transferDone) + { + /* Terminate following data if present. */ + i3cHandle->base->MCTRL |= I3C_MCTRL_RDTERM(1U); + +#if defined(FSL_FEATURE_I3C_HAS_ERRATA_052086) && (FSL_FEATURE_I3C_HAS_ERRATA_052086) + if (i3cHandle->transfer.dataSize > 1U) + { + size_t rxCount; + /* Read out the last byte data. */ + do + { + I3C_MasterGetFifoCounts(i3cHandle->base, &rxCount, NULL); + } while (rxCount == 0U); + *(uint8_t *)((uint32_t)(uint32_t *)i3cHandle->transfer.data + i3cHandle->transfer.dataSize - 1U) = + (uint8_t)i3cHandle->base->MRDATAB; + } +#endif + + /* Disable I3C Rx DMA. */ + i3cHandle->base->MDATACTRL &= ~I3C_MDMACTRL_DMAFB_MASK; + } +} + +static void I3C_MasterTransferEDMACallbackTx(edma_handle_t *dmaHandle, void *param, bool transferDone, uint32_t tcds) +{ + i3c_master_edma_handle_t *i3cHandle = (i3c_master_edma_handle_t *)param; + uint32_t instance; + + if (transferDone) + { + /* Disable I3C Tx DMA. */ + i3cHandle->base->MDATACTRL &= ~I3C_MDMACTRL_DMATB_MASK; + + if (i3cHandle->transferCount != 1U) + { + instance = I3C_GetInstance(i3cHandle->base); + /* Ensure there's space in the Tx FIFO. */ + while ((i3cHandle->base->MDATACTRL & I3C_MDATACTRL_TXFULL_MASK) != 0U) + { + } + i3cHandle->base->MWDATABE = i3cEndByte[instance]; + } + } +} +/*! + * brief Prepares the transfer state machine and fills in the command buffer. + * param handle Master nonblocking driver handle. + */ +static status_t I3C_MasterInitTransferStateMachineEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle) +{ + i3c_master_transfer_t *xfer = &handle->transfer; + status_t result = kStatus_Success; + i3c_direction_t direction = xfer->direction; + + /* Calculate command count and put into command buffer. */ + handle->subaddressCount = 0U; + if (xfer->subaddressSize != 0U) + { + for (uint32_t i = xfer->subaddressSize; i > 0U; i--) + { + handle->subaddressBuffer[handle->subaddressCount++] = (uint8_t)((xfer->subaddress) >> (8U * (i - 1U))); + } + } + + /* Start condition shall be ommited, switch directly to next phase */ + if (xfer->dataSize == 0U) + { + handle->state = (uint8_t)kStopState; + } + + if (0UL != (xfer->flags & (uint32_t)kI3C_TransferStartWithBroadcastAddr)) + { + if (0UL != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) + { + return kStatus_InvalidArgument; + } + + if (0UL != (xfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag)) + { + return kStatus_InvalidArgument; + } + + /* Issue 0x7E as start. */ + result = I3C_MasterStart(base, xfer->busType, 0x7E, kI3C_Write); + if (result != kStatus_Success) + { + return result; + } + + result = I3C_MasterWaitForCtrlDone(base, false); + if (result != kStatus_Success) + { + return result; + } + } + + /* Handle no start option. */ + if (0U != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag)) + { + /* No need to send start flag, directly go to send command or data */ + if (xfer->subaddressSize > 0UL) + { + handle->state = (uint8_t)kSendCommandState; + } + else + { + if (direction == kI3C_Write) + { + /* Next state, send data. */ + handle->state = (uint8_t)kTransmitDataState; + } + else + { + /* Only support write with no stop signal. */ + return kStatus_InvalidArgument; + } + } + } + else + { + if (xfer->subaddressSize != 0U) + { + handle->state = (uint8_t)kSendCommandState; + } + else + { + if (handle->transfer.direction == kI3C_Write) + { + handle->state = (uint8_t)kTransmitDataState; + } + else if (handle->transfer.direction == kI3C_Read) + { + handle->state = (uint8_t)kReceiveDataState; + } + else + { + return kStatus_InvalidArgument; + } + } + + if (handle->transfer.direction == kI3C_Read) + { + I3C_MasterRunEDMATransfer(base, handle, xfer->data, xfer->dataSize, kI3C_Read); + } + + if (handle->state != (uint8_t)kStopState) + { + /* If repeated start is requested, send repeated start. */ + if (0U != (xfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag)) + { + result = I3C_MasterRepeatedStart(base, xfer->busType, xfer->slaveAddress, direction); + } + else /* For normal transfer, send start. */ + { + result = I3C_MasterStart(base, xfer->busType, xfer->slaveAddress, direction); + } + } + } + + I3C_MasterTransferEDMAHandleIRQ(base, handle); + return result; +} + +static void I3C_MasterRunEDMATransfer( + I3C_Type *base, i3c_master_edma_handle_t *handle, void *data, size_t dataSize, i3c_direction_t direction) +{ + bool isEnableTxDMA = false; + bool isEnableRxDMA = false; + edma_transfer_config_t xferConfig; + uint32_t instance; + uint32_t address; + uint32_t width; + + handle->transferCount = dataSize; + + switch (direction) + { + case kI3C_Write: + if (dataSize != 1U) + { + address = (uint32_t)&base->MWDATAB1; + /* Cause controller sends command and data with same interface, need special buffer to store the END byte. */ + instance = I3C_GetInstance(base); + i3cEndByte[instance] = *(uint8_t *)((uint32_t)(uint32_t *)data + dataSize - 1U); + dataSize--; + } + else + { + address = (uint32_t)&base->MWDATABE; + } + EDMA_PrepareTransfer(&xferConfig, data, sizeof(uint8_t), (uint32_t *)address, sizeof(uint8_t), 1, dataSize, + kEDMA_MemoryToPeripheral); + (void)EDMA_SubmitTransfer(handle->txDmaHandle, &xferConfig); + EDMA_StartTransfer(handle->txDmaHandle); + isEnableTxDMA = true; + width = 1U; + break; + + case kI3C_Read: +#if defined(FSL_FEATURE_I3C_HAS_ERRATA_052086) && (FSL_FEATURE_I3C_HAS_ERRATA_052086) + /* ERRATA052086: Soc integration issue results in target misses the last DMA request to copy the + last one byte from controler when transmission data size is > 1 byte. Resolution: Triggering DMA + interrupt one byte in advance, then receive the last one byte data after DMA transmission finishes. */ + if (dataSize > 1U) + { + dataSize--; + } +#endif + address = (uint32_t)&base->MRDATAB; + EDMA_PrepareTransfer(&xferConfig, (uint32_t *)address, sizeof(uint8_t), data, sizeof(uint8_t), 1, dataSize, + kEDMA_PeripheralToMemory); + (void)EDMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); + EDMA_StartTransfer(handle->rxDmaHandle); + isEnableRxDMA = true; + width = 1U; + break; + + default: + /* This should never happen */ + assert(false); + break; + } + + I3C_MasterEnableDMA(base, isEnableTxDMA, isEnableRxDMA, width); +} + +static status_t I3C_MasterRunTransferStateMachineEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, bool *isDone) +{ + uint32_t status; + uint32_t errStatus; + status_t result = kStatus_Success; + i3c_master_transfer_t *xfer; + size_t rxCount = 0; + bool state_complete = false; + + /* Set default isDone return value. */ + *isDone = false; + + /* Check for errors. */ + status = (uint32_t)I3C_MasterGetPendingInterrupts(base); + I3C_MasterClearStatusFlags(base, status); + + i3c_master_state_t masterState = I3C_MasterGetState(base); + errStatus = I3C_MasterGetErrorStatusFlags(base); + result = I3C_MasterCheckAndClearError(base, errStatus); + if (kStatus_Success != result) + { + return result; + } + + if (0UL != (status & (uint32_t)kI3C_MasterSlave2MasterFlag)) + { + if (handle->callback.slave2Master != NULL) + { + handle->callback.slave2Master(base, handle->userData); + } + } + + if ((0UL != (status & (uint32_t)kI3C_MasterSlaveStartFlag)) && (handle->transfer.busType != kI3C_TypeI2C)) + { + handle->state = (uint8_t)kSlaveStartState; + } + + if ((masterState == kI3C_MasterStateIbiRcv) || (masterState == kI3C_MasterStateIbiAck)) + { + handle->state = (uint8_t)kIBIWonState; + } + + if (handle->state == (uint8_t)kIdleState) + { + return result; + } + + if (handle->state == (uint8_t)kIBIWonState) + { + /* Get fifo counts and compute room in tx fifo. */ + rxCount = (base->MDATACTRL & I3C_MDATACTRL_RXCOUNT_MASK) >> I3C_MDATACTRL_RXCOUNT_SHIFT; + } + + /* Get pointer to private data. */ + xfer = &handle->transfer; + + while (!state_complete) + { + /* Execute the state. */ + switch (handle->state) + { + case (uint8_t)kSlaveStartState: + /* Emit start + 0x7E */ + I3C_MasterEmitRequest(base, kI3C_RequestAutoIbi); + handle->state = (uint8_t)kIBIWonState; + state_complete = true; + break; + + case (uint8_t)kIBIWonState: + if (masterState == kI3C_MasterStateIbiAck) + { + handle->ibiType = I3C_GetIBIType(base); + if (handle->callback.ibiCallback != NULL) + { + handle->callback.ibiCallback(base, handle, handle->ibiType, kI3C_IbiAckNackPending); + } + else + { + I3C_MasterEmitIBIResponse(base, kI3C_IbiRespNack); + } + } + + /* Make sure there is data in the rx fifo. */ + if (0UL != rxCount) + { + if ((handle->ibiBuff == NULL) && (handle->callback.ibiCallback != NULL)) + { + handle->callback.ibiCallback(base, handle, kI3C_IbiNormal, kI3C_IbiDataBuffNeed); + } + uint8_t tempData = (uint8_t)base->MRDATAB; + if (handle->ibiBuff != NULL) + { + handle->ibiBuff[handle->ibiPayloadSize++] = tempData; + } + rxCount--; + break; + } + else if (0UL != (status & (uint32_t)kI3C_MasterCompleteFlag)) + { + handle->ibiType = I3C_GetIBIType(base); + handle->ibiAddress = I3C_GetIBIAddress(base); + state_complete = true; + result = kStatus_I3C_IBIWon; + } + else + { + state_complete = true; + } + break; + + case (uint8_t)kSendCommandState: + I3C_MasterRunEDMATransfer(base, handle, handle->subaddressBuffer, handle->subaddressCount, kI3C_Write); + + if ((xfer->direction == kI3C_Read) || (0UL == xfer->dataSize)) + { + if (0UL == xfer->dataSize) + { + handle->state = (uint8_t)kWaitForCompletionState; + } + else + { + /* xfer->dataSize != 0U, xfer->direction = kI3C_Read */ + handle->state = (uint8_t)kWaitRepeatedStartCompleteState; + } + } + else + { + /* Next state, transfer data. */ + handle->state = (uint8_t)kTransmitDataState; + } + + state_complete = true; + break; + + case (uint8_t)kWaitRepeatedStartCompleteState: + /* We stay in this state until the maste complete. */ + if (0UL != (status & (uint32_t)kI3C_MasterCompleteFlag)) + { + handle->state = (uint8_t)kReceiveDataState; + /* Send repeated start and slave address. */ + result = I3C_MasterRepeatedStart(base, xfer->busType, xfer->slaveAddress, kI3C_Read); + } + + state_complete = true; + break; + + case (uint8_t)kTransmitDataState: + I3C_MasterRunEDMATransfer(base, handle, xfer->data, xfer->dataSize, kI3C_Write); + handle->state = (uint8_t)kWaitForCompletionState; + + state_complete = true; + break; + + case (uint8_t)kReceiveDataState: + /* Do DMA read. */ + handle->state = (uint8_t)kWaitForCompletionState; + + state_complete = true; + break; + + case (uint8_t)kWaitForCompletionState: + /* We stay in this state until the maste complete. */ + if (0UL != (status & (uint32_t)kI3C_MasterCompleteFlag)) + { + handle->state = (uint8_t)kStopState; + } + else + { + state_complete = true; + } + break; + + case (uint8_t)kStopState: + /* Only issue a stop transition if the caller requested it. */ + if (0UL == (xfer->flags & (uint32_t)kI3C_TransferNoStopFlag)) + { + if (xfer->busType == kI3C_TypeI3CDdr) + { + I3C_MasterEmitRequest(base, kI3C_RequestForceExit); + } + else + { + I3C_MasterEmitRequest(base, kI3C_RequestEmitStop); + result = I3C_MasterWaitForCtrlDone(base, false); + } + } + *isDone = true; + state_complete = true; + break; + + default: + assert(false); + break; + } + } + return result; +} + +void I3C_MasterTransferCreateHandleEDMA(I3C_Type *base, + i3c_master_edma_handle_t *handle, + const i3c_master_edma_callback_t *callback, + void *userData, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle) +{ + uint32_t instance; + + assert(NULL != handle); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I3C_GetInstance(base); + + handle->base = base; + handle->txDmaHandle = txDmaHandle; + handle->rxDmaHandle = rxDmaHandle; + handle->callback = *callback; + handle->userData = userData; + + /* Save this handle for IRQ use. */ + s_i3cMasterHandle[instance] = handle; + + /* Set irq handler. */ + s_i3cMasterIsr = I3C_MasterTransferEDMAHandleIRQ; + + EDMA_SetCallback(handle->rxDmaHandle, I3C_MasterTransferEDMACallbackRx, handle); + EDMA_SetCallback(handle->txDmaHandle, I3C_MasterTransferEDMACallbackTx, handle); + + /* Clear all flags. */ + I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + + /* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC. + In some cases the I3C IRQ is configured through INTMUX, user needs to enable + INTMUX IRQ in application code. */ + (void)EnableIRQ(kI3cIrqs[instance]); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I3C_MasterEnableInterrupts(base, (uint32_t)kMasterDMAIrqFlags); +} + +/*! + * brief Performs a non-blocking DMA transaction on the I2C/I3C bus. + * + * param base The I3C peripheral base address. + * param handle Pointer to the I3C master driver handle. + * param transfer The pointer to the transfer descriptor. + * retval #kStatus_Success The transaction was started successfully. + * retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t I3C_MasterTransferEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, i3c_master_transfer_t *transfer) +{ + assert(NULL != handle); + assert(NULL != transfer); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + i3c_master_state_t masterState = I3C_MasterGetState(base); + bool checkDdrState = false; + + /* Return busy if another transaction is in progress. */ + if (handle->state != (uint8_t)kIdleState) + { + return kStatus_I3C_Busy; + } + + /* Return an error if the bus is already in use not by us. */ + checkDdrState = (transfer->busType == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true; + if ((masterState != kI3C_MasterStateIdle) && (masterState != kI3C_MasterStateNormAct) && checkDdrState) + { + return kStatus_I3C_Busy; + } + + /* Disable I3C IRQ sources while we configure stuff. */ + I3C_MasterDisableInterrupts( + base, ((uint32_t)kMasterDMAIrqFlags | (uint32_t)kI3C_MasterRxReadyFlag | (uint32_t)kI3C_MasterTxReadyFlag)); + + /* Save transfer into handle. */ + handle->transfer = *transfer; + + /* Configure IBI response type. */ + base->MCTRL &= ~I3C_MCTRL_IBIRESP_MASK; + base->MCTRL |= I3C_MCTRL_IBIRESP(transfer->ibiResponse); + + /* Clear all flags. */ + I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags); + I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + + /* Generate commands to send. */ + (void)I3C_MasterInitTransferStateMachineEDMA(base, handle); + + /* Enable I3C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + I3C_MasterEnableInterrupts(base, (uint32_t)(kMasterDMAIrqFlags)); + + if (transfer->busType == kI3C_TypeI2C) + { + I3C_MasterDisableInterrupts(base, (uint32_t)kI3C_MasterSlaveStartFlag); + } + + return kStatus_Success; +} + +void I3C_MasterTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle) +{ + i3c_master_edma_handle_t *handle = (i3c_master_edma_handle_t *)i3cHandle; + + bool isDone; + status_t result; + + /* Don't do anything if we don't have a valid handle. */ + if (NULL == handle) + { + return; + } + + result = I3C_MasterRunTransferStateMachineEDMA(base, handle, &isDone); + + if (handle->state == (uint8_t)kIdleState) + { + return; + } + + if (isDone || (result != kStatus_Success)) + { + /* XXX need to handle data that may be in rx fifo below watermark level? */ + + /* XXX handle error, terminate xfer */ + if ((result == kStatus_I3C_Nak) || (result == kStatus_I3C_IBIWon)) + { + I3C_MasterEmitRequest(base, kI3C_RequestEmitStop); + (void)I3C_MasterWaitForCtrlDone(base, false); + } + + /* Set handle to idle state. */ + handle->state = (uint8_t)kIdleState; + + /* Invoke IBI user callback. */ + if ((result == kStatus_I3C_IBIWon) && (handle->callback.ibiCallback != NULL)) + { + handle->callback.ibiCallback(base, handle, handle->ibiType, kI3C_IbiReady); + handle->ibiPayloadSize = 0; + } + + /* Invoke callback. */ + if (NULL != handle->callback.transferComplete) + { + handle->callback.transferComplete(base, handle, result, handle->userData); + } + } +} + +/*! + * brief Get master transfer status during a dma non-blocking transfer + * + * param base I3C peripheral base address + * param handle pointer to i2c_master_edma_handle_t structure + * param count Number of bytes transferred so far by the non-blocking transaction. + */ +status_t I3C_MasterTransferGetCountEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state == (uint8_t)kIdleState) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + /* There is no necessity to disable interrupts as we read a single integer value */ + i3c_direction_t dir = handle->transfer.direction; + + if (dir == kI3C_Read) + { + *count = handle->transferCount - + 1U * EDMA_GetRemainingMajorLoopCount(handle->rxDmaHandle->base, handle->rxDmaHandle->channel); + } + else + { + *count = handle->transferCount - + 1U * EDMA_GetRemainingMajorLoopCount(handle->txDmaHandle->base, handle->txDmaHandle->channel); + } + + return kStatus_Success; +} + +/*! + * brief Abort a master edma non-blocking transfer in a early time + * + * param base I3C peripheral base address + * param handle pointer to i2c_master_edma_handle_t structure + */ +void I3C_MasterTransferAbortEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle) +{ + if (handle->state != (uint8_t)kIdleState) + { + EDMA_AbortTransfer(handle->txDmaHandle); + EDMA_AbortTransfer(handle->rxDmaHandle); + + I3C_MasterEnableDMA(base, false, false, 0); + + /* Reset fifos. These flags clear automatically. */ + base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK; + + /* Send a stop command to finalize the transfer. */ + (void)I3C_MasterStop(base); + + /* Reset handle. */ + handle->state = (uint8_t)kIdleState; + } +} + +static void I3C_SlaveTransferEDMACallback(edma_handle_t *dmaHandle, void *param, bool transferDone, uint32_t tcds) +{ + i3c_slave_edma_handle_t *i3cHandle = (i3c_slave_edma_handle_t *)param; + + if (transferDone) + { + /* Simply disable dma enablement */ + if (i3cHandle->txDmaHandle == dmaHandle) + { + i3cHandle->base->SDMACTRL &= ~I3C_SDMACTRL_DMATB_MASK; + + if (i3cHandle->transfer.txDataSize > 1U) + { + /* Ensure there's space in the Tx FIFO. */ + while ((i3cHandle->base->SDATACTRL & I3C_SDATACTRL_TXFULL_MASK) != 0U) + { + } + /* Send the last byte. */ + i3cHandle->base->SWDATABE = *(uint8_t *)((uintptr_t)i3cHandle->transfer.txData + i3cHandle->transfer.txDataSize - 1U); + } + } + else + { +#if defined(FSL_FEATURE_I3C_HAS_ERRATA_052086) && (FSL_FEATURE_I3C_HAS_ERRATA_052086) + if (i3cHandle->transfer.rxDataSize > 1U) + { + size_t rxCount; + /* Read out the last byte data. */ + do + { + I3C_SlaveGetFifoCounts(i3cHandle->base, &rxCount, NULL); + } while (rxCount == 0U); + *(uint8_t *)((uintptr_t)i3cHandle->transfer.rxData + i3cHandle->transfer.rxDataSize - 1U) = + (uint8_t)i3cHandle->base->SRDATAB; + } +#endif + i3cHandle->base->SDMACTRL &= ~I3C_SDMACTRL_DMAFB_MASK; + } + } +} + +/*! + * brief Create a new handle for the I3C slave DMA APIs. + * + * The creation of a handle is for use with the DMA APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I3C_SlaveTransferAbortDMA() API shall be called. + * + * For devices where the I3C send and receive DMA requests are OR'd together, the @a txDmaHandle + * parameter is ignored and may be set to NULL. + * + * param base The I3C peripheral base address. + * param handle Pointer to the I3C slave driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + * param rxDmaHandle Handle for the DMA receive channel. Created by the user prior to calling this function. + * param txDmaHandle Handle for the DMA transmit channel. Created by the user prior to calling this function. + */ +void I3C_SlaveTransferCreateHandleEDMA(I3C_Type *base, + i3c_slave_edma_handle_t *handle, + i3c_slave_edma_callback_t callback, + void *userData, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle) +{ + uint32_t instance; + + assert(NULL != handle); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = I3C_GetInstance(base); + + handle->base = base; + handle->txDmaHandle = txDmaHandle; + handle->rxDmaHandle = rxDmaHandle; + handle->callback = callback; + handle->userData = userData; + + /* Save this handle for IRQ use. */ + s_i3cSlaveHandle[instance] = handle; + + /* Set irq handler. */ + s_i3cSlaveIsr = I3C_SlaveTransferEDMAHandleIRQ; + + EDMA_SetCallback(handle->rxDmaHandle, I3C_SlaveTransferEDMACallback, handle); + EDMA_SetCallback(handle->txDmaHandle, I3C_SlaveTransferEDMACallback, handle); + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + I3C_SlaveDisableInterrupts(base, (uint32_t)kSlaveDMAIrqFlags); + + /* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC. + In some cases the I3C IRQ is configured through INTMUX, user needs to enable + INTMUX IRQ in application code. */ + (void)EnableIRQ(kI3cIrqs[instance]); + + /* Enable IRQ. */ + I3C_SlaveEnableInterrupts(base, (uint32_t)kSlaveDMAIrqFlags); +} + +static void I3C_SlavePrepareTxEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle) +{ + edma_transfer_config_t txConfig; + uint32_t *txFifoBase; + i3c_slave_edma_transfer_t *xfer = &handle->transfer; + + if (xfer->txDataSize == 1U) + { + txFifoBase = (uint32_t *)(uintptr_t)&base->SWDATABE; + EDMA_PrepareTransfer(&txConfig, xfer->txData, 1, (void *)txFifoBase, 1, 1, xfer->txDataSize, + kEDMA_MemoryToPeripheral); + } + else + { + txFifoBase = (uint32_t *)(uintptr_t)&base->SWDATAB1; + EDMA_PrepareTransfer(&txConfig, xfer->txData, 1, (void *)txFifoBase, 1, 1, xfer->txDataSize - 1U, + kEDMA_MemoryToPeripheral); + } + + (void)EDMA_SubmitTransfer(handle->txDmaHandle, &txConfig); + EDMA_StartTransfer(handle->txDmaHandle); +} + +static void I3C_SlavePrepareRxEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle) +{ + uint32_t *rxFifoBase = (uint32_t *)(uintptr_t)&base->SRDATAB; + i3c_slave_edma_transfer_t *xfer = &handle->transfer; + size_t dataSize = xfer->rxDataSize; + edma_transfer_config_t rxConfig; + +#if defined(FSL_FEATURE_I3C_HAS_ERRATA_052086) && (FSL_FEATURE_I3C_HAS_ERRATA_052086) + /* ERRATA052086: Soc integration issue results in target misses the last DMA request to copy the + last one byte from controler when transmission data size is > 1 byte. Resolution: Triggering DMA + interrupt one byte in advance, then receive the last one byte data after DMA transmission finishes. */ + if (dataSize > 1U) + { + dataSize--; + } +#endif + + EDMA_PrepareTransfer(&rxConfig, (void *)rxFifoBase, 1, xfer->rxData, 1, 1, dataSize, + kEDMA_PeripheralToMemory); + (void)EDMA_SubmitTransfer(handle->rxDmaHandle, &rxConfig); + EDMA_StartTransfer(handle->rxDmaHandle); +} + +/*! + * brief Prepares for a non-blocking DMA-based transaction on the I3C bus. + * + * The API will do DMA configuration according to the input transfer descriptor, and the data will be transferred when + * there's bus master requesting transfer from/to this slave. So the timing of call to this API need be aligned + * with master application to ensure the transfer is executed as expected. + * Callback specified when the @a handle was created is invoked when the transaction has completed. + * + * param base The I3C peripheral base address. + * param handle Pointer to the I3C slave driver handle. + * param transfer The pointer to the transfer descriptor. + * param eventMask Bit mask formed by OR'ing together #i3c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. The transmit and receive events is not allowed to be enabled. + * retval kStatus_Success The transaction was started successfully. + * retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or another DMA + * transaction is already in progress. + * retval #kStatus_Fail The transaction can't be set. + */ +status_t I3C_SlaveTransferEDMA(I3C_Type *base, + i3c_slave_edma_handle_t *handle, + i3c_slave_edma_transfer_t *transfer, + uint32_t eventMask) +{ + assert(NULL != handle); + assert(NULL != transfer); + + bool txDmaEn = false, rxDmaEn = false; + uint32_t width; + + if (handle->isBusy) + { + return kStatus_I3C_Busy; + } + /* Clear all flags. */ + I3C_SlaveClearErrorStatusFlags(base, (uint32_t)kSlaveErrorFlags); + I3C_SlaveClearStatusFlags(base, (uint32_t)kSlaveClearFlags); + /* Reset fifos. These flags clear automatically. */ + base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK | I3C_SDATACTRL_FLUSHFB_MASK; + + handle->transfer = *transfer; + + /* Set up event mask. */ + handle->eventMask = eventMask; + + if ((transfer->txData != NULL) && (transfer->txDataSize != 0U)) + { + I3C_SlavePrepareTxEDMA(base, handle); + txDmaEn = true; + width = 1U; + } + + if ((transfer->rxData != NULL) && (transfer->rxDataSize != 0U)) + { + I3C_SlavePrepareRxEDMA(base, handle); + rxDmaEn = true; + width = 1U; + } + + if (txDmaEn || rxDmaEn) + { + I3C_SlaveEnableDMA(base, txDmaEn, rxDmaEn, width); + return kStatus_Success; + } + else + { + return kStatus_Fail; + } +} + +void I3C_SlaveTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle) +{ + uint32_t flags; + uint32_t errFlags; + i3c_slave_edma_transfer_t *xfer; + + i3c_slave_edma_handle_t *handle = (i3c_slave_edma_handle_t *)i3cHandle; + /* Check for a valid handle in case of a spurious interrupt. */ + if (NULL == handle) + { + return; + } + + xfer = &handle->transfer; + + /* Get status flags. */ + flags = I3C_SlaveGetStatusFlags(base); + errFlags = I3C_SlaveGetErrorStatusFlags(base); + + /* Clear status flags. */ + I3C_SlaveClearStatusFlags(base, flags); + + if (0UL != (errFlags & (uint32_t)kSlaveErrorFlags)) + { + xfer->event = (uint32_t)kI3C_SlaveCompletionEvent; + xfer->completionStatus = I3C_SlaveCheckAndClearError(base, errFlags); + + if ((0UL != (handle->eventMask & (uint32_t)kI3C_SlaveCompletionEvent)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + return; + } + + if (0UL != (flags & (uint32_t)kI3C_SlaveEventSentFlag)) + { + xfer->event = (uint32_t)kI3C_SlaveRequestSentEvent; + if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + + if (0UL != (flags & (uint32_t)kI3C_SlaveReceivedCCCFlag)) + { + handle->isBusy = true; + xfer->event = (uint32_t)kI3C_SlaveReceivedCCCEvent; + if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + + if (0UL != (flags & (uint32_t)kI3C_SlaveBusStopFlag)) + { + if (handle->isBusy == true) + { + xfer->event = (uint32_t)kI3C_SlaveCompletionEvent; + xfer->completionStatus = kStatus_Success; + handle->isBusy = false; + + if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + I3C_SlaveTransferAbortEDMA(base, handle); + } + else + { + return; + } + } + + if (0UL != (flags & (uint32_t)kI3C_SlaveMatchedFlag)) + { + xfer->event = (uint32_t)kI3C_SlaveAddressMatchEvent; + handle->isBusy = true; + if ((0UL != (handle->eventMask & (uint32_t)kI3C_SlaveAddressMatchEvent)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } +} + +/*! + * brief Abort a slave dma non-blocking transfer in a early time + * + * param base I3C peripheral base address + * param handle pointer to i3c_slave_edma_handle_t structure + */ +void I3C_SlaveTransferAbortEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle) +{ + if (handle->isBusy != false) + { + EDMA_AbortTransfer(handle->txDmaHandle); + EDMA_AbortTransfer(handle->rxDmaHandle); + + I3C_SlaveEnableDMA(base, false, false, 0); + + /* Reset fifos. These flags clear automatically. */ + base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK | I3C_SDATACTRL_FLUSHFB_MASK; + } +} \ No newline at end of file diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_i3c_edma.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_i3c_edma.h new file mode 100644 index 00000000000..8396e350d35 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_i3c_edma.h @@ -0,0 +1,279 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_I3C_EDMA_H_ +#define FSL_I3C_EDMA_H_ + +#include "fsl_i3c.h" +#include "fsl_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief I3C EDMA driver version. */ +#define FSL_I3C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 9)) +/*! @} */ + +/*! + * @addtogroup i3c_master_edma_driver + * @{ + */ + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +typedef struct _i3c_master_edma_handle i3c_master_edma_handle_t; + +/*! @brief i3c master callback functions. */ +typedef struct _i3c_master_edma_callback +{ + void (*slave2Master)(I3C_Type *base, void *userData); /*!< Transfer complete callback */ + void (*ibiCallback)(I3C_Type *base, + i3c_master_edma_handle_t *handle, + i3c_ibi_type_t ibiType, + i3c_ibi_state_t ibiState); /*!< IBI event callback */ + void (*transferComplete)(I3C_Type *base, + i3c_master_edma_handle_t *handle, + status_t status, + void *userData); /*!< Transfer complete callback */ +} i3c_master_edma_callback_t; +/*! + * @brief Driver handle for master EDMA APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _i3c_master_edma_handle +{ + I3C_Type *base; /*!< I3C base pointer. */ + uint8_t state; /*!< Transfer state machine current state. */ + uint32_t transferCount; /*!< Indicates progress of the transfer */ + uint8_t subaddressBuffer[4]; /*!< Saving subaddress command. */ + uint8_t subaddressCount; /*!< Saving command count. */ + i3c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + i3c_master_edma_callback_t callback; /*!< Callback function pointer. */ + void *userData; /*!< Application data passed to callback. */ + edma_handle_t *rxDmaHandle; /*!< Handle for receive DMA channel. */ + edma_handle_t *txDmaHandle; /*!< Handle for transmit DMA channel. */ + uint8_t ibiAddress; /*!< Slave address which request IBI. */ + uint8_t *ibiBuff; /*!< Pointer to IBI buffer to keep ibi bytes. */ + size_t ibiPayloadSize; /*!< IBI payload size. */ + i3c_ibi_type_t ibiType; /*!< IBI type. */ +}; + +/*! @} */ + +/*! + * @addtogroup i3c_slave_edma_driver + * @{ + */ +/* Forward declaration of the transfer descriptor and handle typedefs. */ +typedef struct _i3c_slave_edma_handle i3c_slave_edma_handle_t; + +/*! @brief I3C slave transfer structure */ +typedef struct _i3c_slave_edma_transfer +{ + uint32_t event; /*!< Reason the callback is being invoked. */ + uint8_t *txData; /*!< Transfer buffer */ + size_t txDataSize; /*!< Transfer size */ + uint8_t *rxData; /*!< Transfer buffer */ + size_t rxDataSize; /*!< Transfer size */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kI3C_SlaveCompletionEvent. */ +} i3c_slave_edma_transfer_t; + +/*! + * @brief Slave event callback function pointer type. + * + * This callback is used only for the slave DMA transfer API. + * + * @param base Base address for the I3C instance on which the event occurred. + * @param handle Pointer to slave DMA transfer handle. + * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*i3c_slave_edma_callback_t)(I3C_Type *base, i3c_slave_edma_transfer_t *transfer, void *userData); +/*! + * @brief I3C slave edma handle structure. + * @note The contents of this structure are private and subject to change. + */ +struct _i3c_slave_edma_handle +{ + I3C_Type *base; /*!< I3C base pointer. */ + i3c_slave_edma_transfer_t transfer; /*!< I3C slave transfer copy. */ + bool isBusy; /*!< Whether transfer is busy. */ + bool wasTransmit; /*!< Whether the last transfer was a transmit. */ + uint32_t eventMask; /*!< Mask of enabled events. */ + i3c_slave_edma_callback_t callback; /*!< Callback function called at transfer event. */ + edma_handle_t *rxDmaHandle; /*!< Handle for receive DMA channel. */ + edma_handle_t *txDmaHandle; /*!< Handle for transmit DMA channel. */ + void *userData; /*!< Callback parameter passed to callback. */ +}; +/*! @} */ +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup i3c_master_edma_driver + * @{ + */ + +/*! @name Master DMA */ +/*! @{ */ + +/*! + * @brief Create a new handle for the I3C master DMA APIs. + * + * The creation of a handle is for use with the DMA APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I3C_MasterTransferAbortDMA() API shall be called. + * + * For devices where the I3C send and receive DMA requests are OR'd together, the @a txDmaHandle + * parameter is ignored and may be set to NULL. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + * @param rxDmaHandle Handle for the DMA receive channel. Created by the user prior to calling this function. + * @param txDmaHandle Handle for the DMA transmit channel. Created by the user prior to calling this function. + */ +void I3C_MasterTransferCreateHandleEDMA(I3C_Type *base, + i3c_master_edma_handle_t *handle, + const i3c_master_edma_callback_t *callback, + void *userData, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle); + +/*! + * @brief Performs a non-blocking DMA-based transaction on the I3C bus. + * + * The callback specified when the @a handle was created is invoked when the transaction has + * completed. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + * @param transfer The pointer to the transfer descriptor. + * @retval kStatus_Success The transaction was started successfully. + * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or another DMA + * transaction is already in progress. + */ +status_t I3C_MasterTransferEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, i3c_master_transfer_t *transfer); + +/*! + * @brief Returns number of bytes transferred so far. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + * @param[out] count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_Success + * @retval kStatus_NoTransferInProgress There is not a DMA transaction currently in progress. + */ +status_t I3C_MasterTransferGetCountEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, size_t *count); + +/*! + * @brief Terminates a non-blocking I3C master transmission early. + * + * @note It is not safe to call this function from an IRQ handler that has a higher priority than the + * DMA peripheral's IRQ priority. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C master driver handle. + */ +void I3C_MasterTransferAbortEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle); + +/*! + * @brief Reusable routine to handle master interrupts. + * @note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * @param base The I3C peripheral base address. + * @param i3cHandle Pointer to the I3C master DMA driver handle. + */ +void I3C_MasterTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle); +/*! @} */ + +/*! @} */ + +/*! + * @addtogroup i3c_slave_edma_driver + * @{ + */ + +/*! @name Slave DMA */ +/*! @{ */ +/*! + * @brief Create a new handle for the I3C slave DMA APIs. + * + * The creation of a handle is for use with the DMA APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the I3C_SlaveTransferAbortDMA() API shall be called. + * + * For devices where the I3C send and receive DMA requests are OR'd together, the @a txDmaHandle + * parameter is ignored and may be set to NULL. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C slave driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + * @param rxDmaHandle Handle for the DMA receive channel. Created by the user prior to calling this function. + * @param txDmaHandle Handle for the DMA transmit channel. Created by the user prior to calling this function. + */ +void I3C_SlaveTransferCreateHandleEDMA(I3C_Type *base, + i3c_slave_edma_handle_t *handle, + i3c_slave_edma_callback_t callback, + void *userData, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle); + +/*! + * @brief Prepares for a non-blocking DMA-based transaction on the I3C bus. + * + * The API will do DMA configuration according to the input transfer descriptor, and the data will be transferred when + * there's bus master requesting transfer from/to this slave. So the timing of call to this API need be aligned + * with master application to ensure the transfer is executed as expected. + * Callback specified when the @a handle was created is invoked when the transaction has completed. + * + * @param base The I3C peripheral base address. + * @param handle Pointer to the I3C slave driver handle. + * @param transfer The pointer to the transfer descriptor. + * @param eventMask Bit mask formed by OR'ing together #i3c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. The transmit and receive events is not allowed to be enabled. + * @retval kStatus_Success The transaction was started successfully. + * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or another DMA + * transaction is already in progress. + * @retval #kStatus_Fail The transaction can't be set. + */ +status_t I3C_SlaveTransferEDMA(I3C_Type *base, + i3c_slave_edma_handle_t *handle, + i3c_slave_edma_transfer_t *transfer, + uint32_t eventMask); +/*! + * @brief Abort a slave edma non-blocking transfer in a early time + * + * @param base I3C peripheral base address + * @param handle pointer to i3c_slave_edma_handle_t structure + */ +void I3C_SlaveTransferAbortEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle); + +/*! + * @brief Reusable routine to handle slave interrupts. + * @note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * @param base The I3C peripheral base address. + * @param i3cHandle Pointer to the I3C slave DMA driver handle. + */ +void I3C_SlaveTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle); +/*! @} */ + +/*! @} */ +#if defined(__cplusplus) +} +#endif + +#endif /* FSL_I3C_EDMA_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_inputmux.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_inputmux.c new file mode 100644 index 00000000000..1f2ce0bcd26 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_inputmux.c @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021, 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_inputmux.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.inputmux" +#endif + +#if defined(INPUTMUX_RSTS) +#define INPUTMUX_RESETS_ARRAY INPUTMUX_RSTS +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(INPUTMUX_RESETS_ARRAY) +/*! + * @brief Get instance number for INPUTMUX module. + * + * @param base INPUTMUX peripheral base address + */ +static uint32_t INPUTMUX_GetInstance(INPUTMUX_Type *base); +#endif +/******************************************************************************* + * Variables + ******************************************************************************/ +#if defined(INPUTMUX_RESETS_ARRAY) +/*! @brief Pointers to INPUTMUX bases for each instance. */ +static INPUTMUX_Type *const s_inputmuxBases[] = INPUTMUX_BASE_PTRS; + +/* Reset array */ +static const reset_ip_name_t s_inputmuxResets[] = INPUTMUX_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(INPUTMUX_RESETS_ARRAY) +static uint32_t INPUTMUX_GetInstance(INPUTMUX_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_inputmuxBases); instance++) + { + if (s_inputmuxBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_inputmuxBases)); + + return instance; +} +#endif + +/*! + * brief Initialize INPUTMUX peripheral. + + * This function enables the INPUTMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * + * retval None. + */ +void INPUTMUX_Init(INPUTMUX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE +#if (defined(FSL_FEATURE_SOC_SCT_COUNT) && (FSL_FEATURE_SOC_SCT_COUNT > 0)) + CLOCK_EnableClock(kCLOCK_Sct); +#endif /* FSL_FEATURE_SOC_SCT_COUNT */ + CLOCK_EnableClock(kCLOCK_Dma); +#else + CLOCK_EnableClock(kCLOCK_InputMux); +#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(INPUTMUX_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_inputmuxResets[INPUTMUX_GetInstance(base)]); +#endif +} + +/*! + * brief Attaches a signal + * + * This function attaches multiplexed signals from INPUTMUX to target signals. + * For example, to attach GPIO PORT0 Pin 5 to PINT peripheral, do the following: + * code + * INPUTMUX_AttachSignal(INPUTMUX, 2, kINPUTMUX_GpioPort0Pin5ToPintsel); + * endcode + * In this example, INTMUX has 8 registers for PINT, PINT_SEL0~PINT_SEL7. + * With parameter p index specified as 2, this function configures register PINT_SEL2. + * + * param base Base address of the INPUTMUX peripheral. + * param index The serial number of destination register in the group of INPUTMUX registers with same name. + * param connection Applies signal from source signals collection to target signal. + * + * retval None. + */ +void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection) +{ + uint32_t pmux_id; + uint32_t output_id; + + /* extract pmux to be used */ + pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT; + /* extract function number */ + output_id = ((uint32_t)(connection)) & ((1UL << PMUX_SHIFT) - 1U); + /* programm signal */ + *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4U)) = output_id; +} + +#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) +/*! + * brief Enable/disable a signal + * + * This function gates the INPUTPMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * param signal Enable signal register id and bit offset. + * param enable Selects enable or disable. + * + * retval None. + */ +void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable) +{ + uint32_t ena_id; + uint32_t ena_id_mask = (1UL << (32U - ENA_SHIFT)) - 1U; + uint32_t bit_offset; + +#if defined(FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX) && FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX + uint32_t chmux_offset; + uint32_t chmux_value; + + /* Only enable need to update channel mux */ + if (enable && ((((uint32_t)signal) & (1UL << CHMUX_AVL_SHIFT)) != 0U)) + { + chmux_offset = (((uint32_t)signal) >> CHMUX_OFF_SHIFT) & ((1UL << (CHMUX_AVL_SHIFT - CHMUX_OFF_SHIFT)) - 1UL); + chmux_value = (((uint32_t)signal) >> CHMUX_VAL_SHIFT) & ((1UL << (CHMUX_OFF_SHIFT - CHMUX_VAL_SHIFT)) - 1UL); + *(volatile uint32_t *)(((uint32_t)base) + chmux_offset) = chmux_value; + } + ena_id_mask = (1UL << (CHMUX_VAL_SHIFT - ENA_SHIFT)) - 1U; +#endif + /* extract enable register to be used */ + ena_id = (((uint32_t)signal) >> ENA_SHIFT) & ena_id_mask; + /* extract enable bit offset */ + bit_offset = ((uint32_t)signal) & ((1UL << ENA_SHIFT) - 1U); + /* set signal */ + if (enable) + { + *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1UL << bit_offset); + } + else + { + *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1UL << bit_offset); + } +} +#endif + +/*! + * brief Deinitialize INPUTMUX peripheral. + + * This function disables the INPUTMUX clock. + * + * param base Base address of the INPUTMUX peripheral. + * + * retval None. + */ +void INPUTMUX_Deinit(INPUTMUX_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE) && FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE +#if (defined(FSL_FEATURE_SOC_SCT_COUNT) && (FSL_FEATURE_SOC_SCT_COUNT > 0)) + CLOCK_DisableClock(kCLOCK_Sct); +#endif /* FSL_FEATURE_SOC_SCT_COUNT */ + CLOCK_DisableClock(kCLOCK_Dma); +#else + CLOCK_DisableClock(kCLOCK_InputMux); +#endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_inputmux.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_inputmux.h new file mode 100644 index 00000000000..a8d5db82ec7 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_inputmux.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021, 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_INPUTMUX_H_ +#define FSL_INPUTMUX_H_ + +#include "fsl_inputmux_connections.h" +#include "fsl_common.h" + +/*! + * @addtogroup inputmux_driver + * @{ + */ + +/*! @file */ +/*! @file fsl_inputmux_connections.h */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief Group interrupt driver version for SDK */ +#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 7)) +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Initialize INPUTMUX peripheral. + + * This function enables the INPUTMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * + * @retval None. + */ +void INPUTMUX_Init(INPUTMUX_Type *base); + +/*! + * @brief Attaches a signal + * + * This function attaches multiplexed signals from INPUTMUX to target signals. + * For example, to attach GPIO PORT0 Pin 5 to PINT peripheral, do the following: + * @code + * INPUTMUX_AttachSignal(INPUTMUX, 2, kINPUTMUX_GpioPort0Pin5ToPintsel); + * @endcode + * In this example, INTMUX has 8 registers for PINT, PINT_SEL0~PINT_SEL7. + * With parameter @p index specified as 2, this function configures register PINT_SEL2. + * + * @param base Base address of the INPUTMUX peripheral. + * @param index The serial number of destination register in the group of INPUTMUX registers with same name. + * @param connection Applies signal from source signals collection to target signal. + * + * @retval None. + */ +void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection); + +#if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) +/*! + * @brief Enable/disable a signal + * + * This function gates the INPUTPMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * @param signal Enable signal register id and bit offset. + * @param enable Selects enable or disable. + * + * @retval None. + */ +void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable); +#endif + +/*! + * @brief Deinitialize INPUTMUX peripheral. + + * This function disables the INPUTMUX clock. + * + * @param base Base address of the INPUTMUX peripheral. + * + * @retval None. + */ +void INPUTMUX_Deinit(INPUTMUX_Type *base); + +#ifdef __cplusplus +} +#endif + +/*! @} */ + +#endif /* FSL_INPUTMUX_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_inputmux_connections.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_inputmux_connections.h new file mode 100644 index 00000000000..8086197ffff --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_inputmux_connections.h @@ -0,0 +1,3635 @@ +/* + * Copyright 2023 , NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_INPUTMUX_CONNECTIONS_ +#define _FSL_INPUTMUX_CONNECTIONS_ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections" +#endif + +#define INPUTMUX_GpioPortPinToPintsel(port, pin) ((pin) + (PINTSEL_PMUX_ID << PMUX_SHIFT)) + +/*! + * @addtogroup inputmux_driver + * @{ + */ + +/*! + * @name Input multiplexing connections + * @{ + */ + +/*! @brief Periphinmux IDs */ +#define TIMER0CAPTSEL0 0x20U +#define TIMER0TRIGIN 0x30U +#define TIMER1CAPTSEL0 0x40U +#define TIMER1TRIGIN 0x50U +#define TIMER2CAPTSEL0 0x60U +#define TIMER2TRIGIN 0x70U +#define FREQMEAS_REF_REG 0x180U +#define FREQMEAS_TAR_REG 0x184U +#define TIMER3CAPTSEL0 0x1A0U +#define TIMER3TRIGIN 0x1B0U +#define TIMER4CAPTSEL0 0x1C0U +#define TIMER4TRIGIN 0x1D0U +#define AOI1_MUX_REG 0x200U +#define CMP0_TRIG_REG 0x260U +#define ADC0_TRIG0_REG 0x280U +#define ADC1_TRIG0_REG 0x2C0U +#define DAC0_TRIG0_REG 0x300U +#define QDC0_TRIG_REG 0x360U +#define QDC0_HOME_REG 0x364U +#define QDC0_INDEX_REG 0x368U +#define QDC0_PHASEB_REG 0x36CU +#define QDC0_PHASEA_REG 0x370U +#define QDC0_ICAP1_REG 0x374U +#define QDC1_TRIG_REG 0x380U +#define QDC1_HOME_REG 0x384U +#define QDC1_INDEX_REG 0x388U +#define QDC1_PHASEB_REG 0x38CU +#define QDC1_PHASEA_REG 0x390U +#define QDC1_ICAP1_REG 0x394U +#define FlexPWM0_SM0_EXTA0_REG 0x3A0U +#define FlexPWM0_SM0_EXTSYNC0_REG 0x3A4U +#define FlexPWM0_SM1_EXTA1_REG 0x3A8U +#define FlexPWM0_SM1_EXTSYNC1_REG 0x3ACU +#define FlexPWM0_SM2_EXTA2_REG 0x3B0U +#define FlexPWM0_SM2_EXTSYNC2_REG 0x3B4U +#define FlexPWM0_FAULT_REG 0x3C0U +#define FlexPWM0_FORCE_REG 0x3D0U +#define FlexPWM1_SM0_EXTA0_REG 0x3E0U +#define FlexPWM1_SM0_EXTSYNC0_REG 0x3E4U +#define FlexPWM1_SM1_EXTA1_REG 0x3E8U +#define FlexPWM1_SM1_EXTSYNC1_REG 0x3ECU +#define FlexPWM1_SM2_EXTA2_REG 0x3F0U +#define FlexPWM1_SM2_EXTSYNC2_REG 0x3F4U +#define FlexPWM1_FAULT_REG 0x400U +#define FlexPWM1_FORCE_REG 0x410U +#define PWM0_EXT_CLK_REG 0x420U +#define PWM1_EXT_CLK_REG 0x424U +#define AOI0_MUX_REG 0x440U +#define USBFS_TRIG_REG 0x480U +#define EXT_TRIG0_REG 0x4C0U +#define CMP1_TRIG_REG 0x4E0U +#define LPI2C2_TRIG_REG 0x540U +#define OPAMP0_TRIG_REG 0x580U +#define LPI2C0_TRIG_REG 0x5A0U +#define LPI2C1_TRIG_REG 0x5C0U +#define LPSPI0_TRIG_REG 0x5E0U +#define LPSPI1_TRIG_REG 0x600U +#define LPUART0_TRIG_REG 0x620U +#define LPUART1_TRIG_REG 0x640U +#define LPUART2_TRIG_REG 0x660U +#define LPUART3_TRIG_REG 0x680U +#define LPUART4_TRIG_REG 0x6A0U +#define FLEXIO_TRIG0_REG 0x6E0U +#define PMUX_SHIFT 20U + +typedef enum _inputmux_index_t +{ + kINPUTMUX_INDEX_CTIMER0CAPTSEL0 = 0U, + kINPUTMUX_INDEX_CTIMER0CAPTSEL1 = 1U, + kINPUTMUX_INDEX_CTIMER0CAPTSEL2 = 2U, + kINPUTMUX_INDEX_CTIMER0CAPTSEL3 = 3U, + kINPUTMUX_INDEX_CTIMER1CAPTSEL0 = 0U, + kINPUTMUX_INDEX_CTIMER1CAPTSEL1 = 1U, + kINPUTMUX_INDEX_CTIMER1CAPTSEL2 = 2U, + kINPUTMUX_INDEX_CTIMER1CAPTSEL3 = 3U, + kINPUTMUX_INDEX_CTIMER2CAPTSEL0 = 0U, + kINPUTMUX_INDEX_CTIMER2CAPTSEL1 = 1U, + kINPUTMUX_INDEX_CTIMER2CAPTSEL2 = 2U, + kINPUTMUX_INDEX_CTIMER2CAPTSEL3 = 3U, + kINPUTMUX_INDEX_ADC0_TRIGSEL0 = 0U, + kINPUTMUX_INDEX_ADC0_TRIGSEL1 = 1U, + kINPUTMUX_INDEX_ADC0_TRIGSEL2 = 2U, + kINPUTMUX_INDEX_ADC0_TRIGSEL3 = 3U, + kINPUTMUX_INDEX_QDC0_ICAPSEL0 = 0U, + kINPUTMUX_INDEX_QDC0_ICAPSEL1 = 1U, + kINPUTMUX_INDEX_QDC0_ICAPSEL2 = 2U, + kINPUTMUX_INDEX_FLEXPWM0_FAULTSEL0 = 0U, + kINPUTMUX_INDEX_FLEXPWM0_FAULTSEL1 = 1U, + kINPUTMUX_INDEX_FLEXPWM0_FAULTSEL2 = 2U, + kINPUTMUX_INDEX_FLEXPWM0_FAULTSEL3 = 3U, + kINPUTMUX_INDEX_AOI0_TRIGSEL0 = 0U, + kINPUTMUX_INDEX_AOI0_TRIGSEL1 = 1U, + kINPUTMUX_INDEX_AOI0_TRIGSEL2 = 2U, + kINPUTMUX_INDEX_AOI0_TRIGSEL3 = 3U, + kINPUTMUX_INDEX_AOI0_TRIGSEL4 = 4U, + kINPUTMUX_INDEX_AOI0_TRIGSEL5 = 5U, + kINPUTMUX_INDEX_AOI0_TRIGSEL6 = 6U, + kINPUTMUX_INDEX_AOI0_TRIGSEL7 = 7U, + kINPUTMUX_INDEX_AOI0_TRIGSEL8 = 8U, + kINPUTMUX_INDEX_AOI0_TRIGSEL9 = 9U, + kINPUTMUX_INDEX_AOI0_TRIGSEL10 = 10U, + kINPUTMUX_INDEX_AOI0_TRIGSEL11 = 11U, + kINPUTMUX_INDEX_AOI0_TRIGSEL12 = 12U, + kINPUTMUX_INDEX_AOI0_TRIGSEL13 = 13U, + kINPUTMUX_INDEX_AOI0_TRIGSEL14 = 14U, + kINPUTMUX_INDEX_AOI0_TRIGSEL15 = 15U, + kINPUTMUX_INDEX_EXT_TRIGSEL0 = 0U, + kINPUTMUX_INDEX_EXT_TRIGSEL1 = 1U, + kINPUTMUX_INDEX_EXT_TRIGSEL2 = 2U, + kINPUTMUX_INDEX_EXT_TRIGSEL3 = 3U, + kINPUTMUX_INDEX_EXT_TRIGSEL4 = 4U, + kINPUTMUX_INDEX_EXT_TRIGSEL6 = 6U, + kINPUTMUX_INDEX_EXT_TRIGSEL7 = 7U +} inputmux_index_t; + +/*! @brief INPUTMUX connections type */ +typedef enum _inputmux_connection_t +{ + /*!< TIMER0 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer0Captsel = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer0Captsel = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer0Captsel = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer0Captsel = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer0Captsel = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer0Captsel = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer0Captsel = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer0Captsel = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer0Captsel = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer0Captsel = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer0Captsel = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer0Captsel = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer0Captsel = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer0Captsel = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer0Captsel = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer0Captsel = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer0Captsel = 17U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer0Captsel = 18U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer0Captsel = 19U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer0Captsel = 20U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer0Captsel = 21U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer0Captsel = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer0Captsel = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer0Captsel = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer0Captsel = 25U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer0Captsel = 26U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer0Captsel = 27U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer0Captsel = 28U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer0Captsel = 29U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer0Captsel = 30U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer0Captsel = 31U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToTimer0Captsel = 33U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToTimer0Captsel = 34U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToTimer0Captsel = 35U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToTimer0Captsel = 36U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToTimer0Captsel = 37U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToTimer0Captsel = 38U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer0Captsel = 39U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer0Captsel = 40U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer0Captsel = 41U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer0Captsel = 42U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer0Captsel = 43U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer0Captsel = 44U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer0Captsel = 45U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer0Captsel = 46U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer0Captsel = 48U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer0Captsel = 49U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer0Captsel = 52U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer0Captsel = 53U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer0Captsel = 54U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer0Captsel = 55U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer0Captsel = 56U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer0Captsel = 57U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer0Captsel = 58U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer0Captsel = 59U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer0Captsel = 60U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer0Captsel = 61U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer0Captsel = 62U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer0Captsel = 63U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer0Captsel = 64U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer0Captsel = 65U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer0Captsel = 66U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer0Captsel = 67U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer0Captsel = 68U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer0Captsel = 69U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer0Captsel = 70U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer0Captsel = 71U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer0Captsel = 72U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer0Captsel = 73U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer0Captsel = 74U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer0Captsel = 75U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer0Captsel = 76U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer0Captsel = 77U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer0Captsel = 78U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToTimer0Captsel = 79U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToTimer0Captsel = 80U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToTimer0Captsel = 81U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToTimer0Captsel = 82U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToTimer0Captsel = 83U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToTimer0Captsel = 84U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer0Captsel = 85U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer0Captsel = 86U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer0Captsel = 87U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer0Captsel = 88U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer0Captsel = 89U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer0Captsel = 90U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer0Captsel = 91U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer0Captsel = 92U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer0Captsel = 94U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer0Captsel = 95U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer0Captsel = 96U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer0Captsel = 97U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + + /*!< Timer1 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer1Captsel = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer1Captsel = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer1Captsel = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer1Captsel = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer1Captsel = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer1Captsel = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer1Captsel = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer1Captsel = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer1Captsel = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer1Captsel = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer1Captsel = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer1Captsel = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer1Captsel = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer1Captsel = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer1Captsel = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer1Captsel = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer1Captsel = 17U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer1Captsel = 18U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer1Captsel = 19U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer1Captsel = 20U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer1Captsel = 21U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer1Captsel = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer1Captsel = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer1Captsel = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer1Captsel = 25U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer1Captsel = 26U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer1Captsel = 27U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer1Captsel = 28U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer1Captsel = 29U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer1Captsel = 30U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer1Captsel = 31U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToTimer1Captsel = 33U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToTimer1Captsel = 34U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToTimer1Captsel = 35U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToTimer1Captsel = 36U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToTimer1Captsel = 37U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToTimer1Captsel = 38U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer1Captsel = 39U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer1Captsel = 40U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer1Captsel = 41U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer1Captsel = 42U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer1Captsel = 43U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer1Captsel = 44U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer1Captsel = 45U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer1Captsel = 46U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer1Captsel = 48U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer1Captsel = 49U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer1Captsel = 52U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer1Captsel = 53U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer1Captsel = 54U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer1Captsel = 55U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer1Captsel = 56U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer1Captsel = 57U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer1Captsel = 58U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer1Captsel = 59U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer1Captsel = 60U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer1Captsel = 61U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer1Captsel = 62U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer1Captsel = 63U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer1Captsel = 64U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer1Captsel = 65U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer1Captsel = 66U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer1Captsel = 67U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer1Captsel = 68U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer1Captsel = 69U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer1Captsel = 70U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer1Captsel = 71U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer1Captsel = 72U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer1Captsel = 73U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer1Captsel = 74U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer1Captsel = 75U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer1Captsel = 76U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer1Captsel = 77U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer1Captsel = 78U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToTimer1Captsel = 79U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToTimer1Captsel = 80U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToTimer1Captsel = 81U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToTimer1Captsel = 82U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToTimer1Captsel = 83U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToTimer1Captsel = 84U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer1Captsel = 85U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer1Captsel = 86U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer1Captsel = 87U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer1Captsel = 88U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer1Captsel = 89U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer1Captsel = 90U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer1Captsel = 91U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer1Captsel = 92U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer1Captsel = 94U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer1Captsel = 95U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer1Captsel = 96U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer1Captsel = 97U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + + /*!< Timer2 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer2Captsel = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer2Captsel = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer2Captsel = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer2Captsel = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer2Captsel = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer2Captsel = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer2Captsel = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer2Captsel = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer2Captsel = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer2Captsel = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer2Captsel = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer2Captsel = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer2Captsel = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer2Captsel = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer2Captsel = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer2Captsel = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer2Captsel = 17U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer2Captsel = 18U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer2Captsel = 19U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer2Captsel = 20U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer2Captsel = 21U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer2Captsel = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer2Captsel = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer2Captsel = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer2Captsel = 25U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer2Captsel = 26U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer2Captsel = 27U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer2Captsel = 28U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer2Captsel = 29U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer2Captsel = 30U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer2Captsel = 31U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToTimer2Captsel = 33U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToTimer2Captsel = 34U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToTimer2Captsel = 35U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToTimer2Captsel = 36U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToTimer2Captsel = 37U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToTimer2Captsel = 38U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer2Captsel = 39U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer2Captsel = 40U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer2Captsel = 41U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer2Captsel = 42U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer2Captsel = 43U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer2Captsel = 44U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer2Captsel = 45U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer2Captsel = 46U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer2Captsel = 48U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer2Captsel = 49U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer2Captsel = 52U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer2Captsel = 53U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer2Captsel = 54U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer2Captsel = 55U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer2Captsel = 56U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer2Captsel = 57U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer2Captsel = 58U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer2Captsel = 59U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer2Captsel = 60U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer2Captsel = 61U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer2Captsel = 62U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer2Captsel = 63U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer2Captsel = 64U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer2Captsel = 65U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer2Captsel = 66U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer2Captsel = 67U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer2Captsel = 68U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer2Captsel = 69U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer2Captsel = 70U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer2Captsel = 71U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer2Captsel = 72U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer2Captsel = 73U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer2Captsel = 74U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer2Captsel = 75U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer2Captsel = 76U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer2Captsel = 77U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer2Captsel = 78U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToTimer2Captsel = 79U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToTimer2Captsel = 80U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToTimer2Captsel = 81U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToTimer2Captsel = 82U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToTimer2Captsel = 83U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToTimer2Captsel = 84U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer2Captsel = 85U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer2Captsel = 86U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer2Captsel = 87U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer2Captsel = 88U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer2Captsel = 89U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer2Captsel = 90U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer2Captsel = 91U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer2Captsel = 92U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer2Captsel = 94U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer2Captsel = 95U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer2Captsel = 96U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer2Captsel = 97U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + + /*!< Timer3 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer3Captsel = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer3Captsel = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer3Captsel = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer3Captsel = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer3Captsel = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer3Captsel = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer3Captsel = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer3Captsel = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer3Captsel = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer3Captsel = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer3Captsel = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer3Captsel = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer3Captsel = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer3Captsel = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer3Captsel = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer3Captsel = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer3Captsel = 17U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer3Captsel = 18U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer3Captsel = 19U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer3Captsel = 20U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer3Captsel = 21U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer3Captsel = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer3Captsel = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer3Captsel = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer3Captsel = 25U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer3Captsel = 26U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer3Captsel = 27U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer3Captsel = 28U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer3Captsel = 29U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer3Captsel = 30U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer3Captsel = 31U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToTimer3Captsel = 33U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToTimer3Captsel = 34U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToTimer3Captsel = 35U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToTimer3Captsel = 36U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToTimer3Captsel = 37U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToTimer3Captsel = 38U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer3Captsel = 39U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer3Captsel = 40U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer3Captsel = 41U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer3Captsel = 42U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer3Captsel = 43U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer3Captsel = 44U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer3Captsel = 45U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer3Captsel = 46U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer3Captsel = 48U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer3Captsel = 49U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer3Captsel = 52U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer3Captsel = 53U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer3Captsel = 54U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer3Captsel = 55U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer3Captsel = 56U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer3Captsel = 57U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer3Captsel = 58U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer3Captsel = 59U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer3Captsel = 60U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer3Captsel = 61U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer3Captsel = 62U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer3Captsel = 63U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer3Captsel = 64U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer3Captsel = 65U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer3Captsel = 66U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer3Captsel = 67U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer3Captsel = 68U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer3Captsel = 69U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer3Captsel = 70U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer3Captsel = 71U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer3Captsel = 72U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer3Captsel = 73U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer3Captsel = 74U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer3Captsel = 75U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer3Captsel = 76U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer3Captsel = 77U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer3Captsel = 78U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToTimer3Captsel = 79U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToTimer3Captsel = 80U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToTimer3Captsel = 81U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToTimer3Captsel = 82U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToTimer3Captsel = 83U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToTimer3Captsel = 84U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer3Captsel = 85U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer3Captsel = 86U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer3Captsel = 87U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer3Captsel = 88U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer3Captsel = 89U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer3Captsel = 90U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer3Captsel = 91U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer3Captsel = 92U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer3Captsel = 94U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer3Captsel = 95U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer3Captsel = 96U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer3Captsel = 97U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + + /*!< Timer4 CAPTSEL. */ + kINPUTMUX_CtimerInp0ToTimer4Captsel = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer4Captsel = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer4Captsel = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer4Captsel = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer4Captsel = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer4Captsel = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer4Captsel = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer4Captsel = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer4Captsel = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer4Captsel = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer4Captsel = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer4Captsel = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer4Captsel = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer4Captsel = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer4Captsel = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer4Captsel = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer4Captsel = 17U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer4Captsel = 18U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer4Captsel = 19U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer4Captsel = 20U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer4Captsel = 21U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer4Captsel = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer4Captsel = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer4Captsel = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer4Captsel = 25U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer4Captsel = 26U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer4Captsel = 27U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer4Captsel = 28U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer4Captsel = 29U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer4Captsel = 30U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer4Captsel = 31U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToTimer4Captsel = 33U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToTimer4Captsel = 34U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToTimer4Captsel = 35U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToTimer4Captsel = 36U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToTimer4Captsel = 37U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToTimer4Captsel = 38U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer4Captsel = 39U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer4Captsel = 40U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer4Captsel = 41U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer4Captsel = 42U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer4Captsel = 43U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer4Captsel = 44U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer4Captsel = 45U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer4Captsel = 46U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer4Captsel = 48U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer4Captsel = 49U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer4Captsel = 52U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer4Captsel = 53U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer4Captsel = 54U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer4Captsel = 55U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer4Captsel = 56U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer4Captsel = 57U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer4Captsel = 58U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer4Captsel = 59U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer4Captsel = 60U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer4Captsel = 61U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer4Captsel = 62U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer4Captsel = 63U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer4Captsel = 64U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer4Captsel = 65U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer4Captsel = 66U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer4Captsel = 67U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer4Captsel = 68U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer4Captsel = 69U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer4Captsel = 70U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer4Captsel = 71U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer4Captsel = 72U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer4Captsel = 73U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer4Captsel = 74U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer4Captsel = 75U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer4Captsel = 76U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer4Captsel = 77U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer4Captsel = 78U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToTimer4Captsel = 79U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToTimer4Captsel = 80U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToTimer4Captsel = 81U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToTimer4Captsel = 82U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToTimer4Captsel = 83U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToTimer4Captsel = 84U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer4Captsel = 85U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer4Captsel = 86U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer4Captsel = 87U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer4Captsel = 88U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer4Captsel = 89U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer4Captsel = 90U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer4Captsel = 91U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer4Captsel = 92U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer4Captsel = 94U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer4Captsel = 95U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer4Captsel = 96U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer4Captsel = 97U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + + /*!< TIMER0 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer0Trigger = 1U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer0Trigger = 2U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer0Trigger = 3U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer0Trigger = 4U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer0Trigger = 5U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer0Trigger = 6U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer0Trigger = 7U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer0Trigger = 8U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer0Trigger = 9U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer0Trigger = 10U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer0Trigger = 11U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer0Trigger = 12U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer0Trigger = 13U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer0Trigger = 14U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer0Trigger = 15U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer0Trigger = 16U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer0Trigger = 17U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer0Trigger = 18U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer0Trigger = 19U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer0Trigger = 20U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer0Trigger = 21U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer0Trigger = 22U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer0Trigger = 23U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer0Trigger = 24U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer0Trigger = 25U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer0Trigger = 26U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer0Trigger = 27U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer0Trigger = 28U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer0Trigger = 29U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer0Trigger = 30U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer0Trigger = 31U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToTimer0Trigger = 33U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToTimer0Trigger = 34U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToTimer0Trigger = 35U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToTimer0Trigger = 36U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToTimer0Trigger = 37U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToTimer0Trigger = 38U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer0Trigger = 39U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer0Trigger = 40U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer0Trigger = 41U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer0Trigger = 42U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer0Trigger = 43U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer0Trigger = 44U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer0Trigger = 45U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer0Trigger = 46U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer0Trigger = 48U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer0Trigger = 49U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer0Trigger = 52U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer0Trigger = 53U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer0Trigger = 54U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer0Trigger = 55U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer0Trigger = 56U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer0Trigger = 57U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer0Trigger = 58U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer0Trigger = 59U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer0Trigger = 60U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer0Trigger = 61U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer0Trigger = 62U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer0Trigger = 63U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer0Trigger = 64U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer0Trigger = 65U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer0Trigger = 66U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer0Trigger = 67U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer0Trigger = 68U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer0Trigger = 69U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer0Trigger = 70U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer0Trigger = 71U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer0Trigger = 72U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer0Trigger = 73U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer0Trigger = 74U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer0Trigger = 75U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer0Trigger = 76U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer0Trigger = 77U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer0Trigger = 78U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToTimer0Trigger = 79U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToTimer0Trigger = 80U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToTimer0Trigger = 81U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToTimer0Trigger = 82U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToTimer0Trigger = 83U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToTimer0Trigger = 84U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer0Trigger = 85U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer0Trigger = 86U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer0Trigger = 87U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer0Trigger = 88U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer0Trigger = 89U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer0Trigger = 90U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer0Trigger = 91U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer0Trigger = 92U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer0Trigger = 94U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer0Trigger = 95U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer0Trigger = 96U + (TIMER0TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer0Trigger = 97U + (TIMER0TRIGIN << PMUX_SHIFT), + + /*!< Timer1 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer1Trigger = 1U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer1Trigger = 2U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer1Trigger = 3U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer1Trigger = 4U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer1Trigger = 5U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer1Trigger = 6U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer1Trigger = 7U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer1Trigger = 8U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer1Trigger = 9U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer1Trigger = 10U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer1Trigger = 11U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer1Trigger = 12U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer1Trigger = 13U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer1Trigger = 14U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer1Trigger = 15U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer1Trigger = 16U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer1Trigger = 17U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer1Trigger = 18U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer1Trigger = 19U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer1Trigger = 20U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer1Trigger = 21U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer1Trigger = 22U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer1Trigger = 23U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer1Trigger = 24U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer1Trigger = 25U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer1Trigger = 26U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer1Trigger = 27U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer1Trigger = 28U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer1Trigger = 29U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer1Trigger = 30U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer1Trigger = 31U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToTimer1Trigger = 33U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToTimer1Trigger = 34U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToTimer1Trigger = 35U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToTimer1Trigger = 36U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToTimer1Trigger = 37U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToTimer1Trigger = 38U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer1Trigger = 39U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer1Trigger = 40U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer1Trigger = 41U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer1Trigger = 42U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer1Trigger = 43U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer1Trigger = 44U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer1Trigger = 45U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer1Trigger = 46U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer1Trigger = 48U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer1Trigger = 49U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer1Trigger = 52U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer1Trigger = 53U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer1Trigger = 54U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer1Trigger = 55U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer1Trigger = 56U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer1Trigger = 57U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer1Trigger = 58U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer1Trigger = 59U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer1Trigger = 60U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer1Trigger = 61U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer1Trigger = 62U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer1Trigger = 63U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer1Trigger = 64U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer1Trigger = 65U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer1Trigger = 66U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer1Trigger = 67U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer1Trigger = 68U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer1Trigger = 69U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer1Trigger = 70U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer1Trigger = 71U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer1Trigger = 72U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer1Trigger = 73U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer1Trigger = 74U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer1Trigger = 75U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer1Trigger = 76U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer1Trigger = 77U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer1Trigger = 78U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToTimer1Trigger = 79U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToTimer1Trigger = 80U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToTimer1Trigger = 81U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToTimer1Trigger = 82U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToTimer1Trigger = 83U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToTimer1Trigger = 84U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer1Trigger = 85U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer1Trigger = 86U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer1Trigger = 87U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer1Trigger = 88U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer1Trigger = 89U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer1Trigger = 90U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer1Trigger = 91U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer1Trigger = 92U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer1Trigger = 94U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer1Trigger = 95U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer1Trigger = 96U + (TIMER1TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer1Trigger = 97U + (TIMER1TRIGIN << PMUX_SHIFT), + + /*!< Timer2 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer2Trigger = 1U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer2Trigger = 2U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer2Trigger = 3U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer2Trigger = 4U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer2Trigger = 5U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer2Trigger = 6U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer2Trigger = 7U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer2Trigger = 8U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer2Trigger = 9U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer2Trigger = 10U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer2Trigger = 11U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer2Trigger = 12U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer2Trigger = 13U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer2Trigger = 14U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer2Trigger = 15U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer2Trigger = 16U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer2Trigger = 17U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer2Trigger = 18U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer2Trigger = 19U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer2Trigger = 20U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer2Trigger = 21U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer2Trigger = 22U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer2Trigger = 23U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer2Trigger = 24U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer2Trigger = 25U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer2Trigger = 26U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer2Trigger = 27U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer2Trigger = 28U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer2Trigger = 29U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer2Trigger = 30U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer2Trigger = 31U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToTimer2Trigger = 33U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToTimer2Trigger = 34U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToTimer2Trigger = 35U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToTimer2Trigger = 36U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToTimer2Trigger = 37U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToTimer2Trigger = 38U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer2Trigger = 39U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer2Trigger = 40U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer2Trigger = 41U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer2Trigger = 42U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer2Trigger = 43U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer2Trigger = 44U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer2Trigger = 45U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer2Trigger = 46U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer2Trigger = 48U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer2Trigger = 49U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer2Trigger = 52U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer2Trigger = 53U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer2Trigger = 54U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer2Trigger = 55U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer2Trigger = 56U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer2Trigger = 57U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer2Trigger = 58U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer2Trigger = 59U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer2Trigger = 60U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer2Trigger = 61U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer2Trigger = 62U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer2Trigger = 63U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer2Trigger = 64U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer2Trigger = 65U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer2Trigger = 66U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer2Trigger = 67U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer2Trigger = 68U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer2Trigger = 69U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer2Trigger = 70U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer2Trigger = 71U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer2Trigger = 72U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer2Trigger = 73U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer2Trigger = 74U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer2Trigger = 75U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer2Trigger = 76U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer2Trigger = 77U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer2Trigger = 78U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToTimer2Trigger = 79U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToTimer2Trigger = 80U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToTimer2Trigger = 81U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToTimer2Trigger = 82U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToTimer2Trigger = 83U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToTimer2Trigger = 84U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer2Trigger = 85U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer2Trigger = 86U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer2Trigger = 87U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer2Trigger = 88U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer2Trigger = 89U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer2Trigger = 90U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer2Trigger = 91U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer2Trigger = 92U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer2Trigger = 94U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer2Trigger = 95U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer2Trigger = 96U + (TIMER2TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer2Trigger = 97U + (TIMER2TRIGIN << PMUX_SHIFT), + + /*!< Timer3 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer3Trigger = 1U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer3Trigger = 2U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer3Trigger = 3U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer3Trigger = 4U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer3Trigger = 5U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer3Trigger = 6U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer3Trigger = 7U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer3Trigger = 8U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer3Trigger = 9U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer3Trigger = 10U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer3Trigger = 11U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer3Trigger = 12U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer3Trigger = 13U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer3Trigger = 14U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer3Trigger = 15U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer3Trigger = 16U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer3Trigger = 17U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer3Trigger = 18U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer3Trigger = 19U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer3Trigger = 20U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer3Trigger = 21U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer3Trigger = 22U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer3Trigger = 23U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer3Trigger = 24U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer3Trigger = 25U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer3Trigger = 26U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer3Trigger = 27U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer3Trigger = 28U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer3Trigger = 29U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer3Trigger = 30U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer3Trigger = 31U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToTimer3Trigger = 33U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToTimer3Trigger = 34U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToTimer3Trigger = 35U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToTimer3Trigger = 36U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToTimer3Trigger = 37U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToTimer3Trigger = 38U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer3Trigger = 39U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer3Trigger = 40U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer3Trigger = 41U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer3Trigger = 42U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer3Trigger = 43U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer3Trigger = 44U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer3Trigger = 45U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer3Trigger = 46U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer3Trigger = 48U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer3Trigger = 49U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer3Trigger = 52U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer3Trigger = 53U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer3Trigger = 54U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer3Trigger = 55U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer3Trigger = 56U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer3Trigger = 57U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer3Trigger = 58U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer3Trigger = 59U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer3Trigger = 60U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer3Trigger = 61U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer3Trigger = 62U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer3Trigger = 63U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer3Trigger = 64U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer3Trigger = 65U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer3Trigger = 66U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer3Trigger = 67U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer3Trigger = 68U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer3Trigger = 69U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer3Trigger = 70U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer3Trigger = 71U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer3Trigger = 72U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer3Trigger = 73U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer3Trigger = 74U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer3Trigger = 75U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer3Trigger = 76U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer3Trigger = 77U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer3Trigger = 78U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToTimer3Trigger = 79U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToTimer3Trigger = 80U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToTimer3Trigger = 81U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToTimer3Trigger = 82U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToTimer3Trigger = 83U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToTimer3Trigger = 84U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer3Trigger = 85U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer3Trigger = 86U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer3Trigger = 87U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer3Trigger = 88U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer3Trigger = 89U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer3Trigger = 90U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer3Trigger = 91U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer3Trigger = 92U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer3Trigger = 94U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer3Trigger = 95U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer3Trigger = 96U + (TIMER3TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer3Trigger = 97U + (TIMER3TRIGIN << PMUX_SHIFT), + + /*!< Timer4 Trigger. */ + kINPUTMUX_CtimerInp0ToTimer4Trigger = 1U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer4Trigger = 2U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer4Trigger = 3U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer4Trigger = 4U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer4Trigger = 5U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer4Trigger = 6U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer4Trigger = 7U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer4Trigger = 8U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer4Trigger = 9U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer4Trigger = 10U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer4Trigger = 11U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer4Trigger = 12U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer4Trigger = 13U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer4Trigger = 14U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer4Trigger = 15U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer4Trigger = 16U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer4Trigger = 17U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer4Trigger = 18U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer4Trigger = 19U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer4Trigger = 20U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Usb0StartOfFrameToTimer4Trigger = 21U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToTimer4Trigger = 22U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToTimer4Trigger = 23U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToTimer4Trigger = 24U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToTimer4Trigger = 25U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToTimer4Trigger = 26U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToTimer4Trigger = 27U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToTimer4Trigger = 28U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToTimer4Trigger = 29U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToTimer4Trigger = 30U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToTimer4Trigger = 31U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToTimer4Trigger = 33U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToTimer4Trigger = 34U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToTimer4Trigger = 35U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToTimer4Trigger = 36U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToTimer4Trigger = 37U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToTimer4Trigger = 38U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToTimer4Trigger = 39U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToTimer4Trigger = 40U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToTimer4Trigger = 41U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToTimer4Trigger = 42U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToTimer4Trigger = 43U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToTimer4Trigger = 44U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToTimer4Trigger = 45U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToTimer4Trigger = 46U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToTimer4Trigger = 48U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToTimer4Trigger = 49U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToTimer4Trigger = 52U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToTimer4Trigger = 53U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToTimer4Trigger = 54U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToTimer4Trigger = 55U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToTimer4Trigger = 56U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToTimer4Trigger = 57U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToTimer4Trigger = 58U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToTimer4Trigger = 59U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToTimer4Trigger = 60U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToTimer4Trigger = 61U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToTimer4Trigger = 62U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToTimer4Trigger = 63U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToTimer4Trigger = 64U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToTimer4Trigger = 65U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToTimer4Trigger = 66U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToTimer4Trigger = 67U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToTimer4Trigger = 68U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToTimer4Trigger = 69U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToTimer4Trigger = 70U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToTimer4Trigger = 71U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToTimer4Trigger = 72U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToTimer4Trigger = 73U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToTimer4Trigger = 74U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToTimer4Trigger = 75U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToTimer4Trigger = 76U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToTimer4Trigger = 77U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToTimer4Trigger = 78U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToTimer4Trigger = 79U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToTimer4Trigger = 80U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToTimer4Trigger = 81U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToTimer4Trigger = 82U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToTimer4Trigger = 83U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToTimer4Trigger = 84U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToTimer4Trigger = 85U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToTimer4Trigger = 86U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToTimer4Trigger = 87U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToTimer4Trigger = 88U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToTimer4Trigger = 89U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToTimer4Trigger = 90U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToTimer4Trigger = 91U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToTimer4Trigger = 92U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToTimer4Trigger = 94U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToTimer4Trigger = 95U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToTimer4Trigger = 96U + (TIMER4TRIGIN << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToTimer4Trigger = 97U + (TIMER4TRIGIN << PMUX_SHIFT), + + /*!< Selection for frequency measurement reference clock. */ + kINPUTMUX_ClkInToFreqmeasRef = 1U + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FroOsc12MToFreqmeasRef = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FroHfDivToFreqmeasRef = 3u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Clk16K1ToFreqmeasRef = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_SlowClkToFreqmeasRef = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeClkIn0ToFreqmeasRef = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeClkIn1ToFreqmeasRef = 8u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFreqmeasRef = 9u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFreqmeasRef = 10u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFreqmeasRef = 11u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFreqmeasRef = 12u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFreqmeasRef = 13u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFreqmeasRef = 14u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFreqmeasRef = 15u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFreqmeasRef = 16u + (FREQMEAS_REF_REG << PMUX_SHIFT), + + /*!< Selection for frequency measurement target clock. */ + kINPUTMUX_ClkInToFreqmeasTar = 1U + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_FroOsc12MToFreqmeasTar = 2u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_FroHfDivToFreqmeasTar = 3u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Clk16K1ToFreqmeasTar = 5u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_SlowClkToFreqmeasTar = 6u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeClkIn0ToFreqmeasTar = 7u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeClkIn1ToFreqmeasTar = 8u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFreqmeasTar = 9u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFreqmeasTar = 10u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFreqmeasTar = 11u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFreqmeasTar = 12u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFreqmeasTar = 13u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFreqmeasTar = 14u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFreqmeasTar = 15u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFreqmeasTar = 16u + (FREQMEAS_TAR_REG << PMUX_SHIFT), + + /*!< Cmp0 Trigger. */ + kINPUTMUX_Aoi0Out0ToCmp0Trigger = 2U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToCmp0Trigger = 3U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToCmp0Trigger = 4U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToCmp0Trigger = 5U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToCmp0Trigger = 6U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToCmp0Trigger = 8U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToCmp0Trigger = 9U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToCmp0Trigger = 10U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToCmp0Trigger = 11U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToCmp0Trigger = 12U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToCmp0Trigger = 13U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToCmp0Trigger = 14U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToCmp0Trigger = 16U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToCmp0Trigger = 17U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToCmp0Trigger = 18U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToCmp0Trigger = 19U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToCmp0Trigger = 20U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToCmp0Trigger = 21U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToCmp0Trigger = 22U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToCmp0Trigger = 25U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToCmp0Trigger = 26U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToCmp0Trigger = 27U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToCmp0Trigger = 28U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToCmp0Trigger = 29U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToCmp0Trigger = 30U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToCmp0Trigger = 31U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToCmp0Trigger = 32U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToCmp0Trigger = 33U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToCmp0Trigger = 34U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToCmp0Trigger = 39U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToCmp0Trigger = 40U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToCmp0Trigger = 41U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToCmp0Trigger = 42U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToCmp0Trigger = 47U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToCmp0Trigger = 48U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToCmp0Trigger = 49U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToCmp0Trigger = 50U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToCmp0Trigger = 51U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToCmp0Trigger = 52U + (CMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToCmp0Trigger = 53U + (CMP0_TRIG_REG << PMUX_SHIFT), + + /*!< Cmp1 Trigger. */ + kINPUTMUX_Aoi0Out0ToCmp1Trigger = 2U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToCmp1Trigger = 3U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToCmp1Trigger = 4U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToCmp1Trigger = 5U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToCmp1Trigger = 6U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToCmp1Trigger = 8U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToCmp1Trigger = 9U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToCmp1Trigger = 10U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToCmp1Trigger = 11U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToCmp1Trigger = 12U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToCmp1Trigger = 13U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToCmp1Trigger = 14U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToCmp1Trigger = 16U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToCmp1Trigger = 17U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToCmp1Trigger = 18U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToCmp1Trigger = 19U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToCmp1Trigger = 20U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToCmp1Trigger = 21U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToCmp1Trigger = 22U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToCmp1Trigger = 25U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToCmp1Trigger = 26U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToCmp1Trigger = 27U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToCmp1Trigger = 28U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToCmp1Trigger = 29U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToCmp1Trigger = 30U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToCmp1Trigger = 31U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToCmp1Trigger = 32U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToCmp1Trigger = 33U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToCmp1Trigger = 34U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToCmp1Trigger = 39U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToCmp1Trigger = 40U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToCmp1Trigger = 41U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToCmp1Trigger = 42U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToCmp1Trigger = 47U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToCmp1Trigger = 48U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToCmp1Trigger = 49U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToCmp1Trigger = 50U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToCmp1Trigger = 51U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToCmp1Trigger = 52U + (CMP1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToCmp1Trigger = 53U + (CMP1_TRIG_REG << PMUX_SHIFT), + + /*!< Adc0 Trigger. */ + kINPUTMUX_ArmTxevToAdc0Trigger = 1U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToAdc0Trigger = 2U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToAdc0Trigger = 3U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToAdc0Trigger = 4U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToAdc0Trigger = 5U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToAdc0Trigger = 6U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToAdc0Trigger = 7U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToAdc0Trigger = 9U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToAdc0Trigger = 10U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToAdc0Trigger = 11U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToAdc0Trigger = 12U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToAdc0Trigger = 13U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToAdc0Trigger = 14U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToAdc0Trigger = 15U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToAdc0Trigger = 17U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToAdc0Trigger = 18U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToAdc0Trigger = 19U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToAdc0Trigger = 20U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToAdc0Trigger = 21U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToAdc0Trigger = 22U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToAdc0Trigger = 23U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToAdc0Trigger = 26U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToAdc0Trigger = 27U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToAdc0Trigger = 28U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToAdc0Trigger = 29U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToAdc0Trigger = 30U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WuuToAdc0Trigger = 31U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToAdc0Trigger = 33U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToAdc0Trigger = 34U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToAdc0Trigger = 35U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToAdc0Trigger = 36U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToAdc0Trigger = 37U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToAdc0Trigger = 38U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToAdc0Trigger = 39U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToAdc0Trigger = 40U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToAdc0Trigger = 41U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToAdc0Trigger = 42U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToAdc0Trigger = 43U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToAdc0Trigger = 44U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToAdc0Trigger = 45U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToAdc0Trigger = 46U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToAdc0Trigger = 47U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToAdc0Trigger = 48U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToAdc0Trigger = 49U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToAdc0Trigger = 50U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToAdc0Trigger = 51U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToAdc0Trigger = 52U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToAdc0Trigger = 53U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToAdc0Trigger = 54U + (ADC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToAdc0Trigger = 55U + (ADC0_TRIG0_REG << PMUX_SHIFT), + + /*!< Adc1 Trigger. */ + kINPUTMUX_ArmTxevToAdc1Trigger = 1U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToAdc1Trigger = 2U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToAdc1Trigger = 3U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToAdc1Trigger = 4U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToAdc1Trigger = 5U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToAdc1Trigger = 6U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToAdc1Trigger = 7U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToAdc1Trigger = 9U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToAdc1Trigger = 10U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToAdc1Trigger = 11U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToAdc1Trigger = 12U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToAdc1Trigger = 13U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToAdc1Trigger = 14U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToAdc1Trigger = 15U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToAdc1Trigger = 17U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToAdc1Trigger = 18U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToAdc1Trigger = 19U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToAdc1Trigger = 20U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToAdc1Trigger = 21U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToAdc1Trigger = 22U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToAdc1Trigger = 23U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToAdc1Trigger = 26U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToAdc1Trigger = 27U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToAdc1Trigger = 28U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToAdc1Trigger = 29U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToAdc1Trigger = 30U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WuuToAdc1Trigger = 31U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToAdc1Trigger = 33U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToAdc1Trigger = 34U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToAdc1Trigger = 35U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToAdc1Trigger = 36U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToAdc1Trigger = 37U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToAdc1Trigger = 38U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToAdc1Trigger = 39U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToAdc1Trigger = 40U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToAdc1Trigger = 41U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToAdc1Trigger = 42U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToAdc1Trigger = 43U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToAdc1Trigger = 44U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToAdc1Trigger = 45U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToAdc1Trigger = 46U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToAdc1Trigger = 47U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToAdc1Trigger = 48U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToAdc1Trigger = 49U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToAdc1Trigger = 50U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToAdc1Trigger = 51U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToAdc1Trigger = 52U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToAdc1Trigger = 53U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToAdc1Trigger = 54U + (ADC1_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToAdc1Trigger = 55U + (ADC1_TRIG0_REG << PMUX_SHIFT), + + /*!< Dac0 Trigger. */ + kINPUTMUX_ArmTxevToDac0Trigger = 1U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToDac0Trigger = 2U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToDac0Trigger = 3U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToDac0Trigger = 4U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToDac0Trigger = 5U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToDac0Trigger = 6U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToDac0Trigger = 7U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToDac0Trigger = 9U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToDac0Trigger = 10U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToDac0Trigger = 11U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToDac0Trigger = 12U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToDac0Trigger = 13U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToDac0Trigger = 14U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToDac0Trigger = 15U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToDac0Trigger = 18U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToDac0Trigger = 19U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToDac0Trigger = 20U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToDac0Trigger = 21U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToDac0Trigger = 22U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToDac0Trigger = 23U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToDac0Trigger = 26U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToDac0Trigger = 27U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToDac0Trigger = 28U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToDac0Trigger = 29U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToDac0Trigger = 30U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WuuToDac0Trigger = 31U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToDac0Trigger = 33U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToDac0Trigger = 34U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToDac0Trigger = 35U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToDac0Trigger = 36U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToDac0Trigger = 37U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToDac0Trigger = 38U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToDac0Trigger = 39U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToDac0Trigger = 40U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToDac0Trigger = 41U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToDac0Trigger = 42U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToDac0Trigger = 43U + (DAC0_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToDac0Trigger = 44U + (DAC0_TRIG0_REG << PMUX_SHIFT), + + /*!< Qdc0 Trigger. */ + kINPUTMUX_ArmTxevToQdc0Trigger = 1U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc0Trigger = 2U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc0Trigger = 3U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc0Trigger = 4U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc0Trigger = 5U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Trigger = 6U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Trigger = 7U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc0Trigger = 9U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Trigger = 10U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc0Trigger = 11U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Trigger = 12U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc0Trigger = 13U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Trigger = 14U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Trigger = 16U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Trigger = 17U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Trigger = 18U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Trigger = 19U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Trigger = 20U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Trigger = 21U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Trigger = 24U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Trigger = 25U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Trigger = 26U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Trigger = 27U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Trigger = 28U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Trigger = 29U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Trigger = 30U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Trigger = 31U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Trigger = 32U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Trigger = 33U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc0Trigger = 34U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc0Trigger = 35U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc0Trigger = 36U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc0Trigger = 37U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc0Trigger = 38U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc0Trigger = 39U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc0Trigger = 40U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc0Trigger = 41U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc0Trigger = 42U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc0Trigger = 43U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc0Trigger = 44U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc0Trigger = 49U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc0Trigger = 50U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc0Trigger = 51U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc0Trigger = 52U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Trigger = 62U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Trigger = 63U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Trigger = 64U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Trigger = 65U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Trigger = 66U + (QDC0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Trigger = 67U + (QDC0_TRIG_REG << PMUX_SHIFT), + + /*!< Qdc0 Home. */ + kINPUTMUX_ArmTxevToQdc0Home = 1U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc0Home = 2U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc0Home = 3U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc0Home = 4U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc0Home = 5U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Home = 6U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Home = 7U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc0Home = 9U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Home = 10U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc0Home = 11U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Home = 12U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc0Home = 13U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Home = 14U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Home = 16U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Home = 17U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Home = 18U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Home = 19U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Home = 20U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Home = 21U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Home = 24U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Home = 25U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Home = 26U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Home = 27U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Home = 28U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Home = 29U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Home = 30U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Home = 31U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Home = 32U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Home = 33U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc0Home = 34U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc0Home = 35U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc0Home = 36U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc0Home = 37U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc0Home = 38U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc0Home = 39U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc0Home = 40U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc0Home = 41U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc0Home = 42U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc0Home = 43U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc0Home = 44U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc0Home = 49U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc0Home = 50U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc0Home = 51U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc0Home = 52U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Home = 62U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Home = 63U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Home = 64U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Home = 65U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Home = 66U + (QDC0_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Home = 67U + (QDC0_HOME_REG << PMUX_SHIFT), + + /*!< Qdc0 Index. */ + kINPUTMUX_ArmTxevToQdc0Index = 1U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc0Index = 2U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc0Index = 3U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc0Index = 4U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc0Index = 5U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Index = 6U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Index = 7U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc0Index = 9U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Index = 10U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc0Index = 11U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Index = 12U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc0Index = 13U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Index = 14U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Index = 16U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Index = 17U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Index = 18U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Index = 19U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Index = 20U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Index = 21U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Index = 24U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Index = 25U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Index = 26U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Index = 27U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Index = 28U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Index = 29U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Index = 30U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Index = 31U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Index = 32U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Index = 33U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc0Index = 34U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc0Index = 35U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc0Index = 36U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc0Index = 37U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc0Index = 38U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc0Index = 39U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc0Index = 40U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc0Index = 41U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc0Index = 42U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc0Index = 43U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc0Index = 44U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc0Index = 49U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc0Index = 50U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc0Index = 51U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc0Index = 52U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Index = 62U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Index = 63U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Index = 64U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Index = 65U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Index = 66U + (QDC0_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Index = 67U + (QDC0_INDEX_REG << PMUX_SHIFT), + + /*!< Qdc0 Phaseb. */ + kINPUTMUX_ArmTxevToQdc0Phaseb = 1U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc0Phaseb = 2U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc0Phaseb = 3U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc0Phaseb = 4U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc0Phaseb = 5U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Phaseb = 6U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Phaseb = 7U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc0Phaseb = 9U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Phaseb = 10U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc0Phaseb = 11U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Phaseb = 12U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc0Phaseb = 13U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Phaseb = 14U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Phaseb = 16U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Phaseb = 17U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Phaseb = 18U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Phaseb = 19U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Phaseb = 20U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Phaseb = 21U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Phaseb = 24U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Phaseb = 25U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Phaseb = 26U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Phaseb = 27U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Phaseb = 28U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Phaseb = 29U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Phaseb = 30U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Phaseb = 31U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Phaseb = 32U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Phaseb = 33U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc0Phaseb = 34U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc0Phaseb = 35U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc0Phaseb = 36U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc0Phaseb = 37U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc0Phaseb = 38U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc0Phaseb = 39U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc0Phaseb = 40U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc0Phaseb = 41U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc0Phaseb = 42U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc0Phaseb = 43U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc0Phaseb = 44U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc0Phaseb = 49U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc0Phaseb = 50U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc0Phaseb = 51U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc0Phaseb = 52U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Phaseb = 62U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Phaseb = 63U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Phaseb = 64U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Phaseb = 65U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Phaseb = 66U + (QDC0_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Phaseb = 67U + (QDC0_PHASEB_REG << PMUX_SHIFT), + + /*!< Qdc0 Phasea. */ + kINPUTMUX_ArmTxevToQdc0Phasea = 1U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc0Phasea = 2U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc0Phasea = 3U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc0Phasea = 4U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc0Phasea = 5U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Phasea = 6U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Phasea = 7U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc0Phasea = 9U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Phasea = 10U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc0Phasea = 11U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Phasea = 12U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc0Phasea = 13U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Phasea = 14U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Phasea = 16U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Phasea = 17U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Phasea = 18U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Phasea = 19U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Phasea = 20U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Phasea = 21U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Phasea = 24U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Phasea = 25U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Phasea = 26U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Phasea = 27U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Phasea = 28U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Phasea = 29U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Phasea = 30U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Phasea = 31U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Phasea = 32U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Phasea = 33U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc0Phasea = 34U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc0Phasea = 35U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc0Phasea = 36U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc0Phasea = 37U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc0Phasea = 38U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc0Phasea = 39U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc0Phasea = 40U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc0Phasea = 41U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc0Phasea = 42U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc0Phasea = 43U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc0Phasea = 44U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc0Phasea = 49U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc0Phasea = 50U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc0Phasea = 51U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc0Phasea = 52U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Phasea = 62U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Phasea = 63U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Phasea = 64U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Phasea = 65U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Phasea = 66U + (QDC0_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Phasea = 67U + (QDC0_PHASEA_REG << PMUX_SHIFT), + + /*!< Qdc0 Icap1. */ + kINPUTMUX_ArmTxevToQdc0Icap1 = 1U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc0Icap1 = 2U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc0Icap1 = 3U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc0Icap1 = 4U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc0Icap1 = 5U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc0Icap1 = 6U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc0Icap1 = 7U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc0Icap1 = 9U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc0Icap1 = 10U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc0Icap1 = 11U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc0Icap1 = 12U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc0Icap1 = 13U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc0Icap1 = 14U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc0Icap1 = 16U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc0Icap1 = 17U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc0Icap1 = 18U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc0Icap1 = 19U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc0Icap1 = 20U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc0Icap1 = 21U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc0Icap1 = 24U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc0Icap1 = 25U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc0Icap1 = 26U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc0Icap1 = 27U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc0Icap1 = 28U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc0Icap1 = 29U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc0Icap1 = 30U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc0Icap1 = 31U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc0Icap1 = 32U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc0Icap1 = 33U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc0Icap1 = 34U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc0Icap1 = 35U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc0Icap1 = 36U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc0Icap1 = 37U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc0Icap1 = 38U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc0Icap1 = 39U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc0Icap1 = 40U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc0Icap1 = 41U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc0Icap1 = 42U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc0Icap1 = 43U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc0Icap1 = 44U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc0Icap1 = 49U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc0Icap1 = 50U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc0Icap1 = 51U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc0Icap1 = 52U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc0Icap1 = 62U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc0Icap1 = 63U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc0Icap1 = 64U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc0Icap1 = 65U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc0Icap1 = 66U + (QDC0_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc0Icap1 = 67U + (QDC0_ICAP1_REG << PMUX_SHIFT), + + /*!< Qdc1 Trigger. */ + kINPUTMUX_ArmTxevToQdc1Trigger = 1U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc1Trigger = 2U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc1Trigger = 3U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc1Trigger = 4U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc1Trigger = 5U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Trigger = 6U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Trigger = 7U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc1Trigger = 9U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Trigger = 10U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc1Trigger = 11U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Trigger = 12U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc1Trigger = 13U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Trigger = 14U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Trigger = 16U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Trigger = 17U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Trigger = 18U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Trigger = 19U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Trigger = 20U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Trigger = 21U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Trigger = 24U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Trigger = 25U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Trigger = 26U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Trigger = 27U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Trigger = 28U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Trigger = 29U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Trigger = 30U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Trigger = 31U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Trigger = 32U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Trigger = 33U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc1Trigger = 34U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc1Trigger = 35U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc1Trigger = 36U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc1Trigger = 37U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc1Trigger = 38U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc1Trigger = 39U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc1Trigger = 40U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc1Trigger = 41U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc1Trigger = 42U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc1Trigger = 43U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc1Trigger = 44U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc1Trigger = 49U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc1Trigger = 50U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc1Trigger = 51U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc1Trigger = 52U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Trigger = 62U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Trigger = 63U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Trigger = 64U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Trigger = 65U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Trigger = 66U + (QDC1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Trigger = 67U + (QDC1_TRIG_REG << PMUX_SHIFT), + + /*!< Qdc1 Home. */ + kINPUTMUX_ArmTxevToQdc1Home = 1U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc1Home = 2U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc1Home = 3U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc1Home = 4U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc1Home = 5U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Home = 6U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Home = 7U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc1Home = 9U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Home = 10U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc1Home = 11U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Home = 12U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc1Home = 13U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Home = 14U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Home = 16U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Home = 17U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Home = 18U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Home = 19U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Home = 20U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Home = 21U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Home = 24U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Home = 25U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Home = 26U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Home = 27U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Home = 28U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Home = 29U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Home = 30U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Home = 31U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Home = 32U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Home = 33U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc1Home = 34U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc1Home = 35U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc1Home = 36U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc1Home = 37U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc1Home = 38U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc1Home = 39U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc1Home = 40U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc1Home = 41U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc1Home = 42U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc1Home = 43U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc1Home = 44U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc1Home = 49U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc1Home = 50U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc1Home = 51U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc1Home = 52U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Home = 62U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Home = 63U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Home = 64U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Home = 65U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Home = 66U + (QDC1_HOME_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Home = 67U + (QDC1_HOME_REG << PMUX_SHIFT), + + /*!< Qdc1 Index. */ + kINPUTMUX_ArmTxevToQdc1Index = 1U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc1Index = 2U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc1Index = 3U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc1Index = 4U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc1Index = 5U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Index = 6U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Index = 7U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc1Index = 9U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Index = 10U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc1Index = 11U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Index = 12U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc1Index = 13U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Index = 14U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Index = 16U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Index = 17U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Index = 18U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Index = 19U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Index = 20U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Index = 21U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Index = 24U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Index = 25U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Index = 26U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Index = 27U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Index = 28U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Index = 29U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Index = 30U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Index = 31U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Index = 32U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Index = 33U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc1Index = 34U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc1Index = 35U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc1Index = 36U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc1Index = 37U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc1Index = 38U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc1Index = 39U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc1Index = 40U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc1Index = 41U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc1Index = 42U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc1Index = 43U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc1Index = 44U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc1Index = 49U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc1Index = 50U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc1Index = 51U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc1Index = 52U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Index = 62U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Index = 63U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Index = 64U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Index = 65U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Index = 66U + (QDC1_INDEX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Index = 67U + (QDC1_INDEX_REG << PMUX_SHIFT), + + /*!< Qdc1 Phaseb. */ + kINPUTMUX_ArmTxevToQdc1Phaseb = 1U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc1Phaseb = 2U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc1Phaseb = 3U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc1Phaseb = 4U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc1Phaseb = 5U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Phaseb = 6U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Phaseb = 7U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc1Phaseb = 9U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Phaseb = 10U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc1Phaseb = 11U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Phaseb = 12U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc1Phaseb = 13U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Phaseb = 14U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Phaseb = 16U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Phaseb = 17U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Phaseb = 18U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Phaseb = 19U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Phaseb = 20U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Phaseb = 21U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Phaseb = 24U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Phaseb = 25U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Phaseb = 26U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Phaseb = 27U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Phaseb = 28U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Phaseb = 29U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Phaseb = 30U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Phaseb = 31U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Phaseb = 32U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Phaseb = 33U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc1Phaseb = 34U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc1Phaseb = 35U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc1Phaseb = 36U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc1Phaseb = 37U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc1Phaseb = 38U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc1Phaseb = 39U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc1Phaseb = 40U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc1Phaseb = 41U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc1Phaseb = 42U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc1Phaseb = 43U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc1Phaseb = 44U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc1Phaseb = 49U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc1Phaseb = 50U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc1Phaseb = 51U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc1Phaseb = 52U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Phaseb = 62U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Phaseb = 63U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Phaseb = 64U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Phaseb = 65U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Phaseb = 66U + (QDC1_PHASEB_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Phaseb = 67U + (QDC1_PHASEB_REG << PMUX_SHIFT), + + /*!< Qdc1 Phasea. */ + kINPUTMUX_ArmTxevToQdc1Phasea = 1U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc1Phasea = 2U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc1Phasea = 3U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc1Phasea = 4U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc1Phasea = 5U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Phasea = 6U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Phasea = 7U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc1Phasea = 9U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Phasea = 10U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc1Phasea = 11U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Phasea = 12U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc1Phasea = 13U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Phasea = 14U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Phasea = 16U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Phasea = 17U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Phasea = 18U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Phasea = 19U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Phasea = 20U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Phasea = 21U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Phasea = 24U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Phasea = 25U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Phasea = 26U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Phasea = 27U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Phasea = 28U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Phasea = 29U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Phasea = 30U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Phasea = 31U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Phasea = 32U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Phasea = 33U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc1Phasea = 34U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc1Phasea = 35U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc1Phasea = 36U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc1Phasea = 37U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc1Phasea = 38U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc1Phasea = 39U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc1Phasea = 40U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc1Phasea = 41U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc1Phasea = 42U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc1Phasea = 43U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc1Phasea = 44U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc1Phasea = 49U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc1Phasea = 50U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc1Phasea = 51U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc1Phasea = 52U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Phasea = 62U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Phasea = 63U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Phasea = 64U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Phasea = 65U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Phasea = 66U + (QDC1_PHASEA_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Phasea = 67U + (QDC1_PHASEA_REG << PMUX_SHIFT), + + /*!< Qdc1 Icap1. */ + kINPUTMUX_ArmTxevToQdc1Icap1 = 1U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToQdc1Icap1 = 2U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToQdc1Icap1 = 3U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToQdc1Icap1 = 4U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToQdc1Icap1 = 5U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToQdc1Icap1 = 6U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToQdc1Icap1 = 7U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToQdc1Icap1 = 9U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToQdc1Icap1 = 10U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToQdc1Icap1 = 11U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToQdc1Icap1 = 12U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToQdc1Icap1 = 13U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToQdc1Icap1 = 14U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToQdc1Icap1 = 16U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToQdc1Icap1 = 17U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToQdc1Icap1 = 18U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToQdc1Icap1 = 19U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToQdc1Icap1 = 20U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToQdc1Icap1 = 21U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToQdc1Icap1 = 24U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToQdc1Icap1 = 25U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToQdc1Icap1 = 26U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToQdc1Icap1 = 27U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToQdc1Icap1 = 28U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToQdc1Icap1 = 29U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToQdc1Icap1 = 30U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToQdc1Icap1 = 31U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToQdc1Icap1 = 32U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToQdc1Icap1 = 33U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToQdc1Icap1 = 34U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToQdc1Icap1 = 35U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToQdc1Icap1 = 36U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToQdc1Icap1 = 37U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToQdc1Icap1 = 38U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToQdc1Icap1 = 39U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToQdc1Icap1 = 40U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToQdc1Icap1 = 41U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToQdc1Icap1 = 42U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToQdc1Icap1 = 43U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToQdc1Icap1 = 44U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToQdc1Icap1 = 49U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToQdc1Icap1 = 50U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToQdc1Icap1 = 51U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToQdc1Icap1 = 52U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToQdc1Icap1 = 62U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToQdc1Icap1 = 63U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToQdc1Icap1 = 64U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToQdc1Icap1 = 65U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToQdc1Icap1 = 66U + (QDC1_ICAP1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToQdc1Icap1 = 67U + (QDC1_ICAP1_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM0_EXTA0 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Sm0Exta0 = 1U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Sm0Exta0 = 2U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Sm0Exta0 = 3U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Sm0Exta0 = 4U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Sm0Exta0 = 5U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm0Exta0 = 6U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm0Exta0 = 7U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Sm0Exta0 = 9U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm0Exta0 = 10U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Sm0Exta0 = 11U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm0Exta0 = 12U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Sm0Exta0 = 13U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm0Exta0 = 14U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm0Exta0 = 15U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm0Exta0 = 16U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm0Exta0 = 17U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm0Exta0 = 18U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm0Exta0 = 19U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm0Exta0 = 20U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm0Exta0 = 21U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm0Exta0 = 22U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm0Exta0 = 23U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm0Exta0 = 24U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm0Exta0 = 25U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm0Exta0 = 26U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm0Exta0 = 27U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm0Exta0 = 28U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm0Exta0 = 29U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Sm0Exta0 = 30U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Sm0Exta0 = 31U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm0Exta0 = 32U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm0Exta0 = 33U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm0Exta0 = 34U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm0Exta0 = 35U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm0Exta0 = 36U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Sm0Exta0 = 37U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Sm0Exta0 = 38U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Sm0Exta0 = 39U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Sm0Exta0 = 40U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Sm0Exta0 = 45U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Sm0Exta0 = 46U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Sm0Exta0 = 47U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Sm0Exta0 = 48U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm0Exta0 = 49U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm0Exta0 = 50U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm0Exta0 = 51U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm0Exta0 = 52U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm0Exta0 = 53U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm0Exta0 = 54U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm0Exta0 = 55U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm0Exta0 = 56U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm0Exta0 = 57U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm0Exta0 = 58U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm0Exta0 = 59U + (FlexPWM0_SM0_EXTA0_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM1_EXTA1 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Sm1Exta1 = 1U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Sm1Exta1 = 2U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Sm1Exta1 = 3U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Sm1Exta1 = 4U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Sm1Exta1 = 5U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm1Exta1 = 6U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm1Exta1 = 7U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Sm1Exta1 = 9U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm1Exta1 = 10U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Sm1Exta1 = 11U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm1Exta1 = 12U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Sm1Exta1 = 13U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm1Exta1 = 14U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm1Exta1 = 15U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm1Exta1 = 16U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm1Exta1 = 17U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm1Exta1 = 18U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm1Exta1 = 19U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm1Exta1 = 20U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm1Exta1 = 21U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm1Exta1 = 22U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm1Exta1 = 23U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm1Exta1 = 24U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm1Exta1 = 25U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm1Exta1 = 26U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm1Exta1 = 27U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm1Exta1 = 28U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm1Exta1 = 29U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Sm1Exta1 = 30U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Sm1Exta1 = 31U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm1Exta1 = 32U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm1Exta1 = 33U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm1Exta1 = 34U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm1Exta1 = 35U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm1Exta1 = 36U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Sm1Exta1 = 37U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Sm1Exta1 = 38U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Sm1Exta1 = 39U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Sm1Exta1 = 40U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Sm1Exta1 = 45U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Sm1Exta1 = 46U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Sm1Exta1 = 47U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Sm1Exta1 = 48U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm1Exta1 = 49U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm1Exta1 = 50U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm1Exta1 = 51U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm1Exta1 = 52U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm1Exta1 = 53U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm1Exta1 = 54U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm1Exta1 = 55U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm1Exta1 = 56U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm1Exta1 = 57U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm1Exta1 = 58U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm1Exta1 = 59U + (FlexPWM0_SM1_EXTA1_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM2_EXTA2 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Sm2Exta2 = 1U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Sm2Exta2 = 2U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Sm2Exta2 = 3U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Sm2Exta2 = 4U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Sm2Exta2 = 5U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm2Exta2 = 6U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm2Exta2 = 7U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Sm2Exta2 = 9U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm2Exta2 = 10U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Sm2Exta2 = 11U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm2Exta2 = 12U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Sm2Exta2 = 13U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm2Exta2 = 14U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm2Exta2 = 15U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm2Exta2 = 16U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm2Exta2 = 17U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm2Exta2 = 18U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm2Exta2 = 19U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm2Exta2 = 20U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm2Exta2 = 21U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm2Exta2 = 22U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm2Exta2 = 23U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm2Exta2 = 24U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm2Exta2 = 25U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm2Exta2 = 26U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm2Exta2 = 27U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm2Exta2 = 28U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm2Exta2 = 29U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Sm2Exta2 = 30U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Sm2Exta2 = 31U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm2Exta2 = 32U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm2Exta2 = 33U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm2Exta2 = 34U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm2Exta2 = 35U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm2Exta2 = 36U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Sm2Exta2 = 37U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Sm2Exta2 = 38U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Sm2Exta2 = 39U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Sm2Exta2 = 40U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Sm2Exta2 = 45U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Sm2Exta2 = 46U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Sm2Exta2 = 47U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Sm2Exta2 = 48U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm2Exta2 = 49U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm2Exta2 = 50U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm2Exta2 = 51U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm2Exta2 = 52U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm2Exta2 = 53U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm2Exta2 = 54U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm2Exta2 = 55U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm2Exta2 = 56U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm2Exta2 = 57U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm2Exta2 = 58U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm2Exta2 = 59U + (FlexPWM0_SM2_EXTA2_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM0_EXTSYNC0 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Sm0Extsync0 = 1U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Sm0Extsync0 = 2U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Sm0Extsync0 = 3U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Sm0Extsync0 = 4U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Sm0Extsync0 = 5U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm0Extsync0 = 6U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm0Extsync0 = 7U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Sm0Extsync0 = 9U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm0Extsync0 = 10U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Sm0Extsync0 = 11U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm0Extsync0 = 12U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Sm0Extsync0 = 13U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm0Extsync0 = 14U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm0Extsync0 = 15U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm0Extsync0 = 16U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm0Extsync0 = 17U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm0Extsync0 = 18U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm0Extsync0 = 19U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm0Extsync0 = 20U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm0Extsync0 = 21U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm0Extsync0 = 22U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm0Extsync0 = 23U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm0Extsync0 = 24U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm0Extsync0 = 25U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm0Extsync0 = 26U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm0Extsync0 = 27U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm0Extsync0 = 28U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm0Extsync0 = 29U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Sm0Extsync0 = 30U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Sm0Extsync0 = 31U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm0Extsync0 = 32U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm0Extsync0 = 33U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm0Extsync0 = 34U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm0Extsync0 = 35U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm0Extsync0 = 36U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Sm0Extsync0 = 37U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Sm0Extsync0 = 38U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Sm0Extsync0 = 39U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Sm0Extsync0 = 40U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Sm0Extsync0 = 45U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Sm0Extsync0 = 46U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Sm0Extsync0 = 47U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Sm0Extsync0 = 48U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm0Extsync0 = 49U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm0Extsync0 = 50U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm0Extsync0 = 51U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm0Extsync0 = 52U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm0Extsync0 = 53U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm0Extsync0 = 54U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm0Extsync0 = 55U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm0Extsync0 = 56U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm0Extsync0 = 57U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm0Extsync0 = 58U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm0Extsync0 = 59U + (FlexPWM0_SM0_EXTSYNC0_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM1_EXTSYNC1 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Sm1Extsync1 = 1U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Sm1Extsync1 = 2U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Sm1Extsync1 = 3U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Sm1Extsync1 = 4U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Sm1Extsync1 = 5U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm1Extsync1 = 6U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm1Extsync1 = 7U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Sm1Extsync1 = 9U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm1Extsync1 = 10U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Sm1Extsync1 = 11U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm1Extsync1 = 12U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Sm1Extsync1 = 13U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm1Extsync1 = 14U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm1Extsync1 = 15U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm1Extsync1 = 16U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm1Extsync1 = 17U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm1Extsync1 = 18U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm1Extsync1 = 19U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm1Extsync1 = 20U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm1Extsync1 = 21U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm1Extsync1 = 22U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm1Extsync1 = 23U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm1Extsync1 = 24U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm1Extsync1 = 25U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm1Extsync1 = 26U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm1Extsync1 = 27U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm1Extsync1 = 28U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm1Extsync1 = 29U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Sm1Extsync1 = 30U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Sm1Extsync1 = 31U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm1Extsync1 = 32U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm1Extsync1 = 33U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm1Extsync1 = 34U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm1Extsync1 = 35U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm1Extsync1 = 36U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Sm1Extsync1 = 37U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Sm1Extsync1 = 38U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Sm1Extsync1 = 39U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Sm1Extsync1 = 40U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Sm1Extsync1 = 45U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Sm1Extsync1 = 46U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Sm1Extsync1 = 47U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Sm1Extsync1 = 48U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm1Extsync1 = 49U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm1Extsync1 = 50U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm1Extsync1 = 51U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm1Extsync1 = 52U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm1Extsync1 = 53U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm1Extsync1 = 54U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm1Extsync1 = 55U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm1Extsync1 = 56U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm1Extsync1 = 57U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm1Extsync1 = 58U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm1Extsync1 = 59U + (FlexPWM0_SM1_EXTSYNC1_REG << PMUX_SHIFT), + + /*!< FlexPWM0_SM2_EXTSYNC2 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Sm2Extsync2 = 1U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Sm2Extsync2 = 2U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Sm2Extsync2 = 3U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Sm2Extsync2 = 4U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Sm2Extsync2 = 5U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Sm2Extsync2 = 6U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Sm2Extsync2 = 7U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Sm2Extsync2 = 9U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Sm2Extsync2 = 10U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Sm2Extsync2 = 11U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Sm2Extsync2 = 12U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Sm2Extsync2 = 13U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Sm2Extsync2 = 14U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Sm2Extsync2 = 15U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Sm2Extsync2 = 16U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Sm2Extsync2 = 17U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Sm2Extsync2 = 18U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Sm2Extsync2 = 19U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Sm2Extsync2 = 20U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Sm2Extsync2 = 21U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Sm2Extsync2 = 22U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Sm2Extsync2 = 23U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Sm2Extsync2 = 24U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Sm2Extsync2 = 25U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Sm2Extsync2 = 26U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Sm2Extsync2 = 27U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Sm2Extsync2 = 28U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Sm2Extsync2 = 29U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Sm2Extsync2 = 30U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Sm2Extsync2 = 31U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Sm2Extsync2 = 32U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Sm2Extsync2 = 33U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Sm2Extsync2 = 34U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Sm2Extsync2 = 35U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Sm2Extsync2 = 36U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Sm2Extsync2 = 37U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Sm2Extsync2 = 38U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Sm2Extsync2 = 39U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Sm2Extsync2 = 40U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Sm2Extsync2 = 45U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Sm2Extsync2 = 46U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Sm2Extsync2 = 47U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Sm2Extsync2 = 48U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Sm2Extsync2 = 49U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Sm2Extsync2 = 50U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Sm2Extsync2 = 51U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Sm2Extsync2 = 52U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Sm2Extsync2 = 53U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Sm2Extsync2 = 54U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Sm2Extsync2 = 55U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Sm2Extsync2 = 56U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Sm2Extsync2 = 57U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Sm2Extsync2 = 58U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Sm2Extsync2 = 59U + (FlexPWM0_SM2_EXTSYNC2_REG << PMUX_SHIFT), + + /*!< FlexPWM0_FAULT input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Fault = 1U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Fault = 2U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Fault = 3U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Fault = 4U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Fault = 5U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Fault = 6U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Fault = 7U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Fault = 9U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Fault = 10U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Fault = 11U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Fault = 12U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Fault = 13U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Fault = 14U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Fault = 15U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Fault = 16U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Fault = 17U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Fault = 18U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Fault = 19U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Fault = 20U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Fault = 21U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Fault = 22U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Fault = 23U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Fault = 24U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Fault = 25U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Fault = 26U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Fault = 27U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Fault = 28U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Fault = 29U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Fault = 30U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Fault = 31U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Fault = 32U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Fault = 33U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Fault = 34U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Fault = 35U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Fault = 36U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Fault = 37U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Fault = 38U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Fault = 39U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Fault = 40U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Fault = 45U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Fault = 46U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Fault = 47U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Fault = 48U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Fault = 49U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Fault = 50U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Fault = 51U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Fault = 52U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Fault = 53U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Fault = 54U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Fault = 55U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Fault = 56U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Fault = 57U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Fault = 58U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Fault = 59U + (FlexPWM0_FAULT_REG << PMUX_SHIFT), + + /*!< FlexPWM0_FORCE input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm0Force = 1U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm0Force = 2U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm0Force = 3U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm0Force = 4U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm0Force = 5U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm0Force = 6U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm0Force = 7U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm0Force = 9U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm0Force = 10U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm0Force = 11U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm0Force = 12U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm0Force = 13U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm0Force = 14U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm0Force = 15U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm0Force = 16U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm0Force = 17U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm0Force = 18U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm0Force = 19U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm0Force = 20U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm0Force = 21U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm0Force = 22U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm0Force = 23U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm0Force = 24U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm0Force = 25U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm0Force = 26U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm0Force = 27U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm0Force = 28U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm0Force = 29U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm0Force = 30U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm0Force = 31U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm0Force = 32U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm0Force = 33U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm0Force = 34U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm0Force = 35U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm0Force = 36U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm0Force = 37U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm0Force = 38U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm0Force = 39U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm0Force = 40U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm0Force = 45U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm0Force = 46U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm0Force = 47U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm0Force = 48U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm0Force = 49U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm0Force = 50U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm0Force = 51U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm0Force = 52U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm0Force = 53U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexPwm0Force = 54U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToFlexPwm0Force = 55U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexPwm0Force = 56U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToFlexPwm0Force = 57U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexPwm0Force = 58U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToFlexPwm0Force = 59U + (FlexPWM0_FORCE_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM0_EXTA0 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Sm0Exta0 = 1U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Sm0Exta0 = 2U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Sm0Exta0 = 3U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Sm0Exta0 = 4U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Sm0Exta0 = 5U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm0Exta0 = 6U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm0Exta0 = 7U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Sm0Exta0 = 9U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm0Exta0 = 10U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Sm0Exta0 = 11U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm0Exta0 = 12U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Sm0Exta0 = 13U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm0Exta0 = 14U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm0Exta0 = 15U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm0Exta0 = 16U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm0Exta0 = 17U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm0Exta0 = 18U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm0Exta0 = 19U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm0Exta0 = 20U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm0Exta0 = 21U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm0Exta0 = 22U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm0Exta0 = 23U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm0Exta0 = 24U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm0Exta0 = 25U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm0Exta0 = 26U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm0Exta0 = 27U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm0Exta0 = 28U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm0Exta0 = 29U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Sm0Exta0 = 30U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Sm0Exta0 = 31U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm0Exta0 = 32U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm0Exta0 = 33U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm0Exta0 = 34U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm0Exta0 = 35U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm0Exta0 = 36U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Sm0Exta0 = 37U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Sm0Exta0 = 38U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Sm0Exta0 = 39U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Sm0Exta0 = 40U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Sm0Exta0 = 45U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Sm0Exta0 = 46U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Sm0Exta0 = 47U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Sm0Exta0 = 48U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm0Exta0 = 49U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm0Exta0 = 50U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm0Exta0 = 51U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm0Exta0 = 52U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm0Exta0 = 53U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm0Exta0 = 54U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm0Exta0 = 55U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm0Exta0 = 56U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm0Exta0 = 57U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm0Exta0 = 58U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm0Exta0 = 59U + (FlexPWM1_SM0_EXTA0_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM1_EXTA1 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Sm1Exta1 = 1U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Sm1Exta1 = 2U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Sm1Exta1 = 3U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Sm1Exta1 = 4U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Sm1Exta1 = 5U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm1Exta1 = 6U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm1Exta1 = 7U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Sm1Exta1 = 9U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm1Exta1 = 10U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Sm1Exta1 = 11U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm1Exta1 = 12U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Sm1Exta1 = 13U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm1Exta1 = 14U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm1Exta1 = 15U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm1Exta1 = 16U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm1Exta1 = 17U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm1Exta1 = 18U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm1Exta1 = 19U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm1Exta1 = 20U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm1Exta1 = 21U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm1Exta1 = 22U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm1Exta1 = 23U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm1Exta1 = 24U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm1Exta1 = 25U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm1Exta1 = 26U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm1Exta1 = 27U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm1Exta1 = 28U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm1Exta1 = 29U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Sm1Exta1 = 30U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Sm1Exta1 = 31U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm1Exta1 = 32U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm1Exta1 = 33U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm1Exta1 = 34U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm1Exta1 = 35U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm1Exta1 = 36U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Sm1Exta1 = 37U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Sm1Exta1 = 38U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Sm1Exta1 = 39U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Sm1Exta1 = 40U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Sm1Exta1 = 45U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Sm1Exta1 = 46U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Sm1Exta1 = 47U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Sm1Exta1 = 48U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm1Exta1 = 49U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm1Exta1 = 50U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm1Exta1 = 51U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm1Exta1 = 52U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm1Exta1 = 53U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm1Exta1 = 54U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm1Exta1 = 55U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm1Exta1 = 56U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm1Exta1 = 57U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm1Exta1 = 58U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm1Exta1 = 59U + (FlexPWM1_SM1_EXTA1_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM2_EXTA2 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Sm2Exta2 = 1U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Sm2Exta2 = 2U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Sm2Exta2 = 3U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Sm2Exta2 = 4U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Sm2Exta2 = 5U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm2Exta2 = 6U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm2Exta2 = 7U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Sm2Exta2 = 9U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm2Exta2 = 10U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Sm2Exta2 = 11U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm2Exta2 = 12U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Sm2Exta2 = 13U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm2Exta2 = 14U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm2Exta2 = 15U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm2Exta2 = 16U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm2Exta2 = 17U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm2Exta2 = 18U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm2Exta2 = 19U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm2Exta2 = 20U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm2Exta2 = 21U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm2Exta2 = 22U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm2Exta2 = 23U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm2Exta2 = 24U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm2Exta2 = 25U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm2Exta2 = 26U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm2Exta2 = 27U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm2Exta2 = 28U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm2Exta2 = 29U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Sm2Exta2 = 30U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Sm2Exta2 = 31U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm2Exta2 = 32U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm2Exta2 = 33U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm2Exta2 = 34U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm2Exta2 = 35U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm2Exta2 = 36U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Sm2Exta2 = 37U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Sm2Exta2 = 38U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Sm2Exta2 = 39U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Sm2Exta2 = 40U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Sm2Exta2 = 45U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Sm2Exta2 = 46U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Sm2Exta2 = 47U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Sm2Exta2 = 48U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm2Exta2 = 49U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm2Exta2 = 50U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm2Exta2 = 51U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm2Exta2 = 52U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm2Exta2 = 53U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm2Exta2 = 54U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm2Exta2 = 55U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm2Exta2 = 56U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm2Exta2 = 57U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm2Exta2 = 58U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm2Exta2 = 59U + (FlexPWM1_SM2_EXTA2_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM0_EXTSYNC0 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Sm0Extsync0 = 1U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Sm0Extsync0 = 2U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Sm0Extsync0 = 3U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Sm0Extsync0 = 4U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Sm0Extsync0 = 5U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm0Extsync0 = 6U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm0Extsync0 = 7U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Sm0Extsync0 = 9U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm0Extsync0 = 10U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Sm0Extsync0 = 11U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm0Extsync0 = 12U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Sm0Extsync0 = 13U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm0Extsync0 = 14U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm0Extsync0 = 15U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm0Extsync0 = 16U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm0Extsync0 = 17U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm0Extsync0 = 18U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm0Extsync0 = 19U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm0Extsync0 = 20U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm0Extsync0 = 21U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm0Extsync0 = 22U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm0Extsync0 = 23U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm0Extsync0 = 24U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm0Extsync0 = 25U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm0Extsync0 = 26U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm0Extsync0 = 27U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm0Extsync0 = 28U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm0Extsync0 = 29U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Sm0Extsync0 = 30U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Sm0Extsync0 = 31U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm0Extsync0 = 32U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm0Extsync0 = 33U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm0Extsync0 = 34U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm0Extsync0 = 35U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm0Extsync0 = 36U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Sm0Extsync0 = 37U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Sm0Extsync0 = 38U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Sm0Extsync0 = 39U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Sm0Extsync0 = 40U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Sm0Extsync0 = 45U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Sm0Extsync0 = 46U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Sm0Extsync0 = 47U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Sm0Extsync0 = 48U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm0Extsync0 = 49U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm0Extsync0 = 50U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm0Extsync0 = 51U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm0Extsync0 = 52U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm0Extsync0 = 53U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm0Extsync0 = 54U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm0Extsync0 = 55U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm0Extsync0 = 56U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm0Extsync0 = 57U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm0Extsync0 = 58U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm0Extsync0 = 59U + (FlexPWM1_SM0_EXTSYNC0_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM1_EXTSYNC1 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Sm1Extsync1 = 1U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Sm1Extsync1 = 2U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Sm1Extsync1 = 3U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Sm1Extsync1 = 4U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Sm1Extsync1 = 5U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm1Extsync1 = 6U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm1Extsync1 = 7U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Sm1Extsync1 = 9U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm1Extsync1 = 10U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Sm1Extsync1 = 11U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm1Extsync1 = 12U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Sm1Extsync1 = 13U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm1Extsync1 = 14U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm1Extsync1 = 15U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm1Extsync1 = 16U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm1Extsync1 = 17U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm1Extsync1 = 18U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm1Extsync1 = 19U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm1Extsync1 = 20U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm1Extsync1 = 21U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm1Extsync1 = 22U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm1Extsync1 = 23U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm1Extsync1 = 24U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm1Extsync1 = 25U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm1Extsync1 = 26U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm1Extsync1 = 27U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm1Extsync1 = 28U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm1Extsync1 = 29U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Sm1Extsync1 = 30U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Sm1Extsync1 = 31U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm1Extsync1 = 32U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm1Extsync1 = 33U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm1Extsync1 = 34U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm1Extsync1 = 35U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm1Extsync1 = 36U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Sm1Extsync1 = 37U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Sm1Extsync1 = 38U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Sm1Extsync1 = 39U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Sm1Extsync1 = 40U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Sm1Extsync1 = 45U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Sm1Extsync1 = 46U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Sm1Extsync1 = 47U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Sm1Extsync1 = 48U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm1Extsync1 = 49U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm1Extsync1 = 50U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm1Extsync1 = 51U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm1Extsync1 = 52U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm1Extsync1 = 53U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm1Extsync1 = 54U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm1Extsync1 = 55U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm1Extsync1 = 56U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm1Extsync1 = 57U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm1Extsync1 = 58U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm1Extsync1 = 59U + (FlexPWM1_SM1_EXTSYNC1_REG << PMUX_SHIFT), + + /*!< FlexPWM1_SM2_EXTSYNC2 input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Sm2Extsync2 = 1U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Sm2Extsync2 = 2U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Sm2Extsync2 = 3U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Sm2Extsync2 = 4U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Sm2Extsync2 = 5U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Sm2Extsync2 = 6U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Sm2Extsync2 = 7U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Sm2Extsync2 = 9U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Sm2Extsync2 = 10U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Sm2Extsync2 = 11U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Sm2Extsync2 = 12U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Sm2Extsync2 = 13U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Sm2Extsync2 = 14U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Sm2Extsync2 = 15U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Sm2Extsync2 = 16U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Sm2Extsync2 = 17U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Sm2Extsync2 = 18U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Sm2Extsync2 = 19U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Sm2Extsync2 = 20U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Sm2Extsync2 = 21U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Sm2Extsync2 = 22U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Sm2Extsync2 = 23U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Sm2Extsync2 = 24U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Sm2Extsync2 = 25U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Sm2Extsync2 = 26U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Sm2Extsync2 = 27U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Sm2Extsync2 = 28U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Sm2Extsync2 = 29U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Sm2Extsync2 = 30U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Sm2Extsync2 = 31U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Sm2Extsync2 = 32U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Sm2Extsync2 = 33U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Sm2Extsync2 = 34U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Sm2Extsync2 = 35U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Sm2Extsync2 = 36U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Sm2Extsync2 = 37U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Sm2Extsync2 = 38U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Sm2Extsync2 = 39U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Sm2Extsync2 = 40U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Sm2Extsync2 = 45U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Sm2Extsync2 = 46U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Sm2Extsync2 = 47U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Sm2Extsync2 = 48U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Sm2Extsync2 = 49U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Sm2Extsync2 = 50U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Sm2Extsync2 = 51U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Sm2Extsync2 = 52U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Sm2Extsync2 = 53U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Sm2Extsync2 = 54U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Sm2Extsync2 = 55U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Sm2Extsync2 = 56U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Sm2Extsync2 = 57U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Sm2Extsync2 = 58U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Sm2Extsync2 = 59U + (FlexPWM1_SM2_EXTSYNC2_REG << PMUX_SHIFT), + + /*!< FlexPWM1_FAULT input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Fault = 1U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Fault = 2U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Fault = 3U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Fault = 4U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Fault = 5U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Fault = 6U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Fault = 7U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Fault = 9U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Fault = 10U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Fault = 11U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Fault = 12U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Fault = 13U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Fault = 14U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Fault = 15U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Fault = 16U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Fault = 17U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Fault = 18U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Fault = 19U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Fault = 20U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Fault = 21U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Fault = 22U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Fault = 23U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Fault = 24U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Fault = 25U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Fault = 26U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Fault = 27U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Fault = 28U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Fault = 29U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Fault = 30U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Fault = 31U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Fault = 32U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Fault = 33U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Fault = 34U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Fault = 35U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Fault = 36U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Fault = 37U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Fault = 38U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Fault = 39U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Fault = 40U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Fault = 45U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Fault = 46U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Fault = 47U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Fault = 48U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Fault = 49U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Fault = 50U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Fault = 51U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Fault = 52U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Fault = 53U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Fault = 54U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Fault = 55U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Fault = 56U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Fault = 57U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Fault = 58U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Fault = 59U + (FlexPWM1_FAULT_REG << PMUX_SHIFT), + + /*!< FlexPWM1_FORCE input trigger connections. */ + kINPUTMUX_ArmTxevToFlexPwm1Force = 1U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToFlexPwm1Force = 2U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexPwm1Force = 3U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexPwm1Force = 4U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexPwm1Force = 5U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexPwm1Force = 6U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexPwm1Force = 7U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexPwm1Force = 9U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToFlexPwm1Force = 10U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexPwm1Force = 11U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToFlexPwm1Force = 12U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexPwm1Force = 13U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToFlexPwm1Force = 14U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToFlexPwm1Force = 15U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToFlexPwm1Force = 16U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToFlexPwm1Force = 17U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToFlexPwm1Force = 18U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatch0ToFlexPwm1Force = 19U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexPwm1Force = 20U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexPwm1Force = 21U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexPwm1Force = 22U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexPwm1Force = 23U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexPwm1Force = 24U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexPwm1Force = 25U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexPwm1Force = 26U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexPwm1Force = 27U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToFlexPwm1Force = 28U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToFlexPwm1Force = 29U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToFlexPwm1Force = 30U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToFlexPwm1Force = 31U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexPwm1Force = 32U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToFlexPwm1Force = 33U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexPwm1Force = 34U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexPwm1Force = 35U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexPwm1Force = 36U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexPwm1Force = 37U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexPwm1Force = 38U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexPwm1Force = 39U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexPwm1Force = 40U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexPwm1Force = 45U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexPwm1Force = 46U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexPwm1Force = 47U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexPwm1Force = 48U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToFlexPwm1Force = 49U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToFlexPwm1Force = 50U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToFlexPwm1Force = 51U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToFlexPwm1Force = 52U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatch0ToFlexPwm1Force = 53U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexPwm1Force = 54U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToFlexPwm1Force = 55U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexPwm1Force = 56U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToFlexPwm1Force = 57U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexPwm1Force = 58U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToFlexPwm1Force = 59U + (FlexPWM1_FORCE_REG << PMUX_SHIFT), + + /*!< PWM0 external clock trigger. */ + kINPUTMUX_Clk16K1ToPwm0ExtClk = 1U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ClkInToPwm0ExtClk = 2U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToPwm0ExtClk = 3U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToPwm0ExtClk = 4U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ExttrigIn0ToPwm0ExtClk = 5U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ExttrigIn7ToPwm0ExtClk = 6U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToPwm0ExtClk = 7U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToPwm0ExtClk = 8U + (PWM0_EXT_CLK_REG << PMUX_SHIFT), + + /*!< PWM1 external clock trigger. */ + kINPUTMUX_Clk16K1ToPwm1ExtClk = 1U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ClkInToPwm1ExtClk = 2U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out0ToPwm1ExtClk = 3U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToPwm1ExtClk = 4U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ExttrigIn0ToPwm1ExtClk = 5U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_ExttrigIn7ToPwm1ExtClk = 6U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToPwm1ExtClk = 7U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToPwm1ExtClk = 8U + (PWM1_EXT_CLK_REG << PMUX_SHIFT), + + /*!< AOI0 trigger input connections. */ + kINPUTMUX_Adc0Tcomp0ToAoi0Mux = 1U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToAoi0Mux = 2U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToAoi0Mux = 3U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToAoi0Mux = 4U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToAoi0Mux = 5U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToAoi0Mux = 6U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToAoi0Mux = 8U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToAoi0Mux = 9U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToAoi0Mux = 10U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToAoi0Mux = 11U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToAoi0Mux = 12U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToAoi0Mux = 13U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToAoi0Mux = 14U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToAoi0Mux = 15U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToAoi0Mux = 16U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToAoi0Mux = 17U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToAoi0Mux = 18U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToAoi0Mux = 19U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToAoi0Mux = 20U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToAoi0Mux = 22U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToAoi0Mux = 23U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToAoi0Mux = 24U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToAoi0Mux = 25U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatchToAoi0Mux = 26U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToAoi0Mux = 27U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToAoi0Mux = 28U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToAoi0Mux = 29U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToAoi0Mux = 30U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToAoi0Mux = 31U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToAoi0Mux = 32U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToAoi0Mux = 35U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToAoi0Mux = 36U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToAoi0Mux = 37U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToAoi0Mux = 38U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToAoi0Mux = 39U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToAoi0Mux = 40U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToAoi0Mux = 41U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToAoi0Mux = 42U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToAoi0Mux = 43U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToAoi0Mux = 44U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToAoi0Mux = 45U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToAoi0Mux = 46U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToAoi0Mux = 47U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToAoi0Mux = 48U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToAoi0Mux = 49U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToAoi0Mux = 50U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToAoi0Mux = 51U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToAoi0Mux = 52U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToAoi0Mux = 53U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToAoi0Mux = 54U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToAoi0Mux = 55U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToAoi0Mux = 56U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToAoi0Mux = 57U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToAoi0Mux = 58U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToAoi0Mux = 59U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToAoi0Mux = 60U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToAoi0Mux = 61U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToAoi0Mux = 62U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToAoi0Mux = 63U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToAoi0Mux = 64U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToAoi0Mux = 65U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToAoi0Mux = 66U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToAoi0Mux = 67U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToAoi0Mux = 68U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToAoi0Mux = 69U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToAoi0Mux = 70U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToAoi0Mux = 71U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatchToAoi0Mux = 72U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToAoi0Mux = 73U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToAoi0Mux = 74U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToAoi0Mux = 75U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToAoi0Mux = 76U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToAoi0Mux = 77U + (AOI0_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToAoi0Mux = 78U + (AOI0_MUX_REG << PMUX_SHIFT), + + /*!< AOI1 trigger input connections. */ + kINPUTMUX_Adc0Tcomp0ToAoi1Mux = 1U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToAoi1Mux = 2U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToAoi1Mux = 3U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToAoi1Mux = 4U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToAoi1Mux = 5U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToAoi1Mux = 6U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToAoi1Mux = 8U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToAoi1Mux = 9U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToAoi1Mux = 10U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToAoi1Mux = 11U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToAoi1Mux = 12U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToAoi1Mux = 13U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToAoi1Mux = 14U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToAoi1Mux = 15U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToAoi1Mux = 16U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToAoi1Mux = 17U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToAoi1Mux = 18U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToAoi1Mux = 19U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToAoi1Mux = 20U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag0ToAoi1Mux = 22U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag1ToAoi1Mux = 23U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag2ToAoi1Mux = 24U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0CmpFlag3ToAoi1Mux = 25U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc0PosMatchToAoi1Mux = 26U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToAoi1Mux = 27U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToAoi1Mux = 28U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToAoi1Mux = 29U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToAoi1Mux = 30U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToAoi1Mux = 31U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToAoi1Mux = 32U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToAoi1Mux = 35U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToAoi1Mux = 36U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToAoi1Mux = 37U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToAoi1Mux = 38U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToAoi1Mux = 39U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToAoi1Mux = 40U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToAoi1Mux = 41U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToAoi1Mux = 42U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToAoi1Mux = 43U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToAoi1Mux = 44U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToAoi1Mux = 45U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToAoi1Mux = 46U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToAoi1Mux = 47U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToAoi1Mux = 48U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToAoi1Mux = 49U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToAoi1Mux = 50U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToAoi1Mux = 51U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToAoi1Mux = 52U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToAoi1Mux = 53U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToAoi1Mux = 54U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToAoi1Mux = 55U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToAoi1Mux = 56U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToAoi1Mux = 57U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToAoi1Mux = 58U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToAoi1Mux = 59U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToAoi1Mux = 60U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToAoi1Mux = 61U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToAoi1Mux = 62U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToAoi1Mux = 63U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToAoi1Mux = 64U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToAoi1Mux = 65U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToAoi1Mux = 66U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToAoi1Mux = 67U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag0ToAoi1Mux = 68U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag1ToAoi1Mux = 69U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag2ToAoi1Mux = 70U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1CmpFlag3ToAoi1Mux = 71U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Qdc1PosMatchToAoi1Mux = 72U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToAoi1Mux = 73U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToAoi1Mux = 74U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToAoi1Mux = 75U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToAoi1Mux = 76U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToAoi1Mux = 77U + (AOI1_MUX_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToAoi1Mux = 78U + (AOI1_MUX_REG << PMUX_SHIFT), + + /*!< USB-FS trigger input connections. */ + kINPUTMUX_Lpuart0TrgTxdataToUsbfsTrigger = 1U + (USBFS_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart1TrgTxdataToUsbfsTrigger = 2U + (USBFS_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart2TrgTxdataToUsbfsTrigger = 3U + (USBFS_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart3TrgTxdataToUsbfsTrigger = 4U + (USBFS_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart4TrgTxdataToUsbfsTrigger = 5U + (USBFS_TRIG_REG << PMUX_SHIFT), + + /*!< EXT trigger connections. */ + kINPUTMUX_Aoi0Out0ToExtTrigger = 2U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToExtTrigger = 3U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToExtTrigger = 4U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToExtTrigger = 5U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToExtTrigger = 6U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToExtTrigger = 7U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart0ToExtTrigger = 9U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart1ToExtTrigger = 10U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart2ToExtTrigger = 11U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart3ToExtTrigger = 12U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart4ToExtTrigger = 13U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToExtTrigger = 14U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToExtTrigger = 15U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToExtTrigger = 16U + (EXT_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToExtTrigger = 17U + (EXT_TRIG0_REG << PMUX_SHIFT), + + /*!< LPI2C0 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpi2c0Trigger = 2U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpi2c0Trigger = 3U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpi2c0Trigger = 4U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpi2c0Trigger = 5U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpi2c0Trigger = 6U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpi2c0Trigger = 7U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToLpi2c0Trigger = 9U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToLpi2c0Trigger = 10U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToLpi2c0Trigger = 11U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToLpi2c0Trigger = 12U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToLpi2c0Trigger = 13U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToLpi2c0Trigger = 14U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpi2c0Trigger = 15U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpi2c0Trigger = 17U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpi2c0Trigger = 18U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpi2c0Trigger = 19U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpi2c0Trigger = 20U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpi2c0Trigger = 21U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpi2c0Trigger = 22U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpi2c0Trigger = 23U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpi2c0Trigger = 24U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpi2c0Trigger = 25U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpi2c0Trigger = 26U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpi2c0Trigger = 27U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpi2c0Trigger = 28U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpi2c0Trigger = 29U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpi2c0Trigger = 30U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpi2c0Trigger = 31U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpi2c0Trigger = 32U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpi2c0Trigger = 33U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpi2c0Trigger = 34U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpi2c0Trigger = 35U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpi2c0Trigger = 36U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpi2c0Trigger = 37U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpi2c0Trigger = 38U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpi2c0Trigger = 39U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpi2c0Trigger = 40U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpi2c0Trigger = 41U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpi2c0Trigger = 42U + (LPI2C0_TRIG_REG << PMUX_SHIFT), + + /*!< LPI2C1 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpi2c1Trigger = 2U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpi2c1Trigger = 3U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpi2c1Trigger = 4U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpi2c1Trigger = 5U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpi2c1Trigger = 6U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpi2c1Trigger = 7U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToLpi2c1Trigger = 9U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToLpi2c1Trigger = 10U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToLpi2c1Trigger = 11U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToLpi2c1Trigger = 12U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToLpi2c1Trigger = 13U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToLpi2c1Trigger = 14U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpi2c1Trigger = 15U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpi2c1Trigger = 17U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpi2c1Trigger = 18U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpi2c1Trigger = 19U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpi2c1Trigger = 20U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpi2c1Trigger = 21U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpi2c1Trigger = 22U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpi2c1Trigger = 23U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpi2c1Trigger = 24U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpi2c1Trigger = 25U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpi2c1Trigger = 26U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpi2c1Trigger = 27U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpi2c1Trigger = 28U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpi2c1Trigger = 29U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpi2c1Trigger = 30U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpi2c1Trigger = 31U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpi2c1Trigger = 32U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpi2c1Trigger = 33U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpi2c1Trigger = 34U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpi2c1Trigger = 35U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpi2c1Trigger = 36U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpi2c1Trigger = 37U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpi2c1Trigger = 38U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpi2c1Trigger = 39U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpi2c1Trigger = 40U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpi2c1Trigger = 41U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpi2c1Trigger = 42U + (LPI2C1_TRIG_REG << PMUX_SHIFT), + + /*!< LPI2C2 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpi2c2Trigger = 2U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpi2c2Trigger = 3U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpi2c2Trigger = 4U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpi2c2Trigger = 5U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpi2c2Trigger = 6U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpi2c2Trigger = 7U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToLpi2c2Trigger = 9U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToLpi2c2Trigger = 10U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToLpi2c2Trigger = 11U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToLpi2c2Trigger = 12U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToLpi2c2Trigger = 13U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToLpi2c2Trigger = 14U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpi2c2Trigger = 15U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpi2c2Trigger = 17U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpi2c2Trigger = 18U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpi2c2Trigger = 19U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpi2c2Trigger = 20U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpi2c2Trigger = 21U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpi2c2Trigger = 22U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpi2c2Trigger = 23U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpi2c2Trigger = 24U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpi2c2Trigger = 25U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpi2c2Trigger = 26U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpi2c2Trigger = 27U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpi2c2Trigger = 28U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpi2c2Trigger = 29U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpi2c2Trigger = 30U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpi2c2Trigger = 31U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpi2c2Trigger = 32U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpi2c2Trigger = 33U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpi2c2Trigger = 34U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpi2c2Trigger = 35U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpi2c2Trigger = 36U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpi2c2Trigger = 37U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpi2c2Trigger = 38U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpi2c2Trigger = 39U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpi2c2Trigger = 40U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpi2c2Trigger = 41U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpi2c2Trigger = 42U + (LPI2C2_TRIG_REG << PMUX_SHIFT), + + /*!< LPSPI0 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpspi0Trigger = 2U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpspi0Trigger = 3U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpspi0Trigger = 4U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpspi0Trigger = 5U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpspi0Trigger = 6U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpspi0Trigger = 7U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToLpspi0Trigger = 9U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToLpspi0Trigger = 10U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToLpspi0Trigger = 11U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToLpspi0Trigger = 12U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToLpspi0Trigger = 13U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToLpspi0Trigger = 14U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpspi0Trigger = 15U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpspi0Trigger = 17U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpspi0Trigger = 18U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpspi0Trigger = 19U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpspi0Trigger = 20U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpspi0Trigger = 21U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpspi0Trigger = 22U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpspi0Trigger = 23U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpspi0Trigger = 24U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpspi0Trigger = 25U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpspi0Trigger = 26U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpspi0Trigger = 27U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpspi0Trigger = 28U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpspi0Trigger = 29U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpspi0Trigger = 30U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpspi0Trigger = 31U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpspi0Trigger = 32U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpspi0Trigger = 33U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpspi0Trigger = 34U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpspi0Trigger = 35U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpspi0Trigger = 36U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpspi0Trigger = 37U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpspi0Trigger = 38U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpspi0Trigger = 39U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpspi0Trigger = 40U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpspi0Trigger = 41U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpspi0Trigger = 42U + (LPSPI0_TRIG_REG << PMUX_SHIFT), + + /*!< LPSPI1 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpspi1Trigger = 2U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpspi1Trigger = 3U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpspi1Trigger = 4U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpspi1Trigger = 5U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpspi1Trigger = 6U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpspi1Trigger = 7U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToLpspi1Trigger = 9U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToLpspi1Trigger = 10U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToLpspi1Trigger = 11U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToLpspi1Trigger = 12U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToLpspi1Trigger = 13U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToLpspi1Trigger = 14U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpspi1Trigger = 15U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpspi1Trigger = 17U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpspi1Trigger = 18U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpspi1Trigger = 19U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpspi1Trigger = 20U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpspi1Trigger = 21U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpspi1Trigger = 22U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpspi1Trigger = 23U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpspi1Trigger = 24U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpspi1Trigger = 25U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpspi1Trigger = 26U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpspi1Trigger = 27U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpspi1Trigger = 28U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpspi1Trigger = 29U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpspi1Trigger = 30U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpspi1Trigger = 31U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpspi1Trigger = 32U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpspi1Trigger = 33U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpspi1Trigger = 34U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpspi1Trigger = 35U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpspi1Trigger = 36U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpspi1Trigger = 37U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpspi1Trigger = 38U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpspi1Trigger = 39U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpspi1Trigger = 40U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpspi1Trigger = 41U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpspi1Trigger = 42U + (LPSPI1_TRIG_REG << PMUX_SHIFT), + + /*!< LPUART0 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpuart0Trigger = 2U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpuart0Trigger = 3U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpuart0Trigger = 4U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpuart0Trigger = 5U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpuart0Trigger = 6U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpuart0Trigger = 7U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToLpuart0Trigger = 9U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToLpuart0Trigger = 10U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToLpuart0Trigger = 11U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToLpuart0Trigger = 12U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToLpuart0Trigger = 13U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToLpuart0Trigger = 14U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpuart0Trigger = 15U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpuart0Trigger = 17U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpuart0Trigger = 18U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpuart0Trigger = 19U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpuart0Trigger = 20U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpuart0Trigger = 21U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpuart0Trigger = 22U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpuart0Trigger = 23U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpuart0Trigger = 24U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToLpuart0Trigger = 25U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToLpuart0Trigger = 26U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToLpuart0Trigger = 27U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToLpuart0Trigger = 28U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpuart0Trigger = 29U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpuart0Trigger = 30U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpuart0Trigger = 31U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpuart0Trigger = 32U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpuart0Trigger = 33U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpuart0Trigger = 34U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart0Trigger = 35U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpuart0Trigger = 36U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpuart0Trigger = 37U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpuart0Trigger = 38U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpuart0Trigger = 39U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpuart0Trigger = 40U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpuart0Trigger = 41U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpuart0Trigger = 42U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpuart0Trigger = 43U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpuart0Trigger = 44U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpuart0Trigger = 45U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpuart0Trigger = 46U + (LPUART0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpuart0Trigger = 47U + (LPUART0_TRIG_REG << PMUX_SHIFT), + + /*!< LPUART1 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpuart1Trigger = 2U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpuart1Trigger = 3U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpuart1Trigger = 4U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpuart1Trigger = 5U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpuart1Trigger = 6U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpuart1Trigger = 7U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToLpuart1Trigger = 9U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToLpuart1Trigger = 10U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToLpuart1Trigger = 11U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToLpuart1Trigger = 12U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToLpuart1Trigger = 13U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToLpuart1Trigger = 14U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpuart1Trigger = 15U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpuart1Trigger = 17U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpuart1Trigger = 18U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpuart1Trigger = 19U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpuart1Trigger = 20U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpuart1Trigger = 21U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpuart1Trigger = 22U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpuart1Trigger = 23U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpuart1Trigger = 24U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToLpuart1Trigger = 25U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToLpuart1Trigger = 26U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToLpuart1Trigger = 27U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToLpuart1Trigger = 28U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpuart1Trigger = 29U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpuart1Trigger = 30U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpuart1Trigger = 31U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpuart1Trigger = 32U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpuart1Trigger = 33U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpuart1Trigger = 34U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart1Trigger = 35U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpuart1Trigger = 36U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpuart1Trigger = 37U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpuart1Trigger = 38U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpuart1Trigger = 39U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpuart1Trigger = 40U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpuart1Trigger = 41U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpuart1Trigger = 42U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpuart1Trigger = 43U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpuart1Trigger = 44U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpuart1Trigger = 45U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpuart1Trigger = 46U + (LPUART1_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpuart1Trigger = 47U + (LPUART1_TRIG_REG << PMUX_SHIFT), + + /*!< LPUART2 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpuart2Trigger = 2U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpuart2Trigger = 3U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpuart2Trigger = 4U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpuart2Trigger = 5U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpuart2Trigger = 6U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpuart2Trigger = 7U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToLpuart2Trigger = 9U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToLpuart2Trigger = 10U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToLpuart2Trigger = 11U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToLpuart2Trigger = 12U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToLpuart2Trigger = 13U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToLpuart2Trigger = 14U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpuart2Trigger = 15U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpuart2Trigger = 17U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpuart2Trigger = 18U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpuart2Trigger = 19U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpuart2Trigger = 20U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpuart2Trigger = 21U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpuart2Trigger = 22U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpuart2Trigger = 23U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpuart2Trigger = 24U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToLpuart2Trigger = 25U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToLpuart2Trigger = 26U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToLpuart2Trigger = 27U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToLpuart2Trigger = 28U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpuart2Trigger = 29U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpuart2Trigger = 30U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpuart2Trigger = 31U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpuart2Trigger = 32U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpuart2Trigger = 33U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpuart2Trigger = 34U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart2Trigger = 35U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpuart2Trigger = 36U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpuart2Trigger = 37U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpuart2Trigger = 38U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpuart2Trigger = 39U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpuart2Trigger = 40U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpuart2Trigger = 41U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpuart2Trigger = 42U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpuart2Trigger = 43U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpuart2Trigger = 44U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpuart2Trigger = 45U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpuart2Trigger = 46U + (LPUART2_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpuart2Trigger = 47U + (LPUART2_TRIG_REG << PMUX_SHIFT), + + /*!< LPUART3 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpuart3Trigger = 2U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpuart3Trigger = 3U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpuart3Trigger = 4U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpuart3Trigger = 5U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpuart3Trigger = 6U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpuart3Trigger = 7U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToLpuart3Trigger = 9U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToLpuart3Trigger = 10U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToLpuart3Trigger = 11U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToLpuart3Trigger = 12U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToLpuart3Trigger = 13U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToLpuart3Trigger = 14U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpuart3Trigger = 15U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpuart3Trigger = 17U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpuart3Trigger = 18U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpuart3Trigger = 19U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpuart3Trigger = 20U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpuart3Trigger = 21U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpuart3Trigger = 22U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpuart3Trigger = 23U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpuart3Trigger = 24U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToLpuart3Trigger = 25U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToLpuart3Trigger = 26U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToLpuart3Trigger = 27U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToLpuart3Trigger = 28U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpuart3Trigger = 29U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpuart3Trigger = 30U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpuart3Trigger = 31U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpuart3Trigger = 32U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpuart3Trigger = 33U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpuart3Trigger = 34U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart3Trigger = 35U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpuart3Trigger = 36U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpuart3Trigger = 37U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpuart3Trigger = 38U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpuart3Trigger = 39U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpuart3Trigger = 40U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpuart3Trigger = 41U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpuart3Trigger = 42U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpuart3Trigger = 43U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpuart3Trigger = 44U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpuart3Trigger = 45U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpuart3Trigger = 46U + (LPUART3_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpuart3Trigger = 47U + (LPUART3_TRIG_REG << PMUX_SHIFT), + + /*!< LPUART4 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToLpuart4Trigger = 2U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToLpuart4Trigger = 3U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToLpuart4Trigger = 4U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToLpuart4Trigger = 5U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToLpuart4Trigger = 6U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToLpuart4Trigger = 7U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToLpuart4Trigger = 9U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M3ToLpuart4Trigger = 10U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToLpuart4Trigger = 11U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M3ToLpuart4Trigger = 12U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToLpuart4Trigger = 13U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M3ToLpuart4Trigger = 14U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToLpuart4Trigger = 15U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToLpuart4Trigger = 17U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToLpuart4Trigger = 18U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToLpuart4Trigger = 19U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToLpuart4Trigger = 20U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToLpuart4Trigger = 21U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToLpuart4Trigger = 22U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToLpuart4Trigger = 23U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToLpuart4Trigger = 24U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn8ToLpuart4Trigger = 25U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn9ToLpuart4Trigger = 26U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn10ToLpuart4Trigger = 27U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn11ToLpuart4Trigger = 28U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToLpuart4Trigger = 29U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToLpuart4Trigger = 30U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToLpuart4Trigger = 31U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToLpuart4Trigger = 32U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToLpuart4Trigger = 33U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToLpuart4Trigger = 34U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart4Trigger = 35U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToLpuart4Trigger = 36U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToLpuart4Trigger = 37U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToLpuart4Trigger = 38U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToLpuart4Trigger = 39U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToLpuart4Trigger = 40U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToLpuart4Trigger = 41U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToLpuart4Trigger = 42U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToLpuart4Trigger = 43U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToLpuart4Trigger = 44U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToLpuart4Trigger = 45U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToLpuart4Trigger = 46U + (LPUART4_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToLpuart4Trigger = 47U + (LPUART4_TRIG_REG << PMUX_SHIFT), + +/*!< Flexio trigger0 input connections. */ + kINPUTMUX_Aoi0Out0ToFlexioTrigger = 1U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToFlexioTrigger = 2U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToFlexioTrigger = 3U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToFlexioTrigger = 4U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp0ToFlexioTrigger = 5U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp1ToFlexioTrigger = 6U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp2ToFlexioTrigger = 7U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc0Tcomp3ToFlexioTrigger = 8U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToFlexioTrigger = 9U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToFlexioTrigger = 10U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToFlexioTrigger = 12U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M2ToFlexioTrigger = 13U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToFlexioTrigger = 14U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M2ToFlexioTrigger = 15U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToFlexioTrigger = 16U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M2ToFlexioTrigger = 17U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToFlexioTrigger = 18U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToFlexioTrigger = 20U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToFlexioTrigger = 21U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToFlexioTrigger = 22U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn0ToFlexioTrigger = 24U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn1ToFlexioTrigger = 25U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn2ToFlexioTrigger = 26U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn3ToFlexioTrigger = 27U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn4ToFlexioTrigger = 28U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn5ToFlexioTrigger = 29U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn6ToFlexioTrigger = 30U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_TrigIn7ToFlexioTrigger = 31U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToFlexioTrigger = 32U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToFlexioTrigger = 33U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToFlexioTrigger = 34U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToFlexioTrigger = 35U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_WuuToFlexioTrigger = 36U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1A0Trig0ToFlexioTrigger = 37U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c0MasterEndOfPacketToFlexioTrigger = 38U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c0SlaveEndOfPacketToFlexioTrigger = 39U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c1MasterEndOfPacketToFlexioTrigger = 40U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c1SlaveEndOfPacketToFlexioTrigger = 41U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpspi0EndOfFrameToFlexioTrigger = 42U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpspi0ReceivedDataWordToFlexioTrigger = 43U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpspi1EndOfFrameToFlexioTrigger = 44U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpspi1ReceivedDataWordToFlexioTrigger = 45U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceivedDataWordToFlexioTrigger = 46U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart0TransmittedDataWordToFlexioTrigger = 47U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart0ReceiveLineIdleToFlexioTrigger = 48U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceivedDataWordToFlexioTrigger = 49U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart1TransmittedDataWordToFlexioTrigger = 50U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart1ReceiveLineIdleToFlexioTrigger = 51U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceivedDataWordToFlexioTrigger = 52U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart2TransmittedDataWordToFlexioTrigger = 53U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart2ReceiveLineIdleToFlexioTrigger = 54U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceivedDataWordToFlexioTrigger = 55U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart3TransmittedDataWordToFlexioTrigger = 56U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart3ReceiveLineIdleToFlexioTrigger = 57U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceivedDataWordToFlexioTrigger = 58U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart4TransmittedDataWordToFlexioTrigger = 59U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpuart4ReceiveLineIdleToFlexioTrigger = 60U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToFlexioTrigger = 61U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToFlexioTrigger = 62U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToFlexioTrigger = 63U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToFlexioTrigger = 64U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToFlexioTrigger = 65U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToFlexioTrigger = 66U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToFlexioTrigger = 67U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToFlexioTrigger = 68U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M2ToFlexioTrigger = 69U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M3ToFlexioTrigger = 70U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M2ToFlexioTrigger = 71U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M3ToFlexioTrigger = 72U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToFlexioTrigger = 73U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToFlexioTrigger = 74U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToFlexioTrigger = 75U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c2MasterEndOfPacketToFlexioTrigger = 77U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c2SlaveEndOfPacketToFlexioTrigger = 78U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c3MasterEndOfPacketToFlexioTrigger = 79U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + kINPUTMUX_Lpi2c3SlaveEndOfPacketToFlexioTrigger = 80U + (FLEXIO_TRIG0_REG << PMUX_SHIFT), + +/*!< Opamp0 trigger input connections. */ + kINPUTMUX_Aoi0Out0ToOpamp0Trigger = 2U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out1ToOpamp0Trigger = 3U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out2ToOpamp0Trigger = 4U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi0Out3ToOpamp0Trigger = 5U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp0OutToOpamp0Trigger = 6U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Cmp1OutToOpamp0Trigger = 7U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToOpamp0Trigger = 9U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToOpamp0Trigger = 10U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToOpamp0Trigger = 11U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToOpamp0Trigger = 12U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToOpamp0Trigger = 13U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToOpamp0Trigger = 14U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Lptmr0ToOpamp0Trigger = 15U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig0ToOpamp0Trigger = 18U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm0OutTrig1ToOpamp0Trigger = 19U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig0ToOpamp0Trigger = 20U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm1OutTrig1ToOpamp0Trigger = 21U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig0ToOpamp0Trigger = 22U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm0Sm2OutTrig1ToOpamp0Trigger = 23U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio0PinEventTrig0ToOpamp0Trigger = 26U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio1PinEventTrig0ToOpamp0Trigger = 27U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio2PinEventTrig0ToOpamp0Trigger = 28U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio3PinEventTrig0ToOpamp0Trigger = 29U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Gpio4PinEventTrig0ToOpamp0Trigger = 30U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_WuuToOpamp0Trigger = 31U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out0ToOpamp0Trigger = 33U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out1ToOpamp0Trigger = 34U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out2ToOpamp0Trigger = 35U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Aoi1Out3ToOpamp0Trigger = 36U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp0ToOpamp0Trigger = 37U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp1ToOpamp0Trigger = 38U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp2ToOpamp0Trigger = 39U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Adc1Tcomp3ToOpamp0Trigger = 40U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToOpamp0Trigger = 41U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToOpamp0Trigger = 42U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToOpamp0Trigger = 43U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToOpamp0Trigger = 44U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh0ToOpamp0Trigger = 45U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh1ToOpamp0Trigger = 46U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh2ToOpamp0Trigger = 47U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_FlexioCh3ToOpamp0Trigger = 48U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig0ToOpamp0Trigger = 50U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm0OutTrig1ToOpamp0Trigger = 51U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig0ToOpamp0Trigger = 52U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm1OutTrig1ToOpamp0Trigger = 53U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig0ToOpamp0Trigger = 54U + (OPAMP0_TRIG_REG << PMUX_SHIFT), + kINPUTMUX_Pwm1Sm2OutTrig1ToOpamp0Trigger = 55U + (OPAMP0_TRIG_REG << PMUX_SHIFT), +} inputmux_connection_t; + +/*@}*/ + +/*@}*/ + +#endif /* _FSL_INPUTMUX_CONNECTIONS_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpadc.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpadc.c new file mode 100644 index 00000000000..c22741c4f58 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpadc.c @@ -0,0 +1,977 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpadc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpadc" +#endif + +#ifndef ADC_VERID_DIFFEN_MASK +#define ADC_VERID_DIFFEN_MASK (0x2U) +#endif /* ADC_VERID_DIFFEN_MASK */ + +#ifndef ADC_VERID_NUM_SEC_MASK +#define ADC_VERID_NUM_SEC_MASK (0x800U) +#endif /* ADC_VERID_NUM_SEC_MASK */ + +#define ADC_CMDL_CHANNEL_MODE_MASK (0x60U) +#define ADC_CMDL_CHANNEL_MODE_SHIFT (5U) +#define ADC_CMDL_CHANNEL_MODE(x) \ + (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CHANNEL_MODE_SHIFT)) & ADC_CMDL_CHANNEL_MODE_MASK) + +#define GET_ADC_CFG_TPRICTRL_VALUE(val) (((uint32_t)val) & 0x3U) + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES +#define GET_ADC_CFG_TRES_VALUE(val) ((((uint32_t)val) & 0x4U) >> 2U) +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES +#define GET_ADC_CFG_TCMDRES_VALUE(val) ((((uint32_t)val) & 0x8U) >> 3U) +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI +#define GET_ADC_CFG_HPT_EXDI_VALUE(val) ((((uint32_t)val) & 0x10U) >> 4U) +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI */ + +#if defined(LPADC_RSTS) +#define LPADC_RESETS_ARRAY LPADC_RSTS +#elif defined(ADC_RSTS) +#define LPADC_RESETS_ARRAY ADC_RSTS +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get instance number for LPADC module. + * + * @param base LPADC peripheral base address + */ +static uint32_t LPADC_GetInstance(ADC_Type *base); + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ +/*! + * @brief Get gain conversion result . + * + * @param gainAdjustment gain adjustment value. + */ +static uint32_t LPADC_GetGainConvResult(float gainAdjustment); +#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to LPADC bases for each instance. */ +static ADC_Type *const s_lpadcBases[] = ADC_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to LPADC clocks for each instance. */ +static const clock_ip_name_t s_lpadcClocks[] = LPADC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(LPADC_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_lpadcResets[] = LPADC_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t LPADC_GetInstance(ADC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + /* + * $Branch Coverage Justification$ + * (instance >= ARRAY_SIZE(s_lpadcBases)) not covered. The peripheral base + * address is always valid and checked by assert. + */ + for (instance = 0; instance < ARRAY_SIZE(s_lpadcBases); instance++) + { + /* + * $Branch Coverage Justification$ + * (s_lpadcBases[instance] != base) not covered. The peripheral base + * address is always valid and checked by assert. + */ + if (s_lpadcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_lpadcBases)); + + return instance; +} + +#if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) +/*! + * brief Get gain conversion Result . + * + * param gainAdjustment gain adjustment value. + */ +static uint32_t LPADC_GetGainConvResult(float gainAdjustment) +{ + uint16_t i = 0U; + uint32_t tmp32 = 0U; + uint32_t GCRa[17] = {0}; + uint32_t GCALR = 0U; + + for (i = 0x11U; i > 0U; i--) + { + tmp32 = (uint32_t)((gainAdjustment) / ((float)(1.0 / (double)(1U << (0x10U - (i - 1U)))))); + GCRa[i - 1U] = tmp32; + gainAdjustment = gainAdjustment - ((float)tmp32) * ((float)(1.0 / (double)(1U << (0x10U - (i - 1U))))); + } + /* Get GCALR value calculated */ + for (i = 0x11U; i > 0U; i--) + { + GCALR += GCRa[i - 1U] * ((uint32_t)(1UL << (uint32_t)(i - 1UL))); + } + + /* to return GCALR value calculated */ + return GCALR; +} +#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ + +/*! + * brief Initializes the LPADC module. + * + * param base LPADC peripheral base address. + * param config Pointer to configuration structure. See "lpadc_config_t". + */ +void LPADC_Init(ADC_Type *base, const lpadc_config_t *config) +{ + /* Check if the pointer is available. */ + assert(config != NULL); + + uint32_t tmp32 = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock for LPADC instance. */ + (void)CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(LPADC_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_lpadcResets[LPADC_GetInstance(base)]); +#endif + + /* Reset the module. */ + LPADC_DoResetConfig(base); +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + LPADC_DoResetFIFO0(base); + LPADC_DoResetFIFO1(base); +#else + LPADC_DoResetFIFO(base); +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + + /* Disable the module before setting configuration. */ + LPADC_Enable(base, false); + + /* Configure the module generally. */ + if (config->enableInDozeMode) + { + base->CTRL &= ~ADC_CTRL_DOZEN_MASK; + } + else + { + base->CTRL |= ADC_CTRL_DOZEN_MASK; + } + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS + /* Set calibration average mode. */ + base->CTRL |= ADC_CTRL_CAL_AVGS(config->conversionAverageMode); +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ + +/* ADCx_CFG. */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN + if (config->enableInternalClock) + { + tmp32 |= ADC_CFG_ADCKEN_MASK; + } +#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG + if (config->enableVref1LowVoltage) + { + tmp32 |= ADC_CFG_VREF1RNG_MASK; + } +#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ + if (config->enableAnalogPreliminary) + { + tmp32 |= ADC_CFG_PWREN_MASK; + } + tmp32 |= (ADC_CFG_PUDLY(config->powerUpDelay) /* Power up delay. */ + | ADC_CFG_REFSEL(config->referenceVoltageSource) /* Reference voltage. */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) + | ADC_CFG_PWRSEL(config->powerLevelMode) /* Power configuration. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) */ + ); + + tmp32 |= ADC_CFG_TPRICTRL(GET_ADC_CFG_TPRICTRL_VALUE(config->triggerPriorityPolicy)); + +#if (defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES) + tmp32 |= ADC_CFG_TRES(GET_ADC_CFG_TRES_VALUE(config->triggerPriorityPolicy)); +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES */ + +#if (defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) + tmp32 |= ADC_CFG_TCMDRES(GET_ADC_CFG_TCMDRES_VALUE(config->triggerPriorityPolicy)); +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES */ + +#if (defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) + tmp32 |= ADC_CFG_HPT_EXDI(GET_ADC_CFG_HPT_EXDI_VALUE(config->triggerPriorityPolicy)); +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI */ + + base->CFG = tmp32; + + /* ADCx_PAUSE. */ + if (config->enableConvPause) + { + base->PAUSE = ADC_PAUSE_PAUSEEN_MASK | ADC_PAUSE_PAUSEDLY(config->convPauseDelay); + } + else + { + base->PAUSE = 0U; + } + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + /* ADCx_FCTRL0. */ + base->FCTRL[0] = ADC_FCTRL_FWMARK(config->FIFO0Watermark); + /* ADCx_FCTRL1. */ + base->FCTRL[1] = ADC_FCTRL_FWMARK(config->FIFO1Watermark); +#else + /* ADCx_FCTRL. */ + base->FCTRL = ADC_FCTRL_FWMARK(config->FIFOWatermark); +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + + /* Enable the module after setting configuration. */ + LPADC_Enable(base, true); +} + +/*! + * brief Gets an available pre-defined settings for initial configuration. + * + * This function initializes the converter configuration structure with an available settings. The default values are: + * code + * config->enableInDozeMode = true; + * config->conversionAverageMode = kLPADC_ConversionAverage1; + * config->enableAnalogPreliminary = false; + * config->powerUpDelay = 0x80; + * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; + * config->powerLevelMode = kLPADC_PowerLevelAlt1; + * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; + * config->enableConvPause = false; + * config->convPauseDelay = 0U; + * config->FIFO0Watermark = 0U; + * config->FIFO1Watermark = 0U; + * config->FIFOWatermark = 0U; + * endcode + * param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConfig(lpadc_config_t *config) +{ + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN + config->enableInternalClock = false; +#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG + config->enableVref1LowVoltage = false; +#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ + config->enableInDozeMode = true; +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS + /* Set calibration average mode. */ + config->conversionAverageMode = kLPADC_ConversionAverage1; +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ + config->enableAnalogPreliminary = false; + config->powerUpDelay = 0x80; + config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; +#if defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) + config->powerLevelMode = kLPADC_PowerLevelAlt1; +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) */ + config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; + config->enableConvPause = false; + config->convPauseDelay = 0U; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + config->FIFO0Watermark = 0U; + config->FIFO1Watermark = 0U; +#else + config->FIFOWatermark = 0U; +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ +} + +/*! + * brief De-initializes the LPADC module. + * + * param base LPADC peripheral base address. + */ +void LPADC_Deinit(ADC_Type *base) +{ + /* Disable the module. */ + LPADC_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the clock. */ + (void)CLOCK_DisableClock(s_lpadcClocks[LPADC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * brief Get the result in conversion FIFOn. + * + * param base LPADC peripheral base address. + * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. + * param index Result FIFO index. + * + * return Status whether FIFOn entry is valid. + */ +bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index) +{ + assert(result != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32 = 0U; + + tmp32 = base->RESFIFO[index]; + + if (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK)) + { + return false; /* FIFO is empty. Discard any read from RESFIFO. */ + } + + result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; + result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; + result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; + result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); + + return true; +} +/*! + * brief Get the result in conversion FIFOn using blocking method. + * + * param base LPADC peripheral base address. + * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. + * param index Result FIFO index. + */ +void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index) +{ + assert(result != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32 = 0U; + + tmp32 = base->RESFIFO[index]; + + while (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK)) + { + tmp32 = base->RESFIFO[index]; + } + + result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; + result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; + result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; + result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); +} +#else +/*! + * brief Get the result in conversion FIFO. + * + * param base LPADC peripheral base address. + * param result Pointer to structure variable that keeps the conversion result in conversion FIFO. + * + * return Status whether FIFO entry is valid. + */ +bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result) +{ + assert(result != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32 = 0U; + + tmp32 = base->RESFIFO; + + if (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK)) + { + return false; /* FIFO is empty. Discard any read from RESFIFO. */ + } + + result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; + result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; + result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; + result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); + + return true; +} +/*! + * @brief Get the result in conversion FIFO using blocking method. + * + * @param base LPADC peripheral base address. + * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO. + */ +void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result) +{ + assert(result != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32 = 0U; + + tmp32 = base->RESFIFO; + + while (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK)) + { + tmp32 = base->RESFIFO; + } + + result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT; + result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT; + result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT; + result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK); +} +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + +/*! + * brief Configure the conversion trigger source. + * + * Each programmable trigger can launch the conversion command in command buffer. + * + * param base LPADC peripheral base address. + * param triggerId ID for each trigger. Typically, the available value range is from 0 to 3. + * param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. + */ +void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config) +{ + assert(triggerId < ADC_TCTRL_COUNT); /* Check if the triggerId is available in this device. */ + assert(config != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32; + + tmp32 = ADC_TCTRL_TCMD(config->targetCommandId) /* Trigger command select. */ + | ADC_TCTRL_TDLY(config->delayPower) /* Trigger delay select. */ + | ADC_TCTRL_TPRI(config->priority) /* Trigger priority setting. */ +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + | ADC_TCTRL_FIFO_SEL_A(config->channelAFIFOSelect) +#if !(defined(FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) && FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) + | ADC_TCTRL_FIFO_SEL_B(config->channelBFIFOSelect) +#endif /* FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B */ +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + ; + if (config->enableHardwareTrigger) + { + tmp32 |= ADC_TCTRL_HTEN_MASK; + } + + base->TCTRL[triggerId] = tmp32; +} + +/*! + * brief Gets an available pre-defined settings for trigger's configuration. + * + * This function initializes the trigger's configuration structure with an available settings. The default values are: + * code + * config->targetCommandId = 0U; + * config->delayPower = 0U; + * config->priority = 0U; + * config->channelAFIFOSelect = 0U; + * config->channelBFIFOSelect = 0U; + * config->enableHardwareTrigger = false; + * endcode + * param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config) +{ + assert(config != NULL); /* Check if the input pointer is available. */ + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->targetCommandId = 0U; + config->delayPower = 0U; + config->priority = 0U; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + config->channelAFIFOSelect = 0U; + config->channelBFIFOSelect = 0U; +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + config->enableHardwareTrigger = false; +} + +/*! + * brief Configure conversion command. + * + * note The number of compare value register on different chips is different, that is mean in some chips, some + * command buffers do not have the compare functionality. + * + * param base LPADC peripheral base address. + * param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. + * param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. + */ +void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config) +{ + assert(commandId < (ADC_CMDL_COUNT + 1U)); /* Check if the commandId is available on this device. */ + assert(config != NULL); /* Check if the input pointer is available. */ + + uint32_t tmp32 = 0; + + commandId--; /* The available command number are 1-15, while the index of register group are 0-14. */ + + /* ADCx_CMDL. */ + tmp32 = ADC_CMDL_ADCH(config->channelNumber); /* Channel number. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH + tmp32 |= ADC_CMDL_ALTB_ADCH(config->channelBNumber); /* Alternate channel B number. */ +#endif +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE + tmp32 |= ADC_CMDL_CSCALE(config->sampleScaleMode); /* Full/Part scale input voltage. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE + tmp32 |= ADC_CMDL_ALTB_CSCALE(config->channelBScaleMode); /* Alternate channel B full/Part scale input voltage. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE */ + +#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF + assert(((config->sampleChannelMode >= kLPADC_SampleChannelDiffBothSideAB) && + (((base->VERID) & ADC_VERID_DIFFEN_MASK) != 0U)) || + (config->sampleChannelMode < kLPADC_SampleChannelDiffBothSideAB)); +#endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF */ + +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE + assert(((config->sampleChannelMode == kLPADC_SampleChannelDiffBothSide) && + (((base->VERID) & ADC_VERID_DIFFEN_MASK) != 0U)) || + ((config->sampleChannelMode == kLPADC_SampleChannelDualSingleEndBothSide) && + (((base->VERID) & ADC_VERID_NUM_SEC_MASK) != 0U)) || + (config->sampleChannelMode < kLPADC_SampleChannelDualSingleEndBothSide)); +#endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */ +#endif /* !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */ + + tmp32 |= ADC_CMDL_CHANNEL_MODE(config->sampleChannelMode); + +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE + tmp32 |= ADC_CMDL_MODE(config->conversionResolutionMode); +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ + +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN) && FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN + /* Enable alternate channel B.*/ + if (config->enableChannelB) + { + tmp32 |= ADC_CMDL_ALTBEN_MASK; + } +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN */ + + base->CMD[commandId].CMDL = tmp32; + + /* ADCx_CMDH. */ + tmp32 = ADC_CMDH_NEXT(config->chainedNextCommandNumber) /* Next Command Select. */ + | ADC_CMDH_LOOP(config->loopCount) /* Loop Count Select. */ + | ADC_CMDH_AVGS(config->hardwareAverageMode) /* Hardware Average Select. */ + | ADC_CMDH_STS(config->sampleTimeMode) /* Sample Time Select. */ + | ADC_CMDH_CMPEN(config->hardwareCompareMode); /* Hardware compare enable. */ +#if (defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) + if (config->enableWaitTrigger) + { + tmp32 |= ADC_CMDH_WAIT_TRIG_MASK; /* Wait trigger enable. */ + } +#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ + + if (config->enableAutoChannelIncrement) + { + tmp32 |= ADC_CMDH_LWI_MASK; + } + base->CMD[commandId].CMDH = tmp32; + + /* Hardware compare settings. + * Not all Command Buffers have an associated Compare Value register. The compare function is only available on + * Command Buffers that have a corresponding Compare Value register. Therefore, assertion judgment needs to be + * made before setting the CV register. + */ + + if ((kLPADC_HardwareCompareDisabled != config->hardwareCompareMode) && (commandId < ADC_CV_COUNT)) + { + /* Set CV register. */ + base->CV[commandId] = (ADC_CV_CVH(config->hardwareCompareValueHigh) /* Compare value high. */ + | ADC_CV_CVL(config->hardwareCompareValueLow)); /* Compare value low. */ + } +} + +/*! + * brief Gets an available pre-defined settings for conversion command's configuration. + * + * This function initializes the conversion command's configuration structure with an available settings. The default + * values are: + * code + * config->sampleScaleMode = kLPADC_SampleFullScale; + * config->channelBScaleMode = kLPADC_SampleFullScale; + * config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; + * config->channelNumber = 0U; + * config->channelBNumber = 0U; + * config->chainedNextCommandNumber = 0U; + * config->enableAutoChannelIncrement = false; + * config->loopCount = 0U; + * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; + * config->sampleTimeMode = kLPADC_SampleTimeADCK3; + * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; + * config->hardwareCompareValueHigh = 0U; + * config->hardwareCompareValueLow = 0U; + * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; + * config->enableWaitTrigger = false; + * config->enableChannelB = false; + * endcode + * param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config) +{ + assert(config != NULL); /* Check if the input pointer is available. */ + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE + config->sampleScaleMode = kLPADC_SampleFullScale; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE + config->channelBScaleMode = kLPADC_SampleFullScale; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE */ + config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; + config->channelNumber = 0U; +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH + config->channelBNumber = 0U; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE */ + config->chainedNextCommandNumber = 0U; /* No next command defined. */ + config->enableAutoChannelIncrement = false; + config->loopCount = 0U; + config->hardwareAverageMode = kLPADC_HardwareAverageCount1; + config->sampleTimeMode = kLPADC_SampleTimeADCK3; + config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; + config->hardwareCompareValueHigh = 0U; /* No used. */ + config->hardwareCompareValueLow = 0U; /* No used. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE + config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG + config->enableWaitTrigger = false; +#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN) && FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN + config->enableChannelB = false; /* Enable alternate channel B.*/ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN */ +} + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS +/*! + * brief Enable the calibration function. + * + * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes + * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value + * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- + * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the + * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. + * + * param base LPADC peripheral base address. + * param enable switcher to the calibration function. + */ +void LPADC_EnableCalibration(ADC_Type *base, bool enable) +{ + LPADC_Enable(base, false); + if (enable) + { + base->CFG |= ADC_CFG_CALOFS_MASK; + } + else + { + base->CFG &= ~ADC_CFG_CALOFS_MASK; + } + LPADC_Enable(base, true); +} + +#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM +/*! + * brief Do auto calibration. + * + * Calibration function should be executed before using converter in application. It used the software trigger and a + * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API + * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) + * -LPADC_SetConvTriggerConfig(...) + * + * param base LPADC peripheral base address. + */ +void LPADC_DoAutoCalibration(ADC_Type *base) +{ + assert(0u == LPADC_GetConvResultCount(base)); + + uint32_t mLpadcCMDL; + uint32_t mLpadcCMDH; + uint32_t mLpadcTrigger; + lpadc_conv_trigger_config_t mLpadcTriggerConfigStruct; + lpadc_conv_command_config_t mLpadcCommandConfigStruct; + lpadc_conv_result_t mLpadcResultConfigStruct; + + /* Enable the calibration function. */ + LPADC_EnableCalibration(base, true); + + /* Keep the CMD and TRG state here and restore it later if the calibration completes.*/ + mLpadcCMDL = base->CMD[0].CMDL; /* CMD1L. */ + mLpadcCMDH = base->CMD[0].CMDH; /* CMD1H. */ + mLpadcTrigger = base->TCTRL[0]; /* Trigger0. */ + + /* Set trigger0 configuration - for software trigger. */ + LPADC_GetDefaultConvTriggerConfig(&mLpadcTriggerConfigStruct); + mLpadcTriggerConfigStruct.targetCommandId = 1U; /* CMD1 is executed. */ + LPADC_SetConvTriggerConfig(base, 0U, &mLpadcTriggerConfigStruct); /* Configurate the trigger0. */ + + /* Set conversion CMD configuration. */ + LPADC_GetDefaultConvCommandConfig(&mLpadcCommandConfigStruct); + mLpadcCommandConfigStruct.hardwareAverageMode = kLPADC_HardwareAverageCount128; + LPADC_SetConvCommandConfig(base, 1U, &mLpadcCommandConfigStruct); /* Set CMD1 configuration. */ + + /* Do calibration. */ + LPADC_DoSoftwareTrigger(base, 1U); /* 1U is trigger0 mask. */ + while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct)) + { + } + /* The valid bits of data are bits 14:3 in the RESFIFO register. */ + LPADC_SetOffsetValue(base, (uint32_t)(mLpadcResultConfigStruct.convValue) >> 3UL); + /* Disable the calibration function. */ + LPADC_EnableCalibration(base, false); + + /* restore CMD and TRG registers. */ + base->CMD[0].CMDL = mLpadcCMDL; /* CMD1L. */ + base->CMD[0].CMDH = mLpadcCMDH; /* CMD1H. */ + base->TCTRL[0] = mLpadcTrigger; /* Trigger0. */ +} +#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS +/*! + * brief Do offset calibration. + * + * param base LPADC peripheral base address. + */ +void LPADC_DoOffsetCalibration(ADC_Type *base) +{ + LPADC_EnableOffsetCalibration(base, true); + while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) + { + } +} + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ +/*! + * brief Do auto calibration. + * + * param base LPADC peripheral base address. + */ +void LPADC_DoAutoCalibration(ADC_Type *base) +{ + LPADC_PrepareAutoCalibration(base); + LPADC_FinishAutoCalibration(base); +} + +/*! + * brief Prepare auto calibration, LPADC_FinishAutoCalibration has to be called before using the LPADC. + * LPADC_DoAutoCalibration has been split in two API to avoid to be stuck too long in the function. + * + * param base LPADC peripheral base address. + */ +void LPADC_PrepareAutoCalibration(ADC_Type *base) +{ +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + assert((0U == LPADC_GetConvResultCount(base, 0)) && (0U == LPADC_GetConvResultCount(base, 1))); +#else /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 1)) */ + assert(LPADC_GetConvResultCount(base) == 0U); +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) */ + + /* Request gain calibration. */ + base->CTRL |= ADC_CTRL_CAL_REQ_MASK; +} + +/*! + * brief Finish auto calibration start with LPADC_PrepareAutoCalibration. + * + * param base LPADC peripheral base address. + */ +void LPADC_FinishAutoCalibration(ADC_Type *base) +{ +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE + int32_t GCCa; + int32_t GCCb; + float GCRa; + float GCRb; +#else + uint32_t GCCa; + float GCRa; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + uint32_t GCCb; + float GCRb; +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ + + while ((ADC_GCC_RDY_MASK != (base->GCC[0] & ADC_GCC_RDY_MASK)) +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + || (ADC_GCC_RDY_MASK != (base->GCC[1] & ADC_GCC_RDY_MASK)) +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ + ) + { + } + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE + GCCa = (int32_t)(base->GCC[0] & ADC_GCC_GAIN_CAL_MASK); + GCCb = (int32_t)(base->GCC[1] & ADC_GCC_GAIN_CAL_MASK); + if (0U != ((base->GCC[0]) & 0x8000U)) + { + GCCa = GCCa - 0x10000; + GCRa = (float)((131072.0) / + (131072.0 - (double)GCCa)); /* Gain_CalA = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[0]))*/ + base->GCR[0] = LPADC_GetGainConvResult(GCRa); /* write A side GCALR. */ + } + + if (0U != ((base->GCC[1]) & 0x8000U)) + { + GCCb = GCCb - 0x10000; + GCRb = (float)((131072.0) / + (131072.0 - (double)GCCb)); /* Gain_CalB = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[1]))*/ + base->GCR[1] = LPADC_GetGainConvResult(GCRb); /* write B side GCALR. */ + } +#else + /* Calculate gain offset. */ + GCCa = (base->GCC[0] & ADC_GCC_GAIN_CAL_MASK); + GCRa = (float)((131072.0) / + (131072.0 - (double)GCCa)); /* Gain_CalA = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[0]))*/ + base->GCR[0] = LPADC_GetGainConvResult(GCRa); /* write A side GCALR. */ + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + GCCb = (base->GCC[1] & ADC_GCC_GAIN_CAL_MASK); + GCRb = (float)((131072.0) / + (131072.0 - (double)GCCb)); /* Gain_CalB = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[1]))*/ + base->GCR[1] = LPADC_GetGainConvResult(GCRb); /* write B side GCALR. */ +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ + /* Indicate the values are valid. */ + base->GCR[0] |= ADC_GCR_RDY_MASK; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + base->GCR[1] |= ADC_GCR_RDY_MASK; +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ + + while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) + { + } +} +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ + +/*! + * brief Get calibration value into the memory which is defined by invoker. + * + * note Please note the ADC will be disabled temporary. + * note This function should be used after finish calibration. + * + * param base LPADC peripheral base address. + * param ptrCalibrationValue Pointer to lpadc_calibration_value_t structure, this memory block should be always powered + * on even in low power modes. + */ +void LPADC_GetCalibrationValue(ADC_Type *base, lpadc_calibration_value_t *ptrCalibrationValue) +{ + assert(ptrCalibrationValue != NULL); + + bool adcEnabled = false; + + /* Check if ADC is enabled. */ + if ((base->CTRL & ADC_CTRL_ADCEN_MASK) != 0UL) + { + LPADC_Enable(base, false); + adcEnabled = true; + } + +#if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) + uint32_t i; + for (i = 0UL; i < 33UL; i++) + { +#if defined(ADC_CAL_GAR0_CAL_GAR_VAL_MASK) + ptrCalibrationValue->generalCalibrationValueA[i] = + (uint16_t)((*(((volatile uint32_t *)(&(base->CAL_GAR0))) + i)) & 0xFFFFU); +#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) + ptrCalibrationValue->generalCalibrationValueB[i] = + (uint16_t)((*(((volatile uint32_t *)(&(base->CAL_GBR0))) + i)) & 0xFFFFU); +#endif /* (defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */ +#else + ptrCalibrationValue->generalCalibrationValueA[i] = + (uint16_t)((*(((volatile uint32_t *)(&(base->CAL_GAR[0]))) + i)) & 0xFFFFU); +#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) + ptrCalibrationValue->generalCalibrationValueB[i] = + (uint16_t)((*(((volatile uint32_t *)(&(base->CAL_GBR[0]))) + i)) & 0xFFFFU); +#endif /* (defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */ + +#endif /* defined(ADC_CAL_GAR0_CAL_GAR_VAL_MASK) */ + } +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ + + ptrCalibrationValue->gainCalibrationResultA = (uint16_t)(base->GCR[0] & ADC_GCR_GCALR_MASK); +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + ptrCalibrationValue->gainCalibrationResultB = (uint16_t)(base->GCR[1] & ADC_GCR_GCALR_MASK); +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ + + if (adcEnabled) + { + LPADC_Enable(base, true); + } +} + +/*! + * brief Set calibration value into ADC calibration registers. + * + * note Please note the ADC will be disabled temporary. + * + * param base LPADC peripheral base address. + * param ptrCalibrationValue Pointer to lpadc_calibration_value_t structure which contains ADC's calibration value. + */ +void LPADC_SetCalibrationValue(ADC_Type *base, const lpadc_calibration_value_t *ptrCalibrationValue) +{ + assert(ptrCalibrationValue != NULL); + + bool adcEnabled = false; + + /* Check if ADC is enabled. */ + if ((base->CTRL & ADC_CTRL_ADCEN_MASK) != 0UL) + { + LPADC_Enable(base, false); + adcEnabled = true; + } + +#if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) + for (uint32_t i = 0UL; i < 33UL; i++) + { +#if defined(ADC_CAL_GAR0_CAL_GAR_VAL_MASK) + *(((volatile uint32_t *)(&(base->CAL_GAR0))) + i) = ptrCalibrationValue->generalCalibrationValueA[i]; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + *(((volatile uint32_t *)(&(base->CAL_GBR0))) + i) = ptrCalibrationValue->generalCalibrationValueB[i]; +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ +#else + *(((volatile uint32_t *)(&(base->CAL_GAR[0]))) + i) = ptrCalibrationValue->generalCalibrationValueA[i]; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + *(((volatile uint32_t *)(&(base->CAL_GBR[0]))) + i) = ptrCalibrationValue->generalCalibrationValueB[i]; +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ +#endif /* defined(ADC_CAL_GAR0_CAL_GAR_VAL_MASK) */ + } +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ + + base->GCR[0] = ADC_GCR_GCALR(ptrCalibrationValue->gainCalibrationResultA) | ADC_GCR_RDY_MASK; +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + base->GCR[1] = ADC_GCR_GCALR(ptrCalibrationValue->gainCalibrationResultB) | ADC_GCR_RDY_MASK; +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ + /* + * $Branch Coverage Justification$ + * while ((base->STAT & ADC_STAT_CAL_RDY_MASK) == ADC_STAT_CAL_RDY_MASK) not covered. Test unfeasible, + * the calibration ready state is too short not to catch. + */ + while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK)) + { + } + + if (adcEnabled) + { + LPADC_Enable(base, true); + } +} + +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpadc.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpadc.h new file mode 100644 index 00000000000..e0d2f4b6ee4 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpadc.h @@ -0,0 +1,1529 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LPADC_H_ +#define FSL_LPADC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpadc + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief LPADC driver version 2.8.4. */ +#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 8, 4)) +/*! @} */ + +#if (defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) && (FSL_FEATURE_LPADC_OFSTRIM_COUNT == 1)) +#define ADC_OFSTRIM_OFSTRIM_MAX (ADC_OFSTRIM_OFSTRIM_MASK >> ADC_OFSTRIM_OFSTRIM_SHIFT) +#define ADC_OFSTRIM_OFSTRIM_SIGN ((ADC_OFSTRIM_OFSTRIM_MAX + 1U) >> 1U) + +#elif (defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) && (FSL_FEATURE_LPADC_OFSTRIM_COUNT == 2)) +#define ADC_OFSTRIM_OFSTRIM_A_MAX (ADC_OFSTRIM_OFSTRIM_A_MASK >> ADC_OFSTRIM_OFSTRIM_A_SHIFT) +#define ADC_OFSTRIM_OFSTRIM_B_MAX (ADC_OFSTRIM_OFSTRIM_B_MASK >> ADC_OFSTRIM_OFSTRIM_B_SHIFT) +#define ADC_OFSTRIM_OFSTRIM_A_SIGN ((ADC_OFSTRIM_OFSTRIM_A_MAX + 1U) >> 1U) +#define ADC_OFSTRIM_OFSTRIM_B_SIGN ((ADC_OFSTRIM_OFSTRIM_B_MAX + 1U) >> 1U) +#endif /* defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) */ + +/*! + * @brief Define the MACRO function to get command status from status value. + * + * The statusVal is the return value from LPADC_GetStatusFlags(). + */ +#define LPADC_GET_ACTIVE_COMMAND_STATUS(statusVal) ((statusVal & ADC_STAT_CMDACT_MASK) >> ADC_STAT_CMDACT_SHIFT) + +/*! + * @brief Define the MACRO function to get trigger status from status value. + * + * The statusVal is the return value from LPADC_GetStatusFlags(). + */ +#define LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal) ((statusVal & ADC_STAT_TRGACT_MASK) >> ADC_STAT_TRGACT_SHIFT) + +/* Map macros to the unified name. */ +#if !defined(ADC_STAT_FOF0_MASK) +#ifdef ADC_STAT_FOF_MASK +#define ADC_STAT_FOF0_MASK ADC_STAT_FOF_MASK +#else +#error "ADC_STAT_FOF0_MASK not defined" +#endif /* ifdef(ADC_STAT_FOF_MASK) */ +#endif /* !defined(ADC_STAT_FOF0_MASK) */ + +#if !defined(ADC_STAT_RDY0_MASK) +#ifdef ADC_STAT_RDY_MASK +#define ADC_STAT_RDY0_MASK ADC_STAT_RDY_MASK +#else +#error "ADC_STAT_RDY0_MASK not defined" +#endif /* ifdef ADC_STAT_RDY_MASK */ +#endif /* !defined(ADC_STAT_RDY0_MASK) */ + +#if !defined(ADC_IE_FOFIE0_MASK) +#ifdef ADC_IE_FOFIE_MASK +#define ADC_IE_FOFIE0_MASK ADC_IE_FOFIE_MASK +#else +#error "ADC_IE_FOFIE0_MASK not defined" +#endif /* ifdef ADC_IE_FOFIE_MASK */ +#endif /* !defined(ADC_IE_FOFIE0_MASK) */ + +#if !defined(ADC_IE_FWMIE0_MASK) +#ifdef ADC_IE_FWMIE_MASK +#define ADC_IE_FWMIE0_MASK ADC_IE_FWMIE_MASK +#else +#error "ADC_IE_FWMIE0_MASK not defined" +#endif /* ifdef ADC_IE_FWMIE_MASK */ +#endif /* !defined(ADC_IE_FWMIE0_MASK) */ + +/*! + * @brief Define hardware flags of the module. + */ +enum _lpadc_status_flags +{ + kLPADC_ResultFIFO0OverflowFlag = ADC_STAT_FOF0_MASK, /*!< Indicates that more data has been written to the Result + FIFO 0 than it can hold. */ + kLPADC_ResultFIFO0ReadyFlag = ADC_STAT_RDY0_MASK, /*!< Indicates when the number of valid datawords in the result + FIFO 0 is greater than the setting watermark level. */ + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + kLPADC_ResultFIFO1OverflowFlag = ADC_STAT_FOF1_MASK, /*!< Indicates that more data has been written to the Result + FIFO 1 than it can hold. */ + kLPADC_ResultFIFO1ReadyFlag = ADC_STAT_RDY1_MASK, /*!< Indicates when the number of valid datawords in the result + FIFO 1 is greater than the setting watermark level. */ +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT) && (FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT == 1U)) + kLPADC_TriggerExceptionFlag = ADC_STAT_TEXC_INT_MASK, /*!< Indicates that a trigger exception event has occurred. */ +#endif /* (defined(FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT) && (FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT == 1U)) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT) && (FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT == 1U)) + kLPADC_TriggerCompletionFlag = ADC_STAT_TCOMP_INT_MASK, /*!< Indicates that a trigger completion event has occurred. + */ +#endif /* (defined(FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT) && (FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT == 1U)) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY) && (FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY == 1U)) + kLPADC_CalibrationReadyFlag = ADC_STAT_CAL_RDY_MASK, /*!< Indicates that the calibration process is done. */ +#endif /* (defined(FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY) && (FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY == 1U)) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE) && (FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE == 1U)) + kLPADC_ActiveFlag = ADC_STAT_ADC_ACTIVE_MASK, /*!< Indicates that the ADC is in active state. */ +#endif /* (defined(FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE) && (FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE == 1U)) */ + + kLPADC_ResultFIFOOverflowFlag = kLPADC_ResultFIFO0OverflowFlag, /*!< To compilitable with old version, do not + recommend using this, please use @ref + kLPADC_ResultFIFO0OverflowFlag as instead. */ + + kLPADC_ResultFIFOReadyFlag = kLPADC_ResultFIFO0ReadyFlag, /*!< To compilitable with old version, do not + recommend using this, please use @ref + kLPADC_ResultFIFO0ReadyFlag as instead. */ +}; + +/*! + * @brief Define interrupt switchers of the module. + * + * Note: LPADC of different chips supports different number of trigger sources, + * please check the Reference Manual for details. + */ +enum _lpadc_interrupt_enable +{ + kLPADC_ResultFIFO0OverflowInterruptEnable = ADC_IE_FOFIE0_MASK, /*!< Configures ADC to generate overflow interrupt + requests when FOF0 flag is asserted. */ + kLPADC_FIFO0WatermarkInterruptEnable = ADC_IE_FWMIE0_MASK, /*!< Configures ADC to generate watermark interrupt + requests when RDY0 flag is asserted. */ + kLPADC_ResultFIFOOverflowInterruptEnable = kLPADC_ResultFIFO0OverflowInterruptEnable, /*!< To compilitable with old + version, do not recommend using this, + please use + #kLPADC_ResultFIFO0OverflowInterruptEnable + as instead. */ + kLPADC_FIFOWatermarkInterruptEnable = kLPADC_FIFO0WatermarkInterruptEnable, /*!< To compilitable with old version, + do not recommend using this, please + use + #kLPADC_FIFO0WatermarkInterruptEnable + as instead. */ + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) + kLPADC_ResultFIFO1OverflowInterruptEnable = ADC_IE_FOFIE1_MASK, /*!< Configures ADC to generate overflow interrupt + requests when FOF1 flag is asserted. */ + kLPADC_FIFO1WatermarkInterruptEnable = ADC_IE_FWMIE1_MASK, /*!< Configures ADC to generate watermark interrupt + requests when RDY1 flag is asserted. */ +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_IE_TEXC_IE) && (FSL_FEATURE_LPADC_HAS_IE_TEXC_IE == 1U)) + kLPADC_TriggerExceptionInterruptEnable = ADC_IE_TEXC_IE_MASK, /*!< Configures ADC to generate trigger exception + interrupt. */ +#endif /* (defined(FSL_FEATURE_LPADC_HAS_IE_TEXC_IE) && (FSL_FEATURE_LPADC_HAS_IE_TEXC_IE == 1U)) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) + kLPADC_Trigger0CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 0UL), /*!< Configures ADC to generate interrupt + when trigger 0 completion. */ + kLPADC_Trigger1CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 1UL), /*!< Configures ADC to generate interrupt + when trigger 1 completion. */ + kLPADC_Trigger2CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 2UL), /*!< Configures ADC to generate interrupt + when trigger 2 completion. */ + kLPADC_Trigger3CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 3UL), /*!< Configures ADC to generate interrupt + when trigger 3 completion. */ + kLPADC_Trigger4CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 4UL), /*!< Configures ADC to generate interrupt + when trigger 4 completion. */ + kLPADC_Trigger5CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 5UL), /*!< Configures ADC to generate interrupt + when trigger 5 completion. */ + kLPADC_Trigger6CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 6UL), /*!< Configures ADC to generate interrupt + when trigger 6 completion. */ + kLPADC_Trigger7CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 7UL), /*!< Configures ADC to generate interrupt + when trigger 7 completion. */ + kLPADC_Trigger8CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 8UL), /*!< Configures ADC to generate interrupt + when trigger 8 completion. */ + kLPADC_Trigger9CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 9UL), /*!< Configures ADC to generate interrupt + when trigger 9 completion. */ + kLPADC_Trigger10CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 10UL), /*!< Configures ADC to generate interrupt + when trigger 10 completion. */ + kLPADC_Trigger11CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 11UL), /*!< Configures ADC to generate interrupt + when trigger 11 completion. */ + kLPADC_Trigger12CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 12UL), /*!< Configures ADC to generate interrupt + when trigger 12 completion. */ + kLPADC_Trigger13CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 13UL), /*!< Configures ADC to generate interrupt + when trigger 13 completion. */ + kLPADC_Trigger14CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 14UL), /*!< Configures ADC to generate interrupt + when trigger 14 completion. */ + kLPADC_Trigger15CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 15UL), /*!< Configures ADC to generate interrupt + when trigger 15 completion. */ +#endif /* #if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) */ +}; + +#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && (FSL_FEATURE_LPADC_HAS_TSTAT)) +/*! + * @brief The enumerator of lpadc trigger status flags, including interrupted flags and completed flags. + * + * Note: LPADC of different chips supports different number of trigger sources, + * please check the Reference Manual for details. + */ +enum _lpadc_trigger_status_flags +{ + kLPADC_Trigger0InterruptedFlag = 1UL << 0UL, /*!< Trigger 0 is interrupted by a high priority exception. */ + kLPADC_Trigger1InterruptedFlag = 1UL << 1UL, /*!< Trigger 1 is interrupted by a high priority exception. */ + kLPADC_Trigger2InterruptedFlag = 1UL << 2UL, /*!< Trigger 2 is interrupted by a high priority exception. */ + kLPADC_Trigger3InterruptedFlag = 1UL << 3UL, /*!< Trigger 3 is interrupted by a high priority exception. */ + kLPADC_Trigger4InterruptedFlag = 1UL << 4UL, /*!< Trigger 4 is interrupted by a high priority exception. */ + kLPADC_Trigger5InterruptedFlag = 1UL << 5UL, /*!< Trigger 5 is interrupted by a high priority exception. */ + kLPADC_Trigger6InterruptedFlag = 1UL << 6UL, /*!< Trigger 6 is interrupted by a high priority exception. */ + kLPADC_Trigger7InterruptedFlag = 1UL << 7UL, /*!< Trigger 7 is interrupted by a high priority exception. */ + kLPADC_Trigger8InterruptedFlag = 1UL << 8UL, /*!< Trigger 8 is interrupted by a high priority exception. */ + kLPADC_Trigger9InterruptedFlag = 1UL << 9UL, /*!< Trigger 9 is interrupted by a high priority exception. */ + kLPADC_Trigger10InterruptedFlag = 1UL << 10UL, /*!< Trigger 10 is interrupted by a high priority exception. */ + kLPADC_Trigger11InterruptedFlag = 1UL << 11UL, /*!< Trigger 11 is interrupted by a high priority exception. */ + kLPADC_Trigger12InterruptedFlag = 1UL << 12UL, /*!< Trigger 12 is interrupted by a high priority exception. */ + kLPADC_Trigger13InterruptedFlag = 1UL << 13UL, /*!< Trigger 13 is interrupted by a high priority exception. */ + kLPADC_Trigger14InterruptedFlag = 1UL << 14UL, /*!< Trigger 14 is interrupted by a high priority exception. */ + kLPADC_Trigger15InterruptedFlag = 1UL << 15UL, /*!< Trigger 15 is interrupted by a high priority exception. */ + + kLPADC_Trigger0CompletedFlag = 1UL << 16UL, /*!< Trigger 0 is completed and + trigger 0 has enabled completion interrupts. */ + kLPADC_Trigger1CompletedFlag = 1UL << 17UL, /*!< Trigger 1 is completed and + trigger 1 has enabled completion interrupts. */ + kLPADC_Trigger2CompletedFlag = 1UL << 18UL, /*!< Trigger 2 is completed and + trigger 2 has enabled completion interrupts. */ + kLPADC_Trigger3CompletedFlag = 1UL << 19UL, /*!< Trigger 3 is completed and + trigger 3 has enabled completion interrupts. */ + kLPADC_Trigger4CompletedFlag = 1UL << 20UL, /*!< Trigger 4 is completed and + trigger 4 has enabled completion interrupts. */ + kLPADC_Trigger5CompletedFlag = 1UL << 21UL, /*!< Trigger 5 is completed and + trigger 5 has enabled completion interrupts. */ + kLPADC_Trigger6CompletedFlag = 1UL << 22UL, /*!< Trigger 6 is completed and + trigger 6 has enabled completion interrupts. */ + kLPADC_Trigger7CompletedFlag = 1UL << 23UL, /*!< Trigger 7 is completed and + trigger 7 has enabled completion interrupts. */ + kLPADC_Trigger8CompletedFlag = 1UL << 24UL, /*!< Trigger 8 is completed and + trigger 8 has enabled completion interrupts. */ + kLPADC_Trigger9CompletedFlag = 1UL << 25UL, /*!< Trigger 9 is completed and + trigger 9 has enabled completion interrupts. */ + kLPADC_Trigger10CompletedFlag = 1UL << 26UL, /*!< Trigger 10 is completed and + trigger 10 has enabled completion interrupts. */ + kLPADC_Trigger11CompletedFlag = 1UL << 27UL, /*!< Trigger 11 is completed and + trigger 11 has enabled completion interrupts. */ + kLPADC_Trigger12CompletedFlag = 1UL << 28UL, /*!< Trigger 12 is completed and + trigger 12 has enabled completion interrupts. */ + kLPADC_Trigger13CompletedFlag = 1UL << 29UL, /*!< Trigger 13 is completed and + trigger 13 has enabled completion interrupts. */ + kLPADC_Trigger14CompletedFlag = 1UL << 30UL, /*!< Trigger 14 is completed and + trigger 14 has enabled completion interrupts. */ + kLPADC_Trigger15CompletedFlag = 1UL << 31UL, /*!< Trigger 15 is completed and + trigger 15 has enabled completion interrupts. */ +}; +#endif /* (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && (FSL_FEATURE_LPADC_HAS_TSTAT)) */ + +/*! + * @brief Define enumeration of sample scale mode. + * + * The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum + * possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the + * reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows + * conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode. + */ +typedef enum _lpadc_sample_scale_mode +{ + kLPADC_SamplePartScale = 0U, /*!< Use divided input voltage signal. + (For scale select,please refer to the reference manual). */ + kLPADC_SampleFullScale = 1U, /*!< Full scale (Factor of 1). */ +} lpadc_sample_scale_mode_t; + +/*! + * @brief Define enumeration of channel sample mode. + * + * The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B. + */ +typedef enum _lpadc_sample_channel_mode +{ + kLPADC_SampleChannelSingleEndSideA = 0x0U, /*!< Single-end mode, only A-side channel is converted. */ +#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) + kLPADC_SampleChannelSingleEndSideB = 0x1U, /*!< Single-end mode, only B-side channel is converted. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF + kLPADC_SampleChannelDiffBothSideAB = 0x2U, /*!< Differential mode, the ADC result is (CHnA-CHnB). */ + kLPADC_SampleChannelDiffBothSideBA = 0x3U, /*!< Differential mode, the ADC result is (CHnB-CHnA). */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE + kLPADC_SampleChannelDiffBothSide = 0x02U, /*!< Differential mode, the ADC result is (CHnA-CHnB). */ + kLPADC_SampleChannelDualSingleEndBothSide = 0x03U, /*!< Dual-Single-Ended Mode. Both A side and B side + channels are converted independently. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */ +#endif /* !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */ +} lpadc_sample_channel_mode_t; + +/*! + * @brief Define enumeration of hardware average selection. + * + * It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to + * capture temporary results while the averaging iterations are executed. + * + * @note Some enumerator values are not available on some devices, mainly depends on the size of AVGS field in CMDH + * register. + */ +typedef enum _lpadc_hardware_average_mode +{ + kLPADC_HardwareAverageCount1 = 0U, /*!< Single conversion. */ + kLPADC_HardwareAverageCount2 = 1U, /*!< 2 conversions averaged. */ + kLPADC_HardwareAverageCount4 = 2U, /*!< 4 conversions averaged. */ + kLPADC_HardwareAverageCount8 = 3U, /*!< 8 conversions averaged. */ + kLPADC_HardwareAverageCount16 = 4U, /*!< 16 conversions averaged. */ + kLPADC_HardwareAverageCount32 = 5U, /*!< 32 conversions averaged. */ + kLPADC_HardwareAverageCount64 = 6U, /*!< 64 conversions averaged. */ + kLPADC_HardwareAverageCount128 = 7U, /*!< 128 conversions averaged. */ +#if (defined(FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH) && \ + (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4U)) + kLPADC_HardwareAverageCount256 = 8U, /*!< 256 conversions averaged. */ + kLPADC_HardwareAverageCount512 = 9U, /*!< 512 conversions averaged. */ + kLPADC_HardwareAverageCount1024 = 10U, /*!< 1024 conversions averaged. */ +#endif /* (defined(FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH) && \ + (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4U))*/ +} lpadc_hardware_average_mode_t; + +/*! + * @brief Define enumeration of sample time selection. + * + * The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher + * impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption + * when command looping and sequencing is configured and high conversion rates are not required. + */ +typedef enum _lpadc_sample_time_mode +{ + kLPADC_SampleTimeADCK3 = 0U, /*!< 3 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK5 = 1U, /*!< 5 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK7 = 2U, /*!< 7 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK11 = 3U, /*!< 11 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK19 = 4U, /*!< 19 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK35 = 5U, /*!< 35 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK67 = 6U, /*!< 69 ADCK cycles total sample time. */ + kLPADC_SampleTimeADCK131 = 7U, /*!< 131 ADCK cycles total sample time. */ +} lpadc_sample_time_mode_t; + +/*! + * @brief Define enumeration of hardware compare mode. + * + * After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting + * guides operation of the automatic compare function to optionally only store when the compare operation is true. + * When compare is enabled, the conversion result is compared to the compare values. + */ +typedef enum _lpadc_hardware_compare_mode +{ + kLPADC_HardwareCompareDisabled = 0U, /*!< Compare disabled. */ + kLPADC_HardwareCompareStoreOnTrue = 2U, /*!< Compare enabled. Store on true. */ + kLPADC_HardwareCompareRepeatUntilTrue = 3U, /*!< Compare enabled. Repeat channel acquisition until true. */ +} lpadc_hardware_compare_mode_t; + +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE +/*! + * @brief Define enumeration of conversion resolution mode. + * + * Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to + * #lpadc_sample_channel_mode_t + */ +typedef enum _lpadc_conversion_resolution_mode +{ + kLPADC_ConversionResolutionStandard = 0U, /*!< Standard resolution. Single-ended 12-bit conversion, Differential + 13-bit conversion with 2's complement output. */ + kLPADC_ConversionResolutionHigh = 1U, /*!< High resolution. Single-ended 16-bit conversion; Differential 16-bit + conversion with 2's complement output. */ +} lpadc_conversion_resolution_mode_t; +#endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE */ + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS +/*! + * @brief Define enumeration of conversion averages mode. + * + * Configure the converion average number for auto-calibration. + * @note Some enumerator values are not available on some devices, mainly depends on the size of CAL_AVGS field in CTRL + * register. + */ +typedef enum _lpadc_conversion_average_mode +{ + kLPADC_ConversionAverage1 = 0U, /*!< Single conversion. */ + kLPADC_ConversionAverage2 = 1U, /*!< 2 conversions averaged. */ + kLPADC_ConversionAverage4 = 2U, /*!< 4 conversions averaged. */ + kLPADC_ConversionAverage8 = 3U, /*!< 8 conversions averaged. */ + kLPADC_ConversionAverage16 = 4U, /*!< 16 conversions averaged. */ + kLPADC_ConversionAverage32 = 5U, /*!< 32 conversions averaged. */ + kLPADC_ConversionAverage64 = 6U, /*!< 64 conversions averaged. */ + kLPADC_ConversionAverage128 = 7U, /*!< 128 conversions averaged. */ +#if (defined(FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH) && \ + (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4U)) + kLPADC_ConversionAverage256 = 8U, /*!< 256 conversions averaged. */ + kLPADC_ConversionAverage512 = 9U, /*!< 512 conversions averaged. */ + kLPADC_ConversionAverage1024 = 10U, /*!< 1024 conversions averaged. */ +#endif /* (defined(FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH) && \ + (FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH == 4U))*/ +} lpadc_conversion_average_mode_t; +#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ + +/*! + * @brief Define enumeration of reference voltage source. + * + * For detail information, need to check the SoC's specification. + */ +typedef enum _lpadc_reference_voltage_mode +{ + kLPADC_ReferenceVoltageAlt1 = 0U, /*!< Option 1 setting. */ + kLPADC_ReferenceVoltageAlt2 = 1U, /*!< Option 2 setting. */ + kLPADC_ReferenceVoltageAlt3 = 2U, /*!< Option 3 setting. */ +} lpadc_reference_voltage_source_t; + +/*! + * @brief Define enumeration of power configuration. + * + * Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be + * possible. Refer to the device data sheet for power and performance capabilities for each setting. + */ +typedef enum _lpadc_power_level_mode +{ + kLPADC_PowerLevelAlt1 = 0U, /*!< Lowest power setting. */ + kLPADC_PowerLevelAlt2 = 1U, /*!< Next lowest power setting. */ + kLPADC_PowerLevelAlt3 = 2U, /*!< ... */ + kLPADC_PowerLevelAlt4 = 3U, /*!< Highest power setting. */ +} lpadc_power_level_mode_t; + +#if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) +/*! + * @brief Define enumeration of offset calibration mode. + * + */ +typedef enum _lpadc_offset_calibration_mode +{ + kLPADC_OffsetCalibration12bitMode = 0U, /*!< 12 bit offset calibration mode. */ + kLPADC_OffsetCalibration16bitMode = 1U, /*!< 16 bit offset calibration mode. */ +} lpadc_offset_calibration_mode_t; +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ + +/*! + * @brief Define enumeration of trigger priority policy. + * + * This selection controls how higher priority triggers are handled. + * @note \b kLPADC_TriggerPriorityPreemptSubsequently is not available on some devices, mainly depends on the size of + * TPRICTRL field in CFG register. + */ +typedef enum _lpadc_trigger_priority_policy +{ + kLPADC_ConvPreemptImmediatelyNotAutoResumed = 0x0U, /*!< If a higher priority trigger is detected during command + processing, the current conversion is aborted and the new + command specified by the trigger is started, when higher + priority conversion finishes, the preempted conversion is not + automatically resumed or restarted. */ + kLPADC_ConvPreemptSoftlyNotAutoResumed = 0x1U, /*!< If a higher priority trigger is received during command + processing, the current conversion is completed (including averaging + iterations and compare function if enabled) and stored to the result + FIFO before the higher priority trigger/command is initiated, when + higher priority conversion finishes, the preempted conversion is not + resumed or restarted. */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES + kLPADC_ConvPreemptImmediatelyAutoRestarted = 0x4U, /*!< If a higher priority trigger is detected during command + processing, the current conversion is aborted and the new + command specified by the trigger is started, when higher + priority conversion finishes, the preempted conversion will + automatically be restarted. */ + kLPADC_ConvPreemptSoftlyAutoRestarted = 0x5U, /*!< If a higher priority trigger is received during command + processing, the current conversion is completed (including averaging + iterations and compare function if enabled) and stored to the result + FIFO before the higher priority trigger/command is initiated, when + higher priority conversion finishes, the preempted conversion will + automatically be restarted. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES + kLPADC_ConvPreemptImmediatelyAutoResumed = 0xCU, /*!< If a higher priority trigger is detected during command + processing, the current conversion is aborted and the new + command specified by the trigger is started, when higher + priority conversion finishes, the preempted conversion will + automatically be resumed. */ + kLPADC_ConvPreemptSoftlyAutoResumed = 0xDU, /*!< If a higher priority trigger is received during command + processing, the current conversion is completed (including averaging + iterations and compare function if enabled) and stored to the result + FIFO before the higher priority trigger/command is initiated, when + higher priority conversion finishes, the preempted conversion will + be automatically be resumed. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES */ + + kLPADC_TriggerPriorityPreemptImmediately = + kLPADC_ConvPreemptImmediatelyNotAutoResumed, /*!< Legacy support is not recommended as it only ensures + compatibility with older versions. */ + kLPADC_TriggerPriorityPreemptSoftly = + kLPADC_ConvPreemptSoftlyNotAutoResumed, /*!< Legacy support is not recommended as it only ensures compatibility + with older versions. */ + +#if (defined(FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH) && (FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH == 2U)) + kLPADC_ConvPreemptSubsequentlyNotAutoResumed = 0x2U, /*!< If a higher priority trigger is received during command + processing, the current command will be completed (averaging, + looping, compare) before servicing the higher priority trigger, when + higher priority conversion finishes, the preempted conversion will + not automatically be restarted or resumed. */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES + kLPADC_ConvPreemptSubsequentlyAutoRestarted = 0x6U, /*!< If a higher priority trigger is received during command + processing, the current command will be completed (averaging, + looping, compare) before servicing the higher priority trigger, when + higher priority conversion finishes, the preempted conversion will + be automatically restarted. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES + kLPADC_ConvPreemptSubsequentlyAutoResumed = 0xEU, /*!< If a higher priority trigger is received during command + processing, the current command will be completed (averaging, + looping, compare) before servicing the higher priority trigger, when + higher priority conversion finishes, the preempted conversion will + be automatically resumed. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES */ + + kLPADC_TriggerPriorityPreemptSubsequently = + kLPADC_ConvPreemptSubsequentlyNotAutoResumed, /*!< Legacy support is not recommended as it only ensures + compatibility with older versions. */ +#endif /* #if (defined(FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH) && \ + (FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH == 2U)) */ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI + kLPADC_TriggerPriorityExceptionDisabled = 0x10U, /*!< High priority trigger exception disabled. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI */ +} lpadc_trigger_priority_policy_t; + +#if ((defined(FSL_FEATURE_LPADC_HAS_CTRL_CALHS)) && FSL_FEATURE_LPADC_HAS_CTRL_CALHS) +/*! + * @brief Define enumeration of tune value. + */ +typedef enum _lpadc_tune_value +{ + kLPADC_TuneValue0 = 0U, /*!< Tune value 0. */ + kLPADC_TuneValue1 = 1U, /*!< Tune value 1. */ + kLPADC_TuneValue2 = 2U, /*!< Tune value 2. */ + kLPADC_TuneValue3 = 3U, /*!< Tune value 3. */ +} lpadc_tune_value_t; +#endif /* ((defined(FSL_FEATURE_LPADC_HAS_CTRL_CALHS)) && FSL_FEATURE_LPADC_HAS_CTRL_CALHS) */ + +/*! + * @brief LPADC global configuration. + * + * This structure would used to keep the settings for initialization. + */ +typedef struct +{ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN + bool enableInternalClock; /*!< Enables the internally generated clock source. The clock source is used in clock + selection logic at the chip level and is optionally used for the ADC clock source. */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */ +#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG + bool enableVref1LowVoltage; /*!< If voltage reference option1 input is below 1.8V, it should be "true". + If voltage reference option1 input is above 1.8V, it should be "false". */ +#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */ + bool enableInDozeMode; /*!< Control system transition to Stop and Wait power modes while ADC is converting. When + enabled in Doze mode, immediate entries to Wait or Stop are allowed. When disabled, the + ADC will wait for the current averaging iteration/FIFO storage to complete before + acknowledging stop or wait mode entry. */ +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS + lpadc_conversion_average_mode_t conversionAverageMode; /*!< Auto-Calibration Averages. */ +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */ + bool enableAnalogPreliminary; /*!< ADC analog circuits are pre-enabled and ready to execute conversions without + startup delays(at the cost of higher DC current consumption). */ + uint32_t powerUpDelay; /*!< When the analog circuits are not pre-enabled, the ADC analog circuits are only powered + while the ADC is active and there is a counted delay defined by this field after an + initial trigger transitions the ADC from its Idle state to allow time for the analog + circuits to stabilize. The startup delay count of (powerUpDelay * 4) ADCK cycles must + result in a longer delay than the analog startup time. */ + lpadc_reference_voltage_source_t referenceVoltageSource; /*!< Selects the voltage reference high used for + conversions.*/ + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) + lpadc_power_level_mode_t powerLevelMode; /*!< Power Configuration Selection. */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) */ + lpadc_trigger_priority_policy_t triggerPriorityPolicy; /*!< Control how higher priority triggers are handled, see to + lpadc_trigger_priority_policy_t. */ + bool enableConvPause; /*!< Enables the ADC pausing function. When enabled, a programmable delay is inserted during + command execution sequencing between LOOP iterations, between commands in a sequence, and + between conversions when command is executing in "Compare Until True" configuration. */ + uint32_t convPauseDelay; /*!< Controls the duration of pausing during command execution sequencing. The pause delay + is a count of (convPauseDelay*4) ADCK cycles. Only available when ADC pausing + function is enabled. The available value range is in 9-bit. */ +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + /* for FIFO0. */ + uint32_t FIFO0Watermark; /*!< FIFO0Watermark is a programmable threshold setting. When the number of datawords + stored in the ADC Result FIFO0 is greater than the value in this field, the ready flag + would be asserted to indicate stored data has reached the programmable threshold. */ + /* for FIFO1. */ + uint32_t FIFO1Watermark; /*!< FIFO1Watermark is a programmable threshold setting. When the number of datawords + stored in the ADC Result FIFO1 is greater than the value in this field, the ready flag + would be asserted to indicate stored data has reached the programmable threshold. */ +#else + /* for FIFO. */ + uint32_t FIFOWatermark; /*!< FIFOWatermark is a programmable threshold setting. When the number of datawords stored + in the ADC Result FIFO is greater than the value in this field, the ready flag would be + asserted to indicate stored data has reached the programmable threshold. */ +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ +#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && (FSL_FEATURE_LPADC_HAS_TSTAT)) + +#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ +} lpadc_config_t; + +/*! + * @brief Define structure to keep the configuration for conversion command. + */ +typedef struct +{ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE + lpadc_sample_scale_mode_t sampleScaleMode; /*!< Sample scale mode. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE + lpadc_sample_scale_mode_t channelBScaleMode; /*!< Alternate channe B Scale mode. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE */ + lpadc_sample_channel_mode_t sampleChannelMode; /*!< Channel sample mode. */ + uint32_t channelNumber; /*!< Channel number, select the channel or channel pair. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH + uint32_t channelBNumber; /*!< Alternate Channel B number, select the channel. */ +#endif + uint32_t chainedNextCommandNumber; /*!< Selects the next command to be executed after this command completes. + 1-15 is available, 0 is to terminate the chain after this command. */ + bool enableAutoChannelIncrement; /*!< Loop with increment: when disabled, the "loopCount" field selects the number + of times the selected channel is converted consecutively; when enabled, the + "loopCount" field defines how many consecutive channels are converted as part + of the command execution. */ + uint32_t loopCount; /*!< Selects how many times this command executes before finish and transition to the next + command or Idle state. Command executes LOOP+1 times. 0-15 is available. */ + lpadc_hardware_average_mode_t hardwareAverageMode; /*!< Hardware average selection. */ + lpadc_sample_time_mode_t sampleTimeMode; /*!< Sample time selection. */ + + lpadc_hardware_compare_mode_t hardwareCompareMode; /*!< Hardware compare selection. */ + uint32_t hardwareCompareValueHigh; /*!< Compare Value High. The available value range is in 16-bit. */ + uint32_t hardwareCompareValueLow; /*!< Compare Value Low. The available value range is in 16-bit. */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE + lpadc_conversion_resolution_mode_t conversionResolutionMode; /*!< Conversion resolution mode. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG + bool enableWaitTrigger; /*!< Wait for trigger assertion before execution: when disabled, this command will be + automatically executed; when enabled, the active trigger must be asserted again before + executing this command. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */ +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN) && FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN + bool enableChannelB; /*! Enable alternate Channel B */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN */ +} lpadc_conv_command_config_t; + +/*! + * @brief Define structure to keep the configuration for conversion trigger. + */ +typedef struct +{ + uint32_t targetCommandId; /*!< Select the command from command buffer to execute upon detect of the associated + trigger event. */ + uint32_t delayPower; /*!< Select the trigger delay duration to wait at the start of servicing a trigger event. + When this field is clear, then no delay is incurred. When this field is set to a non-zero + value, the duration for the delay is 2^delayPower ADCK cycles. The available value range + is 4-bit. */ + uint32_t priority; /*!< Sets the priority of the associated trigger source. If two or more triggers have the same + priority level setting, the lower order trigger event has the higher priority. The lower + value for this field is for the higher priority, the available value range is 1-bit. */ +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) + uint8_t channelAFIFOSelect; /* SAR Result Destination For Channel A. */ + uint8_t channelBFIFOSelect; /* SAR Result Destination For Channel B. */ +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + bool enableHardwareTrigger; /*!< Enable hardware trigger source to initiate conversion on the rising edge of the + input trigger source or not. THe software trigger is always available. */ +} lpadc_conv_trigger_config_t; + +/*! + * @brief Define the structure to keep the conversion result. + */ +typedef struct +{ + uint32_t commandIdSource; /*!< Indicate the command buffer being executed that generated this result. */ + uint32_t loopCountIndex; /*!< Indicate the loop count value during command execution that generated this result. */ + uint32_t triggerIdSource; /*!< Indicate the trigger source that initiated a conversion and generated this result. */ + uint16_t convValue; /*!< Data result. */ +} lpadc_conv_result_t; + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS +/*! + * @brief A structure of calibration value. + */ +typedef struct _lpadc_calibration_value +{ + /* gain calibration result. */ + uint16_t gainCalibrationResultA; +#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) + uint16_t gainCalibrationResultB; +#endif /* !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */ +#if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) + /* general calibration value. */ + uint16_t generalCalibrationValueA[33U]; +#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) + uint16_t generalCalibrationValueB[33U]; +#endif /* !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */ +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ +} lpadc_calibration_value_t; +#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ +/*! + * @name Initialization & de-initialization. + * @{ + */ + +/*! + * @brief Initializes the LPADC module. + * + * @param base LPADC peripheral base address. + * @param config Pointer to configuration structure. See "lpadc_config_t". + */ +void LPADC_Init(ADC_Type *base, const lpadc_config_t *config); + +/*! + * @brief Gets an available pre-defined settings for initial configuration. + * + * This function initializes the converter configuration structure with an available settings. The default values are: + * @code + * config->enableInDozeMode = true; + * config->enableAnalogPreliminary = false; + * config->powerUpDelay = 0x80; + * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; + * config->powerLevelMode = kLPADC_PowerLevelAlt1; + * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; + * config->enableConvPause = false; + * config->convPauseDelay = 0U; + * config->FIFOWatermark = 0U; + * @endcode + * @param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConfig(lpadc_config_t *config); + +/*! + * @brief De-initializes the LPADC module. + * + * @param base LPADC peripheral base address. + */ +void LPADC_Deinit(ADC_Type *base); + +/*! + * @brief Switch on/off the LPADC module. + * + * @param base LPADC peripheral base address. + * @param enable switcher to the module. + */ +static inline void LPADC_Enable(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= ADC_CTRL_ADCEN_MASK; + } + else + { + base->CTRL &= ~ADC_CTRL_ADCEN_MASK; + } +} + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * @brief Do reset the conversion FIFO0. + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_DoResetFIFO0(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_RSTFIFO0_MASK; +} + +/*! + * @brief Do reset the conversion FIFO1. + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_DoResetFIFO1(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_RSTFIFO1_MASK; +} +#else + +#if defined(ADC_CTRL_RSTFIFO0_MASK) +#define ADC_CTRL_RSTFIFO_MASK ADC_CTRL_RSTFIFO0_MASK +#endif /* defined(ADC_CTRL_RSTFIFO0_MASK) */ +/*! + * @brief Do reset the conversion FIFO. + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_DoResetFIFO(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_RSTFIFO_MASK; +} +#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ + +/*! + * @brief Do reset the module's configuration. + * + * Reset all ADC internal logic and registers, except the Control Register (ADCx_CTRL). + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_DoResetConfig(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_RST_MASK; + base->CTRL &= ~ADC_CTRL_RST_MASK; +} + +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Get status flags. + * + * @param base LPADC peripheral base address. + * @return status flags' mask. See to #_lpadc_status_flags. + */ +static inline uint32_t LPADC_GetStatusFlags(ADC_Type *base) +{ + return base->STAT; +} + +/*! + * @brief Clear status flags. + * + * Only the flags can be cleared by writing ADCx_STATUS register would be cleared by this API. + * + * @param base LPADC peripheral base address. + * @param mask Mask value for flags to be cleared. See to #_lpadc_status_flags. + */ +static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) +{ + base->STAT = mask; +} + +#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) +/*! + * @brief Get trigger status flags to indicate which trigger sequences have been completed or interrupted by a high + * priority trigger exception. + * + * @param base LPADC peripheral base address. + * @return The OR'ed value of @ref _lpadc_trigger_status_flags. + */ +static inline uint32_t LPADC_GetTriggerStatusFlags(ADC_Type *base) +{ + return base->TSTAT; +} + +/*! + * @brief Clear trigger status flags. + * + * @param base LPADC peripheral base address. + * @param mask The mask of trigger status flags to be cleared, should be the + * OR'ed value of @ref _lpadc_trigger_status_flags. + */ +static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask) +{ + /* This assert used to avoid user use doesn't supported trigger sources. */ + assert(((mask & 0xFFFFU) == (mask & ADC_TSTAT_TEXC_NUM_MASK)) && + ((mask & 0xFFFF0000U) == (mask & ADC_TSTAT_TCOMP_FLAG_MASK))); + base->TSTAT = mask; +} +#endif /* (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) */ + +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enable interrupts. + * + * @param base LPADC peripheral base address. + * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. + */ +static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask) +{ +#if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) + /* This assert used to avoid user use doesn't supported trigger sources. */ + assert((mask <= 0xFFFFU) || ((mask & 0xFFFF0000U) == (mask & ADC_IE_TCOMP_IE_MASK))); +#endif /* #if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) */ + base->IE |= mask; +} + +/*! + * @brief Disable interrupts. + * + * @param base LPADC peripheral base address. + * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. + */ +static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask) +{ +#if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) + /* This assert used to avoid user use doesn't supported trigger sources. */ + assert((mask <= 0xFFFFU) || ((mask & 0xFFFF0000U) == (mask & ADC_IE_TCOMP_IE_MASK))); +#endif /* #if (defined(FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE) && (FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE == 1U)) */ + base->IE &= ~mask; +} + +/*! + * @name DMA Control + * @{ + */ + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * @brief Switch on/off the DMA trigger for FIFO0 watermark event. + * + * @param base LPADC peripheral base address. + * @param enable Switcher to the event. + */ +static inline void LPADC_EnableFIFO0WatermarkDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->DE |= ADC_DE_FWMDE0_MASK; + } + else + { + base->DE &= ~ADC_DE_FWMDE0_MASK; + } +} + +/*! + * @brief Switch on/off the DMA trigger for FIFO1 watermark event. + * + * @param base LPADC peripheral base address. + * @param enable Switcher to the event. + */ +static inline void LPADC_EnableFIFO1WatermarkDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->DE |= ADC_DE_FWMDE1_MASK; + } + else + { + base->DE &= ~ADC_DE_FWMDE1_MASK; + } +} +#else +#if defined(ADC_DE_FWMDE0_MASK) +#define ADC_DE_FWMDE_MASK ADC_DE_FWMDE0_MASK +#endif /* defined(ADC_DE_FWMDE0_MASK) */ +/*! + * @brief Switch on/off the DMA trigger for FIFO watermark event. + * + * @param base LPADC peripheral base address. + * @param enable Switcher to the event. + */ +static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable) +{ + if (enable) + { + base->DE |= ADC_DE_FWMDE_MASK; + } + else + { + base->DE &= ~ADC_DE_FWMDE_MASK; + } +} +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) */ +/*! @} */ + +/*! + * @name Trigger and conversion with FIFO. + * @{ + */ + +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) +/*! + * @brief Get the count of result kept in conversion FIFOn. + * + * @param base LPADC peripheral base address. + * @param index Result FIFO index. + * @return The count of result kept in conversion FIFOn. + */ +static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base, uint8_t index) +{ + return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL[index]) >> ADC_FCTRL_FCOUNT_SHIFT; +} + +/*! + * @brief Get the result in conversion FIFOn. + * + * @param base LPADC peripheral base address. + * @param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. + * @param index Result FIFO index. + * + * @return Status whether FIFOn entry is valid. + */ +bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index); + +/*! + * @brief Get the result in conversion FIFOn using blocking method. + * + * @param base LPADC peripheral base address. + * @param result Pointer to structure variable that keeps the conversion result in conversion FIFOn. + * @param index Result FIFO index. + */ +void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index); +#else /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 1)) */ +/*! + * @brief Get the count of result kept in conversion FIFO. + * + * @param base LPADC peripheral base address. + * @return The count of result kept in conversion FIFO. + */ +static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base) +{ + return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL) >> ADC_FCTRL_FCOUNT_SHIFT; +} + +/*! + * @brief Get the result in conversion FIFO. + * + * @param base LPADC peripheral base address. + * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO. + * + * @return Status whether FIFO entry is valid. + */ +bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result); + +/*! + * @brief Get the result in conversion FIFO using blocking method. + * + * @param base LPADC peripheral base address. + * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO. + */ +void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result); +#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) */ + +/*! + * @brief Configure the conversion trigger source. + * + * Each programmable trigger can launch the conversion command in command buffer. + * + * @param base LPADC peripheral base address. + * @param triggerId ID for each trigger. Typically, the available value range is from 0. + * @param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t. + */ +void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config); + +/*! + * @brief Gets an available pre-defined settings for trigger's configuration. + * + * This function initializes the trigger's configuration structure with an available settings. The default values are: + * @code + * config->targetCommandId = 0U; + * config->delayPower = 0U; + * config->priority = 0U; + * config->channelAFIFOSelect = 0U; + * config->channelBFIFOSelect = 0U; + * config->enableHardwareTrigger = false; + * @endcode + * @param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config); + +/*! + * @brief Do software trigger to conversion command. + * + * @param base LPADC peripheral base address. + * @param triggerIdMask Mask value for software trigger indexes, which count from zero. + */ +static inline void LPADC_DoSoftwareTrigger(ADC_Type *base, uint32_t triggerIdMask) +{ + /* Writes to ADCx_SWTRIG register are ignored while ADCx_CTRL[ADCEN] is clear. */ + base->SWTRIG = triggerIdMask; +} + +#if defined(FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL) && FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL +/*! + * @brief Enable hardware trigger command selection. + * + * This function will use the hardware trigger command from ADC_ETC.The trigger command is then defined + * by ADC hardware trigger command selection field in ADC_ETC- >TRIGx_CHAINy_z_n[CSEL]. + * + * @param base LPADC peripheral base address. + * @param triggerId ID for each trigger. Typically, the available value range is from 0. + * @param enable True to enable or flase to disable. + */ +static inline void LPADC_EnableHardwareTriggerCommandSelection(ADC_Type *base, uint32_t triggerId, bool enable) +{ + if (enable) + { + base->TCTRL[triggerId] |= ADC_TCTRL_CMD_SEL_MASK; + } + else + { + base->TCTRL[triggerId] &= ~ADC_TCTRL_CMD_SEL_MASK; + } +} +#endif /* defined(FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL) && FSL_FEATURE_LPADC_HAS_TCTRL_CMD_SEL*/ + +/*! + * @brief Configure conversion command. + + * @note The number of compare value register on different chips is different, that is mean in some chips, some + * command buffers do not have the compare functionality. + * + * @param base LPADC peripheral base address. + * @param commandId ID for command in command buffer. Typically, the available value range is 1 - 15. + * @param config Pointer to configuration structure. See to #lpadc_conv_command_config_t. + */ +void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config); + +/*! + * @brief Gets an available pre-defined settings for conversion command's configuration. + * + * This function initializes the conversion command's configuration structure with an available settings. The default + * values are: + * @code + * config->sampleScaleMode = kLPADC_SampleFullScale; + * config->channelBScaleMode = kLPADC_SampleFullScale; + * config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA; + * config->channelNumber = 0U; + * config->channelBNumber = 0U; + * config->chainedNextCommandNumber = 0U; + * config->enableAutoChannelIncrement = false; + * config->loopCount = 0U; + * config->hardwareAverageMode = kLPADC_HardwareAverageCount1; + * config->sampleTimeMode = kLPADC_SampleTimeADCK3; + * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; + * config->hardwareCompareValueHigh = 0U; + * config->hardwareCompareValueLow = 0U; + * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; + * config->enableWaitTrigger = false; + * config->enableChannelB = false; + * @endcode + * @param config Pointer to configuration structure. + */ +void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config); + +#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS +/*! + * @brief Enable the calibration function. + * + * When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes + * a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value + * between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6- + * bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the + * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. + * + * @param base LPADC peripheral base address. + * @param enable switcher to the calibration function. + */ +void LPADC_EnableCalibration(ADC_Type *base, bool enable); +#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM +/*! + * @brief Set proper offset value to trim ADC. + * + * To minimize the offset during normal operation, software should read the conversion result from + * the RESFIFO calibration operation and write the lower 6 bits to the OFSTRIM register. + * + * @param base LPADC peripheral base address. + * @param value Setting offset value. + */ +static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value) +{ + base->OFSTRIM = (value & ADC_OFSTRIM_OFSTRIM_MASK) >> ADC_OFSTRIM_OFSTRIM_SHIFT; +} + +/*! + * @brief Do auto calibration. + * + * Calibration function should be executed before using converter in application. It used the software trigger and a + * dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API + * including: -LPADC_EnableCalibration(...) -LPADC_LPADC_SetOffsetValue(...) -LPADC_SetConvCommandConfig(...) + * -LPADC_SetConvTriggerConfig(...) + * + * @param base LPADC peripheral base address. + */ +void LPADC_DoAutoCalibration(ADC_Type *base); +#endif /* defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM */ +#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS */ + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS +#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM +#if defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) && (FSL_FEATURE_LPADC_OFSTRIM_COUNT == 1U) +/*! + * @brief Set trim value for offset. + * + * @note For 16-bit conversions, each increment is 1/2 LSB resulting in a programmable offset range of -256 LSB to 255.5 + * LSB; For 12-bit conversions, each increment is 1/32 LSB resulting in a programmable offset range of -16 LSB to + * 15.96875 LSB. + * + * @param base LPADC peripheral base address. + * @param value Offset trim value, is a 10-bit signed value between -512 and 511. + */ +static inline void LPADC_SetOffsetValue(ADC_Type *base, int16_t value) +{ + base->OFSTRIM = ADC_OFSTRIM_OFSTRIM(value); +} + +/*! + * @brief Get trim value of offset. + * + * @param base LPADC peripheral base address. + * @param pValue Pointer to the variable in type of int16_t to store offset value. + */ +static inline void LPADC_GetOffsetValue(ADC_Type *base, int16_t *pValue) +{ + assert(pValue != NULL); + + uint16_t ofstrim = (uint16_t)((base->OFSTRIM & (ADC_OFSTRIM_OFSTRIM_MASK)) >> ADC_OFSTRIM_OFSTRIM_SHIFT); + + if ((ofstrim & ADC_OFSTRIM_OFSTRIM_SIGN) != 0U) + { + /* If the sign bit is set, then set the other MSB. */ + ofstrim |= (uint16_t)(~ADC_OFSTRIM_OFSTRIM_MAX); + } + + *pValue = (int16_t)ofstrim; +} +#elif (defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) && (FSL_FEATURE_LPADC_OFSTRIM_COUNT == 2U)) +/*! + * @brief Set proper offset value to trim ADC. + * + * Set the offset trim value for offset calibration manually. + * + * @param base LPADC peripheral base address. + * @param valueA Setting offset value A. + * @param valueB Setting offset value B. + * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration. + */ +static inline void LPADC_SetOffsetValue(ADC_Type *base, int32_t valueA, int32_t valueB) +{ + base->OFSTRIM = ADC_OFSTRIM_OFSTRIM_A(valueA) | ADC_OFSTRIM_OFSTRIM_B(valueB); +} + +/*! + * @brief Get trim value of offset. + * + * @param base LPADC peripheral base address. + * @param pValueA Pointer to the variable in type of int32_t to store offset A value. + * @param pValueB Pointer to the variable in type of int32_t to store offset B value. + */ +static inline void LPADC_GetOffsetValue(ADC_Type *base, int32_t *pValueA, int32_t *pValueB) +{ + assert(pValueA != NULL); + assert(pValueB != NULL); + + uint32_t ofstrimA = (base->OFSTRIM & (ADC_OFSTRIM_OFSTRIM_A_MASK)) >> ADC_OFSTRIM_OFSTRIM_A_SHIFT; + uint32_t ofstrimB = (base->OFSTRIM & (ADC_OFSTRIM_OFSTRIM_B_MASK)) >> ADC_OFSTRIM_OFSTRIM_B_SHIFT; + + if ((ofstrimA & ADC_OFSTRIM_OFSTRIM_A_SIGN) != 0U) + { + /* If the sign bit is set, then set the other MSB. */ + ofstrimA |= (~ADC_OFSTRIM_OFSTRIM_A_MAX); + } + if ((ofstrimB & ADC_OFSTRIM_OFSTRIM_B_SIGN) != 0U) + { + /* If the sign bit is set, then set the other MSB. */ + ofstrimB |= (~ADC_OFSTRIM_OFSTRIM_B_MAX); + } + + *pValueA = (int32_t)ofstrimA; + *pValueB = (int32_t)ofstrimB; +} +#endif /* defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) */ +#else /* !(defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM) */ +/*! + * @brief Set proper offset value to trim 12 bit ADC conversion. + * + * Set the offset trim value for offset calibration manually. + * + * @param base LPADC peripheral base address. + * @param valueA Setting offset value A. + * @param valueB Setting offset value B. + * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration. + */ +static inline void LPADC_SetOffset12BitValue(ADC_Type *base, uint32_t valueA, uint32_t valueB) +{ + base->OFSTRIM12 = ADC_OFSTRIM12_OFSTRIM_A(valueA) | ADC_OFSTRIM12_OFSTRIM_A(valueB); +} + +/*! + * @brief Set proper offset value to trim 16 bit ADC conversion. + * + * Set the offset trim value for offset calibration manually. + * + * @param base LPADC peripheral base address. + * @param valueA Setting offset value A. + * @param valueB Setting offset value B. + * @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration. + */ +static inline void LPADC_SetOffset16BitValue(ADC_Type *base, uint32_t valueA, uint32_t valueB) +{ + base->OFSTRIM16 = ADC_OFSTRIM16_OFSTRIM_A(valueA) | ADC_OFSTRIM16_OFSTRIM_B(valueB); +} +#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */ + +/*! + * @brief Enable the offset calibration function. + * + * @param base LPADC peripheral base address. + * @param enable switcher to the calibration function. + */ +static inline void LPADC_EnableOffsetCalibration(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= ADC_CTRL_CALOFS_MASK; + } + else + { + base->CTRL &= ~ADC_CTRL_CALOFS_MASK; + } +} +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE +/*! + * @brief Set offset calibration mode. + * + * @param base LPADC peripheral base address. + * @param mode set offset calibration mode.see to #lpadc_offset_calibration_mode_t . + */ +static inline void LPADC_SetOffsetCalibrationMode(ADC_Type *base, lpadc_offset_calibration_mode_t mode) +{ + base->CTRL = (base->CTRL & ~ADC_CTRL_CALOFSMODE_MASK) | ADC_CTRL_CALOFSMODE(mode); +} + +#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */ + +/*! + * @brief Do offset calibration. + * + * @param base LPADC peripheral base address. + */ +void LPADC_DoOffsetCalibration(ADC_Type *base); + +#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ +/*! + * @brief Do auto calibration. + * + * @param base LPADC peripheral base address. + */ +void LPADC_DoAutoCalibration(ADC_Type *base); + +/*! + * @brief Prepare auto calibration, LPADC_FinishAutoCalibration has to be called before using the LPADC. + * LPADC_DoAutoCalibration has been split in two API to avoid to be stuck too long in the function. + * + * @param base LPADC peripheral base address. + */ +void LPADC_PrepareAutoCalibration(ADC_Type *base); + +/*! + * @brief Finish auto calibration start with LPADC_PrepareAutoCalibration. + * + * @param base LPADC peripheral base address. + */ +void LPADC_FinishAutoCalibration(ADC_Type *base); + +#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ + +/*! + * @brief Get calibration value into the memory which is defined by invoker. + * + * @note Please note the ADC will be disabled temporary. + * @note This function should be used after finish calibration. + * + * @param base LPADC peripheral base address. + * @param ptrCalibrationValue Pointer to @ref lpadc_calibration_value_t structure, this memory block should be always + * powered on even in low power modes. + */ +void LPADC_GetCalibrationValue(ADC_Type *base, lpadc_calibration_value_t *ptrCalibrationValue); + +/*! + * @brief Set calibration value into ADC calibration registers. + * + * @note Please note the ADC will be disabled temporary. + * + * @param base LPADC peripheral base address. + * @param ptrCalibrationValue Pointer to @ref lpadc_calibration_value_t structure which contains ADC's calibration + * value. + */ +void LPADC_SetCalibrationValue(ADC_Type *base, const lpadc_calibration_value_t *ptrCalibrationValue); + +#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ + +#if ((defined(FSL_FEATURE_LPADC_HAS_CTRL_CALHS)) && FSL_FEATURE_LPADC_HAS_CTRL_CALHS) +/*! + * @brief Request high speed mode trim calculation. + * + * @param base LPADC peripheral base address. + */ +static inline void LPADC_RequestHighSpeedModeTrim(ADC_Type *base) +{ + base->CTRL |= ADC_CTRL_CALHS_MASK; +} + +/*! + * @brief Get high speed mode trim value, the result is a 5-bit signed value between -16 and 15. + * + * @note The high speed mode trim value is used to minimize offset for high speed conversion. + * + * @param base LPADC peripheral base address. + * @return The calculated high speed mode trim value. + */ +static inline int8_t LPADC_GetHighSpeedTrimValue(ADC_Type *base) +{ + return (int8_t)(base->HSTRIM); +} + +/*! + * @brief Set high speed mode trim value. + * + * @note If is possible to set the trim value manually, but it is recommended to use the LPADC_RequestHighSpeedModeTrim. + * + * @param base LPADC peripheral base address. + * @param trimValue The trim value to be set. + */ +static inline void LPADC_SetHighSpeedTrimValue(ADC_Type *base, int8_t trimValue) +{ + base->HSTRIM = ADC_HSTRIM_HSTRIM(trimValue); +} + +/*! + * @brief Enable/disable high speed conversion mode, if enabled conversions complete 2 or 3 ADCK cycles sooner compared + * to conversion cycle counts when high speed mode is disabled. + * + * @param base LPADC peripheral base address. + * @param enable Used to enable/disable high speed conversion mode: + * - \b true Enable high speed conversion mode; + * - \b false Disable high speed conversion mode. + */ +static inline void LPADC_EnableHighSpeedConversionMode(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CFG2 |= ADC_CFG2_HS_MASK; + } + else + { + base->CFG2 &= ~ADC_CFG2_HS_MASK; + } +} + +/*! + * @brief Enable/disable an additional ADCK cycle to conversion. + * + * @param base LPADC peripheral base address. + * @param enable Used to enable/disable an additional ADCK cycle to conversion: + * - \b true Enable an additional ADCK cycle to conversion; + * - \b false Disable an additional ADCK cycle to conversion. + */ +static inline void LPADC_EnableExtraCycle(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CFG2 |= ADC_CFG2_HSEXTRA_MASK; + } + else + { + base->CFG2 &= ~ADC_CFG2_HSEXTRA_MASK; + } +} + +/*! + * @brief Set tune value which provides some variability in how many cycles are needed to complete a conversion. + * + * @param base LPADC peripheral base address. + * @param tuneValue The tune value to be set, please refer to @ref lpadc_tune_value_t. + */ +static inline void LPADC_SetTuneValue(ADC_Type *base, lpadc_tune_value_t tuneValue) +{ + base->CFG2 = (base->CFG2 & ~ADC_CFG2_TUNE_MASK) | ADC_CFG2_TUNE(tuneValue); +} + +/*! + * @brief Get tune value which provides some variability in how many cycles are needed to complete a conversion. + * + * @param base LPADC peripheral base address. + * @return The tune value, please refer to @ref lpadc_tune_value_t. + */ +static inline lpadc_tune_value_t LPADC_GetTuneValue(ADC_Type *base) +{ + return (lpadc_tune_value_t)((base->CFG2 & ADC_CFG2_TUNE_MASK) >> ADC_CFG2_TUNE_SHIFT); +} +#endif /* ((defined(FSL_FEATURE_LPADC_HAS_CTRL_CALHS)) && FSL_FEATURE_LPADC_HAS_CTRL_CALHS) */ + +#if (defined(FSL_FEATURE_LPADC_HAS_CFG2_JLEFT) && FSL_FEATURE_LPADC_HAS_CFG2_JLEFT) +/*! + * @brief Enable/disable left-justify format in 12-bit single-end mode. + * + * @param base LPADC peripheral base address. + * @param enable Used to enable/disable left-justify format in 12-bit single-end mode: + * - \b true Enable left-justify format in 12-bit single-end mode; + * - \b false Disable left-justify format in 12-bit single-end mode. + */ +static inline void LPADC_EnableJustifiedLeft(ADC_Type *base, bool enable) +{ + if (enable) + { + base->CFG2 |= ADC_CFG2_JLEFT_MASK; + } + else + { + base->CFG2 &= ~ADC_CFG2_JLEFT_MASK; + } +} +#endif /* (defined(FSL_FEATURE_LPADC_HAS_CFG2_JLEFT) && FSL_FEATURE_LPADC_HAS_CFG2_JLEFT) */ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* FSL_LPADC_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpcmp.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpcmp.c new file mode 100644 index 00000000000..4ed2d921db9 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpcmp.c @@ -0,0 +1,372 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019, 2023 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpcmp.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpcmp" +#endif + +#if defined(LPCMP_RSTS) +#define LPCMP_RESETS_ARRAY LPCMP_RSTS +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(LPCMP_CLOCKS) +/*! + * @brief Get instance number for LPCMP module. + * + * @param base LPCMP peripheral base address + */ +static uint32_t LPCMP_GetInstance(LPCMP_Type *base); +#endif /* LPCMP_CLOCKS */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if defined(LPCMP_CLOCKS) +/*! @brief Pointers to LPCMP bases for each instance. */ +static LPCMP_Type *const s_lpcmpBases[] = LPCMP_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to LPCMP clocks for each instance. */ +static const clock_ip_name_t s_lpcmpClocks[] = LPCMP_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* LPCMP_CLOCKS */ + +#if defined(LPCMP_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_lpcmpResets[] = LPCMP_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Codes + ******************************************************************************/ +#if defined(LPCMP_CLOCKS) +static uint32_t LPCMP_GetInstance(LPCMP_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + /* + * $Branch Coverage Justification$ + * (instance >= ARRAY_SIZE(s_lpcmpBases)) not covered. The peripheral base + * address is always valid and checked by assert. + */ + for (instance = 0; instance < ARRAY_SIZE(s_lpcmpBases); instance++) + { + /* + * $Branch Coverage Justification$ + * (s_lpcmpBases[instance] != base) not covered. The peripheral base + * address is always valid and checked by assert. + */ + if (s_lpcmpBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_lpcmpBases)); + + return instance; +} +#endif /* LPCMP_CLOCKS */ + +/*! + * brief Initialize the LPCMP + * + * This function initializes the LPCMP module. The operations included are: + * - Enabling the clock for LPCMP module. + * - Configuring the comparator. + * - Enabling the LPCMP module. + * Note: For some devices, multiple LPCMP instance share the same clock gate. In this case, to enable the clock for + * any instance enables all the LPCMPs. Check the chip reference manual for the clock assignment of the LPCMP. + * + * param base LPCMP peripheral base address. + * param config Pointer to "lpcmp_config_t" structure. + */ +void LPCMP_Init(LPCMP_Type *base, const lpcmp_config_t *config) +{ + assert(config != NULL); + + uint32_t tmp32; + +#if defined(LPCMP_CLOCKS) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_lpcmpClocks[LPCMP_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* LPCMP_CLOCKS */ + +#if defined(LPCMP_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_lpcmpResets[LPCMP_GetInstance(base)]); +#endif + + /* Configure. */ + LPCMP_Enable(base, false); + +#if !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) + /* CCR0 register. */ +#if defined(FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn) + if (1U == FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(base)) +#endif /* FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn */ + { + if (config->enableStopMode) + { + base->CCR0 |= LPCMP_CCR0_CMP_STOP_EN_MASK; + } + else + { + base->CCR0 &= ~LPCMP_CCR0_CMP_STOP_EN_MASK; + } + } +#endif /* !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) */ + + /* CCR1 register. */ + tmp32 = (base->CCR1 & (~(LPCMP_CCR1_COUT_PEN_MASK | LPCMP_CCR1_COUT_SEL_MASK | LPCMP_CCR1_COUT_INV_MASK +#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL + | LPCMP_CCR1_FUNC_CLK_SEL_MASK +#endif /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */ + ))); + + if (config->enableOutputPin) + { + tmp32 |= LPCMP_CCR1_COUT_PEN_MASK; + } + if (config->useUnfilteredOutput) + { + tmp32 |= LPCMP_CCR1_COUT_SEL_MASK; + } + if (config->enableInvertOutput) + { + tmp32 |= LPCMP_CCR1_COUT_INV_MASK; + } +#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL + tmp32 |= LPCMP_CCR1_FUNC_CLK_SEL(config->functionalSourceClock); +#endif /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */ + base->CCR1 = tmp32; + /* CCR2 register. */ + tmp32 = base->CCR2 & ~(LPCMP_CCR2_HYSTCTR_MASK | LPCMP_CCR2_CMP_NPMD_MASK | LPCMP_CCR2_CMP_HPMD_MASK); + tmp32 |= LPCMP_CCR2_HYSTCTR(config->hysteresisMode); + tmp32 |= ((uint32_t)(config->powerMode) << LPCMP_CCR2_CMP_HPMD_SHIFT); + base->CCR2 = tmp32; + + LPCMP_Enable(base, true); /* Enable the LPCMP module. */ +} + +/*! + * brief De-initializes the LPCMP module. + * + * This function de-initializes the LPCMP module. The operations included are: + * - Disabling the LPCMP module. + * - Disabling the clock for LPCMP module. + * + * This function disables the clock for the LPCMP. + * Note: For some devices, multiple LPCMP instance shares the same clock gate. In this case, before disabling the + * clock for the LPCMP, ensure that all the LPCMP instances are not used. + * + * param base LPCMP peripheral base address. + */ +void LPCMP_Deinit(LPCMP_Type *base) +{ + /* Disable the LPCMP module. */ + LPCMP_Enable(base, false); +#if defined(LPCMP_CLOCKS) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_lpcmpClocks[LPCMP_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* LPCMP_CLOCKS */ +} + +/*! + * brief Gets an available pre-defined settings for the comparator's configuration. + * + * This function initializes the comparator configuration structure to these default values: + * code + * config->enableStopMode = false; + * config->enableOutputPin = false; + * config->useUnfilteredOutput = false; + * config->enableInvertOutput = false; + * config->hysteresisMode = kLPCMP_HysteresisLevel0; + * config->powerMode = kLPCMP_LowSpeedPowerMode; + * config->functionalSourceClock = kLPCMP_FunctionalClockSource0; + * endcode + * param config Pointer to "lpcmp_config_t" structure. + */ +void LPCMP_GetDefaultConfig(lpcmp_config_t *config) +{ + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); +#if !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) + config->enableStopMode = false; +#endif /* !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) */ + config->enableOutputPin = false; + config->useUnfilteredOutput = false; + config->enableInvertOutput = false; + config->hysteresisMode = kLPCMP_HysteresisLevel0; + config->powerMode = kLPCMP_LowSpeedPowerMode; +#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL + config->functionalSourceClock = kLPCMP_FunctionalClockSource0; +#endif /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */ +} + +/*! + * brief Select the input channels for LPCMP. This function determines which input + * is selected for the negative and positive mux. + * + * param base LPCMP peripheral base address. + * param positiveChannel Positive side input channel number. + * param negativeChannel Negative side input channel number. + */ +void LPCMP_SetInputChannels(LPCMP_Type *base, uint32_t positiveChannel, uint32_t negativeChannel) +{ + uint32_t tmp32; + + tmp32 = base->CCR2 & ~(LPCMP_CCR2_PSEL_MASK | LPCMP_CCR2_MSEL_MASK); + tmp32 |= LPCMP_CCR2_PSEL(positiveChannel) | LPCMP_CCR2_MSEL(negativeChannel); + base->CCR2 = tmp32; +} + +/*! + * brief Configures the filter. + * + * param base LPCMP peripheral base address. + * param config Pointer to "lpcmp_filter_config_t" structure. + */ +void LPCMP_SetFilterConfig(LPCMP_Type *base, const lpcmp_filter_config_t *config) +{ + assert(config != NULL); + + uint32_t tmp32; + + tmp32 = base->CCR1 & ~(LPCMP_CCR1_FILT_PER_MASK | LPCMP_CCR1_FILT_CNT_MASK | LPCMP_CCR1_SAMPLE_EN_MASK); + if (config->enableSample) + { + tmp32 |= LPCMP_CCR1_SAMPLE_EN_MASK; + } + tmp32 |= LPCMP_CCR1_FILT_PER(config->filterSamplePeriod) | LPCMP_CCR1_FILT_CNT(config->filterSampleCount); + base->CCR1 = tmp32; +} + +/*! + * brief Configure the internal DAC module. + * + * param base LPCMP peripheral base address. + * param config Pointer to "lpcmp_dac_config_t" structure. If config is "NULL", disable internal DAC. + */ +void LPCMP_SetDACConfig(LPCMP_Type *base, const lpcmp_dac_config_t *config) +{ + uint32_t tmp32; + if (config == NULL) + { + tmp32 = 0U; /* Disable internal DAC. */ + } + else + { + tmp32 = LPCMP_DCR_VRSEL(config->referenceVoltageSource) | LPCMP_DCR_DAC_DATA(config->DACValue); + if (config->enableLowPowerMode) + { + tmp32 |= LPCMP_DCR_DAC_HPMD_MASK; + } + tmp32 |= LPCMP_DCR_DAC_EN_MASK; + } + base->DCR = tmp32; +} + +#if defined(FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL) && FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL +/*! + * @brief Configure the window control, users can use this API to implement operations on the window, + * such as inverting the window signal, setting the window closing event(only valid in windowing mode), + * and setting the COUTA signal after the window is closed(only valid in windowing mode). + * + * @param base LPCMP peripheral base address. + * @param config Pointer "lpcmp_window_control_config_t" structure. + */ +void LPCMP_SetWindowControl(LPCMP_Type *base, const lpcmp_window_control_config_t *config) +{ + assert(config != NULL); + + uint32_t tmp32 = 0UL; + + tmp32 = (base->CCR1 & (~(LPCMP_CCR1_COUTA_CFG_MASK | LPCMP_CCR1_EVT_SEL_CFG_MASK | LPCMP_CCR1_WINDOW_INV_MASK))); + + if (config->enableInvertWindowSignal) + { + tmp32 |= LPCMP_CCR1_WINDOW_INV_MASK; + } + + /* Set COUT event, which can close the active window in window mode. */ + tmp32 |= LPCMP_CCR1_EVT_SEL_CFG(config->closeWindowEvent); + + /* Set the COUTA signal value when the window is closed. */ + tmp32 |= LPCMP_CCR1_COUTA_CFG(config->COUTASignal); + + base->CCR1 = tmp32; +} +#endif /* FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL */ + +#if defined(FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE) && FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE +/*! + * @brief Configure the roundrobin mode. + * + * @param base LPCMP peripheral base address. + * @param config Pointer "lpcmp_roundrobin_config_t" structure. + */ +void LPCMP_SetRoundRobinConfig(LPCMP_Type *base, const lpcmp_roundrobin_config_t *config) +{ + assert(config != NULL); + + uint32_t tmp32 = 0UL; + + /* LPCMPx_RRCR0 register, Configuration options for the round-robin operation. */ + tmp32 = (base->RRCR0 & + (~(LPCMP_RRCR0_RR_TRG_SEL_MASK | LPCMP_RRCR0_RR_NSAM_MASK | LPCMP_RRCR0_RR_CLK_SEL_MASK | + LPCMP_RRCR0_RR_INITMOD_MASK | LPCMP_RRCR0_RR_SAMPLE_CNT_MASK | LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK))); + + tmp32 |= + (LPCMP_RRCR0_RR_TRG_SEL(config->roundrobinTriggerSource) | LPCMP_RRCR0_RR_NSAM(config->sampleClockNumbers) | + LPCMP_RRCR0_RR_CLK_SEL(config->roundrobinClockSource) | LPCMP_RRCR0_RR_INITMOD(config->initDelayModules) | + LPCMP_RRCR0_RR_SAMPLE_CNT(config->channelSampleNumbers) | + LPCMP_RRCR0_RR_SAMPLE_THRESHOLD(config->sampleTimeThreshhold)); + + base->RRCR0 = tmp32; + + /* LPCMPx_RRCR1 register, Configure the fix port, fix channel and checker channel. */ + tmp32 = + (base->RRCR1 & (~(LPCMP_RRCR1_FIXP_MASK | LPCMP_RRCR1_FIXCH_MASK | (0xFFUL << LPCMP_RRCR1_RR_CH0EN_SHIFT)))); + tmp32 |= (LPCMP_RRCR1_FIXP(config->fixedMuxPort) | LPCMP_RRCR1_FIXCH(config->fixedChannel) | + ((uint32_t)(config->checkerChannelMask) << LPCMP_RRCR1_RR_CH0EN_SHIFT)); + + base->RRCR1 = tmp32; +} + +/*! + * brief Configure the roundrobin internal timer reload value. + * + * param base LPCMP peripheral base address. + * param value RoundRobin internal timer reload value, allowed range:0x0UL-0xFFFFFFFUL. + */ +void LPCMP_SetRoundRobinInternalTimer(LPCMP_Type *base, uint32_t value) +{ + uint32_t tmp32 = 0UL; + + tmp32 = (base->RRCR2 & (~LPCMP_RRCR2_RR_TIMER_RELOAD_MASK)); + tmp32 |= LPCMP_RRCR2_RR_TIMER_RELOAD(value); + + base->RRCR2 = tmp32; +} + +#endif /* FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpcmp.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpcmp.h new file mode 100644 index 00000000000..5105c98fcc1 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpcmp.h @@ -0,0 +1,585 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020, 2023-2024 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_LPCMP_H_ +#define FSL_LPCMP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpcmp + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @name Driver version */ +/*! @{ */ +/*! @brief LPCMP driver version 2.1.3. */ +#define FSL_LPCMP_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) +/*! @} */ + +#define LPCMP_CCR1_COUTA_CFG_MASK (LPCMP_CCR1_COUTA_OWEN_MASK | LPCMP_CCR1_COUTA_OW_MASK) +#define LPCMP_CCR1_COUTA_CFG_SHIFT LPCMP_CCR1_COUTA_OWEN_SHIFT +#define LPCMP_CCR1_COUTA_CFG(x) \ + (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_CFG_SHIFT)) & LPCMP_CCR1_COUTA_CFG_MASK) + +#define LPCMP_CCR1_EVT_SEL_CFG_MASK (LPCMP_CCR1_EVT_SEL_MASK | LPCMP_CCR1_WINDOW_CLS_MASK) +#define LPCMP_CCR1_EVT_SEL_CFG_SHIFT LPCMP_CCR1_WINDOW_CLS_SHIFT +#define LPCMP_CCR1_EVT_SEL_CFG(x) \ + (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_EVT_SEL_CFG_SHIFT)) & LPCMP_CCR1_EVT_SEL_CFG_MASK) + +/*! + * @brief LPCMP status falgs mask. + */ +enum _lpcmp_status_flags +{ + kLPCMP_OutputRisingEventFlag = LPCMP_CSR_CFR_MASK, /*!< Rising-edge on the comparison output has occurred. */ + kLPCMP_OutputFallingEventFlag = LPCMP_CSR_CFF_MASK, /*!< Falling-edge on the comparison output has occurred. */ +#if defined(FSL_FEATURE_LPCMP_HAS_CSR_RRF) && FSL_FEATURE_LPCMP_HAS_CSR_RRF + kLPCMP_OutputRoundRobinEventFlag = LPCMP_CSR_RRF_MASK, /*!< Detects when any channel's last comparison result is + different from the pre-set value in trigger mode. */ +#endif /* FSL_FEATURE_LPCMP_HAS_CSR_RRF */ + kLPCMP_OutputAssertEventFlag = LPCMP_CSR_COUT_MASK, /*!< Return the current value of the analog comparator output. + The flag does not support W1C. */ +}; + +/*! + * @brief LPCMP interrupt enable/disable mask. + */ +enum _lpcmp_interrupt_enable +{ + kLPCMP_OutputRisingInterruptEnable = LPCMP_IER_CFR_IE_MASK, /*!< Comparator interrupt enable rising. */ + kLPCMP_OutputFallingInterruptEnable = LPCMP_IER_CFF_IE_MASK, /*!< Comparator interrupt enable falling. */ +#if defined(FSL_FEATURE_LPCMP_HAS_IER_RRF_IE) && FSL_FEATURE_LPCMP_HAS_IER_RRF_IE + kLPCMP_RoundRobinInterruptEnable = LPCMP_IER_RRF_IE_MASK, /*!< Comparator round robin mode interrupt + occurred when the comparison result changes for a given channel. */ +#endif /* FSL_FEATURE_LPCMP_HAS_IER_RRF_IE */ +}; + +/*! + * @brief LPCMP hysteresis mode. See chip data sheet to get the actual hystersis + * value with each level + */ +typedef enum _lpcmp_hysteresis_mode +{ + kLPCMP_HysteresisLevel0 = 0U, /*!< The hard block output has level 0 hysteresis internally. */ + kLPCMP_HysteresisLevel1 = 1U, /*!< The hard block output has level 1 hysteresis internally. */ + kLPCMP_HysteresisLevel2 = 2U, /*!< The hard block output has level 2 hysteresis internally. */ + kLPCMP_HysteresisLevel3 = 3U, /*!< The hard block output has level 3 hysteresis internally. */ +} lpcmp_hysteresis_mode_t; + +/*! + * @brief LPCMP nano mode. + */ +typedef enum _lpcmp_power_mode +{ + kLPCMP_LowSpeedPowerMode = 0U, /*!< Low speed comparison mode is selected. */ + kLPCMP_HighSpeedPowerMode = 1U, /*!< High speed comparison mode is selected. */ + kLPCMP_NanoPowerMode = 2U, /*!< Nano power comparator is enabled. */ +} lpcmp_power_mode_t; + +/*! + * @brief Internal DAC reference voltage source. + */ +typedef enum _lpcmp_dac_reference_voltage_source +{ + kLPCMP_VrefSourceVin1 = 0U, /*!< vrefh_int is selected as resistor ladder network supply reference Vin. */ + kLPCMP_VrefSourceVin2 = 1U, /*!< vrefh_ext is selected as resistor ladder network supply reference Vin. */ +} lpcmp_dac_reference_voltage_source_t; + +#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL +/*! + * @brief LPCMP functional mode clock source selection. + * + * Note: In different devices, the functional mode clock source selection is different, + * please refer to specific device Reference Manual for details. + */ +typedef enum _lpcmp_functional_source_clock +{ + kLPCMP_FunctionalClockSource0 = 0U, /*!< Select functional mode clock source0. */ + kLPCMP_FunctionalClockSource1 = 1U, /*!< Select functional mode clock source1. */ + kLPCMP_FunctionalClockSource2 = 2U, /*!< Select functional mode clock source2. */ + kLPCMP_FunctionalClockSource3 = 3U, /*!< Select functional mode clock source3. */ +} lpcmp_functional_source_clock_t; +#endif /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */ + +#if defined(FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL) && FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL +/*! + * @brief Set the COUTA signal value when the window is closed. + */ +typedef enum _lpcmp_couta_signal +{ + kLPCMP_COUTASignalNoSet = 0U, /*!< NO set the COUTA signal value when the window is closed. */ + kLPCMP_COUTASignalLow = 1U, /*!< Set COUTA signal low(0) when the window is closed. */ + kLPCMP_COUTASignalHigh = 3U, /*!< Set COUTA signal high(1) when the window is closed. */ +} lpcmp_couta_signal_t; + +/*! + * @brief Set COUT event, which can close the active window in window mode. + */ +typedef enum _lpcmp_close_window_event +{ + kLPCMP_CLoseWindowEventNoSet = 0U, /*!< No Set COUT event, which can close the active window in window mode. */ + kLPCMP_CloseWindowEventRisingEdge = 1U, /*!< Set rising edge COUT signal as COUT event. */ + kLPCMP_CloseWindowEventFallingEdge = 3U, /*!< Set falling edge COUT signal as COUT event. */ + kLPCMP_CLoseWindowEventBothEdge = 5U, /*!< Set both rising and falling edge COUT signal as COUT event. */ +} lpcmp_close_window_event_t; +#endif /* FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL */ + +#if defined(FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE) && FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE +/*! + * @brief LPCMP round robin mode fixed mux port. + */ +typedef enum _lpcmp_roundrobin_fixedmuxport +{ + kLPCMP_FixedPlusMuxPort = 0U, /*!< Fixed plus mux port. */ + kLPCMP_FixedMinusMuxPort = 1U, /*!< Fixed minus mux port. */ +} lpcmp_roundrobin_fixedmuxport_t; + +/*! + * @brief LPCMP round robin mode clock source selection. + * + * Note: In different devices,the round robin mode clock source selection is different, + * please refer to the specific device Reference Manual for details. + */ +typedef enum _lpcmp_roundrobin_clock_source +{ + kLPCMP_RoundRobinClockSource0 = 0U, /*!< Select roundrobin mode clock source0. */ + kLPCMP_RoundRobinClockSource1 = 1U, /*!< Select roundrobin mode clock source1. */ + kLPCMP_RoundRobinClockSource2 = 2U, /*!< Select roundrobin mode clock source2. */ + kLPCMP_RoundRobinClockSource3 = 3U, /*!< Select roundrobin mode clock source3. */ +} lpcmp_roundrobin_clock_source_t; + +/*! + * @brief LPCMP round robin mode trigger source. + */ +typedef enum _lpcmp_roundrobin_trigger_source +{ + kLPCMP_TriggerSourceExternally = 0U, /*!< Select external trigger source. */ + kLPCMP_TriggerSourceInternally = 1U, /*!< Select internal trigger source. */ +} lpcmp_roundrobin_trigger_source_t; +#endif /* FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE */ + +/*! + * @brief Configure the filter. + */ +typedef struct _lpcmp_filter_config +{ + bool enableSample; /*!< Decide whether to use the external SAMPLE as a sampling clock input. */ + uint8_t filterSampleCount; /*!< Filter Sample Count. Available range is 1-7; 0 disables the filter. */ + uint8_t filterSamplePeriod; /*!< Filter Sample Period. The divider to the bus clock. Available range is 0-255. The + sampling clock must be at least 4 times slower than the system clock to the comparator. + So if enableSample is "false", filterSamplePeriod should be set greater than 4.*/ +} lpcmp_filter_config_t; + +/*! + * @brief configure the internal DAC. + */ +typedef struct _lpcmp_dac_config +{ + bool enableLowPowerMode; /*!< Decide whether to enable DAC low power mode. */ + lpcmp_dac_reference_voltage_source_t referenceVoltageSource; /*!< Internal DAC supply voltage reference source. */ + uint8_t DACValue; /*!< Value for the DAC Output Voltage. Different devices has different available range, + for specific values, please refer to the reference manual.*/ +} lpcmp_dac_config_t; + +/*! + * @brief Configures the comparator. + */ +typedef struct _lpcmp_config +{ +#if !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) + bool enableStopMode; /*!< Decide whether to enable the comparator when in STOP modes. */ +#endif /* !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) */ + + bool enableOutputPin; /*!< Decide whether to enable the comparator is available in selected pin. */ + bool useUnfilteredOutput; /*!< Decide whether to use unfiltered output. */ + bool enableInvertOutput; /*!< Decide whether to inverts the comparator output. */ + lpcmp_hysteresis_mode_t hysteresisMode; /*!< LPCMP hysteresis mode. */ + lpcmp_power_mode_t powerMode; /*!< LPCMP power mode. */ +#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL + lpcmp_functional_source_clock_t functionalSourceClock; /*!< Select LPCMP functional mode clock source. */ +#endif /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */ +} lpcmp_config_t; + +#if defined(FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL) && FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL +/*! + * @brief Configure the window mode control. + */ +typedef struct _lpcmp_window_control_config +{ + bool enableInvertWindowSignal; /*!< True: enable invert window signal, False: disable invert window signal. */ + lpcmp_couta_signal_t COUTASignal; /*!< Decide whether to define the COUTA signal value when the window is closed. */ + lpcmp_close_window_event_t closeWindowEvent; /*!< Decide whether to select COUT event signal edge defines + a COUT event to close window. */ +} lpcmp_window_control_config_t; +#endif /* FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL */ + +#if defined(FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE) && FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE +/*! + * @brief Configure the round robin mode. + */ +typedef struct _lpcmp_roundrobin_config +{ + uint8_t initDelayModules; /*!< Comparator and DAC initialization delay modulus, See Reference Manual and DataSheet + for specific value. */ + uint8_t sampleClockNumbers; /*!< Specify the number of the round robin clock cycles(0~3) to wait after scanning the + active channel before sampling the channel's comparison result. */ + uint8_t channelSampleNumbers; /*!< Specify the number of samples for one channel, note that channelSampleNumbers + must not smaller than sampleTimeThreshhold. */ + uint8_t sampleTimeThreshhold; /*!< Specify that for one channel, when (sampleTimeThreshhold + 1) sample results are + "1",the final result is "1", otherwise the final result is "0", note that the + sampleTimeThreshhold must not be larger than channelSampleNumbers. */ + lpcmp_roundrobin_clock_source_t roundrobinClockSource; /*!< Decide which clock source to + choose in round robin mode. */ + lpcmp_roundrobin_trigger_source_t roundrobinTriggerSource; /*!< Decide which trigger source to + choose in round robin mode. */ + lpcmp_roundrobin_fixedmuxport_t fixedMuxPort; /*!< Decide which mux port to choose as + fixed channel in round robin mode. */ + uint8_t fixedChannel; /*!< Indicate which channel of the fixed mux port is used in round robin mode. */ + uint8_t checkerChannelMask; /*!< Indicate which channel of the non-fixed mux port to check its voltage value in + round robin mode, for example, if checkerChannelMask set to 0x11U means select + channel 0 and channel 4 as checker channel.*/ +} lpcmp_roundrobin_config_t; +#endif /* FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and configuration + * @{ + */ + +/*! + * @brief Initialize the LPCMP + * + * This function initializes the LPCMP module. The operations included are: + * - Enabling the clock for LPCMP module. + * - Configuring the comparator. + * - Enabling the LPCMP module. + * Note: For some devices, multiple LPCMP instance share the same clock gate. In this case, to enable the clock for + * any instance enables all the LPCMPs. Check the chip reference manual for the clock assignment of the LPCMP. + * + * @param base LPCMP peripheral base address. + * @param config Pointer to "lpcmp_config_t" structure. + */ +void LPCMP_Init(LPCMP_Type *base, const lpcmp_config_t *config); + +/*! + * @brief De-initializes the LPCMP module. + * + * This function de-initializes the LPCMP module. The operations included are: + * - Disabling the LPCMP module. + * - Disabling the clock for LPCMP module. + * + * This function disables the clock for the LPCMP. + * Note: For some devices, multiple LPCMP instance shares the same clock gate. In this case, before disabling the + * clock for the LPCMP, ensure that all the LPCMP instances are not used. + * + * @param base LPCMP peripheral base address. + */ +void LPCMP_Deinit(LPCMP_Type *base); + +/*! + * @brief Gets an available pre-defined settings for the comparator's configuration. + * + * This function initializes the comparator configuration structure to these default values: + * @code + * config->enableStopMode = false; + * config->enableOutputPin = false; + * config->useUnfilteredOutput = false; + * config->enableInvertOutput = false; + * config->hysteresisMode = kLPCMP_HysteresisLevel0; + * config->powerMode = kLPCMP_LowSpeedPowerMode; + * config->functionalSourceClock = kLPCMP_FunctionalClockSource0; + * @endcode + * @param config Pointer to "lpcmp_config_t" structure. + */ +void LPCMP_GetDefaultConfig(lpcmp_config_t *config); + +/*! + * @brief Enable/Disable LPCMP module. + * + * @param base LPCMP peripheral base address. + * @param enable "true" means enable the module, and "false" means disable the module. + */ +static inline void LPCMP_Enable(LPCMP_Type *base, bool enable) +{ + if (enable) + { + base->CCR0 |= LPCMP_CCR0_CMP_EN_MASK; + } + else + { + base->CCR0 &= ~LPCMP_CCR0_CMP_EN_MASK; + } +} + +/*! + * @brief Select the input channels for LPCMP. This function determines which input + * is selected for the negative and positive mux. + * + * @param base LPCMP peripheral base address. + * @param positiveChannel Positive side input channel number. Available range is 0-7. + * @param negativeChannel Negative side input channel number. Available range is 0-7. + */ +void LPCMP_SetInputChannels(LPCMP_Type *base, uint32_t positiveChannel, uint32_t negativeChannel); + +/*! + * @brief Enables/disables the DMA request for rising/falling events. + * Normally, the LPCMP generates a CPU interrupt if there is a rising/falling event. When + * DMA support is enabled and the rising/falling interrupt is enabled , the rising/falling + * event forces a DMA transfer request rather than a CPU interrupt instead. + * + * @param base LPCMP peripheral base address. + * @param enable "true" means enable DMA support, and "false" means disable DMA support. + */ +static inline void LPCMP_EnableDMA(LPCMP_Type *base, bool enable) +{ + if (enable) + { + base->CCR1 |= LPCMP_CCR1_DMA_EN_MASK; + } + else + { + base->CCR1 &= ~LPCMP_CCR1_DMA_EN_MASK; + } +} + +/*! + * @brief Configures the filter. + * + * @param base LPCMP peripheral base address. + * @param config Pointer to "lpcmp_filter_config_t" structure. + */ +void LPCMP_SetFilterConfig(LPCMP_Type *base, const lpcmp_filter_config_t *config); + +/*! + * @brief Configure the internal DAC module. + * + * @param base LPCMP peripheral base address. + * @param config Pointer to "lpcmp_dac_config_t" structure. If config is "NULL", disable internal DAC. + */ +void LPCMP_SetDACConfig(LPCMP_Type *base, const lpcmp_dac_config_t *config); + +/*! + * @brief Enable the interrupts. + * + * @param base LPCMP peripheral base address. + * @param mask Mask value for interrupts. See "_lpcmp_interrupt_enable". + */ +static inline void LPCMP_EnableInterrupts(LPCMP_Type *base, uint32_t mask) +{ + base->IER |= mask; +} + +/*! + * @brief Disable the interrupts. + * + * @param base LPCMP peripheral base address. + * @param mask Mask value for interrupts. See "_lpcmp_interrupt_enable". + */ +static inline void LPCMP_DisableInterrupts(LPCMP_Type *base, uint32_t mask) +{ + base->IER &= ~mask; +} + +/*! + * @brief Get the LPCMP status flags. + * + * @param base LPCMP peripheral base address. + * + * @return Mask value for the asserted flags. See "_lpcmp_status_flags". + */ +static inline uint32_t LPCMP_GetStatusFlags(LPCMP_Type *base) +{ + return base->CSR; +} + +/*! + * @brief Clear the LPCMP status flags + * + * @param base LPCMP peripheral base address. + * @param mask Mask value for the flags. See "_lpcmp_status_flags". + */ +static inline void LPCMP_ClearStatusFlags(LPCMP_Type *base, uint32_t mask) +{ + base->CSR = mask; +} + +/*! @} */ + +/*! + * @name Window mode + * @{ + */ + +/*! + * @brief Enable/Disable window mode.When any windowed mode is active, COUTA is clocked by + * the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. + * The optionally inverted comparator output COUT_RAW is sampled on every bus clock + * when WINDOW=1 to generate COUTA. + * + * @param base LPCMP peripheral base address. + * @param enable "true" means enable window mode, and "false" means disable window mode. + */ +static inline void LPCMP_EnableWindowMode(LPCMP_Type *base, bool enable) +{ + if (enable) + { + base->CCR1 |= LPCMP_CCR1_WINDOW_EN_MASK; + } + else + { + base->CCR1 &= ~LPCMP_CCR1_WINDOW_EN_MASK; + } +} + +#if defined(FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL) && FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL +/*! + * @brief Configure the window control, users can use this API to implement operations on the window, + * such as inverting the window signal, setting the window closing event(only valid in windowing mode), + * and setting the COUTA signal after the window is closed(only valid in windowing mode). + * + * @param base LPCMP peripheral base address. + * @param config Pointer "lpcmp_window_control_config_t" structure. + */ +void LPCMP_SetWindowControl(LPCMP_Type *base, const lpcmp_window_control_config_t *config); +#endif /* FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL */ + +/*! @} */ + +#if defined(FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE) && FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE +/*! + * @name RoundRobin mode + * @{ + */ + +/*! + * @brief Configure the roundrobin mode. + * + * @param base LPCMP peripheral base address. + * @param config Pointer "lpcmp_roundrobin_config_t" structure. + */ +void LPCMP_SetRoundRobinConfig(LPCMP_Type *base, const lpcmp_roundrobin_config_t *config); + +/*! + * brief Configure the roundrobin internal timer reload value. + * + * param base LPCMP peripheral base address. + * param value RoundRobin internal timer reload value, allowed range:0x0UL-0xFFFFFFFUL. + */ +void LPCMP_SetRoundRobinInternalTimer(LPCMP_Type *base, uint32_t value); + +/*! + * @brief Enable/Disable roundrobin mode. + * + * @param base LPCMP peripheral base address. + * @param enable "true" means enable roundrobin mode, and "false" means disable roundrobin mode. + */ +static inline void LPCMP_EnableRoundRobinMode(LPCMP_Type *base, bool enable) +{ + if (enable) + { + base->RRCR0 |= LPCMP_RRCR0_RR_EN_MASK; + } + else + { + base->RRCR0 &= ~LPCMP_RRCR0_RR_EN_MASK; + } +} + +/*! + * @brief Enable/Disable roundrobin internal timer, note that this function is only valid + * when using the internal trigger source. + * + * @param base LPCMP peripheral base address. + * @param enable "true" means enable roundrobin internal timer, and "false" means disable roundrobin internal timer. + */ +static inline void LPCMP_EnableRoundRobinInternalTimer(LPCMP_Type *base, bool enable) +{ + if (enable) + { + base->RRCR2 |= LPCMP_RRCR2_RR_TIMER_EN_MASK; + } + else + { + base->RRCR2 &= ~LPCMP_RRCR2_RR_TIMER_EN_MASK; + } +} + +/*! + * @brief Set preset value for all channels, users can set all channels' preset vaule through this API, + * for example, if the mask set to 0x03U means channel0 and channel2's preset value set to 1U and other + * channels' preset value set to 0U. + * + * @param base LPCMP peripheral base address. + * @param mask Mask of channel index. + */ +static inline void LPCMP_SetPreSetValue(LPCMP_Type *base, uint8_t mask) +{ + base->RRCSR = (uint32_t)mask; +} + +/*! + * @brief Get comparison results for all channels, users can get all channels' comparison + * results through this API. + * + * @param base LPCMP peripheral base address. + * @return return All channels' comparison result. + */ +static inline uint8_t LPCMP_GetComparisonResult(LPCMP_Type *base) +{ + return (uint8_t)base->RRCSR; +} + +/*! + * @brief Clear input changed flags for single channel or multiple channels, users can clear + * input changed flag of a single channel or multiple channels through this API, for example, + * if the mask set to 0x03U means clear channel0 and channel2's input changed flags. + * + * @param base LPCMP peripheral base address. + * @param mask Mask of channel index. + */ +static inline void LPCMP_ClearInputChangedFlags(LPCMP_Type *base, uint8_t mask) +{ + base->RRSR = (uint32_t)mask; +} + +/*! + * @brief Get input changed flags for all channels, Users can get all channels' input changed + * flags through this API. + * + * @param base LPCMP peripheral base address. + * @return return All channels' changed flag. + */ +static inline uint8_t LPCMP_GetInputChangedFlags(LPCMP_Type *base) +{ + return (uint8_t)base->RRSR; +} + +/*! @} */ + +#endif /* FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* FSL_LPCMP_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpi2c.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpi2c.c new file mode 100644 index 00000000000..1c49f2e4a2d --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpi2c.c @@ -0,0 +1,2715 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpi2c.h" +#include +#include + +/* + * $Coverage Justification Reference$ + * + * $Justification fsl_lpi2c_c_ref_1$ + * The default branch cannot be executed in any circumstances, it is only added to avoid MISRA violation. + * + * $Justification fsl_lpi2c_c_ref_2$ + * Two instances failed to simulate #kStatus_LPI2C_Busy. + * + * $Justification fsl_lpi2c_c_ref_3$ + * When the transmission is completed (remaining == 0), the SDF and RSF will be set, and the flags are get before + * that(get before set), it will be over when the next cycle occurs, the first condition cannot be verified, and the + * remaining will not be verified.(will improve) + * + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpi2c" +#endif + +#if defined(LPI2C_RSTS) +#define LPI2C_RESETS_ARRAY LPI2C_RSTS +#endif + +/*! @brief LPI2C master fifo commands. */ +enum +{ + kTxDataCmd = LPI2C_MTDR_CMD(0x0U), /*!< Transmit DATA[7:0] */ + kRxDataCmd = LPI2C_MTDR_CMD(0X1U), /*!< Receive (DATA[7:0] + 1) bytes */ + kStopCmd = LPI2C_MTDR_CMD(0x2U), /*!< Generate STOP condition */ + kStartCmd = LPI2C_MTDR_CMD(0x4U), /*!< Generate(repeated) START and transmit address in DATA[[7:0] */ +}; + +/*! + * @brief Default watermark values. + * + * The default watermarks are set to zero. + */ +enum +{ + kDefaultTxWatermark = 0, + kDefaultRxWatermark = 0, +}; + +/*! @brief States for the state machine used by transactional APIs. */ +enum +{ + kIdleState = 0, + kSendCommandState, + kIssueReadCommandState, + kTransferDataState, + kStopState, + kWaitForCompletionState, +}; + +/*! + * @brief Structure definition for variables that passed as parameters in LPI2C_RunTransferStateMachine. + * The structure is private. + */ +typedef struct _lpi2c_state_machine_param +{ + bool state_complete; /*!< status of complete */ + size_t rxCount; /*!< rx count */ + size_t txCount; /*!< tx count */ + uint32_t status; /*!< machine status */ +} lpi2c_state_machine_param_t; + +/*! @brief Typedef for slave interrupt handler. */ +typedef void (*lpi2c_slave_isr_t)(LPI2C_Type *base, lpi2c_slave_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static uint32_t LPI2C_GetCyclesForWidth( + uint32_t sourceClock_Hz, uint32_t width_ns, uint32_t minCycles, uint32_t maxCycles, uint32_t prescaler); + +static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base); + +static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_handle_t *handle, bool *isDone); + +static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle); + +static status_t LPI2C_SlaveCheckAndClearError(LPI2C_Type *base, uint32_t flags); + +static void LPI2C_CommonIRQHandler(LPI2C_Type *base, uint32_t instance); + +/*! + * @brief introduce function LPI2C_TransferStateMachineSendCommandState. + * This function was deal with Send Command State. + * + * @param base The I2C peripheral base address. + * @param handle Master nonblocking driver handle. + * @param variable_set Pass the address of the parent function variable. + */ +static void LPI2C_TransferStateMachineSendCommand(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_state_machine_param_t *stateParams); + +/*! + * @brief introduce function LPI2C_TransferStateMachineIssueReadCommandState. + * This function was deal with Issue Read Command State. + * + * @param base The I2C peripheral base address. + * @param handle Master nonblocking driver handle. + * @param stateParams Pass the address of the parent function variable. + */ +static void LPI2C_TransferStateMachineReadCommand(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_state_machine_param_t *stateParams); + +/*! + * @brief introduce function LPI2C_TransferStateMachineTransferDataState. + * This function was deal with init Transfer Data State. + * + * @param base The I2C peripheral base address. + * @param handle Master nonblocking driver handle. + * @param stateParams Pass the address of the parent function variable. + */ +static void LPI2C_TransferStateMachineTransferData(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_state_machine_param_t *stateParams); + +/*! + * @brief introduce function LPI2C_TransferStateMachineStopState. + * This function was deal with Stop State. + * + * @param base The I2C peripheral base address. + * @param handle Master nonblocking driver handle. + * @param stateParams Pass the address of the parent function variable. + * @param[out] isDone Set to true if the transfer has completed. + */ +static void LPI2C_TransferStateMachineStopState(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_state_machine_param_t *stateParams, + bool *isDone); + +/*! + * @brief introduce function LPI2C_TransferStateMachineWaitState. + * This function was deal with Wait For Completion State. + * + * @param base The I2C peripheral base address. + * @param handle Master nonblocking driver handle. + * @param stateParams Pass the address of the parent function variable. + * @param[out] isDone Set to true if the transfer has completed. + */ +static void LPI2C_TransferStateMachineWaitState(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_state_machine_param_t *stateParams, + bool *isDone); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Array to map LPI2C instance number to base pointer. */ +static LPI2C_Type *const kLpi2cBases[] = LPI2C_BASE_PTRS; + +/*! @brief Array to map LPI2C instance number to IRQ number, used internally for LPI2C master interrupt and EDMA +transactional APIs. */ +IRQn_Type const kLpi2cIrqs[] = LPI2C_IRQS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map LPI2C instance number to clock gate enum. */ +static clock_ip_name_t const kLpi2cClocks[] = LPI2C_CLOCKS; + +#if defined(LPI2C_PERIPH_CLOCKS) +/*! @brief Array to map LPI2C instance number to pheripheral clock gate enum. */ +static const clock_ip_name_t kLpi2cPeriphClocks[] = LPI2C_PERIPH_CLOCKS; +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief Pointer to master IRQ handler for each instance, used internally for LPI2C master interrupt and EDMA +transactional APIs. */ +lpi2c_master_isr_t s_lpi2cMasterIsr; + +/*! @brief Pointers to master handles for each instance, used internally for LPI2C master interrupt and EDMA +transactional APIs. */ +void *s_lpi2cMasterHandle[ARRAY_SIZE(kLpi2cBases)]; + +/*! @brief Pointer to slave IRQ handler for each instance. */ +static lpi2c_slave_isr_t s_lpi2cSlaveIsr; + +/*! @brief Pointers to slave handles for each instance. */ +static lpi2c_slave_handle_t *s_lpi2cSlaveHandle[ARRAY_SIZE(kLpi2cBases)]; + +#if defined(LPI2C_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_lpi2cResets[] = LPI2C_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * param base The LPI2C peripheral base address. + * return LPI2C instance number starting from 0. + */ +uint32_t LPI2C_GetInstance(LPI2C_Type *base) +{ + uint32_t instance; + for (instance = 0U; instance < ARRAY_SIZE(kLpi2cBases); ++instance) + { + if (kLpi2cBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(kLpi2cBases)); + return instance; +} + +/*! + * @brief Computes a cycle count for a given time in nanoseconds. + * @param sourceClock_Hz LPI2C functional clock frequency in Hertz. + * @param width_ns Desired with in nanoseconds. + * @param minCycles Minimum cycle count. + * @param maxCycles Maximum cycle count. + * @param prescaler LPI2C prescaler setting. If the cycle period is not affected by the prescaler value, set it to 0. + */ +static uint32_t LPI2C_GetCyclesForWidth( + uint32_t sourceClock_Hz, uint32_t width_ns, uint32_t minCycles, uint32_t maxCycles, uint32_t prescaler) +{ + assert(sourceClock_Hz > 0U); + + uint32_t divider = 1U; + + while (prescaler != 0U) + { + divider *= 2U; + prescaler--; + } + + uint32_t busCycle_ns = 1000000U / (sourceClock_Hz / divider / 1000U); + /* Calculate the cycle count, round up the calculated value. */ + uint32_t cycles = (width_ns * 10U / busCycle_ns + 5U) / 10U; + + /* If the calculated value is smaller than the minimum value, use the minimum value */ + if (cycles < minCycles) + { + cycles = minCycles; + } + /* If the calculated value is larger than the maximum value, use the maxmum value */ + if (cycles > maxCycles) + { + cycles = maxCycles; + } + + return cycles; +} + +/*! + * brief Convert provided flags to status code, and clear any errors if present. + * param base The LPI2C peripheral base address. + * param status Current status flags value that will be checked. + * retval #kStatus_Success + * retval #kStatus_LPI2C_PinLowTimeout + * retval #kStatus_LPI2C_ArbitrationLost + * retval #kStatus_LPI2C_Nak + * retval #kStatus_LPI2C_FifoError + */ +status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status) +{ + status_t result = kStatus_Success; + + /* Check for error. These errors cause a stop to automatically be sent. We must */ + /* clear the errors before a new transfer can start. */ + status &= (uint32_t)kLPI2C_MasterErrorFlags; + if (0U != status) + { + /* Select the correct error code. Ordered by severity, with bus issues first. */ + if (0U != (status & (uint32_t)kLPI2C_MasterPinLowTimeoutFlag)) + { + result = kStatus_LPI2C_PinLowTimeout; + } + else if (0U != (status & (uint32_t)kLPI2C_MasterArbitrationLostFlag)) + { + result = kStatus_LPI2C_ArbitrationLost; + } + else if (0U != (status & (uint32_t)kLPI2C_MasterNackDetectFlag)) + { + result = kStatus_LPI2C_Nak; + } + /* + * $Branch Coverage Justification$ + * Before that, the state was stripped of other attributes, and it only contained the four brother flags.(will + * improve) + */ + else if (0U != (status & (uint32_t)kLPI2C_MasterFifoErrFlag)) + { + result = kStatus_LPI2C_FifoError; + } + else + { + ; /* Intentional empty */ + } + + /* Clear the flags. */ + LPI2C_MasterClearStatusFlags(base, status); + + if (((base->MCFGR1 & LPI2C_MCFGR1_IGNACK_MASK) != 0x00U) && (result == kStatus_LPI2C_Nak)) + { + /* ERR051119: If IGNACK was set and nak detect , we will ignore the Nak status */ + result = kStatus_Success; + } + else + { + /* Reset fifos. These flags clear automatically.*/ + base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; + } + } + else + { + ; /* Intentional empty */ + } + + return result; +} + +/*! + * @brief Wait until there is room in the tx fifo. + * @param base The LPI2C peripheral base address. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_PinLowTimeout + * @retval #kStatus_LPI2C_ArbitrationLost + * @retval #kStatus_LPI2C_Nak + * @retval #kStatus_LPI2C_FifoError + */ +static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base) +{ + status_t result = kStatus_Success; + uint32_t status; + size_t txCount; + size_t txFifoSize = (size_t)FSL_FEATURE_LPI2C_FIFO_SIZEn(base); + +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + do + { + /* Get the number of words in the tx fifo and compute empty slots. */ + LPI2C_MasterGetFifoCounts(base, NULL, &txCount); + txCount = txFifoSize - txCount; + + /* Check for error flags. */ + status = LPI2C_MasterGetStatusFlags(base); + result = LPI2C_MasterCheckAndClearError(base, status); + if (kStatus_Success != result) + { + break; + } +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while ((0U == txCount) && (0U != waitTimes)); + + if (0U == waitTimes) + { + result = kStatus_LPI2C_Timeout; + } +#else + } while (0U == txCount); +#endif + + return result; +} + +/*! + * brief Make sure the bus isn't already busy. + * + * A busy bus is allowed if we are the one driving it. + * + * param base The LPI2C peripheral base address. + * retval #kStatus_Success + * retval #kStatus_LPI2C_Busy + */ +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +status_t LPI2C_CheckForBusyBus(LPI2C_Type *base) +{ + status_t ret = kStatus_Success; + + uint32_t status = LPI2C_MasterGetStatusFlags(base); + /* + * $Branch Coverage Justification$ + * $ref fsl_lpi2c_c_ref_2$ + */ + if ((0U != (status & (uint32_t)kLPI2C_MasterBusBusyFlag)) && (0U == (status & (uint32_t)kLPI2C_MasterBusyFlag))) + { + ret = kStatus_LPI2C_Busy; + } + + return ret; +} + +/*! + * brief Provides a default configuration for the LPI2C master peripheral. + * + * This function provides the following default configuration for the LPI2C master peripheral: + * code + * masterConfig->enableMaster = true; + * masterConfig->debugEnable = false; + * masterConfig->ignoreAck = false; + * masterConfig->pinConfig = kLPI2C_2PinOpenDrain; + * masterConfig->baudRate_Hz = 100000U; + * masterConfig->busIdleTimeout_ns = 0U; + * masterConfig->pinLowTimeout_ns = 0U; + * masterConfig->sdaGlitchFilterWidth_ns = 0U; + * masterConfig->sclGlitchFilterWidth_ns = 0U; + * masterConfig->hostRequest.enable = false; + * masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; + * masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; + * endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with LPI2C_MasterInit(). + * + * param[out] masterConfig User provided configuration structure for default values. Refer to #lpi2c_master_config_t. + */ +void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig) +{ + /* Initializes the configure structure to zero. */ + (void)memset(masterConfig, 0, sizeof(*masterConfig)); + + masterConfig->enableMaster = true; + masterConfig->debugEnable = false; + masterConfig->enableDoze = true; + masterConfig->ignoreAck = false; + masterConfig->pinConfig = kLPI2C_2PinOpenDrain; + masterConfig->baudRate_Hz = 100000U; + masterConfig->busIdleTimeout_ns = 0U; /* Set to 0 to disable the function */ + masterConfig->pinLowTimeout_ns = 0U; /* Set to 0 to disable the function */ + masterConfig->sdaGlitchFilterWidth_ns = 0U; /* Set to 0 to disable the function */ + masterConfig->sclGlitchFilterWidth_ns = 0U; /* Set to 0 to disable the function */ + masterConfig->hostRequest.enable = false; + masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; + masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; +} + +/*! + * brief Initializes the LPI2C master peripheral. + * + * This function enables the peripheral clock and initializes the LPI2C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * param base The LPI2C peripheral base address. + * param masterConfig User provided peripheral configuration. Use LPI2C_MasterGetDefaultConfig() to get a set of + * defaults + * that you can override. + * param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz) +{ + uint32_t prescaler; + uint32_t cycles; + uint32_t cfgr2; + uint32_t value; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPI2C_GetInstance(base); + + /* Ungate the clock. */ + (void)CLOCK_EnableClock(kLpi2cClocks[instance]); +#if defined(LPI2C_PERIPH_CLOCKS) + /* Ungate the functional clock in initialize function. */ + CLOCK_EnableClock(kLpi2cPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(LPI2C_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_lpi2cResets[LPI2C_GetInstance(base)]); +#endif + + /* Reset peripheral before configuring it. */ + LPI2C_MasterReset(base); + + /* Doze bit: 0 is enable, 1 is disable */ + base->MCR = LPI2C_MCR_DBGEN(masterConfig->debugEnable) | LPI2C_MCR_DOZEN(!(masterConfig->enableDoze)); + + /* host request */ + value = base->MCFGR0; + value &= (~(LPI2C_MCFGR0_HREN_MASK | LPI2C_MCFGR0_HRPOL_MASK | LPI2C_MCFGR0_HRSEL_MASK)); + value |= LPI2C_MCFGR0_HREN(masterConfig->hostRequest.enable) | + LPI2C_MCFGR0_HRPOL(masterConfig->hostRequest.polarity) | + LPI2C_MCFGR0_HRSEL(masterConfig->hostRequest.source); + base->MCFGR0 = value; + + /* pin config and ignore ack */ + value = base->MCFGR1; + value &= ~(LPI2C_MCFGR1_PINCFG_MASK | LPI2C_MCFGR1_IGNACK_MASK); + value |= LPI2C_MCFGR1_PINCFG(masterConfig->pinConfig); + value |= LPI2C_MCFGR1_IGNACK(masterConfig->ignoreAck); + base->MCFGR1 = value; + + LPI2C_MasterSetWatermarks(base, (size_t)kDefaultTxWatermark, (size_t)kDefaultRxWatermark); + + /* Configure glitch filters. */ + cfgr2 = base->MCFGR2; + if (0U != (masterConfig->sdaGlitchFilterWidth_ns)) + { + /* Calculate SDA filter width. The width is equal to FILTSDA cycles of functional clock. + And set FILTSDA to 0 disables the fileter, so the min value is 1. */ + cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->sdaGlitchFilterWidth_ns, 1U, + (LPI2C_MCFGR2_FILTSDA_MASK >> LPI2C_MCFGR2_FILTSDA_SHIFT), 0U); + cfgr2 &= ~LPI2C_MCFGR2_FILTSDA_MASK; + cfgr2 |= LPI2C_MCFGR2_FILTSDA(cycles); + } + if (0U != masterConfig->sclGlitchFilterWidth_ns) + { + /* Calculate SDL filter width. The width is equal to FILTSCL cycles of functional clock. + And set FILTSCL to 0 disables the fileter, so the min value is 1. */ + cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->sclGlitchFilterWidth_ns, 1U, + (LPI2C_MCFGR2_FILTSCL_MASK >> LPI2C_MCFGR2_FILTSCL_SHIFT), 0U); + cfgr2 &= ~LPI2C_MCFGR2_FILTSCL_MASK; + cfgr2 |= LPI2C_MCFGR2_FILTSCL(cycles); + } + base->MCFGR2 = cfgr2; + + /* Configure baudrate after the SDA/SCL glitch filter setting, + since the baudrate calculation needs them as parameter. */ + LPI2C_MasterSetBaudRate(base, sourceClock_Hz, masterConfig->baudRate_Hz); + + /* Configure bus idle and pin low timeouts after baudrate setting, + since the timeout calculation needs prescaler as parameter. */ + prescaler = (base->MCFGR1 & LPI2C_MCFGR1_PRESCALE_MASK) >> LPI2C_MCFGR1_PRESCALE_SHIFT; + + if (0U != (masterConfig->busIdleTimeout_ns)) + { + /* Calculate bus idle timeout value. The value is equal to BUSIDLE cycles of functional clock divided by + prescaler. And set BUSIDLE to 0 disables the fileter, so the min value is 1. */ + cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->busIdleTimeout_ns, 1U, + (LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler); + base->MCFGR2 = (base->MCFGR2 & (~LPI2C_MCFGR2_BUSIDLE_MASK)) | LPI2C_MCFGR2_BUSIDLE(cycles); + } + if (0U != masterConfig->pinLowTimeout_ns) + { + /* Calculate bus pin low timeout value. The value is equal to PINLOW cycles of functional clock divided by + prescaler. And set PINLOW to 0 disables the fileter, so the min value is 1. */ + cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->pinLowTimeout_ns / 256U, 1U, + (LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler); + base->MCFGR3 = (base->MCFGR3 & ~LPI2C_MCFGR3_PINLOW_MASK) | LPI2C_MCFGR3_PINLOW(cycles); + } + + LPI2C_MasterEnable(base, masterConfig->enableMaster); +} + +/*! + * brief Deinitializes the LPI2C master peripheral. + * + * This function disables the LPI2C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The LPI2C peripheral base address. + */ +void LPI2C_MasterDeinit(LPI2C_Type *base) +{ + /* Restore to reset state. */ + LPI2C_MasterReset(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPI2C_GetInstance(base); + + /* Gate clock. */ + (void)CLOCK_DisableClock(kLpi2cClocks[instance]); +#if defined(LPI2C_PERIPH_CLOCKS) + /* Gate the functional clock. */ + CLOCK_DisableClock(kLpi2cPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Configures LPI2C master data match feature. + * + * param base The LPI2C peripheral base address. + * param matchConfig Settings for the data match feature. + */ +void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *matchConfig) +{ + /* Disable master mode. */ + bool wasEnabled = (0U != ((base->MCR & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT)); + LPI2C_MasterEnable(base, false); + + base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_MATCFG_MASK) | LPI2C_MCFGR1_MATCFG(matchConfig->matchMode); + base->MCFGR0 = (base->MCFGR0 & ~LPI2C_MCFGR0_RDMO_MASK) | LPI2C_MCFGR0_RDMO(matchConfig->rxDataMatchOnly); + base->MDMR = LPI2C_MDMR_MATCH0(matchConfig->match0) | LPI2C_MDMR_MATCH1(matchConfig->match1); + + /* Restore master mode. */ + if (wasEnabled) + { + LPI2C_MasterEnable(base, true); + } +} + +/*! + * brief Sets the I2C bus frequency for master transactions. + * + * The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * note Please note that the second parameter is the clock frequency of LPI2C module, the third + * parameter means user configured bus baudrate, this implementation is different from other I2C drivers + * which use baudrate configuration as second parameter and source clock frequency as third parameter. + * + * param base The LPI2C peripheral base address. + * param sourceClock_Hz LPI2C functional clock frequency in Hertz. + * param baudRate_Hz Requested bus frequency in Hertz. + */ +void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz) +{ + bool wasEnabled; + uint8_t filtScl = (uint8_t)((base->MCFGR2 & LPI2C_MCFGR2_FILTSCL_MASK) >> LPI2C_MCFGR2_FILTSCL_SHIFT); + + uint8_t divider = 1U; + uint8_t bestDivider = 1U; + uint8_t prescale = 0U; + uint8_t bestPre = 0U; + + uint8_t clkCycle; + uint8_t bestclkCycle = 0U; + + uint32_t absError = 0U; + uint32_t bestError = 0xffffffffu; + uint32_t computedRate; + + uint32_t tmpReg = 0U; + + /* Disable master mode. */ + wasEnabled = (0U != ((base->MCR & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT)); + LPI2C_MasterEnable(base, false); + + /* Baud rate = (sourceClock_Hz / 2 ^ prescale) / (CLKLO + 1 + CLKHI + 1 + SCL_LATENCY) + * SCL_LATENCY = ROUNDDOWN((2 + FILTSCL) / (2 ^ prescale)) + */ + for (prescale = 0U; prescale <= 7U; prescale++) + { + /* Calculate the clkCycle, clkCycle = CLKLO + CLKHI, divider = 2 ^ prescale */ + clkCycle = (uint8_t)((10U * sourceClock_Hz / divider / baudRate_Hz + 5U) / 10U - (2U + filtScl) / divider - 2U); + /* According to register description, The max value for CLKLO and CLKHI is 63. + however to meet the I2C specification of tBUF, CLKHI should be less than + clkCycle - 0.52 x sourceClock_Hz / baudRate_Hz / divider + 1U. Refer to the comment of the tmpHigh's + calculation for details. So we have: + CLKHI < clkCycle - 0.52 x sourceClock_Hz / baudRate_Hz / divider + 1U, + clkCycle = CLKHI + CLKLO and + sourceClock_Hz / baudRate_Hz / divider = clkCycle + 2 + ROUNDDOWN((2 + FILTSCL) / divider), + we can come up with: CLKHI < 0.92 x CLKLO - ROUNDDOWN(2 + FILTSCL) / divider + so the max boundary of CLKHI should be 0.92 x 63 - ROUNDDOWN(2 + FILTSCL) / divider, + and the max boundary of clkCycle is 1.92 x 63 - ROUNDDOWN(2 + FILTSCL) / divider. */ + if (clkCycle > (120U - (2U + filtScl) / divider)) + { + divider *= 2U; + continue; + } + /* Calculate the computed baudrate and compare it with the desired baudrate */ + computedRate = (sourceClock_Hz / (uint32_t)divider) / + ((uint32_t)clkCycle + 2U + (2U + (uint32_t)filtScl) / (uint32_t)divider); + absError = baudRate_Hz > computedRate ? baudRate_Hz - computedRate : computedRate - baudRate_Hz; + if (absError < bestError) + { + bestPre = prescale; + bestDivider = divider; + bestclkCycle = clkCycle; + bestError = absError; + + /* If the error is 0, then we can stop searching because we won't find a better match. */ + if (absError == 0U) + { + break; + } + } + divider *= 2U; + } + + /* SCL low time tLO should be larger than or equal to SCL high time tHI: + tLO = ((CLKLO + 1) x (2 ^ PRESCALE)) >= tHI = ((CLKHI + 1 + SCL_LATENCY) x (2 ^ PRESCALE)), + which is CLKLO >= CLKHI + (2U + filtScl) / bestDivider. + Also since bestclkCycle = CLKLO + CLKHI, bestDivider = 2 ^ PRESCALE + which makes CLKHI <= (bestclkCycle - (2U + filtScl) / bestDivider) / 2U. + + The max tBUF should be at least 0.52 times of the SCL clock cycle: + tBUF = ((CLKLO + 1) x (2 ^ PRESCALE) / sourceClock_Hz) > (0.52 / baudRate_Hz), + plus bestDivider = 2 ^ PRESCALE, bestclkCycle = CLKLO + CLKHI we can come up with + CLKHI <= (bestclkCycle - 0.52 x sourceClock_Hz / baudRate_Hz / bestDivider + 1U). + In this case to get a safe CLKHI calculation, we can assume: + */ + uint8_t tmpHigh = (bestclkCycle - (2U + filtScl) / bestDivider) / 2U; + while (tmpHigh > (bestclkCycle - 52U * sourceClock_Hz / baudRate_Hz / bestDivider / 100U + 1U)) + { + tmpHigh = tmpHigh - 1U; + } + + /* Calculate DATAVD and SETHOLD. + To meet the timing requirement of I2C spec for standard mode, fast mode and fast mode plus: */ + /* The min tHD:STA/tSU:STA/tSU:STO should be at least 0.4 times of the SCL clock cycle, use 0.5 to be safe: + tHD:STA = ((SETHOLD + 1) x (2 ^ PRESCALE) / sourceClock_Hz) > (0.5 / baudRate_Hz), bestDivider = 2 ^ PRESCALE */ + uint8_t tmpHold = (uint8_t)(sourceClock_Hz / baudRate_Hz / bestDivider / 2U) - 1U; + + /* The max tVD:DAT/tVD:ACK/tHD:DAT should be at most 0.345 times of the SCL clock cycle, use 0.25 to be safe: + tVD:DAT = ((DATAVD + 1) x (2 ^ PRESCALE) / sourceClock_Hz) < (0.25 / baudRate_Hz), bestDivider = 2 ^ PRESCALE */ + uint8_t tmpDataVd = (uint8_t)(sourceClock_Hz / baudRate_Hz / bestDivider / 4U) - 1U; + + /* The min tSU:DAT should be at least 0.05 times of the SCL clock cycle: + tSU:DAT = ((2 + FILTSDA + 2 ^ PRESCALE) / sourceClock_Hz) >= (0.05 / baud), + plus bestDivider = 2 ^ PRESCALE, we can come up with: + FILTSDA >= (0.05 x sourceClock_Hz / baudRate_Hz - bestDivider - 2) */ + if ((sourceClock_Hz / baudRate_Hz / 20U) > (bestDivider + 2U)) + { + /* Read out the FILTSDA configuration, if it is smaller than expected, change the setting. */ + uint8_t filtSda = (uint8_t)((base->MCFGR2 & LPI2C_MCFGR2_FILTSDA_MASK) >> LPI2C_MCFGR2_FILTSDA_SHIFT); + if (filtSda < (sourceClock_Hz / baudRate_Hz / 20U - bestDivider - 2U)) + { + filtSda = (uint8_t)(sourceClock_Hz / baudRate_Hz / 20U) - bestDivider - 2U; + } + base->MCFGR2 = (base->MCFGR2 & ~LPI2C_MCFGR2_FILTSDA_MASK) | LPI2C_MCFGR2_FILTSDA(filtSda); + } + + /* Set CLKHI, CLKLO, SETHOLD, DATAVD value. */ + tmpReg = LPI2C_MCCR0_CLKHI((uint32_t)tmpHigh) | + LPI2C_MCCR0_CLKLO((uint32_t)((uint32_t)bestclkCycle - (uint32_t)tmpHigh)) | + LPI2C_MCCR0_SETHOLD((uint32_t)tmpHold) | LPI2C_MCCR0_DATAVD((uint32_t)tmpDataVd); + base->MCCR0 = tmpReg; + + /* Set PRESCALE value. */ + base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_PRESCALE_MASK) | LPI2C_MCFGR1_PRESCALE(bestPre); + + /* Restore master mode. */ + if (wasEnabled) + { + LPI2C_MasterEnable(base, true); + } +} + +/*! + * brief Sends a START signal and slave address on the I2C bus. + * + * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure + * that another master is not occupying the bus. Then a START signal is transmitted, followed by the + * 7-bit address specified in the a address parameter. Note that this function does not actually wait + * until the START and address are successfully sent on the bus before returning. + * + * param base The LPI2C peripheral base address. + * param address 7-bit slave device address, in bits [6:0]. + * param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + */ +status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir) +{ + /* Return an error if the bus is already in use not by us. */ + status_t result = LPI2C_CheckForBusyBus(base); + /* + * $Branch Coverage Justification$ + * $ref fsl_lpi2c_c_ref_2$ + */ + if (kStatus_Success == result) + { + /* Clear all flags. */ + LPI2C_MasterClearStatusFlags(base, (uint32_t)kLPI2C_MasterClearFlags); + + /* Turn off auto-stop option. */ + base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; + + /* Wait until there is room in the fifo. */ + result = LPI2C_MasterWaitForTxReady(base); + if (kStatus_Success == result) + { + /* Issue start command. */ + base->MTDR = (uint32_t)kStartCmd | (((uint32_t)address << 1U) | (uint32_t)dir); + } + } + + return result; +} + +/*! + * brief Sends a STOP signal on the I2C bus. + * + * This function does not return until the STOP signal is seen on the bus, or an error occurs. + * + * param base The LPI2C peripheral base address. + * retval #kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterStop(LPI2C_Type *base) +{ + /* Wait until there is room in the fifo. */ + status_t result = LPI2C_MasterWaitForTxReady(base); + if (kStatus_Success == result) + { + /* Send the STOP signal */ + base->MTDR = (uint32_t)kStopCmd; + + /* Wait for the stop detected flag to set, indicating the transfer has completed on the bus. */ + /* Also check for errors while waiting. */ +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + +#if I2C_RETRY_TIMES != 0U + while ((result == kStatus_Success) && (0U != waitTimes)) + { + waitTimes--; +#else + while (result == kStatus_Success) + { +#endif + uint32_t status = LPI2C_MasterGetStatusFlags(base); + + /* Check for error flags. */ + result = LPI2C_MasterCheckAndClearError(base, status); + + /* Check if the stop was sent successfully. */ + if ((0U != (status & (uint32_t)kLPI2C_MasterStopDetectFlag)) && + (0U != (status & (uint32_t)kLPI2C_MasterTxReadyFlag))) + { + LPI2C_MasterClearStatusFlags(base, (uint32_t)kLPI2C_MasterStopDetectFlag); + break; + } + } + +#if I2C_RETRY_TIMES != 0U + if (0U == waitTimes) + { + result = kStatus_LPI2C_Timeout; + } +#endif + } + + return result; +} + +/*! + * brief Performs a polling receive transfer on the I2C bus. + * + * param base The LPI2C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * retval #kStatus_Success Data was received successfully. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize) +{ + assert(NULL != rxBuff); + + status_t result = kStatus_Success; + uint8_t *buf; + size_t tmpRxSize = rxSize; +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes; +#endif + + /* Check transfer data size. */ + if (rxSize > ((size_t)256 * (size_t)FSL_FEATURE_LPI2C_FIFO_SIZEn(base))) + { + return kStatus_InvalidArgument; + } + + /* Handle empty read. */ + if (rxSize != 0U) + { + /* Wait until there is room in the command fifo. */ + result = LPI2C_MasterWaitForTxReady(base); + if (kStatus_Success == result) + { + /* Issue command to receive data. A single write to MTDR can issue read operation of 0xFFU + 1 byte of data + at most, so when the rxSize is larger than 0x100U, push multiple read commands to MTDR until rxSize is + reached. */ + while (tmpRxSize != 0U) + { + if (tmpRxSize > 256U) + { + base->MTDR = (uint32_t)(kRxDataCmd) | (uint32_t)LPI2C_MTDR_DATA(0xFFU); + tmpRxSize -= 256U; + } + else + { + base->MTDR = (uint32_t)(kRxDataCmd) | (uint32_t)LPI2C_MTDR_DATA(tmpRxSize - 1U); + tmpRxSize = 0U; + } + } + + /* Receive data */ + buf = (uint8_t *)rxBuff; + while (0U != (rxSize--)) + { +#if I2C_RETRY_TIMES != 0U + waitTimes = I2C_RETRY_TIMES; +#endif + /* Read LPI2C receive fifo register. The register includes a flag to indicate whether */ + /* the FIFO is empty, so we can both get the data and check if we need to keep reading */ + /* using a single register read. */ + uint32_t value = 0U; + do + { + /* Check for errors. */ + result = LPI2C_MasterCheckAndClearError(base, LPI2C_MasterGetStatusFlags(base)); + if (kStatus_Success != result) + { + break; + } + + value = base->MRDR; +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while ((0U != (value & LPI2C_MRDR_RXEMPTY_MASK)) && (0U != waitTimes)); + if (0U == waitTimes) + { + result = kStatus_LPI2C_Timeout; + } +#else + } while (0U != (value & LPI2C_MRDR_RXEMPTY_MASK)); +#endif + if ((status_t)kStatus_Success != result) + { + break; + } + + *buf++ = (uint8_t)(value & LPI2C_MRDR_DATA_MASK); + } + } + } + + return result; +} + +/*! + * brief Performs a polling send transfer on the I2C bus. + * + * Sends up to a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_LPI2C_Nak. + * + * param base The LPI2C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * retval #kStatus_Success Data was sent successfully. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_LPI2C_FifoError FIFO under run or over run. + * retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterSend(LPI2C_Type *base, void *txBuff, size_t txSize) +{ + status_t result = kStatus_Success; + uint8_t *buf = (uint8_t *)txBuff; + + assert(NULL != txBuff); + + /* Send data buffer */ + while (0U != (txSize--)) + { + /* Wait until there is room in the fifo. This also checks for errors. */ + result = LPI2C_MasterWaitForTxReady(base); + if (kStatus_Success != result) + { + break; + } + + /* Write byte into LPI2C master data register. */ + base->MTDR = *buf++; + } + + return result; +} + +/*! + * brief Performs a master polling transfer on the I2C bus. + * + * note The API does not return until the transfer succeeds or fails due + * to error happens during transfer. + * + * param base The LPI2C peripheral base address. + * param transfer Pointer to the transfer structure. + * retval #kStatus_Success Data was received successfully. + * retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer) +{ + assert(NULL != transfer); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + + status_t result = kStatus_Success; + uint16_t commandBuffer[7]; + uint32_t cmdCount = 0U; + + /* Check transfer data size in read operation. */ + if ((transfer->direction == kLPI2C_Read) && + (transfer->dataSize > ((size_t)256 * (size_t)FSL_FEATURE_LPI2C_FIFO_SIZEn(base)))) + { + return kStatus_InvalidArgument; + } + + /* Enable the master function and disable the slave function. */ + LPI2C_MasterEnable(base, true); + LPI2C_SlaveEnable(base, false); + + /* Return an error if the bus is already in use not by us. */ + result = LPI2C_CheckForBusyBus(base); + /* + * $Branch Coverage Justification$ + * $ref fsl_lpi2c_c_ref_2$ + */ + if (kStatus_Success == result) + { + /* Clear all flags. */ + LPI2C_MasterClearStatusFlags(base, (uint32_t)kLPI2C_MasterClearFlags); + + /* Turn off auto-stop option. */ + base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; + + lpi2c_direction_t direction = (0U != transfer->subaddressSize) ? kLPI2C_Write : transfer->direction; + if (0U == (transfer->flags & (uint32_t)kLPI2C_TransferNoStartFlag)) + { + commandBuffer[cmdCount++] = + (uint16_t)kStartCmd | + (uint16_t)((uint16_t)((uint16_t)transfer->slaveAddress << 1U) | (uint16_t)direction); + } + + /* Subaddress, MSB first. */ + if (0U != transfer->subaddressSize) + { + uint32_t subaddressRemaining = transfer->subaddressSize; + while (0U != subaddressRemaining--) + { + uint8_t subaddressByte = (uint8_t)((transfer->subaddress >> (8U * subaddressRemaining)) & 0xffU); + commandBuffer[cmdCount++] = subaddressByte; + } + } + + /* Reads need special handling. */ + if ((0U != transfer->dataSize) && (transfer->direction == kLPI2C_Read)) + { + /* Need to send repeated start if switching directions to read. */ + if (direction == kLPI2C_Write) + { + commandBuffer[cmdCount++] = + (uint16_t)kStartCmd | + (uint16_t)((uint16_t)((uint16_t)transfer->slaveAddress << 1U) | (uint16_t)kLPI2C_Read); + } + } + + /* Send command buffer */ + uint32_t index = 0U; + while (0U != cmdCount--) + { + /* Wait until there is room in the fifo. This also checks for errors. */ + result = LPI2C_MasterWaitForTxReady(base); + if (kStatus_Success != result) + { + break; + } + + /* Write byte into LPI2C master data register. */ + base->MTDR = commandBuffer[index]; + index++; + } + + if (kStatus_Success == result) + { + /* Transmit data. */ + if ((transfer->direction == kLPI2C_Write) && (transfer->dataSize > 0U)) + { + /* Send Data. */ + result = LPI2C_MasterSend(base, transfer->data, transfer->dataSize); + } + + /* Receive Data. */ + if ((transfer->direction == kLPI2C_Read) && (transfer->dataSize > 0U)) + { + result = LPI2C_MasterReceive(base, transfer->data, transfer->dataSize); + } + /* + * $Branch Coverage Justification$ + * Errors cannot be simulated by software during transmission.(will improve) + */ + if (kStatus_Success == result) + { + if ((transfer->flags & (uint32_t)kLPI2C_TransferNoStopFlag) == 0U) + { + result = LPI2C_MasterStop(base); + } + } + } + + /* Transmit fail */ + if (kStatus_Success != result) + { + if ((transfer->flags & (uint32_t)kLPI2C_TransferNoStopFlag) == 0U) + { + (void)LPI2C_MasterStop(base); + } + } + } + + return result; +} + +/*! + * brief Creates a new handle for the LPI2C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called. + * + * + * note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + * + * param base The LPI2C peripheral base address. + * param[out] handle Pointer to the LPI2C master driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_callback_t callback, + void *userData) +{ + uint32_t instance; + + assert(NULL != handle); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = LPI2C_GetInstance(base); + + /* Save base and instance. */ + handle->completionCallback = callback; + handle->userData = userData; + + /* Save this handle for IRQ use. */ + s_lpi2cMasterHandle[instance] = handle; + + /* Set irq handler. */ + s_lpi2cMasterIsr = LPI2C_MasterTransferHandleIRQ; + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); + + /* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC. + In some cases the LPI2C IRQ is configured through INTMUX, user needs to enable + INTMUX IRQ in application code. */ + (void)EnableIRQ(kLpi2cIrqs[instance]); +} + +static void LPI2C_TransferStateMachineSendCommand(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_state_machine_param_t *stateParams) +{ + assert(stateParams != NULL); + uint16_t sendval; + + /* Make sure there is room in the tx fifo for the next command. */ + if (0U == (stateParams->txCount)--) + { + stateParams->state_complete = true; + return; + } + + /* Issue command. buf is a uint8_t* pointing at the uint16 command array. */ + sendval = ((uint16_t)handle->buf[0]) | (((uint16_t)handle->buf[1]) << 8U); + base->MTDR = sendval; + handle->buf++; + handle->buf++; + + /* Count down until all commands are sent. */ + if (--handle->remainingBytes == 0U) + { + /* Choose next state and set up buffer pointer and count. */ + if (0U != handle->transfer.dataSize) + { + /* Either a send or receive transfer is next. */ + handle->state = (uint8_t)kTransferDataState; + handle->buf = (uint8_t *)handle->transfer.data; + handle->remainingBytes = (uint16_t)handle->transfer.dataSize; + if (handle->transfer.direction == kLPI2C_Read) + { + /* Disable TX interrupt */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterTxReadyFlag); + /* Issue command to receive data. A single write to MTDR can issue read operation of + 0xFFU + 1 byte of data at most, so when the dataSize is larger than 0x100U, push + multiple read commands to MTDR until dataSize is reached. */ + size_t tmpRxSize = handle->transfer.dataSize; + while (tmpRxSize != 0U) + { + LPI2C_MasterGetFifoCounts(base, NULL, &stateParams->txCount); + /* + * $Branch Coverage Justification$ + * The transmission commands will not exceed FIFO SIZE.(will improve) + */ + while ((size_t)FSL_FEATURE_LPI2C_FIFO_SIZEn(base) == stateParams->txCount) + { + LPI2C_MasterGetFifoCounts(base, NULL, &stateParams->txCount); + } + + if (tmpRxSize > 256U) + { + base->MTDR = (uint32_t)(kRxDataCmd) | (uint32_t)LPI2C_MTDR_DATA(0xFFU); + tmpRxSize -= 256U; + } + else + { + base->MTDR = (uint32_t)(kRxDataCmd) | (uint32_t)LPI2C_MTDR_DATA(tmpRxSize - 1U); + tmpRxSize = 0U; + } + } + } + } + else + { + /* No transfer, so move to stop state. */ + handle->state = (uint8_t)kStopState; + } + } +} + +static void LPI2C_TransferStateMachineReadCommand(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_state_machine_param_t *stateParams) +{ + assert(stateParams != NULL); + + /* Make sure there is room in the tx fifo for the read command. */ + if (0U == (stateParams->txCount)--) + { + stateParams->state_complete = true; + return; + } + + base->MTDR = (uint32_t)kRxDataCmd | LPI2C_MTDR_DATA(handle->transfer.dataSize - 1U); + + /* Move to transfer state. */ + handle->state = (uint8_t)kTransferDataState; + if (handle->transfer.direction == kLPI2C_Read) + { + /* Disable TX interrupt */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterTxReadyFlag); + } +} + +static void LPI2C_TransferStateMachineTransferData(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_state_machine_param_t *stateParams) +{ + assert(stateParams != NULL); + + if (handle->transfer.direction == kLPI2C_Write) + { + /* Make sure there is room in the tx fifo. */ + if (0U == stateParams->txCount--) + { + stateParams->state_complete = true; + return; + } + + /* Put byte to send in fifo. */ + base->MTDR = *(handle->buf)++; + } + else + { + /* XXX handle receive sizes > 256, use kIssueReadCommandState */ + /* Make sure there is data in the rx fifo. */ + if (0U == stateParams->rxCount--) + { + stateParams->state_complete = true; + return; + } + + /* Read byte from fifo. */ + *(handle->buf)++ = (uint8_t)(base->MRDR & LPI2C_MRDR_DATA_MASK); + } + + /* Move to stop when the transfer is done. */ + if (--handle->remainingBytes == 0U) + { + if (handle->transfer.direction == kLPI2C_Write) + { + stateParams->state_complete = true; + } + handle->state = (uint8_t)kStopState; + } +} + +static void LPI2C_TransferStateMachineStopState(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_state_machine_param_t *stateParams, + bool *isDone) +{ + assert(stateParams != NULL); + + /* Only issue a stop transition if the caller requested it. */ + if ((handle->transfer.flags & (uint32_t)kLPI2C_TransferNoStopFlag) == 0U) + { + /* Make sure there is room in the tx fifo for the stop command. */ + if (0U == (stateParams->txCount)--) + { + stateParams->state_complete = true; + return; + } + + base->MTDR = (uint32_t)kStopCmd; + } + else + { + /* If all data is read and no stop flag is required to send, we are done. */ + if (handle->transfer.direction == kLPI2C_Read) + { + *isDone = true; + } + stateParams->state_complete = true; + } + handle->state = (uint8_t)kWaitForCompletionState; +} + +static void LPI2C_TransferStateMachineWaitState(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_state_machine_param_t *stateParams, + bool *isDone) +{ + assert(stateParams != NULL); + + if ((handle->transfer.flags & (uint32_t)kLPI2C_TransferNoStopFlag) == 0U) + { + /* We stay in this state until the stop state is detected. */ + if (0U != ((stateParams->status) & (uint32_t)kLPI2C_MasterStopDetectFlag)) + { + *isDone = true; + } + } + else + { + /* If all data is pushed to FIFO and no stop flag is required to send, we need to make sure they + are all send out to bus. */ + if ((handle->transfer.direction == kLPI2C_Write) && ((base->MFSR & LPI2C_MFSR_TXCOUNT_MASK) == 0U)) + { + /* We stay in this state until the data is sent out to bus. */ + *isDone = true; + } + } + stateParams->state_complete = true; +} + +/*! + * @brief Execute states until FIFOs are exhausted. + * @param handle Master nonblocking driver handle. + * @param[out] isDone Set to true if the transfer has completed. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_PinLowTimeout + * @retval #kStatus_LPI2C_ArbitrationLost + * @retval #kStatus_LPI2C_Nak + * @retval #kStatus_LPI2C_FifoError + */ +static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_handle_t *handle, bool *isDone) +{ + assert(NULL != base && NULL != handle && NULL != isDone); + + status_t result = kStatus_Success; + lpi2c_state_machine_param_t stateParams; + (void)memset(&stateParams, 0, sizeof(stateParams)); + + stateParams.state_complete = false; + + /* Set default isDone return value. */ + *isDone = false; + + /* Check for errors. */ + stateParams.status = LPI2C_MasterGetStatusFlags(base); + + /* Get fifo counts. */ + LPI2C_MasterGetFifoCounts(base, &stateParams.rxCount, &stateParams.txCount); + + /* For the last byte, nack flag is expected. + Do not check and clear kLPI2C_MasterNackDetectFlag for the last byte, + in case FIFO is emptied when stop command has not been sent. */ + if (handle->remainingBytes == 0U) + { + /* When data size is not zero which means it is not only one byte of address is sent, and */ + /* when the txfifo is empty, or have one byte which is the stop command, then the nack status can be ignored. */ + if (((handle->transfer).dataSize != 0U) && + ((stateParams.txCount == 0U) || + (((stateParams.txCount) == 1U) && (handle->state == (uint8_t)kWaitForCompletionState) && + (((handle->transfer).flags & (uint32_t)kLPI2C_TransferNoStopFlag) == 0U)))) + { + (stateParams.status) &= ~(uint32_t)kLPI2C_MasterNackDetectFlag; + } + } + + result = LPI2C_MasterCheckAndClearError(base, stateParams.status); + + if (kStatus_Success == result) + { + /* Compute room in tx fifo */ + stateParams.txCount = (size_t)FSL_FEATURE_LPI2C_FIFO_SIZEn(base) - stateParams.txCount; + + while (!stateParams.state_complete) + { + /* Execute the state. */ + /* + * $Branch Coverage Justification$ + * $ref fsl_lpi2c_c_ref_1$ + */ + switch (handle->state) + { + case (uint8_t)kSendCommandState: + LPI2C_TransferStateMachineSendCommand(base, handle, &stateParams); + break; + + case (uint8_t)kIssueReadCommandState: + LPI2C_TransferStateMachineReadCommand(base, handle, &stateParams); + break; + + case (uint8_t)kTransferDataState: + LPI2C_TransferStateMachineTransferData(base, handle, &stateParams); + break; + + case (uint8_t)kStopState: + LPI2C_TransferStateMachineStopState(base, handle, &stateParams, isDone); + break; + + case (uint8_t)kWaitForCompletionState: + LPI2C_TransferStateMachineWaitState(base, handle, &stateParams, isDone); + break; + default: + assert(false); + break; + } + } + } + return result; +} + +/*! + * @brief Prepares the transfer state machine and fills in the command buffer. + * @param handle Master nonblocking driver handle. + */ +static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle) +{ + lpi2c_master_transfer_t *xfer = &handle->transfer; + + /* Handle no start option. */ + if (0U != (xfer->flags & (uint32_t)kLPI2C_TransferNoStartFlag)) + { + if (xfer->direction == kLPI2C_Read) + { + /* Need to issue read command first. */ + handle->state = (uint8_t)kIssueReadCommandState; + } + else + { + /* Start immediately in the data transfer state. */ + handle->state = (uint8_t)kTransferDataState; + } + + handle->buf = (uint8_t *)xfer->data; + handle->remainingBytes = (uint16_t)xfer->dataSize; + } + else + { + uint16_t *cmd = (uint16_t *)&handle->commandBuffer; + uint32_t cmdCount = 0U; + + /* Initial direction depends on whether a subaddress was provided, and of course the actual */ + /* data transfer direction. */ + lpi2c_direction_t direction = (0U != xfer->subaddressSize) ? kLPI2C_Write : xfer->direction; + + /* Start command. */ + cmd[cmdCount++] = + (uint16_t)kStartCmd | (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)direction); + + /* Subaddress, MSB first. */ + if (0U != xfer->subaddressSize) + { + uint32_t subaddressRemaining = xfer->subaddressSize; + while (0U != (subaddressRemaining--)) + { + uint8_t subaddressByte = (uint8_t)((xfer->subaddress >> (8U * subaddressRemaining)) & 0xffU); + cmd[cmdCount++] = subaddressByte; + } + } + + /* Reads need special handling. */ + if ((0U != xfer->dataSize) && (xfer->direction == kLPI2C_Read)) + { + /* Need to send repeated start if switching directions to read. */ + if (direction == kLPI2C_Write) + { + cmd[cmdCount++] = (uint16_t)kStartCmd | + (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)kLPI2C_Read); + } + } + + /* Set up state machine for transferring the commands. */ + handle->state = (uint8_t)kSendCommandState; + handle->remainingBytes = (uint16_t)cmdCount; + handle->buf = (uint8_t *)&handle->commandBuffer; + } +} + +/*! + * brief Performs a non-blocking transaction on the I2C bus. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * param transfer The pointer to the transfer descriptor. + * retval #kStatus_Success The transaction was started successfully. + * retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_t *transfer) +{ + assert(NULL != handle); + assert(NULL != transfer); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + + status_t result; + + /* Check transfer data size in read operation. */ + if ((transfer->direction == kLPI2C_Read) && + (transfer->dataSize > (256U * (uint32_t)FSL_FEATURE_LPI2C_FIFO_SIZEn(base)))) + { + return kStatus_InvalidArgument; + } + + /* Return busy if another transaction is in progress. */ + if (handle->state != (uint8_t)kIdleState) + { + result = kStatus_LPI2C_Busy; + } + else + { + result = LPI2C_CheckForBusyBus(base); + } + + if ((status_t)kStatus_Success == result) + { + /* Enable the master function and disable the slave function. */ + LPI2C_MasterEnable(base, true); + LPI2C_SlaveEnable(base, false); + + /* Disable LPI2C IRQ sources while we configure stuff. */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); + + /* Reset FIFO in case there are data. */ + base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; + + /* Save transfer into handle. */ + handle->transfer = *transfer; + + /* Generate commands to send. */ + LPI2C_InitTransferStateMachine(handle); + + /* Clear all flags. */ + LPI2C_MasterClearStatusFlags(base, (uint32_t)kLPI2C_MasterClearFlags); + + /* Turn off auto-stop option. */ + base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; + + /* Enable LPI2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + LPI2C_MasterEnableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); + } + + return result; +} + +/*! + * brief Returns number of bytes transferred so far. + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * param[out] count Number of bytes transferred so far by the non-blocking transaction. + * retval #kStatus_Success + * retval #kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count) +{ + status_t result = kStatus_Success; + + assert(NULL != handle); + + if (NULL == count) + { + result = kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + else if (handle->state == (uint8_t)kIdleState) + { + *count = 0; + result = kStatus_NoTransferInProgress; + } + else + { + uint8_t state; + uint16_t remainingBytes; + uint32_t dataSize; + + /* Cache some fields with IRQs disabled. This ensures all field values */ + /* are synchronized with each other during an ongoing transfer. */ + uint32_t irqs = LPI2C_MasterGetEnabledInterrupts(base); + LPI2C_MasterDisableInterrupts(base, irqs); + state = handle->state; + remainingBytes = handle->remainingBytes; + dataSize = handle->transfer.dataSize; + LPI2C_MasterEnableInterrupts(base, irqs); + + /* Get transfer count based on current transfer state. */ + switch (state) + { + case (uint8_t)kIdleState: + case (uint8_t)kSendCommandState: + case (uint8_t) + kIssueReadCommandState: /* XXX return correct value for this state when >256 reads are supported */ + *count = 0; + break; + + case (uint8_t)kTransferDataState: + *count = dataSize - remainingBytes; + break; + + case (uint8_t)kStopState: + case (uint8_t)kWaitForCompletionState: + default: + *count = dataSize; + break; + } + } + + return result; +} + +/*! + * brief Terminates a non-blocking LPI2C master transmission early. + * + * note It is not safe to call this function from an IRQ handler that has a higher priority than the + * LPI2C peripheral's IRQ priority. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + */ +void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle) +{ + if (handle->state != (uint8_t)kIdleState) + { + /* Disable internal IRQ enables. */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); + + /* Reset fifos. */ + base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; + + /* If master is still busy and has not send out stop signal yet. */ + if ((LPI2C_MasterGetStatusFlags(base) & ((uint32_t)kLPI2C_MasterStopDetectFlag | + (uint32_t)kLPI2C_MasterBusyFlag)) == (uint32_t)kLPI2C_MasterBusyFlag) + { + /* Send a stop command to finalize the transfer. */ + base->MTDR = (uint32_t)kStopCmd; + } + + /* Reset handle. */ + handle->state = (uint8_t)kIdleState; + } +} + +/*! + * brief Reusable routine to handle master interrupts. + * note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * param base The LPI2C peripheral base address. + * param lpi2cMasterHandle Pointer to the LPI2C master driver handle. + */ +void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, void *lpi2cMasterHandle) +{ + assert(lpi2cMasterHandle != NULL); + + lpi2c_master_handle_t *handle = (lpi2c_master_handle_t *)lpi2cMasterHandle; + bool isDone = false; + status_t result; + + /* Don't do anything if we don't have a valid handle. */ + if (NULL != handle) + { + if (handle->state != (uint8_t)kIdleState) + { + result = LPI2C_RunTransferStateMachine(base, handle, &isDone); + + if ((result != kStatus_Success) || isDone) + { + /* Handle error, terminate xfer */ + if (result != kStatus_Success) + { + LPI2C_MasterTransferAbort(base, handle); + } + + /* Disable internal IRQ enables. */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); + + /* Set handle to idle state. */ + handle->state = (uint8_t)kIdleState; + + /* Invoke callback. */ + if (NULL != handle->completionCallback) + { + handle->completionCallback(base, handle, result, handle->userData); + } + } + } + } +} + +/*! + * brief Provides a default configuration for the LPI2C slave peripheral. + * + * This function provides the following default configuration for the LPI2C slave peripheral: + * code + * slaveConfig->enableSlave = true; + * slaveConfig->address0 = 0U; + * slaveConfig->address1 = 0U; + * slaveConfig->addressMatchMode = kLPI2C_MatchAddress0; + * slaveConfig->filterDozeEnable = true; + * slaveConfig->filterEnable = true; + * slaveConfig->enableGeneralCall = false; + * slaveConfig->sclStall.enableAck = false; + * slaveConfig->sclStall.enableTx = true; + * slaveConfig->sclStall.enableRx = true; + * slaveConfig->sclStall.enableAddress = true; + * slaveConfig->ignoreAck = false; + * slaveConfig->enableReceivedAddressRead = false; + * slaveConfig->sdaGlitchFilterWidth_ns = 0; + * slaveConfig->sclGlitchFilterWidth_ns = 0; + * slaveConfig->dataValidDelay_ns = 0; + * slaveConfig->clockHoldTime_ns = 0; + * endcode + * + * After calling this function, override any settings to customize the configuration, + * prior to initializing the master driver with LPI2C_SlaveInit(). Be sure to override at least the a + * address0 member of the configuration structure with the desired slave address. + * + * param[out] slaveConfig User provided configuration structure that is set to default values. Refer to + * #lpi2c_slave_config_t. + */ +void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig) +{ + /* Initializes the configure structure to zero. */ + (void)memset(slaveConfig, 0, sizeof(*slaveConfig)); + + slaveConfig->enableSlave = true; + slaveConfig->address0 = 0U; + slaveConfig->address1 = 0U; + slaveConfig->addressMatchMode = kLPI2C_MatchAddress0; + slaveConfig->filterDozeEnable = true; + slaveConfig->filterEnable = true; + slaveConfig->enableGeneralCall = false; + slaveConfig->sclStall.enableAck = false; + slaveConfig->sclStall.enableTx = true; + slaveConfig->sclStall.enableRx = true; + slaveConfig->sclStall.enableAddress = false; + slaveConfig->ignoreAck = false; + slaveConfig->enableReceivedAddressRead = false; + slaveConfig->sdaGlitchFilterWidth_ns = 0U; /* Set to 0 to disable the function */ + slaveConfig->sclGlitchFilterWidth_ns = 0U; /* Set to 0 to disable the function */ + slaveConfig->dataValidDelay_ns = 0U; + /* When enabling the slave tx SCL stall, set the default clock hold time to 250ns according + to I2C spec for standard mode baudrate(100k). User can manually change it to 100ns or 50ns + for fast-mode(400k) or fast-mode+(1m). */ + slaveConfig->clockHoldTime_ns = 250U; +} + +/*! + * brief Initializes the LPI2C slave peripheral. + * + * This function enables the peripheral clock and initializes the LPI2C slave peripheral as described by the user + * provided configuration. + * + * param base The LPI2C peripheral base address. + * param slaveConfig User provided peripheral configuration. Use LPI2C_SlaveGetDefaultConfig() to get a set of defaults + * that you can override. + * param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the filter widths, + * data valid delay, and clock hold time. + */ +void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz) +{ + uint32_t tmpReg; + uint32_t tmpCycle; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPI2C_GetInstance(base); + + /* Ungate the clock. */ + (void)CLOCK_EnableClock(kLpi2cClocks[instance]); +#if defined(LPI2C_PERIPH_CLOCKS) + /* Ungate the functional clock in initialize function. */ + CLOCK_EnableClock(kLpi2cPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(LPI2C_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_lpi2cResets[LPI2C_GetInstance(base)]); +#endif + + /* Restore to reset conditions. */ + LPI2C_SlaveReset(base); + + /* Configure peripheral. */ + base->SAMR = LPI2C_SAMR_ADDR0(slaveConfig->address0) | LPI2C_SAMR_ADDR1(slaveConfig->address1); + + base->SCFGR1 = + LPI2C_SCFGR1_ADDRCFG(slaveConfig->addressMatchMode) | LPI2C_SCFGR1_IGNACK(slaveConfig->ignoreAck) | + LPI2C_SCFGR1_RXCFG(slaveConfig->enableReceivedAddressRead) | LPI2C_SCFGR1_GCEN(slaveConfig->enableGeneralCall) | + LPI2C_SCFGR1_ACKSTALL(slaveConfig->sclStall.enableAck) | LPI2C_SCFGR1_TXDSTALL(slaveConfig->sclStall.enableTx) | + LPI2C_SCFGR1_RXSTALL(slaveConfig->sclStall.enableRx) | + LPI2C_SCFGR1_ADRSTALL(slaveConfig->sclStall.enableAddress); + + /* Calculate SDA filter width. The width is equal to FILTSDA+3 cycles of functional clock. + And set FILTSDA to 0 disables the fileter, so the min value is 4. */ + tmpReg = LPI2C_SCFGR2_FILTSDA( + LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->sdaGlitchFilterWidth_ns, 4U, + (LPI2C_SCFGR2_FILTSDA_MASK >> LPI2C_SCFGR2_FILTSDA_SHIFT) + 3U, 0U) - + 3U); + + /* Calculate SDL filter width. The width is equal to FILTSCL+3 cycles of functional clock. + And set FILTSCL to 0 disables the fileter, so the min value is 4. */ + tmpCycle = LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->sclGlitchFilterWidth_ns, 4U, + (LPI2C_SCFGR2_FILTSCL_MASK >> LPI2C_SCFGR2_FILTSCL_SHIFT) + 3U, 0U); + tmpReg |= LPI2C_SCFGR2_FILTSCL(tmpCycle - 3U); + + /* Calculate data valid time. The time is equal to FILTSCL+DATAVD+3 cycles of functional clock. + So the min value is FILTSCL+3. */ + tmpReg |= LPI2C_SCFGR2_DATAVD( + LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->dataValidDelay_ns, tmpCycle, + tmpCycle + (LPI2C_SCFGR2_DATAVD_MASK >> LPI2C_SCFGR2_DATAVD_SHIFT), 0U) - + tmpCycle); + + /* Calculate clock hold time. The time is equal to CLKHOLD+3 cycles of functional clock. + So the min value is 3. */ + base->SCFGR2 = + tmpReg | LPI2C_SCFGR2_CLKHOLD( + LPI2C_GetCyclesForWidth(sourceClock_Hz, slaveConfig->clockHoldTime_ns, 3U, + (LPI2C_SCFGR2_CLKHOLD_MASK >> LPI2C_SCFGR2_CLKHOLD_SHIFT) + 3U, 0U) - + 3U); + + /* Save SCR to last so we don't enable slave until it is configured */ + base->SCR = LPI2C_SCR_FILTDZ(!slaveConfig->filterDozeEnable) | LPI2C_SCR_FILTEN(slaveConfig->filterEnable) | + LPI2C_SCR_SEN(slaveConfig->enableSlave); +} + +/*! + * brief Deinitializes the LPI2C slave peripheral. + * + * This function disables the LPI2C slave peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * param base The LPI2C peripheral base address. + */ +void LPI2C_SlaveDeinit(LPI2C_Type *base) +{ + LPI2C_SlaveReset(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPI2C_GetInstance(base); + + /* Gate the clock. */ + (void)CLOCK_DisableClock(kLpi2cClocks[instance]); + +#if defined(LPI2C_PERIPH_CLOCKS) + /* Gate the functional clock. */ + CLOCK_DisableClock(kLpi2cPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief Convert provided flags to status code, and clear any errors if present. + * @param base The LPI2C peripheral base address. + * @param status Current status flags value that will be checked. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_BitError + * @retval #kStatus_LPI2C_FifoError + */ +static status_t LPI2C_SlaveCheckAndClearError(LPI2C_Type *base, uint32_t flags) +{ + status_t result = kStatus_Success; + + flags &= (uint32_t)kLPI2C_SlaveErrorFlags; + if (0U != flags) + { + /* + * $Branch Coverage Justification$ + * It is hard to simulate bitError in automation test environment, need interference on bus.(will improve) + */ + if (0U != (flags & (uint32_t)kLPI2C_SlaveBitErrFlag)) + { + result = kStatus_LPI2C_BitError; + } + else if (0U != (flags & (uint32_t)kLPI2C_SlaveFifoErrFlag)) + { + result = kStatus_LPI2C_FifoError; + } + else + { + ; /* Intentional empty */ + } + + /* Clear the errors. */ + LPI2C_SlaveClearStatusFlags(base, flags); + } + else + { + ; /* Intentional empty */ + } + + return result; +} + +/*! + * brief Performs a polling send transfer on the I2C bus. + * + * param base The LPI2C peripheral base address. + * param txBuff The pointer to the data to be transferred. + * param txSize The length in bytes of the data to be transferred. + * param[out] actualTxSize + * return Error or success status returned by API. + */ +status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *actualTxSize) +{ + status_t result = kStatus_Success; + uint8_t *buf = (uint8_t *)txBuff; + size_t remaining = txSize; + + assert(NULL != txBuff); + +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + + /* Clear stop flag. */ + LPI2C_SlaveClearStatusFlags(base, + (uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag); + + while (0U != remaining) + { + uint32_t flags; + + /* Wait until we can transmit. */ + do + { + /* Check for errors */ + flags = LPI2C_SlaveGetStatusFlags(base); + result = LPI2C_SlaveCheckAndClearError(base, flags); + if (kStatus_Success != result) + { + if (NULL != actualTxSize) + { + *actualTxSize = txSize - remaining; + } + break; + } +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while ((0U == (flags & ((uint32_t)kLPI2C_SlaveTxReadyFlag | (uint32_t)kLPI2C_SlaveStopDetectFlag | + (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))) && + (0U != waitTimes)); + if (0U == waitTimes) + { + result = kStatus_LPI2C_Timeout; + } +#else + } while (0U == (flags & ((uint32_t)kLPI2C_SlaveTxReadyFlag | (uint32_t)kLPI2C_SlaveStopDetectFlag | + (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))); +#endif + + if (kStatus_Success != result) + { + break; + } + + /* Send a byte. */ + if (0U != (flags & (uint32_t)kLPI2C_SlaveTxReadyFlag)) + { + base->STDR = *buf++; + --remaining; + } + + /* Exit loop if we see a stop or restart in transfer*/ + /* + * $Branch Coverage Justification$ + * $ref fsl_lpi2c_c_ref_3$ + */ + if ((0U != (flags & ((uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))) && + (remaining != 0U)) + { + LPI2C_SlaveClearStatusFlags( + base, (uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag); + break; + } + } + + if (NULL != actualTxSize) + { + *actualTxSize = txSize - remaining; + } + + return result; +} + +/*! + * brief Performs a polling receive transfer on the I2C bus. + * + * param base The LPI2C peripheral base address. + * param rxBuff The pointer to the data to be transferred. + * param rxSize The length in bytes of the data to be transferred. + * param[out] actualRxSize + * return Error or success status returned by API. + */ +status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize) +{ + status_t result = kStatus_Success; + uint8_t *buf = (uint8_t *)rxBuff; + size_t remaining = rxSize; + + assert(NULL != rxBuff); + +#if I2C_RETRY_TIMES != 0U + uint32_t waitTimes = I2C_RETRY_TIMES; +#endif + + /* Clear stop flag. */ + LPI2C_SlaveClearStatusFlags(base, + (uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag); + + while (0U != remaining) + { + uint32_t flags; + + /* Wait until we can receive. */ + do + { + /* Check for errors */ + flags = LPI2C_SlaveGetStatusFlags(base); + result = LPI2C_SlaveCheckAndClearError(base, flags); + if (kStatus_Success != result) + { + if (NULL != actualRxSize) + { + *actualRxSize = rxSize - remaining; + } + break; + } +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while ((0U == (flags & ((uint32_t)kLPI2C_SlaveRxReadyFlag | (uint32_t)kLPI2C_SlaveStopDetectFlag | + (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))) && + (0U != waitTimes)); + if (0U == waitTimes) + { + result = kStatus_LPI2C_Timeout; + } +#else + } while (0U == (flags & ((uint32_t)kLPI2C_SlaveRxReadyFlag | (uint32_t)kLPI2C_SlaveStopDetectFlag | + (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))); +#endif + + if ((status_t)kStatus_Success != result) + { + break; + } + + /* Receive a byte. */ + if (0U != (flags & (uint32_t)kLPI2C_SlaveRxReadyFlag)) + { + *buf++ = (uint8_t)(base->SRDR & LPI2C_SRDR_DATA_MASK); + --remaining; + } + + /* Exit loop if we see a stop or restart */ + /* + * $Branch Coverage Justification$ + * $ref fsl_lpi2c_c_ref_3$ + */ + if ((0U != (flags & ((uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))) && + (remaining != 0U)) + { + LPI2C_SlaveClearStatusFlags( + base, (uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag); + break; + } + } + + if (NULL != actualRxSize) + { + *actualRxSize = rxSize - remaining; + } + + return result; +} + +/*! + * brief Creates a new handle for the LPI2C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_SlaveTransferAbort() API shall be called. + * + * note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + + * param base The LPI2C peripheral base address. + * param[out] handle Pointer to the LPI2C slave driver handle. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, + lpi2c_slave_handle_t *handle, + lpi2c_slave_transfer_callback_t callback, + void *userData) +{ + uint32_t instance; + + assert(NULL != handle); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Look up instance number */ + instance = LPI2C_GetInstance(base); + + /* Save base and instance. */ + handle->callback = callback; + handle->userData = userData; + + /* Save this handle for IRQ use. */ + s_lpi2cSlaveHandle[instance] = handle; + + /* Set irq handler. */ + s_lpi2cSlaveIsr = LPI2C_SlaveTransferHandleIRQ; + + /* Clear internal IRQ enables and enable NVIC IRQ. */ + LPI2C_SlaveDisableInterrupts(base, (uint32_t)kLPI2C_SlaveIrqFlags); + (void)EnableIRQ(kLpi2cIrqs[instance]); + + /* Nack by default. */ + base->STAR = LPI2C_STAR_TXNACK_MASK; +} + +/*! + * brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and LPI2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to LPI2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the a eventMask parameter to + * the OR'd combination of #lpi2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kLPI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kLPI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + * param eventMask Bit mask formed by OR'ing together #lpi2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kLPI2C_SlaveAllEvents to enable all events. + * + * retval #kStatus_Success Slave transfers were successfully started. + * retval #kStatus_LPI2C_Busy Slave transfers have already been started on this handle. + */ +status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask) +{ + status_t result = kStatus_Success; + + assert(NULL != handle); + + /* Return busy if another transaction is in progress. */ + if (handle->isBusy) + { + result = kStatus_LPI2C_Busy; + } + else + { + /* Enable the slave function and disable the master function. */ + LPI2C_MasterEnable(base, false); + LPI2C_SlaveEnable(base, true); + /* Return an error if the bus is already in use not by us. */ + uint32_t status = LPI2C_SlaveGetStatusFlags(base); + /* + * $Branch Coverage Justification$ + * $ref fsl_lpi2c_c_ref_2$ + */ + if ((0U != (status & (uint32_t)kLPI2C_SlaveBusBusyFlag)) && (0U == (status & (uint32_t)kLPI2C_SlaveBusyFlag))) + { + result = kStatus_LPI2C_Busy; + } + } + + if ((status_t)kStatus_Success == result) + { + /* Disable LPI2C IRQ sources while we configure stuff. */ + LPI2C_SlaveDisableInterrupts(base, (uint32_t)kLPI2C_SlaveIrqFlags); + + /* Clear transfer in handle. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* Record that we're busy. */ + handle->isBusy = true; + + /* Set up event mask. tx and rx are always enabled. */ + handle->eventMask = eventMask | (uint32_t)kLPI2C_SlaveTransmitEvent | (uint32_t)kLPI2C_SlaveReceiveEvent; + + /* Ack by default. */ + base->STAR = 0U; + + /* Clear all flags. */ + LPI2C_SlaveClearStatusFlags(base, (uint32_t)kLPI2C_SlaveClearFlags); + + /* Enable LPI2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ + LPI2C_SlaveEnableInterrupts(base, (uint32_t)kLPI2C_SlaveIrqFlags); + } + + return result; +} + +/*! + * brief Gets the slave transfer status during a non-blocking transfer. + * param base The LPI2C peripheral base address. + * param handle Pointer to i2c_slave_handle_t structure. + * param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not + * required. + * retval #kStatus_Success + * retval #kStatus_NoTransferInProgress + */ +status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count) +{ + status_t status = kStatus_Success; + + assert(NULL != handle); + + if (count == NULL) + { + status = kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + else if (!handle->isBusy) + { + *count = 0; + status = kStatus_NoTransferInProgress; + } + + /* For an active transfer, just return the count from the handle. */ + else + { + *count = handle->transferredCount; + } + + return status; +} + +/*! + * brief Aborts the slave non-blocking transfers. + * note This API could be called at any time to stop slave for handling the bus events. + * param base The LPI2C peripheral base address. + * param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + */ +void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle) +{ + assert(NULL != handle); + + /* Return idle if no transaction is in progress. */ + if (handle->isBusy) + { + /* Disable LPI2C IRQ sources. */ + LPI2C_SlaveDisableInterrupts(base, (uint32_t)kLPI2C_SlaveIrqFlags); + + /* Nack by default. */ + base->STAR = LPI2C_STAR_TXNACK_MASK; + + /* Reset transfer info. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + + /* We're no longer busy. */ + handle->isBusy = false; + } +} + +/*! + * brief Reusable routine to handle slave interrupts. + * note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * param base The LPI2C peripheral base address. + * param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state. + */ +void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle) +{ + uint32_t flags; + lpi2c_slave_transfer_t *xfer; + + /* Check for a valid handle in case of a spurious interrupt. */ + if (NULL != handle) + { + xfer = &handle->transfer; + + /* Get status flags. */ + flags = LPI2C_SlaveGetStatusFlags(base); + + if (0U != (flags & ((uint32_t)kLPI2C_SlaveBitErrFlag | (uint32_t)kLPI2C_SlaveFifoErrFlag))) + { + xfer->event = kLPI2C_SlaveCompletionEvent; + xfer->completionStatus = LPI2C_SlaveCheckAndClearError(base, flags); + + if ((0U != (handle->eventMask & (uint32_t)kLPI2C_SlaveCompletionEvent)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + else + { + if (0U != + (flags & (((uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag) | ((uint32_t)kLPI2C_SlaveStopDetectFlag)))) + { + xfer->event = (0U != (flags & (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag)) ? + kLPI2C_SlaveRepeatedStartEvent : + kLPI2C_SlaveCompletionEvent; + xfer->receivedAddress = 0U; + xfer->completionStatus = kStatus_Success; + xfer->transferredCount = handle->transferredCount; + + if (xfer->event == kLPI2C_SlaveCompletionEvent) + { + handle->isBusy = false; + } + + if (handle->wasTransmit) + { + /* Subtract one from the transmit count to offset the fact that LPI2C asserts the */ + /* tx flag before it sees the nack from the master-receiver, thus causing one more */ + /* count that the master actually receives. */ + --xfer->transferredCount; + handle->wasTransmit = false; + } + + /* Clear the flag. */ + LPI2C_SlaveClearStatusFlags(base, flags & ((uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag | + (uint32_t)kLPI2C_SlaveStopDetectFlag)); + + /* Revert to sending an Ack by default, in case we sent a Nack for receive. */ + base->STAR = 0U; + + if ((0U != (handle->eventMask & (uint32_t)xfer->event)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + + if (0U != (flags & (uint32_t)kLPI2C_SlaveStopDetectFlag)) + { + /* Clean up transfer info on completion, after the callback has been invoked. */ + (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); + } + } + if (0U != (flags & (uint32_t)kLPI2C_SlaveAddressValidFlag)) + { + xfer->event = kLPI2C_SlaveAddressMatchEvent; + xfer->receivedAddress = (uint8_t)(base->SASR & LPI2C_SASR_RADDR_MASK); + + /* Update handle status to busy because slave is addressed. */ + handle->isBusy = true; + if ((0U != (handle->eventMask & (uint32_t)kLPI2C_SlaveAddressMatchEvent)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + if (0U != (flags & (uint32_t)kLPI2C_SlaveTransmitAckFlag)) + { + xfer->event = kLPI2C_SlaveTransmitAckEvent; + + if ((0U != (handle->eventMask & (uint32_t)kLPI2C_SlaveTransmitAckEvent)) && (NULL != handle->callback)) + { + handle->callback(base, xfer, handle->userData); + } + } + + /* Handle transmit and receive. */ + if (0U != (flags & (uint32_t)kLPI2C_SlaveTxReadyFlag)) + { + handle->wasTransmit = true; + + /* If we're out of data, invoke callback to get more. */ + if ((NULL == xfer->data) || (0U == xfer->dataSize)) + { + xfer->event = kLPI2C_SlaveTransmitEvent; + if (NULL != handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + handle->transferredCount = 0U; + } + + /* Transmit a byte. */ + if ((NULL != xfer->data) && (0U != xfer->dataSize)) + { + base->STDR = *xfer->data++; + --xfer->dataSize; + ++handle->transferredCount; + } + } + if (0U != (flags & (uint32_t)kLPI2C_SlaveRxReadyFlag)) + { + /* If we're out of room in the buffer, invoke callback to get another. */ + if ((NULL == xfer->data) || (0U == xfer->dataSize)) + { + xfer->event = kLPI2C_SlaveReceiveEvent; + if (NULL != handle->callback) + { + handle->callback(base, xfer, handle->userData); + } + + /* Clear the transferred count now that we have a new buffer. */ + handle->transferredCount = 0U; + } + + /* Receive a byte. */ + if ((NULL != xfer->data) && (0U != xfer->dataSize)) + { + *xfer->data++ = (uint8_t)base->SRDR; + --xfer->dataSize; + ++handle->transferredCount; + } + else + { + /* We don't have any room to receive more data, so send a nack. */ + base->STAR = LPI2C_STAR_TXNACK_MASK; + } + } + } + } +} + +#if !(defined(FSL_FEATURE_I2C_HAS_NO_IRQ) && FSL_FEATURE_I2C_HAS_NO_IRQ) +/*! + * @brief Shared IRQ handler that can call both master and slave ISRs. + * + * The master and slave ISRs are called through function pointers in order to decouple + * this code from the ISR functions. Without this, the linker would always pull in both + * ISRs and every function they call, even if only the functional API was used. + * + * @param base The LPI2C peripheral base address. + * @param instance The LPI2C peripheral instance number. + */ +static void LPI2C_CommonIRQHandler(LPI2C_Type *base, uint32_t instance) +{ + /* Check for master IRQ. */ + if ((0U != (base->MCR & LPI2C_MCR_MEN_MASK)) && (NULL != s_lpi2cMasterIsr)) + { + /* Master mode. */ + s_lpi2cMasterIsr(base, s_lpi2cMasterHandle[instance]); + } + + /* Check for slave IRQ. */ + if ((0U != (base->SCR & LPI2C_SCR_SEN_MASK)) && (NULL != s_lpi2cSlaveIsr)) + { + /* Slave mode. */ + s_lpi2cSlaveIsr(base, s_lpi2cSlaveHandle[instance]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(LPI2C0) +/* Implementation of LPI2C0 handler named in startup code. */ +void LPI2C0_DriverIRQHandler(void); +void LPI2C0_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(LPI2C0, 0U); +} +#endif + +#if defined(LPI2C1) +/* Implementation of LPI2C1 handler named in startup code. */ +void LPI2C1_DriverIRQHandler(void); +void LPI2C1_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(LPI2C1, 1U); +} +#endif + +#if defined(LPI2C2) +/* Implementation of LPI2C2 handler named in startup code. */ +void LPI2C2_DriverIRQHandler(void); +void LPI2C2_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(LPI2C2, 2U); +} +#endif + +#if defined(LPI2C3) +/* Implementation of LPI2C3 handler named in startup code. */ +void LPI2C3_DriverIRQHandler(void); +void LPI2C3_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(LPI2C3, 3U); +} +#endif + +#if defined(LPI2C4) +/* Implementation of LPI2C4 handler named in startup code. */ +void LPI2C4_DriverIRQHandler(void); +void LPI2C4_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(LPI2C4, 4U); +} +#endif + +#if defined(LPI2C5) +/* Implementation of LPI2C5 handler named in startup code. */ +void LPI2C5_DriverIRQHandler(void); +void LPI2C5_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(LPI2C5, 5U); +} +#endif + +#if defined(LPI2C6) +/* Implementation of LPI2C6 handler named in startup code. */ +void LPI2C6_DriverIRQHandler(void); +void LPI2C6_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(LPI2C6, 6U); +} +#endif + +#if defined(LPI2C7) +/* Implementation of LPI2C7 handler named in startup code. */ +void LPI2C7_DriverIRQHandler(void); +void LPI2C7_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(LPI2C7, 7U); +} +#endif + +#if defined(LPI2C8) +/* Implementation of LPI2C8 handler named in startup code. */ +void LPI2C8_DriverIRQHandler(void); +void LPI2C8_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(LPI2C8, 8U); +} +#endif + +#if defined(CM4_0__LPI2C) +/* Implementation of CM4_0__LPI2C handler named in startup code. */ +void M4_0_LPI2C_DriverIRQHandler(void); +void M4_0_LPI2C_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(CM4_0__LPI2C, LPI2C_GetInstance(CM4_0__LPI2C)); +} +#endif + +#if defined(CM4__LPI2C) +/* Implementation of CM4__LPI2C handler named in startup code. */ +void M4_LPI2C_DriverIRQHandler(void); +void M4_LPI2C_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(CM4__LPI2C, LPI2C_GetInstance(CM4__LPI2C)); +} +#endif + +#if defined(CM4_1__LPI2C) +/* Implementation of CM4_1__LPI2C handler named in startup code. */ +void M4_1_LPI2C_DriverIRQHandler(void); +void M4_1_LPI2C_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(CM4_1__LPI2C, LPI2C_GetInstance(CM4_1__LPI2C)); +} +#endif + +#if defined(DMA__LPI2C0) +/* Implementation of DMA__LPI2C0 handler named in startup code. */ +void DMA_I2C0_INT_DriverIRQHandler(void); +void DMA_I2C0_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(DMA__LPI2C0, LPI2C_GetInstance(DMA__LPI2C0)); +} +#endif + +#if defined(DMA__LPI2C1) +/* Implementation of DMA__LPI2C1 handler named in startup code. */ +void DMA_I2C1_INT_DriverIRQHandler(void); +void DMA_I2C1_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(DMA__LPI2C1, LPI2C_GetInstance(DMA__LPI2C1)); +} +#endif + +#if defined(DMA__LPI2C2) +/* Implementation of DMA__LPI2C2 handler named in startup code. */ +void DMA_I2C2_INT_DriverIRQHandler(void); +void DMA_I2C2_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(DMA__LPI2C2, LPI2C_GetInstance(DMA__LPI2C2)); +} +#endif + +#if defined(DMA__LPI2C3) +/* Implementation of DMA__LPI2C3 handler named in startup code. */ +void DMA_I2C3_INT_DriverIRQHandler(void); +void DMA_I2C3_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(DMA__LPI2C3, LPI2C_GetInstance(DMA__LPI2C3)); +} +#endif + +#if defined(DMA__LPI2C4) +/* Implementation of DMA__LPI2C3 handler named in startup code. */ +void DMA_I2C4_INT_DriverIRQHandler(void); +void DMA_I2C4_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(DMA__LPI2C4, LPI2C_GetInstance(DMA__LPI2C4)); +} +#endif + +#if defined(ADMA__LPI2C0) +/* Implementation of DMA__LPI2C0 handler named in startup code. */ +void ADMA_I2C0_INT_DriverIRQHandler(void); +void ADMA_I2C0_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(ADMA__LPI2C0, LPI2C_GetInstance(ADMA__LPI2C0)); +} +#endif + +#if defined(ADMA__LPI2C1) +/* Implementation of DMA__LPI2C1 handler named in startup code. */ +void ADMA_I2C1_INT_DriverIRQHandler(void); +void ADMA_I2C1_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(ADMA__LPI2C1, LPI2C_GetInstance(ADMA__LPI2C1)); +} +#endif + +#if defined(ADMA__LPI2C2) +/* Implementation of DMA__LPI2C2 handler named in startup code. */ +void ADMA_I2C2_INT_DriverIRQHandler(void); +void ADMA_I2C2_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(ADMA__LPI2C2, LPI2C_GetInstance(ADMA__LPI2C2)); +} +#endif + +#if defined(ADMA__LPI2C3) +/* Implementation of DMA__LPI2C3 handler named in startup code. */ +void ADMA_I2C3_INT_DriverIRQHandler(void); +void ADMA_I2C3_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(ADMA__LPI2C3, LPI2C_GetInstance(ADMA__LPI2C3)); +} +#endif + +#if defined(ADMA__LPI2C4) +/* Implementation of DMA__LPI2C3 handler named in startup code. */ +void ADMA_I2C4_INT_DriverIRQHandler(void); +void ADMA_I2C4_INT_DriverIRQHandler(void) +{ + LPI2C_CommonIRQHandler(ADMA__LPI2C4, LPI2C_GetInstance(ADMA__LPI2C4)); +} +#endif diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpi2c.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpi2c.h new file mode 100644 index 00000000000..390bcc5a743 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpi2c.h @@ -0,0 +1,1389 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LPI2C_H_ +#define FSL_LPI2C_H_ + +#include +#include "fsl_device_registers.h" +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @addtogroup lpi2c + * @{ + */ + +/*! + * @name Driver version + * @{ + */ +/*! @brief LPI2C driver version. */ +#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 5, 4)) +/*! @} */ + +/*! @brief Retry times for waiting flag. */ +#ifndef I2C_RETRY_TIMES +#define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +/*! @brief LPI2C status return codes. */ +enum +{ + kStatus_LPI2C_Busy = MAKE_STATUS(kStatusGroup_LPI2C, 0), /*!< The master is already performing a transfer. */ + kStatus_LPI2C_Idle = MAKE_STATUS(kStatusGroup_LPI2C, 1), /*!< The slave driver is idle. */ + kStatus_LPI2C_Nak = MAKE_STATUS(kStatusGroup_LPI2C, 2), /*!< The slave device sent a NAK in response to a byte. */ + kStatus_LPI2C_FifoError = MAKE_STATUS(kStatusGroup_LPI2C, 3), /*!< FIFO under run or overrun. */ + kStatus_LPI2C_BitError = MAKE_STATUS(kStatusGroup_LPI2C, 4), /*!< Transferred bit was not seen on the bus. */ + kStatus_LPI2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_LPI2C, 5), /*!< Arbitration lost error. */ + kStatus_LPI2C_PinLowTimeout = + MAKE_STATUS(kStatusGroup_LPI2C, 6), /*!< SCL or SDA were held low longer than the timeout. */ + kStatus_LPI2C_NoTransferInProgress = + MAKE_STATUS(kStatusGroup_LPI2C, 7), /*!< Attempt to abort a transfer when one is not in progress. */ + kStatus_LPI2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_LPI2C, 8), /*!< DMA request failed. */ + kStatus_LPI2C_Timeout = MAKE_STATUS(kStatusGroup_LPI2C, 9), /*!< Timeout polling status flags. */ +}; + +/*! + * @addtogroup lpi2c_master_driver + * @{ + */ + +/*! + * @brief LPI2C master peripheral flags. + * + * The following status register flags can be cleared: + * - #kLPI2C_MasterEndOfPacketFlag + * - #kLPI2C_MasterStopDetectFlag + * - #kLPI2C_MasterNackDetectFlag + * - #kLPI2C_MasterArbitrationLostFlag + * - #kLPI2C_MasterFifoErrFlag + * - #kLPI2C_MasterPinLowTimeoutFlag + * - #kLPI2C_MasterDataMatchFlag + * + * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as + * interrupts. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _lpi2c_master_flags +{ + kLPI2C_MasterTxReadyFlag = LPI2C_MSR_TDF_MASK, /*!< Transmit data flag */ + kLPI2C_MasterRxReadyFlag = LPI2C_MSR_RDF_MASK, /*!< Receive data flag */ + kLPI2C_MasterEndOfPacketFlag = LPI2C_MSR_EPF_MASK, /*!< End Packet flag */ + kLPI2C_MasterStopDetectFlag = LPI2C_MSR_SDF_MASK, /*!< Stop detect flag */ + kLPI2C_MasterNackDetectFlag = LPI2C_MSR_NDF_MASK, /*!< NACK detect flag */ + kLPI2C_MasterArbitrationLostFlag = LPI2C_MSR_ALF_MASK, /*!< Arbitration lost flag */ + kLPI2C_MasterFifoErrFlag = LPI2C_MSR_FEF_MASK, /*!< FIFO error flag */ + kLPI2C_MasterPinLowTimeoutFlag = LPI2C_MSR_PLTF_MASK, /*!< Pin low timeout flag */ + kLPI2C_MasterDataMatchFlag = LPI2C_MSR_DMF_MASK, /*!< Data match flag */ + kLPI2C_MasterBusyFlag = LPI2C_MSR_MBF_MASK, /*!< Master busy flag */ + kLPI2C_MasterBusBusyFlag = LPI2C_MSR_BBF_MASK, /*!< Bus busy flag */ + + /*! All flags which are cleared by the driver upon starting a transfer. */ + kLPI2C_MasterClearFlags = kLPI2C_MasterEndOfPacketFlag | kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | + kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag | + kLPI2C_MasterPinLowTimeoutFlag | kLPI2C_MasterDataMatchFlag, + /*! IRQ sources enabled by the non-blocking transactional API. */ + kLPI2C_MasterIrqFlags = kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterTxReadyFlag | kLPI2C_MasterRxReadyFlag | + kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | kLPI2C_MasterPinLowTimeoutFlag | + kLPI2C_MasterFifoErrFlag, + /*! Errors to check for. */ + kLPI2C_MasterErrorFlags = kLPI2C_MasterNackDetectFlag | kLPI2C_MasterArbitrationLostFlag | + kLPI2C_MasterFifoErrFlag | kLPI2C_MasterPinLowTimeoutFlag +}; + +/*! @brief Direction of master and slave transfers. */ +typedef enum _lpi2c_direction +{ + kLPI2C_Write = 0U, /*!< Master transmit. */ + kLPI2C_Read = 1U /*!< Master receive. */ +} lpi2c_direction_t; + +/*! @brief LPI2C pin configuration. */ +typedef enum _lpi2c_master_pin_config +{ + kLPI2C_2PinOpenDrain = 0x0U, /*!< LPI2C Configured for 2-pin open drain mode */ + kLPI2C_2PinOutputOnly = 0x1U, /*!< LPI2C Configured for 2-pin output only mode (ultra-fast mode) */ + kLPI2C_2PinPushPull = 0x2U, /*!< LPI2C Configured for 2-pin push-pull mode */ + kLPI2C_4PinPushPull = 0x3U, /*!< LPI2C Configured for 4-pin push-pull mode */ + kLPI2C_2PinOpenDrainWithSeparateSlave = + 0x4U, /*!< LPI2C Configured for 2-pin open drain mode with separate LPI2C slave */ + kLPI2C_2PinOutputOnlyWithSeparateSlave = + 0x5U, /*!< LPI2C Configured for 2-pin output only mode(ultra-fast mode) with separate LPI2C slave */ + kLPI2C_2PinPushPullWithSeparateSlave = + 0x6U, /*!< LPI2C Configured for 2-pin push-pull mode with separate LPI2C slave */ + kLPI2C_4PinPushPullWithInvertedOutput = 0x7U /*!< LPI2C Configured for 4-pin push-pull mode(inverted outputs) */ +} lpi2c_master_pin_config_t; + +/*! @brief LPI2C master host request selection. */ +typedef enum _lpi2c_host_request_source +{ + kLPI2C_HostRequestExternalPin = 0x0U, /*!< Select the LPI2C_HREQ pin as the host request input */ + kLPI2C_HostRequestInputTrigger = 0x1U, /*!< Select the input trigger as the host request input */ +} lpi2c_host_request_source_t; + +/*! @brief LPI2C master host request pin polarity configuration. */ +typedef enum _lpi2c_host_request_polarity +{ + kLPI2C_HostRequestPinActiveLow = 0x0U, /*!< Configure the LPI2C_HREQ pin active low */ + kLPI2C_HostRequestPinActiveHigh = 0x1U /*!< Configure the LPI2C_HREQ pin active high */ +} lpi2c_host_request_polarity_t; + +/*! + * @brief Structure with settings to initialize the LPI2C master module. + * + * This structure holds configuration settings for the LPI2C peripheral. To initialize this + * structure to reasonable defaults, call the LPI2C_MasterGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _lpi2c_master_config +{ + bool enableMaster; /*!< Whether to enable master mode. */ + bool enableDoze; /*!< Whether master is enabled in doze mode. */ + bool debugEnable; /*!< Enable transfers to continue when halted in debug mode. */ + bool ignoreAck; /*!< Whether to ignore ACK/NACK. */ + lpi2c_master_pin_config_t pinConfig; /*!< The pin configuration option. */ + uint32_t baudRate_Hz; /*!< Desired baud rate in Hertz. */ + uint32_t busIdleTimeout_ns; /*!< Bus idle timeout in nanoseconds. Set to 0 to disable. */ + uint32_t pinLowTimeout_ns; /*!< Pin low timeout in nanoseconds. Set to 0 to disable. */ + uint8_t sdaGlitchFilterWidth_ns; /*!< Width in nanoseconds of glitch filter on SDA pin. Set to 0 to disable. */ + uint8_t sclGlitchFilterWidth_ns; /*!< Width in nanoseconds of glitch filter on SCL pin. Set to 0 to disable. */ + struct + { + bool enable; /*!< Enable host request. */ + lpi2c_host_request_source_t source; /*!< Host request source. */ + lpi2c_host_request_polarity_t polarity; /*!< Host request pin polarity. */ + } hostRequest; /*!< Host request options. */ +} lpi2c_master_config_t; + +/*! @brief LPI2C master data match configuration modes. */ +typedef enum _lpi2c_data_match_config_mode +{ + kLPI2C_MatchDisabled = 0x0U, /*!< LPI2C Match Disabled */ + kLPI2C_1stWordEqualsM0OrM1 = 0x2U, /*!< LPI2C Match Enabled and 1st data word equals MATCH0 OR MATCH1 */ + kLPI2C_AnyWordEqualsM0OrM1 = 0x3U, /*!< LPI2C Match Enabled and any data word equals MATCH0 OR MATCH1 */ + kLPI2C_1stWordEqualsM0And2ndWordEqualsM1 = + 0x4U, /*!< LPI2C Match Enabled and 1st data word equals MATCH0, 2nd data equals MATCH1 */ + kLPI2C_AnyWordEqualsM0AndNextWordEqualsM1 = + 0x5U, /*!< LPI2C Match Enabled and any data word equals MATCH0, next data equals MATCH1 */ + kLPI2C_1stWordAndM1EqualsM0AndM1 = + 0x6U, /*!< LPI2C Match Enabled and 1st data word and MATCH0 equals MATCH0 and MATCH1 */ + kLPI2C_AnyWordAndM1EqualsM0AndM1 = + 0x7U /*!< LPI2C Match Enabled and any data word and MATCH0 equals MATCH0 and MATCH1 */ +} lpi2c_data_match_config_mode_t; + +/*! @brief LPI2C master data match configuration structure. */ +typedef struct _lpi2c_match_config +{ + lpi2c_data_match_config_mode_t matchMode; /*!< Data match configuration setting. */ + bool rxDataMatchOnly; /*!< When set to true, received data is ignored until a successful match. */ + uint32_t match0; /*!< Match value 0. */ + uint32_t match1; /*!< Match value 1. */ +} lpi2c_data_match_config_t; + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +/*! @brief LPI2C master descriptor of the transfer. */ +typedef struct _lpi2c_master_transfer lpi2c_master_transfer_t; +/*! @brief LPI2C master handle of the transfer. */ +typedef struct _lpi2c_master_handle lpi2c_master_handle_t; + +/*! + * @brief Master completion callback function pointer type. + * + * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use + * in the call to LPI2C_MasterTransferCreateHandle(). + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*lpi2c_master_transfer_callback_t)(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + status_t completionStatus, + void *userData); + +/*! + * @brief Transfer option flags. + * + * @note These enumerations are intended to be OR'd together to form a bit mask of options for + * the #_lpi2c_master_transfer::flags field. + */ +enum _lpi2c_master_transfer_flags +{ + kLPI2C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */ + kLPI2C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */ + kLPI2C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */ + kLPI2C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */ +}; + +/*! + * @brief Non-blocking transfer descriptor structure. + * + * This structure is used to pass transaction parameters to the LPI2C_MasterTransferNonBlocking() API. + */ +struct _lpi2c_master_transfer +{ + uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_lpi2c_master_transfer_flags for + available options. Set to 0 or #kLPI2C_TransferDefaultFlag for normal transfers. */ + uint16_t slaveAddress; /*!< The 7-bit slave address. */ + lpi2c_direction_t direction; /*!< Either #kLPI2C_Read or #kLPI2C_Write. */ + uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ + size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ + void *data; /*!< Pointer to data to transfer. */ + size_t dataSize; /*!< Number of bytes to transfer. */ +}; + +/*! + * @brief Driver handle for master non-blocking APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _lpi2c_master_handle +{ + uint8_t state; /*!< Transfer state machine current state. */ + uint16_t remainingBytes; /*!< Remaining byte count in current state. */ + uint8_t *buf; /*!< Buffer pointer for current state. */ + uint16_t commandBuffer[6]; /*!< LPI2C command sequence. When all 6 command words are used: + Start&addr&write[1 word] + subaddr[4 words] + restart&addr&read[1 word] */ + lpi2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + lpi2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */ + void *userData; /*!< Application data passed to callback. */ +}; + +/*! @brief Typedef for master interrupt handler, used internally for LPI2C master interrupt and EDMA transactional APIs. + */ +typedef void (*lpi2c_master_isr_t)(LPI2C_Type *base, void *handle); + +/*! @} */ + +/*! + * @addtogroup lpi2c_slave_driver + * @{ + */ + +/*! + * @brief LPI2C slave peripheral flags. + * + * The following status register flags can be cleared: + * - #kLPI2C_SlaveRepeatedStartDetectFlag + * - #kLPI2C_SlaveStopDetectFlag + * - #kLPI2C_SlaveBitErrFlag + * - #kLPI2C_SlaveFifoErrFlag + * + * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as + * interrupts. + * + * @note These enumerations are meant to be OR'd together to form a bit mask. + */ +enum _lpi2c_slave_flags +{ + kLPI2C_SlaveTxReadyFlag = LPI2C_SSR_TDF_MASK, /*!< Transmit data flag */ + kLPI2C_SlaveRxReadyFlag = LPI2C_SSR_RDF_MASK, /*!< Receive data flag */ + kLPI2C_SlaveAddressValidFlag = LPI2C_SSR_AVF_MASK, /*!< Address valid flag */ + kLPI2C_SlaveTransmitAckFlag = LPI2C_SSR_TAF_MASK, /*!< Transmit ACK flag */ + kLPI2C_SlaveRepeatedStartDetectFlag = LPI2C_SSR_RSF_MASK, /*!< Repeated start detect flag */ + kLPI2C_SlaveStopDetectFlag = LPI2C_SSR_SDF_MASK, /*!< Stop detect flag */ + kLPI2C_SlaveBitErrFlag = LPI2C_SSR_BEF_MASK, /*!< Bit error flag */ + kLPI2C_SlaveFifoErrFlag = LPI2C_SSR_FEF_MASK, /*!< FIFO error flag */ + kLPI2C_SlaveAddressMatch0Flag = LPI2C_SSR_AM0F_MASK, /*!< Address match 0 flag */ + kLPI2C_SlaveAddressMatch1Flag = LPI2C_SSR_AM1F_MASK, /*!< Address match 1 flag */ + kLPI2C_SlaveGeneralCallFlag = LPI2C_SSR_GCF_MASK, /*!< General call flag */ + kLPI2C_SlaveBusyFlag = LPI2C_SSR_SBF_MASK, /*!< Master busy flag */ + kLPI2C_SlaveBusBusyFlag = LPI2C_SSR_BBF_MASK, /*!< Bus busy flag */ + /*! All flags which are cleared by the driver upon starting a transfer. */ + kLPI2C_SlaveClearFlags = kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveBitErrFlag | + kLPI2C_SlaveFifoErrFlag, + /*! IRQ sources enabled by the non-blocking transactional API. */ + kLPI2C_SlaveIrqFlags = kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag | + kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag | + kLPI2C_SlaveTransmitAckFlag | kLPI2C_SlaveAddressValidFlag, + /*! Errors to check for. */ + kLPI2C_SlaveErrorFlags = kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag +}; + +/*! @brief LPI2C slave address match options. */ +typedef enum _lpi2c_slave_address_match +{ + kLPI2C_MatchAddress0 = 0U, /*!< Match only address 0. */ + kLPI2C_MatchAddress0OrAddress1 = 2U, /*!< Match either address 0 or address 1. */ + kLPI2C_MatchAddress0ThroughAddress1 = 6U, /*!< Match a range of slave addresses from address 0 through address 1. */ +} lpi2c_slave_address_match_t; + +/*! + * @brief Structure with settings to initialize the LPI2C slave module. + * + * This structure holds configuration settings for the LPI2C slave peripheral. To initialize this + * structure to reasonable defaults, call the LPI2C_SlaveGetDefaultConfig() function and + * pass a pointer to your configuration structure instance. + * + * The configuration structure can be made constant so it resides in flash. + */ +typedef struct _lpi2c_slave_config +{ + bool enableSlave; /*!< Enable slave mode. */ + uint8_t address0; /*!< Slave's 7-bit address. */ + uint8_t address1; /*!< Alternate slave 7-bit address. */ + lpi2c_slave_address_match_t addressMatchMode; /*!< Address matching options. */ + bool filterDozeEnable; /*!< Enable digital glitch filter in doze mode. */ + bool filterEnable; /*!< Enable digital glitch filter. */ + bool enableGeneralCall; /*!< Enable general call address matching. */ + struct + { + bool enableAck; /*!< Enables SCL clock stretching during slave-transmit address byte(s) + and slave-receiver address and data byte(s) to allow software to + write the Transmit ACK Register before the ACK or NACK is transmitted. + Clock stretching occurs when transmitting the 9th bit. When + enableAckSCLStall is enabled, there is no need to set either + enableRxDataSCLStall or enableAddressSCLStall. */ + bool enableTx; /*!< Enables SCL clock stretching when the transmit data flag is set + during a slave-transmit transfer. */ + bool enableRx; /*!< Enables SCL clock stretching when receive data flag is set during + a slave-receive transfer. */ + bool enableAddress; /*!< Enables SCL clock stretching when the address valid flag is asserted. */ + } sclStall; /*!< SCL stall enable options. */ + bool ignoreAck; /*!< Continue transfers after a NACK is detected. */ + bool enableReceivedAddressRead; /*!< Enable reading the address received address as the first byte of data. */ + uint32_t sdaGlitchFilterWidth_ns; /*!< Width in nanoseconds of the digital filter on the SDA signal. Set to 0 to + disable. */ + uint32_t sclGlitchFilterWidth_ns; /*!< Width in nanoseconds of the digital filter on the SCL signal. Set to 0 to + disable. */ + uint32_t dataValidDelay_ns; /*!< Width in nanoseconds of the data valid delay. */ + uint32_t clockHoldTime_ns; /*!< Width in nanoseconds of the clock hold time. */ +} lpi2c_slave_config_t; + +/*! + * @brief Set of events sent to the callback for non blocking slave transfers. + * + * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together + * events is passed to LPI2C_SlaveTransferNonBlocking() in order to specify which events to enable. + * Then, when the slave callback is invoked, it is passed the current event through its @a transfer + * parameter. + * + * @note These enumerations are meant to be OR'd together to form a bit mask of events. + */ +typedef enum _lpi2c_slave_transfer_event +{ + kLPI2C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */ + kLPI2C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit + (slave-transmitter role). */ + kLPI2C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received + data (slave-receiver role). */ + kLPI2C_SlaveTransmitAckEvent = 0x08U, /*!< Callback needs to either transmit an ACK or NACK. */ + kLPI2C_SlaveRepeatedStartEvent = 0x10U, /*!< A repeated start was detected. */ + kLPI2C_SlaveCompletionEvent = 0x20U, /*!< A stop was detected, completing the transfer. */ + + /*! Bit mask of all available events. */ + kLPI2C_SlaveAllEvents = kLPI2C_SlaveAddressMatchEvent | kLPI2C_SlaveTransmitEvent | kLPI2C_SlaveReceiveEvent | + kLPI2C_SlaveTransmitAckEvent | kLPI2C_SlaveRepeatedStartEvent | kLPI2C_SlaveCompletionEvent, +} lpi2c_slave_transfer_event_t; + +/*! @brief LPI2C slave transfer structure */ +typedef struct _lpi2c_slave_transfer +{ + lpi2c_slave_transfer_event_t event; /*!< Reason the callback is being invoked. */ + uint8_t receivedAddress; /*!< Matching address send by master. */ + uint8_t *data; /*!< Transfer buffer */ + size_t dataSize; /*!< Transfer size */ + status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for + #kLPI2C_SlaveCompletionEvent. */ + size_t transferredCount; /*!< Number of bytes actually transferred since start or last repeated start. */ +} lpi2c_slave_transfer_t; + +/* Forward declaration. */ +/*! @brief LPI2C slave handle structure. */ +typedef struct _lpi2c_slave_handle lpi2c_slave_handle_t; + +/*! + * @brief Slave event callback function pointer type. + * + * This callback is used only for the slave non-blocking transfer API. To install a callback, + * use the LPI2C_SlaveSetCallback() function after you have created a handle. + * + * @param base Base address for the LPI2C instance on which the event occurred. + * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*lpi2c_slave_transfer_callback_t)(LPI2C_Type *base, lpi2c_slave_transfer_t *transfer, void *userData); + +/*! + * @brief LPI2C slave handle structure. + * @note The contents of this structure are private and subject to change. + */ +struct _lpi2c_slave_handle +{ + lpi2c_slave_transfer_t transfer; /*!< LPI2C slave transfer copy. */ + bool isBusy; /*!< Whether transfer is busy. */ + bool wasTransmit; /*!< Whether the last transfer was a transmit. */ + uint32_t eventMask; /*!< Mask of enabled events. */ + uint32_t transferredCount; /*!< Count of bytes transferred. */ + lpi2c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */ + void *userData; /*!< Callback parameter passed to callback. */ +}; + +/*! @} */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! Array to map LPI2C instance number to IRQ number, used internally for LPI2C master interrupt and EDMA transactional +APIs. */ +extern IRQn_Type const kLpi2cIrqs[]; + +/*! Pointer to master IRQ handler for each instance, used internally for LPI2C master interrupt and EDMA transactional +APIs. */ +extern lpi2c_master_isr_t s_lpi2cMasterIsr; + +/*! Pointers to master handles for each instance, used internally for LPI2C master interrupt and EDMA transactional +APIs. */ +extern void *s_lpi2cMasterHandle[]; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Returns an instance number given a base address. + * + * If an invalid base address is passed, debug builds will assert. Release builds will just return + * instance number 0. + * + * @param base The LPI2C peripheral base address. + * @return LPI2C instance number starting from 0. + */ +uint32_t LPI2C_GetInstance(LPI2C_Type *base); + +/*! + * @addtogroup lpi2c_master_driver + * @{ + */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Provides a default configuration for the LPI2C master peripheral. + * + * This function provides the following default configuration for the LPI2C master peripheral: + * @code + * masterConfig->enableMaster = true; + * masterConfig->debugEnable = false; + * masterConfig->ignoreAck = false; + * masterConfig->pinConfig = kLPI2C_2PinOpenDrain; + * masterConfig->baudRate_Hz = 100000U; + * masterConfig->busIdleTimeout_ns = 0; + * masterConfig->pinLowTimeout_ns = 0; + * masterConfig->sdaGlitchFilterWidth_ns = 0; + * masterConfig->sclGlitchFilterWidth_ns = 0; + * masterConfig->hostRequest.enable = false; + * masterConfig->hostRequest.source = kLPI2C_HostRequestExternalPin; + * masterConfig->hostRequest.polarity = kLPI2C_HostRequestPinActiveHigh; + * @endcode + * + * After calling this function, you can override any settings in order to customize the configuration, + * prior to initializing the master driver with LPI2C_MasterInit(). + * + * @param[out] masterConfig User provided configuration structure for default values. Refer to #lpi2c_master_config_t. + */ +void LPI2C_MasterGetDefaultConfig(lpi2c_master_config_t *masterConfig); + +/*! + * @brief Initializes the LPI2C master peripheral. + * + * This function enables the peripheral clock and initializes the LPI2C master peripheral as described by the user + * provided configuration. A software reset is performed prior to configuration. + * + * @param base The LPI2C peripheral base address. + * @param masterConfig User provided peripheral configuration. Use LPI2C_MasterGetDefaultConfig() to get a set of + * defaults + * that you can override. + * @param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the baud rate divisors, + * filter widths, and timeout periods. + */ +void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfig, uint32_t sourceClock_Hz); + +/*! + * @brief Deinitializes the LPI2C master peripheral. + * + * This function disables the LPI2C master peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The LPI2C peripheral base address. + */ +void LPI2C_MasterDeinit(LPI2C_Type *base); + +/*! + * @brief Configures LPI2C master data match feature. + * + * @param base The LPI2C peripheral base address. + * @param matchConfig Settings for the data match feature. + */ +void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *matchConfig); + +/*! + * @brief Convert provided flags to status code, and clear any errors if present. + * @param base The LPI2C peripheral base address. + * @param status Current status flags value that will be checked. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_PinLowTimeout + * @retval #kStatus_LPI2C_ArbitrationLost + * @retval #kStatus_LPI2C_Nak + * @retval #kStatus_LPI2C_FifoError + */ +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status); + +/*! + * @brief Make sure the bus isn't already busy. + * + * A busy bus is allowed if we are the one driving it. + * + * @param base The LPI2C peripheral base address. + * @retval #kStatus_Success + * @retval #kStatus_LPI2C_Busy + */ +/* Not static so it can be used from fsl_lpi2c_edma.c. */ +status_t LPI2C_CheckForBusyBus(LPI2C_Type *base); + +/*! + * @brief Performs a software reset. + * + * Restores the LPI2C master peripheral to reset conditions. + * + * @param base The LPI2C peripheral base address. + */ +static inline void LPI2C_MasterReset(LPI2C_Type *base) +{ + base->MCR = LPI2C_MCR_RST_MASK; + base->MCR = 0; +} + +/*! + * @brief Enables or disables the LPI2C module as master. + * + * @param base The LPI2C peripheral base address. + * @param enable Pass true to enable or false to disable the specified LPI2C as master. + */ +static inline void LPI2C_MasterEnable(LPI2C_Type *base, bool enable) +{ + base->MCR = (base->MCR & ~LPI2C_MCR_MEN_MASK) | LPI2C_MCR_MEN(enable); +} + +/*! @}*/ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the LPI2C master status flags. + * + * A bit mask with the state of all LPI2C master status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The LPI2C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _lpi2c_master_flags + */ +static inline uint32_t LPI2C_MasterGetStatusFlags(LPI2C_Type *base) +{ + return base->MSR; +} + +/*! + * @brief Clears the LPI2C master status flag state. + * + * The following status register flags can be cleared: + * - #kLPI2C_MasterEndOfPacketFlag + * - #kLPI2C_MasterStopDetectFlag + * - #kLPI2C_MasterNackDetectFlag + * - #kLPI2C_MasterArbitrationLostFlag + * - #kLPI2C_MasterFifoErrFlag + * - #kLPI2C_MasterPinLowTimeoutFlag + * - #kLPI2C_MasterDataMatchFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The LPI2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * _lpi2c_master_flags enumerators OR'd together. You may pass the result of a previous call to + * LPI2C_MasterGetStatusFlags(). + * @see _lpi2c_master_flags. + */ +static inline void LPI2C_MasterClearStatusFlags(LPI2C_Type *base, uint32_t statusMask) +{ + base->MSR = statusMask; +} + +/*! @}*/ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the LPI2C master interrupt requests. + * + * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See _lpi2c_master_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_MasterEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->MIER |= interruptMask; +} + +/*! + * @brief Disables the LPI2C master interrupt requests. + * + * All flags except #kLPI2C_MasterBusyFlag and #kLPI2C_MasterBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See _lpi2c_master_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_MasterDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->MIER &= ~interruptMask; +} + +/*! + * @brief Returns the set of currently enabled LPI2C master interrupt requests. + * + * @param base The LPI2C peripheral base address. + * @return A bitmask composed of _lpi2c_master_flags enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t LPI2C_MasterGetEnabledInterrupts(LPI2C_Type *base) +{ + return base->MIER; +} + +/*! @}*/ + +/*! + * @name DMA control + * @{ + */ + +/*! + * @brief Enables or disables LPI2C master DMA requests. + * + * @param base The LPI2C peripheral base address. + * @param enableTx Enable flag for transmit DMA request. Pass true for enable, false for disable. + * @param enableRx Enable flag for receive DMA request. Pass true for enable, false for disable. + */ +static inline void LPI2C_MasterEnableDMA(LPI2C_Type *base, bool enableTx, bool enableRx) +{ + base->MDER = LPI2C_MDER_TDDE(enableTx) | LPI2C_MDER_RDDE(enableRx); +} + +/*! + * @brief Gets LPI2C master transmit data register address for DMA transfer. + * + * @param base The LPI2C peripheral base address. + * @return The LPI2C Master Transmit Data Register address. + */ +static inline uint32_t LPI2C_MasterGetTxFifoAddress(LPI2C_Type *base) +{ + return (uint32_t)(uintptr_t)&base->MTDR; +} + +/*! + * @brief Gets LPI2C master receive data register address for DMA transfer. + * + * @param base The LPI2C peripheral base address. + * @return The LPI2C Master Receive Data Register address. + */ +static inline uint32_t LPI2C_MasterGetRxFifoAddress(LPI2C_Type *base) +{ + return (uint32_t)(uintptr_t)&base->MRDR; +} + +/*! @}*/ + +/*! + * @name FIFO control + * @{ + */ + +/*! + * @brief Sets the watermarks for LPI2C master FIFOs. + * + * @param base The LPI2C peripheral base address. + * @param txWords Transmit FIFO watermark value in words. The #kLPI2C_MasterTxReadyFlag flag is set whenever + * the number of words in the transmit FIFO is equal or less than @a txWords. Writing a value equal or + * greater than the FIFO size is truncated. + * @param rxWords Receive FIFO watermark value in words. The #kLPI2C_MasterRxReadyFlag flag is set whenever + * the number of words in the receive FIFO is greater than @a rxWords. Writing a value equal or greater + * than the FIFO size is truncated. + */ +static inline void LPI2C_MasterSetWatermarks(LPI2C_Type *base, size_t txWords, size_t rxWords) +{ + base->MFCR = LPI2C_MFCR_TXWATER(txWords) | LPI2C_MFCR_RXWATER(rxWords); +} + +/*! + * @brief Gets the current number of words in the LPI2C master FIFOs. + * + * @param base The LPI2C peripheral base address. + * @param[out] txCount Pointer through which the current number of words in the transmit FIFO is returned. + * Pass NULL if this value is not required. + * @param[out] rxCount Pointer through which the current number of words in the receive FIFO is returned. + * Pass NULL if this value is not required. + */ +static inline void LPI2C_MasterGetFifoCounts(LPI2C_Type *base, size_t *rxCount, size_t *txCount) +{ + if (NULL != txCount) + { + *txCount = (base->MFSR & LPI2C_MFSR_TXCOUNT_MASK) >> LPI2C_MFSR_TXCOUNT_SHIFT; + } + if (NULL != rxCount) + { + *rxCount = (base->MFSR & LPI2C_MFSR_RXCOUNT_MASK) >> LPI2C_MFSR_RXCOUNT_SHIFT; + } +} + +/*! @}*/ + +/*! + * @name Bus operations + * @{ + */ + +/*! + * @brief Sets the I2C bus frequency for master transactions. + * + * The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud + * rate. Do not call this function during a transfer, or the transfer is aborted. + * + * @note Please note that the second parameter is the clock frequency of LPI2C module, the third + * parameter means user configured bus baudrate, this implementation is different from other I2C drivers + * which use baudrate configuration as second parameter and source clock frequency as third parameter. + * + * @param base The LPI2C peripheral base address. + * @param sourceClock_Hz LPI2C functional clock frequency in Hertz. + * @param baudRate_Hz Requested bus frequency in Hertz. + */ +void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz); + +/*! + * @brief Returns whether the bus is idle. + * + * Requires the master mode to be enabled. + * + * @param base The LPI2C peripheral base address. + * @retval true Bus is busy. + * @retval false Bus is idle. + */ +static inline bool LPI2C_MasterGetBusIdleState(LPI2C_Type *base) +{ + return ((base->MSR & LPI2C_MSR_BBF_MASK) >> LPI2C_MSR_BBF_SHIFT) == 1U ? true : false; +} + +/*! + * @brief Sends a START signal and slave address on the I2C bus. + * + * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure + * that another master is not occupying the bus. Then a START signal is transmitted, followed by the + * 7-bit address specified in the @a address parameter. Note that this function does not actually wait + * until the START and address are successfully sent on the bus before returning. + * + * @param base The LPI2C peripheral base address. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @retval kStatus_Success START signal and address were successfully enqueued in the transmit FIFO. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + */ +status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir); + +/*! + * @brief Sends a repeated START signal and slave address on the I2C bus. + * + * This function is used to send a Repeated START signal when a transfer is already in progress. Like + * LPI2C_MasterStart(), it also sends the specified 7-bit address. + * + * @note This function exists primarily to maintain compatible APIs between LPI2C and I2C drivers, + * as well as to better document the intent of code that uses these APIs. + * + * @param base The LPI2C peripheral base address. + * @param address 7-bit slave device address, in bits [6:0]. + * @param dir Master transfer direction, either #kLPI2C_Read or #kLPI2C_Write. This parameter is used to set + * the R/w bit (bit 0) in the transmitted slave address. + * @retval kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + */ +static inline status_t LPI2C_MasterRepeatedStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t dir) +{ + return LPI2C_MasterStart(base, address, dir); +} + +/*! + * @brief Performs a polling send transfer on the I2C bus. + * + * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may + * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this + * function returns #kStatus_LPI2C_Nak. + * + * @param base The LPI2C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @retval kStatus_Success Data was sent successfully. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or over run. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterSend(LPI2C_Type *base, void *txBuff, size_t txSize); + +/*! + * @brief Performs a polling receive transfer on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @retval kStatus_Success Data was received successfully. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize); + +/*! + * @brief Sends a STOP signal on the I2C bus. + * + * This function does not return until the STOP signal is seen on the bus, or an error occurs. + * + * @param base The LPI2C peripheral base address. + * @retval kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterStop(LPI2C_Type *base); + +/*! + * @brief Performs a master polling transfer on the I2C bus. + * + * @note The API does not return until the transfer succeeds or fails due + * to error happens during transfer. + * + * @param base The LPI2C peripheral base address. + * @param transfer Pointer to the transfer structure. + * @retval kStatus_Success Data was received successfully. + * @retval #kStatus_LPI2C_Busy Another master is currently utilizing the bus. + * @retval #kStatus_LPI2C_Nak The slave device sent a NAK in response to a byte. + * @retval #kStatus_LPI2C_FifoError FIFO under run or overrun. + * @retval #kStatus_LPI2C_ArbitrationLost Arbitration lost error. + * @retval #kStatus_LPI2C_PinLowTimeout SCL or SDA were held low longer than the timeout. + */ +status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer); + +/*! @}*/ + +/*! + * @name Non-blocking + * @{ + */ + +/*! + * @brief Creates a new handle for the LPI2C master non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called. + * + * + * @note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + * + * @param base The LPI2C peripheral base address. + * @param[out] handle Pointer to the LPI2C master driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a non-blocking transaction on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param transfer The pointer to the transfer descriptor. + * @retval kStatus_Success The transaction was started successfully. + * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking + * transaction is already in progress. + */ +status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, + lpi2c_master_handle_t *handle, + lpi2c_master_transfer_t *transfer); + +/*! + * @brief Returns number of bytes transferred so far. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param[out] count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_Success + * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress. + */ +status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *handle, size_t *count); + +/*! + * @brief Terminates a non-blocking LPI2C master transmission early. + * + * @note It is not safe to call this function from an IRQ handler that has a higher priority than the + * LPI2C peripheral's IRQ priority. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + */ +void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle); + +/*! @}*/ + +/*! + * @name IRQ handler + * @{ + */ + +/*! + * @brief Reusable routine to handle master interrupts. + * @note This function does not need to be called unless you are reimplementing the + * nonblocking API's interrupt handler routines to add special functionality. + * @param base The LPI2C peripheral base address. + * @param lpi2cMasterHandle Pointer to the LPI2C master driver handle. + */ +void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, void *lpi2cMasterHandle); + +/*! @}*/ + +/*! @} */ + +/*! + * @addtogroup lpi2c_slave_driver + * @{ + */ + +/*! + * @name Slave initialization and deinitialization + * @{ + */ + +/*! + * @brief Provides a default configuration for the LPI2C slave peripheral. + * + * This function provides the following default configuration for the LPI2C slave peripheral: + * @code + * slaveConfig->enableSlave = true; + * slaveConfig->address0 = 0U; + * slaveConfig->address1 = 0U; + * slaveConfig->addressMatchMode = kLPI2C_MatchAddress0; + * slaveConfig->filterDozeEnable = true; + * slaveConfig->filterEnable = true; + * slaveConfig->enableGeneralCall = false; + * slaveConfig->sclStall.enableAck = false; + * slaveConfig->sclStall.enableTx = true; + * slaveConfig->sclStall.enableRx = true; + * slaveConfig->sclStall.enableAddress = true; + * slaveConfig->ignoreAck = false; + * slaveConfig->enableReceivedAddressRead = false; + * slaveConfig->sdaGlitchFilterWidth_ns = 0; + * slaveConfig->sclGlitchFilterWidth_ns = 0; + * slaveConfig->dataValidDelay_ns = 0; + * slaveConfig->clockHoldTime_ns = 0; + * @endcode + * + * After calling this function, override any settings to customize the configuration, + * prior to initializing the master driver with LPI2C_SlaveInit(). Be sure to override at least the @a + * address0 member of the configuration structure with the desired slave address. + * + * @param[out] slaveConfig User provided configuration structure that is set to default values. Refer to + * #lpi2c_slave_config_t. + */ +void LPI2C_SlaveGetDefaultConfig(lpi2c_slave_config_t *slaveConfig); + +/*! + * @brief Initializes the LPI2C slave peripheral. + * + * This function enables the peripheral clock and initializes the LPI2C slave peripheral as described by the user + * provided configuration. + * + * @param base The LPI2C peripheral base address. + * @param slaveConfig User provided peripheral configuration. Use LPI2C_SlaveGetDefaultConfig() to get a set of defaults + * that you can override. + * @param sourceClock_Hz Frequency in Hertz of the LPI2C functional clock. Used to calculate the filter widths, + * data valid delay, and clock hold time. + */ +void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t sourceClock_Hz); + +/*! + * @brief Deinitializes the LPI2C slave peripheral. + * + * This function disables the LPI2C slave peripheral and gates the clock. It also performs a software + * reset to restore the peripheral to reset conditions. + * + * @param base The LPI2C peripheral base address. + */ +void LPI2C_SlaveDeinit(LPI2C_Type *base); + +/*! + * @brief Performs a software reset of the LPI2C slave peripheral. + * + * @param base The LPI2C peripheral base address. + */ +static inline void LPI2C_SlaveReset(LPI2C_Type *base) +{ + base->SCR = LPI2C_SCR_RST_MASK; + base->SCR = 0; +} + +/*! + * @brief Enables or disables the LPI2C module as slave. + * + * @param base The LPI2C peripheral base address. + * @param enable Pass true to enable or false to disable the specified LPI2C as slave. + */ +static inline void LPI2C_SlaveEnable(LPI2C_Type *base, bool enable) +{ + base->SCR = (base->SCR & ~LPI2C_SCR_SEN_MASK) | LPI2C_SCR_SEN(enable); +} + +/*! @}*/ + +/*! + * @name Slave status + * @{ + */ + +/*! + * @brief Gets the LPI2C slave status flags. + * + * A bit mask with the state of all LPI2C slave status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * @param base The LPI2C peripheral base address. + * @return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * @see _lpi2c_slave_flags + */ +static inline uint32_t LPI2C_SlaveGetStatusFlags(LPI2C_Type *base) +{ + return base->SSR; +} + +/*! + * @brief Clears the LPI2C status flag state. + * + * The following status register flags can be cleared: + * - #kLPI2C_SlaveRepeatedStartDetectFlag + * - #kLPI2C_SlaveStopDetectFlag + * - #kLPI2C_SlaveBitErrFlag + * - #kLPI2C_SlaveFifoErrFlag + * + * Attempts to clear other flags has no effect. + * + * @param base The LPI2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of + * #_lpi2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to + * LPI2C_SlaveGetStatusFlags(). + * @see _lpi2c_slave_flags. + */ +static inline void LPI2C_SlaveClearStatusFlags(LPI2C_Type *base, uint32_t statusMask) +{ + base->SSR = statusMask; +} +/*! @}*/ + +/*! + * @name Slave interrupts + * @{ + */ + +/*! + * @brief Enables the LPI2C slave interrupt requests. + * + * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to enable. See #_lpi2c_slave_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_SlaveEnableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->SIER |= interruptMask; +} + +/*! + * @brief Disables the LPI2C slave interrupt requests. + * + * All flags except #kLPI2C_SlaveBusyFlag and #kLPI2C_SlaveBusBusyFlag can be enabled as + * interrupts. + * + * @param base The LPI2C peripheral base address. + * @param interruptMask Bit mask of interrupts to disable. See #_lpi2c_slave_flags for the set + * of constants that should be OR'd together to form the bit mask. + */ +static inline void LPI2C_SlaveDisableInterrupts(LPI2C_Type *base, uint32_t interruptMask) +{ + base->SIER &= ~interruptMask; +} + +/*! + * @brief Returns the set of currently enabled LPI2C slave interrupt requests. + * @param base The LPI2C peripheral base address. + * @return A bitmask composed of #_lpi2c_slave_flags enumerators OR'd together to indicate the + * set of enabled interrupts. + */ +static inline uint32_t LPI2C_SlaveGetEnabledInterrupts(LPI2C_Type *base) +{ + return base->SIER; +} + +/*! @}*/ + +/*! + * @name Slave DMA control + * @{ + */ + +/*! + * @brief Enables or disables the LPI2C slave peripheral DMA requests. + * + * @param base The LPI2C peripheral base address. + * @param enableAddressValid Enable flag for the address valid DMA request. Pass true for enable, false for disable. + * The address valid DMA request is shared with the receive data DMA request. + * @param enableRx Enable flag for the receive data DMA request. Pass true for enable, false for disable. + * @param enableTx Enable flag for the transmit data DMA request. Pass true for enable, false for disable. + */ +static inline void LPI2C_SlaveEnableDMA(LPI2C_Type *base, bool enableAddressValid, bool enableRx, bool enableTx) +{ + base->SDER = (base->SDER & ~(LPI2C_SDER_AVDE_MASK | LPI2C_SDER_RDDE_MASK | LPI2C_SDER_TDDE_MASK)) | + LPI2C_SDER_AVDE(enableAddressValid) | LPI2C_SDER_RDDE(enableRx) | LPI2C_SDER_TDDE(enableTx); +} + +/*! @}*/ + +/*! + * @name Slave bus operations + * @{ + */ + +/*! + * @brief Returns whether the bus is idle. + * + * Requires the slave mode to be enabled. + * + * @param base The LPI2C peripheral base address. + * @retval true Bus is busy. + * @retval false Bus is idle. + */ +static inline bool LPI2C_SlaveGetBusIdleState(LPI2C_Type *base) +{ + return ((base->SSR & LPI2C_SSR_BBF_MASK) >> LPI2C_SSR_BBF_SHIFT) == 1U ? true : false; +} + +/*! + * @brief Transmits either an ACK or NAK on the I2C bus in response to a byte from the master. + * + * Use this function to send an ACK or NAK when the #kLPI2C_SlaveTransmitAckFlag is asserted. This + * only happens if you enable the sclStall.enableAck field of the ::lpi2c_slave_config_t configuration + * structure used to initialize the slave peripheral. + * + * @param base The LPI2C peripheral base address. + * @param ackOrNack Pass true for an ACK or false for a NAK. + */ +static inline void LPI2C_SlaveTransmitAck(LPI2C_Type *base, bool ackOrNack) +{ + base->STAR = LPI2C_STAR_TXNACK(!ackOrNack); +} + +/*! + * @brief Enables or disables ACKSTALL. + * + * When enables ACKSTALL, software can transmit either an ACK or NAK on the I2C bus in response to + * a byte from the master. + * + * @param base The LPI2C peripheral base address. + * @param enable True will enable ACKSTALL,false will disable ACKSTALL. + */ +static inline void LPI2C_SlaveEnableAckStall(LPI2C_Type *base, bool enable) +{ + if (enable) + { + base->SCFGR1 |= LPI2C_SCFGR1_ACKSTALL_MASK; + } + else + { + base->SCFGR1 &= ~LPI2C_SCFGR1_ACKSTALL_MASK; + } +} + +/*! + * @brief Returns the slave address sent by the I2C master. + * + * This function should only be called if the #kLPI2C_SlaveAddressValidFlag is asserted. + * + * @param base The LPI2C peripheral base address. + * @return The 8-bit address matched by the LPI2C slave. Bit 0 contains the R/w direction bit, and + * the 7-bit slave address is in the upper 7 bits. + */ +static inline uint32_t LPI2C_SlaveGetReceivedAddress(LPI2C_Type *base) +{ + return base->SASR & LPI2C_SASR_RADDR_MASK; +} + +/*! + * @brief Performs a polling send transfer on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @param[out] actualTxSize + * @return Error or success status returned by API. + */ +status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *actualTxSize); + +/*! + * @brief Performs a polling receive transfer on the I2C bus. + * + * @param base The LPI2C peripheral base address. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @param[out] actualRxSize + * @return Error or success status returned by API. + */ +status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize); + +/*! @}*/ + +/*! + * @name Slave non-blocking + * @{ + */ + +/*! + * @brief Creates a new handle for the LPI2C slave non-blocking APIs. + * + * The creation of a handle is for use with the non-blocking APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_SlaveTransferAbort() API shall be called. + * + * @note The function also enables the NVIC IRQ for the input LPI2C. Need to notice + * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to + * enable the associated INTMUX IRQ in application. + + * @param base The LPI2C peripheral base address. + * @param[out] handle Pointer to the LPI2C slave driver handle. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, + lpi2c_slave_handle_t *handle, + lpi2c_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and LPI2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to LPI2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to + * the OR'd combination of #lpi2c_slave_transfer_event_t enumerators for the events you wish to receive. + * The #kLPI2C_SlaveTransmitEvent and #kLPI2C_SlaveReceiveEvent events are always enabled and do not need + * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and + * receive events that are always enabled. In addition, the #kLPI2C_SlaveAllEvents constant is provided as + * a convenient way to enable all events. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to lpi2c_slave_handle_t structure which stores the transfer state. + * @param eventMask Bit mask formed by OR'ing together #lpi2c_slave_transfer_event_t enumerators to specify + * which events to send to the callback. Other accepted values are 0 to get a default set of + * only the transmit and receive events, and #kLPI2C_SlaveAllEvents to enable all events. + * + * @retval kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_LPI2C_Busy Slave transfers have already been started on this handle. + */ +status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t *handle, uint32_t eventMask); + +/*! + * @brief Gets the slave transfer status during a non-blocking transfer. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to i2c_slave_handle_t structure. + * @param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not + * required. + * @retval kStatus_Success + * @retval kStatus_NoTransferInProgress + */ +status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *handle, size_t *count); + +/*! + * @brief Aborts the slave non-blocking transfers. + * @note This API could be called at any time to stop slave for handling the bus events. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to lpi2c_slave_handle_t structure which stores the transfer state. + */ +void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle); + +/*! @}*/ + +/*! + * @name Slave IRQ handler + * @{ + */ + +/*! + * @brief Reusable routine to handle slave interrupts. + * @note This function does not need to be called unless you are reimplementing the + * non blocking API's interrupt handler routines to add special functionality. + * @param base The LPI2C peripheral base address. + * @param handle Pointer to lpi2c_slave_handle_t structure which stores the transfer state. + */ +void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle); + +/*! @}*/ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif +/*! @} */ +#endif /* FSL_LPI2C_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpi2c_edma.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpi2c_edma.c new file mode 100644 index 00000000000..9c57f55006b --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpi2c_edma.c @@ -0,0 +1,659 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpi2c_edma.h" +#include +#include + +/* + * $Coverage Justification Reference$ + * + * $Justification fsl_lpi2c_edma_c_ref_1$ + * Need multiple master and slave modules on bus to simulate the true branch + * + * $Justification fsl_lpi2c_edma_c_ref_2$ + * FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(X) is a constant. + * + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpi2c_edma" +#endif + +/* @brief Mask to align an address to edma_tcd_t size. */ +#define ALIGN_TCD_SIZE_MASK (sizeof(edma_tcd_t) - 1U) + +/* ! @brief LPI2C master fifo commands. */ +enum _lpi2c_master_fifo_cmd +{ + kTxDataCmd = LPI2C_MTDR_CMD(0x0U), /*!< Transmit DATA[7:0] */ + kRxDataCmd = LPI2C_MTDR_CMD(0X1U), /*!< Receive (DATA[7:0] + 1) bytes */ + kStopCmd = LPI2C_MTDR_CMD(0x2U), /*!< Generate STOP condition */ + kStartCmd = LPI2C_MTDR_CMD(0x4U), /*!< Generate(repeated) START and transmit address in DATA[[7:0] */ +}; + +/*! @brief States for the state machine used by transactional APIs. */ +enum _lpi2c_transfer_states +{ + kIdleState = 0, + kSendCommandState, + kIssueReadCommandState, + kTransferDataState, + kStopState, + kWaitForCompletionState, +}; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*lpi2c_isr_t)(LPI2C_Type *base, void *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Prepares the command buffer with the sequence of commands needed to send the requested transaction. + * @param handle Master DMA driver handle. + * @return Number of command words. + */ +static uint32_t LPI2C_GenerateCommands(lpi2c_master_edma_handle_t *handle); + +/*! + * @brief DMA completion callback. + * @param dmaHandle DMA channel handle for the channel that completed. + * @param userData User data associated with the channel handle. For this callback, the user data is the + * LPI2C DMA driver handle. + * @param isTransferDone Whether the DMA transfer has completed. + * @param tcds Number of TCDs that completed. + */ +static void LPI2C_MasterEDMACallback(edma_handle_t *dmaHandle, void *userData, bool isTransferDone, uint32_t tcds); + +/*! + * @brief LPI2C master edma transfer IRQ handle routine. + * + * This API handles the LPI2C bus error status and invoke callback if needed. + * + * @param base The LPI2C peripheral base address. + * @param lpi2cMasterEdmaHandle Pointer to the LPI2C master edma handle. + */ +static void LPI2C_MasterTransferEdmaHandleIRQ(LPI2C_Type *base, void *lpi2cMasterEdmaHandle); +/******************************************************************************* + * Variables + ******************************************************************************/ + +static uint32_t lpi2c_edma_RecSetting = 0x02; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Create a new handle for the LPI2C master DMA APIs. + * + * The creation of a handle is for use with the DMA APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_MasterTransferAbortEDMA() API shall be called. + * + * For devices where the LPI2C send and receive DMA requests are OR'd together, the a txDmaHandle + * parameter is ignored and may be set to NULL. + * + * param base The LPI2C peripheral base address. + * param[out] handle Pointer to the LPI2C master driver handle. + * param rxDmaHandle Handle for the eDMA receive channel. Created by the user prior to calling this function. + * param txDmaHandle Handle for the eDMA transmit channel. Created by the user prior to calling this function. + * param callback User provided pointer to the asynchronous callback function. + * param userData User provided pointer to the application callback data. + */ +void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle, + lpi2c_master_edma_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + assert(rxDmaHandle != NULL); + assert(txDmaHandle != NULL); + + /* Look up instance number */ + uint32_t instance = LPI2C_GetInstance(base); + + /* Clear out the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Set up the handle. For combined rx/tx DMA requests, the tx channel handle is set to the rx handle */ + /* in order to make the transfer API code simpler. */ + handle->base = base; + handle->completionCallback = callback; + handle->userData = userData; + handle->rx = rxDmaHandle; + handle->tx = (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) > 0) ? txDmaHandle : rxDmaHandle; + + /* Save the handle in global variables to support the double weak mechanism. */ + s_lpi2cMasterHandle[instance] = handle; + + /* Set LPI2C_MasterTransferEdmaHandleIRQ as LPI2C DMA IRQ handler */ + s_lpi2cMasterIsr = LPI2C_MasterTransferEdmaHandleIRQ; + + /* Enable interrupt in NVIC. */ + (void)EnableIRQ(kLpi2cIrqs[instance]); + + /* Set DMA channel completion callbacks. */ + EDMA_SetCallback(handle->rx, LPI2C_MasterEDMACallback, handle); + if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) != 0) + { + EDMA_SetCallback(handle->tx, LPI2C_MasterEDMACallback, handle); + } +} + +static uint32_t LPI2C_GenerateCommands(lpi2c_master_edma_handle_t *handle) +{ + lpi2c_master_transfer_t *xfer = &handle->transfer; + uint16_t *cmd = (uint16_t *)&handle->commandBuffer; + uint32_t cmdCount = 0; + + /* Handle no start option. */ + if ((xfer->flags & (uint32_t)kLPI2C_TransferNoStartFlag) != 0U) + { + if (xfer->direction == kLPI2C_Read) + { + /* Need to issue read command first. */ + cmd[cmdCount++] = (uint16_t)kRxDataCmd | (uint16_t)LPI2C_MTDR_DATA(xfer->dataSize - 1U); + } + } + else + { + /* + * Initial direction depends on whether a subaddress was provided, and of course the actual + * data transfer direction. + */ + lpi2c_direction_t direction = (xfer->subaddressSize != 0U) ? kLPI2C_Write : xfer->direction; + + /* Start command. */ + cmd[cmdCount++] = + (uint16_t)kStartCmd | (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)direction); + + /* Subaddress, MSB first. */ + if (xfer->subaddressSize != 0U) + { + uint32_t subaddressRemaining = xfer->subaddressSize; + while (0U != subaddressRemaining--) + { + uint8_t subaddressByte = (uint8_t)(xfer->subaddress >> (8U * subaddressRemaining)) & 0xffU; + cmd[cmdCount++] = subaddressByte; + } + } + + /* Reads need special handling because we have to issue a read command and maybe a repeated start. */ + if ((xfer->dataSize != 0U) && (xfer->direction == kLPI2C_Read)) + { + /* Need to send repeated start if switching directions to read. */ + if (direction == kLPI2C_Write) + { + cmd[cmdCount++] = (uint16_t)kStartCmd | + (uint16_t)((uint16_t)((uint16_t)xfer->slaveAddress << 1U) | (uint16_t)kLPI2C_Read); + } + + /* Read command. A single write to MTDR can issue read operation of 0xFFU + 1 byte of data at most, so when + the dataSize is larger than 0x100U, push multiple read commands to MTDR until dataSize is reached. */ + size_t tmpRxSize = xfer->dataSize; + while (tmpRxSize != 0U) + { + if (tmpRxSize > 256U) + { + cmd[cmdCount++] = (uint16_t)kRxDataCmd | (uint16_t)LPI2C_MTDR_DATA(0xFFU); + tmpRxSize -= 256U; + } + else + { + cmd[cmdCount++] = (uint16_t)kRxDataCmd | (uint16_t)LPI2C_MTDR_DATA(tmpRxSize - 1U); + tmpRxSize = 0U; + } + } + } + } + + return cmdCount; +} + +/*! + * brief Performs a non-blocking DMA-based transaction on the I2C bus. + * + * The callback specified when the a handle was created is invoked when the transaction has + * completed. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * param transfer The pointer to the transfer descriptor. + * retval #kStatus_Success The transaction was started successfully. + * retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or another DMA + * transaction is already in progress. + */ +status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + lpi2c_master_transfer_t *transfer) +{ + status_t result; + + assert(handle != NULL); + assert(transfer != NULL); + assert(transfer->subaddressSize <= sizeof(transfer->subaddress)); + + /* Check transfer data size in read operation. */ + /* A single write to MTDR can issue read operation of 0xFFU + 1 byte of data at most, so when the dataSize is larger + than 0x100U, push multiple read commands to MTDR until dataSize is reached. LPI2C edma transfer uses linked + descriptor to transfer command and data, the command buffer is stored in handle. Allocate 4 command words to + carry read command which can cover nearly all use cases. */ + if ((transfer->direction == kLPI2C_Read) && (transfer->dataSize > (256U * 4U))) + { + return kStatus_InvalidArgument; + } + + /* Return busy if another transaction is in progress. */ + if (handle->isBusy) + { + return kStatus_LPI2C_Busy; + } + + /* Enable the master function and disable the slave function. */ + LPI2C_MasterEnable(base, true); + LPI2C_SlaveEnable(base, false); + + /* Return an error if the bus is already in use not by us. */ + result = LPI2C_CheckForBusyBus(base); + /* + * $Branch Coverage Justification$ + * $ref fsl_lpi2c_edma_c_ref_1$ + */ + if (result != kStatus_Success) + { + return result; + } + + /* We're now busy. */ + handle->isBusy = true; + + /* Disable LPI2C IRQ and DMA sources while we configure stuff. */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); + LPI2C_MasterEnableDMA(base, false, false); + + /* Clear all flags. */ + LPI2C_MasterClearStatusFlags(base, (uint32_t)kLPI2C_MasterClearFlags); + + /* Save transfer into handle. */ + handle->transfer = *transfer; + + /* Generate commands to send. */ + uint32_t commandCount = LPI2C_GenerateCommands(handle); + + /* If the user is transmitting no data with no start or stop, then just go ahead and invoke the callback. */ + if ((0U == commandCount) && (transfer->dataSize == 0U)) + { + if (handle->completionCallback != NULL) + { + handle->completionCallback(base, handle, kStatus_Success, handle->userData); + } + return kStatus_Success; + } + + /* Reset DMA channels. */ + EDMA_ResetChannel(handle->rx->base, handle->rx->channel); + if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) != 0) + { + EDMA_ResetChannel(handle->tx->base, handle->tx->channel); + } + + /* Get a 32-byte aligned TCD pointer. */ + edma_tcd_t *tcd = (edma_tcd_t *)((uint32_t)(&handle->tcds[1]) & (~ALIGN_TCD_SIZE_MASK)); + + bool hasSendData = (transfer->direction == kLPI2C_Write) && (transfer->dataSize != 0U); + bool hasReceiveData = (transfer->direction == kLPI2C_Read) && (transfer->dataSize != 0U); + + edma_transfer_config_t transferConfig = {0}; + edma_tcd_t *linkTcd = NULL; + + /* Set up data transmit. */ + if (hasSendData) + { + uint32_t *srcAddr = (uint32_t *)transfer->data; + transferConfig.srcAddr = (uint32_t)srcAddr; + transferConfig.destAddr = (uint32_t)LPI2C_MasterGetTxFifoAddress(base); + transferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.srcOffset = (int16_t)sizeof(uint8_t); + transferConfig.destOffset = 0; + transferConfig.minorLoopBytes = sizeof(uint8_t); /* TODO optimize to fill fifo */ + transferConfig.majorLoopCounts = transfer->dataSize; + + /* Store the initially configured eDMA minor byte transfer count into the LPI2C handle */ + handle->nbytes = (uint8_t)transferConfig.minorLoopBytes; + + if (commandCount != 0U) + { +#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4 + /* Create a software TCD, which will be chained after the commands. */ + EDMA_TcdResetExt(handle->tx->base, tcd); + EDMA_TcdSetTransferConfigExt(handle->tx->base, tcd, &transferConfig, NULL); + EDMA_TcdEnableInterruptsExt(handle->tx->base, tcd, (uint32_t)kEDMA_MajorInterruptEnable); +#else + /* Create a software TCD, which will be chained after the commands. */ + EDMA_TcdReset(tcd); + EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL); + EDMA_TcdEnableInterrupts(tcd, (uint32_t)kEDMA_MajorInterruptEnable); +#endif + linkTcd = tcd; + } + else + { + /* User is only transmitting data with no required commands, so this transfer can stand alone. */ + EDMA_SetTransferConfig(handle->tx->base, handle->tx->channel, &transferConfig, NULL); + EDMA_EnableChannelInterrupts(handle->tx->base, handle->tx->channel, (uint32_t)kEDMA_MajorInterruptEnable); + } + } + else if (hasReceiveData) + { + uint32_t *srcAddr = (uint32_t *)transfer->data; + /* Set up data receive. */ + transferConfig.srcAddr = (uint32_t)LPI2C_MasterGetRxFifoAddress(base); + transferConfig.destAddr = (uint32_t)srcAddr; + transferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.srcOffset = 0; + transferConfig.destOffset = (int16_t)sizeof(uint8_t); + transferConfig.minorLoopBytes = sizeof(uint8_t); /* TODO optimize to empty fifo */ + transferConfig.majorLoopCounts = transfer->dataSize; + + /* Store the initially configured eDMA minor byte transfer count into the LPI2C handle */ + handle->nbytes = (uint8_t)transferConfig.minorLoopBytes; + + if ((FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) != 0) || (0U == commandCount)) + { + /* We can put this receive transfer on its own DMA channel. */ + EDMA_SetTransferConfig(handle->rx->base, handle->rx->channel, &transferConfig, NULL); + EDMA_EnableChannelInterrupts(handle->rx->base, handle->rx->channel, (uint32_t)kEDMA_MajorInterruptEnable); + } + else + { + /* For shared rx/tx DMA requests, when there are commands, create a software TCD of + enabling rx dma and disabling tx dma, which will be chained onto the commands transfer, + and create another software TCD of transfering data and chain it onto the last TCD. + Notice that in this situation assume tx/rx uses same channel */ +#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4 + EDMA_TcdResetExt(handle->rx->base, tcd); + EDMA_TcdSetTransferConfigExt(handle->rx->base, tcd, &transferConfig, NULL); + EDMA_TcdEnableInterruptsExt(handle->rx->base, tcd, (uint32_t)kEDMA_MajorInterruptEnable); +#else + EDMA_TcdReset(tcd); + EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL); + EDMA_TcdEnableInterrupts(tcd, (uint32_t)kEDMA_MajorInterruptEnable); +#endif + + transferConfig.srcAddr = (uint32_t)&lpi2c_edma_RecSetting; + transferConfig.destAddr = (uint32_t) & (base->MDER); + transferConfig.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfig.srcOffset = 0; + transferConfig.destOffset = (int16_t)sizeof(uint8_t); + transferConfig.minorLoopBytes = sizeof(uint8_t); + transferConfig.majorLoopCounts = 1; + + edma_tcd_t *tcdSetRxClearTxDMA = (edma_tcd_t *)((uint32_t)(&handle->tcds[2]) & (~ALIGN_TCD_SIZE_MASK)); +#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4 + EDMA_TcdResetExt(handle->rx->base, tcdSetRxClearTxDMA); + EDMA_TcdSetTransferConfigExt(handle->rx->base, tcdSetRxClearTxDMA, &transferConfig, tcd); +#else + EDMA_TcdReset(tcdSetRxClearTxDMA); + EDMA_TcdSetTransferConfig(tcdSetRxClearTxDMA, &transferConfig, tcd); +#endif + linkTcd = tcdSetRxClearTxDMA; + } + } + else + { + /* No data to send */ + } + + /* Set up commands transfer. */ + if (commandCount != 0U) + { + transferConfig.srcAddr = (uint32_t)handle->commandBuffer; + transferConfig.destAddr = (uint32_t)LPI2C_MasterGetTxFifoAddress(base); + transferConfig.srcTransferSize = kEDMA_TransferSize2Bytes; + transferConfig.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfig.srcOffset = (int16_t)sizeof(uint16_t); + transferConfig.destOffset = 0; + transferConfig.minorLoopBytes = sizeof(uint16_t); /* TODO optimize to fill fifo */ + transferConfig.majorLoopCounts = commandCount; + + EDMA_SetTransferConfig(handle->tx->base, handle->tx->channel, &transferConfig, linkTcd); + } + + /* Start DMA transfer. */ + /* + * $Branch Coverage Justification$ + * $ref fsl_lpi2c_edma_c_ref_2$ + */ + if (hasReceiveData || (0 == FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base))) + { + EDMA_StartTransfer(handle->rx); + } + /* + * $Branch Coverage Justification$ + * $ref fsl_lpi2c_edma_c_ref_2$ + */ + if ((hasSendData || (commandCount != 0U)) && (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) != 0)) + { + EDMA_StartTransfer(handle->tx); + } + + /* Enable DMA in both directions. This actually kicks of the transfer. */ + LPI2C_MasterEnableDMA(base, true, true); + + /* Enable all LPI2C master interrupts */ + LPI2C_MasterEnableInterrupts(base, + (uint32_t)kLPI2C_MasterArbitrationLostFlag | (uint32_t)kLPI2C_MasterNackDetectFlag | + (uint32_t)kLPI2C_MasterPinLowTimeoutFlag | (uint32_t)kLPI2C_MasterFifoErrFlag); + + return result; +} + +/*! + * brief Returns number of bytes transferred so far. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * param[out] count Number of bytes transferred so far by the non-blocking transaction. + * retval #kStatus_Success + * retval #kStatus_NoTransferInProgress There is not a DMA transaction currently in progress. + */ +status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (!handle->isBusy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + uint32_t remaining = handle->transfer.dataSize; + + /* If the DMA is still on a commands transfer that chains to the actual data transfer, */ + /* we do nothing and return the number of transferred bytes as zero. */ + if (EDMA_GetNextTCDAddress(handle->tx) == 0U) + { + if (handle->transfer.direction == kLPI2C_Write) + { + remaining = + (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->tx->base, handle->tx->channel); + } + else + { + remaining = + (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->rx->base, handle->rx->channel); + } + } + + *count = handle->transfer.dataSize - remaining; + + return kStatus_Success; +} + +/*! + * brief Terminates a non-blocking LPI2C master transmission early. + * + * note It is not safe to call this function from an IRQ handler that has a higher priority than the + * eDMA peripheral's IRQ priority. + * + * param base The LPI2C peripheral base address. + * param handle Pointer to the LPI2C master driver handle. + * retval #kStatus_Success A transaction was successfully aborted. + * retval #kStatus_LPI2C_Idle There is not a DMA transaction currently in progress. + */ +status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle) +{ + /* Catch when there is not an active transfer. */ + if (!handle->isBusy) + { + return kStatus_LPI2C_Idle; + } + + /* Terminate DMA transfers. */ + EDMA_AbortTransfer(handle->rx); + if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) != 0) + { + EDMA_AbortTransfer(handle->tx); + } + + /* Reset fifos. */ + base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; + + /* Disable LPI2C interrupts. */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); + + /* If master is still busy and has not send out stop signal yet. */ + if ((LPI2C_MasterGetStatusFlags(base) & + ((uint32_t)kLPI2C_MasterStopDetectFlag | (uint32_t)kLPI2C_MasterBusyFlag)) == (uint32_t)kLPI2C_MasterBusyFlag) + { + /* Send a stop command to finalize the transfer. */ + base->MTDR = (uint32_t)kStopCmd; + } + + /* Reset handle. */ + handle->isBusy = false; + + return kStatus_Success; +} + +static void LPI2C_MasterEDMACallback(edma_handle_t *dmaHandle, void *userData, bool isTransferDone, uint32_t tcds) +{ + lpi2c_master_edma_handle_t *handle = (lpi2c_master_edma_handle_t *)userData; + + if (NULL == handle) + { + return; + } + + /* Check for errors. */ + status_t result = LPI2C_MasterCheckAndClearError(handle->base, LPI2C_MasterGetStatusFlags(handle->base)); + + /* Done with this transaction. */ + handle->isBusy = false; + + if (0U == (handle->transfer.flags & (uint32_t)kLPI2C_TransferNoStopFlag)) + { + /* Send a stop command to finalize the transfer. */ + handle->base->MTDR = (uint32_t)kStopCmd; + } + + /* Invoke callback. */ + if (handle->completionCallback != NULL) + { + handle->completionCallback(handle->base, handle, result, handle->userData); + } +} + +static void LPI2C_MasterTransferEdmaHandleIRQ(LPI2C_Type *base, void *lpi2cMasterEdmaHandle) +{ + assert(lpi2cMasterEdmaHandle != NULL); + + lpi2c_master_edma_handle_t *handle = (lpi2c_master_edma_handle_t *)lpi2cMasterEdmaHandle; + uint32_t status = LPI2C_MasterGetStatusFlags(base); + status_t result = kStatus_Success; + + /* Terminate DMA transfers. */ + EDMA_AbortTransfer(handle->rx); + if (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) != 0) + { + EDMA_AbortTransfer(handle->tx); + } + + /* Done with this transaction. */ + handle->isBusy = false; + + /* Disable LPI2C interrupts. */ + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); + + /* Check error status */ + if (0U != (status & (uint32_t)kLPI2C_MasterPinLowTimeoutFlag)) + { + result = kStatus_LPI2C_PinLowTimeout; + } + /* + * $Branch Coverage Justification$ + * $ref fsl_lpi2c_edma_c_ref_1$ + */ + else if (0U != (status & (uint32_t)kLPI2C_MasterArbitrationLostFlag)) + { + result = kStatus_LPI2C_ArbitrationLost; + } + else if (0U != (status & (uint32_t)kLPI2C_MasterNackDetectFlag)) + { + result = kStatus_LPI2C_Nak; + } + else if (0U != (status & (uint32_t)kLPI2C_MasterFifoErrFlag)) + { + result = kStatus_LPI2C_FifoError; + } + else + { + ; /* Intentional empty */ + } + + /* Clear error status. */ + (void)LPI2C_MasterCheckAndClearError(base, status); + + /* Send stop flag if needed */ + if (0U == (handle->transfer.flags & (uint32_t)kLPI2C_TransferNoStopFlag)) + { + status = LPI2C_MasterGetStatusFlags(base); + /* If bus is still busy and the master has not generate stop flag */ + if ((status & ((uint32_t)kLPI2C_MasterBusBusyFlag | (uint32_t)kLPI2C_MasterStopDetectFlag)) == + (uint32_t)kLPI2C_MasterBusBusyFlag) + { + /* Send a stop command to finalize the transfer. */ + handle->base->MTDR = (uint32_t)kStopCmd; + } + } + + /* Invoke callback. */ + if (handle->completionCallback != NULL) + { + handle->completionCallback(base, handle, result, handle->userData); + } +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpi2c_edma.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpi2c_edma.h new file mode 100644 index 00000000000..66da36b866d --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpi2c_edma.h @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LPI2C_EDMA_H_ +#define FSL_LPI2C_EDMA_H_ + +#include "fsl_lpi2c.h" +#include "fsl_edma.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @name Driver version + * @{ + */ +/*! @brief LPI2C EDMA driver version. */ +#define FSL_LPI2C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 2)) +/*! @} */ + +/*! + * @addtogroup lpi2c_master_edma_driver + * @{ + */ + +/* Forward declaration of the transfer descriptor and handle typedefs. */ +/*! @brief LPI2C master EDMA handle of the transfer. */ +typedef struct _lpi2c_master_edma_handle lpi2c_master_edma_handle_t; + +/*! + * @brief Master DMA completion callback function pointer type. + * + * This callback is used only for the non-blocking master transfer API. Specify the callback you wish to use + * in the call to LPI2C_MasterCreateEDMAHandle(). + * + * @param base The LPI2C peripheral base address. + * @param handle Handle associated with the completed transfer. + * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed. + * @param userData Arbitrary pointer-sized value passed from the application. + */ +typedef void (*lpi2c_master_edma_transfer_callback_t)(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + status_t completionStatus, + void *userData); + +/*! + * @brief Driver handle for master DMA APIs. + * @note The contents of this structure are private and subject to change. + */ +struct _lpi2c_master_edma_handle +{ + LPI2C_Type *base; /*!< LPI2C base pointer. */ + bool isBusy; /*!< Transfer state machine current state. */ + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + uint16_t commandBuffer[10]; /*!< LPI2C command sequence. When all 10 command words are used: + Start&addr&write[1 word] + subaddr[4 words] + restart&addr&read[1 word] + receive&Size[4 words] */ + lpi2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + lpi2c_master_edma_transfer_callback_t completionCallback; /*!< Callback function pointer. */ + void *userData; /*!< Application data passed to callback. */ + edma_handle_t *rx; /*!< Handle for receive DMA channel. */ + edma_handle_t *tx; /*!< Handle for transmit DMA channel. */ + edma_tcd_t tcds[3]; /*!< Software TCD. Three are allocated to provide enough room to align to 32-bytes. */ +}; + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @addtogroup lpi2c_master_edma_driver + * @{ + */ + +/*! + * @name Master DMA + * @{ + */ + +/*! + * @brief Create a new handle for the LPI2C master DMA APIs. + * + * The creation of a handle is for use with the DMA APIs. Once a handle + * is created, there is not a corresponding destroy handle. If the user wants to + * terminate a transfer, the LPI2C_MasterTransferAbortEDMA() API shall be called. + * + * For devices where the LPI2C send and receive DMA requests are OR'd together, the @a txDmaHandle + * parameter is ignored and may be set to NULL. + * + * @param base The LPI2C peripheral base address. + * @param[out] handle Pointer to the LPI2C master driver handle. + * @param rxDmaHandle Handle for the eDMA receive channel. Created by the user prior to calling this function. + * @param txDmaHandle Handle for the eDMA transmit channel. Created by the user prior to calling this function. + * @param callback User provided pointer to the asynchronous callback function. + * @param userData User provided pointer to the application callback data. + */ +void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + edma_handle_t *rxDmaHandle, + edma_handle_t *txDmaHandle, + lpi2c_master_edma_transfer_callback_t callback, + void *userData); + +/*! + * @brief Performs a non-blocking DMA-based transaction on the I2C bus. + * + * The callback specified when the @a handle was created is invoked when the transaction has + * completed. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param transfer The pointer to the transfer descriptor. + * @retval kStatus_Success The transaction was started successfully. + * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or another DMA + * transaction is already in progress. + */ +status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base, + lpi2c_master_edma_handle_t *handle, + lpi2c_master_transfer_t *transfer); + +/*! + * @brief Returns number of bytes transferred so far. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @param[out] count Number of bytes transferred so far by the non-blocking transaction. + * @retval kStatus_Success + * @retval kStatus_NoTransferInProgress There is not a DMA transaction currently in progress. + */ +status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle, size_t *count); + +/*! + * @brief Terminates a non-blocking LPI2C master transmission early. + * + * @note It is not safe to call this function from an IRQ handler that has a higher priority than the + * eDMA peripheral's IRQ priority. + * + * @param base The LPI2C peripheral base address. + * @param handle Pointer to the LPI2C master driver handle. + * @retval kStatus_Success A transaction was successfully aborted. + * @retval #kStatus_LPI2C_Idle There is not a DMA transaction currently in progress. + */ +status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle); + +/*! @} */ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* FSL_LPI2C_EDMA_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpspi.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpspi.c new file mode 100644 index 00000000000..edf955ea255 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpspi.c @@ -0,0 +1,2604 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022, 2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpspi.h" +/* + * $Coverage Justification Reference$ + * + * $Justification fsl_lpspi_c_ref_1$ + * The default branch cannot be executed in any circumstances, it is only added to avoid MISRA violation. + * + * $Justification fsl_lpspi_c_ref_2$ + * The FIFO was emptied before the check and there was no writing after the FIFO was emptied, so the obtained FIFO count + * is 0, and the #kStatus_LPSPI_Timeout cannot be obtained.(will improve) + * + * $Justification fsl_lpspi_c_ref_3$ + * The fifosize is determined by the hardware. + * + * $Justification fsl_lpspi_c_ref_4$ + * If an interrupt is generated by this error, the corresponding interrupt bit must be set.(will improve) + * + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpspi" +#endif + +#if defined(LPSPI_RSTS) +#define LPSPI_RESETS_ARRAY LPSPI_RSTS +#endif + +/*! + * @brief Default watermark values. + * + * The default watermarks are set to zero. + */ +enum _lpspi_default_watermarks +{ + kLpspiDefaultTxWatermark = 0, + kLpspiDefaultRxWatermark = 0, +}; + +/* + * CR |= LPSPI_CR_RRF_MASK | LPSPI_CR_RTF_MASK; + base->IER = 0U; + base->CR = 0U; + + /* Disable LPSPI first */ + LPSPI_Enable(base, false); + + /* Set LPSPI to master */ + LPSPI_SetMasterSlaveMode(base, kLPSPI_Master); + + /* Set specific PCS to active high or low */ + LPSPI_SetOnePcsPolarity(base, masterConfig->whichPcs, masterConfig->pcsActiveHighOrLow); + + /* Set Configuration Register 1 related setting.*/ + base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK | LPSPI_CFGR1_NOSTALL_MASK | + LPSPI_CFGR1_SAMPLE_MASK)) | + LPSPI_CFGR1_OUTCFG(masterConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(masterConfig->pinCfg) | +#if !(defined(FSL_FEATURE_LPSPI_HAS_NO_PCSCFG) && FSL_FEATURE_LPSPI_HAS_NO_PCSCFG) + LPSPI_CFGR1_PCSCFG(masterConfig->pcsFunc) | +#endif + LPSPI_CFGR1_NOSTALL(0) | LPSPI_CFGR1_SAMPLE((uint32_t)masterConfig->enableInputDelay); + + if ((masterConfig->pinCfg == kLPSPI_SdiInSdiOut) || (masterConfig->pinCfg == kLPSPI_SdoInSdoOut)) + { + base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; + } + /* Set baudrate and delay times*/ + (void)LPSPI_MasterSetBaudRate(base, masterConfig->baudRate, srcClock_Hz, &tcrPrescaleValue); + + /* Set default watermarks */ + LPSPI_SetFifoWatermarks(base, (uint32_t)kLpspiDefaultTxWatermark, (uint32_t)kLpspiDefaultRxWatermark); + + /* Set Transmit Command Register*/ + base->TCR = LPSPI_TCR_CPOL(masterConfig->cpol) | LPSPI_TCR_CPHA(masterConfig->cpha) | + LPSPI_TCR_LSBF(masterConfig->direction) | LPSPI_TCR_FRAMESZ(masterConfig->bitsPerFrame - 1U) | + LPSPI_TCR_PRESCALE(tcrPrescaleValue) | LPSPI_TCR_PCS(masterConfig->whichPcs); + + LPSPI_Enable(base, true); + + (void)LPSPI_MasterSetDelayTimes(base, masterConfig->pcsToSckDelayInNanoSec, kLPSPI_PcsToSck, srcClock_Hz); + (void)LPSPI_MasterSetDelayTimes(base, masterConfig->lastSckToPcsDelayInNanoSec, kLPSPI_LastSckToPcs, srcClock_Hz); + (void)LPSPI_MasterSetDelayTimes(base, masterConfig->betweenTransferDelayInNanoSec, kLPSPI_BetweenTransfer, + srcClock_Hz); + + LPSPI_SetDummyData(base, LPSPI_DUMMY_DATA); +} + +/*! + * brief Sets the lpspi_master_config_t structure to default values. + * + * This API initializes the configuration structure for LPSPI_MasterInit(). + * The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified + * before calling the LPSPI_MasterInit(). + * Example: + * code + * lpspi_master_config_t masterConfig; + * LPSPI_MasterGetDefaultConfig(&masterConfig); + * endcode + * param masterConfig pointer to lpspi_master_config_t structure + */ +void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig) +{ + assert(masterConfig != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(masterConfig, 0, sizeof(*masterConfig)); + + masterConfig->baudRate = 500000; + masterConfig->bitsPerFrame = 8; + masterConfig->cpol = kLPSPI_ClockPolarityActiveHigh; + masterConfig->cpha = kLPSPI_ClockPhaseFirstEdge; + masterConfig->direction = kLPSPI_MsbFirst; +#if !(defined(FSL_FEATURE_LPSPI_HAS_NO_PCSCFG) && FSL_FEATURE_LPSPI_HAS_NO_PCSCFG) + masterConfig->pcsFunc = kLPSPI_PcsAsCs; +#endif + + masterConfig->pcsToSckDelayInNanoSec = (1000000000U / masterConfig->baudRate) / 2U; + masterConfig->lastSckToPcsDelayInNanoSec = (1000000000U / masterConfig->baudRate) / 2U; + masterConfig->betweenTransferDelayInNanoSec = (1000000000U / masterConfig->baudRate) / 2U; + + masterConfig->whichPcs = kLPSPI_Pcs0; + masterConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow; + + masterConfig->pinCfg = kLPSPI_SdiInSdoOut; + masterConfig->dataOutConfig = kLpspiDataOutRetained; + + masterConfig->enableInputDelay = false; +} + +/*! + * brief LPSPI slave configuration. + * + * param base LPSPI peripheral address. + * param slaveConfig Pointer to a structure lpspi_slave_config_t. + */ +void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig) +{ + assert(slaveConfig != NULL); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPSPI_GetInstance(base); + /* Enable LPSPI clock */ + (void)CLOCK_EnableClock(s_lpspiClocks[instance]); + +#if defined(LPSPI_PERIPH_CLOCKS) + (void)CLOCK_EnableClock(s_LpspiPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(LPSPI_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_lpspiResets[LPSPI_GetInstance(base)]); +#endif + + LPSPI_SetMasterSlaveMode(base, kLPSPI_Slave); + + LPSPI_SetOnePcsPolarity(base, slaveConfig->whichPcs, slaveConfig->pcsActiveHighOrLow); + + base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK)) | + LPSPI_CFGR1_OUTCFG(slaveConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(slaveConfig->pinCfg); + + if ((slaveConfig->pinCfg == kLPSPI_SdiInSdiOut) || (slaveConfig->pinCfg == kLPSPI_SdoInSdoOut)) + { + base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; + } + + LPSPI_SetFifoWatermarks(base, (uint32_t)kLpspiDefaultTxWatermark, (uint32_t)kLpspiDefaultRxWatermark); + + base->TCR = LPSPI_TCR_CPOL(slaveConfig->cpol) | LPSPI_TCR_CPHA(slaveConfig->cpha) | + LPSPI_TCR_LSBF(slaveConfig->direction) | LPSPI_TCR_FRAMESZ(slaveConfig->bitsPerFrame - 1U); + + /* This operation will set the dummy data for edma transfer, no effect in interrupt way. */ + LPSPI_SetDummyData(base, LPSPI_DUMMY_DATA); + + LPSPI_Enable(base, true); +} + +/*! + * brief Sets the lpspi_slave_config_t structure to default values. + * + * This API initializes the configuration structure for LPSPI_SlaveInit(). + * The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified + * before calling the LPSPI_SlaveInit(). + * Example: + * code + * lpspi_slave_config_t slaveConfig; + * LPSPI_SlaveGetDefaultConfig(&slaveConfig); + * endcode + * param slaveConfig pointer to lpspi_slave_config_t structure. + */ +void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig) +{ + assert(slaveConfig != NULL); + + /* Initializes the configure structure to zero. */ + (void)memset(slaveConfig, 0, sizeof(*slaveConfig)); + + slaveConfig->bitsPerFrame = 8; /*!< Bits per frame, minimum 8, maximum 4096.*/ + slaveConfig->cpol = kLPSPI_ClockPolarityActiveHigh; /*!< Clock polarity. */ + slaveConfig->cpha = kLPSPI_ClockPhaseFirstEdge; /*!< Clock phase. */ + slaveConfig->direction = kLPSPI_MsbFirst; /*!< MSB or LSB data shift direction. */ + + slaveConfig->whichPcs = kLPSPI_Pcs0; /*!< Desired Peripheral Chip Select (pcs) */ + slaveConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow; /*!< Desired PCS active high or low */ + + slaveConfig->pinCfg = kLPSPI_SdiInSdoOut; + slaveConfig->dataOutConfig = kLpspiDataOutRetained; +} + +/*! + * brief Restores the LPSPI peripheral to reset state. Note that this function + * sets all registers to reset state. As a result, the LPSPI module can't work after calling + * this API. + * param base LPSPI peripheral address. + */ +void LPSPI_Reset(LPSPI_Type *base) +{ + /* Reset all internal logic and registers, except the Control Register. Remains set until cleared by software.*/ + base->CR |= LPSPI_CR_RST_MASK; + + /* Software reset doesn't reset the CR, so manual reset the FIFOs */ + base->CR |= LPSPI_CR_RRF_MASK | LPSPI_CR_RTF_MASK; + + /* Master logic is not reset and module is disabled.*/ + base->CR = 0x00U; +} + +/*! + * brief De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock. + * param base LPSPI peripheral address. + */ +void LPSPI_Deinit(LPSPI_Type *base) +{ + /* Reset to default value */ + LPSPI_Reset(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPSPI_GetInstance(base); + /* Enable LPSPI clock */ + (void)CLOCK_DisableClock(s_lpspiClocks[instance]); + +#if defined(LPSPI_PERIPH_CLOCKS) + (void)CLOCK_DisableClock(s_LpspiPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +static void LPSPI_SetOnePcsPolarity(LPSPI_Type *base, + lpspi_which_pcs_t pcs, + lpspi_pcs_polarity_config_t activeLowOrHigh) +{ + uint32_t cfgr1Value = 0; + /* Clear the PCS polarity bit */ + cfgr1Value = base->CFGR1 & ~(1UL << (LPSPI_CFGR1_PCSPOL_SHIFT + (uint32_t)pcs)); + + /* Configure the PCS polarity bit according to the activeLowOrHigh setting */ + base->CFGR1 = cfgr1Value | ((uint32_t)activeLowOrHigh << (LPSPI_CFGR1_PCSPOL_SHIFT + (uint32_t)pcs)); +} + +/*! + * brief Sets the LPSPI baud rate in bits per second. + * + * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest + * possible baud rate without exceeding the desired baud rate and returns the + * calculated baud rate in bits-per-second. It requires the caller to provide + * the frequency of the module source clock (in Hertz). Note that the baud rate + * does not go into effect until the Transmit Control Register (TCR) is programmed + * with the prescale value. Hence, this function returns the prescale tcrPrescaleValue + * parameter for later programming in the TCR. The higher level + * peripheral driver should alert the user of an out of range baud rate input. + * + * Note that the LPSPI module must first be disabled before configuring this. + * Note that the LPSPI module must be configured for master mode before configuring this. + * + * param base LPSPI peripheral address. + * param baudRate_Bps The desired baud rate in bits per second. + * param srcClock_Hz Module source input clock in Hertz. + * param tcrPrescaleValue The TCR prescale value needed to program the TCR. + * return The actual calculated baud rate. This function may also return a "0" if the + * LPSPI is not configured for master mode or if the LPSPI module is not disabled. + */ + +uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, + uint32_t baudRate_Bps, + uint32_t srcClock_Hz, + uint32_t *tcrPrescaleValue) +{ + assert(tcrPrescaleValue != NULL); + + /* For master mode configuration only, if slave mode detected, return 0. + * Also, the LPSPI module needs to be disabled first, if enabled, return 0 + */ + if ((!LPSPI_IsMaster(base)) || ((base->CR & LPSPI_CR_MEN_MASK) != 0U)) + { + return 0U; + } + + uint32_t prescaler, bestPrescaler; + uint32_t scaler, bestScaler; + uint32_t realBaudrate, bestBaudrate; + uint32_t diff, min_diff; + uint32_t desiredBaudrate = baudRate_Bps; + + /* find combination of prescaler and scaler resulting in baudrate closest to the + * requested value + */ + min_diff = 0xFFFFFFFFU; + + /* Set to maximum divisor value bit settings so that if baud rate passed in is less + * than the minimum possible baud rate, then the SPI will be configured to the lowest + * possible baud rate + */ + bestPrescaler = 7; + bestScaler = 255; + + bestBaudrate = 0; /* required to avoid compilation warning */ + + /* In all for loops, if min_diff = 0, the exit for loop*/ + for (prescaler = 0U; prescaler < 8U; prescaler++) + { + if (min_diff == 0U) + { + break; + } + for (scaler = 0U; scaler < 256U; scaler++) + { + if (min_diff == 0U) + { + break; + } + realBaudrate = (srcClock_Hz / (s_baudratePrescaler[prescaler] * (scaler + 2U))); + + /* calculate the baud rate difference based on the conditional statement + * that states that the calculated baud rate must not exceed the desired baud rate + */ + if (desiredBaudrate >= realBaudrate) + { + diff = desiredBaudrate - realBaudrate; + if (min_diff > diff) + { + /* a better match found */ + min_diff = diff; + bestPrescaler = prescaler; + bestScaler = scaler; + bestBaudrate = realBaudrate; + } + } + } + } + + /* Write the best baud rate scalar to the CCR. + * Note, no need to check for error since we've already checked to make sure the module is + * disabled and in master mode. Also, there is a limit on the maximum divider so we will not + * exceed this. + */ +#if defined(FSL_FEATURE_LPSPI_HAS_CCR1) && FSL_FEATURE_LPSPI_HAS_CCR1 + /* When CCR1 is present, the CCR[DBT] and CCR[SCKDIV] is write only, all read will return 0 + The real DBT and SCKDIV can be obtained in CCR1, CCR[DBT]=CCR1[SCKSCK] and CCR[SCKDIV]=CCR1[SCKHLD]+CCR1[SCKSET] + So when changing either CCR[DBT] or CCR[SCKDIV] make sure the other value is not overwritten by 0 */ + base->CCR = base->CCR | LPSPI_CCR_DBT((base->CCR1 & LPSPI_CCR1_SCKSCK_MASK) >> LPSPI_CCR1_SCKSCK_SHIFT) | + LPSPI_CCR_SCKDIV(bestScaler); +#else + base->CCR = (base->CCR & ~LPSPI_CCR_SCKDIV_MASK) | LPSPI_CCR_SCKDIV(bestScaler); +#endif /* FSL_FEATURE_LPSPI_HAS_CCR1 */ + + /* return the best prescaler value for user to use later */ + *tcrPrescaleValue = bestPrescaler; + + /* return the actual calculated baud rate */ + return bestBaudrate; +} + +/*! + * brief Manually configures a specific LPSPI delay parameter (module must be disabled to + * change the delay values). + * + * This function configures the following: + * SCK to PCS delay, or + * PCS to SCK delay, or + * The configurations must occur between the transfer delay. + * + * The delay names are available in type lpspi_delay_type_t. + * + * The user passes the desired delay along with the delay value. + * This allows the user to directly set the delay values if they have + * pre-calculated them or if they simply wish to manually increment the value. + * + * Note that the LPSPI module must first be disabled before configuring this. + * Note that the LPSPI module must be configured for master mode before configuring this. + * + * param base LPSPI peripheral address. + * param scaler The 8-bit delay value 0x00 to 0xFF (255). + * param whichDelay The desired delay to configure, must be of type lpspi_delay_type_t. + */ +void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay) +{ + /*These settings are only relevant in master mode */ +#if defined(FSL_FEATURE_LPSPI_HAS_CCR1) && FSL_FEATURE_LPSPI_HAS_CCR1 + /* When CCR1 is present, the CCR[DBT] and CCR[SCKDIV] is write only, all read will return 0 + The real DBT and SCKDIV can be obtained in CCR1, CCR[DBT]=CCR1[SCKSCK] and CCR[SCKDIV]=CCR1[SCKHLD]+CCR1[SCKSET] + So when changing either CCR[DBT] or CCR[SCKDIV] make sure the other value is not overwritten by 0 */ + uint32_t dbt = (base->CCR1 & LPSPI_CCR1_SCKSCK_MASK) >> LPSPI_CCR1_SCKSCK_SHIFT; + uint32_t sckdiv = (base->CCR1 & LPSPI_CCR1_SCKHLD_MASK) >> LPSPI_CCR1_SCKHLD_SHIFT; + sckdiv += (base->CCR1 & LPSPI_CCR1_SCKSET_MASK) >> LPSPI_CCR1_SCKSET_SHIFT; + switch (whichDelay) + { + case kLPSPI_PcsToSck: + base->CCR = (base->CCR & (~LPSPI_CCR_PCSSCK_MASK)) | LPSPI_CCR_PCSSCK(scaler) | LPSPI_CCR_DBT(dbt) | + LPSPI_CCR_SCKDIV(sckdiv); + + break; + case kLPSPI_LastSckToPcs: + base->CCR = (base->CCR & (~LPSPI_CCR_SCKPCS_MASK)) | LPSPI_CCR_SCKPCS(scaler) | LPSPI_CCR_DBT(dbt) | + LPSPI_CCR_SCKDIV(sckdiv); + + break; + case kLPSPI_BetweenTransfer: + base->CCR = base->CCR | LPSPI_CCR_DBT(scaler) | LPSPI_CCR_SCKDIV(sckdiv); +#else + switch (whichDelay) + { + case kLPSPI_PcsToSck: + base->CCR = (base->CCR & (~LPSPI_CCR_PCSSCK_MASK)) | LPSPI_CCR_PCSSCK(scaler); + + break; + case kLPSPI_LastSckToPcs: + base->CCR = (base->CCR & (~LPSPI_CCR_SCKPCS_MASK)) | LPSPI_CCR_SCKPCS(scaler); + + break; + case kLPSPI_BetweenTransfer: + base->CCR = (base->CCR & (~LPSPI_CCR_DBT_MASK)) | LPSPI_CCR_DBT(scaler); +#endif /* FSL_FEATURE_LPSPI_HAS_CCR1 */ + break; + default: + assert(false); + break; + } +} + +/*! + * brief Calculates the delay based on the desired delay input in nanoseconds (module must be + * disabled to change the delay values). + * + * This function calculates the values for the following: + * SCK to PCS delay, or + * PCS to SCK delay, or + * The configurations must occur between the transfer delay. + * + * The delay names are available in type lpspi_delay_type_t. + * + * The user passes the desired delay and the desired delay value in + * nano-seconds. The function calculates the value needed for the desired delay parameter + * and returns the actual calculated delay because an exact delay match may not be possible. In this + * case, the closest match is calculated without going below the desired delay value input. + * It is possible to input a very large delay value that exceeds the capability of the part, in + * which case the maximum supported delay is returned. It is up to the higher level + * peripheral driver to alert the user of an out of range delay input. + * + * Note that the LPSPI module must be configured for master mode before configuring this. And note that + * the delayTime = LPSPI_clockSource / (PRESCALE * Delay_scaler). + * + * param base LPSPI peripheral address. + * param delayTimeInNanoSec The desired delay value in nano-seconds. + * param whichDelay The desired delay to configuration, which must be of type lpspi_delay_type_t. + * param srcClock_Hz Module source input clock in Hertz. + * return actual Calculated delay value in nano-seconds. + */ +uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, + uint32_t delayTimeInNanoSec, + lpspi_delay_type_t whichDelay, + uint32_t srcClock_Hz) +{ + uint64_t realDelay, bestDelay; + uint32_t scaler, bestScaler; + uint32_t diff, min_diff; + uint64_t initialDelayNanoSec; + uint32_t clockDividedPrescaler; + + /* For delay between transfer, an additional scaler value is needed */ + uint32_t additionalScaler = 0; + + /*As the RM note, the LPSPI baud rate clock is itself divided by the PRESCALE setting, which can vary between + * transfers.*/ + clockDividedPrescaler = + srcClock_Hz / s_baudratePrescaler[(base->TCR & LPSPI_TCR_PRESCALE_MASK) >> LPSPI_TCR_PRESCALE_SHIFT]; + + /* Find combination of prescaler and scaler resulting in the delay closest to the requested value.*/ + min_diff = 0xFFFFFFFFU; + + /* Initialize scaler to max value to generate the max delay */ + bestScaler = 0xFFU; + + /* Calculate the initial (min) delay and maximum possible delay based on the specific delay as + * the delay divisors are slightly different based on which delay we are configuring. + */ + if (whichDelay == kLPSPI_BetweenTransfer) + { + /* First calculate the initial, default delay, note min delay is 2 clock cycles. Due to large size of + calculated values (uint64_t), we need to break up the calculation into several steps to ensure + accurate calculated results + */ + initialDelayNanoSec = 1000000000U; + initialDelayNanoSec *= 2U; + initialDelayNanoSec /= clockDividedPrescaler; + + /* Calculate the maximum delay */ + bestDelay = 1000000000U; + bestDelay *= 257U; /* based on DBT+2, or 255 + 2 */ + bestDelay /= clockDividedPrescaler; + + additionalScaler = 1U; + } + else + { + /* First calculate the initial, default delay, min delay is 1 clock cycle. Due to large size of calculated + values (uint64_t), we need to break up the calculation into several steps to ensure accurate calculated + results. + */ + initialDelayNanoSec = 1000000000U; + initialDelayNanoSec /= clockDividedPrescaler; + + /* Calculate the maximum delay */ + bestDelay = 1000000000U; + bestDelay *= 256U; /* based on SCKPCS+1 or PCSSCK+1, or 255 + 1 */ + bestDelay /= clockDividedPrescaler; + + additionalScaler = 0U; + } + + /* If the initial, default delay is already greater than the desired delay, then + * set the delay to their initial value (0) and return the delay. In other words, + * there is no way to decrease the delay value further. + */ + if (initialDelayNanoSec >= delayTimeInNanoSec) + { + LPSPI_MasterSetDelayScaler(base, 0, whichDelay); + return (uint32_t)initialDelayNanoSec; + } + + /* If min_diff = 0, the exit for loop */ + for (scaler = 0U; scaler < 256U; scaler++) + { + if (min_diff == 0U) + { + break; + } + /* Calculate the real delay value as we cycle through the scaler values. + Due to large size of calculated values (uint64_t), we need to break up the + calculation into several steps to ensure accurate calculated results + */ + realDelay = 1000000000U; + realDelay *= ((uint64_t)scaler + 1UL + (uint64_t)additionalScaler); + realDelay /= clockDividedPrescaler; + + /* calculate the delay difference based on the conditional statement + * that states that the calculated delay must not be less then the desired delay + */ + if (realDelay >= delayTimeInNanoSec) + { + diff = (uint32_t)(realDelay - (uint64_t)delayTimeInNanoSec); + if (min_diff > diff) + { + /* a better match found */ + min_diff = diff; + bestScaler = scaler; + bestDelay = realDelay; + } + } + } + + /* write the best scaler value for the delay */ + LPSPI_MasterSetDelayScaler(base, bestScaler, whichDelay); + + /* return the actual calculated delay value (in ns) */ + return (uint32_t)bestDelay; +} + +/*Transactional APIs -- Master*/ + +/*! + * brief Initializes the LPSPI master handle. + * + * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + + * param base LPSPI peripheral address. + * param handle LPSPI handle pointer to lpspi_master_handle_t. + * param callback DSPI callback. + * param userData callback function parameter. + */ +void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, + lpspi_master_handle_t *handle, + lpspi_master_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + s_lpspiHandle[LPSPI_GetInstance(base)] = handle; + + /* Set irq handler. */ + s_lpspiMasterIsr = LPSPI_MasterTransferHandleIRQ; + + handle->callback = callback; + handle->userData = userData; +} + +/*! + * brief Check the argument for transfer . + * + * param base LPSPI peripheral address. + * param transfer the transfer struct to be used. + * param isEdma True to check for EDMA transfer, false to check interrupt non-blocking transfer + * return Return true for right and false for wrong. + */ +bool LPSPI_CheckTransferArgument(LPSPI_Type *base, lpspi_transfer_t *transfer, bool isEdma) +{ + assert(transfer != NULL); + uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1U; + uint32_t bytesPerFrame = (bitsPerFrame + 7U) / 8U; + uint32_t temp = (base->CFGR1 & LPSPI_CFGR1_PINCFG_MASK); + /* If the transfer count is zero, then return immediately.*/ + if (transfer->dataSize == 0U) + { + return false; + } + + /* If both send buffer and receive buffer is null */ + if ((NULL == (transfer->txData)) && (NULL == (transfer->rxData))) + { + return false; + } + + /*The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4 . + *For bytesPerFrame greater than 4 situation: + *the transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4 , + *otherwise , the transfer data size can be integer multiples of bytesPerFrame. + */ + if (bytesPerFrame <= 4U) + { + if ((transfer->dataSize % bytesPerFrame) != 0U) + { + return false; + } + } + else + { + if ((bytesPerFrame % 4U) != 0U) + { + if (transfer->dataSize != bytesPerFrame) + { + return false; + } + } + else + { + if ((transfer->dataSize % bytesPerFrame) != 0U) + { + return false; + } + } + } + + /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */ + if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) + { + /* The 3-wire mode can't send and receive data at the same time. */ + if ((transfer->txData != NULL) && (transfer->rxData != NULL)) + { + return false; + } + } + + if (isEdma && ((bytesPerFrame % 4U) == 3U)) + { + return false; + } + + return true; +} + +static bool LPSPI_MasterTransferWriteAllTxData(LPSPI_Type *base, + lpspi_transfer_t *transfer, + lpspi_transfer_blocking_param_t *stateParams) +{ + uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; + uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; + uint32_t txRemainingByteCount = transfer->dataSize; + bool isByteSwap = ((transfer->configFlags & (uint32_t)kLPSPI_MasterByteSwap) != 0U); + uint32_t wordToSend = + ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); + uint32_t rxFifoMaxBytes = MIN(bytesPerFrame, 4U) * LPSPI_GetRxFifoSize(base); + uint32_t readData; + uint8_t fifo_size = LPSPI_GetRxFifoSize(base); + /*Write the TX data until txRemainingByteCount is equal to 0 */ + while (txRemainingByteCount > 0U) + { + if (txRemainingByteCount < (stateParams->bytesEachWrite)) + { + (stateParams->bytesEachWrite) = (uint8_t)txRemainingByteCount; + } + + /*Wait until TX FIFO is not full*/ +#if SPI_RETRY_TIMES + uint32_t waitTimes = SPI_RETRY_TIMES; + while ((LPSPI_GetTxFifoCount(base) == fifo_size) && ((--waitTimes) != 0U)) +#else + while (LPSPI_GetTxFifoCount(base) == fifo_size) +#endif + { + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return false; + } +#endif + + /* To prevent rxfifo overflow, ensure transmitting and receiving are executed in parallel */ + if (((NULL == (stateParams->rxData)) || + ((stateParams->rxRemainingByteCount) - txRemainingByteCount) < rxFifoMaxBytes)) + { + if (stateParams->isTxMask) + { + /* When TCR[TXMSK]=1, transfer is initiate by writting a new command word to TCR. TCR[TXMSK] is cleared + by hardware every time when TCR[FRAMESZ] bit of data is transfered. + In this case TCR[TXMSK] should be set to initiate each transfer. */ + base->TCR |= LPSPI_TCR_TXMSK_MASK; + if (stateParams->isPcsContinuous && (txRemainingByteCount == bytesPerFrame)) + { + /* For the last piece of frame size of data, if is PCS continous mode(TCR[CONT]), TCR[CONTC] should + * be cleared to de-assert the PCS. Be sure to clear the TXMSK as well otherwise another FRAMESZ + * of data will be received. */ + base->TCR &= ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK | LPSPI_TCR_TXMSK_MASK); + } + else + { + if (!LPSPI_WaitTxFifoEmpty(base)) + { + return false; + } + } + txRemainingByteCount -= bytesPerFrame; + } + else + { + if ((stateParams->txData) != NULL) + { + if (stateParams->bytesEachWrite != 1U) + { + wordToSend = + LPSPI_CombineWriteData((stateParams->txData), (stateParams->bytesEachWrite), isByteSwap); + (stateParams->txData) += (stateParams->bytesEachWrite); + } + else + { + wordToSend = *(stateParams->txData); + (stateParams->txData) += 1U; + } + } + /* Otherwise push data to tx FIFO to initiate transfer */ + LPSPI_WriteData(base, wordToSend); + txRemainingByteCount -= (stateParams->bytesEachWrite); + } + } + + /* Check whether there is RX data in RX FIFO . Read out the RX data so that the RX FIFO would not overrun. */ + /* + * $Branch Coverage Justification$ + * Data will be transferred in the inner loop until complete, after which the interrupt will end.(will improve) + */ + if (((stateParams->rxData) != NULL) && ((stateParams->rxRemainingByteCount) != 0U)) + { + /* To ensure parallel execution in 3-wire mode, after writting 1 to TXMSK to generate clock of + bytesPerFrame's data wait until bytesPerFrame's data is received. */ + while ((stateParams->isTxMask) && (LPSPI_GetRxFifoCount(base) == 0U)) + { + } +#if SPI_RETRY_TIMES + uint32_t waitTimes = SPI_RETRY_TIMES; + while ((LPSPI_GetRxFifoCount(base) != 0U) && (--waitTimes != 0U)) +#else + while (LPSPI_GetRxFifoCount(base) != 0U) +#endif + { + readData = LPSPI_ReadData(base); + /* + * $Branch Coverage Justification$ + * rxRemainingByteCount must be an integer multiple of bytesEachRead, otherwise it cannot pass the check + * of #LPSPI_CheckTransferArgument,so it doesn't happen here.(will improve) + */ + if ((stateParams->rxRemainingByteCount) < (stateParams->bytesEachRead)) + { + (stateParams->bytesEachRead) = (uint8_t)(stateParams->rxRemainingByteCount); + } + + LPSPI_SeparateReadData((stateParams->rxData), readData, (stateParams->bytesEachRead), isByteSwap); + (stateParams->rxData) += (stateParams->bytesEachRead); + + (stateParams->rxRemainingByteCount) -= (stateParams->bytesEachRead); + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return false; + } +#endif + } + } + return true; +} + +static bool LPSPI_MasterTransferClearTCR(LPSPI_Type *base, lpspi_transfer_blocking_param_t *stateParams) +{ +#if SPI_RETRY_TIMES + uint32_t waitTimes = SPI_RETRY_TIMES; + while ((LPSPI_GetTxFifoCount(base) == LPSPI_GetRxFifoSize(base)) && (--waitTimes != 0U)) +#else + while (LPSPI_GetTxFifoCount(base) == LPSPI_GetRxFifoSize(base)) +#endif + { + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return false; + } +#endif + base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK)); + + return true; +} + +static bool LPSPI_MasterTransferReadDataInFifo(LPSPI_Type *base, + lpspi_transfer_t *transfer, + lpspi_transfer_blocking_param_t *stateParams) +{ + uint32_t readData; + bool isByteSwap = ((transfer->configFlags & (uint32_t)kLPSPI_MasterByteSwap) != 0U); + while ((stateParams->rxRemainingByteCount) > 0U) + { +#if SPI_RETRY_TIMES + uint32_t waitTimes = SPI_RETRY_TIMES; + while ((LPSPI_GetRxFifoCount(base) != 0U) && (--waitTimes != 0U)) +#else + while (LPSPI_GetRxFifoCount(base) != 0U) +#endif + { + readData = LPSPI_ReadData(base); + + if ((stateParams->rxRemainingByteCount) < (stateParams->bytesEachRead)) + { + (stateParams->bytesEachRead) = (uint8_t)(stateParams->rxRemainingByteCount); + } + + LPSPI_SeparateReadData((stateParams->rxData), readData, (stateParams->bytesEachRead), isByteSwap); + (stateParams->rxData) += (stateParams->bytesEachRead); + + (stateParams->rxRemainingByteCount) -= (stateParams->bytesEachRead); + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return false; + } +#endif + } + + return true; +} + +static bool LPSPI_MasterTransferReadDataInFifoNoBuf(LPSPI_Type *base, lpspi_transfer_blocking_param_t *stateParams) +{ +#if SPI_RETRY_TIMES + uint32_t waitTimes = SPI_RETRY_TIMES; + while (((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_TransferCompleteFlag) == 0U) && (--waitTimes != 0U)) +#else + while ((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_TransferCompleteFlag) == 0U) +#endif + { + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return false; + } +#endif + return true; +} + +/*! + * brief LPSPI master transfer data using a polling method. + * + * This function transfers data using a polling method. This is a blocking function, which does not return until all + * transfers have been completed. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral address. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ +status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer) +{ + assert(transfer != NULL); + + /* Check that LPSPI is not busy.*/ + /* + * $Branch Coverage Justification$ + * MBF state setting and clearing is done by hardware, the state is too fast to be overwritten.(will improve) + */ + if ((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_ModuleBusyFlag) != 0U) + { + return kStatus_LPSPI_Busy; + } + LPSPI_Enable(base, false); + /* Check arguements */ + if (!LPSPI_CheckTransferArgument(base, transfer, false)) + { + return kStatus_InvalidArgument; + } + + LPSPI_FlushFifo(base, true, true); + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_AllStatusFlag); + + /* Variables */ + uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; +#if !(defined(FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH) && FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH) + uint32_t width = (transfer->configFlags & LPSPI_MASTER_WIDTH_MASK) >> LPSPI_MASTER_WIDTH_SHIFT; +#endif + uint32_t temp = (base->CFGR1 & LPSPI_CFGR1_PINCFG_MASK); + lpspi_transfer_blocking_param_t stateParams; + (void)memset(&stateParams, 0, sizeof(stateParams)); + + stateParams.txData = transfer->txData; + stateParams.rxData = transfer->rxData; + stateParams.isTxMask = false; + stateParams.rxRemainingByteCount = transfer->dataSize; + /*The TX and RX FIFO sizes are always the same*/ + uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; + /* No need to configure PCS continous if the transfer byte count is smaller than frame size */ + stateParams.isPcsContinuous = (((transfer->configFlags & (uint32_t)kLPSPI_MasterPcsContinuous) != 0U) && + (bytesPerFrame < transfer->dataSize)); + + /* Mask tx data in half duplex mode */ + if (((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) && + (stateParams.txData == NULL)) + { + stateParams.isTxMask = true; + } + + base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); + LPSPI_Enable(base, true); + + /* Configure transfer control register. */ + base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | + LPSPI_TCR_TXMSK_MASK | LPSPI_TCR_PCS_MASK)) | +#if !(defined(FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH) && FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH) + LPSPI_TCR_WIDTH(width) | +#endif + LPSPI_TCR_PCS(whichPcs); + /*TCR is also shared the FIFO, so wait for TCR written.*/ + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_c_ref_2$ + */ + if (!LPSPI_WaitTxFifoEmpty(base)) + { + return kStatus_LPSPI_Timeout; + } + + /* PCS should be configured separately from the other bits, otherwise it will not take effect. */ + base->TCR |= LPSPI_TCR_CONT(stateParams.isPcsContinuous) | LPSPI_TCR_CONTC(stateParams.isPcsContinuous) | + LPSPI_TCR_RXMSK(NULL == stateParams.rxData); + + /*TCR is also shared the FIFO, so wait for TCR written.*/ + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_c_ref_2$ + */ + if (!LPSPI_WaitTxFifoEmpty(base)) + { + return kStatus_LPSPI_Timeout; + } + + if (bytesPerFrame <= 4U) + { + stateParams.bytesEachWrite = (uint8_t)bytesPerFrame; + stateParams.bytesEachRead = (uint8_t)bytesPerFrame; + } + else + { + stateParams.bytesEachWrite = 4U; + stateParams.bytesEachRead = 4U; + } + + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_c_ref_2$ + */ + if (false == LPSPI_MasterTransferWriteAllTxData(base, transfer, &stateParams)) + { + return kStatus_LPSPI_Timeout; + } + + if (stateParams.isPcsContinuous && !stateParams.isTxMask) + { + /* In PCS continous mode(TCR[CONT]), after write all the data in TX FIFO, TCR[CONTC] and TCR[CONT] should be + cleared to de-assert the PCS. Note that TCR register also use the TX FIFO. Also CONTC should be cleared when + tx is not masked, otherwise written to TCR register with TXMSK bit set will initiate a new transfer. */ + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_c_ref_2$ + */ + if (false == LPSPI_MasterTransferClearTCR(base, &stateParams)) + { + return kStatus_LPSPI_Timeout; + } + } + + /*Read out the RX data in FIFO*/ + if (stateParams.rxData != NULL) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_c_ref_2$ + */ + if (false == LPSPI_MasterTransferReadDataInFifo(base, transfer, &stateParams)) + { + return kStatus_LPSPI_Timeout; + } + } + else + { + /* If no RX buffer, then transfer is not complete until transfer complete flag sets */ + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_c_ref_2$ + */ + if (false == LPSPI_MasterTransferReadDataInFifoNoBuf(base, &stateParams)) + { + return kStatus_LPSPI_Timeout; + } + } + + return kStatus_Success; +} + +/*! + * brief LPSPI master transfer data using an interrupt method. + * + * This function transfers data using an interrupt method. This is a non-blocking function, which returns right away. + * When all data is transferred, the callback function is called. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ +status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer) +{ + assert(handle != NULL); + assert(transfer != NULL); + + /* Check that we're not busy.*/ + if (handle->state == (uint8_t)kLPSPI_Busy) + { + return kStatus_LPSPI_Busy; + } + + LPSPI_Enable(base, false); + /* Check arguements */ + if (!LPSPI_CheckTransferArgument(base, transfer, false)) + { + return kStatus_InvalidArgument; + } + + /* Flush FIFO, clear status, disable all the interrupts. */ + LPSPI_FlushFifo(base, true, true); + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_AllStatusFlag); + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_AllInterruptEnable); + + /* Variables */ + bool isRxMask = false; + handle->isTxMask = false; + uint8_t txWatermark; + uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; + uint32_t tmpTimes; + uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; + uint32_t temp = (base->CFGR1 & LPSPI_CFGR1_PINCFG_MASK); + + /* Assign the original value for members of transfer handle. */ + handle->state = (uint8_t)kLPSPI_Busy; + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->txRemainingByteCount = transfer->dataSize; + handle->rxRemainingByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + handle->writeTcrInIsr = false; + handle->bytesPerFrame = (uint16_t)((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; + /* No need to configure PCS continous if the transfer byte count is smaller than frame size */ + bool isPcsContinuous = (((transfer->configFlags & (uint32_t)kLPSPI_MasterPcsContinuous) != 0U) && + (transfer->dataSize > handle->bytesPerFrame)); + handle->writeRegRemainingTimes = + (transfer->dataSize / (uint32_t)handle->bytesPerFrame) * (((uint32_t)handle->bytesPerFrame + 3U) / 4U); + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + handle->txBuffIfNull = + ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); + /*The TX and RX FIFO sizes are always the same*/ + handle->fifoSize = LPSPI_GetRxFifoSize(base); + handle->isPcsContinuous = isPcsContinuous; + handle->isByteSwap = ((transfer->configFlags & (uint32_t)kLPSPI_MasterByteSwap) != 0U); + /*Calculate the bytes for write/read the TX/RX register each time*/ + if (handle->bytesPerFrame <= 4U) + { + handle->bytesEachWrite = (uint8_t)handle->bytesPerFrame; + handle->bytesEachRead = (uint8_t)handle->bytesPerFrame; + } + else + { + handle->bytesEachWrite = 4U; + handle->bytesEachRead = 4U; + } + + /*Set the RX and TX watermarks to reduce the ISR times.*/ + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_c_ref_3$ + */ + if (handle->fifoSize > 1U) + { + txWatermark = 1U; + handle->rxWatermark = handle->fifoSize - 2U; + } + else + { + txWatermark = 0U; + handle->rxWatermark = 0U; + } + LPSPI_SetFifoWatermarks(base, txWatermark, handle->rxWatermark); + + /* If there is no rxData, mask the receive data so that receive data is not stored in receive FIFO. */ + if (handle->rxData == NULL) + { + isRxMask = true; + handle->rxRemainingByteCount = 0; + } + + /* Mask tx data in half duplex mode since the tx/rx share the same pin, so that the data received from slave is not + * interfered. */ + if (((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) && + (handle->txData == NULL)) + { + handle->isTxMask = true; + } + + /*Transfers will stall when transmit FIFO is empty or receive FIFO is full. */ + base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); + + /* Enable module for following configuration of TCR to take effect. */ + LPSPI_Enable(base, true); + + /* Configure transfer control register. */ + base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | + LPSPI_TCR_TXMSK_MASK | LPSPI_TCR_PCS_MASK)) | + LPSPI_TCR_PCS(whichPcs); + + /*TCR is also shared the FIFO , so wait for TCR written.*/ + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_c_ref_2$ + */ + if (!LPSPI_WaitTxFifoEmpty(base)) + { + return kStatus_LPSPI_Timeout; + } + + /* PCS should be configured separately from the other bits, otherwise it will not take effect. */ + base->TCR |= LPSPI_TCR_CONT(isPcsContinuous) | LPSPI_TCR_CONTC(isPcsContinuous) | LPSPI_TCR_RXMSK(isRxMask); + + /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX , + * and you should also enable the INTMUX interupt in your application. + */ + (void)EnableIRQ(s_lpspiIRQ[LPSPI_GetInstance(base)]); + + /*TCR is also shared the FIFO , so wait for TCR written.*/ + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_c_ref_2$ + */ + if (!LPSPI_WaitTxFifoEmpty(base)) + { + return kStatus_LPSPI_Timeout; + } + + if (handle->isTxMask) + { + /* When TCR[TXMSK]=1, transfer is initiate by writting a new command word to TCR. TCR[TXMSK] is cleared by + hardware every time when TCR[FRAMESZ] bit of data is transfered. In this case TCR[TXMSK] should be set to + initiate each transfer. */ + + base->TCR |= LPSPI_TCR_TXMSK_MASK; + handle->txRemainingByteCount -= (uint32_t)handle->bytesPerFrame; + if (!LPSPI_WaitTxFifoEmpty(base)) + { + return kStatus_LPSPI_Timeout; + } + } + else + { + /* Fill up the TX data in FIFO to initiate transfer */ + LPSPI_MasterTransferFillUpTxFifo(base, handle); + } + + /* Since SPI is a synchronous interface, we only need to enable the RX interrupt if there is RX data. + * The IRQ handler will get the status of RX and TX interrupt flags. + */ + if (handle->rxData != NULL) + { + if (handle->isTxMask) + { + /* if tx data is masked, transfer is initiated by writing 1 to TCR[TXMSK] and TCR[FRMESZ] bits of data is + read. If rx water mark is set larger than TCR[FRMESZ], rx interrupt will not be generated. Lower the rx + water mark setting */ + if ((handle->bytesPerFrame / 4U) < (uint16_t)handle->rxWatermark) + { + handle->rxWatermark = + (uint8_t)(handle->bytesPerFrame / 4U) > 0U ? (uint8_t)(handle->bytesPerFrame / 4U - 1U) : 0U; + base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | LPSPI_FCR_RXWATER(handle->rxWatermark); + } + } + else + { + /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise + *there is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. + */ + tmpTimes = handle->readRegRemainingTimes; + if (tmpTimes <= handle->rxWatermark) + { + base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | LPSPI_FCR_RXWATER(tmpTimes - 1U); + } + } + + LPSPI_EnableInterrupts(base, (uint32_t)kLPSPI_RxInterruptEnable); + } + else + { + LPSPI_EnableInterrupts(base, (uint32_t)kLPSPI_TxInterruptEnable); + } + + return kStatus_Success; +} + +static void LPSPI_MasterTransferFillUpTxFifo(LPSPI_Type *base, lpspi_master_handle_t *handle) +{ + assert(handle != NULL); + + uint32_t wordToSend = 0; + uint8_t fifoSize = handle->fifoSize; + uint32_t writeRegRemainingTimes = handle->writeRegRemainingTimes; + uint32_t readRegRemainingTimes = handle->readRegRemainingTimes; + size_t txRemainingByteCount = handle->txRemainingByteCount; + uint8_t bytesEachWrite = handle->bytesEachWrite; + bool isByteSwap = handle->isByteSwap; + + /* Make sure the difference in remaining TX and RX byte counts does not exceed FIFO depth + * and that the number of TX FIFO entries does not exceed the FIFO depth. + * But no need to make the protection if there is no rxData. + */ + while ((LPSPI_GetTxFifoCount(base) < fifoSize) && + (((readRegRemainingTimes - writeRegRemainingTimes) < (uint32_t)fifoSize) || (handle->rxData == NULL))) + { + if (txRemainingByteCount < (size_t)bytesEachWrite) + { + handle->bytesEachWrite = (uint8_t)txRemainingByteCount; + bytesEachWrite = handle->bytesEachWrite; + } + + if (handle->txData != NULL) + { + wordToSend = LPSPI_CombineWriteData(handle->txData, bytesEachWrite, isByteSwap); + handle->txData += bytesEachWrite; + } + else + { + wordToSend = handle->txBuffIfNull; + } + + /*Write the word to TX register*/ + LPSPI_WriteData(base, wordToSend); + + /*Decrease the write TX register times.*/ + --handle->writeRegRemainingTimes; + writeRegRemainingTimes = handle->writeRegRemainingTimes; + + /*Decrease the remaining TX byte count.*/ + handle->txRemainingByteCount -= (size_t)bytesEachWrite; + txRemainingByteCount = handle->txRemainingByteCount; + + if (handle->txRemainingByteCount == 0U) + { + /* If PCS is continuous, update TCR to de-assert PCS */ + if (handle->isPcsContinuous) + { + /* Only write to the TCR if the FIFO has room */ + if (LPSPI_GetTxFifoCount(base) < fifoSize) + { + base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); + handle->writeTcrInIsr = false; + } + /* Else, set a global flag to tell the ISR to do write to the TCR */ + else + { + handle->writeTcrInIsr = true; + } + } + break; + } + } +} + +static void LPSPI_MasterTransferComplete(LPSPI_Type *base, lpspi_master_handle_t *handle) +{ + assert(handle != NULL); + + /* Disable interrupt requests*/ + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_AllInterruptEnable); + + handle->state = (uint8_t)kLPSPI_Idle; + + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_Success, handle->userData); + } +} + +/*! + * brief Gets the master transfer remaining bytes. + * + * This function gets the master transfer remaining bytes. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the non-blocking transaction. + * return status of status_t. + */ +status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != (uint8_t)kLPSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t remainingByte; + + if (handle->rxData != NULL) + { + remainingByte = handle->rxRemainingByteCount; + } + else + { + remainingByte = handle->txRemainingByteCount; + } + + *count = handle->totalByteCount - remainingByte; + + return kStatus_Success; +} + +/*! + * brief LPSPI master abort transfer which uses an interrupt method. + * + * This function aborts a transfer which uses an interrupt method. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + */ +void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle) +{ + assert(handle != NULL); + + /* Disable interrupt requests*/ + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_AllInterruptEnable); + + LPSPI_Reset(base); + + handle->state = (uint8_t)kLPSPI_Idle; + handle->txRemainingByteCount = 0; + handle->rxRemainingByteCount = 0; +} + +/*! + * brief LPSPI Master IRQ handler function. + * + * This function processes the LPSPI transmit and receive IRQ. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + */ +void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle) +{ + assert(handle != NULL); + + uint32_t readData; + uint8_t bytesEachRead = handle->bytesEachRead; + bool isByteSwap = handle->isByteSwap; + uint32_t readRegRemainingTimes = handle->readRegRemainingTimes; + + if (handle->rxData != NULL) + { + if (handle->rxRemainingByteCount != 0U) + { + /* First, disable the interrupts to avoid potentially triggering another interrupt + * while reading out the RX FIFO as more data may be coming into the RX FIFO. We'll + * re-enable the interrupts based on the LPSPI state after reading out the FIFO. + */ + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_RxInterruptEnable); + + /* + * $Branch Coverage Justification$ + * If the remaining number is 0, the FIFO must be 0, and the condition after will not be judged.(will + * improve) + */ + while ((LPSPI_GetRxFifoCount(base) != 0U) && (handle->rxRemainingByteCount != 0U)) + { + /*Read out the data*/ + readData = LPSPI_ReadData(base); + + /*Decrease the read RX register times.*/ + --handle->readRegRemainingTimes; + readRegRemainingTimes = handle->readRegRemainingTimes; + + if (handle->rxRemainingByteCount < (size_t)bytesEachRead) + { + handle->bytesEachRead = (uint8_t)(handle->rxRemainingByteCount); + bytesEachRead = handle->bytesEachRead; + } + + LPSPI_SeparateReadData(handle->rxData, readData, bytesEachRead, isByteSwap); + handle->rxData += bytesEachRead; + + /*Decrease the remaining RX byte count.*/ + handle->rxRemainingByteCount -= (size_t)bytesEachRead; + } + + /* Re-enable the interrupts only if rxCount indicates there is more data to receive, + * else we may get a spurious interrupt. + * */ + if (handle->rxRemainingByteCount != 0U) + { + /* Set the TDF and RDF interrupt enables simultaneously to avoid race conditions */ + LPSPI_EnableInterrupts(base, (uint32_t)kLPSPI_RxInterruptEnable); + } + } + + /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there + *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. + */ + if (readRegRemainingTimes <= (uint32_t)handle->rxWatermark) + { + base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | + LPSPI_FCR_RXWATER((readRegRemainingTimes > 1U) ? (readRegRemainingTimes - 1U) : (0U)); + } + } + + if (handle->txRemainingByteCount != 0U) + { + if (handle->isTxMask) + { + /* When TCR[TXMSK]=1, transfer is initiate by writting a new command word to TCR. TCR[TXMSK] is cleared by + hardware every time when TCR[FRAMESZ] bit of data is transfered. + In this case TCR[TXMSK] should be set to initiate each transfer. */ + base->TCR |= LPSPI_TCR_TXMSK_MASK; + if ((handle->txRemainingByteCount == (uint32_t)handle->bytesPerFrame) && (handle->isPcsContinuous)) + { + /* For the last piece of frame size of data, if is PCS continous mode(TCR[CONT]), TCR[CONTC] should + * be cleared to de-assert the PCS. Be sure to clear the TXMSK as well otherwise another FRAMESZ + * of data will be received. */ + base->TCR &= ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK | LPSPI_TCR_TXMSK_MASK); + } + else + { + if (!LPSPI_WaitTxFifoEmpty(base)) + { + return; + } + } + handle->txRemainingByteCount -= (uint32_t)handle->bytesPerFrame; + } + else + { + LPSPI_MasterTransferFillUpTxFifo(base, handle); + } + } + else + { + if ((LPSPI_GetTxFifoCount(base) < (handle->fifoSize))) + { + if ((handle->isPcsContinuous) && (handle->writeTcrInIsr) && (!handle->isTxMask)) + { + base->TCR = (base->TCR & ~(LPSPI_TCR_CONTC_MASK)); + handle->writeTcrInIsr = false; + } + } + } + + if ((handle->txRemainingByteCount == 0U) && (handle->rxRemainingByteCount == 0U) && (!handle->writeTcrInIsr)) + { + /* If no RX buffer, then transfer is not complete until transfer complete flag sets */ + if (handle->rxData == NULL) + { + if ((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_TransferCompleteFlag) != 0U) + { + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_TransferCompleteFlag); + /* Complete the transfer and disable the interrupts */ + LPSPI_MasterTransferComplete(base, handle); + } + else + { + LPSPI_EnableInterrupts(base, (uint32_t)kLPSPI_TransferCompleteInterruptEnable); + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_TxInterruptEnable | (uint32_t)kLPSPI_RxInterruptEnable); + } + } + else + { + /* Complete the transfer and disable the interrupts */ + LPSPI_MasterTransferComplete(base, handle); + } + } +} + +/*Transactional APIs -- Slave*/ +/*! + * brief Initializes the LPSPI slave handle. + * + * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + * + * param base LPSPI peripheral address. + * param handle LPSPI handle pointer to lpspi_slave_handle_t. + * param callback DSPI callback. + * param userData callback function parameter. + */ +void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, + lpspi_slave_handle_t *handle, + lpspi_slave_transfer_callback_t callback, + void *userData) +{ + assert(handle != NULL); + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + s_lpspiHandle[LPSPI_GetInstance(base)] = handle; + + /* Set irq handler. */ + s_lpspiSlaveIsr = LPSPI_SlaveTransferHandleIRQ; + + handle->callback = callback; + handle->userData = userData; +} + +/*! + * brief LPSPI slave transfer data using an interrupt method. + * + * This function transfer data using an interrupt method. This is a non-blocking function, which returns right away. + * When all data is transferred, the callback function is called. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ +status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer) +{ + assert(handle != NULL); + assert(transfer != NULL); + + /* Check that we're not busy.*/ + if (handle->state == (uint8_t)kLPSPI_Busy) + { + return kStatus_LPSPI_Busy; + } + LPSPI_Enable(base, false); + /* Check arguements */ + if (!LPSPI_CheckTransferArgument(base, transfer, false)) + { + return kStatus_InvalidArgument; + } + + /* Flush FIFO, clear status, disable all the inerrupts. */ + LPSPI_FlushFifo(base, true, true); + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_AllStatusFlag); + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_AllInterruptEnable); + + /* Variables */ + bool isRxMask = false; + bool isTxMask = false; + uint8_t txWatermark; + uint32_t readRegRemainingTimes; + uint32_t whichPcs = (transfer->configFlags & LPSPI_SLAVE_PCS_MASK) >> LPSPI_SLAVE_PCS_SHIFT; + uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; + + /* Assign the original value for members of transfer handle. */ + handle->state = (uint8_t)kLPSPI_Busy; + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->txRemainingByteCount = transfer->dataSize; + handle->rxRemainingByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3U) / 4U); + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + /*The TX and RX FIFO sizes are always the same*/ + handle->fifoSize = LPSPI_GetRxFifoSize(base); + handle->isByteSwap = ((transfer->configFlags & (uint32_t)kLPSPI_SlaveByteSwap) != 0U); + /*Calculate the bytes for write/read the TX/RX register each time*/ + if (bytesPerFrame <= 4U) + { + handle->bytesEachWrite = (uint8_t)bytesPerFrame; + handle->bytesEachRead = (uint8_t)bytesPerFrame; + } + else + { + handle->bytesEachWrite = 4U; + handle->bytesEachRead = 4U; + } + /* Set proper RX and TX watermarks to reduce the ISR response times. */ + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_c_ref_3$ + */ + if (handle->fifoSize > 1U) + { + txWatermark = 1U; + handle->rxWatermark = handle->fifoSize / 2U; + } + else + { + txWatermark = 0U; + handle->rxWatermark = 0U; + } + LPSPI_SetFifoWatermarks(base, txWatermark, handle->rxWatermark); + + /* If there is no rxData, mask the receive data so that receive data is not stored in receive FIFO. */ + if (handle->rxData == NULL) + { + isRxMask = true; + handle->rxRemainingByteCount = 0U; + } + /* If there is no txData, mask the transmit data so that no data is loaded from transmit FIFO and output pin + * is tristated. */ + if (handle->txData == NULL) + { + isTxMask = true; + handle->txRemainingByteCount = 0U; + } + + /* Enable module for following configuration of TCR to take effect. */ + LPSPI_Enable(base, true); + + base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK | + LPSPI_TCR_TXMSK_MASK | LPSPI_TCR_PCS_MASK)) | + LPSPI_TCR_RXMSK(isRxMask) | LPSPI_TCR_TXMSK(isTxMask) | LPSPI_TCR_PCS(whichPcs); + + /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX , + * and you should also enable the INTMUX interupt in your application. + */ + (void)EnableIRQ(s_lpspiIRQ[LPSPI_GetInstance(base)]); + + /*TCR is also shared the FIFO, so wait for TCR written.*/ + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_c_ref_3$ + */ + if (!LPSPI_WaitTxFifoEmpty(base)) + { + return kStatus_LPSPI_Timeout; + } + + /* Fill up the TX data in FIFO */ + if (handle->txData != NULL) + { + LPSPI_SlaveTransferFillUpTxFifo(base, handle); + } + + /* Since SPI is a synchronous interface, we only need to enable the RX interrupt if there is RX data. + * The IRQ handler will get the status of RX and TX interrupt flags. + */ + if (handle->rxData != NULL) + { + /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there + *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. + */ + readRegRemainingTimes = handle->readRegRemainingTimes; + if (readRegRemainingTimes <= (uint32_t)handle->rxWatermark) + { + base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | LPSPI_FCR_RXWATER(readRegRemainingTimes - 1U); + } + + /* RX request and FIFO overflow request enable */ + LPSPI_EnableInterrupts(base, (uint32_t)kLPSPI_RxInterruptEnable | (uint32_t)kLPSPI_ReceiveErrorInterruptEnable); + } + else + { + LPSPI_EnableInterrupts(base, (uint32_t)kLPSPI_TxInterruptEnable); + } + + if (handle->txData != NULL) + { + /* TX FIFO underflow request enable */ + LPSPI_EnableInterrupts(base, (uint32_t)kLPSPI_TransmitErrorInterruptEnable); + } + + return kStatus_Success; +} + +static void LPSPI_SlaveTransferFillUpTxFifo(LPSPI_Type *base, lpspi_slave_handle_t *handle) +{ + assert(handle != NULL); + + uint32_t wordToSend = 0U; + uint8_t bytesEachWrite = handle->bytesEachWrite; + bool isByteSwap = handle->isByteSwap; + + while (LPSPI_GetTxFifoCount(base) < (handle->fifoSize)) + { + if (handle->txRemainingByteCount < (size_t)bytesEachWrite) + { + handle->bytesEachWrite = (uint8_t)handle->txRemainingByteCount; + bytesEachWrite = handle->bytesEachWrite; + } + + wordToSend = LPSPI_CombineWriteData(handle->txData, bytesEachWrite, isByteSwap); + handle->txData += bytesEachWrite; + + /*Decrease the remaining TX byte count.*/ + handle->txRemainingByteCount -= (size_t)bytesEachWrite; + + /*Write the word to TX register*/ + LPSPI_WriteData(base, wordToSend); + + if (handle->txRemainingByteCount == 0U) + { + break; + } + } +} + +static void LPSPI_SlaveTransferComplete(LPSPI_Type *base, lpspi_slave_handle_t *handle) +{ + assert(handle != NULL); + + status_t status = kStatus_Success; + + /* Disable interrupt requests*/ + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_AllInterruptEnable); + + if (handle->state == (uint8_t)kLPSPI_Error) + { + status = kStatus_LPSPI_Error; + } + else + { + status = kStatus_Success; + } + + handle->state = (uint8_t)kLPSPI_Idle; + + if (handle->callback != NULL) + { + handle->callback(base, handle, status, handle->userData); + } +} + +/*! + * brief Gets the slave transfer remaining bytes. + * + * This function gets the slave transfer remaining bytes. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the non-blocking transaction. + * return status of status_t. + */ +status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != (uint8_t)kLPSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t remainingByte; + + if (handle->rxData != NULL) + { + remainingByte = handle->rxRemainingByteCount; + } + else + { + remainingByte = handle->txRemainingByteCount; + } + + *count = handle->totalByteCount - remainingByte; + + return kStatus_Success; +} + +/*! + * brief LPSPI slave aborts a transfer which uses an interrupt method. + * + * This function aborts a transfer which uses an interrupt method. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + */ +void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle) +{ + assert(handle != NULL); + + /* Disable interrupt requests*/ + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_TxInterruptEnable | (uint32_t)kLPSPI_RxInterruptEnable); + + LPSPI_Reset(base); + + handle->state = (uint8_t)kLPSPI_Idle; + handle->txRemainingByteCount = 0U; + handle->rxRemainingByteCount = 0U; +} + +/*! + * brief LPSPI Slave IRQ handler function. + * + * This function processes the LPSPI transmit and receives an IRQ. + * + * param base LPSPI peripheral address. + * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + */ +void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle) +{ + assert(handle != NULL); + + uint32_t readData; /* variable to store word read from RX FIFO */ + uint8_t bytesEachRead = handle->bytesEachRead; + bool isByteSwap = handle->isByteSwap; + uint32_t readRegRemainingTimes; + + if (handle->rxData != NULL) + { + if (handle->rxRemainingByteCount > 0U) + { + while (LPSPI_GetRxFifoCount(base) != 0U) + { + /*Read out the data*/ + readData = LPSPI_ReadData(base); + + /*Decrease the read RX register times.*/ + --handle->readRegRemainingTimes; + + if (handle->rxRemainingByteCount < (size_t)bytesEachRead) + { + handle->bytesEachRead = (uint8_t)handle->rxRemainingByteCount; + bytesEachRead = handle->bytesEachRead; + } + + LPSPI_SeparateReadData(handle->rxData, readData, bytesEachRead, isByteSwap); + handle->rxData += bytesEachRead; + + /*Decrease the remaining RX byte count.*/ + handle->rxRemainingByteCount -= (size_t)bytesEachRead; + + if ((handle->txRemainingByteCount > 0U) && (handle->txData != NULL)) + { + LPSPI_SlaveTransferFillUpTxFifo(base, handle); + } + + if (handle->rxRemainingByteCount == 0U) + { + break; + } + } + } + + /*Set rxWatermark to (readRegRemainingTimes-1) if readRegRemainingTimes less than rxWatermark. Otherwise there + *is not RX interrupt for the last datas because the RX count is not greater than rxWatermark. + */ + readRegRemainingTimes = handle->readRegRemainingTimes; + if (readRegRemainingTimes <= (uint32_t)handle->rxWatermark) + { + base->FCR = (base->FCR & (~LPSPI_FCR_RXWATER_MASK)) | + LPSPI_FCR_RXWATER((readRegRemainingTimes > 1U) ? (readRegRemainingTimes - 1U) : (0U)); + } + } + if ((handle->rxData == NULL) && (handle->txRemainingByteCount != 0U) && (handle->txData != NULL)) + { + LPSPI_SlaveTransferFillUpTxFifo(base, handle); + } + + if ((handle->txRemainingByteCount == 0U) && (handle->rxRemainingByteCount == 0U)) + { + /* If no RX buffer, then transfer is not complete until transfer complete flag sets and the TX FIFO empty*/ + if (handle->rxData == NULL) + { + if (((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_FrameCompleteFlag) != 0U) && + (LPSPI_GetTxFifoCount(base) == 0U)) + { + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_FrameCompleteFlag); + /* Complete the transfer and disable the interrupts */ + LPSPI_SlaveTransferComplete(base, handle); + } + else + { + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_FrameCompleteFlag); + LPSPI_EnableInterrupts(base, (uint32_t)kLPSPI_FrameCompleteInterruptEnable); + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_TxInterruptEnable | (uint32_t)kLPSPI_RxInterruptEnable); + } + } + else + { + /* Complete the transfer and disable the interrupts */ + LPSPI_SlaveTransferComplete(base, handle); + } + } + + /* Catch tx fifo underflow conditions, service only if tx under flow interrupt enabled */ + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_c_ref_4$ + */ + if (((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_TransmitErrorFlag) != 0U) && + ((base->IER & LPSPI_IER_TEIE_MASK) != 0U)) + { + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_TransmitErrorFlag); + /* Change state to error and clear flag */ + if (handle->txData != NULL) + { + handle->state = (uint8_t)kLPSPI_Error; + } + handle->errorCount++; + /* ERR051588: Clear FIFO after underrun occurs */ + LPSPI_FlushFifo(base, true, false); + } + /* Catch rx fifo overflow conditions, service only if rx over flow interrupt enabled */ + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_c_ref_4$ + */ + if (((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_ReceiveErrorFlag) != 0U) && + ((base->IER & LPSPI_IER_REIE_MASK) != 0U)) + { + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_ReceiveErrorFlag); + /* Change state to error and clear flag */ + /* + * $Branch Coverage Justification$ + * This error happens on receive, so rxData won't be empty.(will improve) + */ + if (handle->rxData != NULL) + { + handle->state = (uint8_t)kLPSPI_Error; + } + handle->errorCount++; + } +} + +static uint32_t LPSPI_CombineWriteData(const uint8_t *txData, uint8_t bytesEachWrite, bool isByteSwap) +{ + assert(txData != NULL); + + uint32_t wordToSend = 0U; + + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_c_ref_1$ + */ + switch (bytesEachWrite) + { + case 1: + wordToSend = *txData; + ++txData; + break; + + case 2: + if (!isByteSwap) + { + wordToSend = *txData; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + } + else + { + wordToSend = (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= *txData; + ++txData; + } + + break; + + case 3: + if (!isByteSwap) + { + wordToSend = *txData; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= (unsigned)(*txData) << 16U; + ++txData; + } + else + { + wordToSend = (unsigned)(*txData) << 16U; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= *txData; + ++txData; + } + break; + + case 4: + if (!isByteSwap) + { + wordToSend = *txData; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= (unsigned)(*txData) << 16U; + ++txData; + wordToSend |= (unsigned)(*txData) << 24U; + ++txData; + } + else + { + wordToSend = (unsigned)(*txData) << 24U; + ++txData; + wordToSend |= (unsigned)(*txData) << 16U; + ++txData; + wordToSend |= (unsigned)(*txData) << 8U; + ++txData; + wordToSend |= *txData; + ++txData; + } + break; + + default: + assert(false); + break; + } + return wordToSend; +} + +static void LPSPI_SeparateReadData(uint8_t *rxData, uint32_t readData, uint8_t bytesEachRead, bool isByteSwap) +{ + assert(rxData != NULL); + + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_c_ref_1$ + */ + switch (bytesEachRead) + { + case 1: + *rxData = (uint8_t)readData; + ++rxData; + break; + + case 2: + if (!isByteSwap) + { + *rxData = (uint8_t)readData; + ++rxData; + *rxData = (uint8_t)(readData >> 8); + ++rxData; + } + else + { + *rxData = (uint8_t)(readData >> 8); + ++rxData; + *rxData = (uint8_t)readData; + ++rxData; + } + break; + + case 3: + if (!isByteSwap) + { + *rxData = (uint8_t)readData; + ++rxData; + *rxData = (uint8_t)(readData >> 8); + ++rxData; + *rxData = (uint8_t)(readData >> 16); + ++rxData; + } + else + { + *rxData = (uint8_t)(readData >> 16); + ++rxData; + *rxData = (uint8_t)(readData >> 8); + ++rxData; + *rxData = (uint8_t)readData; + ++rxData; + } + break; + + case 4: + if (!isByteSwap) + { + *rxData = (uint8_t)readData; + ++rxData; + *rxData = (uint8_t)(readData >> 8); + ++rxData; + *rxData = (uint8_t)(readData >> 16); + ++rxData; + *rxData = (uint8_t)(readData >> 24); + ++rxData; + } + else + { + *rxData = (uint8_t)(readData >> 24); + ++rxData; + *rxData = (uint8_t)(readData >> 16); + ++rxData; + *rxData = (uint8_t)(readData >> 8); + ++rxData; + *rxData = (uint8_t)readData; + ++rxData; + } + break; + + default: + assert(false); + break; + } +} + +/*! + * brief Wait for tx FIFO to be empty. + * Wait the tx fifo empty when set TCR register + * param base LPSPI peripheral address. + * return true for the tx FIFO is ready, false is not. + */ +bool LPSPI_WaitTxFifoEmpty(LPSPI_Type *base) +{ +#if SPI_RETRY_TIMES + uint32_t waitTimes = SPI_RETRY_TIMES; + while (((uint8_t)LPSPI_GetTxFifoCount(base) != 0U) && (--waitTimes != 0U)) +#else + while ((uint8_t)LPSPI_GetTxFifoCount(base) != 0U) +#endif + { + } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return false; + } +#endif + return true; +} + +static void LPSPI_CommonIRQHandler(LPSPI_Type *base, void *param) +{ + if (LPSPI_IsMaster(base)) + { + s_lpspiMasterIsr(base, (lpspi_master_handle_t *)param); + } + else + { + s_lpspiSlaveIsr(base, (lpspi_slave_handle_t *)param); + } + SDK_ISR_EXIT_BARRIER; +} + +#if defined(LPSPI0) +void LPSPI0_DriverIRQHandler(void); +void LPSPI0_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[0] != NULL); + LPSPI_CommonIRQHandler(LPSPI0, s_lpspiHandle[0]); +} +#endif + +#if defined(LPSPI1) +void LPSPI1_DriverIRQHandler(void); +void LPSPI1_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[1] != NULL); + LPSPI_CommonIRQHandler(LPSPI1, s_lpspiHandle[1]); +} +#endif + +#if defined(LPSPI2) +void LPSPI2_DriverIRQHandler(void); +void LPSPI2_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[2] != NULL); + LPSPI_CommonIRQHandler(LPSPI2, s_lpspiHandle[2]); +} +#endif + +#if defined(LPSPI3) +void LPSPI3_DriverIRQHandler(void); +void LPSPI3_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[3] != NULL); + LPSPI_CommonIRQHandler(LPSPI3, s_lpspiHandle[3]); +} +#endif + +#if defined(LPSPI4) +void LPSPI4_DriverIRQHandler(void); +void LPSPI4_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[4] != NULL); + LPSPI_CommonIRQHandler(LPSPI4, s_lpspiHandle[4]); +} +#endif + +#if defined(LPSPI5) +void LPSPI5_DriverIRQHandler(void); +void LPSPI5_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[5] != NULL); + LPSPI_CommonIRQHandler(LPSPI5, s_lpspiHandle[5]); +} +#endif + +#if defined(LPSPI6) +void LPSPI6_DriverIRQHandler(void); +void LPSPI6_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[6] != NULL); + LPSPI_CommonIRQHandler(LPSPI6, s_lpspiHandle[6]); +} +#endif + +#if defined(DMA__LPSPI0) +void DMA_SPI0_INT_DriverIRQHandler(void); +void DMA_SPI0_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI0)] != NULL); + LPSPI_CommonIRQHandler(DMA__LPSPI0, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI0)]); +} +#endif + +#if defined(DMA__LPSPI1) +void DMA_SPI1_INT_DriverIRQHandler(void); +void DMA_SPI1_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI1)] != NULL); + LPSPI_CommonIRQHandler(DMA__LPSPI1, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI1)]); +} +#endif +#if defined(DMA__LPSPI2) +void DMA_SPI2_INT_DriverIRQHandler(void); +void DMA_SPI2_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI2)] != NULL); + LPSPI_CommonIRQHandler(DMA__LPSPI2, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI2)]); +} +#endif + +#if defined(DMA__LPSPI3) +void DMA_SPI3_INT_DriverIRQHandler(void); +void DMA_SPI3_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI3)] != NULL); + LPSPI_CommonIRQHandler(DMA__LPSPI3, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI3)]); +} +#endif + +#if defined(ADMA__LPSPI0) +void ADMA_SPI0_INT_DriverIRQHandler(void); +void ADMA_SPI0_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI0)] != NULL); + LPSPI_CommonIRQHandler(ADMA__LPSPI0, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI0)]); +} +#endif + +#if defined(ADMA__LPSPI1) +void ADMA_SPI1_INT_DriverIRQHandler(void); +void ADMA_SPI1_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI1)] != NULL); + LPSPI_CommonIRQHandler(ADMA__LPSPI1, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI1)]); +} +#endif +#if defined(ADMA__LPSPI2) +void ADMA_SPI2_INT_DriverIRQHandler(void); +void ADMA_SPI2_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI2)] != NULL); + LPSPI_CommonIRQHandler(ADMA__LPSPI2, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI2)]); +} +#endif + +#if defined(ADMA__LPSPI3) +void ADMA_SPI3_INT_DriverIRQHandler(void); +void ADMA_SPI3_INT_DriverIRQHandler(void) +{ + assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI3)] != NULL); + LPSPI_CommonIRQHandler(ADMA__LPSPI3, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI3)]); +} +#endif diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpspi.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpspi.h new file mode 100644 index 00000000000..517179054aa --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpspi.h @@ -0,0 +1,1231 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2023, 2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LPSPI_H_ +#define FSL_LPSPI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpspi_driver + * @{ + */ + +/********************************************************************************************************************** + * Definitions + *********************************************************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief LPSPI driver version. */ +#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 6, 8)) +/*! @} */ + +#ifndef LPSPI_DUMMY_DATA +/*! @brief LPSPI dummy data if no Tx data.*/ +#define LPSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for tx if there is not txData. */ +#endif + +/*! @brief Retry times for waiting flag. */ +#ifndef SPI_RETRY_TIMES +#define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif + +/*! @brief Global variable for dummy data value setting. */ +extern volatile uint8_t g_lpspiDummyData[]; + +/*! @brief Status for the LPSPI driver.*/ +enum +{ + kStatus_LPSPI_Busy = MAKE_STATUS(kStatusGroup_LPSPI, 0), /*!< LPSPI transfer is busy.*/ + kStatus_LPSPI_Error = MAKE_STATUS(kStatusGroup_LPSPI, 1), /*!< LPSPI driver error. */ + kStatus_LPSPI_Idle = MAKE_STATUS(kStatusGroup_LPSPI, 2), /*!< LPSPI is idle.*/ + kStatus_LPSPI_OutOfRange = MAKE_STATUS(kStatusGroup_LPSPI, 3), /*!< LPSPI transfer out Of range. */ + kStatus_LPSPI_Timeout = MAKE_STATUS(kStatusGroup_LPSPI, 4) /*!< LPSPI timeout polling status flags. */ +}; + +/*! @brief LPSPI status flags in SPIx_SR register.*/ +enum _lpspi_flags +{ + kLPSPI_TxDataRequestFlag = LPSPI_SR_TDF_MASK, /*!< Transmit data flag */ + kLPSPI_RxDataReadyFlag = LPSPI_SR_RDF_MASK, /*!< Receive data flag */ + kLPSPI_WordCompleteFlag = LPSPI_SR_WCF_MASK, /*!< Word Complete flag */ + kLPSPI_FrameCompleteFlag = LPSPI_SR_FCF_MASK, /*!< Frame Complete flag */ + kLPSPI_TransferCompleteFlag = LPSPI_SR_TCF_MASK, /*!< Transfer Complete flag */ + kLPSPI_TransmitErrorFlag = LPSPI_SR_TEF_MASK, /*!< Transmit Error flag (FIFO underrun) */ + kLPSPI_ReceiveErrorFlag = LPSPI_SR_REF_MASK, /*!< Receive Error flag (FIFO overrun) */ + kLPSPI_DataMatchFlag = LPSPI_SR_DMF_MASK, /*!< Data Match flag */ + kLPSPI_ModuleBusyFlag = LPSPI_SR_MBF_MASK, /*!< Module Busy flag */ + kLPSPI_AllStatusFlag = (LPSPI_SR_TDF_MASK | LPSPI_SR_RDF_MASK | LPSPI_SR_WCF_MASK | LPSPI_SR_FCF_MASK | + LPSPI_SR_TCF_MASK | LPSPI_SR_TEF_MASK | LPSPI_SR_REF_MASK | LPSPI_SR_DMF_MASK | + LPSPI_SR_MBF_MASK) /*!< Used for clearing all w1c status flags */ +}; + +/*! @brief LPSPI interrupt source.*/ +enum _lpspi_interrupt_enable +{ + kLPSPI_TxInterruptEnable = LPSPI_IER_TDIE_MASK, /*!< Transmit data interrupt enable */ + kLPSPI_RxInterruptEnable = LPSPI_IER_RDIE_MASK, /*!< Receive data interrupt enable */ + kLPSPI_WordCompleteInterruptEnable = LPSPI_IER_WCIE_MASK, /*!< Word complete interrupt enable */ + kLPSPI_FrameCompleteInterruptEnable = LPSPI_IER_FCIE_MASK, /*!< Frame complete interrupt enable */ + kLPSPI_TransferCompleteInterruptEnable = LPSPI_IER_TCIE_MASK, /*!< Transfer complete interrupt enable */ + kLPSPI_TransmitErrorInterruptEnable = LPSPI_IER_TEIE_MASK, /*!< Transmit error interrupt enable(FIFO underrun)*/ + kLPSPI_ReceiveErrorInterruptEnable = LPSPI_IER_REIE_MASK, /*!< Receive Error interrupt enable (FIFO overrun) */ + kLPSPI_DataMatchInterruptEnable = LPSPI_IER_DMIE_MASK, /*!< Data Match interrupt enable */ + kLPSPI_AllInterruptEnable = + (LPSPI_IER_TDIE_MASK | LPSPI_IER_RDIE_MASK | LPSPI_IER_WCIE_MASK | LPSPI_IER_FCIE_MASK | LPSPI_IER_TCIE_MASK | + LPSPI_IER_TEIE_MASK | LPSPI_IER_REIE_MASK | LPSPI_IER_DMIE_MASK) /*!< All above interrupts enable.*/ +}; + +/*! @brief LPSPI DMA source.*/ +enum _lpspi_dma_enable +{ + kLPSPI_TxDmaEnable = LPSPI_DER_TDDE_MASK, /*!< Transmit data DMA enable */ + kLPSPI_RxDmaEnable = LPSPI_DER_RDDE_MASK /*!< Receive data DMA enable */ +}; + +/*! @brief LPSPI master or slave mode configuration.*/ +typedef enum _lpspi_master_slave_mode +{ + kLPSPI_Master = 1U, /*!< LPSPI peripheral operates in master mode.*/ + kLPSPI_Slave = 0U /*!< LPSPI peripheral operates in slave mode.*/ +} lpspi_master_slave_mode_t; + +/*! @brief LPSPI Peripheral Chip Select (PCS) configuration (which PCS to configure).*/ +typedef enum _lpspi_which_pcs_config +{ + kLPSPI_Pcs0 = 0U, /*!< PCS[0] */ + kLPSPI_Pcs1 = 1U, /*!< PCS[1] */ + kLPSPI_Pcs2 = 2U, /*!< PCS[2] */ + kLPSPI_Pcs3 = 3U /*!< PCS[3] */ +} lpspi_which_pcs_t; + +/*! @brief LPSPI Peripheral Chip Select (PCS) Polarity configuration.*/ +typedef enum _lpspi_pcs_polarity_config +{ + kLPSPI_PcsActiveHigh = 1U, /*!< PCS Active High (idles low) */ + kLPSPI_PcsActiveLow = 0U /*!< PCS Active Low (idles high) */ +} lpspi_pcs_polarity_config_t; + +/*! @brief LPSPI Peripheral Chip Select (PCS) Polarity.*/ +enum _lpspi_pcs_polarity +{ + kLPSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */ + kLPSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */ + kLPSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */ + kLPSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */ + kLPSPI_PcsAllActiveLow = 0xFU /*!< Pcs0 to Pcs5 Active Low (idles high). */ +}; + +/*! @brief LPSPI clock polarity configuration.*/ +typedef enum _lpspi_clock_polarity +{ + kLPSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high LPSPI clock (idles low)*/ + kLPSPI_ClockPolarityActiveLow = 1U /*!< CPOL=1. Active-low LPSPI clock (idles high)*/ +} lpspi_clock_polarity_t; + +/*! @brief LPSPI clock phase configuration.*/ +typedef enum _lpspi_clock_phase +{ + kLPSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the + following edge.*/ + kLPSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the + following edge.*/ +} lpspi_clock_phase_t; + +/*! @brief LPSPI data shifter direction options.*/ +typedef enum _lpspi_shift_direction +{ + kLPSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/ + kLPSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit.*/ +} lpspi_shift_direction_t; + +/*! @brief LPSPI Host Request select configuration. */ +typedef enum _lpspi_host_request_select +{ + kLPSPI_HostReqExtPin = 0U, /*!< Host Request is an ext pin. */ + kLPSPI_HostReqInternalTrigger = 1U /*!< Host Request is an internal trigger. */ +} lpspi_host_request_select_t; + +/*! @brief LPSPI Match configuration options. */ +typedef enum _lpspi_match_config +{ + kLPSI_MatchDisabled = 0x0U, /*!< LPSPI Match Disabled. */ + kLPSI_1stWordEqualsM0orM1 = 0x2U, /*!< LPSPI Match Enabled. */ + kLPSI_AnyWordEqualsM0orM1 = 0x3U, /*!< LPSPI Match Enabled. */ + kLPSI_1stWordEqualsM0and2ndWordEqualsM1 = 0x4U, /*!< LPSPI Match Enabled. */ + kLPSI_AnyWordEqualsM0andNxtWordEqualsM1 = 0x5U, /*!< LPSPI Match Enabled. */ + kLPSI_1stWordAndM1EqualsM0andM1 = 0x6U, /*!< LPSPI Match Enabled. */ + kLPSI_AnyWordAndM1EqualsM0andM1 = 0x7U, /*!< LPSPI Match Enabled. */ +} lpspi_match_config_t; + +/*! @brief LPSPI pin (SDO and SDI) configuration. */ +typedef enum _lpspi_pin_config +{ + kLPSPI_SdiInSdoOut = 0U, /*!< LPSPI SDI input, SDO output. */ + kLPSPI_SdiInSdiOut = 1U, /*!< LPSPI SDI input, SDI output. */ + kLPSPI_SdoInSdoOut = 2U, /*!< LPSPI SDO input, SDO output. */ + kLPSPI_SdoInSdiOut = 3U /*!< LPSPI SDO input, SDI output. */ +} lpspi_pin_config_t; + +/*! @brief LPSPI data output configuration. */ +typedef enum _lpspi_data_out_config +{ + kLpspiDataOutRetained = 0U, /*!< Data out retains last value when chip select is de-asserted */ + kLpspiDataOutTristate = 1U /*!< Data out is tristated when chip select is de-asserted */ +} lpspi_data_out_config_t; + +#if !(defined(FSL_FEATURE_LPSPI_HAS_NO_PCSCFG) && FSL_FEATURE_LPSPI_HAS_NO_PCSCFG) +/*! @brief LPSPI cs function configuration. */ +typedef enum _lpspi_pcs_function_config +{ + kLPSPI_PcsAsCs = 0U, /*!< PCS pin select as cs function */ + kLPSPI_PcsAsData = 1U, /*!< PCS pin select as date function */ +} lpspi_pcs_function_config_t; +#endif + +/*! @brief LPSPI transfer width configuration. */ +typedef enum _lpspi_transfer_width +{ + kLPSPI_SingleBitXfer = 0U, /*!< 1-bit shift at a time, data out on SDO, in on SDI (normal mode) */ + kLPSPI_TwoBitXfer = 1U, /*!< 2-bits shift out on SDO/SDI and in on SDO/SDI */ + kLPSPI_FourBitXfer = 2U /*!< 4-bits shift out on SDO/SDI/PCS[3:2] and in on SDO/SDI/PCS[3:2] */ +} lpspi_transfer_width_t; + +/*! @brief LPSPI delay type selection.*/ +typedef enum _lpspi_delay_type +{ + kLPSPI_PcsToSck = 1U, /*!< PCS-to-SCK delay. */ + kLPSPI_LastSckToPcs, /*!< Last SCK edge to PCS delay. */ + kLPSPI_BetweenTransfer /*!< Delay between transfers. */ +} lpspi_delay_type_t; + +#define LPSPI_MASTER_PCS_SHIFT (4U) /*!< LPSPI master PCS shift macro , internal used. */ +#define LPSPI_MASTER_PCS_MASK (0xF0U) /*!< LPSPI master PCS shift macro , internal used. */ +#if !(defined(FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH) && FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH) +#define LPSPI_MASTER_WIDTH_SHIFT (16U) /*!< LPSPI master width shift macro, internal used */ +#define LPSPI_MASTER_WIDTH_MASK (0x30000U) /*!< LPSPI master width shift mask, internal used */ +#endif + +/*! @brief Use this enumeration for LPSPI master transfer configFlags. */ +enum _lpspi_transfer_config_flag_for_master +{ + kLPSPI_MasterPcs0 = 0U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS0 signal */ + kLPSPI_MasterPcs1 = 1U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS1 signal */ + kLPSPI_MasterPcs2 = 2U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS2 signal */ + kLPSPI_MasterPcs3 = 3U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS3 signal */ +#if !(defined(FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH) && FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH) + kLPSPI_MasterWidth1 = 0U << LPSPI_MASTER_WIDTH_SHIFT, /*!< LPSPI master transfer 1bit */ + kLPSPI_MasterWidth2 = 1U << LPSPI_MASTER_WIDTH_SHIFT, /*!< LPSPI master transfer 2bit */ + kLPSPI_MasterWidth4 = 2U << LPSPI_MASTER_WIDTH_SHIFT, /*!< LPSPI master transfer 4bit */ +#endif + + kLPSPI_MasterPcsContinuous = 1U << 20, /*!< Is PCS signal continuous */ + + kLPSPI_MasterByteSwap = + 1U << 22 /*!< Is master swap the byte. + * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set + * lpspi_shift_direction_t to MSB). + * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used + * or not, the waveform is 1 2 3 4 5 6 7 8. + * 2. If you set bitPerFrame = 16 : + * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. + * 3. If you set bitPerFrame = 32 : + * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag. + */ +}; + +#define LPSPI_SLAVE_PCS_SHIFT (4U) /*!< LPSPI slave PCS shift macro , internal used. */ +#define LPSPI_SLAVE_PCS_MASK (0xF0U) /*!< LPSPI slave PCS shift macro , internal used. */ + +/*! @brief Use this enumeration for LPSPI slave transfer configFlags. */ +enum _lpspi_transfer_config_flag_for_slave +{ + kLPSPI_SlavePcs0 = 0U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS0 signal */ + kLPSPI_SlavePcs1 = 1U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS1 signal */ + kLPSPI_SlavePcs2 = 2U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS2 signal */ + kLPSPI_SlavePcs3 = 3U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS3 signal */ + + kLPSPI_SlaveByteSwap = + 1U << 22 /*!< Is slave swap the byte. + * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set + * lpspi_shift_direction_t to MSB). + * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used + * or not, the waveform is 1 2 3 4 5 6 7 8. + * 2. If you set bitPerFrame = 16 : + * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. + * 3. If you set bitPerFrame = 32 : + * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag. + * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag. + */ +}; + +/*! @brief LPSPI transfer state, which is used for LPSPI transactional API state machine. */ +enum _lpspi_transfer_state +{ + kLPSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */ + kLPSPI_Busy, /*!< Transfer queue is not finished. */ + kLPSPI_Error /*!< Transfer error. */ +}; + +/*! @brief LPSPI master configuration structure.*/ +typedef struct _lpspi_master_config +{ + uint32_t baudRate; /*!< Baud Rate for LPSPI. */ + uint32_t bitsPerFrame; /*!< Bits per frame, minimum 8, maximum 4096.*/ + lpspi_clock_polarity_t cpol; /*!< Clock polarity. */ + lpspi_clock_phase_t cpha; /*!< Clock phase. */ + lpspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */ + + uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time in nanoseconds, setting to 0 sets the minimum delay. + It sets the boundary value if out of range.*/ + uint32_t lastSckToPcsDelayInNanoSec; /*!< Last SCK to PCS delay time in nanoseconds, setting to 0 sets the minimum + delay. It sets the boundary value if out of range.*/ + uint32_t betweenTransferDelayInNanoSec; /*!< After the SCK delay time with nanoseconds, setting to 0 sets the + minimum delay. It sets the boundary value if out of range.*/ + + lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (PCS). */ + lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */ + + lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data + *during single bit transfers.*/ + +#if !(defined(FSL_FEATURE_LPSPI_HAS_NO_PCSCFG) && FSL_FEATURE_LPSPI_HAS_NO_PCSCFG) + lpspi_pcs_function_config_t pcsFunc; /*!< Configures cs pins function.*/ +#endif + lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated + * between accesses (LPSPI_PCS is negated). */ + bool enableInputDelay; /*!< Enable master to sample the input data on a delayed SCK. This can help improve slave + setup time. Refer to device data sheet for specific time length. */ +} lpspi_master_config_t; + +/*! @brief LPSPI slave configuration structure.*/ +typedef struct _lpspi_slave_config +{ + uint32_t bitsPerFrame; /*!< Bits per frame, minimum 8, maximum 4096.*/ + lpspi_clock_polarity_t cpol; /*!< Clock polarity. */ + lpspi_clock_phase_t cpha; /*!< Clock phase. */ + lpspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */ + + lpspi_which_pcs_t whichPcs; /*!< Desired Peripheral Chip Select (pcs) */ + lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< Desired PCS active high or low */ + + lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data + *during single bit transfers.*/ + + lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated + * between accesses (LPSPI_PCS is negated). */ +} lpspi_slave_config_t; + +/*! + * @brief Forward declaration of the _lpspi_master_handle typedefs. + */ +typedef struct _lpspi_master_handle lpspi_master_handle_t; + +/*! + * @brief Forward declaration of the _lpspi_slave_handle typedefs. + */ +typedef struct _lpspi_slave_handle lpspi_slave_handle_t; + +/*! + * @brief Master completion callback function pointer type. + * + * @param base LPSPI peripheral address. + * @param handle Pointer to the handle for the LPSPI master. + * @param status Success or error code describing whether the transfer is completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*lpspi_master_transfer_callback_t)(LPSPI_Type *base, + lpspi_master_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief Slave completion callback function pointer type. + * + * @param base LPSPI peripheral address. + * @param handle Pointer to the handle for the LPSPI slave. + * @param status Success or error code describing whether the transfer is completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base, + lpspi_slave_handle_t *handle, + status_t status, + void *userData); + +/*! @brief LPSPI master/slave transfer structure.*/ +typedef struct _lpspi_transfer +{ + const uint8_t *txData; /*!< Send buffer. */ + uint8_t *rxData; /*!< Receive buffer. */ + volatile size_t dataSize; /*!< Transfer bytes. */ + + uint32_t configFlags; /*!< Transfer transfer configuration flags. Set from _lpspi_transfer_config_flag_for_master if + the transfer is used for master or _lpspi_transfer_config_flag_for_slave enumeration if the + transfer is used for slave.*/ +} lpspi_transfer_t; + +/*! @brief LPSPI master transfer handle structure used for transactional API. */ +struct _lpspi_master_handle +{ + volatile bool isPcsContinuous; /*!< Is PCS continuous in transfer. */ + volatile bool writeTcrInIsr; /*!< A flag that whether should write TCR in ISR. */ + + volatile bool isByteSwap; /*!< A flag that whether should byte swap. */ + volatile bool isTxMask; /*!< A flag that whether TCR[TXMSK] is set. */ + volatile uint16_t bytesPerFrame; /*!< Number of bytes in each frame */ + + volatile uint8_t fifoSize; /*!< FIFO dataSize. */ + + volatile uint8_t rxWatermark; /*!< Rx watermark. */ + + volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ + volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ + + const uint8_t *volatile txData; /*!< Send buffer. */ + uint8_t *volatile rxData; /*!< Receive buffer. */ + volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ + volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ + + volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */ + volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */ + + uint32_t totalByteCount; /*!< Number of transfer bytes*/ + + uint32_t txBuffIfNull; /*!< Used if the txData is NULL. */ + + volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/ + + lpspi_master_transfer_callback_t callback; /*!< Completion callback. */ + void *userData; /*!< Callback user data. */ +}; + +/*! @brief LPSPI slave transfer handle structure used for transactional API. */ +struct _lpspi_slave_handle +{ + volatile bool isByteSwap; /*!< A flag that whether should byte swap. */ + + volatile uint8_t fifoSize; /*!< FIFO dataSize. */ + + volatile uint8_t rxWatermark; /*!< Rx watermark. */ + + volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ + volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ + + const uint8_t *volatile txData; /*!< Send buffer. */ + uint8_t *volatile rxData; /*!< Receive buffer. */ + + volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ + volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ + + volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */ + volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */ + + uint32_t totalByteCount; /*!< Number of transfer bytes*/ + + volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/ + + volatile uint32_t errorCount; /*!< Error count for slave transfer.*/ + + lpspi_slave_transfer_callback_t callback; /*!< Completion callback. */ + void *userData; /*!< Callback user data. */ +}; + +/********************************************************************************************************************** + * API + *********************************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes the LPSPI master. + * + * @param base LPSPI peripheral address. + * @param masterConfig Pointer to structure lpspi_master_config_t. + * @param srcClock_Hz Module source input clock in Hertz + */ +void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz); + +/*! + * @brief Sets the lpspi_master_config_t structure to default values. + * + * This API initializes the configuration structure for LPSPI_MasterInit(). + * The initialized structure can remain unchanged in LPSPI_MasterInit(), or can be modified + * before calling the LPSPI_MasterInit(). + * Example: + * @code + * lpspi_master_config_t masterConfig; + * LPSPI_MasterGetDefaultConfig(&masterConfig); + * @endcode + * @param masterConfig pointer to lpspi_master_config_t structure + */ +void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig); + +/*! + * @brief LPSPI slave configuration. + * + * @param base LPSPI peripheral address. + * @param slaveConfig Pointer to a structure lpspi_slave_config_t. + */ +void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig); + +/*! + * @brief Sets the lpspi_slave_config_t structure to default values. + * + * This API initializes the configuration structure for LPSPI_SlaveInit(). + * The initialized structure can remain unchanged in LPSPI_SlaveInit() or can be modified + * before calling the LPSPI_SlaveInit(). + * Example: + * @code + * lpspi_slave_config_t slaveConfig; + * LPSPI_SlaveGetDefaultConfig(&slaveConfig); + * @endcode + * @param slaveConfig pointer to lpspi_slave_config_t structure. + */ +void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig); + +/*! + * @brief De-initializes the LPSPI peripheral. Call this API to disable the LPSPI clock. + * @param base LPSPI peripheral address. + */ +void LPSPI_Deinit(LPSPI_Type *base); + +/*! + * @brief Restores the LPSPI peripheral to reset state. Note that this function + * sets all registers to reset state. As a result, the LPSPI module can't work after calling + * this API. + * @param base LPSPI peripheral address. + */ +void LPSPI_Reset(LPSPI_Type *base); + +/*! + * @brief Get the LPSPI instance from peripheral base address. + * + * @param base LPSPI peripheral base address. + * @return LPSPI instance. + */ +uint32_t LPSPI_GetInstance(LPSPI_Type *base); + +/*! + * @brief Enables the LPSPI peripheral and sets the MCR MDIS to 0. + * + * @param base LPSPI peripheral address. + * @param enable Pass true to enable module, false to disable module. + */ +static inline void LPSPI_Enable(LPSPI_Type *base, bool enable) +{ + if (enable) + { + base->CR |= LPSPI_CR_MEN_MASK; + } + else + { + base->CR &= ~LPSPI_CR_MEN_MASK; + } +#if defined(FSL_FEATURE_LPSPI_HAS_ERRATA_051472) && FSL_FEATURE_LPSPI_HAS_ERRATA_051472 + /* ERRATA051472: The SR[REF] would assert if software disables the LPSPI module + after receiving some data and then enabled the LPSPI again without performing a software reset. + Clear SR[REF] flag after LPSPI module enabled*/ + if ((base->SR & (uint32_t)kLPSPI_ReceiveErrorFlag) != 0U) + { + base->SR = (uint32_t)kLPSPI_ReceiveErrorFlag; + } +#endif +} + +/*! + *@} + */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the LPSPI status flag state. + * @param base LPSPI peripheral address. + * @return The LPSPI status(in SR register). + */ +static inline uint32_t LPSPI_GetStatusFlags(LPSPI_Type *base) +{ + return (base->SR); +} + +/*! + * @brief Gets the LPSPI Tx FIFO size. + * @param base LPSPI peripheral address. + * @return The LPSPI Tx FIFO size. + */ +static inline uint8_t LPSPI_GetTxFifoSize(LPSPI_Type *base) +{ + return (1U << ((base->PARAM & LPSPI_PARAM_TXFIFO_MASK) >> LPSPI_PARAM_TXFIFO_SHIFT)); +} + +/*! + * @brief Gets the LPSPI Rx FIFO size. + * @param base LPSPI peripheral address. + * @return The LPSPI Rx FIFO size. + */ +static inline uint8_t LPSPI_GetRxFifoSize(LPSPI_Type *base) +{ + return (1U << ((base->PARAM & LPSPI_PARAM_RXFIFO_MASK) >> LPSPI_PARAM_RXFIFO_SHIFT)); +} + +/*! + * @brief Gets the LPSPI Tx FIFO count. + * @param base LPSPI peripheral address. + * @return The number of words in the transmit FIFO. + */ +static inline uint32_t LPSPI_GetTxFifoCount(LPSPI_Type *base) +{ + return ((base->FSR & LPSPI_FSR_TXCOUNT_MASK) >> LPSPI_FSR_TXCOUNT_SHIFT); +} + +/*! + * @brief Gets the LPSPI Rx FIFO count. + * @param base LPSPI peripheral address. + * @return The number of words in the receive FIFO. + */ +static inline uint32_t LPSPI_GetRxFifoCount(LPSPI_Type *base) +{ + return ((base->FSR & LPSPI_FSR_RXCOUNT_MASK) >> LPSPI_FSR_RXCOUNT_SHIFT); +} + +/*! + * @brief Clears the LPSPI status flag. + * + * This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the + * desired status flag bit to clear. The list of status flags is defined in the _lpspi_flags. + * Example usage: + * @code + * LPSPI_ClearStatusFlags(base, kLPSPI_TxDataRequestFlag|kLPSPI_RxDataReadyFlag); + * @endcode + * + * @param base LPSPI peripheral address. + * @param statusFlags The status flag used from type _lpspi_flags. + */ +static inline void LPSPI_ClearStatusFlags(LPSPI_Type *base, uint32_t statusFlags) +{ + base->SR = statusFlags; /*!< The status flags are cleared by writing 1 (w1c).*/ +} + +/*! + *@} + */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables the LPSPI interrupts. + * + * This function configures the various interrupt masks of the LPSPI. The parameters are base and an interrupt mask. + * Note that, for Tx fill and Rx FIFO drain requests, enabling the interrupt request disables the DMA request. + * + * @code + * LPSPI_EnableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable ); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The interrupt mask; Use the enum _lpspi_interrupt_enable. + */ +static inline void LPSPI_EnableInterrupts(LPSPI_Type *base, uint32_t mask) +{ + base->IER |= mask; +} + +/*! + * @brief Disables the LPSPI interrupts. + * + * @code + * LPSPI_DisableInterrupts(base, kLPSPI_TxInterruptEnable | kLPSPI_RxInterruptEnable ); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The interrupt mask; Use the enum _lpspi_interrupt_enable. + */ +static inline void LPSPI_DisableInterrupts(LPSPI_Type *base, uint32_t mask) +{ + base->IER &= ~mask; +} + +/*! + *@} + */ + +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables the LPSPI DMA request. + * + * This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask. + * @code + * LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The interrupt mask; Use the enum _lpspi_dma_enable. + */ +static inline void LPSPI_EnableDMA(LPSPI_Type *base, uint32_t mask) +{ + base->DER |= mask; +} + +/*! + * @brief Disables the LPSPI DMA request. + * + * This function configures the Rx and Tx DMA mask of the LPSPI. The parameters are base and a DMA mask. + * @code + * SPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The interrupt mask; Use the enum _lpspi_dma_enable. + */ +static inline void LPSPI_DisableDMA(LPSPI_Type *base, uint32_t mask) +{ + base->DER &= ~mask; +} + +/*! + * @brief Gets the LPSPI Transmit Data Register address for a DMA operation. + * + * This function gets the LPSPI Transmit Data Register address because this value is needed + * for the DMA operation. + * This function can be used for either master or slave mode. + * + * @param base LPSPI peripheral address. + * @return The LPSPI Transmit Data Register address. + */ +static inline uint32_t LPSPI_GetTxRegisterAddress(LPSPI_Type *base) +{ + return (uint32_t) & (base->TDR); +} + +/*! + * @brief Gets the LPSPI Receive Data Register address for a DMA operation. + * + * This function gets the LPSPI Receive Data Register address because this value is needed + * for the DMA operation. + * This function can be used for either master or slave mode. + * + * @param base LPSPI peripheral address. + * @return The LPSPI Receive Data Register address. + */ +static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base) +{ + return (uint32_t) & (base->RDR); +} + +/*! + *@} + */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Check the argument for transfer . + * + * @param base LPSPI peripheral address. + * @param transfer the transfer struct to be used. + * @param isEdma True to check for EDMA transfer, false to check interrupt non-blocking transfer + * @return Return true for right and false for wrong. + */ +bool LPSPI_CheckTransferArgument(LPSPI_Type *base, lpspi_transfer_t *transfer, bool isEdma); + +/*! + * @brief Configures the LPSPI for either master or slave. + * + * Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0). + * + * @param base LPSPI peripheral address. + * @param mode Mode setting (master or slave) of type lpspi_master_slave_mode_t. + */ +static inline void LPSPI_SetMasterSlaveMode(LPSPI_Type *base, lpspi_master_slave_mode_t mode) +{ + base->CFGR1 = (base->CFGR1 & (~LPSPI_CFGR1_MASTER_MASK)) | LPSPI_CFGR1_MASTER(mode); +} + +/*! + * @brief Configures the peripheral chip select used for the transfer. + * + * @param base LPSPI peripheral address. + * @param select LPSPI Peripheral Chip Select (PCS) configuration. + */ +static inline void LPSPI_SelectTransferPCS(LPSPI_Type *base, lpspi_which_pcs_t select) +{ + base->TCR = (base->TCR & (~LPSPI_TCR_PCS_MASK)) | LPSPI_TCR_PCS((uint8_t)select); +} + +/*! + * @brief Set the PCS signal to continuous or uncontinuous mode. + * + * @note In master mode, continuous transfer will keep the PCS asserted at the end of the frame size, until a command + * word is received that starts a new frame. So PCS must be set back to uncontinuous when transfer finishes. + * In slave mode, when continuous transfer is enabled, the LPSPI will only transmit the first frame size bits, after + * that the LPSPI will transmit received data back (assuming a 32-bit shift register). + * + * @param base LPSPI peripheral address. + * @param IsContinous True to set the transfer PCS to continuous mode, false to set to uncontinuous mode. + */ +static inline void LPSPI_SetPCSContinous(LPSPI_Type *base, bool IsContinous) +{ + if (IsContinous) + { + base->TCR |= LPSPI_TCR_CONT_MASK; + } + else + { + base->TCR &= ~LPSPI_TCR_CONT_MASK; + } +} + +/*! + * @brief Returns whether the LPSPI module is in master mode. + * + * @param base LPSPI peripheral address. + * @return Returns true if the module is in master mode or false if the module is in slave mode. + */ +static inline bool LPSPI_IsMaster(LPSPI_Type *base) +{ + return (bool)((base->CFGR1) & LPSPI_CFGR1_MASTER_MASK); +} + +/*! + * @brief Flushes the LPSPI FIFOs. + * + * @param base LPSPI peripheral address. + * @param flushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO. + * @param flushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO. + */ +static inline void LPSPI_FlushFifo(LPSPI_Type *base, bool flushTxFifo, bool flushRxFifo) +{ +#if defined(FSL_FEATURE_LPSPI_HAS_ERRATA_050456) && FSL_FEATURE_LPSPI_HAS_ERRATA_050456 + /* + * Resetting the FIFO using CR[RTF] and CR[RRF] does not clear the FIFO pointers completely. + * Workaround by reseting the entire module using CR[RST] bit. + */ + + (void)flushTxFifo; + (void)flushRxFifo; + + /* Save current state before resetting */ + bool enabled = base->CR & LPSPI_CR_MEN_MASK; + uint32_t cfgr1 = base->CFGR1; + uint32_t ccr = base->CCR; + uint32_t ccr1 = base->CCR1; + + /* To read the current state of the existing command word, LPSPI must be enabled */ + LPSPI_Enable(base, true); + uint32_t tcr = base->TCR; + + /* Reset all internal logic and registers. Bit remains set until cleared by software */ + LPSPI_Enable(base, false); + base->CR |= LPSPI_CR_RST_MASK; + base->CR &= ~LPSPI_CR_RST_MASK; + + /* Restore saved registers */ + base->CFGR1 = cfgr1; + base->CCR = ccr; + base->CCR1 = ccr1; + base->TCR = tcr; + + LPSPI_Enable(base, enabled); +#else + base->CR |= ((uint32_t)flushTxFifo << LPSPI_CR_RTF_SHIFT) | ((uint32_t)flushRxFifo << LPSPI_CR_RRF_SHIFT); +#endif +} + +/*! + * @brief Sets the transmit and receive FIFO watermark values. + * + * This function allows the user to set the receive and transmit FIFO watermarks. The function + * does not compare the watermark settings to the FIFO size. The FIFO watermark should not be + * equal to or greater than the FIFO size. It is up to the higher level driver to make this check. + * + * @param base LPSPI peripheral address. + * @param txWater The TX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated. + * @param rxWater The RX FIFO watermark value. Writing a value equal or greater than the FIFO size is truncated. + */ +static inline void LPSPI_SetFifoWatermarks(LPSPI_Type *base, uint32_t txWater, uint32_t rxWater) +{ + base->FCR = LPSPI_FCR_TXWATER(txWater) | LPSPI_FCR_RXWATER(rxWater); +} + +/*! + * @brief Configures all LPSPI peripheral chip select polarities simultaneously. + * + * Note that the CFGR1 should only be written when the LPSPI is disabled (LPSPIx_CR_MEN = 0). + * + * This is an example: PCS0 and PCS1 set to active low and other PCSs set to active high. Note that the number of + * PCS is device-specific. + * @code + * LPSPI_SetAllPcsPolarity(base, kLPSPI_Pcs0ActiveLow | kLPSPI_Pcs1ActiveLow); + * @endcode + * + * @param base LPSPI peripheral address. + * @param mask The PCS polarity mask; Use the enum _lpspi_pcs_polarity. + */ +static inline void LPSPI_SetAllPcsPolarity(LPSPI_Type *base, uint32_t mask) +{ + base->CFGR1 = (base->CFGR1 & ~LPSPI_CFGR1_PCSPOL_MASK) | LPSPI_CFGR1_PCSPOL(~mask); +} + +/*! + * @brief Configures the frame size. + * + * The minimum frame size is 8-bits and the maximum frame size is 4096-bits. If the frame size is less than or equal + * to 32-bits, the word size and frame size are identical. If the frame size is greater than 32-bits, the word + * size is 32-bits for each word except the last (the last word contains the remainder bits if the frame size is not + * divisible by 32). The minimum word size is 2-bits. A frame size of 33-bits (or similar) is not supported. + * + * Note 1: The transmit command register should be initialized before enabling the LPSPI in slave mode, although + * the command register does not update until after the LPSPI is enabled. After it is enabled, the transmit command + * register + * should only be changed if the LPSPI is idle. + * + * Note 2: The transmit and command FIFO is a combined FIFO that includes both transmit data and command words. That + * means the TCR register should be written to when the Tx FIFO is not full. + * + * @param base LPSPI peripheral address. + * @param frameSize The frame size in number of bits. + */ +static inline void LPSPI_SetFrameSize(LPSPI_Type *base, uint32_t frameSize) +{ + base->TCR = (base->TCR & ~LPSPI_TCR_FRAMESZ_MASK) | LPSPI_TCR_FRAMESZ(frameSize - 1U); +} + +/*! + * @brief Sets the LPSPI baud rate in bits per second. + * + * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest + * possible baud rate without exceeding the desired baud rate and returns the + * calculated baud rate in bits-per-second. It requires the caller to provide + * the frequency of the module source clock (in Hertz). Note that the baud rate + * does not go into effect until the Transmit Control Register (TCR) is programmed + * with the prescale value. Hence, this function returns the prescale tcrPrescaleValue + * parameter for later programming in the TCR. The higher level + * peripheral driver should alert the user of an out of range baud rate input. + * + * Note that the LPSPI module must first be disabled before configuring this. + * Note that the LPSPI module must be configured for master mode before configuring this. + * + * @param base LPSPI peripheral address. + * @param baudRate_Bps The desired baud rate in bits per second. + * @param srcClock_Hz Module source input clock in Hertz. + * @param tcrPrescaleValue The TCR prescale value needed to program the TCR. + * @return The actual calculated baud rate. This function may also return a "0" if the + * LPSPI is not configured for master mode or if the LPSPI module is not disabled. + */ + +uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, + uint32_t baudRate_Bps, + uint32_t srcClock_Hz, + uint32_t *tcrPrescaleValue); + +/*! + * @brief Manually configures a specific LPSPI delay parameter (module must be disabled to + * change the delay values). + * + * This function configures the following: + * SCK to PCS delay, or + * PCS to SCK delay, or + * The configurations must occur between the transfer delay. + * + * The delay names are available in type lpspi_delay_type_t. + * + * The user passes the desired delay along with the delay value. + * This allows the user to directly set the delay values if they have + * pre-calculated them or if they simply wish to manually increment the value. + * + * Note that the LPSPI module must first be disabled before configuring this. + * Note that the LPSPI module must be configured for master mode before configuring this. + * + * @param base LPSPI peripheral address. + * @param scaler The 8-bit delay value 0x00 to 0xFF (255). + * @param whichDelay The desired delay to configure, must be of type lpspi_delay_type_t. + */ +void LPSPI_MasterSetDelayScaler(LPSPI_Type *base, uint32_t scaler, lpspi_delay_type_t whichDelay); + +/*! + * @brief Calculates the delay based on the desired delay input in nanoseconds (module must be + * disabled to change the delay values). + * + * This function calculates the values for the following: + * SCK to PCS delay, or + * PCS to SCK delay, or + * The configurations must occur between the transfer delay. + * + * The delay names are available in type lpspi_delay_type_t. + * + * The user passes the desired delay and the desired delay value in + * nano-seconds. The function calculates the value needed for the desired delay parameter + * and returns the actual calculated delay because an exact delay match may not be possible. In this + * case, the closest match is calculated without going below the desired delay value input. + * It is possible to input a very large delay value that exceeds the capability of the part, in + * which case the maximum supported delay is returned. It is up to the higher level + * peripheral driver to alert the user of an out of range delay input. + * + * Note that the LPSPI module must be configured for master mode before configuring this. And note that + * the delayTime = LPSPI_clockSource / (PRESCALE * Delay_scaler). + * + * @param base LPSPI peripheral address. + * @param delayTimeInNanoSec The desired delay value in nano-seconds. + * @param whichDelay The desired delay to configuration, which must be of type lpspi_delay_type_t. + * @param srcClock_Hz Module source input clock in Hertz. + * @return actual Calculated delay value in nano-seconds. + */ +uint32_t LPSPI_MasterSetDelayTimes(LPSPI_Type *base, + uint32_t delayTimeInNanoSec, + lpspi_delay_type_t whichDelay, + uint32_t srcClock_Hz); + +/*! + * @brief Writes data into the transmit data buffer. + * + * This function writes data passed in by the user to the Transmit Data Register (TDR). + * The user can pass up to 32-bits of data to load into the TDR. If the frame size exceeds 32-bits, + * the user has to manage sending the data one 32-bit word at a time. + * Any writes to the TDR result in an immediate push to the transmit FIFO. + * This function can be used for either master or slave modes. + * + * @param base LPSPI peripheral address. + * @param data The data word to be sent. + */ +static inline void LPSPI_WriteData(LPSPI_Type *base, uint32_t data) +{ + base->TDR = data; +} + +/*! + * @brief Reads data from the data buffer. + * + * This function reads the data from the Receive Data Register (RDR). + * This function can be used for either master or slave mode. + * + * @param base LPSPI peripheral address. + * @return The data read from the data buffer. + */ +static inline uint32_t LPSPI_ReadData(LPSPI_Type *base) +{ + return (base->RDR); +} + +/*! + * @brief Set up the dummy data. + * + * @param base LPSPI peripheral address. + * @param dummyData Data to be transferred when tx buffer is NULL. + * Note: + * This API has no effect when LPSPI in slave interrupt mode, because driver + * will set the TXMSK bit to 1 if txData is NULL, no data is loaded from transmit + * FIFO and output pin is tristated. + */ +void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData); + +/*! + *@} + */ + +/*! + * @name Transactional + * @{ + */ +/*Transactional APIs*/ + +/*! + * @brief Initializes the LPSPI master handle. + * + * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + + * @param base LPSPI peripheral address. + * @param handle LPSPI handle pointer to lpspi_master_handle_t. + * @param callback DSPI callback. + * @param userData callback function parameter. + */ +void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, + lpspi_master_handle_t *handle, + lpspi_master_transfer_callback_t callback, + void *userData); + +/*! + * @brief LPSPI master transfer data using a polling method. + * + * This function transfers data using a polling method. This is a blocking function, which does not return until all + * transfers have been + * completed. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * @param base LPSPI peripheral address. + * @param transfer pointer to lpspi_transfer_t structure. + * @return status of status_t. + */ +status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer); + +/*! + * @brief LPSPI master transfer data using an interrupt method. + * + * This function transfers data using an interrupt method. This is a non-blocking function, which returns right away. + * When all data is transferred, the callback function is called. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not integer multiples of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + * @param transfer pointer to lpspi_transfer_t structure. + * @return status of status_t. + */ +status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer); + +/*! + * @brief Gets the master transfer remaining bytes. + * + * This function gets the master transfer remaining bytes. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @return status of status_t. + */ +status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count); + +/*! + * @brief LPSPI master abort transfer which uses an interrupt method. + * + * This function aborts a transfer which uses an interrupt method. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + */ +void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle); + +/*! + * @brief LPSPI Master IRQ handler function. + * + * This function processes the LPSPI transmit and receive IRQ. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_master_handle_t structure which stores the transfer state. + */ +void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle); + +/*! + * @brief Initializes the LPSPI slave handle. + * + * This function initializes the LPSPI handle, which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + * + * @param base LPSPI peripheral address. + * @param handle LPSPI handle pointer to lpspi_slave_handle_t. + * @param callback DSPI callback. + * @param userData callback function parameter. + */ +void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, + lpspi_slave_handle_t *handle, + lpspi_slave_transfer_callback_t callback, + void *userData); + +/*! + * @brief LPSPI slave transfer data using an interrupt method. + * + * This function transfer data using an interrupt method. This is a non-blocking function, which returns right away. + * When all data is transferred, the callback function is called. + * + * Note: + * The transfer data size should be integer multiples of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + * @param transfer pointer to lpspi_transfer_t structure. + * @return status of status_t. + */ +status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer); + +/*! + * @brief Gets the slave transfer remaining bytes. + * + * This function gets the slave transfer remaining bytes. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + * @param count Number of bytes transferred so far by the non-blocking transaction. + * @return status of status_t. + */ +status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *handle, size_t *count); + +/*! + * @brief LPSPI slave aborts a transfer which uses an interrupt method. + * + * This function aborts a transfer which uses an interrupt method. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + */ +void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle); + +/*! + * @brief LPSPI Slave IRQ handler function. + * + * This function processes the LPSPI transmit and receives an IRQ. + * + * @param base LPSPI peripheral address. + * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state. + */ +void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle); + +/*! + * @brief Wait for tx FIFO to be empty. + * + * This function wait the tx fifo empty + * + * @param base LPSPI peripheral address. + * @return true for the tx FIFO is ready, false is not. + */ +bool LPSPI_WaitTxFifoEmpty(LPSPI_Type *base); + +/*! + *@} + */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /*FSL_LPSPI_H_*/ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpspi_edma.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpspi_edma.c new file mode 100644 index 00000000000..1b2af7d90f8 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpspi_edma.c @@ -0,0 +1,1324 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpspi_edma.h" + +/* + * $Coverage Justification Reference$ + * + * $Justification fsl_lpspi_edma_c_ref_1$ + * The default branch cannot be executed in any circumstances, it is only added to avoid MISRA violation. + * + */ +/*********************************************************************************************************************** + * Definitions + ***********************************************************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpspi_edma" +#endif + +/*! + * @brief Structure definition for dspi_master_edma_private_handle_t. The structure is private. + */ +typedef struct _lpspi_master_edma_private_handle +{ + LPSPI_Type *base; /*!< LPSPI peripheral base address. */ + lpspi_master_edma_handle_t *handle; /*!< lpspi_master_edma_handle_t handle */ +} lpspi_master_edma_private_handle_t; + +/*! + * @brief Structure definition for dspi_slave_edma_private_handle_t. The structure is private. + */ +typedef struct _lpspi_slave_edma_private_handle +{ + LPSPI_Type *base; /*!< LPSPI peripheral base address. */ + lpspi_slave_edma_handle_t *handle; /*!< lpspi_slave_edma_handle_t handle */ +} lpspi_slave_edma_private_handle_t; + +/*********************************************************************************************************************** + * Prototypes + ***********************************************************************************************************************/ + +/*! + * @brief EDMA_LpspiMasterCallback after the LPSPI master transfer completed by using EDMA. + * This is not a public API. + */ +static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle, + void *g_lpspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds); + +/*! + * @brief EDMA_LpspiSlaveCallback after the LPSPI slave transfer completed by using EDMA. + * This is not a public API. + */ +static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle, + void *g_lpspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds); + +static void LPSPI_SeparateEdmaReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap); + +/*********************************************************************************************************************** + * Variables + ***********************************************************************************************************************/ +/*! @brief Pointers to lpspi bases for each instance. */ +static LPSPI_Type *const s_lpspiBases[] = LPSPI_BASE_PTRS; + +/*! @brief Pointers to lpspi edma handles for each instance. */ +static lpspi_master_edma_private_handle_t s_lpspiMasterEdmaPrivateHandle[ARRAY_SIZE(s_lpspiBases)]; +static lpspi_slave_edma_private_handle_t s_lpspiSlaveEdmaPrivateHandle[ARRAY_SIZE(s_lpspiBases)]; + +/*********************************************************************************************************************** + * Code + ***********************************************************************************************************************/ +static void LPSPI_SeparateEdmaReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap) +{ + assert(rxData != NULL); + + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_edma_c_ref_1$ + */ + switch (bytesEachRead) + { + case 1: + if (!isByteSwap) + { + *rxData = (uint8_t)readData; + ++rxData; + } + else + { + *rxData = (uint8_t)(readData >> 24); + ++rxData; + } + break; + + case 2: + if (!isByteSwap) + { + *rxData = (uint8_t)readData; + ++rxData; + *rxData = (uint8_t)(readData >> 8); + ++rxData; + } + else + { + *rxData = (uint8_t)(readData >> 16); + ++rxData; + *rxData = (uint8_t)(readData >> 24); + ++rxData; + } + break; + + case 4: + + *rxData = (uint8_t)readData; + ++rxData; + *rxData = (uint8_t)(readData >> 8); + ++rxData; + *rxData = (uint8_t)(readData >> 16); + ++rxData; + *rxData = (uint8_t)(readData >> 24); + ++rxData; + + break; + + default: + assert(false); + break; + } +} + +/*! + * brief Initializes the LPSPI master eDMA handle. + * + * This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + * + * Note that the LPSPI eDMA has a separated (Rx and Rx as two sources) or shared (Rx and Tx are the same source) DMA + * request source. + * (1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and + * Tx DMAMUX source for edmaIntermediaryToTxRegHandle. + * (2) For a shared DMA request source, enable and set the Rx/Rx DMAMUX source for edmaRxRegToRxDataHandle. + * + * param base LPSPI peripheral base address. + * param handle LPSPI handle pointer to lpspi_master_edma_handle_t. + * param callback LPSPI callback. + * param userData callback function parameter. + * param edmaRxRegToRxDataHandle edmaRxRegToRxDataHandle pointer to edma_handle_t. + * param edmaTxDataToTxRegHandle edmaTxDataToTxRegHandle pointer to edma_handle_t. + */ +void LPSPI_MasterTransferCreateHandleEDMA(LPSPI_Type *base, + lpspi_master_edma_handle_t *handle, + lpspi_master_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *edmaRxRegToRxDataHandle, + edma_handle_t *edmaTxDataToTxRegHandle) +{ + assert(handle != NULL); + assert(edmaRxRegToRxDataHandle != NULL); + assert(edmaTxDataToTxRegHandle != NULL); + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + uint32_t instance = LPSPI_GetInstance(base); + + s_lpspiMasterEdmaPrivateHandle[instance].base = base; + s_lpspiMasterEdmaPrivateHandle[instance].handle = handle; + + handle->callback = callback; + handle->userData = userData; + handle->dataBytesEveryTime = DMA_MAX_TRANSFER_COUNT; + + handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle; + handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle; +} + +static void LPSPI_PrepareTransferEDMA(LPSPI_Type *base) +{ + /* Flush FIFO, clear status, disable all the inerrupts and DMA requests. */ + LPSPI_FlushFifo(base, true, true); + LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_AllStatusFlag); + LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_AllInterruptEnable); + LPSPI_DisableDMA(base, (uint32_t)kLPSPI_RxDmaEnable | (uint32_t)kLPSPI_TxDmaEnable); +} + +/*! + * brief LPSPI master config transfer parameter using eDMA. + * + * This function is preparing to transfer data using eDMA. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + * param configFlags transfer configuration flags. ref _lpspi_transfer_config_flag_for_master. + * return Indicates whether LPSPI master transfer was successful or not. + * retval kStatus_Success Execution successfully. + * retval kStatus_LPSPI_Busy The LPSPI device is busy. + */ +status_t LPSPI_MasterTransferPrepareEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, uint32_t configFlags) +{ + assert(handle != NULL); + + /* Check that we're not busy.*/ + if (handle->state == (uint8_t)kLPSPI_Busy) + { + return kStatus_LPSPI_Busy; + } + + /* Disable module before configuration */ + LPSPI_Enable(base, false); + + LPSPI_PrepareTransferEDMA(base); + + bool isByteSwap = ((configFlags & (uint32_t)kLPSPI_MasterByteSwap) != 0U); + bool isPcsContinuous = ((configFlags & (uint32_t)kLPSPI_MasterPcsContinuous) != 0U); + uint32_t instance = LPSPI_GetInstance(base); + uint8_t dummyData = g_lpspiDummyData[instance]; + /*Used for byte swap*/ + uint32_t whichPcs = (configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; + uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; + + handle->txBuffIfNull = + ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); + /*The TX and RX FIFO sizes are always the same*/ + handle->fifoSize = LPSPI_GetRxFifoSize(base); + handle->isPcsContinuous = isPcsContinuous; + handle->isByteSwap = isByteSwap; + handle->isThereExtraRxBytes = false; + + /*Because DMA is fast enough , so set the RX and TX watermarks to 0 .*/ + LPSPI_SetFifoWatermarks(base, 0U, 0U); + + /* Transfers will stall when transmit FIFO is empty or receive FIFO is full. */ + base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); + + /* Enable module for following configuration of TCR to take effect. */ + LPSPI_Enable(base, true); + + /* For DMA transfer , we'd better not masked the transmit data and receive data in TCR since the transfer flow is + * hard to controlled by software. */ + base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK | LPSPI_TCR_PCS_MASK)) | + LPSPI_TCR_CONT(isPcsContinuous) | LPSPI_TCR_BYSW(isByteSwap) | LPSPI_TCR_PCS(whichPcs); + /*Calculate the bytes for write/read the TX/RX register each time*/ + if (bytesPerFrame <= 4U) + { + handle->bytesEachWrite = (uint8_t)bytesPerFrame; + handle->bytesEachRead = (uint8_t)bytesPerFrame; + handle->bytesLastRead = (uint8_t)bytesPerFrame; + } + else + { + handle->bytesEachWrite = 4U; + handle->bytesEachRead = 4U; + + handle->bytesLastRead = 4U; + } + return kStatus_Success; +} + +/*! + * brief LPSPI master transfer data using eDMA without configs. + * + * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data + * is transferred, the callback function is called. + * + * Note: + * This API is only for transfer through DMA without configuration. + * Before calling this API, you must call LPSPI_MasterTransferPrepareEDMALite to configure it once. + * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure, config field is not working. + * return Indicates whether LPSPI master transfer was successful or not. + * retval kStatus_Success Execution successfully. + * retval kStatus_LPSPI_Busy The LPSPI device is busy. + * retval kStatus_InvalidArgument The transfer structure is invalid. + */ +status_t LPSPI_MasterTransferEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer) +{ + assert(handle != NULL); + assert(transfer != NULL); + + /* Check that we're not busy.*/ + if (handle->state == (uint8_t)kLPSPI_Busy) + { + return kStatus_LPSPI_Busy; + } + + /* Check arguements */ + if (!LPSPI_CheckTransferArgument(base, transfer, true)) + { + return kStatus_InvalidArgument; + } + + /* Variables */ + uint32_t firstTimeDataSize = 0; + bool isThereExtraTxBytes = false; + uint8_t bytesLastWrite = 0; + uint32_t instance = LPSPI_GetInstance(base); + /*Used for byte swap*/ + uint32_t addrOffset = 0; + uint32_t rxAddr = LPSPI_GetRxRegisterAddress(base); + uint32_t txAddr = LPSPI_GetTxRegisterAddress(base); + uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; + edma_transfer_config_t transferConfigRx = {0}; + edma_transfer_config_t transferConfigTx = {0}; + edma_tcd_t *softwareTCD_pcsContinuous = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[2]) & (~0x1FU)); + edma_tcd_t *softwareTCD_extraBytes = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU)); + + if (transfer->dataSize <= bytesPerFrame) + { + /* Once dma transfer*/ + firstTimeDataSize = transfer->dataSize; + handle->isMultiDMATransmit = false; + } + else if (transfer->dataSize > handle->dataBytesEveryTime) + { + /* More dma transfer*/ + firstTimeDataSize = handle->dataBytesEveryTime; + handle->isMultiDMATransmit = true; + if (transfer->dataSize % handle->dataBytesEveryTime != 0U) + { + handle->lastTimeDataBytes = transfer->dataSize % handle->dataBytesEveryTime; + } + else + { + handle->lastTimeDataBytes = handle->dataBytesEveryTime; + } + + handle->dmaTransmitTime = + (uint8_t)((transfer->dataSize + handle->dataBytesEveryTime - 1U) / handle->dataBytesEveryTime); + } + else + { + /* Once dma transfer*/ + firstTimeDataSize = transfer->dataSize; + handle->isMultiDMATransmit = false; + } + handle->state = (uint8_t)kLPSPI_Busy; + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->txRemainingByteCount = firstTimeDataSize; + handle->rxRemainingByteCount = firstTimeDataSize; + handle->totalByteCount = firstTimeDataSize; + handle->writeRegRemainingTimes = (firstTimeDataSize / bytesPerFrame) * ((bytesPerFrame + 3U) / 4U); + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + + handle->isThereExtraRxBytes = false; + + /*Calculate the bytes for write/read the TX/RX register each time*/ + if (bytesPerFrame > 4U) + { + if ((transfer->dataSize % 4U) != 0U) + { + bytesLastWrite = (uint8_t)(transfer->dataSize % 4U); + handle->bytesLastRead = bytesLastWrite; + + isThereExtraTxBytes = true; + + --handle->writeRegRemainingTimes; + + --handle->readRegRemainingTimes; + handle->isThereExtraRxBytes = true; + } + } + + EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_LpspiMasterCallback, + &s_lpspiMasterEdmaPrivateHandle[instance]); + + /* Configure rx EDMA transfer */ + EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); + + if (handle->rxData != NULL) + { + transferConfigRx.destAddr = (uint32_t) & (handle->rxData[0]); + transferConfigRx.destOffset = 1; + } + else + { + transferConfigRx.destAddr = (uint32_t) & (handle->rxBuffIfNull); + transferConfigRx.destOffset = 0; + } + transferConfigRx.destTransferSize = kEDMA_TransferSize1Bytes; + + addrOffset = 0; + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_edma_c_ref_1$ + */ + switch (handle->bytesEachRead) + { + case (1U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigRx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + addrOffset = 3; + } + break; + + case (2U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize2Bytes; + transferConfigRx.minorLoopBytes = 2; + if (handle->isByteSwap) + { + addrOffset = 2; + } + break; + + case (4U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigRx.minorLoopBytes = 4; + break; + + default: + transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigRx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigRx.srcAddr = (uint32_t)rxAddr + addrOffset; + transferConfigRx.srcOffset = 0; + + transferConfigRx.majorLoopCounts = handle->readRegRemainingTimes; + + /* Store the initially configured eDMA minor byte transfer count into the LPSPI handle */ + handle->nbytes = (uint8_t)transferConfigRx.minorLoopBytes; + + EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &transferConfigRx, NULL); + EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + (uint32_t)kEDMA_MajorInterruptEnable); + + /* Configure tx EDMA transfer */ + EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel); + + if (isThereExtraTxBytes) + { + if (handle->txData != NULL) + { + transferConfigTx.srcAddr = (uint32_t) & (transfer->txData[transfer->dataSize - bytesLastWrite]); + transferConfigTx.srcOffset = 1; + } + else + { + transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigTx.srcOffset = 0; + } + + transferConfigTx.destOffset = 0; + + transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; + + addrOffset = 0; + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_edma_c_ref_1$ + */ + switch (bytesLastWrite) + { + case (1U): + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + addrOffset = 3; + } + break; + + case (2U): + transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigTx.minorLoopBytes = 2; + if (handle->isByteSwap) + { + addrOffset = 2; + } + break; + + default: + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigTx.destAddr = (uint32_t)txAddr + addrOffset; + transferConfigTx.majorLoopCounts = 1; + +#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4 + EDMA_TcdResetExt(handle->edmaRxRegToRxDataHandle->base, softwareTCD_extraBytes); + if (handle->isPcsContinuous) + { + EDMA_TcdSetTransferConfigExt(handle->edmaRxRegToRxDataHandle->base, softwareTCD_extraBytes, + &transferConfigTx, softwareTCD_pcsContinuous); + } + else + { + EDMA_TcdSetTransferConfigExt(handle->edmaRxRegToRxDataHandle->base, softwareTCD_extraBytes, + &transferConfigTx, NULL); + } +#else + EDMA_TcdReset(softwareTCD_extraBytes); + if (handle->isPcsContinuous) + { + EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, softwareTCD_pcsContinuous); + } + else + { + EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, NULL); + } +#endif + } + + if (handle->isPcsContinuous) + { + /* Set continue incase of twice call transfer. */ + LPSPI_SetPCSContinous(base, true); + handle->transmitCommand = base->TCR & ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK); + transferConfigTx.srcAddr = (uint32_t) & (handle->transmitCommand); + transferConfigTx.srcOffset = 0; + + transferConfigTx.destAddr = (uint32_t) & (base->TCR); + transferConfigTx.destOffset = 0; + + transferConfigTx.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigTx.minorLoopBytes = 4; + transferConfigTx.majorLoopCounts = 1; + +#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4 + EDMA_TcdResetExt(handle->edmaRxRegToRxDataHandle->base, softwareTCD_pcsContinuous); + EDMA_TcdSetTransferConfigExt(handle->edmaRxRegToRxDataHandle->base, softwareTCD_pcsContinuous, + &transferConfigTx, NULL); +#else + EDMA_TcdReset(softwareTCD_pcsContinuous); + EDMA_TcdSetTransferConfig(softwareTCD_pcsContinuous, &transferConfigTx, NULL); +#endif + } + + if (handle->txData != NULL) + { + transferConfigTx.srcAddr = (uint32_t)(handle->txData); + transferConfigTx.srcOffset = 1; + } + else + { + transferConfigTx.srcAddr = (uint32_t)(&handle->txBuffIfNull); + transferConfigTx.srcOffset = 0; + } + + transferConfigTx.destOffset = 0; + + transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; + + addrOffset = 0U; + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_edma_c_ref_1$ + */ + switch (handle->bytesEachRead) + { + case (1U): + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + addrOffset = 3; + } + break; + + case (2U): + transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigTx.minorLoopBytes = 2; + + if (handle->isByteSwap) + { + addrOffset = 2; + } + break; + + case (4U): + transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigTx.minorLoopBytes = 4; + break; + + default: + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigTx.destAddr = (uint32_t)txAddr + addrOffset; + + transferConfigTx.majorLoopCounts = handle->writeRegRemainingTimes; + + if (isThereExtraTxBytes) + { + handle->lastTimeTCD = softwareTCD_extraBytes; + } + else if (handle->isPcsContinuous) + { + handle->lastTimeTCD = softwareTCD_pcsContinuous; + } + else + { + handle->lastTimeTCD = NULL; + } + + if (handle->isMultiDMATransmit) + { + transferConfigTx.majorLoopCounts = handle->dataBytesEveryTime; + if (handle->isPcsContinuous) + { + /* Pcs-continue mode is not supported in Multi DMA. + Please use no-continue mode and use GPIO control CS pin*/ + LPSPI_SetPCSContinous(base, false); + assert(false); + } + + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigTx, NULL); + (void)memcpy(&handle->transferConfigTx, &transferConfigTx, sizeof(edma_transfer_config_t)); + (void)memcpy(&handle->transferConfigRx, &transferConfigRx, sizeof(edma_transfer_config_t)); + } + else + { + transferConfigTx.majorLoopCounts = handle->writeRegRemainingTimes; + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigTx, handle->lastTimeTCD); + } + EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle); + EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); + LPSPI_EnableDMA(base, (uint32_t)kLPSPI_RxDmaEnable | (uint32_t)kLPSPI_TxDmaEnable); + + return kStatus_Success; +} + +/*! + * brief LPSPI master transfer data using eDMA. + * + * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data + * is transferred, the callback function is called. + * + * Note: + * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ +status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer) +{ + status_t status = kStatus_Fail; + status = LPSPI_MasterTransferPrepareEDMALite(base, handle, transfer->configFlags); + if (kStatus_Success != status) + { + return status; + } + return LPSPI_MasterTransferEDMALite(base, handle, transfer); +} + +static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle, + void *g_lpspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds) +{ + assert(edmaHandle != NULL); + assert(g_lpspiEdmaPrivateHandle != NULL); + + uint32_t readData; + status_t callbackStatus = kStatus_Success; + lpspi_master_edma_private_handle_t *lpspiEdmaPrivateHandle; + lpspi_master_edma_handle_t *lpspiEdmaHandle; + lpspiEdmaPrivateHandle = (lpspi_master_edma_private_handle_t *)g_lpspiEdmaPrivateHandle; + + lpspiEdmaHandle = lpspiEdmaPrivateHandle->handle; + size_t rxRemainingByteCount = lpspiEdmaHandle->rxRemainingByteCount; + uint8_t bytesLastRead = lpspiEdmaHandle->bytesLastRead; + bool isByteSwap = lpspiEdmaHandle->isByteSwap; + + bool lpspitxDmaUpdate = false; + bool lpspirxDmaUpdate = false; + + LPSPI_DisableDMA(lpspiEdmaPrivateHandle->base, (uint32_t)kLPSPI_TxDmaEnable | (uint32_t)kLPSPI_RxDmaEnable); + + if (!transferDone) + { + callbackStatus = kStatus_LPSPI_Error; + } + else + { + if (lpspiEdmaHandle->isMultiDMATransmit) + { + /* multi DMA transmit */ + lpspiEdmaHandle->dmaTransmitTime--; + if (lpspiEdmaHandle->dmaTransmitTime >= 1U) + { + if (lpspiEdmaHandle->txData != NULL) + { + lpspitxDmaUpdate = true; + lpspiEdmaHandle->transferConfigTx.srcAddr += lpspiEdmaHandle->dataBytesEveryTime; + } + if (lpspiEdmaHandle->rxData != NULL) + { + lpspirxDmaUpdate = true; + lpspiEdmaHandle->transferConfigRx.destAddr += lpspiEdmaHandle->dataBytesEveryTime; + } + /* The last time - 1 time, need check the lastTime data bytes */ + if (lpspiEdmaHandle->dmaTransmitTime == 1U) + { + if (lpspiEdmaHandle->lastTimeDataBytes != lpspiEdmaHandle->dataBytesEveryTime) + { + /* Need update count if last time count is not dataBytesEveryTime*/ + lpspiEdmaHandle->transferConfigTx.majorLoopCounts = lpspiEdmaHandle->lastTimeDataBytes; + lpspiEdmaHandle->transferConfigRx.majorLoopCounts = lpspiEdmaHandle->lastTimeDataBytes; + lpspitxDmaUpdate = true; + lpspirxDmaUpdate = true; + } + } + /* Update RX channel first */ + if (lpspirxDmaUpdate) + { + EDMA_SetTransferConfig(lpspiEdmaHandle->edmaRxRegToRxDataHandle->base, + lpspiEdmaHandle->edmaRxRegToRxDataHandle->channel, + &lpspiEdmaHandle->transferConfigRx, NULL); + } + EDMA_StartTransfer(lpspiEdmaHandle->edmaRxRegToRxDataHandle); + /* Update TX channel */ + if (lpspitxDmaUpdate) + { + EDMA_SetTransferConfig(lpspiEdmaHandle->edmaTxDataToTxRegHandle->base, + lpspiEdmaHandle->edmaTxDataToTxRegHandle->channel, + &lpspiEdmaHandle->transferConfigTx, NULL); + } + EDMA_StartTransfer(lpspiEdmaHandle->edmaTxDataToTxRegHandle); + + LPSPI_EnableDMA(lpspiEdmaPrivateHandle->base, + (uint32_t)kLPSPI_TxDmaEnable | (uint32_t)kLPSPI_RxDmaEnable); + /* Continue DMA transmit*/ + return; + } + else + { + /* Transmit complete */ + } + } + else + { + /* Once DMA transfer */ + if (lpspiEdmaPrivateHandle->handle->isThereExtraRxBytes) + { + while (LPSPI_GetRxFifoCount(lpspiEdmaPrivateHandle->base) == 0U) + { + } + readData = LPSPI_ReadData(lpspiEdmaPrivateHandle->base); + if (lpspiEdmaPrivateHandle->handle->rxData != NULL) + { + LPSPI_SeparateEdmaReadData( + &(lpspiEdmaPrivateHandle->handle->rxData[rxRemainingByteCount - bytesLastRead]), readData, + bytesLastRead, isByteSwap); + } + } + /* Transmit complete */ + } + } + + lpspiEdmaPrivateHandle->handle->state = (uint8_t)kLPSPI_Idle; + + if (lpspiEdmaPrivateHandle->handle->callback != NULL) + { + lpspiEdmaPrivateHandle->handle->callback(lpspiEdmaPrivateHandle->base, lpspiEdmaPrivateHandle->handle, + callbackStatus, lpspiEdmaPrivateHandle->handle->userData); + } +} + +/*! + * brief LPSPI master aborts a transfer which is using eDMA. + * + * This function aborts a transfer which is using eDMA. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + */ +void LPSPI_MasterTransferAbortEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle) +{ + assert(handle != NULL); + + LPSPI_DisableDMA(base, (uint32_t)kLPSPI_RxDmaEnable | (uint32_t)kLPSPI_TxDmaEnable); + + EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle); + EDMA_AbortTransfer(handle->edmaTxDataToTxRegHandle); + + handle->state = (uint8_t)kLPSPI_Idle; +} + +/*! + * brief Gets the master eDMA transfer remaining bytes. + * + * This function gets the master eDMA transfer remaining bytes. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the EDMA transaction. + * return status of status_t. + */ +status_t LPSPI_MasterTransferGetCountEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != (uint8_t)kLPSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t remainingByte; + + remainingByte = + (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base, + handle->edmaRxRegToRxDataHandle->channel); + + *count = handle->totalByteCount - remainingByte; + + return kStatus_Success; +} + +/*! + * brief Initializes the LPSPI slave eDMA handle. + * + * This function initializes the LPSPI eDMA handle which can be used for other LPSPI transactional APIs. Usually, for a + * specified LPSPI instance, call this API once to get the initialized handle. + * + * Note that LPSPI eDMA has a separated (Rx and Tx as two sources) or shared (Rx and Tx as the same source) DMA request + * source. + * + * (1) For a separated DMA request source, enable and set the Rx DMAMUX source for edmaRxRegToRxDataHandle and + * Tx DMAMUX source for edmaTxDataToTxRegHandle. + * (2) For a shared DMA request source, enable and set the Rx/Rx DMAMUX source for edmaRxRegToRxDataHandle . + * + * param base LPSPI peripheral base address. + * param handle LPSPI handle pointer to lpspi_slave_edma_handle_t. + * param callback LPSPI callback. + * param userData callback function parameter. + * param edmaRxRegToRxDataHandle edmaRxRegToRxDataHandle pointer to edma_handle_t. + * param edmaTxDataToTxRegHandle edmaTxDataToTxRegHandle pointer to edma_handle_t. + */ +void LPSPI_SlaveTransferCreateHandleEDMA(LPSPI_Type *base, + lpspi_slave_edma_handle_t *handle, + lpspi_slave_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *edmaRxRegToRxDataHandle, + edma_handle_t *edmaTxDataToTxRegHandle) +{ + assert(handle != NULL); + assert(edmaRxRegToRxDataHandle != NULL); + assert(edmaTxDataToTxRegHandle != NULL); + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + uint32_t instance = LPSPI_GetInstance(base); + + s_lpspiSlaveEdmaPrivateHandle[instance].base = base; + s_lpspiSlaveEdmaPrivateHandle[instance].handle = handle; + + handle->callback = callback; + handle->userData = userData; + + handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle; + handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle; +} + +/*! + * brief LPSPI slave transfers data using eDMA. + * + * This function transfers data using eDMA. This is a non-blocking function, which return right away. When all data + * is transferred, the callback function is called. + * + * Note: + * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4. + * For bytesPerFrame greater than 4: + * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4. + * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_slave_edma_handle_t structure which stores the transfer state. + * param transfer pointer to lpspi_transfer_t structure. + * return status of status_t. + */ +status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, lpspi_transfer_t *transfer) +{ + assert(handle != NULL); + assert(transfer != NULL); + + /* Check that we're not busy.*/ + if (handle->state == (uint8_t)kLPSPI_Busy) + { + return kStatus_LPSPI_Busy; + } + /* Disable module before configuration. */ + LPSPI_Enable(base, false); + /* Check arguements, also dma transfer can not support 3 bytes */ + if (!LPSPI_CheckTransferArgument(base, transfer, true)) + { + return kStatus_InvalidArgument; + } + + LPSPI_PrepareTransferEDMA(base); + + /* Variables */ + bool isThereExtraTxBytes = false; + bool isByteSwap = ((transfer->configFlags & (uint32_t)kLPSPI_MasterByteSwap) != 0U); + uint8_t bytesLastWrite = 0; + uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)]; + uint32_t mask = (uint32_t)kLPSPI_RxDmaEnable; + + /* Used for byte swap */ + uint32_t addrOffset = 0; + uint32_t instance = LPSPI_GetInstance(base); + uint32_t rxAddr = LPSPI_GetRxRegisterAddress(base); + uint32_t txAddr = LPSPI_GetTxRegisterAddress(base); + uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT; + uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U; + edma_transfer_config_t transferConfigRx = {0}; + edma_transfer_config_t transferConfigTx = {0}; + edma_tcd_t *softwareTCD_extraBytes = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU)); + + /* Assign the original value for members of transfer handle. */ + handle->state = (uint8_t)kLPSPI_Busy; + handle->txData = transfer->txData; + handle->rxData = transfer->rxData; + handle->txRemainingByteCount = transfer->dataSize; + handle->rxRemainingByteCount = transfer->dataSize; + handle->totalByteCount = transfer->dataSize; + handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3U) / 4U); + handle->readRegRemainingTimes = handle->writeRegRemainingTimes; + handle->txBuffIfNull = + ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24); + /*The TX and RX FIFO sizes are always the same*/ + handle->fifoSize = LPSPI_GetRxFifoSize(base); + handle->isByteSwap = isByteSwap; + handle->isThereExtraRxBytes = false; + + /* Because DMA is fast enough, set the RX and TX watermarks to 0. */ + LPSPI_SetFifoWatermarks(base, 0U, 0U); + + /* Transfers will stall when transmit FIFO is empty or receive FIFO is full. */ + base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); + + /* Enable module for following configuration of TCR to take effect. */ + LPSPI_Enable(base, true); + + /* For DMA transfer, mask the transmit data if the tx data is null, for rx the receive data should not be masked at + any time since we use rx dma transfer finish cllback to indicate transfer finish. */ + base->TCR = + (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK | LPSPI_TCR_TXMSK_MASK)) | + LPSPI_TCR_TXMSK(transfer->txData == NULL) | LPSPI_TCR_BYSW(isByteSwap) | LPSPI_TCR_PCS(whichPcs); + + if (transfer->txData == NULL) + { + if (!LPSPI_WaitTxFifoEmpty(base)) + { + return kStatus_LPSPI_Error; + } + } + + /*Calculate the bytes for write/read the TX/RX register each time*/ + if (bytesPerFrame <= 4U) + { + handle->bytesEachWrite = (uint8_t)bytesPerFrame; + handle->bytesEachRead = (uint8_t)bytesPerFrame; + + handle->bytesLastRead = (uint8_t)bytesPerFrame; + } + else + { + handle->bytesEachWrite = 4U; + handle->bytesEachRead = 4U; + + handle->bytesLastRead = 4U; + + if ((transfer->dataSize % 4U) != 0U) + { + bytesLastWrite = (uint8_t)(transfer->dataSize % 4U); + handle->bytesLastRead = bytesLastWrite; + + isThereExtraTxBytes = true; + --handle->writeRegRemainingTimes; + + handle->isThereExtraRxBytes = true; + --handle->readRegRemainingTimes; + } + } + + EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_LpspiSlaveCallback, + &s_lpspiSlaveEdmaPrivateHandle[instance]); + + /*Rx*/ + /* + * $Branch Coverage Justification$ + * LPSPI_CheckTransferArgument will check parameters, here readRegRemainingTimes cannot be 0. + */ + if (handle->readRegRemainingTimes > 0U) + { + EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel); + + if (handle->rxData != NULL) + { + transferConfigRx.destAddr = (uint32_t) & (handle->rxData[0]); + transferConfigRx.destOffset = 1; + } + else + { + transferConfigRx.destAddr = (uint32_t) & (handle->rxBuffIfNull); + transferConfigRx.destOffset = 0; + } + transferConfigRx.destTransferSize = kEDMA_TransferSize1Bytes; + + addrOffset = 0; + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_edma_c_ref_1$ + */ + switch (handle->bytesEachRead) + { + case (1U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigRx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + addrOffset = 3; + } + break; + + case (2U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize2Bytes; + transferConfigRx.minorLoopBytes = 2; + if (handle->isByteSwap) + { + addrOffset = 2; + } + break; + + case (4U): + transferConfigRx.srcTransferSize = kEDMA_TransferSize4Bytes; + transferConfigRx.minorLoopBytes = 4; + break; + + default: + transferConfigRx.srcTransferSize = kEDMA_TransferSize1Bytes; + transferConfigRx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigRx.srcAddr = (uint32_t)rxAddr + addrOffset; + transferConfigRx.srcOffset = 0; + + transferConfigRx.majorLoopCounts = handle->readRegRemainingTimes; + + /* Store the initially configured eDMA minor byte transfer count into the DSPI handle */ + handle->nbytes = (uint8_t)transferConfigRx.minorLoopBytes; + + EDMA_SetTransferConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + &transferConfigRx, NULL); + EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel, + (uint32_t)kEDMA_MajorInterruptEnable); + EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle); + } + + /*Tx*/ + if (handle->txData != NULL) + { + EDMA_ResetChannel(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel); + if (isThereExtraTxBytes) + { + transferConfigTx.srcAddr = (uint32_t) & (transfer->txData[transfer->dataSize - bytesLastWrite]); + transferConfigTx.srcOffset = 1; + transferConfigTx.destOffset = 0; + transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; + addrOffset = 0; + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_edma_c_ref_1$ + */ + switch (bytesLastWrite) + { + case (1U): + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + addrOffset = 3; + } + break; + + case (2U): + transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigTx.minorLoopBytes = 2; + if (handle->isByteSwap) + { + addrOffset = 2; + } + break; + + default: + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigTx.destAddr = (uint32_t)txAddr + addrOffset; + transferConfigTx.majorLoopCounts = 1; + +#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4 + EDMA_TcdResetExt(handle->edmaRxRegToRxDataHandle->base, softwareTCD_extraBytes); + EDMA_TcdSetTransferConfigExt(handle->edmaRxRegToRxDataHandle->base, softwareTCD_extraBytes, + &transferConfigTx, NULL); +#else + EDMA_TcdReset(softwareTCD_extraBytes); + EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, NULL); +#endif + } + + transferConfigTx.srcAddr = (uint32_t)(handle->txData); + transferConfigTx.srcOffset = 1; + transferConfigTx.destOffset = 0; + transferConfigTx.srcTransferSize = kEDMA_TransferSize1Bytes; + addrOffset = 0; + /* + * $Branch Coverage Justification$ + * $ref fsl_lpspi_edma_c_ref_1$ + */ + switch (handle->bytesEachRead) + { + case (1U): + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + if (handle->isByteSwap) + { + addrOffset = 3; + } + break; + + case (2U): + transferConfigTx.destTransferSize = kEDMA_TransferSize2Bytes; + transferConfigTx.minorLoopBytes = 2; + + if (handle->isByteSwap) + { + addrOffset = 2; + } + break; + + case (4U): + transferConfigTx.destTransferSize = kEDMA_TransferSize4Bytes; + transferConfigTx.minorLoopBytes = 4; + break; + + default: + transferConfigTx.destTransferSize = kEDMA_TransferSize1Bytes; + transferConfigTx.minorLoopBytes = 1; + assert(false); + break; + } + + transferConfigTx.destAddr = (uint32_t)txAddr + addrOffset; + transferConfigTx.majorLoopCounts = handle->writeRegRemainingTimes; + + if (isThereExtraTxBytes) + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigTx, softwareTCD_extraBytes); + } + else + { + EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel, + &transferConfigTx, NULL); + } + EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle); + mask |= (uint32_t)kLPSPI_TxDmaEnable; + } + + LPSPI_EnableDMA(base, mask); + + return kStatus_Success; +} + +static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle, + void *g_lpspiEdmaPrivateHandle, + bool transferDone, + uint32_t tcds) +{ + assert(edmaHandle != NULL); + assert(g_lpspiEdmaPrivateHandle != NULL); + + uint32_t readData; + status_t callbackStatus = kStatus_Success; + + lpspi_slave_edma_private_handle_t *lpspiEdmaPrivateHandle; + + lpspiEdmaPrivateHandle = (lpspi_slave_edma_private_handle_t *)g_lpspiEdmaPrivateHandle; + + size_t rxRemainingByteCount = lpspiEdmaPrivateHandle->handle->rxRemainingByteCount; + uint8_t bytesLastRead = lpspiEdmaPrivateHandle->handle->bytesLastRead; + bool isByteSwap = lpspiEdmaPrivateHandle->handle->isByteSwap; + + LPSPI_DisableDMA(lpspiEdmaPrivateHandle->base, (uint32_t)kLPSPI_TxDmaEnable | (uint32_t)kLPSPI_RxDmaEnable); + + if (!transferDone) + { + callbackStatus = kStatus_LPSPI_Error; + } + + /* + * $Branch Coverage Justification$ + * When there are extra bytes, the slave will not receive the extra bytes,The while here will not stop.(will + * improve) + */ + if (lpspiEdmaPrivateHandle->handle->isThereExtraRxBytes) + { + while (LPSPI_GetRxFifoCount(lpspiEdmaPrivateHandle->base) == 0U) + { + } + readData = LPSPI_ReadData(lpspiEdmaPrivateHandle->base); + + if (lpspiEdmaPrivateHandle->handle->rxData != NULL) + { + LPSPI_SeparateEdmaReadData(&(lpspiEdmaPrivateHandle->handle->rxData[rxRemainingByteCount - bytesLastRead]), + readData, bytesLastRead, isByteSwap); + } + } + + lpspiEdmaPrivateHandle->handle->state = (uint8_t)kLPSPI_Idle; + + if (lpspiEdmaPrivateHandle->handle->callback != NULL) + { + lpspiEdmaPrivateHandle->handle->callback(lpspiEdmaPrivateHandle->base, lpspiEdmaPrivateHandle->handle, + callbackStatus, lpspiEdmaPrivateHandle->handle->userData); + } +} + +/*! + * brief LPSPI slave aborts a transfer which is using eDMA. + * + * This function aborts a transfer which is using eDMA. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_slave_edma_handle_t structure which stores the transfer state. + */ +void LPSPI_SlaveTransferAbortEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle) +{ + assert(handle != NULL); + + LPSPI_DisableDMA(base, (uint32_t)kLPSPI_RxDmaEnable | (uint32_t)kLPSPI_TxDmaEnable); + + EDMA_AbortTransfer(handle->edmaRxRegToRxDataHandle); + EDMA_AbortTransfer(handle->edmaTxDataToTxRegHandle); + + handle->state = (uint8_t)kLPSPI_Idle; +} + +/*! + * brief Gets the slave eDMA transfer remaining bytes. + * + * This function gets the slave eDMA transfer remaining bytes. + * + * param base LPSPI peripheral base address. + * param handle pointer to lpspi_slave_edma_handle_t structure which stores the transfer state. + * param count Number of bytes transferred so far by the eDMA transaction. + * return status of status_t. + */ +status_t LPSPI_SlaveTransferGetCountEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *handle, size_t *count) +{ + assert(handle != NULL); + + if (NULL == count) + { + return kStatus_InvalidArgument; + } + + /* Catch when there is not an active transfer. */ + if (handle->state != (uint8_t)kLPSPI_Busy) + { + *count = 0; + return kStatus_NoTransferInProgress; + } + + size_t remainingByte; + + remainingByte = + (uint32_t)handle->nbytes * EDMA_GetRemainingMajorLoopCount(handle->edmaRxRegToRxDataHandle->base, + handle->edmaRxRegToRxDataHandle->channel); + + *count = handle->totalByteCount - remainingByte; + + return kStatus_Success; +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpspi_edma.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpspi_edma.h new file mode 100644 index 00000000000..9e193393d67 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpspi_edma.h @@ -0,0 +1,353 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LPSPI_EDMA_H_ +#define FSL_LPSPI_EDMA_H_ + +#include "fsl_lpspi.h" +#include "fsl_edma.h" + +/*! + * @addtogroup lpspi_edma_driver + * @{ + */ + +/*********************************************************************************************************************** + * Definitions + **********************************************************************************************************************/ +/*! @name Driver version */ +/*! @{ */ +/*! @brief LPSPI EDMA driver version. */ +#define FSL_LPSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 4)) + +/*! @brief DMA max transfer size */ +#define DMA_MAX_TRANSFER_COUNT 0x7FFFU +/*! @} */ + +/*! + * @brief Forward declaration of the _lpspi_master_edma_handle typedefs. + */ +typedef struct _lpspi_master_edma_handle lpspi_master_edma_handle_t; + +/*! + * @brief Forward declaration of the _lpspi_slave_edma_handle typedefs. + */ +typedef struct _lpspi_slave_edma_handle lpspi_slave_edma_handle_t; + +/*! + * @brief Completion callback function pointer type. + * + * @param base LPSPI peripheral base address. + * @param handle Pointer to the handle for the LPSPI master. + * @param status Success or error code describing whether the transfer completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*lpspi_master_edma_transfer_callback_t)(LPSPI_Type *base, + lpspi_master_edma_handle_t *handle, + status_t status, + void *userData); +/*! + * @brief Completion callback function pointer type. + * + * @param base LPSPI peripheral base address. + * @param handle Pointer to the handle for the LPSPI slave. + * @param status Success or error code describing whether the transfer completed. + * @param userData Arbitrary pointer-dataSized value passed from the application. + */ +typedef void (*lpspi_slave_edma_transfer_callback_t)(LPSPI_Type *base, + lpspi_slave_edma_handle_t *handle, + status_t status, + void *userData); + +/*! @brief LPSPI master eDMA transfer handle structure used for transactional API. */ +struct _lpspi_master_edma_handle +{ + volatile bool isPcsContinuous; /*!< Is PCS continuous in transfer. */ + + volatile bool isByteSwap; /*!< A flag that whether should byte swap. */ + + volatile uint8_t fifoSize; /*!< FIFO dataSize. */ + + volatile uint8_t rxWatermark; /*!< Rx watermark. */ + + volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */ + volatile uint8_t bytesEachRead; /*!< Bytes for each read RDR. */ + + volatile uint8_t bytesLastRead; /*!< Bytes for last read RDR. */ + volatile bool isThereExtraRxBytes; /*!< Is there extra RX byte. */ + + const uint8_t *volatile txData; /*!< Send buffer. */ + uint8_t *volatile rxData; /*!< Receive buffer. */ + volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/ + volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/ + + volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */ + volatile uint32_t readRegRemainingTimes; /*!< Read RDR register remaining times. */ + + uint32_t totalByteCount; /*!< Number of transfer bytes*/ + + edma_tcd_t *lastTimeTCD; /*!< Pointer to the lastTime TCD*/ + bool isMultiDMATransmit; /*!< Is there multi DMA transmit*/ + volatile uint8_t dmaTransmitTime; /*!< DMA Transfer times. */ + uint32_t lastTimeDataBytes; /*!< DMA transmit last Time data Bytes */ + + uint32_t dataBytesEveryTime; /*!< Bytes in a time for DMA transfer, default is DMA_MAX_TRANSFER_COUNT */ + + edma_transfer_config_t transferConfigRx; /*!< Config of DMA rx channel.*/ + edma_transfer_config_t transferConfigTx; /*!< Config of DMA tx channel.*/ + uint32_t txBuffIfNull; /*!< Used if there is not txData for DMA purpose.*/ + uint32_t rxBuffIfNull; /*!< Used if there is not rxData for DMA purpose.*/ + + uint32_t transmitCommand; /*!< Used to write TCR for DMA purpose.*/ + + volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/ + + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + + lpspi_master_edma_transfer_callback_t callback; /*!< Completion callback. */ + void *userData; /*!< Callback user data. */ + + edma_handle_t *edmaRxRegToRxDataHandle; /*!CSR = (LPTMR_CSR_TMS(config->timerMode) | LPTMR_CSR_TFC(config->enableFreeRunning) | + LPTMR_CSR_TPP(config->pinPolarity) | LPTMR_CSR_TPS(config->pinSelect)); + + /* Configure the prescale value and clock source */ + base->PSR = (LPTMR_PSR_PRESCALE(config->value) | LPTMR_PSR_PBYP(config->bypassPrescaler) | + LPTMR_PSR_PCS(config->prescalerClockSource)); +} + +/*! + * brief Gates the LPTMR clock. + * + * param base LPTMR peripheral base address + */ +void LPTMR_Deinit(LPTMR_Type *base) +{ + /* Disable the LPTMR and reset the internal logic */ + base->CSR &= ~LPTMR_CSR_TEN_MASK; + +#if defined(LPTMR_CLOCKS) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPTMR_GetInstance(base); + + /* Gate the LPTMR clock*/ + CLOCK_DisableClock(s_lptmrClocks[instance]); +#if defined(LPTMR_PERIPH_CLOCKS) + CLOCK_DisableClock(s_lptmrPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* LPTMR_CLOCKS */ +} + +/*! + * brief Fills in the LPTMR configuration structure with default settings. + * + * The default values are as follows. + * code + * config->timerMode = kLPTMR_TimerModeTimeCounter; + * config->pinSelect = kLPTMR_PinSelectInput_0; + * config->pinPolarity = kLPTMR_PinPolarityActiveHigh; + * config->enableFreeRunning = false; + * config->bypassPrescaler = true; + * config->prescalerClockSource = kLPTMR_PrescalerClock_1; + * config->value = kLPTMR_Prescale_Glitch_0; + * endcode + * param config A pointer to the LPTMR configuration structure. + */ +void LPTMR_GetDefaultConfig(lptmr_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* Use time counter mode */ + config->timerMode = kLPTMR_TimerModeTimeCounter; + /* Use input 0 as source in pulse counter mode */ + config->pinSelect = kLPTMR_PinSelectInput_0; + /* Pulse input pin polarity is active-high */ + config->pinPolarity = kLPTMR_PinPolarityActiveHigh; + /* Counter resets whenever TCF flag is set */ + config->enableFreeRunning = false; + /* Bypass the prescaler */ + config->bypassPrescaler = true; + /* LPTMR clock source */ +#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT) && \ + FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT) + config->prescalerClockSource = kLPTMR_PrescalerClock_1; +#elif !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT) && \ + FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT) + config->prescalerClockSource = kLPTMR_PrescalerClock_0; +#elif !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT) && \ + FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT) + config->prescalerClockSource = kLPTMR_PrescalerClock_2; +#elif !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT) && \ + FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT) + config->prescalerClockSource = kLPTMR_PrescalerClock_3; +#else +#error No valid source +#endif + + /* Divide the prescaler clock by 2 */ + config->value = kLPTMR_Prescale_Glitch_0; +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lptmr.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lptmr.h new file mode 100644 index 00000000000..b8e473120c5 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lptmr.h @@ -0,0 +1,384 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017, 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LPTMR_H_ +#define FSL_LPTMR_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lptmr + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! Driver Version */ +#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/*! @} */ + +/*! @brief LPTMR pin selection used in pulse counter mode.*/ +typedef enum _lptmr_pin_select +{ + kLPTMR_PinSelectInput_0 = 0x0U, /*!< Pulse counter input 0 is selected */ + kLPTMR_PinSelectInput_1 = 0x1U, /*!< Pulse counter input 1 is selected */ + kLPTMR_PinSelectInput_2 = 0x2U, /*!< Pulse counter input 2 is selected */ + kLPTMR_PinSelectInput_3 = 0x3U /*!< Pulse counter input 3 is selected */ +} lptmr_pin_select_t; + +/*! @brief LPTMR pin polarity used in pulse counter mode.*/ +typedef enum _lptmr_pin_polarity +{ + kLPTMR_PinPolarityActiveHigh = 0x0U, /*!< Pulse Counter input source is active-high */ + kLPTMR_PinPolarityActiveLow = 0x1U /*!< Pulse Counter input source is active-low */ +} lptmr_pin_polarity_t; + +/*! @brief LPTMR timer mode selection.*/ +typedef enum _lptmr_timer_mode +{ + kLPTMR_TimerModeTimeCounter = 0x0U, /*!< Time Counter mode */ + kLPTMR_TimerModePulseCounter = 0x1U /*!< Pulse Counter mode */ +} lptmr_timer_mode_t; + +/*! @brief LPTMR prescaler/glitch filter values*/ +typedef enum _lptmr_prescaler_glitch_value +{ + kLPTMR_Prescale_Glitch_0 = 0x0U, /*!< Prescaler divide 2, glitch filter does not support this setting */ + kLPTMR_Prescale_Glitch_1 = 0x1U, /*!< Prescaler divide 4, glitch filter 2 */ + kLPTMR_Prescale_Glitch_2 = 0x2U, /*!< Prescaler divide 8, glitch filter 4 */ + kLPTMR_Prescale_Glitch_3 = 0x3U, /*!< Prescaler divide 16, glitch filter 8 */ + kLPTMR_Prescale_Glitch_4 = 0x4U, /*!< Prescaler divide 32, glitch filter 16 */ + kLPTMR_Prescale_Glitch_5 = 0x5U, /*!< Prescaler divide 64, glitch filter 32 */ + kLPTMR_Prescale_Glitch_6 = 0x6U, /*!< Prescaler divide 128, glitch filter 64 */ + kLPTMR_Prescale_Glitch_7 = 0x7U, /*!< Prescaler divide 256, glitch filter 128 */ + kLPTMR_Prescale_Glitch_8 = 0x8U, /*!< Prescaler divide 512, glitch filter 256 */ + kLPTMR_Prescale_Glitch_9 = 0x9U, /*!< Prescaler divide 1024, glitch filter 512*/ + kLPTMR_Prescale_Glitch_10 = 0xAU, /*!< Prescaler divide 2048 glitch filter 1024 */ + kLPTMR_Prescale_Glitch_11 = 0xBU, /*!< Prescaler divide 4096, glitch filter 2048 */ + kLPTMR_Prescale_Glitch_12 = 0xCU, /*!< Prescaler divide 8192, glitch filter 4096 */ + kLPTMR_Prescale_Glitch_13 = 0xDU, /*!< Prescaler divide 16384, glitch filter 8192 */ + kLPTMR_Prescale_Glitch_14 = 0xEU, /*!< Prescaler divide 32768, glitch filter 16384 */ + kLPTMR_Prescale_Glitch_15 = 0xFU /*!< Prescaler divide 65536, glitch filter 32768 */ +} lptmr_prescaler_glitch_value_t; + +/*! + * @brief LPTMR prescaler/glitch filter clock select. + * @note Clock connections are SoC-specific + */ +typedef enum _lptmr_prescaler_clock_select +{ +#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT) && \ + FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT) + kLPTMR_PrescalerClock_0 = 0x0U, /*!< Prescaler/glitch filter clock 0 selected. */ +#endif + +#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT) && \ + FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT) + kLPTMR_PrescalerClock_1 = 0x1U, /*!< Prescaler/glitch filter clock 1 selected. */ +#endif /* FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT */ + +#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT) && \ + FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT) + kLPTMR_PrescalerClock_2 = 0x2U, /*!< Prescaler/glitch filter clock 2 selected. */ +#endif + +#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT) && \ + FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT) + kLPTMR_PrescalerClock_3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */ +#endif /* FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT */ +} lptmr_prescaler_clock_select_t; + +/*! @brief List of the LPTMR interrupts */ +typedef enum _lptmr_interrupt_enable +{ + kLPTMR_TimerInterruptEnable = LPTMR_CSR_TIE_MASK, /*!< Timer interrupt enable */ +} lptmr_interrupt_enable_t; + +/*! @brief List of the LPTMR status flags */ +typedef enum _lptmr_status_flags +{ + kLPTMR_TimerCompareFlag = LPTMR_CSR_TCF_MASK, /*!< Timer compare flag */ +} lptmr_status_flags_t; + +/*! + * @brief LPTMR config structure + * + * This structure holds the configuration settings for the LPTMR peripheral. To initialize this + * structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a + * pointer to your configuration structure instance. + * + * The configuration struct can be made constant so it resides in flash. + */ +typedef struct _lptmr_config +{ + lptmr_timer_mode_t timerMode; /*!< Time counter mode or pulse counter mode */ + lptmr_pin_select_t pinSelect; /*!< LPTMR pulse input pin select; used only in pulse counter mode */ + lptmr_pin_polarity_t pinPolarity; /*!< LPTMR pulse input pin polarity; used only in pulse counter mode */ + bool enableFreeRunning; /*!< True: enable free running, counter is reset on overflow + False: counter is reset when the compare flag is set */ + bool bypassPrescaler; /*!< True: bypass prescaler; false: use clock from prescaler */ + lptmr_prescaler_clock_select_t prescalerClockSource; /*!< LPTMR clock source */ + lptmr_prescaler_glitch_value_t value; /*!< Prescaler or glitch filter value */ +} lptmr_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the LPTMR clock and configures the peripheral for a basic operation. + * + * @note This API should be called at the beginning of the application using the LPTMR driver. + * + * @param base LPTMR peripheral base address + * @param config A pointer to the LPTMR configuration structure. + */ +void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config); + +/*! + * @brief Gates the LPTMR clock. + * + * @param base LPTMR peripheral base address + */ +void LPTMR_Deinit(LPTMR_Type *base); + +/*! + * @brief Fills in the LPTMR configuration structure with default settings. + * + * The default values are as follows. + * @code + * config->timerMode = kLPTMR_TimerModeTimeCounter; + * config->pinSelect = kLPTMR_PinSelectInput_0; + * config->pinPolarity = kLPTMR_PinPolarityActiveHigh; + * config->enableFreeRunning = false; + * config->bypassPrescaler = true; + * config->prescalerClockSource = kLPTMR_PrescalerClock_1; + * config->value = kLPTMR_Prescale_Glitch_0; + * @endcode + * @param config A pointer to the LPTMR configuration structure. + */ +void LPTMR_GetDefaultConfig(lptmr_config_t *config); + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected LPTMR interrupts. + * + * @param base LPTMR peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::lptmr_interrupt_enable_t + */ +static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask) +{ + uint32_t reg = base->CSR; + + /* Clear the TCF bit so that we don't clear this w1c bit when writing back */ + reg &= ~(LPTMR_CSR_TCF_MASK); + reg |= mask; + base->CSR = reg; +} + +/*! + * @brief Disables the selected LPTMR interrupts. + * + * @param base LPTMR peripheral base address + * @param mask The interrupts to disable. This is a logical OR of members of the + * enumeration ::lptmr_interrupt_enable_t. + */ +static inline void LPTMR_DisableInterrupts(LPTMR_Type *base, uint32_t mask) +{ + uint32_t reg = base->CSR; + + /* Clear the TCF bit so that we don't clear this w1c bit when writing back */ + reg &= ~(LPTMR_CSR_TCF_MASK); + reg &= ~mask; + base->CSR = reg; +} + +/*! + * @brief Gets the enabled LPTMR interrupts. + * + * @param base LPTMR peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::lptmr_interrupt_enable_t + */ +static inline uint32_t LPTMR_GetEnabledInterrupts(LPTMR_Type *base) +{ + return (base->CSR & LPTMR_CSR_TIE_MASK); +} + +/*! @}*/ + +#if defined(FSL_FEATURE_LPTMR_HAS_CSR_TDRE) && (FSL_FEATURE_LPTMR_HAS_CSR_TDRE) +/*! + * @brief Enable or disable timer DMA request + * + * @param base base LPTMR peripheral base address + * @param enable Switcher of timer DMA feature. "true" means to enable, "false" means to disable. + */ +static inline void LPTMR_EnableTimerDMA(LPTMR_Type *base, bool enable) +{ + if (enable) + { + base->CSR |= LPTMR_CSR_TDRE_MASK; + } + else + { + base->CSR &= ~(LPTMR_CSR_TDRE_MASK); + } +} +#endif /* FSL_FEATURE_LPTMR_HAS_CSR_TDRE */ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the LPTMR status flags. + * + * @param base LPTMR peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::lptmr_status_flags_t + */ +static inline uint32_t LPTMR_GetStatusFlags(LPTMR_Type *base) +{ + return (base->CSR & LPTMR_CSR_TCF_MASK); +} + +/*! + * @brief Clears the LPTMR status flags. + * + * @param base LPTMR peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::lptmr_status_flags_t. + */ +static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask) +{ + base->CSR |= mask; +} + +/*! @}*/ + +/*! + * @name Read and write the timer period + * @{ + */ + +/*! + * @brief Sets the timer period in units of count. + * + * Timers counts from 0 until it equals the count value set here. The count value is written to + * the CMR register. + * + * @note + * 1. The TCF flag is set with the CNR equals the count provided here and then increments. + * 2. Call the utility macros provided in the fsl_common.h to convert to ticks. + * + * @param base LPTMR peripheral base address + * @param ticks A timer period in units of ticks, which should be equal or greater than 1. + */ +static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint32_t ticks) +{ + assert(ticks > 0U); + base->CMR = LPTMR_CMR_COMPARE(ticks - 1U); +} + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value in a range from 0 to a + * timer period. + * + * @note Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec. + * + * @param base LPTMR peripheral base address + * + * @return The current counter value in ticks + */ +static inline uint32_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base) +{ + /* Must first write any value to the CNR. This synchronizes and registers the current value + * of the CNR into a temporary register which can then be read + */ + base->CNR = 0U; + return (uint32_t)((base->CNR & LPTMR_CNR_COUNTER_MASK) >> LPTMR_CNR_COUNTER_SHIFT); +} + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the timer. + * + * After calling this function, the timer counts up to the CMR register value. + * Each time the timer reaches the CMR value and then increments, it generates a + * trigger pulse and sets the timeout interrupt flag. An interrupt is also + * triggered if the timer interrupt is enabled. + * + * @param base LPTMR peripheral base address + */ +static inline void LPTMR_StartTimer(LPTMR_Type *base) +{ + uint32_t reg = base->CSR; + + /* Clear the TCF bit to avoid clearing the w1c bit when writing back. */ + reg &= ~(LPTMR_CSR_TCF_MASK); + reg |= LPTMR_CSR_TEN_MASK; + base->CSR = reg; +} + +/*! + * @brief Stops the timer. + * + * This function stops the timer and resets the timer's counter register. + * + * @param base LPTMR peripheral base address + */ +static inline void LPTMR_StopTimer(LPTMR_Type *base) +{ + uint32_t reg = base->CSR; + + /* Clear the TCF bit to avoid clearing the w1c bit when writing back. */ + reg &= ~(LPTMR_CSR_TCF_MASK); + reg &= ~LPTMR_CSR_TEN_MASK; + base->CSR = reg; +} + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_LPTMR_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpuart.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpuart.c new file mode 100644 index 00000000000..5e8de5a894b --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpuart.c @@ -0,0 +1,2742 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpuart.h" + +/* + * $Coverage Justification Reference$ + * + * $Justification fsl_lpuart_c_ref_1$ + * (osr > 3) (false) can't be not covered, because osr(osrTemp) is increased from 4U. + * + * $Justification fsl_lpuart_c_ref_2$ + * The flag is cleared successfully during test. + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpuart" +#endif + +/* LPUART transfer state. */ +enum +{ + kLPUART_TxIdle, /*!< TX idle. */ + kLPUART_TxBusy, /*!< TX busy. */ + kLPUART_RxIdle, /*!< RX idle. */ + kLPUART_RxBusy /*!< RX busy. */ +}; + +#if defined(LPUART_RSTS) +#define LPUART_RESETS_ARRAY LPUART_RSTS +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Check whether the RX ring buffer is full. + * + * @userData handle LPUART handle pointer. + * @retval true RX ring buffer is full. + * @retval false RX ring buffer is not full. + */ +static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Write to TX register using non-blocking method. + * + * This function writes data to the TX register directly, upper layer must make + * sure the TX register is empty or TX FIFO has empty room before calling this function. + * + * @note This function does not check whether all the data has been sent out to bus, + * so before disable TX, check kLPUART_TransmissionCompleteFlag to ensure the TX is + * finished. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the buffer to be sent. + */ +static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length); +/*! + * @brief Write to TX register using non-blocking method in 9bit or 10bit mode. + * + * The 10bit of data will be writen to TX register DATA. + * Please make sure data 10bit is valid and other bit is 0. + * + * @note This function only support 9bit or 10bit transfer. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the buffer to be sent. + */ +static void LPUART_WriteNonBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length); + +/*! + * @brief Read RX register using non-blocking method. + * + * This function reads data from the TX register directly, upper layer must make + * sure the RX register is full or TX FIFO has data before calling this function. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + */ +static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length); +/*! + * @brief Read RX register using non-blocking method in 9bit or 10bit mode. + * + * This function reads 10bit data from the RX register directly and stores to 16bit data. + * + * @note This function only support 9bit or 10bit transfer. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + */ +static void LPUART_ReadNonBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length); +/*! + * @brief LPUART_TransferHandleIDLEIsReady handle function. + * This function handles when IDLE is ready. + * + * @param base LPUART peripheral base address. + * @param irqHandle LPUART handle pointer. + */ +static void LPUART_TransferHandleIDLEReady(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief LPUART_TransferHandleReceiveDataIsFull handle function. + * This function handles when receive data is full. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +static void LPUART_TransferHandleReceiveDataFull(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief LPUART_TransferHandleSendDataIsEmpty handle function. + * This function handles when send data is empty. + * + * @param base LPUART peripheral base address. + * @param irqHandle LPUART handle pointer. + */ +static void LPUART_TransferHandleSendDataEmpty(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief LPUART_TransferHandleTransmissionIsComplete handle function. + * This function handles Transmission complete and the interrupt is enabled. + * + * @param base LPUART peripheral base address. + * @param irqHandle LPUART handle pointer. + */ +static void LPUART_TransferHandleTransmissionComplete(LPUART_Type *base, lpuart_handle_t *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if defined(LPUART_BASE_PTRS_NS) +static LPUART_Type *const s_lpuartBases_ns[] = LPUART_BASE_PTRS_NS; +#endif +/* Array of LPUART peripheral base address. */ +static LPUART_Type *const s_lpuartBases[] = LPUART_BASE_PTRS; +/* Array of LPUART handle. */ +void *s_lpuartHandle[ARRAY_SIZE(s_lpuartBases)]; +/* Array of LPUART IRQ number. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +static const IRQn_Type s_lpuartRxIRQ[] = LPUART_RX_IRQS; +const IRQn_Type s_lpuartTxIRQ[] = LPUART_TX_IRQS; +#else +const IRQn_Type s_lpuartIRQ[] = LPUART_RX_TX_IRQS; +#endif +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of LPUART clock name. */ +static const clock_ip_name_t s_lpuartClock[] = LPUART_CLOCKS; + +#if defined(LPUART_PERIPH_CLOCKS) +/* Array of LPUART functional clock name. */ +static const clock_ip_name_t s_lpuartPeriphClocks[] = LPUART_PERIPH_CLOCKS; +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* LPUART ISR for transactional APIs. */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +lpuart_isr_t s_lpuartIsr[ARRAY_SIZE(s_lpuartBases)] = {[0 ...(ARRAY_SIZE(s_lpuartBases) - 1)] = + (lpuart_isr_t)DefaultISR}; +#else +lpuart_isr_t s_lpuartIsr[ARRAY_SIZE(s_lpuartBases)]; +#endif + +#if defined(LPUART_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_lpuartResets[] = LPUART_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Get the LPUART instance from peripheral base address. + * + * param base LPUART peripheral base address. + * return LPUART instance. + */ +uint32_t LPUART_GetInstance(LPUART_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0U; instance < ARRAY_SIZE(s_lpuartBases); instance++) + { + if (s_lpuartBases[instance] == base) + { + return instance; + } + } +#if defined(LPUART_BASE_PTRS_NS) + /* Find the instance index from base address mappings. */ + for (instance = 0U; instance < ARRAY_SIZE(s_lpuartBases_ns); instance++) + { + if (s_lpuartBases_ns[instance] == base) + { + return instance; + } + } + assert(instance < ARRAY_SIZE(s_lpuartBases_ns)); +#else + assert(instance < ARRAY_SIZE(s_lpuartBases)); +#endif + + return instance; +} + +/*! + * brief Get the length of received data in RX ring buffer. + * + * userData handle LPUART handle pointer. + * return Length of received data in RX ring buffer. + */ +size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + size_t size; + size_t tmpRxRingBufferSize = handle->rxRingBufferSize; + uint16_t tmpRxRingBufferTail = handle->rxRingBufferTail; + uint16_t tmpRxRingBufferHead = handle->rxRingBufferHead; + + if (tmpRxRingBufferTail > tmpRxRingBufferHead) + { + size = ((size_t)tmpRxRingBufferHead + tmpRxRingBufferSize - (size_t)tmpRxRingBufferTail); + } + else + { + size = ((size_t)tmpRxRingBufferHead - (size_t)tmpRxRingBufferTail); + } + + return size; +} + +static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + bool full; + + if (LPUART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + return full; +} + +static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; + + /* The Non Blocking write data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + base->DATA = data[i]; + } +} +static void LPUART_WriteNonBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; + + /* The Non Blocking write data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + base->DATA = data[i]; + } +} + +static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); +#endif + + /* The Non Blocking read data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (isSevenDataBits) + { + data[i] = (uint8_t)(base->DATA & 0x7FU); + } + else + { + data[i] = (uint8_t)base->DATA; + } +#else + data[i] = (uint8_t)(base->DATA); +#endif + } +} + +static void LPUART_ReadNonBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length) +{ + assert(NULL != data); + + size_t i; + /* The Non Blocking read data API assume user have ensured there is enough space in + peripheral to write. */ + for (i = 0; i < length; i++) + { + data[i] = (uint16_t)(base->DATA & 0x03FFU); + } +} + +/*! + * brief Initializes an LPUART instance with the user configuration structure and the peripheral clock. + * + * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function + * to configure the configuration structure and get the default configuration. + * The example below shows how to use this API to configure the LPUART. + * code + * lpuart_config_t lpuartConfig; + * lpuartConfig.baudRate_Bps = 115200U; + * lpuartConfig.parityMode = kLPUART_ParityDisabled; + * lpuartConfig.dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig.isMsb = false; + * lpuartConfig.stopBitCount = kLPUART_OneStopBit; + * lpuartConfig.txFifoWatermark = 0; + * lpuartConfig.rxFifoWatermark = 1; + * LPUART_Init(LPUART1, &lpuartConfig, 20000000U); + * endcode + * + * param base LPUART peripheral base address. + * param config Pointer to a user-defined configuration structure. + * param srcClock_Hz LPUART clock source frequency in HZ. + * retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_Success LPUART initialize succeed + */ +status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz) +{ + assert(NULL != config); + assert(0U < config->baudRate_Bps); +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > config->txFifoWatermark); + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > config->rxFifoWatermark); +#endif + + status_t status = kStatus_Success; + uint32_t temp; + uint16_t sbr, sbrTemp; + uint8_t osr, osrTemp; + uint32_t tempDiff, calculatedBaud, baudDiff; + + /* This LPUART instantiation uses a slightly different baud rate calculation + * The idea is to use the best OSR (over-sampling rate) possible + * Note, OSR is typically hard-set to 16 in other LPUART instantiations + * loop to find the best OSR value possible, one that generates minimum baudDiff + * iterate through the rest of the supported values of OSR */ + + baudDiff = config->baudRate_Bps; + osr = 0U; + sbr = 0U; + for (osrTemp = 4U; osrTemp <= 32U; osrTemp++) + { + /* calculate the temporary sbr value */ + sbrTemp = (uint16_t)((srcClock_Hz * 2U / (config->baudRate_Bps * (uint32_t)osrTemp) + 1U) / 2U); + /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ + if (sbrTemp == 0U) + { + sbrTemp = 1U; + } + else if (sbrTemp > LPUART_BAUD_SBR_MASK) + { + sbrTemp = LPUART_BAUD_SBR_MASK; + } + else + { + /* Avoid MISRA 15.7 */ + } + /* Calculate the baud rate based on the temporary OSR and SBR values */ + calculatedBaud = (srcClock_Hz / ((uint32_t)osrTemp * (uint32_t)sbrTemp)); + tempDiff = calculatedBaud > config->baudRate_Bps ? (calculatedBaud - config->baudRate_Bps) : + (config->baudRate_Bps - calculatedBaud); + + if (tempDiff <= baudDiff) + { + baudDiff = tempDiff; + osr = osrTemp; /* update and store the best OSR value calculated */ + sbr = sbrTemp; /* update store the best SBR value calculated */ + } + } + + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculate OSR value */ + if (baudDiff > ((config->baudRate_Bps / 100U) * 3U)) + { + /* Unacceptable baud rate difference of more than 3%*/ + status = kStatus_LPUART_BaudrateNotSupport; + } + else + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + + uint32_t instance = LPUART_GetInstance(base); + + /* Enable lpuart clock */ + (void)CLOCK_EnableClock(s_lpuartClock[instance]); +#if defined(LPUART_PERIPH_CLOCKS) + (void)CLOCK_EnableClock(s_lpuartPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(LPUART_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_lpuartResets[LPUART_GetInstance(base)]); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL + /*Reset all internal logic and registers, except the Global Register */ + LPUART_SoftwareReset(base); +#else + /* Disable LPUART TX RX before setting. */ + base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); +#endif + + temp = base->BAUD; + + /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. + * If so, then "BOTHEDGE" sampling must be turned on */ + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_1$ + */ + if ((osr > 3U) && (osr < 8U)) + { + temp |= LPUART_BAUD_BOTHEDGE_MASK; + } + + /* program the osr value (bit value is one less than actual value) */ + temp &= ~LPUART_BAUD_OSR_MASK; + temp |= LPUART_BAUD_OSR((uint32_t)osr - 1UL); + + /* write the sbr value to the BAUD registers */ + temp &= ~LPUART_BAUD_SBR_MASK; + base->BAUD = temp | LPUART_BAUD_SBR(sbr); + + /* Set bit count and parity mode. */ + base->BAUD &= ~LPUART_BAUD_M10_MASK; + + temp = base->CTRL & ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK | + LPUART_CTRL_IDLECFG_MASK); + + temp |= (uint8_t)config->parityMode | LPUART_CTRL_IDLECFG(config->rxIdleConfig) | + LPUART_CTRL_ILT(config->rxIdleType); + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (kLPUART_SevenDataBits == config->dataBitsCount) + { + if (kLPUART_ParityDisabled != config->parityMode) + { + temp &= ~LPUART_CTRL_M7_MASK; /* Seven data bits and one parity bit */ + } + else + { + temp |= LPUART_CTRL_M7_MASK; + } + } + else +#endif + { + if (kLPUART_ParityDisabled != config->parityMode) + { + temp |= LPUART_CTRL_M_MASK; /* Eight data bits and one parity bit */ + } + } + + base->CTRL = temp; + +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + /* set stop bit per char */ + temp = base->BAUD & ~LPUART_BAUD_SBNS_MASK; + base->BAUD = temp | LPUART_BAUD_SBNS((uint8_t)config->stopBitCount); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Set tx/rx WATER watermark + Note: + Take care of the RX FIFO, RX interrupt request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + RX interrupt because the water mark is 2. + */ + base->WATER = (((uint32_t)(config->rxFifoWatermark) << 16U) | config->txFifoWatermark); + + /* Enable tx/rx FIFO */ + base->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK); + + /* Flush FIFO */ + base->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK); +#endif + + /* Clear all status flags */ + temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); + +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp |= LPUART_STAT_LBKDIF_MASK; +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + /* Set the CTS configuration/TX CTS source. */ + base->MODIR |= LPUART_MODIR_TXCTSC(config->txCtsConfig) | LPUART_MODIR_TXCTSSRC(config->txCtsSource); + if (true == config->enableRxRTS) + { + /* Enable the receiver RTS(request-to-send) function. */ + base->MODIR |= LPUART_MODIR_RXRTSE_MASK; + } + if (true == config->enableTxCTS) + { + /* Enable the CTS(clear-to-send) function. */ + base->MODIR |= LPUART_MODIR_TXCTSE_MASK; + } +#endif + + /* Set data bits order. */ + if (true == config->isMsb) + { + temp |= LPUART_STAT_MSBF_MASK; + } + else + { + temp &= ~LPUART_STAT_MSBF_MASK; + } + + base->STAT |= temp; + + /* Enable TX/RX base on configure structure. */ + temp = base->CTRL; + if (true == config->enableTx) + { + temp |= LPUART_CTRL_TE_MASK; + } + + if (true == config->enableRx) + { + temp |= LPUART_CTRL_RE_MASK; + } + + base->CTRL = temp; + } + + return status; +} +/*! + * brief Deinitializes a LPUART instance. + * + * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. + * + * param base LPUART peripheral base address. + */ +void LPUART_Deinit(LPUART_Type *base) +{ + uint32_t temp; + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Wait tx FIFO send out*/ + while (0U != ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXWATER_SHIFT)) + { + } +#endif + /* Wait last char shift out */ + while (0U == (base->STAT & LPUART_STAT_TC_MASK)) + { + } + + /* Clear all status flags */ + temp = (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_NF_MASK | + LPUART_STAT_FE_MASK | LPUART_STAT_PF_MASK); + +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp |= LPUART_STAT_LBKDIF_MASK; +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + temp |= (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK); +#endif + + base->STAT |= temp; + + /* Disable the module. */ + base->CTRL = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance = LPUART_GetInstance(base); + + /* Disable lpuart clock */ + (void)CLOCK_DisableClock(s_lpuartClock[instance]); + +#if defined(LPUART_PERIPH_CLOCKS) + (void)CLOCK_DisableClock(s_lpuartPeriphClocks[instance]); +#endif + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Gets the default configuration structure. + * + * This function initializes the LPUART configuration structure to a default value. The default + * values are: + * lpuartConfig->baudRate_Bps = 115200U; + * lpuartConfig->parityMode = kLPUART_ParityDisabled; + * lpuartConfig->dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig->isMsb = false; + * lpuartConfig->stopBitCount = kLPUART_OneStopBit; + * lpuartConfig->txFifoWatermark = 0; + * lpuartConfig->rxFifoWatermark = 1; + * lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; + * lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; + * lpuartConfig->enableTx = false; + * lpuartConfig->enableRx = false; + * + * param config Pointer to a configuration structure. + */ +void LPUART_GetDefaultConfig(lpuart_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->baudRate_Bps = 115200U; + config->parityMode = kLPUART_ParityDisabled; + config->dataBitsCount = kLPUART_EightDataBits; + config->isMsb = false; +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + config->stopBitCount = kLPUART_OneStopBit; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + config->txFifoWatermark = 0U; + config->rxFifoWatermark = 0U; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + config->enableRxRTS = false; + config->enableTxCTS = false; + config->txCtsConfig = kLPUART_CtsSampleAtStart; + config->txCtsSource = kLPUART_CtsSourcePin; +#endif + config->rxIdleType = kLPUART_IdleTypeStartBit; + config->rxIdleConfig = kLPUART_IdleCharacter1; + config->enableTx = false; + config->enableRx = false; +} + +/*! + * brief Sets the LPUART instance baudrate. + * + * This function configures the LPUART module baudrate. This function is used to update + * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. + * code + * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U); + * endcode + * + * param base LPUART peripheral base address. + * param baudRate_Bps LPUART baudrate to be set. + * param srcClock_Hz LPUART clock source frequency in HZ. + * retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source. + * retval kStatus_Success Set baudrate succeeded. + */ +status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) +{ + assert(0U < baudRate_Bps); + + status_t status = kStatus_Success; + uint32_t temp, oldCtrl; + uint16_t sbr, sbrTemp; + uint8_t osr, osrTemp; + uint32_t tempDiff, calculatedBaud, baudDiff; + + /* This LPUART instantiation uses a slightly different baud rate calculation + * The idea is to use the best OSR (over-sampling rate) possible + * Note, OSR is typically hard-set to 16 in other LPUART instantiations + * loop to find the best OSR value possible, one that generates minimum baudDiff + * iterate through the rest of the supported values of OSR */ + + baudDiff = baudRate_Bps; + osr = 0U; + sbr = 0U; + for (osrTemp = 4U; osrTemp <= 32U; osrTemp++) + { + /* calculate the temporary sbr value */ + sbrTemp = (uint16_t)((srcClock_Hz * 2U / (baudRate_Bps * (uint32_t)osrTemp) + 1U) / 2U); + /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/ + if (sbrTemp == 0U) + { + sbrTemp = 1U; + } + else if (sbrTemp > LPUART_BAUD_SBR_MASK) + { + sbrTemp = LPUART_BAUD_SBR_MASK; + } + else + { + /* Avoid MISRA 15.7 */ + } + /* Calculate the baud rate based on the temporary OSR and SBR values */ + calculatedBaud = srcClock_Hz / ((uint32_t)osrTemp * (uint32_t)sbrTemp); + + tempDiff = calculatedBaud > baudRate_Bps ? (calculatedBaud - baudRate_Bps) : (baudRate_Bps - calculatedBaud); + + if (tempDiff <= baudDiff) + { + baudDiff = tempDiff; + osr = osrTemp; /* update and store the best OSR value calculated */ + sbr = sbrTemp; /* update store the best SBR value calculated */ + } + } + + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculate OSR value */ + if (baudDiff < (uint32_t)((baudRate_Bps / 100U) * 3U)) + { + /* Store CTRL before disable Tx and Rx */ + oldCtrl = base->CTRL; + + /* Disable LPUART TX RX before setting. */ + base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK); + + temp = base->BAUD; + + /* Acceptable baud rate, check if OSR is between 4x and 7x oversampling. + * If so, then "BOTHEDGE" sampling must be turned on */ + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_1$ + */ + if ((osr > 3U) && (osr < 8U)) + { + temp |= LPUART_BAUD_BOTHEDGE_MASK; + } + + /* program the osr value (bit value is one less than actual value) */ + temp &= ~LPUART_BAUD_OSR_MASK; + temp |= LPUART_BAUD_OSR((uint32_t)osr - 1UL); + + /* write the sbr value to the BAUD registers */ + temp &= ~LPUART_BAUD_SBR_MASK; + base->BAUD = temp | LPUART_BAUD_SBR(sbr); + + /* Restore CTRL. */ + base->CTRL = oldCtrl; + } + else + { + /* Unacceptable baud rate difference of more than 3%*/ + status = kStatus_LPUART_BaudrateNotSupport; + } + + return status; +} + +/*! + * brief Enable 9-bit data mode for LPUART. + * + * This function set the 9-bit mode for LPUART module. The 9th bit is not used for parity thus can be modified by user. + * + * param base LPUART peripheral base address. + * param enable true to enable, flase to disable. + */ +void LPUART_Enable9bitMode(LPUART_Type *base, bool enable) +{ + assert(base != NULL); + + uint32_t temp = 0U; + + if (enable) + { + /* Set LPUART_CTRL_M for 9-bit mode, clear LPUART_CTRL_PE to disable parity. */ + temp = base->CTRL & ~((uint32_t)LPUART_CTRL_PE_MASK | (uint32_t)LPUART_CTRL_M_MASK); + temp |= (uint32_t)LPUART_CTRL_M_MASK; + base->CTRL = temp; + } + else + { + /* Clear LPUART_CTRL_M. */ + base->CTRL &= ~(uint32_t)LPUART_CTRL_M_MASK; + } +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + /* Clear LPUART_CTRL_M7 to disable 7-bit mode. */ + base->CTRL &= ~(uint32_t)LPUART_CTRL_M7_MASK; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT + /* Clear LPUART_BAUD_M10 to disable 10-bit mode. */ + base->BAUD &= ~(uint32_t)LPUART_BAUD_M10_MASK; +#endif +} + +/*! + * brief Transmit an address frame in 9-bit data mode. + * + * param base LPUART peripheral base address. + * param address LPUART slave address. + */ +void LPUART_SendAddress(LPUART_Type *base, uint8_t address) +{ + assert(base != NULL); + + uint32_t temp = base->DATA & 0xFFFFFC00UL; + temp |= ((uint32_t)address | (1UL << LPUART_DATA_R8T8_SHIFT)); + base->DATA = temp; +} + +/*! + * brief Enables LPUART interrupts according to a provided mask. + * + * This function enables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See the ref _lpuart_interrupt_enable. + * This examples shows how to enable TX empty interrupt and RX full interrupt: + * code + * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * endcode + * + * param base LPUART peripheral base address. + * param mask The interrupts to enable. Logical OR of ref _lpuart_interrupt_enable. + */ +void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask) +{ + uint32_t s_atomicOldInt; + /* Only consider the real interrupt enable bits. */ + mask &= (uint32_t)kLPUART_AllInterruptEnable; + + /* Check int enable bits in base->BAUD */ + uint32_t baudRegMask = 0UL; +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + baudRegMask |= ((mask << 8U) & LPUART_BAUD_LBKDIE_MASK); + /* Clear bit 7 from mask */ + mask &= ~(uint32_t)kLPUART_LinBreakInterruptEnable; +#endif + baudRegMask |= ((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK); + /* Clear bit 6 from mask */ + mask &= ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable; + + s_atomicOldInt = DisableGlobalIRQ(); + base->BAUD |= baudRegMask; + EnableGlobalIRQ(s_atomicOldInt); + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Check int enable bits in base->FIFO */ + + s_atomicOldInt = DisableGlobalIRQ(); + base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) | + (mask & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); + EnableGlobalIRQ(s_atomicOldInt); + + /* Clear bit 9 and bit 8 from mask */ + mask &= ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable); +#endif + + /* Set int enable bits in base->CTRL */ + s_atomicOldInt = DisableGlobalIRQ(); + base->CTRL |= mask; + EnableGlobalIRQ(s_atomicOldInt); +} + +/*! + * brief Disables LPUART interrupts according to a provided mask. + * + * This function disables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See ref _lpuart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * code + * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * endcode + * + * param base LPUART peripheral base address. + * param mask The interrupts to disable. Logical OR of ref _lpuart_interrupt_enable. + */ +void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask) +{ + uint32_t s_atomicOldInt; + /* Only consider the real interrupt enable bits. */ + mask &= (uint32_t)kLPUART_AllInterruptEnable; + + /* Clear int enable bits in base->BAUD */ + uint32_t baudRegMask = 0UL; +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + baudRegMask |= ((mask << 8U) & LPUART_BAUD_LBKDIE_MASK); + /* Clear bit 7 from mask */ + mask &= ~(uint32_t)kLPUART_LinBreakInterruptEnable; +#endif + baudRegMask |= ((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK); + /* Clear bit 6 from mask */ + mask &= ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable; + + s_atomicOldInt = DisableGlobalIRQ(); + base->BAUD &= ~baudRegMask; + EnableGlobalIRQ(s_atomicOldInt); + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Clear int enable bits in base->FIFO */ + + s_atomicOldInt = DisableGlobalIRQ(); + base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) & + ~(mask & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); + EnableGlobalIRQ(s_atomicOldInt); + /* Clear bit 9 and bit 8 from mask */ + mask &= ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable); +#endif + + /* Clear int enable bits in base->CTRL */ + s_atomicOldInt = DisableGlobalIRQ(); + base->CTRL &= ~mask; + EnableGlobalIRQ(s_atomicOldInt); +} + +/*! + * brief Gets enabled LPUART interrupts. + * + * This function gets the enabled LPUART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators ref _lpuart_interrupt_enable. To check + * a specific interrupt enable status, compare the return value with enumerators + * in ref _lpuart_interrupt_enable. + * For example, to check whether the TX empty interrupt is enabled: + * code + * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1); + * + * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * endcode + * + * param base LPUART peripheral base address. + * return LPUART interrupt flags which are logical OR of the enumerators in ref _lpuart_interrupt_enable. + */ +uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base) +{ + /* Check int enable bits in base->CTRL */ + uint32_t temp = (uint32_t)(base->CTRL & (uint32_t)kLPUART_AllInterruptEnable); + + /* Check int enable bits in base->BAUD */ + temp = (temp & ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable) | ((base->BAUD & LPUART_BAUD_RXEDGIE_MASK) >> 8U); +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + temp = (temp & ~(uint32_t)kLPUART_LinBreakInterruptEnable) | ((base->BAUD & LPUART_BAUD_LBKDIE_MASK) >> 8U); +#endif + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Check int enable bits in base->FIFO */ + temp = + (temp & ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable)) | + (base->FIFO & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK)); +#endif + + return temp; +} + +/*! + * brief Gets LPUART status flags. + * + * This function gets all LPUART status flags. The flags are returned as the logical + * OR value of the enumerators ref _lpuart_flags. To check for a specific status, + * compare the return value with enumerators in the ref _lpuart_flags. + * For example, to check whether the TX is empty: + * code + * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1)) + * { + * ... + * } + * endcode + * + * param base LPUART peripheral base address. + * return LPUART status flags which are ORed by the enumerators in the _lpuart_flags. + */ +uint32_t LPUART_GetStatusFlags(LPUART_Type *base) +{ + uint32_t temp; + temp = base->STAT; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + temp |= (base->FIFO & + (LPUART_FIFO_TXEMPT_MASK | LPUART_FIFO_RXEMPT_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) >> + 16U; +#endif + /* Only keeps the status bits */ + temp &= (uint32_t)kLPUART_AllFlags; + return temp; +} + +/*! + * brief Clears status flags with a provided mask. + * + * This function clears LPUART status flags with a provided mask. Automatically cleared flags + * can't be cleared by this function. + * Flags that can only cleared or set by hardware are: + * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, + * kLPUART_RxActiveFlag, kLPUART_NoiseErrorFlag, kLPUART_ParityErrorFlag, + * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag + * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. + * + * param base LPUART peripheral base address. + * param mask the status flags to be cleared. The user can use the enumerators in the + * _lpuart_status_flag_t to do the OR operation and get the mask. + * return 0 succeed, others failed. + * retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * retval kStatus_Success Status in the mask are cleared. + */ +status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask) +{ + uint32_t temp; + status_t status; + + /* Only deal with the clearable flags */ + mask &= (uint32_t)kLPUART_AllClearFlags; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Status bits in FIFO register */ + if ((mask & ((uint32_t)kLPUART_TxFifoOverflowFlag | (uint32_t)kLPUART_RxFifoUnderflowFlag)) != 0U) + { + /* Get the FIFO register value and mask the rx/tx FIFO flush bits and the status bits that can be W1C in case + they are written 1 accidentally. */ + temp = (uint32_t)base->FIFO; + temp &= (uint32_t)(~(LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK | LPUART_FIFO_TXOF_MASK | + LPUART_FIFO_RXUF_MASK)); + temp |= (mask << 16U) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK); + base->FIFO = temp; + } +#endif + /* Status bits in STAT register */ + /* First get the STAT register value and mask all the bits that not represent status, then OR with the status bit + * that is to be W1C */ + temp = (base->STAT & 0x3E000000UL) | mask; + base->STAT = temp; + /* If some flags still pending. */ + if (0U != (mask & LPUART_GetStatusFlags(base))) + { + status = kStatus_LPUART_FlagCannotClearManually; + } + else + { + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Writes to the transmitter register using a blocking method. + * + * This function polls the transmitter register, first waits for the register to be empty or TX FIFO to have room, + * and writes data to the transmitter buffer, then waits for the data to be sent out to bus. + * + * param base LPUART peripheral base address. + * param data Start address of the data to write. + * param length Size of the data to write. + * retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length) +{ + assert(NULL != data); + + const uint8_t *dataAddress = data; + size_t transferSize = length; + +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != transferSize) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & LPUART_STAT_TDRE_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->STAT & LPUART_STAT_TDRE_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_LPUART_Timeout; + } +#endif + base->DATA = *(dataAddress); + dataAddress++; + transferSize--; + } + /* Ensure all the data in the transmit buffer are sent out to bus. */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & LPUART_STAT_TC_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->STAT & LPUART_STAT_TC_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_LPUART_Timeout; + } +#endif + return kStatus_Success; +} +/*! + * brief Writes to the transmitter register using a blocking method in 9bit or 10bit mode. + * + * note This function only support 9bit or 10bit transfer. + * Please make sure only 10bit of data is valid and other bits are 0. + * + * param base LPUART peripheral base address. + * param data Start address of the data to write. + * param length Size of the data to write. + * retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length) +{ + assert(NULL != data); + + const uint16_t *dataAddress = data; + size_t transferSize = length; + +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != transferSize) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & LPUART_STAT_TDRE_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->STAT & LPUART_STAT_TDRE_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_LPUART_Timeout; + } +#endif + base->DATA = *(dataAddress); + dataAddress++; + transferSize--; + } + /* Ensure all the data in the transmit buffer are sent out to bus. */ +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & LPUART_STAT_TC_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->STAT & LPUART_STAT_TC_MASK)) +#endif + { + } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_LPUART_Timeout; + } +#endif + return kStatus_Success; +} + +/*! + * brief Reads the receiver data register using a blocking method. + * + * This function polls the receiver register, waits for the receiver register full or receiver FIFO + * has data, and reads data from the TX register. + * + * param base LPUART peripheral base address. + * param data Start address of the buffer to store the received data. + * param length Size of the buffer. + * retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length) +{ + assert(NULL != data); + + status_t status = kStatus_Success; + uint32_t statusFlag; + uint8_t *dataAddress = data; + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); +#endif + +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != (length--)) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + while (0U == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)) +#else + while (0U == (base->STAT & LPUART_STAT_RDRF_MASK)) +#endif + { +#if UART_RETRY_TIMES + if (0U == --waitTimes) + { + status = kStatus_LPUART_Timeout; + break; + } +#endif + statusFlag = LPUART_GetStatusFlags(base); + + if (0U != (statusFlag & (uint32_t)kLPUART_RxOverrunFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag)) ? + (kStatus_LPUART_RxHardwareOverrun) : + (kStatus_LPUART_FlagCannotClearManually)); + /* Other error flags(FE, NF, and PF) are prevented from setting once OR is set, no need to check other + * error flags*/ + break; + } + + if (0U != (statusFlag & (uint32_t)kLPUART_ParityErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_ParityErrorFlag)) ? + (kStatus_LPUART_ParityError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_FramingErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_FramingErrorFlag)) ? + (kStatus_LPUART_FramingError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_NoiseErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_NoiseErrorFlag)) ? + (kStatus_LPUART_NoiseError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + if (kStatus_Success != status) + { + break; + } + } + + if (kStatus_Success == status) + { +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (isSevenDataBits) + { + *(dataAddress) = (uint8_t)(base->DATA & 0x7FU); + dataAddress++; + } + else + { + *(dataAddress) = (uint8_t)base->DATA; + dataAddress++; + } +#else + *(dataAddress) = (uint8_t)base->DATA; + dataAddress++; +#endif + } + else + { + break; + } + } + + return status; +} +/*! + * brief Reads the receiver data register in 9bit or 10bit mode. + * + * note This function only support 9bit or 10bit transfer. + * + * param base LPUART peripheral base address. + * param data Start address of the buffer to store the received data by 16bit, only 10bit is valid. + * param length Size of the buffer. + * retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length) +{ + assert(NULL != data); + + status_t status = kStatus_Success; + uint32_t statusFlag; + uint16_t *dataAddress = data; + +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif + + while (0U != (length--)) + { +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + while (0U == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)) +#else + while (0U == (base->STAT & LPUART_STAT_RDRF_MASK)) +#endif + { +#if UART_RETRY_TIMES + if (0U == --waitTimes) + { + status = kStatus_LPUART_Timeout; + break; + } +#endif + statusFlag = LPUART_GetStatusFlags(base); + + if (0U != (statusFlag & (uint32_t)kLPUART_RxOverrunFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag)) ? + (kStatus_LPUART_RxHardwareOverrun) : + (kStatus_LPUART_FlagCannotClearManually)); + /* Other error flags(FE, NF, and PF) are prevented from setting once OR is set, no need to check other + * error flags*/ + break; + } + + if (0U != (statusFlag & (uint32_t)kLPUART_ParityErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_ParityErrorFlag)) ? + (kStatus_LPUART_ParityError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_FramingErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_FramingErrorFlag)) ? + (kStatus_LPUART_FramingError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + + if (0U != (statusFlag & (uint32_t)kLPUART_NoiseErrorFlag)) + { + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_c_ref_2$. + */ + status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_NoiseErrorFlag)) ? + (kStatus_LPUART_NoiseError) : + (kStatus_LPUART_FlagCannotClearManually)); + } + if (kStatus_Success != status) + { + break; + } + } + if (kStatus_Success == status) + { + *(dataAddress) = (uint16_t)(base->DATA & 0x03FFU); + dataAddress++; + } + else + { + break; + } + } + + return status; +} + +/*! + * brief Initializes the LPUART handle. + * + * This function initializes the LPUART handle, which can be used for other LPUART + * transactional APIs. Usually, for a specified LPUART instance, + * call this API once to get the initialized handle. + * + * The LPUART driver supports the "background" receiving, which means that user can set up + * an RX ring buffer optionally. Data received is stored into the ring buffer even when the + * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * The ring buffer is disabled if passing NULL as p ringBuffer. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param callback Callback function. + * param userData User data. + */ +void LPUART_TransferCreateHandle(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_callback_t callback, + void *userData) +{ + assert(NULL != handle); + + uint32_t instance; + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M_MASK) == 0U) && ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); +#endif + + /* Zero the handle. */ + (void)memset(handle, 0, sizeof(lpuart_handle_t)); + + /* Set the TX/RX state. */ + handle->rxState = (uint8_t)kLPUART_RxIdle; + handle->txState = (uint8_t)kLPUART_TxIdle; + + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + /* Initial seven data bits flag */ + handle->isSevenDataBits = isSevenDataBits; +#endif + handle->is16bitData = false; + + /* Get instance from peripheral base address. */ + instance = LPUART_GetInstance(base); + + /* Save the handle in global variables to support the double weak mechanism. */ + s_lpuartHandle[instance] = handle; + + s_lpuartIsr[instance] = LPUART_TransferHandleIRQ; + +/* Enable interrupt in NVIC. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ + (void)EnableIRQ(s_lpuartRxIRQ[instance]); + (void)EnableIRQ(s_lpuartTxIRQ[instance]); +#else + (void)EnableIRQ(s_lpuartIRQ[instance]); +#endif +} + +/*! + * brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * note When using RX ring buffer, one byte is reserved for internal use. In other + * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * param ringBufferSize size of the ring buffer. + */ +void LPUART_TransferStartRingBuffer(LPUART_Type *base, + lpuart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize) +{ + assert(NULL != handle); + assert(NULL != ringBuffer); + + /* Setup the ring buffer address */ + handle->rxRingBuffer = ringBuffer; + if (!handle->is16bitData) + { + handle->rxRingBufferSize = ringBufferSize; + } + else + { + handle->rxRingBufferSize = ringBufferSize / 2U; + } + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. */ + uint32_t irqMask = DisableGlobalIRQ(); + /* Enable the interrupt to accept the data when user need the ring buffer. */ + base->CTRL |= (uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); +} + +/*! + * brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + if (handle->rxState == (uint8_t)kLPUART_RxIdle) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. + */ + uint32_t irqMask = DisableGlobalIRQ(); + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + } + + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +/*! + * brief Transmits a buffer of data using the interrupt method. + * + * This function send data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data written to the transmitter register. When + * all data is written to the TX register in the ISR, the LPUART driver calls the callback + * function and passes the ref kStatus_LPUART_TxIdle as status parameter. + * + * note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written + * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, + * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART transfer structure, see #lpuart_transfer_t. + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(NULL != handle); + assert(NULL != xfer); + assert(NULL != xfer->txData); + assert(0U != xfer->dataSize); + + status_t status; + + /* Return error if current TX busy. */ + if ((uint8_t)kLPUART_TxBusy == handle->txState) + { + status = kStatus_LPUART_TxBusy; + } + else + { + if (!handle->is16bitData) + { + handle->txData = xfer->txData; + } + else + { + handle->txData16 = xfer->txData16; + } + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = (uint8_t)kLPUART_TxBusy; + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. + */ + uint32_t irqMask = DisableGlobalIRQ(); + /* Enable transmitter interrupt. */ + base->CTRL |= (uint32_t)LPUART_CTRL_TIE_MASK; + EnableGlobalIRQ(irqMask); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are not sent out. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. */ + uint32_t irqMask = DisableGlobalIRQ(); + base->CTRL &= ~(uint32_t)(LPUART_CTRL_TIE_MASK | LPUART_CTRL_TCIE_MASK); + EnableGlobalIRQ(irqMask); + + handle->txDataSize = 0; + handle->txState = (uint8_t)kLPUART_TxIdle; +} + +/*! + * brief Gets the number of bytes that have been sent out to bus. + * + * This function gets the number of bytes that have been sent out to bus by an interrupt method. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + status_t status = kStatus_Success; + size_t tmptxDataSize = handle->txDataSize; + + if ((uint8_t)kLPUART_TxIdle == handle->txState) + { + status = kStatus_NoTransferInProgress; + } + else + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + *count = handle->txDataSizeAll - tmptxDataSize - + ((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); +#else + if ((base->STAT & (uint32_t)kLPUART_TxDataRegEmptyFlag) != 0U) + { + *count = handle->txDataSizeAll - tmptxDataSize; + } + else + { + *count = handle->txDataSizeAll - tmptxDataSize - 1U; + } +#endif + } + + return status; +} + +/*! + * brief Receives a buffer of data using the interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function + * which returns without waiting to ensure that all data are received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough for read, the receive + * request is saved by the LPUART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the LPUART driver notifies the upper layer + * through a callback function and passes a status parameter ref kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. + * The 5 bytes are copied to xfer->data, which returns with the + * parameter p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is + * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART transfer structure, see #uart_transfer_t. + * param receivedBytes Bytes received from the ring buffer directly. + * retval kStatus_Success Successfully queue the transfer into the transmit queue. + * retval kStatus_LPUART_RxBusy Previous receive request is not finished. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_t *xfer, + size_t *receivedBytes) +{ + assert(NULL != handle); + assert(NULL != xfer); + assert(NULL != xfer->rxData); + assert(0U != xfer->dataSize); + + uint32_t i; + status_t status; + uint32_t irqMask; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to lpuart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to lpuart handle, receive data + to this empty space and trigger callback when finished. */ + + if ((uint8_t)kLPUART_RxBusy == handle->rxState) + { + status = kStatus_LPUART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0; + + /* If RX ring buffer is used. */ + if (NULL != handle->rxRingBuffer) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + /* Disable LPUART RX IRQ, protect ring buffer. */ + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = LPUART_TransferGetRxRingBufferLength(base, handle); + + if (0U != bytesToCopy) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + + bytesToReceive -= bytesToCopy; + + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + if (!handle->is16bitData) + { + xfer->rxData[bytesCurrentReceived] = handle->rxRingBuffer[handle->rxRingBufferTail]; + } + else + { + xfer->rxData16[bytesCurrentReceived] = handle->rxRingBuffer16[handle->rxRingBufferTail]; + } + bytesCurrentReceived++; + + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if (((uint32_t)handle->rxRingBufferTail + 1U) == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + + /* If ring buffer does not have enough data, still need to read more data. */ + if (0U != bytesToReceive) + { + /* No data in ring buffer, save the request to LPUART handle. */ + + if (!handle->is16bitData) + { + handle->rxData = &xfer->rxData[bytesCurrentReceived]; + } + else + { + handle->rxData16 = &xfer->rxData16[bytesCurrentReceived]; + } + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = xfer->dataSize; + handle->rxState = (uint8_t)kLPUART_RxBusy; + } + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + /* Re-enable LPUART RX IRQ. */ + base->CTRL |= (uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + + /* Call user callback since all data are received. */ + if (0U == bytesToReceive) + { + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + if (!handle->is16bitData) + { + handle->rxData = &xfer->rxData[bytesCurrentReceived]; + } + else + { + handle->rxData16 = &xfer->rxData16[bytesCurrentReceived]; + } + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = (uint8_t)kLPUART_RxBusy; + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + /* Enable RX interrupt. */ + base->CTRL |= (uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ILIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + } + + /* Return the how many bytes have read. */ + if (NULL != receivedBytes) + { + *receivedBytes = bytesCurrentReceived; + } + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + */ +void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle) +{ + assert(NULL != handle); + + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (NULL == handle->rxRingBuffer) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. + */ + uint32_t irqMask = DisableGlobalIRQ(); + /* Disable RX interrupt. */ + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ILIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + } + + handle->rxDataSize = 0U; + handle->rxState = (uint8_t)kLPUART_RxIdle; +} + +/*! + * brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + status_t status = kStatus_Success; + size_t tmprxDataSize = handle->rxDataSize; + + if ((uint8_t)kLPUART_RxIdle == handle->rxState) + { + status = kStatus_NoTransferInProgress; + } + else + { + *count = handle->rxDataSizeAll - tmprxDataSize; + } + + return status; +} + +static void LPUART_TransferHandleIDLEReady(LPUART_Type *base, lpuart_handle_t *handle) +{ + uint32_t irqMask; +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + uint8_t count; + uint8_t tempCount; + count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); + + while ((0U != handle->rxDataSize) && (0U != count)) + { + tempCount = (uint8_t)MIN(handle->rxDataSize, count); + /* Using non block API to read the data from the registers. */ + if (!handle->is16bitData) + { + LPUART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData = &handle->rxData[tempCount]; + } + else + { + LPUART_ReadNonBlocking16bit(base, handle->rxData16, tempCount); + handle->rxData16 = &handle->rxData16[tempCount]; + } + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If rxDataSize is 0, invoke rx idle callback.*/ + if (0U == (handle->rxDataSize)) + { + handle->rxState = (uint8_t)kLPUART_RxIdle; + + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } +#endif + /* Clear IDLE flag.*/ + base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_IDLE_MASK); + + /* If rxDataSize is 0, disable rx ready, overrun and idle line interrupt.*/ + if (0U == handle->rxDataSize) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ILIE_MASK | LPUART_CTRL_ORIE_MASK); + EnableGlobalIRQ(irqMask); + } + /* Invoke callback if callback is not NULL and rxDataSize is not 0. */ + else if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_IdleLineDetected, handle->userData); + } + else + { + /* Avoid MISRA 15.7 */ + } +} + +static void LPUART_TransferHandleReceiveDataFull(LPUART_Type *base, lpuart_handle_t *handle) +{ + uint8_t count; + uint8_t tempCount; + uint16_t tpmRxRingBufferHead; + uint32_t tpmData; + uint32_t irqMask; + + /* Get the size that can be stored into buffer for this interrupt. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = ((uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT)); +#else + count = 1; +#endif + + /* If handle->rxDataSize is not 0, first save data to handle->rxData. */ + while ((0U != handle->rxDataSize) && (0U != count)) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + tempCount = (uint8_t)MIN(handle->rxDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to read the data from the registers. */ + if (!handle->is16bitData) + { + LPUART_ReadNonBlocking(base, handle->rxData, tempCount); + handle->rxData = &handle->rxData[tempCount]; + } + else + { + LPUART_ReadNonBlocking16bit(base, handle->rxData16, tempCount); + handle->rxData16 = &handle->rxData16[tempCount]; + } + handle->rxDataSize -= tempCount; + count -= tempCount; + + /* If all the data required for upper layer is ready, trigger callback. */ + if (0U == handle->rxDataSize) + { + handle->rxState = (uint8_t)kLPUART_RxIdle; + + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxIdle, handle->userData); + } + } + } + + /* If use RX ring buffer, receive data to ring buffer. */ + if (NULL != handle->rxRingBuffer) + { + while (0U != count--) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (LPUART_TransferIsRxRingBufferFull(base, handle)) + { + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_RxRingBufferOverrun, handle->userData); + } + } + + /* If ring buffer is still full after callback function, the oldest data is overridden. */ + if (LPUART_TransferIsRxRingBufferFull(base, handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (((uint32_t)handle->rxRingBufferTail + 1U) == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + + /* Read data. */ + tpmRxRingBufferHead = handle->rxRingBufferHead; + tpmData = base->DATA; +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + if (handle->isSevenDataBits) + { + handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)(tpmData & 0x7FU); + } + else + { + if (!handle->is16bitData) + { + handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData; + } + else + { + handle->rxRingBuffer16[tpmRxRingBufferHead] = (uint16_t)(tpmData & 0x3FFU); + } + } +#else + if (!handle->is16bitData) + { + handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData; + } + else + { + handle->rxRingBuffer16[tpmRxRingBufferHead] = (uint16_t)(tpmData & 0x3FFU); + } +#endif + + /* Increase handle->rxRingBufferHead. */ + if (((uint32_t)handle->rxRingBufferHead + 1U) == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + /* If no receive requst pending, stop RX interrupt. */ + else if (0U == handle->rxDataSize) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + base->CTRL &= ~(uint32_t)(LPUART_CTRL_RIE_MASK | LPUART_CTRL_ORIE_MASK | LPUART_CTRL_ILIE_MASK); + EnableGlobalIRQ(irqMask); + } + else + { + /* Avoid MISRA C-2012 15.7 voiation */ + return; + } +} + +static void LPUART_TransferHandleSendDataEmpty(LPUART_Type *base, lpuart_handle_t *handle) +{ + uint8_t count; + uint8_t tempCount; + uint32_t irqMask; +/* Get the bytes that available at this moment. */ +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + count = (uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) - + (uint8_t)((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); +#else + count = 1; +#endif + + while ((0U != handle->txDataSize) && (0U != count)) + { +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + tempCount = (uint8_t)MIN(handle->txDataSize, count); +#else + tempCount = 1; +#endif + + /* Using non block API to write the data to the registers. */ + if (!handle->is16bitData) + { + LPUART_WriteNonBlocking(base, handle->txData, tempCount); + handle->txData = &handle->txData[tempCount]; + } + else + { + LPUART_WriteNonBlocking16bit(base, handle->txData16, tempCount); + handle->txData16 = &handle->txData16[tempCount]; + } + handle->txDataSize -= tempCount; + count -= tempCount; + + /* If all the data are written to data register, notify user with the callback, then TX finished. */ + if (0U == handle->txDataSize) + { + /* Disable and re-enable the global interrupt to protect the interrupt enable register during + * read-modify-wrte. */ + irqMask = DisableGlobalIRQ(); + /* Disable TX register empty interrupt and enable transmission completion interrupt. */ + base->CTRL = (base->CTRL & ~LPUART_CTRL_TIE_MASK) | LPUART_CTRL_TCIE_MASK; + EnableGlobalIRQ(irqMask); + } + } +} + +static void LPUART_TransferHandleTransmissionComplete(LPUART_Type *base, lpuart_handle_t *handle) +{ + uint32_t irqMask; + /* Set txState to idle only when all data has been sent out to bus. */ + handle->txState = (uint8_t)kLPUART_TxIdle; + + /* Disable and re-enable the global interrupt to protect the interrupt enable register during read-modify-wrte. + */ + irqMask = DisableGlobalIRQ(); + /* Disable transmission complete interrupt. */ + base->CTRL &= ~(uint32_t)LPUART_CTRL_TCIE_MASK; + EnableGlobalIRQ(irqMask); + + /* Trigger callback. */ + if (NULL != handle->callback) + { + handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData); + } +} + +/*! + * brief LPUART IRQ handle function. + * + * This function handles the LPUART transmit and receive IRQ request. + * + * param base LPUART peripheral base address. + * param irqHandle LPUART handle pointer. + */ +void LPUART_TransferHandleIRQ(LPUART_Type *base, void *irqHandle) +{ + assert(NULL != irqHandle); + + uint32_t status = LPUART_GetStatusFlags(base); + uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(base); + + lpuart_handle_t *handle = (lpuart_handle_t *)irqHandle; + + /* If RX overrun. */ + if ((uint32_t)kLPUART_RxOverrunFlag == ((uint32_t)kLPUART_RxOverrunFlag & status)) + { + /* Clear overrun flag, otherwise the RX does not work. */ + base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK); + + /* Trigger callback. */ + if (NULL != (handle->callback)) + { + handle->callback(base, handle, kStatus_LPUART_RxHardwareOverrun, handle->userData); + } + } + + /* If IDLE flag is set and the IDLE interrupt is enabled. */ + if ((0U != ((uint32_t)kLPUART_IdleLineFlag & status)) && + (0U != ((uint32_t)kLPUART_IdleLineInterruptEnable & enabledInterrupts))) + { + LPUART_TransferHandleIDLEReady(base, handle); + } + /* Receive data register full */ + if ((0U != ((uint32_t)kLPUART_RxDataRegFullFlag & status)) && + (0U != ((uint32_t)kLPUART_RxDataRegFullInterruptEnable & enabledInterrupts))) + { + LPUART_TransferHandleReceiveDataFull(base, handle); + } + + /* Send data register empty and the interrupt is enabled. */ + if ((0U != ((uint32_t)kLPUART_TxDataRegEmptyFlag & status)) && + (0U != ((uint32_t)kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts))) + { + LPUART_TransferHandleSendDataEmpty(base, handle); + } + + /* Transmission complete and the interrupt is enabled. */ + if ((0U != ((uint32_t)kLPUART_TransmissionCompleteFlag & status)) && + (0U != ((uint32_t)kLPUART_TransmissionCompleteInterruptEnable & enabledInterrupts))) + { + LPUART_TransferHandleTransmissionComplete(base, handle); + } +} + +/*! + * brief LPUART Error IRQ handle function. + * + * This function handles the LPUART error IRQ request. + * + * param base LPUART peripheral base address. + * param irqHandle LPUART handle pointer. + */ +void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle) +{ + /* To be implemented by User. */ +} +#if defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART0_LPUART1_RX_DriverIRQHandler(void); +void LPUART0_LPUART1_RX_DriverIRQHandler(void) +{ + /* If handle is registered, treat the transfer function is enabled. */ + if (NULL != s_lpuartHandle[0]) + { + s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]); + } + if (NULL != s_lpuartHandle[1]) + { + s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]); + } + SDK_ISR_EXIT_BARRIER; +} +void LPUART0_LPUART1_TX_DriverIRQHandler(void); +void LPUART0_LPUART1_TX_DriverIRQHandler(void) +{ + /* If handle is registered, treat the transfer function is enabled. */ + if (NULL != s_lpuartHandle[0]) + { + s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]); + } + if (NULL != s_lpuartHandle[1]) + { + s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]); + } + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART0_LPUART1_DriverIRQHandler(void); +void LPUART0_LPUART1_DriverIRQHandler(void) +{ + /* If handle is registered, treat the transfer function is enabled. */ + if (NULL != s_lpuartHandle[0]) + { + s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]); + } + if (NULL != s_lpuartHandle[1]) + { + s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]); + } + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART0) +#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART0_TX_DriverIRQHandler(void); +void LPUART0_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART0_RX_DriverIRQHandler(void); +void LPUART0_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART0_DriverIRQHandler(void); +void LPUART0_DriverIRQHandler(void) +{ + s_lpuartIsr[0](LPUART0, s_lpuartHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif +#endif + +#if defined(LPUART1) +#if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART1_TX_DriverIRQHandler(void); +void LPUART1_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART1_RX_DriverIRQHandler(void); +void LPUART1_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART1_DriverIRQHandler(void); +void LPUART1_DriverIRQHandler(void) +{ + s_lpuartIsr[1](LPUART1, s_lpuartHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif +#endif + +#if defined(LPUART2) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART2_TX_DriverIRQHandler(void); +void LPUART2_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[2](LPUART2, s_lpuartHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART2_RX_DriverIRQHandler(void); +void LPUART2_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[2](LPUART2, s_lpuartHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART2_DriverIRQHandler(void); +void LPUART2_DriverIRQHandler(void) +{ + s_lpuartIsr[2](LPUART2, s_lpuartHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART3) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART3_TX_DriverIRQHandler(void); +void LPUART3_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[3](LPUART3, s_lpuartHandle[3]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART3_RX_DriverIRQHandler(void); +void LPUART3_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[3](LPUART3, s_lpuartHandle[3]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART3_DriverIRQHandler(void); +void LPUART3_DriverIRQHandler(void) +{ + s_lpuartIsr[3](LPUART3, s_lpuartHandle[3]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART4) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART4_TX_DriverIRQHandler(void); +void LPUART4_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[4](LPUART4, s_lpuartHandle[4]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART4_RX_DriverIRQHandler(void); +void LPUART4_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[4](LPUART4, s_lpuartHandle[4]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART4_DriverIRQHandler(void); +void LPUART4_DriverIRQHandler(void) +{ + s_lpuartIsr[4](LPUART4, s_lpuartHandle[4]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART5) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART5_TX_DriverIRQHandler(void); +void LPUART5_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[5](LPUART5, s_lpuartHandle[5]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART5_RX_DriverIRQHandler(void); +void LPUART5_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[5](LPUART5, s_lpuartHandle[5]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART5_DriverIRQHandler(void); +void LPUART5_DriverIRQHandler(void) +{ + s_lpuartIsr[5](LPUART5, s_lpuartHandle[5]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART6) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART6_TX_DriverIRQHandler(void); +void LPUART6_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[6](LPUART6, s_lpuartHandle[6]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART6_RX_DriverIRQHandler(void); +void LPUART6_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[6](LPUART6, s_lpuartHandle[6]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART6_DriverIRQHandler(void); +void LPUART6_DriverIRQHandler(void) +{ + s_lpuartIsr[6](LPUART6, s_lpuartHandle[6]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART7) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART7_TX_DriverIRQHandler(void); +void LPUART7_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[7](LPUART7, s_lpuartHandle[7]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART7_RX_DriverIRQHandler(void); +void LPUART7_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[7](LPUART7, s_lpuartHandle[7]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART7_DriverIRQHandler(void); +void LPUART7_DriverIRQHandler(void) +{ + s_lpuartIsr[7](LPUART7, s_lpuartHandle[7]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART8) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART8_TX_DriverIRQHandler(void); +void LPUART8_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[8](LPUART8, s_lpuartHandle[8]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART8_RX_DriverIRQHandler(void); +void LPUART8_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[8](LPUART8, s_lpuartHandle[8]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART8_DriverIRQHandler(void); +void LPUART8_DriverIRQHandler(void) +{ + s_lpuartIsr[8](LPUART8, s_lpuartHandle[8]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART9) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART9_TX_DriverIRQHandler(void); +void LPUART9_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[9](LPUART9, s_lpuartHandle[9]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART9_RX_DriverIRQHandler(void); +void LPUART9_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[9](LPUART9, s_lpuartHandle[9]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART9_DriverIRQHandler(void); +void LPUART9_DriverIRQHandler(void) +{ + s_lpuartIsr[9](LPUART9, s_lpuartHandle[9]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART10) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART10_TX_DriverIRQHandler(void); +void LPUART10_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[10](LPUART10, s_lpuartHandle[10]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART10_RX_DriverIRQHandler(void); +void LPUART10_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[10](LPUART10, s_lpuartHandle[10]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART10_DriverIRQHandler(void); +void LPUART10_DriverIRQHandler(void) +{ + s_lpuartIsr[10](LPUART10, s_lpuartHandle[10]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART11) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART11_TX_DriverIRQHandler(void); +void LPUART11_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[11](LPUART11, s_lpuartHandle[11]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART11_RX_DriverIRQHandler(void); +void LPUART11_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[11](LPUART11, s_lpuartHandle[11]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART11_DriverIRQHandler(void); +void LPUART11_DriverIRQHandler(void) +{ + s_lpuartIsr[11](LPUART11, s_lpuartHandle[11]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(LPUART12) +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART12_TX_DriverIRQHandler(void); +void LPUART12_TX_DriverIRQHandler(void) +{ + s_lpuartIsr[12](LPUART12, s_lpuartHandle[12]); + SDK_ISR_EXIT_BARRIER; +} +void LPUART12_RX_DriverIRQHandler(void); +void LPUART12_RX_DriverIRQHandler(void) +{ + s_lpuartIsr[12](LPUART12, s_lpuartHandle[12]); + SDK_ISR_EXIT_BARRIER; +} +#else +void LPUART12_DriverIRQHandler(void); +void LPUART12_DriverIRQHandler(void) +{ + s_lpuartIsr[12](LPUART12, s_lpuartHandle[12]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#endif + +#if defined(CM4_0__LPUART) +void M4_0_LPUART_DriverIRQHandler(void); +void M4_0_LPUART_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(CM4_0__LPUART)](CM4_0__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_0__LPUART)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CM4_1__LPUART) +void M4_1_LPUART_DriverIRQHandler(void); +void M4_1_LPUART_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(CM4_1__LPUART)](CM4_1__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_1__LPUART)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CM4__LPUART) +void M4_LPUART_DriverIRQHandler(void); +void M4_LPUART_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(CM4__LPUART)](CM4__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4__LPUART)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART0) +void DMA_UART0_INT_DriverIRQHandler(void); +void DMA_UART0_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(DMA__LPUART0)](DMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART0)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART1) +void DMA_UART1_INT_DriverIRQHandler(void); +void DMA_UART1_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(DMA__LPUART1)](DMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART1)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART2) +void DMA_UART2_INT_DriverIRQHandler(void); +void DMA_UART2_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(DMA__LPUART2)](DMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART2)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART3) +void DMA_UART3_INT_DriverIRQHandler(void); +void DMA_UART3_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(DMA__LPUART3)](DMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART3)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__LPUART4) +void DMA_UART4_INT_DriverIRQHandler(void); +void DMA_UART4_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(DMA__LPUART4)](DMA__LPUART4, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART4)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__LPUART0) +void ADMA_UART0_INT_DriverIRQHandler(void); +void ADMA_UART0_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(ADMA__LPUART0)](ADMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART0)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__LPUART1) +void ADMA_UART1_INT_DriverIRQHandler(void); +void ADMA_UART1_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(ADMA__LPUART1)](ADMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART1)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__LPUART2) +void ADMA_UART2_INT_DriverIRQHandler(void); +void ADMA_UART2_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(ADMA__LPUART2)](ADMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART2)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__LPUART3) +void ADMA_UART3_INT_DriverIRQHandler(void); +void ADMA_UART3_INT_DriverIRQHandler(void) +{ + s_lpuartIsr[LPUART_GetInstance(ADMA__LPUART3)](ADMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART3)]); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpuart.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpuart.h new file mode 100644 index 00000000000..13ea2365f63 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpuart.h @@ -0,0 +1,1128 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LPUART_H_ +#define FSL_LPUART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpuart_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief LPUART driver version. */ +#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 8, 2)) +/*! @} */ + +/*! @brief Retry times for waiting flag. */ +#ifndef UART_RETRY_TIMES +#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */ +#endif + +/*! @brief Error codes for the LPUART driver. */ +enum +{ + kStatus_LPUART_TxBusy = MAKE_STATUS(kStatusGroup_LPUART, 0), /*!< TX busy */ + kStatus_LPUART_RxBusy = MAKE_STATUS(kStatusGroup_LPUART, 1), /*!< RX busy */ + kStatus_LPUART_TxIdle = MAKE_STATUS(kStatusGroup_LPUART, 2), /*!< LPUART transmitter is idle. */ + kStatus_LPUART_RxIdle = MAKE_STATUS(kStatusGroup_LPUART, 3), /*!< LPUART receiver is idle. */ + kStatus_LPUART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 4), /*!< TX FIFO watermark too large */ + kStatus_LPUART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_LPUART, 5), /*!< RX FIFO watermark too large */ + kStatus_LPUART_FlagCannotClearManually = MAKE_STATUS(kStatusGroup_LPUART, 6), /*!< Some flag can't manually clear */ + kStatus_LPUART_Error = MAKE_STATUS(kStatusGroup_LPUART, 7), /*!< Error happens on LPUART. */ + kStatus_LPUART_RxRingBufferOverrun = + MAKE_STATUS(kStatusGroup_LPUART, 8), /*!< LPUART RX software ring buffer overrun. */ + kStatus_LPUART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_LPUART, 9), /*!< LPUART RX receiver overrun. */ + kStatus_LPUART_NoiseError = MAKE_STATUS(kStatusGroup_LPUART, 10), /*!< LPUART noise error. */ + kStatus_LPUART_FramingError = MAKE_STATUS(kStatusGroup_LPUART, 11), /*!< LPUART framing error. */ + kStatus_LPUART_ParityError = MAKE_STATUS(kStatusGroup_LPUART, 12), /*!< LPUART parity error. */ + kStatus_LPUART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPUART, 13), /*!< Baudrate is not support in current clock source */ + kStatus_LPUART_IdleLineDetected = MAKE_STATUS(kStatusGroup_LPUART, 14), /*!< IDLE flag. */ + kStatus_LPUART_Timeout = MAKE_STATUS(kStatusGroup_LPUART, 15), /*!< LPUART times out. */ +}; + +/*! @brief LPUART parity mode. */ +typedef enum _lpuart_parity_mode +{ + kLPUART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kLPUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kLPUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} lpuart_parity_mode_t; + +/*! @brief LPUART data bits count. */ +typedef enum _lpuart_data_bits +{ + kLPUART_EightDataBits = 0x0U, /*!< Eight data bit */ +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + kLPUART_SevenDataBits = 0x1U, /*!< Seven data bit */ +#endif +} lpuart_data_bits_t; + +/*! @brief LPUART stop bit count. */ +typedef enum _lpuart_stop_bit_count +{ + kLPUART_OneStopBit = 0U, /*!< One stop bit */ + kLPUART_TwoStopBit = 1U, /*!< Two stop bits */ +} lpuart_stop_bit_count_t; + +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT +/*! @brief LPUART transmit CTS source. */ +typedef enum _lpuart_transmit_cts_source +{ + kLPUART_CtsSourcePin = 0U, /*!< CTS resource is the LPUART_CTS pin. */ + kLPUART_CtsSourceMatchResult = 1U, /*!< CTS resource is the match result. */ +} lpuart_transmit_cts_source_t; + +/*! @brief LPUART transmit CTS configure. */ +typedef enum _lpuart_transmit_cts_config +{ + kLPUART_CtsSampleAtStart = 0U, /*!< CTS input is sampled at the start of each character. */ + kLPUART_CtsSampleAtIdle = 1U, /*!< CTS input is sampled when the transmitter is idle */ +} lpuart_transmit_cts_config_t; +#endif + +/*! @brief LPUART idle flag type defines when the receiver starts counting. */ +typedef enum _lpuart_idle_type_select +{ + kLPUART_IdleTypeStartBit = 0U, /*!< Start counting after a valid start bit. */ + kLPUART_IdleTypeStopBit = 1U, /*!< Start counting after a stop bit. */ +} lpuart_idle_type_select_t; + +/*! @brief LPUART idle detected configuration. + * This structure defines the number of idle characters that must be received before + * the IDLE flag is set. + */ +typedef enum _lpuart_idle_config +{ + kLPUART_IdleCharacter1 = 0U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter2 = 1U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter4 = 2U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter8 = 3U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter16 = 4U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter32 = 5U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter64 = 6U, /*!< the number of idle characters. */ + kLPUART_IdleCharacter128 = 7U, /*!< the number of idle characters. */ +} lpuart_idle_config_t; + +/*! + * @brief LPUART interrupt configuration structure, default settings all disabled. + * + * This structure contains the settings for all LPUART interrupt configurations. + */ +enum _lpuart_interrupt_enable +{ +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8U), /*!< LIN break detect. bit 7 */ +#endif + kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8U), /*!< Receive Active Edge. bit 6 */ + kLPUART_TxDataRegEmptyInterruptEnable = (LPUART_CTRL_TIE_MASK), /*!< Transmit data register empty. bit 23 */ + kLPUART_TransmissionCompleteInterruptEnable = (LPUART_CTRL_TCIE_MASK), /*!< Transmission complete. bit 22 */ + kLPUART_RxDataRegFullInterruptEnable = (LPUART_CTRL_RIE_MASK), /*!< Receiver data register full. bit 21 */ + kLPUART_IdleLineInterruptEnable = (LPUART_CTRL_ILIE_MASK), /*!< Idle line. bit 20 */ + kLPUART_RxOverrunInterruptEnable = (LPUART_CTRL_ORIE_MASK), /*!< Receiver Overrun. bit 27 */ + kLPUART_NoiseErrorInterruptEnable = (LPUART_CTRL_NEIE_MASK), /*!< Noise error flag. bit 26 */ + kLPUART_FramingErrorInterruptEnable = (LPUART_CTRL_FEIE_MASK), /*!< Framing error flag. bit 25 */ + kLPUART_ParityErrorInterruptEnable = (LPUART_CTRL_PEIE_MASK), /*!< Parity error flag. bit 24 */ +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + kLPUART_Match1InterruptEnable = (LPUART_CTRL_MA1IE_MASK), /*!< Parity error flag. bit 15 */ + kLPUART_Match2InterruptEnable = (LPUART_CTRL_MA2IE_MASK), /*!< Parity error flag. bit 14 */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + kLPUART_TxFifoOverflowInterruptEnable = (LPUART_FIFO_TXOFE_MASK), /*!< Transmit FIFO Overflow. bit 9 */ + kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK), /*!< Receive FIFO Underflow. bit 8 */ +#endif + + kLPUART_AllInterruptEnable = kLPUART_RxActiveEdgeInterruptEnable | kLPUART_TxDataRegEmptyInterruptEnable | + kLPUART_TransmissionCompleteInterruptEnable | kLPUART_RxDataRegFullInterruptEnable | + kLPUART_IdleLineInterruptEnable | kLPUART_RxOverrunInterruptEnable | + kLPUART_NoiseErrorInterruptEnable | kLPUART_FramingErrorInterruptEnable | + kLPUART_ParityErrorInterruptEnable +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + | kLPUART_LinBreakInterruptEnable +#endif +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + | kLPUART_Match1InterruptEnable | kLPUART_Match2InterruptEnable +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + | kLPUART_TxFifoOverflowInterruptEnable | kLPUART_RxFifoUnderflowInterruptEnable +#endif + , +}; + +/*! + * @brief LPUART status flags. + * + * This provides constants for the LPUART status flags for use in the LPUART functions. + */ +enum _lpuart_flags +{ + kLPUART_TxDataRegEmptyFlag = + (LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty. bit 23 */ + kLPUART_TransmissionCompleteFlag = + (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete. bit 22 */ + kLPUART_RxDataRegFullFlag = (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive + data buffer is full. bit 21 */ + kLPUART_IdleLineFlag = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected. bit 20 */ + kLPUART_RxOverrunFlag = (LPUART_STAT_OR_MASK), /*!< Receive Overrun, sets when new data is received before data is + read from receive register. bit 19 */ + kLPUART_NoiseErrorFlag = (LPUART_STAT_NF_MASK), /*!< Receive takes 3 samples of each received bit. If any of these + samples differ, noise flag sets. bit 18 */ + kLPUART_FramingErrorFlag = + (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected. bit 17 */ + kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection. bit 16 */ +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break + char detected and LIN circuit enabled. bit 31 */ +#endif + kLPUART_RxActiveEdgeFlag = (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active + edge detected. bit 30 */ + kLPUART_RxActiveFlag = + (LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start. bit 24 */ +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + kLPUART_DataMatch1Flag = + LPUART_STAT_MA1F_MASK, /*!< The next character to be read from LPUART_DATA matches MA1. bit 15 */ + kLPUART_DataMatch2Flag = + LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2. bit 14 */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + kLPUART_TxFifoEmptyFlag = + (LPUART_FIFO_TXEMPT_MASK >> 16), /*!< TXEMPT bit, sets if transmit buffer is empty. bit 7 */ + kLPUART_RxFifoEmptyFlag = + (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty. bit 6 */ + kLPUART_TxFifoOverflowFlag = + (LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred. bit 1 */ + kLPUART_RxFifoUnderflowFlag = + (LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred. bit 0 */ +#endif + + kLPUART_AllClearFlags = kLPUART_RxActiveEdgeFlag | kLPUART_IdleLineFlag | kLPUART_RxOverrunFlag | + kLPUART_NoiseErrorFlag | kLPUART_FramingErrorFlag | kLPUART_ParityErrorFlag +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + | kLPUART_DataMatch1Flag | kLPUART_DataMatch2Flag +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + | kLPUART_TxFifoOverflowFlag | kLPUART_RxFifoUnderflowFlag +#endif +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + | kLPUART_LinBreakFlag +#endif + , + + kLPUART_AllFlags = + kLPUART_RxActiveEdgeFlag | kLPUART_IdleLineFlag | kLPUART_RxOverrunFlag | kLPUART_TxDataRegEmptyFlag | + kLPUART_TransmissionCompleteFlag | kLPUART_RxDataRegFullFlag | kLPUART_RxActiveFlag | kLPUART_NoiseErrorFlag | + kLPUART_FramingErrorFlag | kLPUART_ParityErrorFlag +#if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + | kLPUART_DataMatch1Flag | kLPUART_DataMatch2Flag +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + | kLPUART_TxFifoOverflowFlag | kLPUART_RxFifoUnderflowFlag | kLPUART_TxFifoEmptyFlag | kLPUART_RxFifoEmptyFlag +#endif +#if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT + | kLPUART_LinBreakFlag +#endif + , +}; + +/*! @brief LPUART configuration structure. */ +typedef struct _lpuart_config +{ + uint32_t baudRate_Bps; /*!< LPUART baud rate */ + lpuart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */ + bool isMsb; /*!< Data bits order, LSB (default), MSB */ +#if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT + lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + uint8_t txFifoWatermark; /*!< TX FIFO watermark */ + uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ +#endif +#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT + bool enableRxRTS; /*!< RX RTS enable */ + bool enableTxCTS; /*!< TX CTS enable */ + lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */ + lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */ +#endif + lpuart_idle_type_select_t rxIdleType; /*!< RX IDLE type. */ + lpuart_idle_config_t rxIdleConfig; /*!< RX IDLE configuration. */ + bool enableTx; /*!< Enable TX */ + bool enableRx; /*!< Enable RX */ +} lpuart_config_t; + +/*! @brief LPUART transfer structure. */ +typedef struct _lpuart_transfer +{ + /* + * Use separate TX and RX data pointer, because TX data is const data. + * The member data is kept for backward compatibility. + */ + union + { + uint8_t *data; /*!< The buffer of data to be transfer.*/ + uint8_t *rxData; /*!< The buffer to receive data. */ + uint16_t *rxData16; /*!< The buffer to receive data. */ + const uint8_t *txData; /*!< The buffer of data to be sent. */ + const uint16_t *txData16; /*!< The buffer of data to be sent. */ + }; + size_t dataSize; /*!< The byte count to be transfer. */ +} lpuart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _lpuart_handle lpuart_handle_t; + +/*! @brief LPUART transfer callback function. */ +typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData); + +/*! @brief LPUART handle structure. */ +struct _lpuart_handle +{ + union + { + const uint8_t *volatile txData; /*!< Address of remaining data to send. */ + const uint16_t *volatile txData16; /*!< Address of remaining data to send. */ + }; + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + union + { + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + uint16_t *volatile rxData16; /*!< Address of remaining data to receive. */ + }; + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + union + { + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + uint16_t *rxRingBuffer16; /*!< Start address of the receiver ring buffer. */ + }; + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + lpuart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< LPUART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state. */ + +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + bool isSevenDataBits; /*!< Seven data bits flag. */ +#endif + bool is16bitData; /*!< 16bit data bits flag, only used for 9bit or 10bit data */ +}; + +/* Typedef for interrupt handler. */ +typedef void (*lpuart_isr_t)(LPUART_Type *base, void *handle); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of LPUART handle. */ +extern void *s_lpuartHandle[]; + +/* Array of LPUART IRQ number. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +extern const IRQn_Type s_lpuartTxIRQ[]; +#else +extern const IRQn_Type s_lpuartIRQ[]; +#endif + +/* LPUART ISR for transactional APIs. */ +extern lpuart_isr_t s_lpuartIsr[]; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +#if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL + +/*! + * @name Software Reset + * @{ + */ + +/*! + * @brief Resets the LPUART using software. + * + * This function resets all internal logic and registers except the Global Register. + * Remains set until cleared by software. + * + * @param base LPUART peripheral base address. + */ +static inline void LPUART_SoftwareReset(LPUART_Type *base) +{ + base->GLOBAL |= LPUART_GLOBAL_RST_MASK; + base->GLOBAL &= ~LPUART_GLOBAL_RST_MASK; +} +/*! @} */ +#endif /*FSL_FEATURE_LPUART_HAS_GLOBAL*/ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an LPUART instance with the user configuration structure and the peripheral clock. + * + * This function configures the LPUART module with user-defined settings. Call the LPUART_GetDefaultConfig() function + * to configure the configuration structure and get the default configuration. + * The example below shows how to use this API to configure the LPUART. + * @code + * lpuart_config_t lpuartConfig; + * lpuartConfig.baudRate_Bps = 115200U; + * lpuartConfig.parityMode = kLPUART_ParityDisabled; + * lpuartConfig.dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig.isMsb = false; + * lpuartConfig.stopBitCount = kLPUART_OneStopBit; + * lpuartConfig.txFifoWatermark = 0; + * lpuartConfig.rxFifoWatermark = 1; + * LPUART_Init(LPUART1, &lpuartConfig, 20000000U); + * @endcode + * + * @param base LPUART peripheral base address. + * @param config Pointer to a user-defined configuration structure. + * @param srcClock_Hz LPUART clock source frequency in HZ. + * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success LPUART initialize succeed + */ +status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a LPUART instance. + * + * This function waits for transmit to complete, disables TX and RX, and disables the LPUART clock. + * + * @param base LPUART peripheral base address. + */ +void LPUART_Deinit(LPUART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the LPUART configuration structure to a default value. The default + * values are: + * lpuartConfig->baudRate_Bps = 115200U; + * lpuartConfig->parityMode = kLPUART_ParityDisabled; + * lpuartConfig->dataBitsCount = kLPUART_EightDataBits; + * lpuartConfig->isMsb = false; + * lpuartConfig->stopBitCount = kLPUART_OneStopBit; + * lpuartConfig->txFifoWatermark = 0; + * lpuartConfig->rxFifoWatermark = 1; + * lpuartConfig->rxIdleType = kLPUART_IdleTypeStartBit; + * lpuartConfig->rxIdleConfig = kLPUART_IdleCharacter1; + * lpuartConfig->enableTx = false; + * lpuartConfig->enableRx = false; + * + * @param config Pointer to a configuration structure. + */ +void LPUART_GetDefaultConfig(lpuart_config_t *config); +/*! @} */ + +/*! + * @name Module configuration + * @{ + */ +/*! + * @brief Sets the LPUART instance baudrate. + * + * This function configures the LPUART module baudrate. This function is used to update + * the LPUART module baudrate after the LPUART module is initialized by the LPUART_Init. + * @code + * LPUART_SetBaudRate(LPUART1, 115200U, 20000000U); + * @endcode + * + * @param base LPUART peripheral base address. + * @param baudRate_Bps LPUART baudrate to be set. + * @param srcClock_Hz LPUART clock source frequency in HZ. + * @retval kStatus_LPUART_BaudrateNotSupport Baudrate is not supported in the current clock source. + * @retval kStatus_Success Set baudrate succeeded. + */ +status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); + +/*! + * @brief Enable 9-bit data mode for LPUART. + * + * This function set the 9-bit mode for LPUART module. The 9th bit is not used for parity thus can be modified by user. + * + * @param base LPUART peripheral base address. + * @param enable true to enable, flase to disable. + */ +void LPUART_Enable9bitMode(LPUART_Type *base, bool enable); + +/*! + * @brief Set the LPUART address. + * + * This function configures the address for LPUART module that works as slave in 9-bit data mode. One or two address + * fields can be configured. When the address field's match enable bit is set, the frame it receices with MSB being + * 1 is considered as an address frame, otherwise it is considered as data frame. Once the address frame matches one + * of slave's own addresses, this slave is addressed. This address frame and its following data frames are stored in + * the receive buffer, otherwise the frames will be discarded. To un-address a slave, just send an address frame with + * unmatched address. + * + * @note Any LPUART instance joined in the multi-slave system can work as slave. The position of the address mark is the + * same as the parity bit when parity is enabled for 8 bit and 9 bit data formats. + * + * @param base LPUART peripheral base address. + * @param address1 LPUART slave address1. + * @param address2 LPUART slave address2. + */ +static inline void LPUART_SetMatchAddress(LPUART_Type *base, uint16_t address1, uint16_t address2) +{ + /* Configure match address. */ + uint32_t address = ((uint32_t)address2 << 16U) | (uint32_t)address1 | 0x1000100UL; + base->MATCH = address; +} + +/*! + * @brief Enable the LPUART match address feature. + * + * @param base LPUART peripheral base address. + * @param match1 true to enable match address1, false to disable. + * @param match2 true to enable match address2, false to disable. + */ +static inline void LPUART_EnableMatchAddress(LPUART_Type *base, bool match1, bool match2) +{ + /* Configure match address1 enable bit. */ + if (match1) + { + base->BAUD |= (uint32_t)LPUART_BAUD_MAEN1_MASK; + } + else + { + base->BAUD &= ~(uint32_t)LPUART_BAUD_MAEN1_MASK; + } + /* Configure match address2 enable bit. */ + if (match2) + { + base->BAUD |= (uint32_t)LPUART_BAUD_MAEN2_MASK; + } + else + { + base->BAUD &= ~(uint32_t)LPUART_BAUD_MAEN2_MASK; + } +} + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO +/*! + * @brief Sets the rx FIFO watermark. + * + * @param base LPUART peripheral base address. + * @param water Rx FIFO watermark. + */ +static inline void LPUART_SetRxFifoWatermark(LPUART_Type *base, uint8_t water) +{ + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > water); + base->WATER = (base->WATER & ~LPUART_WATER_RXWATER_MASK) | LPUART_WATER_RXWATER(water); +} + +/*! + * @brief Sets the tx FIFO watermark. + * + * @param base LPUART peripheral base address. + * @param water Tx FIFO watermark. + */ +static inline void LPUART_SetTxFifoWatermark(LPUART_Type *base, uint8_t water) +{ + assert((uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(base) > water); + base->WATER = (base->WATER & ~LPUART_WATER_TXWATER_MASK) | LPUART_WATER_TXWATER(water); +} +#endif + +/*! + * @brief Sets the LPUART using 16bit transmit, only for 9bit or 10bit mode. + * + * This function Enable 16bit Data transmit in lpuart_handle_t. + * + * @param handle LPUART handle pointer. + * @param enable true to enable, false to disable. + */ +static inline void LPUART_TransferEnable16Bit(lpuart_handle_t *handle, bool enable) +{ + handle->is16bitData = enable; +} +/*! @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets LPUART status flags. + * + * This function gets all LPUART status flags. The flags are returned as the logical + * OR value of the enumerators @ref _lpuart_flags. To check for a specific status, + * compare the return value with enumerators in the @ref _lpuart_flags. + * For example, to check whether the TX is empty: + * @code + * if (kLPUART_TxDataRegEmptyFlag & LPUART_GetStatusFlags(LPUART1)) + * { + * ... + * } + * @endcode + * + * @param base LPUART peripheral base address. + * @return LPUART status flags which are ORed by the enumerators in the _lpuart_flags. + */ +uint32_t LPUART_GetStatusFlags(LPUART_Type *base); + +/*! + * @brief Clears status flags with a provided mask. + * + * This function clears LPUART status flags with a provided mask. Automatically cleared flags + * can't be cleared by this function. + * Flags that can only cleared or set by hardware are: + * kLPUART_TxDataRegEmptyFlag, kLPUART_TransmissionCompleteFlag, kLPUART_RxDataRegFullFlag, + * kLPUART_RxActiveFlag, kLPUART_NoiseErrorFlag, kLPUART_ParityErrorFlag, + * kLPUART_TxFifoEmptyFlag,kLPUART_RxFifoEmptyFlag + * Note: This API should be called when the Tx/Rx is idle, otherwise it takes no effects. + * + * @param base LPUART peripheral base address. + * @param mask the status flags to be cleared. The user can use the enumerators in the + * _lpuart_status_flag_t to do the OR operation and get the mask. + * @return 0 succeed, others failed. + * @retval kStatus_LPUART_FlagCannotClearManually The flag can't be cleared by this function but + * it is cleared automatically by hardware. + * @retval kStatus_Success Status in the mask are cleared. + */ +status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask); +/*! @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables LPUART interrupts according to a provided mask. + * + * This function enables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See the @ref _lpuart_interrupt_enable. + * This examples shows how to enable TX empty interrupt and RX full interrupt: + * @code + * LPUART_EnableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base LPUART peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _lpuart_interrupt_enable. + */ +void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask); + +/*! + * @brief Disables LPUART interrupts according to a provided mask. + * + * This function disables the LPUART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See @ref _lpuart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * @code + * LPUART_DisableInterrupts(LPUART1,kLPUART_TxDataRegEmptyInterruptEnable | kLPUART_RxDataRegFullInterruptEnable); + * @endcode + * + * @param base LPUART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _lpuart_interrupt_enable. + */ +void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask); + +/*! + * @brief Gets enabled LPUART interrupts. + * + * This function gets the enabled LPUART interrupts. The enabled interrupts are returned + * as the logical OR value of the enumerators @ref _lpuart_interrupt_enable. To check + * a specific interrupt enable status, compare the return value with enumerators + * in @ref _lpuart_interrupt_enable. + * For example, to check whether the TX empty interrupt is enabled: + * @code + * uint32_t enabledInterrupts = LPUART_GetEnabledInterrupts(LPUART1); + * + * if (kLPUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) + * { + * ... + * } + * @endcode + * + * @param base LPUART peripheral base address. + * @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable. + */ +uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base); +/*! @} */ + +#if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE +/*! + * @name DMA Configuration + * @{ + */ +/*! + * @brief Gets the LPUART data register address. + * + * This function returns the LPUART data register address, which is mainly used by the DMA/eDMA. + * + * @param base LPUART peripheral base address. + * @return LPUART data register addresses which are used both by the transmitter and receiver. + */ +static inline uintptr_t LPUART_GetDataRegisterAddress(LPUART_Type *base) +{ + return (uintptr_t) & (base->DATA); +} + +/*! + * @brief Enables or disables the LPUART transmitter DMA request. + * + * This function enables or disables the transmit data register empty flag, STAT[TDRE], to generate DMA requests. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableTxDMA(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->BAUD |= LPUART_BAUD_TDMAE_MASK; + } + else + { + base->BAUD &= ~LPUART_BAUD_TDMAE_MASK; + } +} + +/*! + * @brief Enables or disables the LPUART receiver DMA. + * + * This function enables or disables the receiver data register full flag, STAT[RDRF], to generate DMA requests. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->BAUD |= LPUART_BAUD_RDMAE_MASK; + } + else + { + base->BAUD &= ~LPUART_BAUD_RDMAE_MASK; + } +} +/*! @} */ +#endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Get the LPUART instance from peripheral base address. + * + * @param base LPUART peripheral base address. + * @return LPUART instance. + */ +uint32_t LPUART_GetInstance(LPUART_Type *base); + +/*! + * @brief Enables or disables the LPUART transmitter. + * + * This function enables or disables the LPUART transmitter. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableTx(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPUART_CTRL_TE_MASK; + } + else + { + base->CTRL &= ~LPUART_CTRL_TE_MASK; + } +} + +/*! + * @brief Enables or disables the LPUART receiver. + * + * This function enables or disables the LPUART receiver. + * + * @param base LPUART peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void LPUART_EnableRx(LPUART_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= LPUART_CTRL_RE_MASK; + } + else + { + base->CTRL &= ~LPUART_CTRL_RE_MASK; + } +} + +/*! + * @brief Writes to the transmitter register. + * + * This function writes data to the transmitter register directly. The upper layer must + * ensure that the TX register is empty or that the TX FIFO has room before calling this function. + * + * @param base LPUART peripheral base address. + * @param data Data write to the TX register. + */ +static inline void LPUART_WriteByte(LPUART_Type *base, uint8_t data) +{ + base->DATA = data; +} + +/*! + * @brief Reads the receiver register. + * + * This function reads data from the receiver register directly. The upper layer must + * ensure that the receiver register is full or that the RX FIFO has data before calling this function. + * + * @param base LPUART peripheral base address. + * @return Data read from data register. + */ +static inline uint8_t LPUART_ReadByte(LPUART_Type *base) +{ +#if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT + uint32_t ctrl = base->CTRL; + uint8_t result; + /* + * $Branch Coverage Justification$ + * (ctrl & LPUART_CTRL_M7_MASK) == 0U) false is not covered. + * If ctrl & LPUART_CTRL_M7_MASK is 0, it can't be !0 in next judge. + */ + bool isSevenDataBits = (((ctrl & LPUART_CTRL_M7_MASK) != 0U) || + (((ctrl & LPUART_CTRL_M7_MASK) == 0U) && ((ctrl & LPUART_CTRL_M_MASK) == 0U) && + ((ctrl & LPUART_CTRL_PE_MASK) != 0U))); + + if (isSevenDataBits) + { + result = (uint8_t)(base->DATA & 0x7FU); + } + else + { + result = (uint8_t)base->DATA; + } + + return result; +#else + return (uint8_t)(base->DATA); +#endif +} + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO +/*! + * @brief Gets the rx FIFO data count. + * + * @param base LPUART peripheral base address. + * @return rx FIFO data count. + */ +static inline uint8_t LPUART_GetRxFifoCount(LPUART_Type *base) +{ + return (uint8_t)((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT); +} + +/*! + * @brief Gets the tx FIFO data count. + * + * @param base LPUART peripheral base address. + * @return tx FIFO data count. + */ +static inline uint8_t LPUART_GetTxFifoCount(LPUART_Type *base) +{ + return (uint8_t)((base->WATER & LPUART_WATER_TXCOUNT_MASK) >> LPUART_WATER_TXCOUNT_SHIFT); +} +#endif + +/*! + * @brief Transmit an address frame in 9-bit data mode. + * + * @param base LPUART peripheral base address. + * @param address LPUART slave address. + */ +void LPUART_SendAddress(LPUART_Type *base, uint8_t address); + +/*! + * @brief Writes to the transmitter register using a blocking method. + * + * This function polls the transmitter register, first waits for the register to be empty or TX FIFO to have room, + * and writes data to the transmitter buffer, then waits for the dat to be sent out to the bus. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Writes to the transmitter register using a blocking method in 9bit or 10bit mode. + * + * @note This function only support 9bit or 10bit transfer. + * Please make sure only 10bit of data is valid and other bits are 0. + * + * @param base LPUART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully wrote all data. + */ +status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length); + +/*! + * @brief Reads the receiver data register using a blocking method. + * + * This function polls the receiver register, waits for the receiver register full or receiver FIFO + * has data, and reads data from the TX register. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * @retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * @retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length); + +/*! + * @brief Reads the receiver data register in 9bit or 10bit mode. + * + * @note This function only support 9bit or 10bit transfer. + * + * @param base LPUART peripheral base address. + * @param data Start address of the buffer to store the received data by 16bit, only 10bit is valid. + * @param length Size of the buffer. + * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data. + * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data. + * @retval kStatus_LPUART_FramingError Framing error happened while receiving data. + * @retval kStatus_LPUART_ParityError Parity error happened while receiving data. + * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted. + * @retval kStatus_Success Successfully received all data. + */ +status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length); + +/*! @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the LPUART handle. + * + * This function initializes the LPUART handle, which can be used for other LPUART + * transactional APIs. Usually, for a specified LPUART instance, + * call this API once to get the initialized handle. + * + * The LPUART driver supports the "background" receiving, which means that user can set up + * an RX ring buffer optionally. Data received is stored into the ring buffer even when the + * user doesn't call the LPUART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * The ring buffer is disabled if passing NULL as @p ringBuffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param callback Callback function. + * @param userData User data. + */ +void LPUART_TransferCreateHandle(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_callback_t callback, + void *userData); +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function send data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data written to the transmitter register. When + * all data is written to the TX register in the ISR, the LPUART driver calls the callback + * function and passes the @ref kStatus_LPUART_TxIdle as status parameter. + * + * @note The kStatus_LPUART_TxIdle is passed to the upper layer when all data are written + * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX, + * check the kLPUART_TransmissionCompleteFlag to ensure that the transmit is finished. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART transfer structure, see #lpuart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_LPUART_TxBusy Previous transmission still not finished, data not all written to the TX register. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific UART handle. + * + * When the RX ring buffer is used, data received is stored into the ring buffer even when + * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize size of the ring buffer. + */ +void LPUART_TransferStartRingBuffer(LPUART_Type *base, + lpuart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferStopRingBuffer(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t LPUART_TransferGetRxRingBufferLength(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are not sent out. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferAbortSend(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been sent out to bus. + * + * This function gets the number of bytes that have been sent out to bus by an interrupt method. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using the interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function + * which returns without waiting to ensure that all data are received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough for read, the receive + * request is saved by the LPUART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the LPUART driver notifies the upper layer + * through a callback function and passes a status parameter kStatus_UART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer. + * The 5 bytes are copied to xfer->data, which returns with the + * parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is + * saved from xfer->data[5]. When 5 bytes are received, the LPUART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to xfer->data. When all data is received, the upper layer is notified. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART transfer structure, see uart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into the transmit queue. + * @retval kStatus_LPUART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base, + lpuart_handle_t *handle, + lpuart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + */ +void LPUART_TransferAbortReceive(LPUART_Type *base, lpuart_handle_t *handle); + +/*! + * @brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCount(LPUART_Type *base, lpuart_handle_t *handle, uint32_t *count); + +/*! + * @brief LPUART IRQ handle function. + * + * This function handles the LPUART transmit and receive IRQ request. + * + * @param base LPUART peripheral base address. + * @param irqHandle LPUART handle pointer. + */ +void LPUART_TransferHandleIRQ(LPUART_Type *base, void *irqHandle); + +/*! + * @brief LPUART Error IRQ handle function. + * + * This function handles the LPUART error IRQ request. + * + * @param base LPUART peripheral base address. + * @param irqHandle LPUART handle pointer. + */ +void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_LPUART_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpuart_edma.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpuart_edma.c new file mode 100644 index 00000000000..79196d9c653 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpuart_edma.c @@ -0,0 +1,522 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_lpuart_edma.h" +/* + * $Coverage Justification Reference$ + * + * $Justification fsl_lpuart_edma_c_ref_1$ + * The EDMA handle is only used by the LPUART EDMA driver, with the LPUART EDMA driver workflow, + * the callback is only called when EDMA transfer done. + * + * $Justification fsl_lpuart_edma_c_ref_2$ + * This function only handles the kLPUART_TransmissionCompleteFlag event. + * + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpuart_edma" +#endif + +/*base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle); + + /* Enable tx complete interrupt */ + LPUART_EnableInterrupts(lpuartPrivateHandle->base, (uint32_t)kLPUART_TransmissionCompleteInterruptEnable); + } +} + +static void LPUART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds) +{ + assert(NULL != param); + + lpuart_edma_private_handle_t *lpuartPrivateHandle = (lpuart_edma_private_handle_t *)param; + + /* Avoid warning for unused parameters. */ + handle = handle; + tcds = tcds; + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_edma_c_ref_1$ + */ + if (transferDone) + { + /* Disable transfer. */ + LPUART_TransferAbortReceiveEDMA(lpuartPrivateHandle->base, lpuartPrivateHandle->handle); + + if (NULL != lpuartPrivateHandle->handle->callback) + { + lpuartPrivateHandle->handle->callback(lpuartPrivateHandle->base, lpuartPrivateHandle->handle, + kStatus_LPUART_RxIdle, lpuartPrivateHandle->handle->userData); + } + } +} + +/*! + * brief Initializes the LPUART handle which is used in transactional functions. + * + * note This function disables all LPUART interrupts. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + * param callback Callback function. + * param userData User data. + * param txEdmaHandle User requested DMA handle for TX DMA transfer. + * param rxEdmaHandle User requested DMA handle for RX DMA transfer. + */ +void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, + lpuart_edma_handle_t *handle, + lpuart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle) +{ + assert(NULL != handle); + + uint32_t instance = LPUART_GetInstance(base); + + s_lpuartEdmaPrivateHandle[instance].base = base; + s_lpuartEdmaPrivateHandle[instance].handle = handle; + + (void)memset(handle, 0, sizeof(*handle)); + + handle->rxState = (uint8_t)kLPUART_RxIdle; + handle->txState = (uint8_t)kLPUART_TxIdle; + + handle->rxEdmaHandle = rxEdmaHandle; + handle->txEdmaHandle = txEdmaHandle; + + handle->callback = callback; + handle->userData = userData; + +#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO + /* Note: + Take care of the RX FIFO, EDMA request only assert when received bytes + equal or more than RX water mark, there is potential issue if RX water + mark larger than 1. + For example, if RX FIFO water mark is 2, upper layer needs 5 bytes and + 5 bytes are received. the last byte will be saved in FIFO but not trigger + EDMA transfer because the water mark is 2. + */ + if (NULL != rxEdmaHandle) + { + base->WATER &= (~LPUART_WATER_RXWATER_MASK); + } +#endif + + /* Save the handle in global variables to support the double weak mechanism. */ + s_lpuartHandle[instance] = handle; + /* Set LPUART_TransferEdmaHandleIRQ as DMA IRQ handler */ + s_lpuartIsr[instance] = LPUART_TransferEdmaHandleIRQ; + /* Disable all LPUART internal interrupts */ + LPUART_DisableInterrupts(base, (uint32_t)kLPUART_AllInterruptEnable); + /* Enable interrupt in NVIC. */ +#if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ + (void)EnableIRQ(s_lpuartTxIRQ[instance]); +#else + (void)EnableIRQ(s_lpuartIRQ[instance]); +#endif + + /* Configure TX. */ + if (NULL != txEdmaHandle) + { + EDMA_SetCallback(handle->txEdmaHandle, LPUART_SendEDMACallback, &s_lpuartEdmaPrivateHandle[instance]); + } + + /* Configure RX. */ + if (NULL != rxEdmaHandle) + { + EDMA_SetCallback(handle->rxEdmaHandle, LPUART_ReceiveEDMACallback, &s_lpuartEdmaPrivateHandle[instance]); + } +} + +/*! + * brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param xfer LPUART eDMA transfer structure. See #lpuart_transfer_t. + * retval kStatus_Success if succeed, others failed. + * retval kStatus_LPUART_TxBusy Previous transfer on going. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(NULL != handle); + assert(NULL != handle->txEdmaHandle); + assert(NULL != xfer); + assert(NULL != xfer->data); + assert(0U != xfer->dataSize); + + edma_transfer_config_t xferConfig; + status_t status; + + /* If previous TX not finished. */ + if ((uint8_t)kLPUART_TxBusy == handle->txState) + { + status = kStatus_LPUART_TxBusy; + } + else + { + handle->txState = (uint8_t)kLPUART_TxBusy; + handle->txDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, xfer->data, sizeof(uint8_t), + (void *)(uint32_t *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), sizeof(uint8_t), + xfer->dataSize, kEDMA_MemoryToPeripheral); + + /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */ + handle->nbytes = (uint8_t)sizeof(uint8_t); + + /* Submit transfer. */ + if (kStatus_Success != + EDMA_SubmitTransfer(handle->txEdmaHandle, (const edma_transfer_config_t *)(uint32_t)&xferConfig)) + { + return kStatus_Fail; + } + EDMA_StartTransfer(handle->txEdmaHandle); + + /* Enable LPUART TX EDMA. */ + LPUART_EnableTxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Receives data using eDMA. + * + * This function receives data using eDMA. This is non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + * param xfer LPUART eDMA transfer structure, see #lpuart_transfer_t. + * retval kStatus_Success if succeed, others fail. + * retval kStatus_LPUART_RxBusy Previous transfer ongoing. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer) +{ + assert(NULL != handle); + assert(NULL != handle->rxEdmaHandle); + assert(NULL != xfer); + assert(NULL != xfer->data); + assert(0U != xfer->dataSize); + + edma_transfer_config_t xferConfig; + status_t status; + + /* If previous RX not finished. */ + if ((uint8_t)kLPUART_RxBusy == handle->rxState) + { + status = kStatus_LPUART_RxBusy; + } + else + { + handle->rxState = (uint8_t)kLPUART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + + /* Prepare transfer. */ + EDMA_PrepareTransfer(&xferConfig, (void *)(uint32_t *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), + xfer->data, sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory); + + /* Store the initially configured eDMA minor byte transfer count into the LPUART handle */ + handle->nbytes = (uint8_t)sizeof(uint8_t); + + /* Submit transfer. */ + if (kStatus_Success != + EDMA_SubmitTransfer(handle->rxEdmaHandle, (const edma_transfer_config_t *)(uint32_t)&xferConfig)) + { + return kStatus_Fail; + } + EDMA_StartTransfer(handle->rxEdmaHandle); + + /* Enable LPUART RX EDMA. */ + LPUART_EnableRxDMA(base, true); + + status = kStatus_Success; + } + + return status; +} + +/*! + * brief Aborts the sent data using eDMA. + * + * This function aborts the sent data using eDMA. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) +{ + assert(NULL != handle); + assert(NULL != handle->txEdmaHandle); + + /* Disable LPUART TX EDMA. */ + LPUART_EnableTxDMA(base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->txEdmaHandle); + + handle->txState = (uint8_t)kLPUART_TxIdle; +} + +/*! + * brief Aborts the received data using eDMA. + * + * This function aborts the received data using eDMA. + * + * param base LPUART peripheral base address. + * param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle) +{ + assert(NULL != handle); + assert(NULL != handle->rxEdmaHandle); + + /* Disable LPUART RX EDMA. */ + LPUART_EnableRxDMA(base, false); + + /* Stop transfer. */ + EDMA_AbortTransfer(handle->rxEdmaHandle); + + handle->rxState = (uint8_t)kLPUART_RxIdle; +} + +/*! + * brief Gets the number of received bytes. + * + * This function gets the number of received bytes. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != handle->rxEdmaHandle); + assert(NULL != count); + + if ((uint8_t)kLPUART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - + ((uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->rxEdmaHandle->base, handle->rxEdmaHandle->channel)); + + return kStatus_Success; +} + +/*! + * brief Gets the number of bytes written to the LPUART TX register. + * + * This function gets the number of bytes written to the LPUART TX + * register by DMA. + * + * param base LPUART peripheral base address. + * param handle LPUART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != handle->txEdmaHandle); + assert(NULL != count); + + if ((uint8_t)kLPUART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - + ((uint32_t)handle->nbytes * + EDMA_GetRemainingMajorLoopCount(handle->txEdmaHandle->base, handle->txEdmaHandle->channel)); + + return kStatus_Success; +} + +/*! + * brief LPUART eDMA IRQ handle function. + * + * This function handles the LPUART tx complete IRQ request and invoke user callback. + * It is not set to static so that it can be used in user application. + * note This function is used as default IRQ handler by double weak mechanism. + * If user's specific IRQ handler is implemented, make sure this function is invoked in the handler. + * + * param base LPUART peripheral base address. + * param lpuartEdmaHandle LPUART handle pointer. + */ +void LPUART_TransferEdmaHandleIRQ(LPUART_Type *base, void *lpuartEdmaHandle) +{ + assert(lpuartEdmaHandle != NULL); + /* + * $Branch Coverage Justification$ + * $ref fsl_lpuart_edma_c_ref_2$ + */ + if (((uint32_t)kLPUART_TransmissionCompleteFlag & LPUART_GetStatusFlags(base)) != 0U) + { + lpuart_edma_handle_t *handle = (lpuart_edma_handle_t *)lpuartEdmaHandle; + + /* Disable tx complete interrupt */ + LPUART_DisableInterrupts(base, (uint32_t)kLPUART_TransmissionCompleteInterruptEnable); + + handle->txState = (uint8_t)kLPUART_TxIdle; + + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_LPUART_TxIdle, handle->userData); + } + } +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpuart_edma.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpuart_edma.h new file mode 100644 index 00000000000..1190ed36e86 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_lpuart_edma.h @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_LPUART_EDMA_H_ +#define FSL_LPUART_EDMA_H_ + +#include "fsl_lpuart.h" +#include "fsl_edma.h" + +/*! + * @addtogroup lpuart_edma_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief LPUART EDMA driver version. */ +#define FSL_LPUART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 6, 0)) +/*! @} */ + +/* Forward declaration of the handle typedef. */ +typedef struct _lpuart_edma_handle lpuart_edma_handle_t; + +/*! @brief LPUART transfer callback function. */ +typedef void (*lpuart_edma_transfer_callback_t)(LPUART_Type *base, + lpuart_edma_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief LPUART eDMA handle + */ +struct _lpuart_edma_handle +{ + lpuart_edma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< LPUART callback function parameter.*/ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + + edma_handle_t *txEdmaHandle; /*!< The eDMA TX channel used. */ + edma_handle_t *rxEdmaHandle; /*!< The eDMA RX channel used. */ + + uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA transactional + * @{ + */ + +/*! + * @brief Initializes the LPUART handle which is used in transactional functions. + * + * @note This function disables all LPUART interrupts. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + * @param callback Callback function. + * @param userData User data. + * @param txEdmaHandle User requested DMA handle for TX DMA transfer. + * @param rxEdmaHandle User requested DMA handle for RX DMA transfer. + */ +void LPUART_TransferCreateHandleEDMA(LPUART_Type *base, + lpuart_edma_handle_t *handle, + lpuart_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *txEdmaHandle, + edma_handle_t *rxEdmaHandle); + +/*! + * @brief Sends data using eDMA. + * + * This function sends data using eDMA. This is a non-blocking function, which returns + * right away. When all data is sent, the send callback function is called. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param xfer LPUART eDMA transfer structure. See #lpuart_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_LPUART_TxBusy Previous transfer on going. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_SendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Receives data using eDMA. + * + * This function receives data using eDMA. This is non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + * @param xfer LPUART eDMA transfer structure, see #lpuart_transfer_t. + * @retval kStatus_Success if succeed, others fail. + * @retval kStatus_LPUART_RxBusy Previous transfer ongoing. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer); + +/*! + * @brief Aborts the sent data using eDMA. + * + * This function aborts the sent data using eDMA. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortSendEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle); + +/*! + * @brief Aborts the received data using eDMA. + * + * This function aborts the received data using eDMA. + * + * @param base LPUART peripheral base address. + * @param handle Pointer to lpuart_edma_handle_t structure. + */ +void LPUART_TransferAbortReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle); + +/*! + * @brief Gets the number of bytes written to the LPUART TX register. + * + * This function gets the number of bytes written to the LPUART TX + * register by DMA. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetSendCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count); + +/*! + * @brief Gets the number of received bytes. + * + * This function gets the number of received bytes. + * + * @param base LPUART peripheral base address. + * @param handle LPUART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, uint32_t *count); + +/*! + * @brief LPUART eDMA IRQ handle function. + * + * This function handles the LPUART tx complete IRQ request and invoke user callback. + * It is not set to static so that it can be used in user application. + * @note This function is used as default IRQ handler by double weak mechanism. + * If user's specific IRQ handler is implemented, make sure this function is invoked in the handler. + * + * @param base LPUART peripheral base address. + * @param lpuartEdmaHandle LPUART handle pointer. + */ +void LPUART_TransferEdmaHandleIRQ(LPUART_Type *base, void *lpuartEdmaHandle); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_LPUART_EDMA_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_opamp.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_opamp.c new file mode 100644 index 00000000000..f75075d3ec4 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_opamp.c @@ -0,0 +1,193 @@ +/* + * Copyright 2021-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_opamp.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.opamp" +#endif + +#if defined(OPAMP_RSTS) +#define OPAMP_RESETS_ARRAY OPAMP_RSTS +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static uint32_t OPAMP_GetInstance(OPAMP_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +static OPAMP_Type *const s_opampBases[] = OPAMP_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to OPAMP clocks for each instance. */ +static const clock_ip_name_t s_opampClocks[] = OPAMP_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(OPAMP_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_opampResets[] = OPAMP_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +static uint32_t OPAMP_GetInstance(OPAMP_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0UL; instance < ARRAY_SIZE(s_opampBases); instance++) + { + if (s_opampBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_opampBases)); + + return instance; +} + +/*! + * brief Initialize OPAMP instance. + * + * param base OPAMP peripheral base address. + * param config The pointer to opamp_config_t. + */ +void OPAMP_Init(OPAMP_Type *base, const opamp_config_t *config) +{ + assert(config != NULL); + + uint32_t tmp32 = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_opampClocks[OPAMP_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(OPAMP_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_opampResets[OPAMP_GetInstance(base)]); +#endif + + tmp32 = OPAMP_OPAMP_CTR_EN(config->enable) | OPAMP_OPAMP_CTR_MODE(config->mode) | + OPAMP_OPAMP_CTR_BIASC(config->trimOption) | OPAMP_OPAMP_CTR_INTREF(config->intRefVoltage) | + OPAMP_OPAMP_CTR_PREF(config->posRefVoltage) | +#if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW + OPAMP_OPAMP_CTR_OUTSW(config->enableOutputSwitch) | +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW */ +#if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 + OPAMP_OPAMP_CTR_ADCSW1(config->enablePosADCSw1) | +#else + OPAMP_OPAMP_CTR_ADCSW(config->enablePosADCSw) | +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 */ +#if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 + OPAMP_OPAMP_CTR_ADCSW2(config->enablePosADCSw2) | +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 */ +#if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL + OPAMP_OPAMP_CTR_INPSEL(config->PosInputChannelSelection) | +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL */ +#if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD + OPAMP_OPAMP_CTR_TRIGMD(config->enableTriggerMode) | +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD */ + OPAMP_OPAMP_CTR_NGAIN(config->negGain); + base->OPAMP_CTR = tmp32; +#if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN + if (config->enableRefBuffer) + { + assert((uint32_t)(config->posGain) <= 7UL); + base->OPAMP_CTR |= OPAMP_OPAMP_CTR_PGAIN(config->posGain) | OPAMP_OPAMP_CTR_BUFEN_MASK; + } + else + { + if ((uint32_t)(config->posGain) > 7UL) + { + base->OPAMP_CTR |= OPAMP_OPAMP_CTR_PGAIN((uint32_t)(config->posGain) - 7UL); + } + else + { + assert((uint32_t)(config->posGain) == 0UL); + base->OPAMP_CTR |= OPAMP_OPAMP_CTR_PGAIN(config->posGain); + } + } +#else + base->OPAMP_CTR |= OPAMP_OPAMP_CTR_PGAIN(config->posGain); +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD */ +} + +/*! + * brief De-initialize OPAMP instance. + * + * param base OPAMP peripheral base address. + */ +void OPAMP_Deinit(OPAMP_Type *base) +{ + /* Disable OPAMP instance. */ + base->OPAMP_CTR &= ~OPAMP_OPAMP_CTR_EN_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_opampClocks[OPAMP_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Get default configuration of OPAMP. + * + * code + * config->enable = false; + * config->mode = kOPAMP_LowNoiseMode; + * config->trimOption = kOPAMP_TrimOptionDefault; + * config->intRefVoltage = kOPAMP_IntRefVoltVddaDiv2; + * config->enablePosADCSw = false; + * config->posRefVoltage = kOPAMP_PosRefVoltVrefh3; + * config->posGain = kOPAMP_PosGainReserved; + * config->negGain = kOPAMP_NegGainBufferMode; + * endcode + * + * param config The pointer to opamp_config_t. + */ +void OPAMP_GetDefaultConfig(opamp_config_t *config) +{ + assert(config != NULL); + + config->enable = false; + config->mode = kOPAMP_LowNoiseMode; + config->trimOption = kOPAMP_TrimOptionDefault; + config->intRefVoltage = kOPAMP_IntRefVoltVddaDiv2; + config->posRefVoltage = kOPAMP_PosRefVoltVrefh3; + config->posGain = kOPAMP_PosGainReserved; + config->negGain = kOPAMP_NegGainBufferMode; +#if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW + config->enableOutputSwitch = true; +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW */ +#if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 + config->enablePosADCSw1 = false; +#else + config->enablePosADCSw = false; +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 */ +#if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 + config->enablePosADCSw2 = false; +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 */ +#if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN + config->enableRefBuffer = false; +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN */ +#if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL + config->PosInputChannelSelection = kOPAMP_PosInputChannel0; +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL */ +#if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD + config->enableTriggerMode = false; +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD */ +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_opamp.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_opamp.h new file mode 100644 index 00000000000..c9767193d0b --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_opamp.h @@ -0,0 +1,301 @@ +/* + * Copyright 2021-2022, 2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_OPAMP_H_ +#define FSL_OPAMP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup opamp + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief OPAMP driver version. */ +#define FSL_OPAMP_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/*! @} */ + +/*! + * @brief The enumeration of OPAMP mode, including low noise mode and high speed mode. + */ +typedef enum _opamp_mode +{ + kOPAMP_LowNoiseMode = 0U, /*!< Set opamp mode as low noise mode. */ + kOPAMP_HighSpeedMode, /*!< Set opamp mode as high speed mode. */ +} opamp_mode_t; + +/*! + * @brief The enumeration of bias current trim option. + */ +typedef enum _opamp_bias_current_trim_option +{ + kOPAMP_TrimOptionDefault = 0U, /*!< Default Bias current trim option. */ + kOPAMP_TrimOptionIncreaseCurrent, /*!< Trim option selected as increase current. */ + kOPAMP_TrimOptionDecreaseCurrent, /*!< Trim option selected as decrease current. */ + kOPAMP_TrimOptionFurtherDecreaseCurrent, /*!< Trim option selected as further decrease current. */ +} opamp_bias_current_trim_option_t; + +/*! + * @brief The enumeration of internal reference voltage. + */ +typedef enum _opamp_internal_ref_voltage +{ + kOPAMP_IntRefVoltVddaDiv2 = 0U, /*!< Internal reference voltage selected as Vdda/2. */ + kOPAMP_IntRefVoltVdda3V, /*!< Internal reference voltage selected as Vdda_3V. */ + kOPAMP_IntRefVoltVssa3V, /*!< Internal reference voltage selected as Vssa_3V. */ + kOPAMP_IntRefVoltNotAllowed, /*!< Internal reference voltage not allowed. */ +} opamp_internal_ref_voltage_t; + +/*! + * @brief The enumeration of positive reference voltage（please refer to manual use）. + */ +typedef enum _opamp_positive_ref_voltage +{ + kOPAMP_PosRefVoltVrefh3 = 0U, /*!< Positive part reference voltage select Vrefh3, connected from DAC output. */ + kOPAMP_PosRefVoltVrefh0 = 1U, /*!< Positive part reference voltage select Vrefh0, connected from VDDA supply. */ + kOPAMP_PosRefVoltVrefh1 = 2U, /*!< Positive part reference voltage select Vrefh1, + connected from Voltage reference output. */ + kOPAMP_PosRefVoltVrefh4 = 3U, /*!< Positive part reference voltage select 520mv or reserved.*/ +} opamp_positive_ref_voltage_t; + +/*! + * @brief The enumeration of positive programmable gain (please refer to manual use). + */ +typedef enum _opamp_positive_gain +{ + kOPAMP_PosGainReserved = 0U, /*!< Positive Gain reserved. */ + kOPAMP_PosGainNonInvert1X = 1U, /*!< Positive non-inverting gain application 1X. */ + kOPAMP_PosGainNonInvert2X = 2U, /*!< Positive non-inverting gain application 2X. */ + kOPAMP_PosGainNonInvert4X = 3U, /*!< Positive non-inverting gain application 4X. */ + kOPAMP_PosGainNonInvert8X = 4U, /*!< Positive non-inverting gain application 8X. */ + kOPAMP_PosGainNonInvert16X = 5U, /*!< Positive non-inverting gain application 16X. */ + kOPAMP_PosGainNonInvert33X = 6U, /*!< Positive non-inverting gain application 33X. */ + kOPAMP_PosGainNonInvert64X = 7U, /*!< Positive non-inverting gain application 64X. */ +#if defined(FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER) && FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER + /* The following gain selections are for basic OPAMP only, and signal inputs are + supported on the non-inverting and inverting terminals.*/ + kOPAMP_PosGainNonInvertDisableBuffer2X = 8U, /*!< Positive non-inverting gain application 2X. */ + kOPAMP_PosGainNonInvertDisableBuffer3X = 9U, /*!< Positive non-inverting gain application 3X. */ + kOPAMP_PosGainNonInvertDisableBuffer5X = 10U, /*!< Positive non-inverting gain application 5X. */ + kOPAMP_PosGainNonInvertDisableBuffer9X = 11U, /*!< Positive non-inverting gain application 9X. */ + kOPAMP_PosGainNonInvertDisableBuffer17X = 12U, /*!< Positive non-inverting gain application 17X. */ + kOPAMP_PosGainNonInvertDisableBuffer34X = 13U, /*!< Positive non-inverting gain application 34X. */ + kOPAMP_PosGainNonInvertDisableBuffer65X = 14U, /*!< Positive non-inverting gain application 65X. */ +#endif /* FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER */ +} opamp_positive_gain_t; + +/*! + * @brief The enumeration of negative programmable gain. + */ +typedef enum _opamp_negative_gain +{ + kOPAMP_NegGainBufferMode = 0U, /*!< Negative Buffer Mode. */ + kOPAMP_NegGainInvert1X, /*!< Negative inverting gain application -1X. */ + kOPAMP_NegGainInvert2X, /*!< Negative inverting gain application -2X. */ + kOPAMP_NegGainInvert4X, /*!< Negative inverting gain application -4X. */ + kOPAMP_NegGainInvert8X, /*!< Negative inverting gain application -8X. */ + kOPAMP_NegGainInvert16X, /*!< Negative inverting gain application -16X. */ + kOPAMP_NegGainInvert33X, /*!< Negative inverting gain application -33X. */ + kOPAMP_NegGainInvert64X, /*!< Negative inverting gain application -64X. */ +} opamp_negative_gain_t; + +#if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL +/*! + * @brief The enumeration of positive input channel selection. + */ +typedef enum _opamp_positive_input_channel_selection +{ + kOPAMP_PosInputChannel0 = 0U, /*!< When OPAMP not in trigger mode, select positive input 0 (INP0).*/ + kOPAMP_PosInputChannel1 = 1U, /*!< When OPAMP not in trigger mode, select positive input 1 (INP1).*/ +} opamp_positive_input_channel_selection_t; +#endif +/*! + * @brief OPAMP configuraion, including mode, internal reference voltage, positive gain, negative gain and so on. + */ +typedef struct _opamp_config +{ + bool enable; /*!< Enable/disable OPAMP. */ + opamp_mode_t mode; /*!< Opamp mode, available values are @ref kOPAMP_LowNoiseMode and @ref kOPAMP_HighSpeedMode. */ + opamp_bias_current_trim_option_t trimOption; /*!< Bias current trim option, please refer to + @ref opamp_bias_current_trim_option_t. */ + opamp_internal_ref_voltage_t intRefVoltage; /*!< Internal reference voltage, please refer to + @ref opamp_internal_ref_voltage_t. */ + opamp_positive_ref_voltage_t posRefVoltage; /*!< Positive part reference voltage, please refer + to @ref opamp_positive_ref_voltage_t. */ + /* Positive part configuration. */ + opamp_positive_gain_t posGain; /*!< Positive part programmable gain, please refer + to @ref opamp_positive_gain_t. */ + /* Negative part configuration. */ + opamp_negative_gain_t negGain; /*!< Negative part programmable gain, please refer + to @ref opamp_negative_gain_t. */ +#if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW + bool enableOutputSwitch; /*!< OPAMP out to negative gain resistor ladder switch.*/ +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_OUTSW */ +#if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 + bool enablePosADCSw1; /*!< Positive part reference voltage switch to ADC channel or not. + - \b true Positive part reference voltage switch to ADC channel. + - \b false Positive part reference voltage do not switch to ADC channel. */ +#else + bool enablePosADCSw; /*!< Positive part reference voltage switch to ADC channel or not. + - \b true Positive part reference voltage switch to ADC channel. + - \b false Positive part reference voltage do not switch to ADC channel. */ +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW1 */ +#if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 + bool enablePosADCSw2; /*!< Positive part reference voltage switch to ADC channel or not. + - \b true Positive part reference voltage switch to ADC channel. + - \b false Positive part reference voltage do not switch to ADC channel. */ +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_ADCSW2 */ +#if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN + bool enableRefBuffer; /*!< Reference buffer enable.*/ +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN */ +#if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL + opamp_positive_input_channel_selection_t PosInputChannelSelection; /*!< Positive Input Channel Selection*/ +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_INPSEL */ +#if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD + bool enableTriggerMode; /*!< Trigger Mode Enable.*/ +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD */ +} opamp_config_t; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initialize OPAMP instance. + * + * @param base OPAMP peripheral base address. + * @param config The pointer to @ref opamp_config_t. + */ +void OPAMP_Init(OPAMP_Type *base, const opamp_config_t *config); + +/*! + * @brief De-initialize OPAMP instance. + * + * @param base OPAMP peripheral base address. + */ +void OPAMP_Deinit(OPAMP_Type *base); + +/*! + * @brief Get default configuration of OPAMP. + * + * @code + * config->enable = false; + * config->mode = kOPAMP_LowNoiseMode; + * config->trimOption = kOPAMP_TrimOptionDefault; + * config->intRefVoltage = kOPAMP_IntRefVoltVddaDiv2; + * config->enablePosADCSw = false; + * config->posRefVoltage = kOPAMP_PosRefVoltVrefh3; + * config->posGain = kOPAMP_PosGainReserved; + * config->negGain = kOPAMP_NegGainBufferMode; + * @endcode + * + * @param config The pointer to @ref opamp_config_t. + */ +void OPAMP_GetDefaultConfig(opamp_config_t *config); + +/*! @} */ + +/*! + * @name Positive port gain and negative gain configuration. + * @{ + */ +/*! + * @brief Configure OPAMP positive port gain. + * + * @param base OPAMP peripheral base address. + * @param option OPAMP positive port gain. + */ +static inline void OPAMP_DoPosGainConfig(OPAMP_Type *base, opamp_positive_gain_t option) +{ + base->OPAMP_CTR = (((base->OPAMP_CTR) & (~OPAMP_OPAMP_CTR_PGAIN_MASK)) | OPAMP_OPAMP_CTR_PGAIN(option)); +} + +/*! + * @brief Configure OPAMP negative port gain. + * + * @param base OPAMP peripheral base address. + * @param option OPAMP negative port gain. + */ +static inline void OPAMP_DoNegGainConfig(OPAMP_Type *base, opamp_negative_gain_t option) +{ + base->OPAMP_CTR = (((base->OPAMP_CTR) & (~OPAMP_OPAMP_CTR_NGAIN_MASK)) | OPAMP_OPAMP_CTR_NGAIN(option)); +} +/*! @} */ + +#if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN +/*! + * @name Reference Buffer Control Interface + * @{ + */ + +/*! + * @brief Enable reference buffer. + * + * @param base OPAMP peripheral base address. + * @param enable true to enable and false to disable. + */ +static inline void OPAMP_EnableRefBuffer(OPAMP_Type *base, bool enable) +{ + if (enable) + { + base->OPAMP_CTR |= OPAMP_OPAMP_CTR_BUFEN_MASK; + } + else + { + base->OPAMP_CTR &= ~(uint32_t)OPAMP_OPAMP_CTR_BUFEN_MASK; + } +} +/*! @} */ +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_BUFEN */ + +#if defined(FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD) && FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD +/*! + * @name Trigger Mode Control Interface + * @{ + */ + +/*! + * @brief Enable OPAMP trigger mode. + * + * @param base OPAMP peripheral base address. + * @param enable true to enable and false to disable. + */ +static inline void OPAMP_EnableTriggerMode(OPAMP_Type *base, bool enable) +{ + if (enable) + { + base->OPAMP_CTR |= OPAMP_OPAMP_CTR_TRIGMD_MASK; + } + else + { + base->OPAMP_CTR &= ~(uint32_t)OPAMP_OPAMP_CTR_TRIGMD_MASK; + } +} +/*! @} */ +#endif /* FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* FSL_OPAMP_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_ostimer.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_ostimer.c new file mode 100644 index 00000000000..d978556afbc --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_ostimer.c @@ -0,0 +1,384 @@ +/* + * Copyright 2018-2021, 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_ostimer.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ostimer" +#endif + +#if defined(OSTIMER_RSTS) +#define OSTIMER_RESETS_ARRAY OSTIMER_RSTS +#endif + +/* Typedef for interrupt handler. */ +typedef void (*ostimer_isr_t)(OSTIMER_Type *base, ostimer_callback_t cb); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base OSTIMER peripheral base address + * + * @return The OSTIMER instance + */ +static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base); + +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) +/* @brief Translate the value from gray-code to decimal by the Code Gray in SYSCTL. + * + * @param gray The gray value input. + * + * @return the decimal value. + */ +static uint64_t OSTIMER_GrayToDecimalbyCodeGray(uint64_t gray); +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of OSTIMER handle. */ +static ostimer_callback_t s_ostimerHandle[FSL_FEATURE_SOC_OSTIMER_COUNT]; +/* Array of OSTIMER peripheral base address. */ +static OSTIMER_Type *const s_ostimerBases[] = OSTIMER_BASE_PTRS; +/* Array of OSTIMER IRQ number. */ +static const IRQn_Type s_ostimerIRQ[] = OSTIMER_IRQS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of OSTIMER clock name. */ +static const clock_ip_name_t s_ostimerClock[] = OSTIMER_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* OSTIMER ISR for transactional APIs. */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +static ostimer_isr_t s_ostimerIsr = (ostimer_isr_t)DefaultISR; +#else +static ostimer_isr_t s_ostimerIsr; +#endif + +#if defined(OSTIMER_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_ostimerResets[] = OSTIMER_RESETS_ARRAY; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* @brief Function for getting the instance number of OS timer. */ +static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_ostimerBases); instance++) + { + if (s_ostimerBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_ostimerBases)); + + return instance; +} + +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) +/* @brief Translate the value from gray-code to decimal by the Code Gray in SYSCTL. + * + * @param gray The gray value input. + * + * @return the decimal value. + */ +static uint64_t OSTIMER_GrayToDecimalbyCodeGray(uint64_t gray) +{ + uint64_t decOut; + + SYSCTL->CODE_GRAY_LSB = (uint32_t)(gray & 0xFFFFFFFFU); + SYSCTL->CODE_GRAY_MSB = (uint32_t)((gray >> 32U) & 0x3FFU); // limit to 42bits as OSevent timer + __NOP(); + decOut = ((uint64_t)(SYSCTL->CODE_BIN_MSB) & 0x3FFU) << 32U; + decOut |= (uint64_t)(SYSCTL->CODE_BIN_LSB); + + return decOut; +} +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ + +/* @brief Translate the value from gray-code to decimal. */ +/* + * @param gray The gray value input. + * + * @return the decimal value. + */ +uint64_t OSTIMER_GrayToDecimal(uint64_t gray) +{ +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) + return OSTIMER_GrayToDecimalbyCodeGray(gray); +#else + uint64_t temp = gray; + while (temp != 0U) + { + temp >>= 1U; + gray ^= temp; + } + + return gray; +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ +} + +/* @brief Enable the OSTIMER interrupt. + * + * After calling this function, the OSTIMER driver will enable/disable the IRQ and module interrupt enablement. + * + * @param base OSTIMER peripheral base address. + * @param enable enable/disable the IRQ and module interrupt enablement. + * - true: Disable the IRQ and module interrupt enablement. + * - false: Disable the IRQ and module interrupt enablement. + * @return none + */ +static void OSTIMER_EnableInterrupt(OSTIMER_Type *base, bool enable) +{ + assert(NULL != base); + + if (enable) + { + /* Enable the IRQ and module interrupt enablement. */ + (void)EnableIRQ(s_ostimerIRQ[OSTIMER_GetInstance(base)]); + base->OSEVENT_CTRL |= OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; + } + else + { + /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ + (void)DisableIRQ(s_ostimerIRQ[OSTIMER_GetInstance(base)]); + base->OSEVENT_CTRL &= ~OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; /* Clear interrupt flag by writing 1. */ + } +} + +/*! + * @brief Initializes an OSTIMER by turning it's clock on. + * + */ +void OSTIMER_Init(OSTIMER_Type *base) +{ + assert(NULL != base); + + uint32_t instance = OSTIMER_GetInstance(base); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if !(defined(FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) && FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) + /* Enable the OSTIMER 32k clock in PMC module. */ + CLOCK_EnableOstimer32kClock(); +#endif + /* Enable clock for OSTIMER. */ + CLOCK_EnableClock(s_ostimerClock[instance]); +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) + CLOCK_EnableClock(kCLOCK_Sysctl); +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(OSTIMER_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_ostimerResets[OSTIMER_GetInstance(base)]); +#endif +} + +/*! + * @brief Deinitializes a OSTIMER instance. + * + * This function shuts down OSTIMER clock + * + * @param base OSTIMER peripheral base address. + */ +void OSTIMER_Deinit(OSTIMER_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable clock for OSTIMER. */ + CLOCK_DisableClock(s_ostimerClock[OSTIMER_GetInstance(base)]); +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) + CLOCK_DisableClock(kCLOCK_Sysctl); +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief Get OSTIMER status Flags. + * + * This returns the status flag. + * Currently, only match interrupt flag can be got. + * + * @param base OSTIMER peripheral base address. + * @return status register value + */ +uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base) +{ + return base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK; +} + +/*! + * @brief Clear Status Interrupt Flags. + * + * This clears intr status flag. + * Currently, only match interrupt flag can be cleared. + * + * @param base OSTIMER peripheral base address. + * @param mask Clear bit mask. + * @return none + */ +void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask) +{ + base->OSEVENT_CTRL |= mask; +} + +/*! + * @brief Set the match raw value for OSTIMER. + * + * This function will set a match value for OSTIMER with an optional callback. And this callback + * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. + * Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue(). + * + * @param base OSTIMER peripheral base address. + * @param count OSTIMER timer match value.(Value is gray-code format) + * + * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). + * @retval kStatus_Success - Set match raw value and enable interrupt Successfully. + * @retval kStatus_Fail - Set match raw value fail. + */ +status_t OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) +{ +#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK + uint64_t decValueTimer; +#endif + status_t status; + uint64_t tmp = count; + uint32_t instance = OSTIMER_GetInstance(base); + + /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ + OSTIMER_EnableInterrupt(base, false); + + s_ostimerIsr = OSTIMER_HandleIRQ; + s_ostimerHandle[instance] = cb; + + /* Set the match value. */ + base->MATCH_L = (uint32_t)tmp; + base->MATCH_H = (uint32_t)(tmp >> 32U); + +#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK + /* Workaround-2019-12-30: + * Since OSTimer's counter register is Gray-encoded, it would cost more time to write register. When EVTimer Match + * Write Ready bit is low, which means the previous match value has been updated successfully by that time, it is + * safe to reload (write) the Match Registers. Even if there is the RM comment that "In typical applications, it + * should not be necessary to test this bit", but we found the interruption would not be reported when the delta + * timer user added is smaller(IE: RT595 11us in 1MHz typical application) in release version." To prevent such + * issue from happening, we'd better wait for the match value to update successfully before enabling IRQ. + */ + while (0U != (base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)) + { + } + + /* After the WR_RDY bit became low, we need to check whether current time goes ahead of the match value we set. + * (1) If current timer value has gone ahead of the match value, the interrupt will not be reported before 64-bit + * timer value over flow. We need to check whether the interrupt flag has been set or not: if yes, we will enable + * interrupt and return success; if not, we will return fail directly. + * (2) If current timer value has not gone ahead of match value, we will enable interrupt and return success. + */ + decValueTimer = OSTIMER_GetCurrentTimerValue(base); + if ((decValueTimer >= OSTIMER_GrayToDecimal(tmp)) && + (0U == (base->OSEVENT_CTRL & (uint32_t)kOSTIMER_MatchInterruptFlag))) + { + status = kStatus_Fail; + } + else +#endif /* #ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK */ + { + /* Enable the module interrupt enablement. */ + OSTIMER_EnableInterrupt(base, true); + status = kStatus_Success; + } + + return status; +} + +/*! + * @brief Set the match value for OSTIMER. + * + * This function will set a match value for OSTIMER with an optional callback. And this callback + * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. + * + * @param base OSTIMER peripheral base address. + * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code in + * API. ) + * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). + * @retval kStatus_Success - Set match value and enable interrupt Successfully. + * @retval kStatus_Fail - Set match value fail. + */ +status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) +{ + uint64_t tmp = OSTIMER_DecimalToGray(count); + + return OSTIMER_SetMatchRawValue(base, tmp, cb); +} + +/*! + * @brief Get current timer count value from OSTIMER. + * + * This function will get a decimal timer count value. + * The RAW value of timer count is gray code format, will be translated to decimal data internally. + * + * @param base OSTIMER peripheral base address. + * @return Value of OSTIMER which will formated to decimal value. + */ +uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base) +{ + uint64_t tmp = 0U; + + tmp = OSTIMER_GetCurrentTimerRawValue(base); + + return OSTIMER_GrayToDecimal(tmp); +} + +/*! + * @brief Get the capture value from OSTIMER. + * + * This function will get a capture decimal-value from OSTIMER. + * The RAW value of timer capture is gray code format, will be translated to decimal data internally. + * + * @param base OSTIMER peripheral base address. + * @return Value of capture register, data format is decimal. + */ +uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base) +{ + uint64_t tmp = 0U; + + tmp = OSTIMER_GetCaptureRawValue(base); + + return OSTIMER_GrayToDecimal(tmp); +} + +void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb) +{ + /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ + OSTIMER_EnableInterrupt(base, false); + + if (cb != NULL) + { + cb(); + } +} + +void OS_EVENT_DriverIRQHandler(void); +void OS_EVENT_DriverIRQHandler(void) +{ + s_ostimerIsr(s_ostimerBases[0], s_ostimerHandle[0]); + SDK_ISR_EXIT_BARRIER; +} + diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_ostimer.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_ostimer.h new file mode 100644 index 00000000000..51b1f45503f --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_ostimer.h @@ -0,0 +1,273 @@ +/* + * Copyright 2018-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_OSTIMER_H_ +#define FSL_OSTIMER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ostimer + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief OSTIMER driver version. */ +#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) +/*! @} */ + +/*! + * @brief OSTIMER status flags. + */ +enum _ostimer_flags +{ + kOSTIMER_MatchInterruptFlag = (OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK), /*!< Match interrupt flag bit, sets if + the match value was reached. */ +}; + +/*! @brief ostimer callback function. */ +typedef void (*ostimer_callback_t)(void); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an OSTIMER by turning its bus clock on + * + */ +void OSTIMER_Init(OSTIMER_Type *base); + +/*! + * @brief Deinitializes a OSTIMER instance. + * + * This function shuts down OSTIMER bus clock + * + * @param base OSTIMER peripheral base address. + */ +void OSTIMER_Deinit(OSTIMER_Type *base); + +/*! + * @brief Translate the value from gray-code to decimal. + * + * @param gray The gray value input. + * @return The decimal value. + */ +uint64_t OSTIMER_GrayToDecimal(uint64_t gray); + +/*! + * @brief Translate the value from decimal to gray-code. + * + * @param dec The decimal value. + * @return The gray code of the input value. + */ +static inline uint64_t OSTIMER_DecimalToGray(uint64_t dec) +{ + return (dec ^ (dec >> 1U)); +} + +/*! + * @brief Get OSTIMER status Flags. + * + * This returns the status flag. + * Currently, only match interrupt flag can be got. + * + * @param base OSTIMER peripheral base address. + * @return status register value + */ +uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base); + +/*! + * @brief Clear Status Interrupt Flags. + * + * This clears intrrupt status flag. + * Currently, only match interrupt flag can be cleared. + * + * @param base OSTIMER peripheral base address. + * @param mask Clear bit mask. + * @return none + */ +void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask); + +/*! + * @brief Set the match raw value for OSTIMER. + * + * This function will set a match value for OSTIMER with an optional callback. And this callback + * will be called while the data in dedicated pair match register is equals to the value of central EVTIMER. + * Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue(). + * + * @param base OSTIMER peripheral base address. + * @param count OSTIMER timer match value.(Value is gray-code format) + * + * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). + * @retval kStatus_Success - Set match raw value and enable interrupt Successfully. + * @retval kStatus_Fail - Set match raw value fail. + */ +status_t OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); + +/*! + * @brief Set the match value for OSTIMER. + * + * This function will set a match value for OSTIMER with an optional callback. And this callback + * will be called while the data in dedicated pair match register is equals to the value of central OS TIMER. + * + * @param base OSTIMER peripheral base address. + * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code + * internally.) + * + * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). + * @retval kStatus_Success - Set match value and enable interrupt Successfully. + * @retval kStatus_Fail - Set match value fail. + */ +status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); + +/*! + * @brief Set value to OSTIMER MATCH register directly. + * + * This function writes the input value to OSTIMER MATCH register directly, + * it does not touch any other registers. Note that, the data format is + * gray-code. The function @ref OSTIMER_DecimalToGray could convert decimal + * value to gray code. + * + * @param base OSTIMER peripheral base address. + * @param value OSTIMER timer match value (Value is gray-code format). + */ +static inline void OSTIMER_SetMatchRegister(OSTIMER_Type *base, uint64_t value) +{ +#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK + /* Wait for MATCH register ready for write. */ + while (0U != (base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)) + { + } +#endif + + base->MATCH_L = (uint32_t)value; + base->MATCH_H = (uint32_t)(value >> 32U); +} + +/*! + * @brief Enable the OSTIMER counter match interrupt. + * + * Enable the timer counter match interrupt. The interrupt happens when OSTIMER + * counter matches the value in MATCH registers. + * + * @param base OSTIMER peripheral base address. + */ +static inline void OSTIMER_EnableMatchInterrupt(OSTIMER_Type *base) +{ + base->OSEVENT_CTRL |= OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; +} + +/*! + * @brief Disable the OSTIMER counter match interrupt. + * + * Disable the timer counter match interrupt. The interrupt happens when OSTIMER + * counter matches the value in MATCH registers. + * + * @param base OSTIMER peripheral base address. + */ +static inline void OSTIMER_DisableMatchInterrupt(OSTIMER_Type *base) +{ + base->OSEVENT_CTRL &= ~OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; +} + +/*! + * @brief Get current timer raw count value from OSTIMER. + * + * This function will get a gray code type timer count value from OS timer register. + * The raw value of timer count is gray code format. + * + * @param base OSTIMER peripheral base address. + * @return Raw value of OSTIMER, gray code format. + */ +static inline uint64_t OSTIMER_GetCurrentTimerRawValue(OSTIMER_Type *base) +{ + uint64_t tmp = 0U; + + tmp = base->EVTIMERL; + tmp |= (uint64_t)(base->EVTIMERH) << 32U; + + return tmp; +} + +/*! + * @brief Get current timer count value from OSTIMER. + * + * This function will get a decimal timer count value. + * The RAW value of timer count is gray code format, will be translated to decimal data internally. + * + * @param base OSTIMER peripheral base address. + * @return Value of OSTIMER which will be formated to decimal value. + */ +uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base); + +/*! + * @brief Get the capture value from OSTIMER. + * + * This function will get a captured gray-code value from OSTIMER. + * The Raw value of timer capture is gray code format. + * + * @param base OSTIMER peripheral base address. + * @return Raw value of capture register, data format is gray code. + */ +static inline uint64_t OSTIMER_GetCaptureRawValue(OSTIMER_Type *base) +{ + uint64_t tmp = 0U; + + tmp = base->CAPTURE_L; + tmp |= (uint64_t)(base->CAPTURE_H) << 32U; + + return tmp; +} + +/*! + * @brief Get the capture value from OSTIMER. + * + * This function will get a capture decimal-value from OSTIMER. + * The RAW value of timer capture is gray code format, will be translated to decimal data internally. + * + * @param base OSTIMER peripheral base address. + * @return Value of capture register, data format is decimal. + */ +uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base); + +/*! + * @brief OS timer interrupt Service Handler. + * + * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request + * in OSTIMER_SetMatchValue()). + * if no user callback is scheduled, the interrupt will simply be cleared. + * + * @param base OS timer peripheral base address. + * @param cb callback scheduled for this instance of OS timer + * @return none + */ +void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb); +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_OSTIMER_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_port.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_port.h new file mode 100644 index 00000000000..8eb512969d8 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_port.h @@ -0,0 +1,684 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022, 2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_PORT_H_ +#define FSL_PORT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup port + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.port" +#endif + +/*! @name Driver version */ +/*! @{ */ +/*! @brief PORT driver version. */ +#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 5, 0)) +/*! @} */ + +#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE +/*! @brief Internal resistor pull feature selection */ +enum _port_pull +{ + kPORT_PullDisable = 0U, /*!< Internal pull-up/down resistor is disabled. */ + kPORT_PullDown = 2U, /*!< Internal pull-down resistor is enabled. */ + kPORT_PullUp = 3U, /*!< Internal pull-up resistor is enabled. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */ + +#if defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE +/*! @brief Internal resistor pull value selection */ +enum _port_pull_value +{ + kPORT_LowPullResistor = 0U, /*!< Low internal pull resistor value is selected. */ + kPORT_HighPullResistor = 1U, /*!< High internal pull resistor value is selected. */ +}; +#endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */ + +#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE +/*! @brief Slew rate selection */ +enum _port_slew_rate +{ + kPORT_FastSlewRate = 0U, /*!< Fast slew rate is configured. */ + kPORT_SlowSlewRate = 1U, /*!< Slow slew rate is configured. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */ + +#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN +/*! @brief Open Drain feature enable/disable */ +enum _port_open_drain_enable +{ + kPORT_OpenDrainDisable = 0U, /*!< Open drain output is disabled. */ + kPORT_OpenDrainEnable = 1U, /*!< Open drain output is enabled. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */ + +#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER +/*! @brief Passive filter feature enable/disable */ +enum _port_passive_filter_enable +{ + kPORT_PassiveFilterDisable = 0U, /*!< Passive input filter is disabled. */ + kPORT_PassiveFilterEnable = 1U, /*!< Passive input filter is enabled. */ +}; +#endif + +#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH +/*! @brief Configures the drive strength. */ +enum _port_drive_strength +{ + kPORT_LowDriveStrength = 0U, /*!< Low-drive strength is configured. */ + kPORT_HighDriveStrength = 1U, /*!< High-drive strength is configured. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */ + +#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 +/*! @brief Configures the drive strength1. */ +enum _port_drive_strength1 +{ + kPORT_NormalDriveStrength = 0U, /*!< Normal drive strength */ + kPORT_DoubleDriveStrength = 1U, /*!< Double drive strength */ +}; +#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 */ + +#if defined(FSL_FEATURE_PORT_HAS_INPUT_BUFFER) && FSL_FEATURE_PORT_HAS_INPUT_BUFFER +/*! @brief input buffer disable/enable. */ +enum _port_input_buffer +{ + kPORT_InputBufferDisable = 0U, /*!< Digital input is disabled */ + kPORT_InputBufferEnable = 1U, /*!< Digital input is enabled */ +}; +#endif /* FSL_FEATURE_PORT_HAS_INPUT_BUFFER */ + +#if defined(FSL_FEATURE_PORT_HAS_INVERT_INPUT) && FSL_FEATURE_PORT_HAS_INVERT_INPUT +/*! @brief Digital input is not inverted or it is inverted. */ +enum _port_invet_input +{ + kPORT_InputNormal = 0U, /*!< Digital input is not inverted */ + kPORT_InputInvert = 1U, /*!< Digital input is inverted */ +}; +#endif /* FSL_FEATURE_PORT_HAS_INVERT_INPUT */ + +#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK +/*! @brief Unlock/lock the pin control register field[15:0] */ +enum _port_lock_register +{ + kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */ + kPORT_LockRegister = 1U, /*!< Pin Control Register fields [15:0] are locked. */ +}; +#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */ + +#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH +/*! @brief Pin mux selection */ +typedef enum _port_mux +{ +#if defined(FSL_FEATURE_PORT_PCR_MUX_GPIO) && (FSL_FEATURE_PORT_PCR_MUX_GPIO == 0) + kPORT_MuxAsGpio = 0U, /*!< Corresponding pin is configured as GPIO. */ +#else + kPORT_PinDisabledOrAnalog = 0U, /*!< Corresponding pin is disabled, but is used as an analog pin. */ + kPORT_MuxAsGpio = 1U, /*!< Corresponding pin is configured as GPIO. */ +#endif + kPORT_MuxAlt0 = 0U, /*!< Chip-specific */ + kPORT_MuxAlt1 = 1U, /*!< Chip-specific */ + kPORT_MuxAlt2 = 2U, /*!< Chip-specific */ + kPORT_MuxAlt3 = 3U, /*!< Chip-specific */ + kPORT_MuxAlt4 = 4U, /*!< Chip-specific */ + kPORT_MuxAlt5 = 5U, /*!< Chip-specific */ + kPORT_MuxAlt6 = 6U, /*!< Chip-specific */ + kPORT_MuxAlt7 = 7U, /*!< Chip-specific */ + kPORT_MuxAlt8 = 8U, /*!< Chip-specific */ + kPORT_MuxAlt9 = 9U, /*!< Chip-specific */ + kPORT_MuxAlt10 = 10U, /*!< Chip-specific */ + kPORT_MuxAlt11 = 11U, /*!< Chip-specific */ + kPORT_MuxAlt12 = 12U, /*!< Chip-specific */ + kPORT_MuxAlt13 = 13U, /*!< Chip-specific */ + kPORT_MuxAlt14 = 14U, /*!< Chip-specific */ + kPORT_MuxAlt15 = 15U, /*!< Chip-specific */ +} port_mux_t; +#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */ + +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +/*! @brief Configures the interrupt generation condition. */ +typedef enum _port_interrupt +{ + kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */ +#if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST || defined(DOXYGEN_OUTPUT) + kPORT_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */ + kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */ + kPORT_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */ +#endif +#if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG || defined(DOXYGEN_OUTPUT) + kPORT_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */ + kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */ + kPORT_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */ +#endif + kPORT_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */ + kPORT_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */ + kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */ + kPORT_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */ + kPORT_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */ +#if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER || defined(DOXYGEN_OUTPUT) + kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high-trigger output. */ + kPORT_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low-trigger output. */ +#endif +} port_interrupt_t; +#endif + +#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER +/*! @brief Digital filter clock source selection */ +typedef enum _port_digital_filter_clock_source +{ + kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */ + kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */ +} port_digital_filter_clock_source_t; + +/*! @brief PORT digital filter feature configuration definition */ +typedef struct _port_digital_filter_config +{ + uint32_t digitalFilterWidth; /*!< Set digital filter width */ + port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */ +} port_digital_filter_config_t; +#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */ + +#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH +/*! @brief PORT pin configuration structure */ +typedef struct _port_pin_config +{ +#if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE + uint16_t pullSelect : 2; /*!< No-pull/pull-down/pull-up select */ +#else + uint16_t : 2; +#endif /* FSL_FEATURE_PORT_HAS_PULL_ENABLE */ + +#if defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE + uint16_t pullValueSelect : 1; /*!< Pull value select */ +#endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */ + +#if defined(FSL_FEATURE_PORT_HAS_SLEW_RATE) && FSL_FEATURE_PORT_HAS_SLEW_RATE + uint16_t slewRate : 1; /*!< Fast/slow slew rate Configure */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_SLEW_RATE */ + +#if !(defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */ + +#if defined(FSL_FEATURE_PORT_HAS_PASSIVE_FILTER) && FSL_FEATURE_PORT_HAS_PASSIVE_FILTER + uint16_t passiveFilterEnable : 1; /*!< Passive filter enable/disable */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_PASSIVE_FILTER */ + +#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN + uint16_t openDrainEnable : 1; /*!< Open drain enable/disable */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */ + +#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH + uint16_t driveStrength : 1; /*!< Fast/slow drive strength configure */ +#else + uint16_t : 1; +#endif + +#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 + uint16_t driveStrength1 : 1; /*!< Normal/Double drive strength enable/disable */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 */ + +#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 3) + uint16_t mux : 3; /*!< Pin mux Configure */ + uint16_t : 1; +#elif defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && (FSL_FEATURE_PORT_PCR_MUX_WIDTH == 4) + uint16_t mux : 4; /*!< Pin mux Configure */ +#else + uint16_t : 4; +#endif + +#if defined(FSL_FEATURE_PORT_HAS_INPUT_BUFFER) && FSL_FEATURE_PORT_HAS_INPUT_BUFFER + uint16_t inputBuffer : 1; /*!< Input Buffer Configure */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_INPUT_BUFFER */ + +#if defined(FSL_FEATURE_PORT_HAS_INVERT_INPUT) && FSL_FEATURE_PORT_HAS_INVERT_INPUT + uint16_t invertInput : 1; /*!< Invert Input Configure */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_INVERT_INPUT */ + + uint16_t : 1; + +#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK + uint16_t lockRegister : 1; /*!< Lock/unlock the PCR field[15:0] */ +#else + uint16_t : 1; +#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */ +} port_pin_config_t; +#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */ + +#if defined(FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER +/*! @brief PORT version information. */ +typedef struct _port_version_info +{ + uint16_t feature; /*!< Feature Specification Number. */ + uint8_t minor; /*!< Minor Version Number. */ + uint8_t major; /*!< Major Version Number. */ +} port_version_info_t; +#endif /* FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER */ + +#if defined(FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE) && FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE +/*! @brief PORT voltage range. */ +typedef enum _port_voltage_range +{ + kPORT_VoltageRange1Dot71V_3Dot6V = 0x0U, /*!< Port voltage range is 1.71 V - 3.6 V. */ + kPORT_VoltageRange2Dot70V_3Dot6V = 0x1U, /*!< Port voltage range is 2.70 V - 3.6 V. */ +} port_voltage_range_t; +#endif /* FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @name Configuration */ +/*! @{ */ + +#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH + +#if defined(FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER +/*! + * @brief Get PORT version information. + * + * @param base PORT peripheral base pointer + * @param info PORT version information + */ +static inline void PORT_GetVersionInfo(PORT_Type *base, port_version_info_t *info) +{ + uint32_t verid = base->VERID; + info->feature = (uint16_t)verid; + info->minor = (uint8_t)(verid >> PORT_VERID_MINOR_SHIFT); + info->major = (uint8_t)(verid >> PORT_VERID_MAJOR_SHIFT); +} +#endif /* FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER */ + +#if defined(FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE) && FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE +/*! + * @brief Get PORT version information. + * + * @note : PORTA_CONFIG[RANGE] controls the voltage ranges of Port A, B, and C. Read or write PORTB_CONFIG[RANGE] and + * PORTC_CONFIG[RANGE] does not take effect. + * + * @param base PORT peripheral base pointer + * @param range port voltage range + */ +static inline void PORT_SecletPortVoltageRange(PORT_Type *base, port_voltage_range_t range) +{ + base->CONFIG = (uint32_t)range; +} +#endif /* FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE */ + +/*! + * @brief Sets the port PCR register. + * + * This is an example to define an input pin or output pin PCR configuration. + * @code + * // Define a digital input pin PCR configuration + * port_pin_config_t config = { + * kPORT_PullUp, + * kPORT_FastSlewRate, + * kPORT_PassiveFilterDisable, + * kPORT_OpenDrainDisable, + * kPORT_LowDriveStrength, + * kPORT_MuxAsGpio, + * kPORT_UnLockRegister, + * }; + * @endcode + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param config PORT PCR register configuration structure. + */ +static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config) +{ + assert(config); + uint32_t addr = (uint32_t)&base->PCR[pin]; + *(volatile uint16_t *)(addr) = *((const uint16_t *)(const void *)config); +} + +/*! + * @brief Sets the port PCR register for multiple pins. + * + * This is an example to define input pins or output pins PCR configuration. + * @code + * Define a digital input pin PCR configuration + * port_pin_config_t config = { + * kPORT_PullUp , + * kPORT_PullEnable, + * kPORT_FastSlewRate, + * kPORT_PassiveFilterDisable, + * kPORT_OpenDrainDisable, + * kPORT_LowDriveStrength, + * kPORT_MuxAsGpio, + * kPORT_UnlockRegister, + * }; + * @endcode + * + * @param base PORT peripheral base pointer. + * @param mask PORT pin number macro. + * @param config PORT PCR register configuration structure. + */ +static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config) +{ + assert(config); + + uint16_t pcrl = *((const uint16_t *)(const void *)config); + + if (0U != (mask & 0xffffU)) + { + base->GPCLR = ((mask & 0xffffU) << 16) | pcrl; + } + if (0U != (mask >> 16)) + { + base->GPCHR = (mask & 0xffff0000U) | pcrl; + } +} + +#if defined(FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG) && FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG +/*! + * @brief Sets the port interrupt configuration in PCR register for multiple pins. + * + * @param base PORT peripheral base pointer. + * @param mask PORT pin number macro. + * @param config PORT pin interrupt configuration. + * - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled. + * - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit). + * - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit). + * - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit). + * - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit). + * - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit). + * - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit). + * - #kPORT_InterruptLogicZero : Interrupt when logic zero. + * - #kPORT_InterruptRisingEdge : Interrupt on rising edge. + * - #kPORT_InterruptFallingEdge: Interrupt on falling edge. + * - #kPORT_InterruptEitherEdge : Interrupt on either edge. + * - #kPORT_InterruptLogicOne : Interrupt when logic one. + * - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit). + * - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit).. + */ +static inline void PORT_SetMultipleInterruptPinsConfig(PORT_Type *base, uint32_t mask, port_interrupt_t config) +{ + assert(config); + + if (0U != ((uint32_t)mask & 0xffffU)) + { + base->GICLR = ((uint32_t)config << 16U) | ((uint32_t)mask & 0xffffU); + } + mask = mask >> 16; + if (0U != mask) + { + base->GICHR = ((uint32_t)config << 16U) | ((uint32_t)mask & 0xffffU); + } +} +#endif + +/*! + * @brief Configures the pin muxing. + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param mux pin muxing slot selection. + * - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function. + * - #kPORT_MuxAsGpio : Set as GPIO. + * - #kPORT_MuxAlt2 : chip-specific. + * - #kPORT_MuxAlt3 : chip-specific. + * - #kPORT_MuxAlt4 : chip-specific. + * - #kPORT_MuxAlt5 : chip-specific. + * - #kPORT_MuxAlt6 : chip-specific. + * - #kPORT_MuxAlt7 : chip-specific. + * @note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because + * the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux is + * reset to zero : kPORT_PinDisabledOrAnalog). + * This function is recommended to use to reset the pin mux + * + */ +static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux) +{ + base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux); +} +#endif /* FSL_FEATURE_PORT_PCR_MUX_WIDTH */ + +#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER + +/*! + * @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin. + * + * @param base PORT peripheral base pointer. + * @param mask PORT pin number macro. + * @param enable PORT digital filter configuration. + */ +static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable) +{ + if (enable == true) + { + base->DFER |= mask; + } + else + { + base->DFER &= ~mask; + } +} + +/*! + * @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin. + * + * @param base PORT peripheral base pointer. + * @param config PORT digital filter configuration structure. + */ +static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config) +{ + assert(config); + + base->DFCR = PORT_DFCR_CS(config->clockSource); + base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth); +} + +#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */ +/*! @} */ + +/*! @name Interrupt */ +/*! @{ */ + +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +/*! + * @brief Configures the port pin interrupt/DMA request. + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param config PORT pin interrupt configuration. + * - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled. + * - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit). + * - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit). + * - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit). + * - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit). + * - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit). + * - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit). + * - #kPORT_InterruptLogicZero : Interrupt when logic zero. + * - #kPORT_InterruptRisingEdge : Interrupt on rising edge. + * - #kPORT_InterruptFallingEdge: Interrupt on falling edge. + * - #kPORT_InterruptEitherEdge : Interrupt on either edge. + * - #kPORT_InterruptLogicOne : Interrupt when logic one. + * - #kPORT_ActiveHighTriggerOutputEnable : Enable active high-trigger output (if the trigger states exit). + * - #kPORT_ActiveLowTriggerOutputEnable : Enable active low-trigger output (if the trigger states exit). + */ +static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config) +{ + base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config); +} +#endif + +#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH +/*! + * @brief Configures the port pin drive strength. + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param strength PORT pin drive strength + * - #kPORT_LowDriveStrength = 0U - Low-drive strength is configured. + * - #kPORT_HighDriveStrength = 1U - High-drive strength is configured. + */ +static inline void PORT_SetPinDriveStrength(PORT_Type *base, uint32_t pin, uint8_t strength) +{ + base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE_MASK) | PORT_PCR_DSE(strength); +} +#endif + +#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH1 +/*! + * @brief Enables the port pin double drive strength. + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param enable PORT pin drive strength configuration. + */ +static inline void PORT_EnablePinDoubleDriveStrength(PORT_Type *base, uint32_t pin, bool enable) +{ + base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE1_MASK) | PORT_PCR_DSE1(enable); +} +#endif + +#if defined(FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE) && FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE +/*! + * @brief Configures the port pin pull value. + * + * @param base PORT peripheral base pointer. + * @param pin PORT pin number. + * @param value PORT pin pull value + * - #kPORT_LowPullResistor = 0U - Low internal pull resistor value is selected. + * - #kPORT_HighPullResistor = 1U - High internal pull resistor value is selected. + */ +static inline void PORT_SetPinPullValue(PORT_Type *base, uint32_t pin, uint8_t value) +{ + base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_PV_MASK) | PORT_PCR_PV(value); +} +#endif /* FSL_FEATURE_PORT_PCR_HAS_PULL_VALUE */ + +#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) +/*! + * @brief Reads the whole port status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base PORT peripheral base pointer. + * @return Current port interrupt status flags, for example, 0x00010001 means the + * pin 0 and 16 have the interrupt. + */ +static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base) +{ + return base->ISFR; +} + +/*! + * @brief Clears the multiple pin interrupt status flag. + * + * @param base PORT peripheral base pointer. + * @param mask PORT pin number macro. + */ +static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask) +{ + base->ISFR = mask; +} +#endif + +#if defined(FSL_FEATURE_PORT_SUPPORT_EFT) && FSL_FEATURE_PORT_SUPPORT_EFT +/*! + * @brief Get EFT detect flags. + * + * @param base PORT peripheral base pointer + * @return EFT detect flags + */ +static inline uint32_t PORT_GetEFTDetectFlags(PORT_Type *base) +{ + return base->EDFR; +} + +/*! + * @brief Enable EFT detect interrupts. + * + * @param base PORT peripheral base pointer + * @param interrupt EFT detect interrupt + */ +static inline void PORT_EnableEFTDetectInterrupts(PORT_Type *base, uint32_t interrupt) +{ + base->EDIER |= interrupt; +} + +/*! + * @brief Disable EFT detect interrupts. + * + * @param base PORT peripheral base pointer + * @param interrupt EFT detect interrupt + */ +static inline void PORT_DisableEFTDetectInterrupts(PORT_Type *base, uint32_t interrupt) +{ + base->EDIER &= ~interrupt; +} + +/*! + * @brief Clear all low EFT detector. + * + * @note : Port B and Port C pins share the same EFT detector clear control from PORTC_EDCR register. Any write to the + * PORTB_EDCR does not take effect. + * @param base PORT peripheral base pointer + * @param interrupt EFT detect interrupt + */ +static inline void PORT_ClearAllLowEFTDetectors(PORT_Type *base) +{ + base->EDCR |= PORT_EDCR_EDLC_MASK; + base->EDCR &= ~PORT_EDCR_EDLC_MASK; +} + +/*! + * @brief Clear all high EFT detector. + * + * @param base PORT peripheral base pointer + * @param interrupt EFT detect interrupt + */ +static inline void PORT_ClearAllHighEFTDetectors(PORT_Type *base) +{ + base->EDCR |= PORT_EDCR_EDHC_MASK; + base->EDCR &= ~PORT_EDCR_EDHC_MASK; +} +#endif /* FSL_FEATURE_PORT_SUPPORT_EFT */ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_PORT_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_pwm.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_pwm.c new file mode 100644 index 00000000000..7fe51bcc779 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_pwm.c @@ -0,0 +1,1491 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_pwm.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pwm" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Get the instance from the base address + * + * @param base PWM peripheral base address + * + * @return The PWM module instance + */ +static uint32_t PWM_GetInstance(PWM_Type *base); + +#if defined(PWM_RSTS) +#define PWM_RESETS_ARRAY PWM_RSTS +#elif defined(FLEXPWM_RSTS) +#define PWM_RESETS_ARRAY FLEXPWM_RSTS +#elif defined(FLEXPWM_RSTS_N) +#define PWM_RESETS_ARRAY FLEXPWM_RSTS_N +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to PWM bases for each instance. */ +static PWM_Type *const s_pwmBases[] = PWM_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to PWM clocks for each PWM submodule. */ +static const clock_ip_name_t s_pwmClocks[][FSL_FEATURE_PWM_SUBMODULE_COUNT] = PWM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(PWM_RESETS_ARRAY) +/* Reset array */ +static const reset_ip_name_t s_pwmResets[] = PWM_RESETS_ARRAY; +#endif + +/*! @brief Temporary PWM duty cycle. */ +static uint8_t s_pwmGetPwmDutyCycle[FSL_FEATURE_PWM_SUBMODULE_COUNT][PWM_SUBMODULE_CHANNEL] = {{0}}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Complement the variable of type uint16_t as needed + * + * This function can complement the variable of type uint16_t as needed.For example, + * need to ask for the opposite of a positive integer. + * + * param value Parameters of type uint16_t + */ +static inline uint16_t PWM_GetComplementU16(uint16_t value) +{ + return (~value + 1U); +} + +static inline uint16_t dutyCycleToReloadValue(uint8_t dutyCyclePercent) +{ + /* Rounding calculations to improve the accuracy of reloadValue */ + return ((65535U * dutyCyclePercent) + 50U) / 100U; +} + +static uint32_t PWM_GetInstance(PWM_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_pwmBases); instance++) + { + if (s_pwmBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_pwmBases)); + + return instance; +} + +/*! + * brief Set register about period on one PWM submodule. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param mode PWM operation mode, options available in enumeration ::pwm_mode_t + * param pulseCnt PWM period, value should be between 0 to 65535 + */ +static void PWM_SetPeriodRegister(PWM_Type *base, pwm_submodule_t subModule, pwm_mode_t mode, uint16_t pulseCnt) +{ + uint16_t modulo = 0; + + switch (mode) + { + case kPWM_SignedCenterAligned: + /* Setup the PWM period for a signed center aligned signal */ + modulo = (pulseCnt >> 1U); + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = PWM_GetComplementU16(modulo); + /* Indicates the center value */ + base->SM[subModule].VAL0 = 0; + /* Indicates the end of the PWM period */ + /* The change during the end to start of the PWM period requires a count time */ + base->SM[subModule].VAL1 = modulo - 1U; + break; + case kPWM_CenterAligned: + /* Setup the PWM period for an unsigned center aligned signal */ + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = 0; + /* Indicates the center value */ + base->SM[subModule].VAL0 = (pulseCnt / 2U); + /* Indicates the end of the PWM period */ + /* The change during the end to start of the PWM period requires a count time */ + base->SM[subModule].VAL1 = pulseCnt - 1U; + break; + case kPWM_SignedEdgeAligned: + /* Setup the PWM period for a signed edge aligned signal */ + modulo = (pulseCnt >> 1U); + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = PWM_GetComplementU16(modulo); + /* Indicates the center value */ + base->SM[subModule].VAL0 = 0; + /* Indicates the end of the PWM period */ + /* The change during the end to start of the PWM period requires a count time */ + base->SM[subModule].VAL1 = modulo - 1U; + break; + case kPWM_EdgeAligned: + /* Setup the PWM period for a unsigned edge aligned signal */ + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = 0; + /* Indicates the center value */ + base->SM[subModule].VAL0 = (pulseCnt / 2U); + /* Indicates the end of the PWM period */ + /* The change during the end to start of the PWM period requires a count time */ + base->SM[subModule].VAL1 = pulseCnt - 1U; + break; + default: + assert(false); + break; + } +} + +/*! + * brief Set register about dutycycle on one PWM submodule. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmSignal Signal (PWM A or PWM B) to update + * param mode PWM operation mode, options available in enumeration ::pwm_mode_t + * param pulseCnt PWM period, value should be between 0 to 65535 + * param dutyCycle New PWM pulse width, value should be between 0 to 65535 + */ +static void PWM_SetDutycycleRegister(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmSignal, + pwm_mode_t mode, + uint16_t pulseCnt, + uint16_t pwmHighPulse) +{ + uint16_t modulo = 0; + + switch (mode) + { + case kPWM_SignedCenterAligned: + /* Setup the PWM dutycycle for a signed center aligned signal */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = PWM_GetComplementU16(pwmHighPulse / 2U); + base->SM[subModule].VAL3 = (pwmHighPulse / 2U); + } + else if (pwmSignal == kPWM_PwmB) + { + base->SM[subModule].VAL4 = PWM_GetComplementU16(pwmHighPulse / 2U); + base->SM[subModule].VAL5 = (pwmHighPulse / 2U); + } + else + { + ; /* Intentional empty */ + } + break; + case kPWM_CenterAligned: + /* Setup the PWM dutycycle for an unsigned center aligned signal */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2U); + base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2U); + } + else if (pwmSignal == kPWM_PwmB) + { + base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2U); + base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2U); + } + else + { + ; /* Intentional empty */ + } + break; + case kPWM_SignedEdgeAligned: + modulo = (pulseCnt >> 1U); + + /* Setup the PWM dutycycle for a signed edge aligned signal */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = PWM_GetComplementU16(modulo); + base->SM[subModule].VAL3 = PWM_GetComplementU16(modulo) + pwmHighPulse; + } + else if (pwmSignal == kPWM_PwmB) + { + base->SM[subModule].VAL4 = PWM_GetComplementU16(modulo); + base->SM[subModule].VAL5 = PWM_GetComplementU16(modulo) + pwmHighPulse; + } + else + { + ; /* Intentional empty */ + } + break; + case kPWM_EdgeAligned: + /* Setup the PWM dutycycle for a unsigned edge aligned signal */ + if (pwmSignal == kPWM_PwmA) + { + base->SM[subModule].VAL2 = 0; + base->SM[subModule].VAL3 = pwmHighPulse; + } + else if (pwmSignal == kPWM_PwmB) + { + base->SM[subModule].VAL4 = 0; + base->SM[subModule].VAL5 = pwmHighPulse; + } + else + { + ; /* Intentional empty */ + } + break; + default: + assert(false); + break; + } +} + +/*! + * brief Ungates the PWM submodule clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application using the PWM driver. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param config Pointer to user's PWM config structure. + * + * return kStatus_Success means success; else failed. + */ +status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t *config) +{ + assert(config); + + uint16_t reg; + + /* Source clock for submodule 0 cannot be itself */ + if ((config->clockSource == kPWM_Submodule0Clock) && (subModule == kPWM_Module_0)) + { + return kStatus_Fail; + } + + /* Reload source select clock for submodule 0 cannot be master reload */ + if ((config->reloadSelect == kPWM_MasterReload) && (subModule == kPWM_Module_0)) + { + return kStatus_Fail; + } + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Ungate the PWM submodule clock*/ + CLOCK_EnableClock(s_pwmClocks[PWM_GetInstance(base)][subModule]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(PWM_RESETS_ARRAY) + RESET_ReleasePeripheralReset(s_pwmResets[PWM_GetInstance(base)]); +#endif + + /* Clear the fault status flags */ + base->FSTS |= PWM_FSTS_FFLAG_MASK; + + reg = base->SM[subModule].CTRL2; + + /* Setup the submodule clock-source, control source of the INIT signal, + * source of the force output signal, operation in debug & wait modes and reload source select + */ + reg &= + ~(uint16_t)(PWM_CTRL2_CLK_SEL_MASK | PWM_CTRL2_FORCE_SEL_MASK | PWM_CTRL2_INIT_SEL_MASK | PWM_CTRL2_INDEP_MASK | +#if !defined(FSL_FEATURE_PWM_HAS_NO_WAITEN) || (!FSL_FEATURE_PWM_HAS_NO_WAITEN) + PWM_CTRL2_WAITEN_MASK | +#endif /* FSL_FEATURE_PWM_HAS_NO_WAITEN */ + PWM_CTRL2_DBGEN_MASK | PWM_CTRL2_RELOAD_SEL_MASK); + reg |= (PWM_CTRL2_CLK_SEL(config->clockSource) | PWM_CTRL2_FORCE_SEL(config->forceTrigger) | + PWM_CTRL2_INIT_SEL(config->initializationControl) | PWM_CTRL2_DBGEN(config->enableDebugMode) | +#if !defined(FSL_FEATURE_PWM_HAS_NO_WAITEN) || (!FSL_FEATURE_PWM_HAS_NO_WAITEN) + PWM_CTRL2_WAITEN(config->enableWait) | +#endif /* FSL_FEATURE_PWM_HAS_NO_WAITEN */ + PWM_CTRL2_RELOAD_SEL(config->reloadSelect)); + + /* Setup PWM A & B to be independent or a complementary-pair */ + switch (config->pairOperation) + { + case kPWM_Independent: + reg |= PWM_CTRL2_INDEP_MASK; + break; + case kPWM_ComplementaryPwmA: + base->MCTRL &= ~((uint16_t)1U << (PWM_MCTRL_IPOL_SHIFT + (uint16_t)subModule)); + break; + case kPWM_ComplementaryPwmB: + base->MCTRL |= ((uint16_t)1U << (PWM_MCTRL_IPOL_SHIFT + (uint16_t)subModule)); + break; + default: + assert(false); + break; + } + base->SM[subModule].CTRL2 = reg; + + reg = base->SM[subModule].CTRL; + + /* Setup the clock prescale, load mode and frequency */ + reg &= ~(uint16_t)(PWM_CTRL_PRSC_MASK | PWM_CTRL_LDFQ_MASK | PWM_CTRL_LDMOD_MASK); + reg |= (PWM_CTRL_PRSC(config->prescale) | PWM_CTRL_LDFQ(config->reloadFrequency)); + + /* Setup register reload logic */ + switch (config->reloadLogic) + { + case kPWM_ReloadImmediate: + reg |= PWM_CTRL_LDMOD_MASK; + break; + case kPWM_ReloadPwmHalfCycle: + reg |= PWM_CTRL_HALF_MASK; + reg &= (uint16_t)(~PWM_CTRL_FULL_MASK); + break; + case kPWM_ReloadPwmFullCycle: + reg &= (uint16_t)(~PWM_CTRL_HALF_MASK); + reg |= PWM_CTRL_FULL_MASK; + break; + case kPWM_ReloadPwmHalfAndFullCycle: + reg |= PWM_CTRL_HALF_MASK; + reg |= PWM_CTRL_FULL_MASK; + break; + default: + assert(false); + break; + } + base->SM[subModule].CTRL = reg; + + /* Set PWM output normal */ +#if defined(PWM_MASK_UPDATE_MASK) + base->MASK &= (uint16_t)(~(uint16_t)(PWM_MASK_MASKX_MASK | PWM_MASK_MASKA_MASK | PWM_MASK_MASKB_MASK | + PWM_MASK_UPDATE_MASK_MASK)); +#else + base->MASK &= ~(uint16_t)(PWM_MASK_MASKX_MASK | PWM_MASK_MASKA_MASK | PWM_MASK_MASKB_MASK); +#endif + + base->DTSRCSEL = 0U; + + /* Issue a Force trigger event when configured to trigger locally */ + if (config->forceTrigger == kPWM_Force_Local) + { + base->SM[subModule].CTRL2 |= PWM_CTRL2_FORCE(1U); + } + + return kStatus_Success; +} + +/*! + * brief Gate the PWM submodule clock + * + * param base PWM peripheral base address + * param subModule PWM submodule to deinitialize + */ +void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule) +{ + /* Stop the submodule */ + base->MCTRL &= ~((uint16_t)1U << (PWM_MCTRL_RUN_SHIFT + (uint16_t)subModule)); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Gate the PWM submodule clock*/ + CLOCK_DisableClock(s_pwmClocks[PWM_GetInstance(base)][subModule]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Fill in the PWM config struct with the default settings + * + * The default values are: + * code + * config->enableDebugMode = false; + * config->enableWait = false; + * config->reloadSelect = kPWM_LocalReload; + * config->clockSource = kPWM_BusClock; + * config->prescale = kPWM_Prescale_Divide_1; + * config->initializationControl = kPWM_Initialize_LocalSync; + * config->forceTrigger = kPWM_Force_Local; + * config->reloadFrequency = kPWM_LoadEveryOportunity; + * config->reloadLogic = kPWM_ReloadImmediate; + * config->pairOperation = kPWM_Independent; + * endcode + * param config Pointer to user's PWM config structure. + */ +void PWM_GetDefaultConfig(pwm_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* PWM is paused in debug mode */ + config->enableDebugMode = false; + /* PWM is paused in wait mode */ +#if !defined(FSL_FEATURE_PWM_HAS_NO_WAITEN) || (!FSL_FEATURE_PWM_HAS_NO_WAITEN) + config->enableWait = false; +#endif /* FSL_FEATURE_PWM_HAS_NO_WAITEN */ + /* PWM module uses the local reload signal to reload registers */ + config->reloadSelect = kPWM_LocalReload; + /* Use the IP Bus clock as source clock for the PWM submodule */ + config->clockSource = kPWM_BusClock; + /* Clock source prescale is set to divide by 1*/ + config->prescale = kPWM_Prescale_Divide_1; + /* Local sync causes initialization */ + config->initializationControl = kPWM_Initialize_LocalSync; + /* The local force signal, CTRL2[FORCE], from the submodule is used to force updates */ + config->forceTrigger = kPWM_Force_Local; + /* PWM reload frequency, reload opportunity is PWM half cycle or full cycle. + * This field is not used in Immediate reload mode + */ + config->reloadFrequency = kPWM_LoadEveryOportunity; + /* Buffered-registers get loaded with new values as soon as LDOK bit is set */ + config->reloadLogic = kPWM_ReloadImmediate; + /* PWM A & PWM B operate as 2 independent channels */ + config->pairOperation = kPWM_Independent; +} + +/*! + * brief Sets up the PWM signals for a PWM submodule. + * + * The function initializes the submodule according to the parameters passed in by the user. The function + * also sets up the value compare registers to match the PWM signal requirements. + * If the dead time insertion logic is enabled, the pulse period is reduced by the + * dead time period specified by the user. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param chnlParams Array of PWM channel parameters to configure the channel(s), PWMX submodule is not supported. + * param numOfChnls Number of channels to configure, this should be the size of the array passed in. + * Array size should not be more than 2 as each submodule has 2 pins to output PWM + * param mode PWM operation mode, options available in enumeration ::pwm_mode_t + * param pwmFreq_Hz PWM signal frequency in Hz + * param srcClock_Hz PWM source clock of correspond submodule in Hz. If source clock of submodule1,2,3 is from + * submodule0 AUX_CLK, its source clock is submodule0 source clock divided with submodule0 + * prescaler value instead of submodule0 source clock. + * + * return Returns kStatusFail if there was error setting up the signal; kStatusSuccess otherwise + */ +status_t PWM_SetupPwm(PWM_Type *base, + pwm_submodule_t subModule, + const pwm_signal_param_t *chnlParams, + uint8_t numOfChnls, + pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz) +{ + assert(chnlParams); + assert(pwmFreq_Hz); + assert(numOfChnls); + assert(srcClock_Hz); + + uint32_t pwmClock; + uint16_t pulseCnt = 0, pwmHighPulse = 0; + uint8_t i, polarityShift = 0, outputEnableShift = 0; + + for (i = 0; i < numOfChnls; i++) + { + if (chnlParams[i].pwmChannel == kPWM_PwmX) + { + /* PWMX configuration is not supported yet */ + return kStatus_Fail; + } + } + + /* Divide the clock by the prescale value */ + pwmClock = (srcClock_Hz / (1UL << ((base->SM[subModule].CTRL & PWM_CTRL_PRSC_MASK) >> PWM_CTRL_PRSC_SHIFT))); + pulseCnt = (uint16_t)(pwmClock / pwmFreq_Hz); + + /* Setup each PWM channel */ + for (i = 0; i < numOfChnls; i++) + { + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * chnlParams->dutyCyclePercent) / 100U; + + /* Setup the different match registers to generate the PWM signal */ + if (i == 0U) + { + /* Update register about period */ + PWM_SetPeriodRegister(base, subModule, mode, pulseCnt); + } + + /* Update register about dutycycle */ + PWM_SetDutycycleRegister(base, subModule, chnlParams->pwmChannel, mode, pulseCnt, pwmHighPulse); + + /* Setup register shift values based on the channel being configured. + * Also setup the deadtime value + */ + if (chnlParams->pwmChannel == kPWM_PwmA) + { + polarityShift = PWM_OCTRL_POLA_SHIFT; + outputEnableShift = PWM_OUTEN_PWMA_EN_SHIFT; + base->SM[subModule].DTCNT0 = PWM_DTCNT0_DTCNT0(chnlParams->deadtimeValue); + } + else + { + polarityShift = PWM_OCTRL_POLB_SHIFT; + outputEnableShift = PWM_OUTEN_PWMB_EN_SHIFT; + base->SM[subModule].DTCNT1 = PWM_DTCNT1_DTCNT1(chnlParams->deadtimeValue); + } + + /* Set PWM output fault status */ + switch (chnlParams->pwmChannel) + { + case kPWM_PwmA: + base->SM[subModule].OCTRL &= ~((uint16_t)PWM_OCTRL_PWMAFS_MASK); + base->SM[subModule].OCTRL |= (((uint16_t)(chnlParams->faultState) << (uint16_t)PWM_OCTRL_PWMAFS_SHIFT) & + (uint16_t)PWM_OCTRL_PWMAFS_MASK); + break; + case kPWM_PwmB: + base->SM[subModule].OCTRL &= ~((uint16_t)PWM_OCTRL_PWMBFS_MASK); + base->SM[subModule].OCTRL |= (((uint16_t)(chnlParams->faultState) << (uint16_t)PWM_OCTRL_PWMBFS_SHIFT) & + (uint16_t)PWM_OCTRL_PWMBFS_MASK); + break; + default: + assert(false); + break; + } + + /* Setup signal active level */ + if ((bool)chnlParams->level == kPWM_HighTrue) + { + base->SM[subModule].OCTRL &= ~((uint16_t)1U << (uint16_t)polarityShift); + } + else + { + base->SM[subModule].OCTRL |= ((uint16_t)1U << (uint16_t)polarityShift); + } + if (chnlParams->pwmchannelenable) + { + /* Enable PWM output */ + base->OUTEN |= ((uint16_t)1U << ((uint16_t)outputEnableShift + (uint16_t)subModule)); + } + + /* Get the pwm duty cycle */ + s_pwmGetPwmDutyCycle[subModule][chnlParams->pwmChannel] = chnlParams->dutyCyclePercent; + + /* Get the next channel parameters */ + chnlParams++; + } + + return kStatus_Success; +} + +/*! + * brief Set PWM phase shift for PWM channel running on channel PWM_A, PWM_B which with 50% duty cycle. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmChannel PWM channel to configure + * param pwmFreq_Hz PWM signal frequency in Hz + * param srcClock_Hz PWM main counter clock in Hz. + * param shiftvalue Phase shift value, range in 0 ~ 50 + * param doSync true: Set LDOK bit for the submodule list; + * false: LDOK bit don't set, need to call PWM_SetPwmLdok to sync update. + * + * return Returns kStatus_Fail if there was error setting up the signal; kStatus_Success otherwise + */ +status_t PWM_SetupPwmPhaseShift(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + uint8_t shiftvalue, + bool doSync) +{ + assert(pwmFreq_Hz != 0U); + assert(srcClock_Hz != 0U); + assert(shiftvalue <= 50U); + + uint32_t pwmClock; + uint16_t pulseCnt = 0, pwmHighPulse = 0; + uint16_t modulo = 0; + uint16_t shift = 0; + + if (pwmChannel != kPWM_PwmX) + { + /* Divide the clock by the prescale value */ + pwmClock = (srcClock_Hz / (1UL << ((base->SM[subModule].CTRL & PWM_CTRL_PRSC_MASK) >> PWM_CTRL_PRSC_SHIFT))); + pulseCnt = (uint16_t)(pwmClock / pwmFreq_Hz); + + /* Clear LDOK bit if it is set */ + if (0U != (base->MCTRL & PWM_MCTRL_LDOK(1UL << (uint8_t)subModule))) + { + base->MCTRL |= PWM_MCTRL_CLDOK(1UL << (uint8_t)subModule); + } + + modulo = (pulseCnt >> 1U); + /* Indicates the start of the PWM period */ + base->SM[subModule].INIT = PWM_GetComplementU16(modulo); + /* Indicates the center value */ + base->SM[subModule].VAL0 = 0; + /* Indicates the end of the PWM period */ + /* The change during the end to start of the PWM period requires a count time */ + base->SM[subModule].VAL1 = modulo - 1U; + + /* Immediately upon when MCTRL[LDOK] being set */ + base->SM[subModule].CTRL |= PWM_CTRL_LDMOD_MASK; + + /* phase shift value */ + shift = (pulseCnt * shiftvalue) / 100U; + + /* duty cycle 50% */ + pwmHighPulse = pulseCnt / 2U; + + if (pwmChannel == kPWM_PwmA) + { + base->SM[subModule].VAL2 = PWM_GetComplementU16(modulo) + shift; + base->SM[subModule].VAL3 = PWM_GetComplementU16(modulo) + pwmHighPulse + shift - 1U; + } + else if (pwmChannel == kPWM_PwmB) + { + base->SM[subModule].VAL4 = PWM_GetComplementU16(modulo) + shift; + base->SM[subModule].VAL5 = PWM_GetComplementU16(modulo) + pwmHighPulse + shift - 1U; + } + else + { + return kStatus_Fail; + } + + if (doSync) + { + /* Set LDOK bit to load VALx bit */ + base->MCTRL |= PWM_MCTRL_LDOK(1UL << (uint8_t)subModule); + } + } + else + { + return kStatus_Fail; + } + + return kStatus_Success; +} + +/*! + * brief Updates the PWM signal's dutycycle. + * + * The function updates the PWM dutycyle to the new value that is passed in. + * If the dead time insertion logic is enabled then the pulse period is reduced by the + * dead time period specified by the user. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmSignal Signal (PWM A or PWM B) to update + * param currPwmMode The current PWM mode set during PWM setup + * param dutyCyclePercent New PWM pulse width, value should be between 0 to 100 + * 0=inactive signal(0% duty cycle)... + * 100=active signal (100% duty cycle) + */ +void PWM_UpdatePwmDutycycle(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmSignal, + pwm_mode_t currPwmMode, + uint8_t dutyCyclePercent) +{ + assert(dutyCyclePercent <= 100U); + assert(pwmSignal != kPWM_PwmX); + uint16_t reloadValue = dutyCycleToReloadValue(dutyCyclePercent); + + PWM_UpdatePwmDutycycleHighAccuracy(base, subModule, pwmSignal, currPwmMode, reloadValue); +} + +/*! + * brief Updates the PWM signal's dutycycle with 16-bit accuracy. + * + * The function updates the PWM dutycyle to the new value that is passed in. + * If the dead time insertion logic is enabled then the pulse period is reduced by the + * dead time period specified by the user. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmSignal Signal (PWM A or PWM B) to update + * param currPwmMode The current PWM mode set during PWM setup + * param dutyCycle New PWM pulse width, value should be between 0 to 65535 + * 0=inactive signal(0% duty cycle)... + * 65535=active signal (100% duty cycle) + */ +void PWM_UpdatePwmDutycycleHighAccuracy( + PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint16_t dutyCycle) +{ + assert(pwmSignal != kPWM_PwmX); + uint16_t pulseCnt = 0, pwmHighPulse = 0; + uint16_t modulo = 0; + + switch (currPwmMode) + { + case kPWM_SignedCenterAligned: + modulo = base->SM[subModule].VAL1 + 1U; + pulseCnt = modulo * 2U; + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; + break; + case kPWM_CenterAligned: + pulseCnt = base->SM[subModule].VAL1 + 1U; + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; + break; + case kPWM_SignedEdgeAligned: + modulo = base->SM[subModule].VAL1 + 1U; + pulseCnt = modulo * 2U; + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; + break; + case kPWM_EdgeAligned: + pulseCnt = base->SM[subModule].VAL1 + 1U; + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; + break; + default: + assert(false); + break; + } + + /* Update register about dutycycle */ + if (kPWM_PwmA == pwmSignal) + { + PWM_SetDutycycleRegister(base, subModule, kPWM_PwmA, currPwmMode, pulseCnt, pwmHighPulse); + } + else if (kPWM_PwmB == pwmSignal) + { + PWM_SetDutycycleRegister(base, subModule, kPWM_PwmB, currPwmMode, pulseCnt, pwmHighPulse); + } + else + { + ; /* Intentional empty */ + } + + if (kPWM_PwmX != pwmSignal) + { + /* Get the pwm duty cycle */ + s_pwmGetPwmDutyCycle[subModule][pwmSignal] = (uint8_t)(dutyCycle * 100U / 65535U); + } +} + +/*! + * brief Update the PWM signal's period and dutycycle for a PWM submodule. + * + * The function updates PWM signal period generated by a specific submodule according to the parameters + * passed in by the user. This function can also set dutycycle weather you want to keep original dutycycle + * or update new dutycycle. Call this function in local sync control mode because PWM period is depended by + * INIT and VAL1 register of each submodule. In master sync initialization control mode, call this function + * to update INIT and VAL1 register of all submodule because PWM period is depended by INIT and VAL1 register + * in submodule0. If the dead time insertion logic is enabled, the pulse period is reduced by the dead time + * period specified by the user. PWM signal will not be generated if its period is less than dead time duration. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmSignal Signal (PWM A or PWM B) to update + * param currPwmMode The current PWM mode set during PWM setup, options available in enumeration ::pwm_mode_t + * param pulseCnt New PWM period, value should be between 0 to 65535 + * 0=minimum PWM period... + * 65535=maximum PWM period + * param dutyCycle New PWM pulse width of channel, value should be between 0 to 65535 + * 0=inactive signal(0% duty cycle)... + * 65535=active signal (100% duty cycle) + * You can keep original dutycycle or update new dutycycle + */ +void PWM_UpdatePwmPeriodAndDutycycle(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmSignal, + pwm_mode_t currPwmMode, + uint16_t pulseCnt, + uint16_t dutyCycle) +{ + uint16_t pwmHighPulse = 0; + + assert(pwmSignal != kPWM_PwmX); + + /* Calculate pulse width */ + pwmHighPulse = (pulseCnt * dutyCycle) / 65535U; + + /* Update register about period */ + PWM_SetPeriodRegister(base, subModule, currPwmMode, pulseCnt); + + /* Update register about dutycycle */ + PWM_SetDutycycleRegister(base, subModule, pwmSignal, currPwmMode, pulseCnt, pwmHighPulse); + + /* Get the pwm duty cycle */ + s_pwmGetPwmDutyCycle[subModule][pwmSignal] = (uint8_t)((dutyCycle * 100U) / 65535U); +} + +/*! + * brief Sets up the PWM input capture + * + * Each PWM submodule has 3 pins that can be configured for use as input capture pins. This function + * sets up the capture parameters for each pin and enables the pin for input capture operation. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmChannel Channel in the submodule to setup + * param inputCaptureParams Parameters passed in to set up the input pin + */ +void PWM_SetupInputCapture(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + const pwm_input_capture_param_t *inputCaptureParams) +{ + uint16_t reg = 0; + switch (pwmChannel) + { +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA + case kPWM_PwmA: + /* Setup the capture paramters for PWM A pin */ + reg = (PWM_CAPTCTRLA_INP_SELA(inputCaptureParams->captureInputSel) | + PWM_CAPTCTRLA_EDGA0(inputCaptureParams->edge0) | PWM_CAPTCTRLA_EDGA1(inputCaptureParams->edge1) | + PWM_CAPTCTRLA_ONESHOTA(inputCaptureParams->enableOneShotCapture) | + PWM_CAPTCTRLA_CFAWM(inputCaptureParams->fifoWatermark)); + /* Enable the edge counter if using the output edge counter */ + if (inputCaptureParams->captureInputSel) + { + reg |= PWM_CAPTCTRLA_EDGCNTA_EN_MASK; + } + /* Enable input capture operation */ + reg |= PWM_CAPTCTRLA_ARMA_MASK; + + base->SM[subModule].CAPTCTRLA = reg; + + /* Setup the compare value when using the edge counter as source */ + base->SM[subModule].CAPTCOMPA = PWM_CAPTCOMPA_EDGCMPA(inputCaptureParams->edgeCompareValue); + /* Setup PWM A pin for input capture */ + base->OUTEN &= ~((uint16_t)1U << (PWM_OUTEN_PWMA_EN_SHIFT + (uint16_t)subModule)); + break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB + case kPWM_PwmB: + /* Setup the capture paramters for PWM B pin */ + reg = (PWM_CAPTCTRLB_INP_SELB(inputCaptureParams->captureInputSel) | + PWM_CAPTCTRLB_EDGB0(inputCaptureParams->edge0) | PWM_CAPTCTRLB_EDGB1(inputCaptureParams->edge1) | + PWM_CAPTCTRLB_ONESHOTB(inputCaptureParams->enableOneShotCapture) | + PWM_CAPTCTRLB_CFBWM(inputCaptureParams->fifoWatermark)); + /* Enable the edge counter if using the output edge counter */ + if (inputCaptureParams->captureInputSel) + { + reg |= PWM_CAPTCTRLB_EDGCNTB_EN_MASK; + } + /* Enable input capture operation */ + reg |= PWM_CAPTCTRLB_ARMB_MASK; + + base->SM[subModule].CAPTCTRLB = reg; + + /* Setup the compare value when using the edge counter as source */ + base->SM[subModule].CAPTCOMPB = PWM_CAPTCOMPB_EDGCMPB(inputCaptureParams->edgeCompareValue); + /* Setup PWM B pin for input capture */ + base->OUTEN &= ~((uint16_t)1U << (PWM_OUTEN_PWMB_EN_SHIFT + (uint16_t)subModule)); + break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX + case kPWM_PwmX: + reg = (PWM_CAPTCTRLX_INP_SELX(inputCaptureParams->captureInputSel) | + PWM_CAPTCTRLX_EDGX0(inputCaptureParams->edge0) | PWM_CAPTCTRLX_EDGX1(inputCaptureParams->edge1) | + PWM_CAPTCTRLX_ONESHOTX(inputCaptureParams->enableOneShotCapture) | + PWM_CAPTCTRLX_CFXWM(inputCaptureParams->fifoWatermark)); + /* Enable the edge counter if using the output edge counter */ + if (inputCaptureParams->captureInputSel) + { + reg |= PWM_CAPTCTRLX_EDGCNTX_EN_MASK; + } + /* Enable input capture operation */ + reg |= PWM_CAPTCTRLX_ARMX_MASK; + + base->SM[subModule].CAPTCTRLX = reg; + + /* Setup the compare value when using the edge counter as source */ + base->SM[subModule].CAPTCOMPX = PWM_CAPTCOMPX_EDGCMPX(inputCaptureParams->edgeCompareValue); + /* Setup PWM X pin for input capture */ + base->OUTEN &= ~((uint16_t)1U << (PWM_OUTEN_PWMX_EN_SHIFT + (uint16_t)subModule)); + break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */ + default: + assert(false); + break; + } +} + +/*! + * @brief Sets up the PWM fault input filter. + * + * @param base PWM peripheral base address + * @param faultInputFilterParams Parameters passed in to set up the fault input filter. + */ +void PWM_SetupFaultInputFilter(PWM_Type *base, const pwm_fault_input_filter_param_t *faultInputFilterParams) +{ + assert(NULL != faultInputFilterParams); + + /* When changing values for fault period from a non-zero value, first write a value of 0 to clear the filter. */ + if (0U != (base->FFILT & PWM_FFILT_FILT_PER_MASK)) + { + base->FFILT &= ~(uint16_t)(PWM_FFILT_FILT_PER_MASK); + } + + base->FFILT = (uint16_t)(PWM_FFILT_FILT_PER(faultInputFilterParams->faultFilterPeriod) | + PWM_FFILT_FILT_CNT(faultInputFilterParams->faultFilterCount) | + PWM_FFILT_GSTR(faultInputFilterParams->faultGlitchStretch ? 1U : 0U)); +} + +/*! + * brief Sets up the PWM fault protection. + * + * PWM has 4 fault inputs. + * + * param base PWM peripheral base address + * param faultNum PWM fault to configure. + * param faultParams Pointer to the PWM fault config structure + */ +void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams) +{ + assert(faultParams); + uint16_t reg; + + reg = base->FCTRL; + /* Set the faults level-settting */ + if (faultParams->faultLevel) + { + reg |= ((uint16_t)1U << (PWM_FCTRL_FLVL_SHIFT + (uint16_t)faultNum)); + } + else + { + reg &= ~((uint16_t)1U << (PWM_FCTRL_FLVL_SHIFT + (uint16_t)faultNum)); + } + /* Set the fault clearing mode */ + if ((uint16_t)faultParams->faultClearingMode != 0U) + { + /* Use manual fault clearing */ + reg &= ~((uint16_t)1U << (PWM_FCTRL_FAUTO_SHIFT + (uint16_t)faultNum)); + if (faultParams->faultClearingMode == kPWM_ManualSafety) + { + /* Use manual fault clearing with safety mode enabled */ + reg |= ((uint16_t)1U << (PWM_FCTRL_FSAFE_SHIFT + (uint16_t)faultNum)); + } + else + { + /* Use manual fault clearing with safety mode disabled */ + reg &= ~((uint16_t)1U << (PWM_FCTRL_FSAFE_SHIFT + (uint16_t)faultNum)); + } + } + else + { + /* Use automatic fault clearing */ + reg |= ((uint16_t)1U << (PWM_FCTRL_FAUTO_SHIFT + (uint16_t)faultNum)); + } + base->FCTRL = reg; + + /* Set the combinational path option */ + if (faultParams->enableCombinationalPath) + { + /* Combinational path from the fault input to the PWM output is available */ + base->FCTRL2 &= ~((uint16_t)1U << (uint16_t)faultNum); + } + else + { + /* No combinational path available, only fault filter & latch signal can disable PWM output */ + base->FCTRL2 |= ((uint16_t)1U << (uint16_t)faultNum); + } + + /* Initially clear both recovery modes */ + reg = base->FSTS; + reg &= ~(((uint16_t)1U << (PWM_FSTS_FFULL_SHIFT + (uint16_t)faultNum)) | + ((uint16_t)1U << (PWM_FSTS_FHALF_SHIFT + (uint16_t)faultNum))); + /* Setup fault recovery */ + switch (faultParams->recoverMode) + { + case kPWM_NoRecovery: + break; + case kPWM_RecoverHalfCycle: + reg |= ((uint16_t)1U << (PWM_FSTS_FHALF_SHIFT + (uint16_t)faultNum)); + break; + case kPWM_RecoverFullCycle: + reg |= ((uint16_t)1U << (PWM_FSTS_FFULL_SHIFT + (uint16_t)faultNum)); + break; + case kPWM_RecoverHalfAndFullCycle: + reg |= ((uint16_t)1U << (PWM_FSTS_FHALF_SHIFT + (uint16_t)faultNum)); + reg |= ((uint16_t)1U << (PWM_FSTS_FFULL_SHIFT + (uint16_t)faultNum)); + break; + default: + assert(false); + break; + } + base->FSTS = reg; +} + +/*! + * brief Fill in the PWM fault config struct with the default settings + * + * The default values are: + * code + * config->faultClearingMode = kPWM_Automatic; + * config->faultLevel = false; + * config->enableCombinationalPath = true; + * config->recoverMode = kPWM_NoRecovery; + * endcode + * param config Pointer to user's PWM fault config structure. + */ +void PWM_FaultDefaultConfig(pwm_fault_param_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* PWM uses automatic fault clear mode */ + config->faultClearingMode = kPWM_Automatic; + /* PWM fault level is set to logic 0 */ + config->faultLevel = false; + /* Combinational Path from fault input is enabled */ + config->enableCombinationalPath = true; + /* PWM output will stay inactive when recovering from a fault */ + config->recoverMode = kPWM_NoRecovery; +} + +/*! + * brief Selects the signal to output on a PWM pin when a FORCE_OUT signal is asserted. + * + * The user specifies which channel to configure by supplying the submodule number and whether + * to modify PWM A or PWM B within that submodule. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmChannel Channel to configure + * param mode Signal to output when a FORCE_OUT is triggered + */ +void PWM_SetupForceSignal(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, pwm_force_signal_t mode) + +{ + uint16_t shift; + uint16_t reg; + + /* DTSRCSEL register has 4 bits per submodule; 2 bits for PWM A and 2 bits for PWM B */ + shift = ((uint16_t)subModule * 4U) + ((uint16_t)pwmChannel * 2U); + + /* Setup the signal to be passed upon occurrence of a FORCE_OUT signal */ + reg = base->DTSRCSEL; + reg &= ~((uint16_t)0x3U << shift); + reg |= (uint16_t)((uint16_t)mode << shift); + base->DTSRCSEL = reg; +} + +/*! + * brief Enables the selected PWM interrupts + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask) +{ + /* Upper 16 bits are for related to the submodule */ + base->SM[subModule].INTEN |= ((uint16_t)mask & 0xFFFFU); + /* Fault related interrupts */ + base->FCTRL |= ((uint16_t)(mask >> 16U) & PWM_FCTRL_FIE_MASK); +} + +/*! + * brief Disables the selected PWM interrupts + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +void PWM_DisableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask) +{ + base->SM[subModule].INTEN &= ~((uint16_t)mask & 0xFFFFU); + base->FCTRL &= ~((uint16_t)(mask >> 16U) & PWM_FCTRL_FIE_MASK); +} + +/*! + * brief Gets the enabled PWM interrupts + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * + * return The enabled interrupts. This is the logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule) +{ + uint32_t enabledInterrupts; + + enabledInterrupts = base->SM[subModule].INTEN; + enabledInterrupts |= (((uint32_t)base->FCTRL & PWM_FCTRL_FIE_MASK) << 16UL); + return enabledInterrupts; +} + +/*! + * brief Gets the PWM status flags + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * + * return The status flags. This is the logical OR of members of the + * enumeration ::pwm_status_flags_t + */ +uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule) +{ + uint32_t statusFlags; + + statusFlags = base->SM[subModule].STS; + statusFlags |= (((uint32_t)base->FSTS & PWM_FSTS_FFLAG_MASK) << 16UL); + + return statusFlags; +} + +/*! + * brief Clears the PWM status flags + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::pwm_status_flags_t + */ +void PWM_ClearStatusFlags(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask) +{ + uint16_t reg; + + base->SM[subModule].STS = ((uint16_t)mask & 0xFFFFU); + reg = base->FSTS; + /* Clear the fault flags and set only the ones we wish to clear as the fault flags are cleared + * by writing a login one + */ + reg &= ~(uint16_t)(PWM_FSTS_FFLAG_MASK); + reg |= (uint16_t)((mask >> 16U) & PWM_FSTS_FFLAG_MASK); + base->FSTS = reg; +} + +/*! + * brief Set PWM output in idle status (high or low). + * + * note This API should call after PWM_SetupPwm() APIs, and PWMX submodule is not supported. + * + * param base PWM peripheral base address + * param pwmChannel PWM channel to configure + * param subModule PWM submodule to configure + * param idleStatus True: PWM output is high in idle status; false: PWM output is low in idle status. + * + * return kStatus_Fail if there was error setting up the signal; kStatus_Success if set output idle success + */ +status_t PWM_SetOutputToIdle(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, bool idleStatus) +{ + uint16_t valOn = 0, valOff = 0; + uint16_t ldmod; + + /* Clear LDOK bit if it is set */ + if (0U != (base->MCTRL & PWM_MCTRL_LDOK(1UL << (uint8_t)subModule))) + { + base->MCTRL |= PWM_MCTRL_CLDOK(1UL << (uint8_t)subModule); + } + + valOff = base->SM[subModule].INIT; + valOn = base->SM[subModule].VAL1 + 0x1U; + + if ((valOff + 1U) == valOn) + { + return kStatus_Fail; + } + + /* Should not PWM_X channel */ + if (kPWM_PwmA == pwmChannel) + { + if (0U != (base->SM[subModule].OCTRL & PWM_OCTRL_POLA_MASK)) + { + if (!idleStatus) + { + valOn = base->SM[subModule].INIT; + valOff = base->SM[subModule].VAL1 + 0x1U; + } + } + else + { + if (idleStatus) + { + valOn = base->SM[subModule].INIT; + valOff = base->SM[subModule].VAL1 + 0x1U; + } + } + base->SM[subModule].VAL2 = valOn; + base->SM[subModule].VAL3 = valOff; + } + else if (kPWM_PwmB == pwmChannel) + { + if (0U != (base->SM[subModule].OCTRL & PWM_OCTRL_POLB_MASK)) + { + if (!idleStatus) + { + valOn = base->SM[subModule].INIT; + valOff = base->SM[subModule].VAL1 + 0x1U; + } + } + else + { + if (idleStatus) + { + valOn = base->SM[subModule].INIT; + valOff = base->SM[subModule].VAL1 + 0x1U; + } + } + base->SM[subModule].VAL4 = valOn; + base->SM[subModule].VAL5 = valOff; + } + else + { + return kStatus_Fail; + } + + /* Record Load mode */ + ldmod = base->SM[subModule].CTRL; + /* Set Load mode to make Buffered registers take effect immediately when LDOK bit set */ + base->SM[subModule].CTRL |= PWM_CTRL_LDMOD_MASK; + /* Set LDOK bit to load buffer registers */ + base->MCTRL |= PWM_MCTRL_LDOK(1UL << (uint8_t)subModule); + /* Restore Load mode */ + base->SM[subModule].CTRL = ldmod; + + /* Get pwm duty cycle */ + s_pwmGetPwmDutyCycle[subModule][pwmChannel] = 0x0U; + + return kStatus_Success; +} + +/*! + * brief Get the dutycycle value. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmChannel PWM channel to configure + * + * return Current channel dutycycle value. + */ +uint8_t PWM_GetPwmChannelState(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel) +{ + return s_pwmGetPwmDutyCycle[subModule][pwmChannel]; +} + +/*! + * brief Set the pwm submodule prescaler. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param prescaler Set prescaler value + */ +void PWM_SetClockMode(PWM_Type *base, pwm_submodule_t subModule, pwm_clock_prescale_t prescaler) +{ + uint16_t reg = base->SM[subModule].CTRL; + + /* Clear LDOK bit if it is set */ + if (0U != (base->MCTRL & PWM_MCTRL_LDOK(1UL << (uint8_t)subModule))) + { + base->MCTRL |= PWM_MCTRL_CLDOK(1UL << (uint8_t)subModule); + } + /* Set submodule prescaler. */ + reg &= ~(uint16_t)PWM_CTRL_PRSC_MASK; + reg |= PWM_CTRL_PRSC(prescaler); + base->SM[subModule].CTRL = reg; + /* Set Load mode to make Buffered registers take effect immediately when LDOK bit set */ + base->SM[subModule].CTRL |= PWM_CTRL_LDMOD_MASK; + /* Set LDOK bit to load buffer registers */ + base->MCTRL |= PWM_MCTRL_LDOK(1UL << (uint8_t)subModule); + /* Restore Load mode */ + base->SM[subModule].CTRL = reg; +} + +/*! + * brief This function enables-disables the forcing of the output of a given eFlexPwm channel to logic 0. + * + * param base PWM peripheral base address + * param pwmChannel PWM channel to configure + * param subModule PWM submodule to configure + * param forcetozero True: Enable the pwm force output to zero; False: Disable the pwm output resumes normal + * function. + */ +void PWM_SetPwmForceOutputToZero(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, bool forcetozero) +{ +#if !defined(PWM_MASK_UPDATE_MASK) + uint16_t reg = base->SM[subModule].CTRL2; +#endif + uint16_t mask; + + if (kPWM_PwmA == pwmChannel) + { + mask = PWM_MASK_MASKA(0x01UL << (uint8_t)subModule); + } + else if (kPWM_PwmB == pwmChannel) + { + mask = PWM_MASK_MASKB(0x01UL << (uint8_t)subModule); + } + else + { + mask = PWM_MASK_MASKX(0x01UL << (uint8_t)subModule); + } + + if (forcetozero) + { + /* Disables the channel output, forcing output level to 0 */ + base->MASK |= mask; + } + else + { + /* Enables the channel output */ + base->MASK &= ~mask; + } + +#if defined(PWM_MASK_UPDATE_MASK) + /* Update output mask bits immediately with UPDATE_MASK bit */ + base->MASK |= PWM_MASK_UPDATE_MASK(0x01UL << (uint8_t)subModule); +#else + /* Select local force signal */ + base->SM[subModule].CTRL2 &= ~(uint16_t)PWM_CTRL2_FORCE_SEL_MASK; + /* Issue a local Force trigger event */ + base->SM[subModule].CTRL2 |= PWM_CTRL2_FORCE_MASK; + /* Restore the source of FORCE OUTPUT signal */ + base->SM[subModule].CTRL2 = reg; +#endif +} + +/*! + * brief This function set the output state of the PWM pin as requested for the current cycle. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmChannel PWM channel to configure + * param outputstate Set pwm output state, see @ref pwm_output_state_t. + */ +void PWM_SetChannelOutput(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + pwm_output_state_t outputstate) +{ + uint16_t mask, swcout, sourceShift; + uint16_t reg = base->SM[subModule].CTRL2; + + if (kPWM_PwmA == pwmChannel) + { + mask = PWM_MASK_MASKA(0x01UL << (uint8_t)subModule); + swcout = (uint16_t)PWM_SWCOUT_SM0OUT23_MASK << ((uint8_t)subModule * 2U); + sourceShift = PWM_DTSRCSEL_SM0SEL23_SHIFT + ((uint16_t)subModule * 4U); + } + else if (kPWM_PwmB == pwmChannel) + { + mask = PWM_MASK_MASKB(0x01UL << (uint8_t)subModule); + swcout = (uint16_t)PWM_SWCOUT_SM0OUT45_MASK << ((uint8_t)subModule * 2U); + sourceShift = PWM_DTSRCSEL_SM0SEL45_SHIFT + ((uint16_t)subModule * 4U); + } + else + { + mask = PWM_MASK_MASKX(0x01UL << (uint8_t)subModule); + swcout = 0U; + sourceShift = 0U; + } + + if (kPWM_MaskState == outputstate) + { + /* Disables the channel output, forcing output level to 0 */ + base->MASK |= mask; + } + else + { + /* Enables the channel output first */ + base->MASK &= ~mask; + /* PwmX only support MASK mode */ + if (kPWM_PwmX != pwmChannel) + { + if (kPWM_HighState == outputstate) + { + base->SWCOUT |= swcout; + base->DTSRCSEL = + (base->DTSRCSEL & ~(uint16_t)(0x3UL << sourceShift)) | (uint16_t)(0x2UL << sourceShift); + } + else if (kPWM_LowState == outputstate) + { + base->SWCOUT &= ~swcout; + base->DTSRCSEL = + (base->DTSRCSEL & ~(uint16_t)(0x3UL << sourceShift)) | (uint16_t)(0x2UL << sourceShift); + } + else if (kPWM_NormalState == outputstate) + { + base->DTSRCSEL &= ~(uint16_t)(0x3UL << sourceShift); + } + else + { + base->DTSRCSEL = + (base->DTSRCSEL & ~(uint16_t)(0x3UL << sourceShift)) | (uint16_t)(0x1UL << sourceShift); + } + } + } + + /* Select local force signal */ + base->SM[subModule].CTRL2 &= ~(uint16_t)PWM_CTRL2_FORCE_SEL_MASK; + /* Issue a local Force trigger event */ + base->SM[subModule].CTRL2 |= PWM_CTRL2_FORCE_MASK; + /* Restore the source of FORCE OUTPUT signal */ + base->SM[subModule].CTRL2 = reg; +} + +#if defined(FSL_FEATURE_PWM_HAS_PHASE_DELAY) && FSL_FEATURE_PWM_HAS_PHASE_DELAY +/*! + * brief This function set the phase delay from the master sync signal of submodule 0. + * + * param base PWM peripheral base address + * param subModule PWM submodule to configure + * param pwmChannel PWM channel to configure + * param delayCycles Number of cycles delayed from submodule 0. + * + * return kStatus_Fail if the number of delay cycles is set larger than the period defined in submodule 0; + * kStatus_Success if set phase delay success + */ +status_t PWM_SetPhaseDelay(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, uint16_t delayCycles) +{ + assert(subModule != kPWM_Module_0); + uint16_t reg = base->SM[subModule].CTRL2; + + /* Clear LDOK bit if it is set */ + if (0U != (base->MCTRL & PWM_MCTRL_LDOK(1UL << (uint8_t)subModule))) + { + base->MCTRL |= PWM_MCTRL_CLDOK(1UL << (uint8_t)subModule); + } + + if (base->SM[kPWM_Module_0].VAL1 < delayCycles) + { + return kStatus_Fail; + } + else + { + /* + * ERR051989: When the value of the phase delay register SMxPHASEDLY is reduced from a + * non-zero value to 0 and submodule x reload source is from submodule0, the submodule + * x may output an unexpected wide PWM pulse. The workaround is set SMxPHASEDLY=1, + * SMxINIT=SM0INIT-1, SMxVALy=SM0VALy-1 (x=1,2,3, y=0,1,2,3,4,5). + */ +#if defined(FSL_FEATURE_PWM_HAS_ERRATA_51989) && FSL_FEATURE_PWM_HAS_ERRATA_51989 + if (delayCycles == 0 && + ((base->SM[subModule].CTRL2 & PWM_CTRL2_RELOAD_SEL_MASK) >> PWM_CTRL2_RELOAD_SEL_SHIFT) == 1U) + { + base->SM[subModule].PHASEDLY = 1U; + base->SM[subModule].INIT = base->SM[0].INIT - 1U; + base->SM[subModule].VAL0 = base->SM[0].VAL0 - 1U; + base->SM[subModule].VAL1 = base->SM[0].VAL1 - 1U; + base->SM[subModule].VAL2 = base->SM[0].VAL2 - 1U; + base->SM[subModule].VAL3 = base->SM[0].VAL3 - 1U; + base->SM[subModule].VAL4 = base->SM[0].VAL4 - 1U; + base->SM[subModule].VAL5 = base->SM[0].VAL5 - 1U; + } + else + { + base->SM[subModule].PHASEDLY = delayCycles; + } +#else + base->SM[subModule].PHASEDLY = delayCycles; +#endif + } + + /* Select the master sync signal as the source for initialization */ + reg = (reg & ~(uint16_t)PWM_CTRL2_INIT_SEL_MASK) | PWM_CTRL2_INIT_SEL(2); + /* Set Load mode to make Buffered registers take effect immediately when LDOK bit set */ + base->SM[subModule].CTRL |= PWM_CTRL_LDMOD_MASK; + /* Set LDOK bit to load buffer registers */ + base->MCTRL |= PWM_MCTRL_LDOK(1UL << (uint8_t)subModule); + /* Restore the source of phase delay register intialization */ + base->SM[subModule].CTRL2 = reg; + return kStatus_Success; +} +#endif /* FSL_FEATURE_PWM_HAS_PHASE_DELAY */ \ No newline at end of file diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_pwm.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_pwm.h new file mode 100644 index 00000000000..9e0b12ba654 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_pwm.h @@ -0,0 +1,1372 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_PWM_H_ +#define FSL_PWM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pwm_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @name Driver version */ +/*! @{ */ +#define FSL_PWM_DRIVER_VERSION (MAKE_VERSION(2, 8, 4)) /*!< Version 2.8.4 */ +/*! @} */ + +/*! Number of bits per submodule for software output control */ +#define PWM_SUBMODULE_SWCONTROL_WIDTH 2 +/*! Because setting the pwm duty cycle doesn't support PWMX, getting the pwm duty cycle also doesn't support PWMX. */ +#define PWM_SUBMODULE_CHANNEL 2 + +/*! @brief List of PWM submodules */ +typedef enum _pwm_submodule +{ + kPWM_Module_0 = 0U, /*!< Submodule 0 */ + kPWM_Module_1, /*!< Submodule 1 */ + kPWM_Module_2, /*!< Submodule 2 */ +#if defined(FSL_FEATURE_PWM_SUBMODULE_COUNT) && (FSL_FEATURE_PWM_SUBMODULE_COUNT > 3U) + kPWM_Module_3 /*!< Submodule 3 */ +#endif /* FSL_FEATURE_PWM_SUBMODULE_COUNT */ +} pwm_submodule_t; + +/*! @brief List of PWM channels in each module */ +typedef enum _pwm_channels +{ + kPWM_PwmB = 0U, + kPWM_PwmA, + kPWM_PwmX +} pwm_channels_t; + +/*! @brief List of PWM value registers */ +typedef enum _pwm_value_register +{ + kPWM_ValueRegister_0 = 0U, /*!< PWM Value0 register */ + kPWM_ValueRegister_1, /*!< PWM Value1 register */ + kPWM_ValueRegister_2, /*!< PWM Value2 register */ + kPWM_ValueRegister_3, /*!< PWM Value3 register */ + kPWM_ValueRegister_4, /*!< PWM Value4 register */ + kPWM_ValueRegister_5 /*!< PWM Value5 register */ +} pwm_value_register_t; + +/*! @brief List of PWM value registers mask */ +enum _pwm_value_register_mask +{ + kPWM_ValueRegisterMask_0 = (1U << 0), /*!< PWM Value0 register mask */ + kPWM_ValueRegisterMask_1 = (1U << 1), /*!< PWM Value1 register mask */ + kPWM_ValueRegisterMask_2 = (1U << 2), /*!< PWM Value2 register mask */ + kPWM_ValueRegisterMask_3 = (1U << 3), /*!< PWM Value3 register mask */ + kPWM_ValueRegisterMask_4 = (1U << 4), /*!< PWM Value4 register mask */ + kPWM_ValueRegisterMask_5 = (1U << 5) /*!< PWM Value5 register mask */ +}; + +/*! @brief PWM clock source selection.*/ +typedef enum _pwm_clock_source +{ + kPWM_BusClock = 0U, /*!< The IPBus clock is used as the clock */ + kPWM_ExternalClock, /*!< EXT_CLK is used as the clock */ + kPWM_Submodule0Clock /*!< Clock of the submodule 0 (AUX_CLK) is used as the source clock */ +} pwm_clock_source_t; + +/*! @brief PWM prescaler factor selection for clock source*/ +typedef enum _pwm_clock_prescale +{ + kPWM_Prescale_Divide_1 = 0U, /*!< PWM clock frequency = fclk/1 */ + kPWM_Prescale_Divide_2, /*!< PWM clock frequency = fclk/2 */ + kPWM_Prescale_Divide_4, /*!< PWM clock frequency = fclk/4 */ + kPWM_Prescale_Divide_8, /*!< PWM clock frequency = fclk/8 */ + kPWM_Prescale_Divide_16, /*!< PWM clock frequency = fclk/16 */ + kPWM_Prescale_Divide_32, /*!< PWM clock frequency = fclk/32 */ + kPWM_Prescale_Divide_64, /*!< PWM clock frequency = fclk/64 */ + kPWM_Prescale_Divide_128 /*!< PWM clock frequency = fclk/128 */ +} pwm_clock_prescale_t; + +/*! @brief Options that can trigger a PWM FORCE_OUT */ +typedef enum _pwm_force_output_trigger +{ + kPWM_Force_Local = 0U, /*!< The local force signal, CTRL2[FORCE], from the submodule is used to force updates */ + kPWM_Force_Master, /*!< The master force signal from submodule 0 is used to force updates */ + kPWM_Force_LocalReload, /*!< The local reload signal from this submodule is used to force updates without regard to + the state of LDOK */ + kPWM_Force_MasterReload, /*!< The master reload signal from submodule 0 is used to force updates if LDOK is set */ + kPWM_Force_LocalSync, /*!< The local sync signal from this submodule is used to force updates */ + kPWM_Force_MasterSync, /*!< The master sync signal from submodule0 is used to force updates */ + kPWM_Force_External, /*!< The external force signal, EXT_FORCE, from outside the PWM module causes updates */ + kPWM_Force_ExternalSync /*!< The external sync signal, EXT_SYNC, from outside the PWM module causes updates */ +} pwm_force_output_trigger_t; + +/*! @brief PWM channel output status */ +typedef enum _pwm_output_state +{ + kPWM_HighState = 0, /*!< The output state of PWM channel is high */ + kPWM_LowState, /*!< The output state of PWM channel is low */ + kPWM_NormalState, /*!< The output state of PWM channel is normal */ + kPWM_InvertState, /*!< The output state of PWM channel is invert */ + kPWM_MaskState /*!< The output state of PWM channel is mask */ +} pwm_output_state_t; + +/*! @brief PWM counter initialization options */ +typedef enum _pwm_init_source +{ + kPWM_Initialize_LocalSync = 0U, /*!< Local sync causes initialization */ + kPWM_Initialize_MasterReload, /*!< Master reload from submodule 0 causes initialization */ + kPWM_Initialize_MasterSync, /*!< Master sync from submodule 0 causes initialization */ + kPWM_Initialize_ExtSync /*!< EXT_SYNC causes initialization */ +} pwm_init_source_t; + +/*! @brief PWM load frequency selection */ +typedef enum _pwm_load_frequency +{ + kPWM_LoadEveryOportunity = 0U, /*!< Every PWM opportunity */ + kPWM_LoadEvery2Oportunity, /*!< Every 2 PWM opportunities */ + kPWM_LoadEvery3Oportunity, /*!< Every 3 PWM opportunities */ + kPWM_LoadEvery4Oportunity, /*!< Every 4 PWM opportunities */ + kPWM_LoadEvery5Oportunity, /*!< Every 5 PWM opportunities */ + kPWM_LoadEvery6Oportunity, /*!< Every 6 PWM opportunities */ + kPWM_LoadEvery7Oportunity, /*!< Every 7 PWM opportunities */ + kPWM_LoadEvery8Oportunity, /*!< Every 8 PWM opportunities */ + kPWM_LoadEvery9Oportunity, /*!< Every 9 PWM opportunities */ + kPWM_LoadEvery10Oportunity, /*!< Every 10 PWM opportunities */ + kPWM_LoadEvery11Oportunity, /*!< Every 11 PWM opportunities */ + kPWM_LoadEvery12Oportunity, /*!< Every 12 PWM opportunities */ + kPWM_LoadEvery13Oportunity, /*!< Every 13 PWM opportunities */ + kPWM_LoadEvery14Oportunity, /*!< Every 14 PWM opportunities */ + kPWM_LoadEvery15Oportunity, /*!< Every 15 PWM opportunities */ + kPWM_LoadEvery16Oportunity /*!< Every 16 PWM opportunities */ +} pwm_load_frequency_t; + +/*! @brief List of PWM fault selections */ +typedef enum _pwm_fault_input +{ + kPWM_Fault_0 = 0U, /*!< Fault 0 input pin */ + kPWM_Fault_1, /*!< Fault 1 input pin */ + kPWM_Fault_2, /*!< Fault 2 input pin */ + kPWM_Fault_3 /*!< Fault 3 input pin */ +} pwm_fault_input_t; + +/*! @brief List of PWM fault disable mapping selections */ +typedef enum _pwm_fault_disable +{ + kPWM_FaultDisable_0 = (1U << 0), /*!< Fault 0 disable mapping */ + kPWM_FaultDisable_1 = (1U << 1), /*!< Fault 1 disable mapping */ + kPWM_FaultDisable_2 = (1U << 2), /*!< Fault 2 disable mapping */ + kPWM_FaultDisable_3 = (1U << 3) /*!< Fault 3 disable mapping */ +} pwm_fault_disable_t; + +/*! @brief List of PWM fault channels */ +typedef enum _pwm_fault_channels +{ + kPWM_faultchannel_0 = 0U, + kPWM_faultchannel_1 +} pwm_fault_channels_t; + +/*! @brief PWM capture edge select */ +typedef enum _pwm_input_capture_edge +{ + kPWM_Disable = 0U, /*!< Disabled */ + kPWM_FallingEdge, /*!< Capture on falling edge only */ + kPWM_RisingEdge, /*!< Capture on rising edge only */ + kPWM_RiseAndFallEdge /*!< Capture on rising or falling edge */ +} pwm_input_capture_edge_t; + +/*! @brief PWM output options when a FORCE_OUT signal is asserted */ +typedef enum _pwm_force_signal +{ + kPWM_UsePwm = 0U, /*!< Generated PWM signal is used by the deadtime logic.*/ + kPWM_InvertedPwm, /*!< Inverted PWM signal is used by the deadtime logic.*/ + kPWM_SoftwareControl, /*!< Software controlled value is used by the deadtime logic. */ + kPWM_UseExternal /*!< PWM_EXTA signal is used by the deadtime logic. */ +} pwm_force_signal_t; + +/*! @brief Options available for the PWM A & B pair operation */ +typedef enum _pwm_chnl_pair_operation +{ + kPWM_Independent = 0U, /*!< PWM A & PWM B operate as 2 independent channels */ + kPWM_ComplementaryPwmA, /*!< PWM A & PWM B are complementary channels, PWM A generates the signal */ + kPWM_ComplementaryPwmB /*!< PWM A & PWM B are complementary channels, PWM B generates the signal */ +} pwm_chnl_pair_operation_t; + +/*! @brief Options available on how to load the buffered-registers with new values */ +typedef enum _pwm_register_reload +{ + kPWM_ReloadImmediate = 0U, /*!< Buffered-registers get loaded with new values as soon as LDOK bit is set */ + kPWM_ReloadPwmHalfCycle, /*!< Registers loaded on a PWM half cycle */ + kPWM_ReloadPwmFullCycle, /*!< Registers loaded on a PWM full cycle */ + kPWM_ReloadPwmHalfAndFullCycle /*!< Registers loaded on a PWM half & full cycle */ +} pwm_register_reload_t; + +/*! @brief Options available on how to re-enable the PWM output when recovering from a fault */ +typedef enum _pwm_fault_recovery_mode +{ + kPWM_NoRecovery = 0U, /*!< PWM output will stay inactive */ + kPWM_RecoverHalfCycle, /*!< PWM output re-enabled at the first half cycle */ + kPWM_RecoverFullCycle, /*!< PWM output re-enabled at the first full cycle */ + kPWM_RecoverHalfAndFullCycle /*!< PWM output re-enabled at the first half or full cycle */ +} pwm_fault_recovery_mode_t; + +/*! @brief List of PWM interrupt options */ +typedef enum _pwm_interrupt_enable +{ + kPWM_CompareVal0InterruptEnable = (1U << 0), /*!< PWM VAL0 compare interrupt */ + kPWM_CompareVal1InterruptEnable = (1U << 1), /*!< PWM VAL1 compare interrupt */ + kPWM_CompareVal2InterruptEnable = (1U << 2), /*!< PWM VAL2 compare interrupt */ + kPWM_CompareVal3InterruptEnable = (1U << 3), /*!< PWM VAL3 compare interrupt */ + kPWM_CompareVal4InterruptEnable = (1U << 4), /*!< PWM VAL4 compare interrupt */ + kPWM_CompareVal5InterruptEnable = (1U << 5), /*!< PWM VAL5 compare interrupt */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX + kPWM_CaptureX0InterruptEnable = (1U << 6), /*!< PWM capture X0 interrupt */ + kPWM_CaptureX1InterruptEnable = (1U << 7), /*!< PWM capture X1 interrupt */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB + kPWM_CaptureB0InterruptEnable = (1U << 8), /*!< PWM capture B0 interrupt */ + kPWM_CaptureB1InterruptEnable = (1U << 9), /*!< PWM capture B1 interrupt */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA + kPWM_CaptureA0InterruptEnable = (1U << 10), /*!< PWM capture A0 interrupt */ + kPWM_CaptureA1InterruptEnable = (1U << 11), /*!< PWM capture A1 interrupt */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */ + kPWM_ReloadInterruptEnable = (1U << 12), /*!< PWM reload interrupt */ + kPWM_ReloadErrorInterruptEnable = (1U << 13), /*!< PWM reload error interrupt */ + kPWM_Fault0InterruptEnable = (1U << 16), /*!< PWM fault 0 interrupt */ + kPWM_Fault1InterruptEnable = (1U << 17), /*!< PWM fault 1 interrupt */ + kPWM_Fault2InterruptEnable = (1U << 18), /*!< PWM fault 2 interrupt */ + kPWM_Fault3InterruptEnable = (1U << 19) /*!< PWM fault 3 interrupt */ +} pwm_interrupt_enable_t; + +/*! @brief List of PWM status flags */ +typedef enum _pwm_status_flags +{ + kPWM_CompareVal0Flag = (1U << 0), /*!< PWM VAL0 compare flag */ + kPWM_CompareVal1Flag = (1U << 1), /*!< PWM VAL1 compare flag */ + kPWM_CompareVal2Flag = (1U << 2), /*!< PWM VAL2 compare flag */ + kPWM_CompareVal3Flag = (1U << 3), /*!< PWM VAL3 compare flag */ + kPWM_CompareVal4Flag = (1U << 4), /*!< PWM VAL4 compare flag */ + kPWM_CompareVal5Flag = (1U << 5), /*!< PWM VAL5 compare flag */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX + kPWM_CaptureX0Flag = (1U << 6), /*!< PWM capture X0 flag */ + kPWM_CaptureX1Flag = (1U << 7), /*!< PWM capture X1 flag */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB + kPWM_CaptureB0Flag = (1U << 8), /*!< PWM capture B0 flag */ + kPWM_CaptureB1Flag = (1U << 9), /*!< PWM capture B1 flag */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA + kPWM_CaptureA0Flag = (1U << 10), /*!< PWM capture A0 flag */ + kPWM_CaptureA1Flag = (1U << 11), /*!< PWM capture A1 flag */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */ + kPWM_ReloadFlag = (1U << 12), /*!< PWM reload flag */ + kPWM_ReloadErrorFlag = (1U << 13), /*!< PWM reload error flag */ + kPWM_RegUpdatedFlag = (1U << 14), /*!< PWM registers updated flag */ + kPWM_Fault0Flag = (1U << 16), /*!< PWM fault 0 flag */ + kPWM_Fault1Flag = (1U << 17), /*!< PWM fault 1 flag */ + kPWM_Fault2Flag = (1U << 18), /*!< PWM fault 2 flag */ + kPWM_Fault3Flag = (1U << 19) /*!< PWM fault 3 flag */ +} pwm_status_flags_t; + +/*! @brief List of PWM DMA options */ +typedef enum _pwm_dma_enable +{ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX + kPWM_CaptureX0DMAEnable = (1U << 0), /*!< PWM capture X0 DMA */ + kPWM_CaptureX1DMAEnable = (1U << 1), /*!< PWM capture X1 DMA */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB + kPWM_CaptureB0DMAEnable = (1U << 2), /*!< PWM capture B0 DMA */ + kPWM_CaptureB1DMAEnable = (1U << 3), /*!< PWM capture B1 DMA */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA + kPWM_CaptureA0DMAEnable = (1U << 4), /*!< PWM capture A0 DMA */ + kPWM_CaptureA1DMAEnable = (1U << 5) /*!< PWM capture A1 DMA */ +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */ +} pwm_dma_enable_t; + +/*! @brief List of PWM capture DMA enable source select */ +typedef enum _pwm_dma_source_select +{ + kPWM_DMARequestDisable = 0U, /*!< Read DMA requests disabled */ + kPWM_DMAWatermarksEnable, /*!< Exceeding a FIFO watermark sets the DMA read request */ + kPWM_DMALocalSync, /*!< A local sync (VAL1 matches counter) sets the read DMA request */ + kPWM_DMALocalReload /*!< A local reload (STS[RF] being set) sets the read DMA request */ +} pwm_dma_source_select_t; + +/*! @brief PWM FIFO Watermark AND Control */ +typedef enum _pwm_watermark_control +{ + kPWM_FIFOWatermarksOR = 0U, /*!< Selected FIFO watermarks are OR'ed together */ + kPWM_FIFOWatermarksAND /*!< Selected FIFO watermarks are AND'ed together */ +} pwm_watermark_control_t; + +/*! @brief PWM operation mode */ +typedef enum _pwm_mode +{ + kPWM_SignedCenterAligned = 0U, /*!< Signed center-aligned */ + kPWM_CenterAligned, /*!< Unsigned cente-aligned */ + kPWM_SignedEdgeAligned, /*!< Signed edge-aligned */ + kPWM_EdgeAligned /*!< Unsigned edge-aligned */ +} pwm_mode_t; + +/*! @brief PWM output pulse mode, high-true or low-true */ +typedef enum _pwm_level_select +{ + kPWM_HighTrue = 0U, /*!< High level represents "on" or "active" state */ + kPWM_LowTrue /*!< Low level represents "on" or "active" state */ +} pwm_level_select_t; + +/*! @brief PWM output fault status */ +typedef enum _pwm_fault_state +{ + kPWM_PwmFaultState0 = + 0U, /*!< Output is forced to logic 0 state prior to consideration of output polarity control. */ + kPWM_PwmFaultState1, /*!< Output is forced to logic 1 state prior to consideration of output polarity control. */ + kPWM_PwmFaultState2, /*!< Output is tristated. */ + kPWM_PwmFaultState3 /*!< Output is tristated. */ +} pwm_fault_state_t; + +/*! @brief PWM reload source select */ +typedef enum _pwm_reload_source_select +{ + kPWM_LocalReload = 0U, /*!< The local reload signal is used to reload registers */ + kPWM_MasterReload /*!< The master reload signal (from submodule 0) is used to reload */ +} pwm_reload_source_select_t; + +/*! @brief PWM fault clearing options */ +typedef enum _pwm_fault_clear +{ + kPWM_Automatic = 0U, /*!< Automatic fault clearing */ + kPWM_ManualNormal, /*!< Manual fault clearing with no fault safety mode */ + kPWM_ManualSafety /*!< Manual fault clearing with fault safety mode */ +} pwm_fault_clear_t; + +/*! @brief Options for submodule master control operation */ +typedef enum _pwm_module_control +{ + kPWM_Control_Module_0 = (1U << 0), /*!< Control submodule 0's start/stop,buffer reload operation */ + kPWM_Control_Module_1 = (1U << 1), /*!< Control submodule 1's start/stop,buffer reload operation */ + kPWM_Control_Module_2 = (1U << 2), /*!< Control submodule 2's start/stop,buffer reload operation */ + kPWM_Control_Module_3 = (1U << 3) /*!< Control submodule 3's start/stop,buffer reload operation */ +} pwm_module_control_t; + +/*! @brief Structure for the user to define the PWM signal characteristics */ +typedef struct _pwm_signal_param +{ + pwm_channels_t pwmChannel; /*!< PWM channel being configured; PWM A or PWM B */ + uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 + 0=inactive signal(0% duty cycle)... + 100=always active signal (100% duty cycle)*/ + pwm_level_select_t level; /*!< PWM output active level select */ + uint16_t deadtimeValue; /*!< The deadtime value; only used if channel pair is operating in complementary mode */ + pwm_fault_state_t faultState; /*!< PWM output fault status */ + bool pwmchannelenable; /*!< Enable PWM output */ +} pwm_signal_param_t; + +/*! + * @brief PWM config structure + * + * This structure holds the configuration settings for the PWM peripheral. To initialize this + * structure to reasonable defaults, call the PWM_GetDefaultConfig() function and pass a + * pointer to your config structure instance. + * + * The config struct can be made const so it resides in flash + */ +typedef struct _pwm_config +{ + bool enableDebugMode; /*!< true: PWM continues to run in debug mode; + false: PWM is paused in debug mode */ +#if !defined(FSL_FEATURE_PWM_HAS_NO_WAITEN) || (!FSL_FEATURE_PWM_HAS_NO_WAITEN) + bool enableWait; /*!< true: PWM continues to run in WAIT mode; + false: PWM is paused in WAIT mode */ +#endif /* FSL_FEATURE_PWM_HAS_NO_WAITEN */ + pwm_init_source_t initializationControl; /*!< Option to initialize the counter */ + pwm_clock_source_t clockSource; /*!< Clock source for the counter */ + pwm_clock_prescale_t prescale; /*!< Pre-scaler to divide down the clock */ + pwm_chnl_pair_operation_t pairOperation; /*!< Channel pair in indepedent or complementary mode */ + pwm_register_reload_t reloadLogic; /*!< PWM Reload logic setup */ + pwm_reload_source_select_t reloadSelect; /*!< Reload source select */ + pwm_load_frequency_t reloadFrequency; /*!< Specifies when to reload, used when user's choice + is not immediate reload */ + pwm_force_output_trigger_t forceTrigger; /*!< Specify which signal will trigger a FORCE_OUT */ +} pwm_config_t; + +/*! @brief Structure for the user to configure the fault input filter. */ +typedef struct _pwm_fault_input_filter_param +{ + uint8_t faultFilterCount; /*!< Fault filter count */ + uint8_t faultFilterPeriod; /*!< Fault filter period;value of 0 will bypass the filter */ + bool faultGlitchStretch; /*!< Fault Glitch Stretch Enable: A logic 1 means that input + fault signals will be stretched to at least 2 IPBus clock cycles */ +} pwm_fault_input_filter_param_t; + +/*! @brief Structure is used to hold the parameters to configure a PWM fault */ +typedef struct _pwm_fault_param +{ + pwm_fault_clear_t faultClearingMode; /*!< Fault clearing mode to use */ + bool faultLevel; /*!< true: Logic 1 indicates fault; + false: Logic 0 indicates fault */ + bool enableCombinationalPath; /*!< true: Combinational Path from fault input is enabled; + false: No combination path is available */ + pwm_fault_recovery_mode_t recoverMode; /*!< Specify when to re-enable the PWM output */ +} pwm_fault_param_t; + +/*! + * @brief Structure is used to hold parameters to configure the capture capability of a signal pin + */ +typedef struct _pwm_input_capture_param +{ + bool captureInputSel; /*!< true: Use the edge counter signal as source + false: Use the raw input signal from the pin as source */ + uint8_t edgeCompareValue; /*!< Compare value, used only if edge counter is used as source */ + pwm_input_capture_edge_t edge0; /*!< Specify which edge causes a capture for input circuitry 0 */ + pwm_input_capture_edge_t edge1; /*!< Specify which edge causes a capture for input circuitry 1 */ + bool enableOneShotCapture; /*!< true: Use one-shot capture mode; + false: Use free-running capture mode */ + uint8_t fifoWatermark; /*!< Watermark level for capture FIFO. The capture flags in + the status register will set if the word count in the FIFO + is greater than this watermark level */ +} pwm_input_capture_param_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the PWM submodule clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application using the PWM driver. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param config Pointer to user's PWM config structure. + * + * @return kStatus_Success means success; else failed. + */ +status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t *config); + +/*! + * @brief Gate the PWM submodule clock + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to deinitialize + */ +void PWM_Deinit(PWM_Type *base, pwm_submodule_t subModule); + +/*! + * @brief Fill in the PWM config struct with the default settings + * + * The default values are: + * @code + * config->enableDebugMode = false; + * config->enableWait = false; + * config->reloadSelect = kPWM_LocalReload; + * config->clockSource = kPWM_BusClock; + * config->prescale = kPWM_Prescale_Divide_1; + * config->initializationControl = kPWM_Initialize_LocalSync; + * config->forceTrigger = kPWM_Force_Local; + * config->reloadFrequency = kPWM_LoadEveryOportunity; + * config->reloadLogic = kPWM_ReloadImmediate; + * config->pairOperation = kPWM_Independent; + * @endcode + * @param config Pointer to user's PWM config structure. + */ +void PWM_GetDefaultConfig(pwm_config_t *config); + +/*! @}*/ + +/*! + * @name Module PWM output + * @{ + */ +/*! + * @brief Sets up the PWM signals for a PWM submodule. + * + * The function initializes the submodule according to the parameters passed in by the user. The function + * also sets up the value compare registers to match the PWM signal requirements. + * If the dead time insertion logic is enabled, the pulse period is reduced by the + * dead time period specified by the user. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param chnlParams Array of PWM channel parameters to configure the channel(s), PWMX submodule is not supported. + * @param numOfChnls Number of channels to configure, this should be the size of the array passed in. + * Array size should not be more than 2 as each submodule has 2 pins to output PWM + * @param mode PWM operation mode, options available in enumeration ::pwm_mode_t + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz PWM source clock of correspond submodule in Hz. If source clock of submodule1,2,3 is from + * submodule0 AUX_CLK, its source clock is submodule0 source clock divided with submodule0 + * prescaler value instead of submodule0 source clock. + * + * @return Returns kStatus_Fail if there was error setting up the signal; kStatus_Success otherwise + */ +status_t PWM_SetupPwm(PWM_Type *base, + pwm_submodule_t subModule, + const pwm_signal_param_t *chnlParams, + uint8_t numOfChnls, + pwm_mode_t mode, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz); + +/*! + * @brief Set PWM phase shift for PWM channel running on channel PWM_A, PWM_B which with 50% duty cycle. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel PWM channel to configure + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz PWM main counter clock in Hz. + * @param shiftvalue Phase shift value, range in 0 ~ 50 + * @param doSync true: Set LDOK bit for the submodule list; + * false: LDOK bit don't set, need to call PWM_SetPwmLdok to sync update. + * + * @return Returns kStatus_Fail if there was error setting up the signal; kStatus_Success otherwise + */ +status_t PWM_SetupPwmPhaseShift(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + uint8_t shiftvalue, + bool doSync); + +/*! + * @brief Updates the PWM signal's dutycycle. + * + * The function updates the PWM dutycyle to the new value that is passed in. + * If the dead time insertion logic is enabled then the pulse period is reduced by the + * dead time period specified by the user. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmSignal Signal (PWM A or PWM B) to update + * @param currPwmMode The current PWM mode set during PWM setup + * @param dutyCyclePercent New PWM pulse width, value should be between 0 to 100 + * 0=inactive signal(0% duty cycle)... + * 100=active signal (100% duty cycle) + */ +void PWM_UpdatePwmDutycycle(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmSignal, + pwm_mode_t currPwmMode, + uint8_t dutyCyclePercent); + +/*! + * @brief Updates the PWM signal's dutycycle with 16-bit accuracy. + * + * The function updates the PWM dutycyle to the new value that is passed in. + * If the dead time insertion logic is enabled then the pulse period is reduced by the + * dead time period specified by the user. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmSignal Signal (PWM A or PWM B) to update + * @param currPwmMode The current PWM mode set during PWM setup + * @param dutyCycle New PWM pulse width, value should be between 0 to 65535 + * 0=inactive signal(0% duty cycle)... + * 65535=active signal (100% duty cycle) + */ +void PWM_UpdatePwmDutycycleHighAccuracy( + PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint16_t dutyCycle); + +/*! + * @brief Update the PWM signal's period and dutycycle for a PWM submodule. + * + * The function updates PWM signal period generated by a specific submodule according to the parameters + * passed in by the user. This function can also set dutycycle weather you want to keep original dutycycle + * or update new dutycycle. Call this function in local sync control mode because PWM period is depended by + * INIT and VAL1 register of each submodule. In master sync initialization control mode, call this function + * to update INIT and VAL1 register of all submodule because PWM period is depended by INIT and VAL1 register + * in submodule0. If the dead time insertion logic is enabled, the pulse period is reduced by the dead time + * period specified by the user. PWM signal will not be generated if its period is less than dead time duration. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmSignal Signal (PWM A or PWM B) to update + * @param currPwmMode The current PWM mode set during PWM setup, options available in enumeration ::pwm_mode_t + * @param pulseCnt New PWM period, value should be between 0 to 65535 + * 0=minimum PWM period... + * 65535=maximum PWM period + * @param dutyCycle New PWM pulse width of channel, value should be between 0 to 65535 + * 0=inactive signal(0% duty cycle)... + * 65535=active signal (100% duty cycle) + * You can keep original duty cycle or update new duty cycle + */ +void PWM_UpdatePwmPeriodAndDutycycle(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmSignal, + pwm_mode_t currPwmMode, + uint16_t pulseCnt, + uint16_t dutyCycle); + +/*! @}*/ + +/*! + * @brief Sets up the PWM input capture + * + * Each PWM submodule has 3 pins that can be configured for use as input capture pins. This function + * sets up the capture parameters for each pin and enables the pin for input capture operation. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel Channel in the submodule to setup + * @param inputCaptureParams Parameters passed in to set up the input pin + */ +void PWM_SetupInputCapture(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + const pwm_input_capture_param_t *inputCaptureParams); + +/*! + * @brief Sets up the PWM fault input filter. + * + * @param base PWM peripheral base address + * @param faultInputFilterParams Parameters passed in to set up the fault input filter. + */ +void PWM_SetupFaultInputFilter(PWM_Type *base, const pwm_fault_input_filter_param_t *faultInputFilterParams); + +/*! + * @brief Sets up the PWM fault protection. + * + * PWM has 4 fault inputs. + * + * @param base PWM peripheral base address + * @param faultNum PWM fault to configure. + * @param faultParams Pointer to the PWM fault config structure + */ +void PWM_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, const pwm_fault_param_t *faultParams); + +/*! + * @brief Fill in the PWM fault config struct with the default settings + * + * The default values are: + * @code + * config->faultClearingMode = kPWM_Automatic; + * config->faultLevel = false; + * config->enableCombinationalPath = true; + * config->recoverMode = kPWM_NoRecovery; + * @endcode + * @param config Pointer to user's PWM fault config structure. + */ +void PWM_FaultDefaultConfig(pwm_fault_param_t *config); + +/*! + * @brief Selects the signal to output on a PWM pin when a FORCE_OUT signal is asserted. + * + * The user specifies which channel to configure by supplying the submodule number and whether + * to modify PWM A or PWM B within that submodule. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel Channel to configure + * @param mode Signal to output when a FORCE_OUT is triggered + */ +void PWM_SetupForceSignal(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + pwm_force_signal_t mode); + +/*! + * @name Interrupts Interface + * @{ + */ + +/*! + * @brief Enables the selected PWM interrupts + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +void PWM_EnableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask); + +/*! + * @brief Disables the selected PWM interrupts + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +void PWM_DisableInterrupts(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask); + +/*! + * @brief Gets the enabled PWM interrupts + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::pwm_interrupt_enable_t + */ +uint32_t PWM_GetEnabledInterrupts(PWM_Type *base, pwm_submodule_t subModule); + +/*! @}*/ + +/*! + * @name DMA Interface + * @{ + */ + +/*! + * @brief Capture DMA Enable Source Select. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwm_watermark_control PWM FIFO watermark and control + */ +static inline void PWM_DMAFIFOWatermarkControl(PWM_Type *base, + pwm_submodule_t subModule, + pwm_watermark_control_t pwm_watermark_control) +{ + uint16_t reg = base->SM[subModule].DMAEN; + if (pwm_watermark_control == kPWM_FIFOWatermarksOR) + { + reg &= ~((uint16_t)PWM_DMAEN_FAND_MASK); + } + else + { + reg |= ((uint16_t)PWM_DMAEN_FAND_MASK); + } + base->SM[subModule].DMAEN = reg; +} + +/*! + * @brief Capture DMA Enable Source Select. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwm_dma_source_select PWM capture DMA enable source select + */ +static inline void PWM_DMACaptureSourceSelect(PWM_Type *base, + pwm_submodule_t subModule, + pwm_dma_source_select_t pwm_dma_source_select) +{ + uint16_t reg = base->SM[subModule].DMAEN; + + reg &= ~((uint16_t)PWM_DMAEN_CAPTDE_MASK); + reg |= (((uint16_t)pwm_dma_source_select << (uint16_t)PWM_DMAEN_CAPTDE_SHIFT) & (uint16_t)PWM_DMAEN_CAPTDE_MASK); + + base->SM[subModule].DMAEN = reg; +} + +/*! + * @brief Enables or disables the selected PWM DMA Capture read request. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param mask The DMA to enable or disable. This is a logical OR of members of the + * enumeration ::pwm_dma_enable_t + * @param activate true: Enable DMA read request; false: Disable DMA read request + */ +static inline void PWM_EnableDMACapture(PWM_Type *base, pwm_submodule_t subModule, uint16_t mask, bool activate) +{ + uint16_t reg = base->SM[subModule].DMAEN; + if (activate) + { + reg |= (uint16_t)(mask); + } + else + { + reg &= ~((uint16_t)(mask)); + } + base->SM[subModule].DMAEN = reg; +} + +/*! + * @brief Enables or disables the PWM DMA write request. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param activate true: Enable DMA write request; false: Disable DMA write request + */ +static inline void PWM_EnableDMAWrite(PWM_Type *base, pwm_submodule_t subModule, bool activate) +{ + uint16_t reg = base->SM[subModule].DMAEN; + if (activate) + { + reg |= ((uint16_t)PWM_DMAEN_VALDE_MASK); + } + else + { + reg &= ~((uint16_t)PWM_DMAEN_VALDE_MASK); + } + base->SM[subModule].DMAEN = reg; +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the PWM status flags + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::pwm_status_flags_t + */ +uint32_t PWM_GetStatusFlags(PWM_Type *base, pwm_submodule_t subModule); + +/*! + * @brief Clears the PWM status flags + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::pwm_status_flags_t + */ +void PWM_ClearStatusFlags(PWM_Type *base, pwm_submodule_t subModule, uint32_t mask); + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the PWM counter for a single or multiple submodules. + * + * Sets the Run bit which enables the clocks to the PWM submodule. This function can start multiple + * submodules at the same time. + * + * @param base PWM peripheral base address + * @param subModulesToStart PWM submodules to start. This is a logical OR of members of the + * enumeration ::pwm_module_control_t + */ +static inline void PWM_StartTimer(PWM_Type *base, uint8_t subModulesToStart) +{ + base->MCTRL |= PWM_MCTRL_RUN(subModulesToStart); +} + +/*! + * @brief Stops the PWM counter for a single or multiple submodules. + * + * Clears the Run bit which resets the submodule's counter. This function can stop multiple + * submodules at the same time. + * + * @param base PWM peripheral base address + * @param subModulesToStop PWM submodules to stop. This is a logical OR of members of the + * enumeration ::pwm_module_control_t + */ +static inline void PWM_StopTimer(PWM_Type *base, uint8_t subModulesToStop) +{ + base->MCTRL &= ~(PWM_MCTRL_RUN(subModulesToStop)); +} + +/*! @}*/ + +/*! + * @brief Set the PWM VALx registers. + * + * This function allows the user to write value into VAL registers directly. And it will destroying the PWM clock period + * set by the PWM_SetupPwm()/PWM_SetupPwmPhaseShift() functions. + * Due to VALx registers are bufferd, the new value will not active uless call PWM_SetPwmLdok() and the reload point is + * reached. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param valueRegister VALx register that will be writen new value + * @param value Value that will been write into VALx register + */ +static inline void PWM_SetVALxValue(PWM_Type *base, + pwm_submodule_t subModule, + pwm_value_register_t valueRegister, + uint16_t value) +{ + switch (valueRegister) + { + case kPWM_ValueRegister_0: + base->SM[subModule].VAL0 = value; + break; + case kPWM_ValueRegister_1: + base->SM[subModule].VAL1 = value; + break; + case kPWM_ValueRegister_2: + base->SM[subModule].VAL2 = value; + break; + case kPWM_ValueRegister_3: + base->SM[subModule].VAL3 = value; + break; + case kPWM_ValueRegister_4: + base->SM[subModule].VAL4 = value; + break; + case kPWM_ValueRegister_5: + base->SM[subModule].VAL5 = value; + break; + default: + assert(false); + break; + } +} + +/*! + * @brief Get the PWM VALx registers. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param valueRegister VALx register that will be read value + * @return The VALx register value + */ +static inline uint16_t PWM_GetVALxValue(PWM_Type *base, pwm_submodule_t subModule, pwm_value_register_t valueRegister) +{ + uint16_t temp = 0U; + + switch (valueRegister) + { + case kPWM_ValueRegister_0: + temp = base->SM[subModule].VAL0; + break; + case kPWM_ValueRegister_1: + temp = base->SM[subModule].VAL1; + break; + case kPWM_ValueRegister_2: + temp = base->SM[subModule].VAL2; + break; + case kPWM_ValueRegister_3: + temp = base->SM[subModule].VAL3; + break; + case kPWM_ValueRegister_4: + temp = base->SM[subModule].VAL4; + break; + case kPWM_ValueRegister_5: + temp = base->SM[subModule].VAL5; + break; + default: + assert(false); + break; + } + + return temp; +} + +/*! + * @brief Enables or disables the PWM output trigger. + * + * This function allows the user to enable or disable the PWM trigger. The PWM has 2 triggers. Trigger 0 + * is activated when the counter matches VAL 0, VAL 2, or VAL 4 register. Trigger 1 is activated + * when the counter matches VAL 1, VAL 3, or VAL 5 register. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param valueRegister Value register that will activate the trigger + * @param activate true: Enable the trigger; false: Disable the trigger + */ +static inline void PWM_OutputTriggerEnable(PWM_Type *base, + pwm_submodule_t subModule, + pwm_value_register_t valueRegister, + bool activate) +{ + if (activate) + { + base->SM[subModule].TCTRL |= ((uint16_t)1U << (uint16_t)valueRegister); + } + else + { + base->SM[subModule].TCTRL &= ~((uint16_t)1U << (uint16_t)valueRegister); + } +} + +/*! + * @brief Enables the PWM output trigger. + * + * This function allows the user to enable one or more (VAL0-5) PWM trigger. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param valueRegisterMask Value register mask that will activate one or more (VAL0-5) trigger + * enumeration ::_pwm_value_register_mask + */ +static inline void PWM_ActivateOutputTrigger(PWM_Type *base, pwm_submodule_t subModule, uint16_t valueRegisterMask) +{ + base->SM[subModule].TCTRL |= (PWM_TCTRL_OUT_TRIG_EN_MASK & (valueRegisterMask)); +} + +/*! + * @brief Disables the PWM output trigger. + * + * This function allows the user to disables one or more (VAL0-5) PWM trigger. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param valueRegisterMask Value register mask that will Deactivate one or more (VAL0-5) trigger + * enumeration ::_pwm_value_register_mask + */ +static inline void PWM_DeactivateOutputTrigger(PWM_Type *base, pwm_submodule_t subModule, uint16_t valueRegisterMask) +{ + base->SM[subModule].TCTRL &= ~(PWM_TCTRL_OUT_TRIG_EN_MASK & (valueRegisterMask)); +} + +/*! + * @brief Sets the software control output for a pin to high or low. + * + * The user specifies which channel to modify by supplying the submodule number and whether + * to modify PWM A or PWM B within that submodule. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel Channel to configure + * @param value true: Supply a logic 1, false: Supply a logic 0. + */ +static inline void PWM_SetupSwCtrlOut(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, bool value) +{ + if (value) + { + base->SWCOUT |= + ((uint16_t)1U << (((uint16_t)subModule * (uint16_t)PWM_SUBMODULE_SWCONTROL_WIDTH) + (uint16_t)pwmChannel)); + } + else + { + base->SWCOUT &= + ~((uint16_t)1U << (((uint16_t)subModule * (uint16_t)PWM_SUBMODULE_SWCONTROL_WIDTH) + (uint16_t)pwmChannel)); + } +} + +/*! + * @brief Sets or clears the PWM LDOK bit on a single or multiple submodules + * + * Set LDOK bit to load buffered values into CTRL[PRSC] and the INIT, FRACVAL and VAL registers. The + * values are loaded immediately if kPWM_ReloadImmediate option was choosen during config. Else the + * values are loaded at the next PWM reload point. + * This function can issue the load command to multiple submodules at the same time. + * + * @param base PWM peripheral base address + * @param subModulesToUpdate PWM submodules to update with buffered values. This is a logical OR of + * members of the enumeration ::pwm_module_control_t + * @param value true: Set LDOK bit for the submodule list; false: Clear LDOK bit + */ +static inline void PWM_SetPwmLdok(PWM_Type *base, uint8_t subModulesToUpdate, bool value) +{ + if (value) + { + base->MCTRL |= PWM_MCTRL_LDOK(subModulesToUpdate); + } + else + { + base->MCTRL |= PWM_MCTRL_CLDOK(subModulesToUpdate); + } +} + +/*! + * @brief Set PWM output fault status + * + * These bits determine the fault state for the PWM_A output in fault conditions + * and STOP mode. It may also define the output state in WAIT and DEBUG modes + * depending on the settings of CTRL2[WAITEN] and CTRL2[DBGEN]. + * This function can update PWM output fault status. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel Channel to configure + * @param faultState PWM output fault status + */ +static inline void PWM_SetPwmFaultState(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + pwm_fault_state_t faultState) +{ + uint16_t reg = base->SM[subModule].OCTRL; + switch (pwmChannel) + { + case kPWM_PwmA: + reg &= ~((uint16_t)PWM_OCTRL_PWMAFS_MASK); + reg |= (((uint16_t)faultState << (uint16_t)PWM_OCTRL_PWMAFS_SHIFT) & (uint16_t)PWM_OCTRL_PWMAFS_MASK); + break; + case kPWM_PwmB: + reg &= ~((uint16_t)PWM_OCTRL_PWMBFS_MASK); + reg |= (((uint16_t)faultState << (uint16_t)PWM_OCTRL_PWMBFS_SHIFT) & (uint16_t)PWM_OCTRL_PWMBFS_MASK); + break; + case kPWM_PwmX: + reg &= ~((uint16_t)PWM_OCTRL_PWMXFS_MASK); + reg |= (((uint16_t)faultState << (uint16_t)PWM_OCTRL_PWMXFS_SHIFT) & (uint16_t)PWM_OCTRL_PWMXFS_MASK); + break; + default: + assert(false); + break; + } + base->SM[subModule].OCTRL = reg; +} + +/*! + * @brief Set PWM fault disable mapping + * + * Each of the four bits of this read/write field is one-to-one associated + * with the four FAULTx inputs of fault channel 0/1. The PWM output will be turned + * off if there is a logic 1 on an FAULTx input and a 1 in the corresponding + * bit of this field. A reset sets all bits in this field. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel PWM channel to configure + * @param pwm_fault_channels PWM fault channel to configure + * @param value Fault disable mapping mask value + * enumeration ::pwm_fault_disable_t + */ +static inline void PWM_SetupFaultDisableMap(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + pwm_fault_channels_t pwm_fault_channels, + uint16_t value) +{ + uint16_t reg = base->SM[subModule].DISMAP[pwm_fault_channels]; + switch (pwmChannel) + { + case kPWM_PwmA: + reg &= ~((uint16_t)PWM_DISMAP_DIS0A_MASK); + reg |= (((uint16_t)(value) << (uint16_t)PWM_DISMAP_DIS0A_SHIFT) & (uint16_t)PWM_DISMAP_DIS0A_MASK); + break; + case kPWM_PwmB: + reg &= ~((uint16_t)PWM_DISMAP_DIS0B_MASK); + reg |= (((uint16_t)(value) << (uint16_t)PWM_DISMAP_DIS0B_SHIFT) & (uint16_t)PWM_DISMAP_DIS0B_MASK); + break; + case kPWM_PwmX: + reg &= ~((uint16_t)PWM_DISMAP_DIS0X_MASK); + reg |= (((uint16_t)(value) << (uint16_t)PWM_DISMAP_DIS0X_SHIFT) & (uint16_t)PWM_DISMAP_DIS0X_MASK); + break; + default: + assert(false); + break; + } + base->SM[subModule].DISMAP[pwm_fault_channels] = reg; +} + +/*! + * @brief Set PWM output enable + * + * This feature allows the user to enable the PWM Output. + * + * @param base PWM peripheral base address + * @param pwmChannel PWM channel to configure + * @param subModule PWM submodule to configure + */ +static inline void PWM_OutputEnable(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule) +{ + /* Set PWM output */ + switch (pwmChannel) + { + case kPWM_PwmA: + base->OUTEN |= ((uint16_t)1U << ((uint16_t)PWM_OUTEN_PWMA_EN_SHIFT + (uint16_t)subModule)); + break; + case kPWM_PwmB: + base->OUTEN |= ((uint16_t)1U << ((uint16_t)PWM_OUTEN_PWMB_EN_SHIFT + (uint16_t)subModule)); + break; + case kPWM_PwmX: + base->OUTEN |= ((uint16_t)1U << ((uint16_t)PWM_OUTEN_PWMX_EN_SHIFT + (uint16_t)subModule)); + break; + default: + assert(false); + break; + } +} + +/*! + * @brief Set PWM output disable + * + *This feature allows the user to disable the PWM output. + * + * @param base PWM peripheral base address + * @param pwmChannel PWM channel to configure + * @param subModule PWM submodule to configure + */ +static inline void PWM_OutputDisable(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule) +{ + switch (pwmChannel) + { + case kPWM_PwmA: + base->OUTEN &= ~((uint16_t)1U << ((uint16_t)PWM_OUTEN_PWMA_EN_SHIFT + (uint16_t)subModule)); + break; + case kPWM_PwmB: + base->OUTEN &= ~((uint16_t)1U << ((uint16_t)PWM_OUTEN_PWMB_EN_SHIFT + (uint16_t)subModule)); + break; + case kPWM_PwmX: + base->OUTEN &= ~((uint16_t)1U << ((uint16_t)PWM_OUTEN_PWMX_EN_SHIFT + (uint16_t)subModule)); + break; + default: + assert(false); + break; + } +} + +/*! + * @brief Get the dutycycle value. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel PWM channel to configure + * + * @return Current channel dutycycle value. + */ +uint8_t PWM_GetPwmChannelState(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel); + +/*! + * @brief Set PWM output in idle status (high or low). + * + * @note This API should call after PWM_SetupPwm() APIs, and PWMX submodule is not supported. + * + * @param base PWM peripheral base address + * @param pwmChannel PWM channel to configure + * @param subModule PWM submodule to configure + * @param idleStatus True: PWM output is high in idle status; false: PWM output is low in idle status. + * + * @return kStatus_Fail if there was error setting up the signal; kStatus_Success if set output idle success + */ +status_t PWM_SetOutputToIdle(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, bool idleStatus); + +/*! + * @brief Set the pwm submodule prescaler. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param prescaler Set prescaler value + */ +void PWM_SetClockMode(PWM_Type *base, pwm_submodule_t subModule, pwm_clock_prescale_t prescaler); + +/*! + * @brief This function enables-disables the forcing of the output of a given eFlexPwm channel to logic 0. + * + * @param base PWM peripheral base address + * @param pwmChannel PWM channel to configure + * @param subModule PWM submodule to configure + * @param forcetozero True: Enable the pwm force output to zero; False: Disable the pwm output resumes normal + * function. + */ +void PWM_SetPwmForceOutputToZero(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + bool forcetozero); + +/*! + * @brief This function set the output state of the PWM pin as requested for the current cycle. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel PWM channel to configure + * @param outputstate Set pwm output state, see @ref pwm_output_state_t. + */ +void PWM_SetChannelOutput(PWM_Type *base, + pwm_submodule_t subModule, + pwm_channels_t pwmChannel, + pwm_output_state_t outputstate); + +#if defined(FSL_FEATURE_PWM_HAS_PHASE_DELAY) && FSL_FEATURE_PWM_HAS_PHASE_DELAY +/*! + * @brief This function set the phase delay from the master sync signal of submodule 0. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel PWM channel to configure + * @param delayCycles Number of cycles delayed from submodule 0. + * + * @return kStatus_Fail if the number of delay cycles is set larger than the period defined in submodule 0; + * kStatus_Success if set phase delay success + */ +status_t PWM_SetPhaseDelay(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submodule_t subModule, uint16_t delayCycles); +#endif + +#if defined(FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE) && FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE +/*! + * @brief This function set the number of consecutive samples that must agree prior to the input filter. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel PWM channel to configure + * @param filterSampleCount Number of consecutive samples. + */ +static inline void PWM_SetFilterSampleCount(PWM_Type *base, + pwm_channels_t pwmChannel, + pwm_submodule_t subModule, + uint8_t filterSampleCount) +{ + switch(pwmChannel) + { +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA + case kPWM_PwmA: + base->SM[subModule].CAPTFILTA &= ~((uint16_t)PWM_CAPTFILTA_CAPTA_FILT_CNT_MASK); + base->SM[subModule].CAPTFILTA |= PWM_CAPTFILTA_CAPTA_FILT_CNT(filterSampleCount); + break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB + case kPWM_PwmB: + base->SM[subModule].CAPTFILTB &= ~((uint16_t)PWM_CAPTFILTB_CAPTB_FILT_CNT_MASK); + base->SM[subModule].CAPTFILTB |= PWM_CAPTFILTB_CAPTB_FILT_CNT(filterSampleCount); + break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX + case kPWM_PwmX: + base->SM[subModule].CAPTFILTX &= ~((uint16_t)PWM_CAPTFILTX_CAPTX_FILT_CNT_MASK); + base->SM[subModule].CAPTFILTX |= PWM_CAPTFILTX_CAPTX_FILT_CNT(filterSampleCount); + break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */ + default: + assert(false); + break; + } +} + +/*! + * @brief This function set the sampling period of the fault pin input filter. + * + * @param base PWM peripheral base address + * @param subModule PWM submodule to configure + * @param pwmChannel PWM channel to configure + * @param filterSamplePeriod Sampling period of input filter. + */ +static inline void PWM_SetFilterSamplePeriod(PWM_Type *base, + pwm_channels_t pwmChannel, + pwm_submodule_t subModule, + uint8_t filterSamplePeriod) +{ + switch(pwmChannel) + { +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA + case kPWM_PwmA: + base->SM[subModule].CAPTFILTA &= ~((uint16_t)PWM_CAPTFILTA_CAPTA_FILT_PER_MASK); + base->SM[subModule].CAPTFILTA |= PWM_CAPTFILTA_CAPTA_FILT_PER(filterSamplePeriod); + break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB + case kPWM_PwmB: + base->SM[subModule].CAPTFILTB &= ~((uint16_t)PWM_CAPTFILTB_CAPTB_FILT_PER_MASK); + base->SM[subModule].CAPTFILTB |= PWM_CAPTFILTB_CAPTB_FILT_PER(filterSamplePeriod); + break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB */ +#if defined(FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX) && FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX + case kPWM_PwmX: + base->SM[subModule].CAPTFILTX &= ~((uint16_t)PWM_CAPTFILTX_CAPTX_FILT_PER_MASK); + base->SM[subModule].CAPTFILTX |= PWM_CAPTFILTX_CAPTX_FILT_PER(filterSamplePeriod); + break; +#endif /* FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX */ + default: + assert(false); + break; + } +} +#endif + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_PWM_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_reset.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_reset.c new file mode 100644 index 00000000000..1b49d0edab8 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_reset.c @@ -0,0 +1,141 @@ +/* + * Copyright 2023, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_reset.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.reset" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#define GET_REG_INDEX(x) ((uint32_t)(((uint32_t)(x) & 0xFF00U) >> 8)) +#define GET_BIT_INDEX(x) ((uint32_t)((uint32_t)(x) & 0x00FFU)) + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral) +{ + uint32_t regIndex = GET_REG_INDEX(peripheral); + uint32_t bitPos = GET_BIT_INDEX(peripheral); + uint32_t bitMask = 1UL << bitPos; + volatile uint32_t *pResetCtrl = &(MRCC0->MRCC_GLB_RST0); + + if (peripheral == NotAvail_RSTn) + { + return; + } + + assert(bitPos < 32u); + assert(regIndex < 2u); + + /* Unlock clock configuration */ + SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK; + + /* reset register is in MRCC */ + /* set bit */ + if (regIndex == 0U) + { + MRCC0->MRCC_GLB_RST0_SET = bitMask; + pResetCtrl = &(MRCC0->MRCC_GLB_RST0); + } + else if (regIndex == 1U) + { + MRCC0->MRCC_GLB_RST1_SET = bitMask; + pResetCtrl = &(MRCC0->MRCC_GLB_RST1); + } + else + { + /* Added comments to prevent the violation of MISRA C-2012 rule 15.7 */ + } + /* wait until it reads 0b1 */ + while (0u == ((*pResetCtrl) & bitMask)) + { + } + + /* Freeze clock configuration */ + SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK; +} + +/*! + * brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) +{ + uint32_t regIndex = GET_REG_INDEX(peripheral); + uint32_t bitPos = GET_BIT_INDEX(peripheral); + uint32_t bitMask = 1UL << bitPos; + volatile uint32_t *pResetCtrl = &(MRCC0->MRCC_GLB_RST0); + + assert(bitPos < 32u); + + /* Unlock clock configuration */ + SYSCON->CLKUNLOCK &= ~SYSCON_CLKUNLOCK_UNLOCK_MASK; + + /* reset register is in MRCC */ + /* clear bit */ + if (regIndex == 0U) + { + MRCC0->MRCC_GLB_RST0_CLR = bitMask; + pResetCtrl = &(MRCC0->MRCC_GLB_RST0); + } + else if (regIndex == 1U) + { + MRCC0->MRCC_GLB_RST1_CLR = bitMask; + pResetCtrl = &(MRCC0->MRCC_GLB_RST1); + } + else + { + /* Added comments to prevent the violation of MISRA C-2012 rule 15.7 */ + } + /* wait until it reads 0b0 */ + while (bitMask == ((*pResetCtrl) & bitMask)) + { + } + + /* Freeze clock configuration */ + SYSCON->CLKUNLOCK |= SYSCON_CLKUNLOCK_UNLOCK_MASK; +} + +/*! + * brief Reset peripheral module. + * + * Reset peripheral module. + * + * param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral) +{ + RESET_ClearPeripheralReset(peripheral); + RESET_SetPeripheralReset(peripheral); +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_reset.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_reset.h new file mode 100644 index 00000000000..29a31915036 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_reset.h @@ -0,0 +1,251 @@ +/* + * Copyright 2023, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_RESET_H_ +#define _FSL_RESET_H_ + +#include +#include +#include +#include +#include "fsl_device_registers.h" + +/*! + * @addtogroup reset + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief reset driver version 2.4.0 */ +#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) +/*@}*/ + +/*! + * @brief Enumeration for peripheral reset control bits + * + * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers + */ +typedef enum _SYSCON_RSTn +{ + kINPUTMUX0_RST_SHIFT_RSTn = (0U | (0U)), /*!< INPUTMUX0 reset control */ + kI3C0_RST_SHIFT_RSTn = (0U | (1U)), /*!< I3C0 reset control */ + kCTIMER0_RST_SHIFT_RSTn = (0U | (2U)), /*!< CTIMER0 reset control */ + kCTIMER1_RST_SHIFT_RSTn = (0U | (3U)), /*!< CTIMER1 reset control */ + kCTIMER2_RST_SHIFT_RSTn = (0U | (4U)), /*!< CTIMER2 reset control */ + kCTIMER3_RST_SHIFT_RSTn = (0U | (5U)), /*!< CTIMER3 reset control */ + kCTIMER4_RST_SHIFT_RSTn = (0U | (6U)), /*!< CTIMER4 reset control */ + kFREQME_RST_SHIFT_RSTn = (0U | (7U)), /*!< FREQME reset control */ + kUTICK0_RST_SHIFT_RSTn = (0U | (8U)), /*!< UTICK0 reset control */ + kDMA_RST_SHIFT_RSTn = (0U | (10U)), /*!< DMA reset control */ + kAOI0_RST_SHIFT_RSTn = (0U | (11U)), /*!< AOI0 reset control */ + kCRC0_RST_SHIFT_RSTn = (0U | (12U)), /*!< CRC0 reset control */ + kEIM0_RST_SHIFT_RSTn = (0U | (13U)), /*!< EIM0 reset control */ + kERM0_RST_SHIFT_RSTn = (0U | (14U)), /*!< ERM0 reset control */ + kAOI1_RST_SHIFT_RSTn = (0U | (16U)), /*!< AOI1 reset control */ + kFLEXIO0_RST_SHIFT_RSTn = (0U | (17U)), /*!< FLEXIO0 reset control */ + kLPI2C0_RST_SHIFT_RSTn = (0U | (18U)), /*!< LPI2C0 reset control */ + kLPI2C1_RST_SHIFT_RSTn = (0U | (19U)), /*!< LPI2C1 reset control */ + kLPSPI0_RST_SHIFT_RSTn = (0U | (20U)), /*!< LPSPI0 reset control */ + kLPSPI1_RST_SHIFT_RSTn = (0U | (21U)), /*!< LPSPI1 reset control */ + kLPUART0_RST_SHIFT_RSTn = (0U | (22U)), /*!< LPUART0 reset control */ + kLPUART1_RST_SHIFT_RSTn = (0U | (23U)), /*!< LPUART1 reset control */ + kLPUART2_RST_SHIFT_RSTn = (0U | (24U)), /*!< LPUART2 reset control */ + kLPUART3_RST_SHIFT_RSTn = (0U | (25U)), /*!< LPUART3 reset control */ + kLPUART4_RST_SHIFT_RSTn = (0U | (26U)), /*!< LPUART4 reset control */ + kUSB0_RST_SHIFT_RSTn = (0U | (27U)), /*!< USB0 reset control */ + kQDC0_RST_SHIFT_RSTn = (0U | (28U)), /*!< QDC0 reset control */ + kQDC1_RST_SHIFT_RSTn = (0U | (29U)), /*!< QDC1 reset control */ + kFLEXPWM0_RST_SHIFT_RSTn = (0U | (30U)), /*!< FLEXPWM0 reset control */ + kFLEXPWM1_RST_SHIFT_RSTn = (0U | (31U)), /*!< FLEXPWM1 reset control */ + kOSTIMER0_RST_SHIFT_RSTn = ((1U << 8U) | (0U)), /*!< OSTIMER0 reset control */ + kADC0_RST_SHIFT_RSTn = ((1U << 8U) | (1U)), /*!< ADC0 reset control */ + kADC1_RST_SHIFT_RSTn = ((1U << 8U) | (2U)), /*!< ADC1 reset control */ + kCMP1_RST_SHIFT_RSTn = ((1U << 8U) | (4U)), /*!< CMP1 reset control */ + kDAC0_RST_SHIFT_RSTn = ((1U << 8U) | (5U)), /*!< DAC0 reset control */ + kOPAMP0_RST_SHIFT_RSTn = ((1U << 8U) | (6U)), /*!< OPAMP0 reset control */ + kPORT0_RST_SHIFT_RSTn = ((1U << 8U) | (7U)), /*!< PORT0 reset control */ + kPORT1_RST_SHIFT_RSTn = ((1U << 8U) | (8U)), /*!< PORT1 reset control */ + kPORT2_RST_SHIFT_RSTn = ((1U << 8U) | (9U)), /*!< PORT2 reset control */ + kPORT3_RST_SHIFT_RSTn = ((1U << 8U) | (10U)), /*!< PORT3 reset control */ + kPORT4_RST_SHIFT_RSTn = ((1U << 8U) | (11U)), /*!< PORT4 reset control */ + kFLEXCAN0_RST_SHIFT_RSTn = ((1U << 8U) | (12U)), /*!< FLEXCAN0 reset control */ + kLPI2C2_RST_SHIFT_RSTn = ((1U << 8U) | (13U)), /*!< LPI2C2 reset control */ + kLPI2C3_RST_SHIFT_RSTn = ((1U << 8U) | (14U)), /*!< LPI2C3 reset control */ + kGPIO0_RST_SHIFT_RSTn = ((1U << 8U) | (20U)), /*!< GPIO0 reset control */ + kGPIO1_RST_SHIFT_RSTn = ((1U << 8U) | (21U)), /*!< GPIO1 reset control */ + kGPIO2_RST_SHIFT_RSTn = ((1U << 8U) | (22U)), /*!< GPIO2 reset control */ + kGPIO3_RST_SHIFT_RSTn = ((1U << 8U) | (23U)), /*!< GPIO3 reset control */ + kGPIO4_RST_SHIFT_RSTn = ((1U << 8U) | (24U)), /*!< GPIO4 reset control */ + NotAvail_RSTn = (0xFFFFU), /*!< No reset control */ +} SYSCON_RSTn_t; + +/** Array initializers with peripheral reset bits **/ +#define AOI_RSTS \ + { \ + kAOI0_RST_SHIFT_RSTn, kAOI1_RST_SHIFT_RSTn \ + } /* Reset bits for ADC peripheral */ +#define ADC_RSTS \ + { \ + kADC0_RST_SHIFT_RSTn, kADC1_RST_SHIFT_RSTn \ + } /* Reset bits for ADC peripheral */ +#define CRC_RSTS \ + { \ + kCRC0_RST_SHIFT_RSTn \ + } /* Reset bits for CRC peripheral */ +#define CTIMER_RSTS \ + { \ + kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \ + kCTIMER4_RST_SHIFT_RSTn \ + } /* Reset bits for CTIMER peripheral */ +#define DAC_RSTS_N \ + { \ + kDAC0_RST_SHIFT_RSTn \ + } /* Reset bits for DAC peripheral */ +#define DMA_RSTS_N \ + { \ + kDMA_RST_SHIFT_RSTn \ + } /* Reset bits for DMA peripheral */ +#define EIM_RSTS_N \ + { \ + kEIM0_RST_SHIFT_RSTn \ + } /* Reset bits for EIM peripheral */ +#define ERM_RSTS_N \ + { \ + kERM0_RST_SHIFT_RSTn \ + } /* Reset bits for ERM peripheral */ +#define FLEXCAN_RSTS_N \ + { \ + kFLEXCAN0_RST_SHIFT_RSTn \ + } /* Reset bits for FLEXCAN peripheral */ +#define FLEXIO_RSTS_N \ + { \ + kFLEXIO0_RST_SHIFT_RSTn \ + } /* Reset bits for FLEXIO peripheral */ +#define FLEXPWM_RSTS_N \ + { \ + kFLEXPWM0_RST_SHIFT_RSTn, kFLEXPWM1_RST_SHIFT_RSTn \ + } /* Reset bits for FLEXPWM peripheral */ +#define FREQME_RSTS_N \ + { \ + kFREQME_RST_SHIFT_RSTn \ + } /* Reset bits for FREQME peripheral */ +#define GPIO_RSTS_N \ + { \ + kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \ + kGPIO4_RST_SHIFT_RSTn \ + } /* Reset bits for GPIO peripheral */ +#define I3C_RSTS \ + { \ + kI3C0_RST_SHIFT_RSTn \ + } /* Reset bits for I3C peripheral */ +#define INPUTMUX_RSTS \ + { \ + kINPUTMUX0_RST_SHIFT_RSTn \ + } /* Reset bits for INPUTMUX peripheral */ +#define LPUART_RSTS \ + { \ + kLPUART0_RST_SHIFT_RSTn, kLPUART1_RST_SHIFT_RSTn, kLPUART2_RST_SHIFT_RSTn, kLPUART3_RST_SHIFT_RSTn, \ + kLPUART4_RST_SHIFT_RSTn \ + } /* Reset bits for LPUART peripheral */ +#define LPSPI_RSTS \ + { \ + kLPSPI0_RST_SHIFT_RSTn, kLPSPI1_RST_SHIFT_RSTn \ + } /* Reset bits for LPSPI peripheral */ +#define LPI2C_RSTS \ + { \ + kLPI2C0_RST_SHIFT_RSTn, kLPI2C1_RST_SHIFT_RSTn, kLPI2C2_RST_SHIFT_RSTn, kLPI2C3_RST_SHIFT_RSTn \ + } /* Reset bits for LPI2C peripheral */ +#define LPCMP_RSTS \ + { \ + NotAvail_RSTn, kCMP1_RST_SHIFT_RSTn \ + } /* Reset bits for LPCMP peripheral */ +#define OPAMP_RSTS \ + { \ + kOPAMP0_RST_SHIFT_RSTn \ + } /* Reset bits for OPAMP peripheral */ +#define OSTIMER_RSTS \ + { \ + kOSTIMER0_RST_SHIFT_RSTn \ + } /* Reset bits for OSTIMER peripheral */ +#define PORT_RSTS_N \ + { \ + kPORT0_RST_SHIFT_RSTn, kPORT1_RST_SHIFT_RSTn, kPORT2_RST_SHIFT_RSTn, kPORT3_RST_SHIFT_RSTn, \ + kPORT4_RST_SHIFT_RSTn \ + } /* Reset bits for PORT peripheral */ +#define EQDC_RSTS \ + { \ + kQDC0_RST_SHIFT_RSTn, kQDC1_RST_SHIFT_RSTn \ + } /* Reset bits for EQDC peripheral */ +#define UTICK_RSTS \ + { \ + kUTICK0_RST_SHIFT_RSTn \ + } /* Reset bits for UTICK peripheral */ + +typedef SYSCON_RSTn_t reset_ip_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Reset peripheral module. + * + * Reset peripheral module. + * + * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Release peripheral module. + * + * Release peripheral module. + * + * @param peripheral Peripheral to release. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +static inline void RESET_ReleasePeripheralReset(reset_ip_name_t peripheral) +{ + RESET_SetPeripheralReset(peripheral); +} + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_RESET_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_romapi.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_romapi.h new file mode 100644 index 00000000000..1f2f64f424f --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_romapi.h @@ -0,0 +1,507 @@ +/* + * Copyright 2023, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_ROMAPI_H_ +#define FSL_ROMAPI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup romapi + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.romapi" +#endif + +/*! @name Driver version */ +/*@{*/ + +/*! @brief romapi driver version 2.0.0. */ +#define FSL_ROMAPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! + * @name Flash status + * @{ + */ +/*! @brief Flash driver status group. */ +#if defined(kStatusGroup_FlashDriver) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FlashDriver +#elif defined(kStatusGroup_FLASHIAP) +#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupFlashDriver kStatusGroup_FLASH +#else +#define kStatusGroupGeneric 0 +#define kStatusGroupFlashDriver 1 +#endif + +/*! @brief Constructs a status code value from a group and a code number. */ +#if !defined(MAKE_STATUS) +#define MAKE_STATUS(group, code) ((((group) * 100) + (code))) +#endif + +/*! + * @brief Flash driver status codes. + */ +enum +{ + kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< API is executed successfully*/ + kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/ + kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/ + kStatus_FLASH_AlignmentError = + MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/ + kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */ + kStatus_FLASH_AccessError = + MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */ + kStatus_FLASH_ProtectionViolation = MAKE_STATUS( + kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */ + kStatus_FLASH_CommandFailure = + MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */ + kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/ + kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7) /*!< API erase key is invalid.*/ +}; +/*@}*/ + +/*! + * @brief Enumeration for various flash properties. + */ +typedef enum _flash_property_tag +{ + kFLASH_PropertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/ + kFLASH_PropertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/ + kFLASH_PropertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/ + kFLASH_PropertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/ + kFLASH_PropertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/ + kFLASH_PropertyPflashPageSize = 0x30U, /*!< Pflash page size property.*/ + kFLASH_PropertyPflashSystemFreq = 0x31U, /*!< System Frequency property.*/ + kFLASH_PropertyFfrSectorSize = 0x40U, /*!< FFR sector size property.*/ + kFLASH_PropertyFfrTotalSize = 0x41U, /*!< FFR total size property.*/ + kFLASH_PropertyFfrBlockBaseAddr = 0x42U, /*!< FFR block base address property.*/ + kFLASH_PropertyFfrPageSize = 0x43U, /*!< FFR page size property.*/ +} flash_property_tag_t; + +/*! @brief Flash controller paramter config. */ +typedef struct _flash_ffr_config +{ + uint32_t ffrBlockBase; + uint32_t ffrTotalSize; + uint32_t ffrPageSize; + uint32_t sectorSize; + uint32_t cfpaPageVersion; + uint32_t cfpaPageOffset; +} flash_ffr_config_t; + +/*! @brief Flash driver state information. + * + * An instance of this structure is allocated by the user of the flash driver and + * passed into each of the driver APIs. + */ +typedef struct _flash_config +{ + uint32_t PFlashBlockBase; /*!< A base address of the first PFlash block */ + uint32_t PFlashTotalSize; /*!< The size of the combined PFlash block. */ + uint32_t PFlashBlockCount; /*!< A number of PFlash blocks. */ + uint32_t PFlashPageSize; /*!< The size in bytes of a page of PFlash. */ + uint32_t PFlashSectorSize; /*!< The size in bytes of a sector of PFlash. */ + flash_ffr_config_t ffrConfig; +} flash_config_t; + +/*! @brief Interface for the flash driver. */ +typedef struct _flash_driver_interface +{ + /* Flash driver */ + status_t (*flash_init)(flash_config_t *config); + status_t (*flash_erase_sector)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*flash_program_phrase)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); + status_t (*flash_program_page)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); + status_t (*flash_verify_program)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + status_t (*flash_verify_erase_phrase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + status_t (*flash_verify_erase_page)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + status_t (*flash_verify_erase_sector)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + /* IFR driver */ + status_t (*ifr_verify_erase_phrase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + status_t (*ifr_verify_erase_page)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + status_t (*ifr_verify_erase_sector)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + status_t (*flash_read)(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); + /* version */ + uint32_t version; +} flash_driver_interface_t; + +/*! @brief Constructs the four character code for the Flash driver API key. */ +#if !defined(FOUR_CHAR_CODE) +#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a))) +#endif + +/*! + * @brief Enumeration for Flash driver API keys. + * + * @note The resulting value is built with a byte order such that the string + * being readable in expected order when viewed in a hex editor, if the value + * is treated as a 32-bit little endian value. + */ +enum _flash_driver_api_keys +{ + kFLASH_ApiEraseKey = FOUR_CHAR_CODE('l', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/ +}; + +/* API prototype fields definition. +| 31 : 24 | 23 : 20 | 19 : 16 | 15 : 12 | 11 : 8 | 7 ： 0 | +| Tag | Boot mode | bootloader periphal| Instance | Image Index| Reserved | +| | | | Used For Boot mode 0| | | +| | 0: Passive mode | 0 - Auto detection | | | | +| | 1: ISP mode | 1 - USB-HID | | | | +| | | 2 - UART | | | | +| | | 3 - SPI | | | | +| | | 4 - I2C | | | | +| | | 5 - CAN | | | | +*/ +typedef struct +{ + union + { + struct + { + uint32_t reserved : 8; + uint32_t boot_image_index : 4; + uint32_t instance : 4; + uint32_t boot_interface : 4; + uint32_t mode : 4; + uint32_t tag : 8; + } B; + uint32_t U; + } option; +} user_app_boot_invoke_option_t; + +/*! @brief Root of the bootloader API tree. + * + * An instance of this struct resides in read-only memory in the bootloader. It + * provides a user application access to APIs exported by the bootloader. + * + */ +typedef struct _bootloader_tree +{ + void (*run_bootloader)(void *arg); /*!< Function to start the bootloader executing. */ + const flash_driver_interface_t *flash_driver; /*!< Internal Flash driver API. */ + void (*jump)(void *arg); +} bootloader_tree_t; + +/** ROM API base address */ +#define ROM_API_BASE (0x03003fe0u) +/** ROM API base pointer */ +#define ROM_API ((bootloader_tree_t *)ROM_API_BASE) +/** FLASH API base pointer */ +#define FLASH_API (ROM_API->flash_driver) + +/*! + * @name Flash API + * @{ + */ + +/*! + * @brief Initializes the global flash properties structure members + * + * This function checks and initializes the Flash module for the other Flash APIs. + * + * @param config Pointer to the storage for the driver runtime state. + * + */ +static inline status_t FLASH_Init(flash_config_t *config) +{ + return FLASH_API->flash_init(config); +} + +/*! + * @brief Erases the flash sectors encompassed by parameters passed into function + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + * + * @param config The pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be erased. + * NOTE: The start address need to be 4 Bytes-aligned. + * + * @param lengthInBytes The length, given in bytes need be 4 Bytes-aligned. + * + * @param key The value used to validate all flash erase APIs. + * + */ +static inline status_t FLASH_EraseSector(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) +{ + return FLASH_API->flash_erase_sector(config, start, lengthInBytes, key); +} + +/*! + * @brief Programs flash phrases with data at locations passed in through parameters + * + * This function programs the flash memory with the desired data for a given + * flash area as determined by the start address and the length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param src A pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be programmed. Must be word-aligned. + * + */ +static inline status_t FLASH_ProgramPhrase(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) +{ + return FLASH_API->flash_program_phrase(config, start, src, lengthInBytes); +} + +/*! + * @brief Programs flash page with data at locations passed in through parameters + * + * This function programs the flash memory with the desired data for a given + * flash area as determined by the start address and the length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be programmed. Must be + * word-aligned. + * @param src A pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be programmed. Must be word-aligned. + * + */ +static inline status_t FLASH_ProgramPage(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) +{ + return FLASH_API->flash_program_page(config, start, src, lengthInBytes); +} + +/*! + * @brief Verifies programming of the desired flash area + * + * This function verifies the data programed in the flash memory using the + * Flash Program Check Command and compares it to the expected data for a given + * flash area as determined by the start address and length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. Must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be word-aligned. + * @param expectedData A pointer to the expected data that is to be + * verified against. + * @param failedAddress A pointer to the returned failing address. + * @param failedData A pointer to the returned failing data. Some derivatives do + * not include failed data as part of the FCCOBx registers. In this + * case, zeros are returned upon failure. + * + */ +static inline status_t FLASH_VerifyProgram(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData) +{ + return FLASH_API->flash_verify_program(config, start, lengthInBytes, expectedData, failedAddress, failedData); +} + +/*! + * @brief Verify that the flash phrases are erased + * + * This function checks the appropriate number of flash sectors based on + * the desired start address and length to check whether the flash is erased + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. + * The start address does not need to be sector-aligned but must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be word-aligned. + * + */ +static inline status_t FLASH_VerifyErasePhrase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes) +{ + return FLASH_API->flash_verify_erase_phrase(config, start, lengthInBytes); +} + +/*! + * @brief Verify that the flash pages are erased + * + * This function checks the appropriate number of flash sectors based on + * the desired start address and length to check whether the flash is erased + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. + * The start address does not need to be sector-aligned but must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be word-aligned. + * + */ +static inline status_t FLASH_VerifyErasePage(flash_config_t *config, uint32_t start, uint32_t lengthInBytes) +{ + return FLASH_API->flash_verify_erase_page(config, start, lengthInBytes); +} + +/*! + * @brief Verify that the flash sectors are erased + * + * This function checks the appropriate number of flash sectors based on + * the desired start address and length to check whether the flash is erased + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. + * The start address does not need to be sector-aligned but must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be word-aligned. + * + */ +static inline status_t FLASH_VerifyEraseSector(flash_config_t *config, uint32_t start, uint32_t lengthInBytes) +{ + return FLASH_API->flash_verify_erase_sector(config, start, lengthInBytes); +} + +/*! + * @brief Returns the desired flash property + * + * @param config A pointer to the storage for the driver runtime state. + * @param whichProperty The desired property from the list of properties in + * enum flash_property_tag_t + * @param value A pointer to the value returned for the desired flash property. + * + */ +static inline status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) +{ + return FLASH_API->flash_get_property(config, whichProperty, value); +} + +/*! + * @brief Verify that the IFR0 phrases are erased + * + * This function checks the appropriate number of flash sectors based on + * the desired start address and length to check whether the flash is erased + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. + * The start address does not need to be sector-aligned but must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be word-aligned. + * + */ +static inline status_t IFR_VerifyErasePhrase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes) +{ + return FLASH_API->ifr_verify_erase_phrase(config, start, lengthInBytes); +} + +/*! + * @brief Verify that the IFR0 pages are erased + * + * This function checks the appropriate number of flash sectors based on + * the desired start address and length to check whether the flash is erased + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. + * The start address does not need to be sector-aligned but must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be word-aligned. + * + */ +static inline status_t IFR_VerifyErasePage(flash_config_t *config, uint32_t start, uint32_t lengthInBytes) +{ + return FLASH_API->ifr_verify_erase_page(config, start, lengthInBytes); +} + +/*! + * @brief Verify that the IFR0 sectors are erased + * + * This function checks the appropriate number of flash sectors based on + * the desired start address and length to check whether the flash is erased + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be verified. + * The start address does not need to be sector-aligned but must be word-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be verified. Must be word-aligned. + * + */ +static inline status_t IFR_VerifyEraseSector(flash_config_t *config, uint32_t start, uint32_t lengthInBytes) +{ + return FLASH_API->ifr_verify_erase_sector(config, start, lengthInBytes); +} + +/*! + * @brief Reads flash at locations passed in through parameters + * + * This function read the flash memory from a given flash area as determined + * by the start address and the length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be read. + * @param dest A pointer to the dest buffer of data that is to be read + * from the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be read. + * + */ +static inline status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes) +{ + return FLASH_API->flash_read(config, start, dest, lengthInBytes); +} + +/*! + * @brief Get ROM API version. + * + * This function read the ROM API version. + * + */ +static inline uint32_t ROMAPI_GetVersion(void) +{ + return FLASH_API->version; +} + +/*! + * @brief Run the Bootloader API to force into the ISP mode base on the user arg + * + * @param arg Indicates API prototype fields definition. + * Refer to the above #user_app_boot_invoke_option_t structure + */ +static inline void ROMAPI_RunBootloader(void *arg) +{ + ROM_API->run_bootloader(arg); +} + +/*! + * @brief Get the UUID + * + * @param uuid UUID data array + * + */ +static inline void ROMAPI_GetUUID(uint8_t *uuid) +{ +#define MCXA_UUID_ADDR (0x01100800U) +#define MCXA_UUID_SIZE (16U) + + uint8_t *p = (uint8_t *)MCXA_UUID_ADDR; + for (uint8_t i = 0; i < MCXA_UUID_SIZE; i++) + { + *uuid = *p; + uuid++; + p++; + } +} + +/* @} */ + +/*! @} */ + +#endif /* FSL_ROMAPI_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_spc.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_spc.c new file mode 100644 index 00000000000..c6a9b293262 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_spc.c @@ -0,0 +1,1680 @@ +/* + * Copyright 2022-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_spc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.mcx_spc" +#endif + +/* + * $Coverage Justification Reference$ + * + * $Justification spc_c_ref_1$ + * The SPC busy status flag is too short to get coverage data. + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Gets selected power domain's requested low power mode. + * + * param base SPC peripheral base address. + * param powerDomainId Power Domain Id, please refer to spc_power_domain_id_t. + * + * return The selected power domain's requested low power mode, please refer to spc_power_domain_low_power_mode_t. + */ +spc_power_domain_low_power_mode_t SPC_GetPowerDomainLowPowerMode(SPC_Type *base, spc_power_domain_id_t powerDomainId) +{ + assert((uint8_t)powerDomainId < SPC_PD_STATUS_COUNT); + + uint32_t val; + + val = ((base->PD_STATUS[(uint8_t)powerDomainId] & SPC_PD_STATUS_LP_MODE_MASK) >> SPC_PD_STATUS_LP_MODE_SHIFT); + return (spc_power_domain_low_power_mode_t)val; +} + +/*! + * brief Gets Isolation status for each power domains. + * + * This function gets the status which indicates whether certain + * peripheral and the IO pads are in a latched state as a result + * of having been in POWERDOWN mode. + * + * param base SPC peripheral base address. + * return Current isolation status for each power domains. + */ +uint8_t SPC_GetPeriphIOIsolationStatus(SPC_Type *base) +{ + uint32_t reg; + + reg = base->SC; + return (uint8_t)((reg & SPC_SC_ISO_CLR_MASK) >> SPC_SC_ISO_CLR_SHIFT); +} + +/*! + * brief Configs Low power request output pin. + * + * This function configs the low power request output pin + * + * param base SPC peripheral base address. + * param config Pointer the spc_LowPower_Request_config_t structure. + */ +void SPC_SetLowPowerRequestConfig(SPC_Type *base, const spc_lowpower_request_config_t *config) +{ + assert(config != NULL); + + uint32_t reg; + + reg = base->LPREQ_CFG; + reg &= ~(SPC_LPREQ_CFG_LPREQOE_MASK | SPC_LPREQ_CFG_LPREQPOL_MASK | SPC_LPREQ_CFG_LPREQOV_MASK); + + if (config->enable) + { + reg |= SPC_LPREQ_CFG_LPREQOE_MASK | SPC_LPREQ_CFG_LPREQPOL((uint8_t)(config->polarity)) | + SPC_LPREQ_CFG_LPREQOV((uint8_t)(config->override)); + } + else + { + reg &= ~SPC_LPREQ_CFG_LPREQOE_MASK; + } + + base->LPREQ_CFG = reg; +} + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) +/*! + * brief Configures VDD Core Glitch detector, including ripple counter selection, timeout value and so on. + * + * param base SPC peripheral base address. + * param config Pointer to the structure in type of spc_vdd_core_glitch_detector_config_t. + */ +void SPC_ConfigVddCoreGlitchDetector(SPC_Type *base, const spc_vdd_core_glitch_detector_config_t *config) +{ + assert(config != NULL); + + uint32_t reg; + + reg = (base->VDD_CORE_GLITCH_DETECT_SC) & + ~(SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_MASK | SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_MASK | + SPC_VDD_CORE_GLITCH_DETECT_SC_RE_MASK | SPC_VDD_CORE_GLITCH_DETECT_SC_IE_MASK); + + reg |= SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT(config->rippleCounterSelect) | + SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT(config->resetTimeoutValue) | + SPC_VDD_CORE_GLITCH_DETECT_SC_RE(config->enableReset) | + SPC_VDD_CORE_GLITCH_DETECT_SC_IE(config->enableInterrupt); + + base->VDD_CORE_GLITCH_DETECT_SC = reg; +} +#endif + +/*! + * brief Set SRAM operate voltage. + * + * param base SPC peripheral base address. + * param config The pointer to spc_sram_voltage_config_t, specifies the configuration of sram voltage. + */ +void SPC_SetSRAMOperateVoltage(SPC_Type *base, const spc_sram_voltage_config_t *config) +{ + assert(config != NULL); + + uint32_t reg = 0UL; + + reg |= SPC_SRAMCTL_VSM(config->operateVoltage); + + base->SRAMCTL = reg; + + if (config->requestVoltageUpdate) + { + base->SRAMCTL |= SPC_SRAMCTL_REQ_MASK; + while ((base->SRAMCTL & SPC_SRAMCTL_ACK_MASK) == 0UL) + { + /* Wait until acknowledged */ + ; + } + base->SRAMCTL &= ~SPC_SRAMCTL_REQ_MASK; + } +} + +/*! + * brief Configs Bandgap mode in Active mode. + * + * @note To disable bandgap in Active mode: + * 1. Disable all LVD's and HVD's in active mode; + * 2. Disable Glitch detect; + * 3. Configrue LDO's and DCDC to low drive strength in active mode; + * 4. Invoke this function to disable bandgap in active mode; + * otherwise the error status will be reported. + * + * @note Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please + * take care of other system resources. + * + * param base SPC peripheral base address. + * param mode The Bandgap mode be selected. + * + * retval kStatus_SPC_BandgapModeWrong The Bandgap can not be disabled in active mode. + * retval kStatus_Success Config Bandgap mode in Active power mode successful. + */ +status_t SPC_SetActiveModeBandgapModeConfig(SPC_Type *base, spc_bandgap_mode_t mode) +{ + uint32_t reg; + uint32_t state; + + reg = base->ACTIVE_CFG; + + if (mode == kSPC_BandgapDisabled) + { + state = SPC_GetActiveModeVoltageDetectStatus(base); + + /* If any of the LVD/HVDs are kept enabled, bandgap mode must be enabled with buffer disabled. */ + if (state != 0UL) + { + return kStatus_SPC_BandgapModeWrong; + } + + /* The bandgap mode must be enabled if any regulators' drive strength set as Normal. */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) == + SPC_ACTIVE_CFG_SYSLDO_VDD_DS(kSPC_SysLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK) == SPC_ACTIVE_CFG_DCDC_VDD_DS(kSPC_DCDC_NormalVoltage)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) + /* state of GLITCH_DETECT_DISABLE will be ignored if bandgap is disabled. */ + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) == + SPC_ACTIVE_CFG_CORELDO_VDD_DS(kSPC_CoreLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + } + + reg &= ~SPC_ACTIVE_CFG_BGMODE_MASK; + reg |= SPC_ACTIVE_CFG_BGMODE(mode); + + base->ACTIVE_CFG = reg; + + return kStatus_Success; +} + +/*! + * brief Configs Bandgap mode in Low Power mode. + * + * @note To disable Bandgap in Low-power mode: + * 1. Disable all LVD's ad HVD's in low power mode; + * 2. Disable Glitch detect in low power mode; + * 3. Configure LDO's and DCDC to low drive strength in low power mode; + * 4. Disable bandgap in low power mode; + * Otherwise, the error status will be reported. + * + * @note Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please + * take care of other system resources. + * + * param base SPC peripheral base address. + * param mode The Bandgap mode be selected. + * + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. + * retval kStatus_Success Config Bandgap mode in Low Power power mode successful. + */ +status_t SPC_SetLowPowerModeBandgapmodeConfig(SPC_Type *base, spc_bandgap_mode_t mode) +{ + uint32_t reg; + uint32_t state; + + reg = base->LP_CFG; + + if (mode == kSPC_BandgapDisabled) + { + state = (uint32_t)SPC_GetLowPowerModeVoltageDetectStatus(base); + + /* If any of the LVD/HVDs are kept enabled, bandgap mode must be enabled with buffer disabled. */ + if (state != 0UL) + { + return kStatus_SPC_BandgapModeWrong; + } + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + if ((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_DS_MASK) == SPC_LP_CFG_DCDC_VDD_DS(kSPC_DCDC_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + if ((base->LP_CFG & SPC_LP_CFG_SYSLDO_VDD_DS_MASK) == SPC_LP_CFG_SYSLDO_VDD_DS(kSPC_SysLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + + if ((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_DS_MASK) == + SPC_LP_CFG_CORELDO_VDD_DS(kSPC_CoreLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) + /* state of GLITCH_DETECT_DISABLE will be ignored if bandgap is disabled. */ + if ((base->LP_CFG & SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL) + { + return kStatus_SPC_BandgapModeWrong; + } +#endif + } + + reg &= ~SPC_LP_CFG_BGMODE_MASK; + reg |= SPC_LP_CFG_BGMODE(mode); + base->LP_CFG = reg; + + return kStatus_Success; +} + +/*! + * brief Configs CORE voltage detect options. + * + * This function configs CORE voltage detect options. + * Note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset only one is enabled. + * + * param base SPC peripheral base address. + * param config Pointer to spc_core_voltage_detect_config_t structure. + */ +void SPC_SetCoreVoltageDetectConfig(SPC_Type *base, const spc_core_voltage_detect_config_t *config) +{ + assert(config != NULL); + + uint32_t reg = 0UL; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) + reg |= (config->option.HVDInterruptEnable) ? SPC_VD_CORE_CFG_HVDIE(1U) : SPC_VD_CORE_CFG_HVDIE(0U); + reg |= (config->option.HVDResetEnable) ? SPC_VD_CORE_CFG_HVDRE(1U) : SPC_VD_CORE_CFG_HVDRE(0U); +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + reg |= (config->option.LVDInterruptEnable) ? SPC_VD_CORE_CFG_LVDIE(1U) : SPC_VD_CORE_CFG_LVDIE(0U); + reg |= (config->option.LVDResetEnable) ? SPC_VD_CORE_CFG_LVDRE(1U) : SPC_VD_CORE_CFG_LVDRE(0U); + + base->VD_CORE_CFG = reg; +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) +/*! + * brief Enables the Core High Voltage Detector in Active mode. + * + * note If the CORE_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low. + * + * param base SPC peripheral base address. + * param enable Enable/Disable Core HVD. + * true - Enable Core High voltage detector in active mode. + * false - Disable Core High voltage detector in active mode. + * + * retval kStatus_Success Enable Core High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeCoreHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_CORE_HVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORE_HVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the Core High Voltage Detector in Low Power mode. + * + * note If the CORE_LDO high voltage detect is enabled in Low Power mode, + * please note that the bandgap must be enabled and the drive strength of each regulator + * must not set to low in low power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable Core HVD. + * true - Enable Core High voltage detector in low power mode. + * false - Disable Core High voltage detector in low power mode. + * + * retval kStatus_Success Enable Core High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeCoreHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_CORE_HVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_CORE_HVDE_MASK; + } + + return status; +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + +/*! + * brief Enables the Core VDD Low Voltage Detector in Active mode. + * + * note If the Core VDD high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low. + * + * param base SPC peripheral base address. + * param enable Enable/Disable Core LVD. + * true - Enable Core Low voltage detector in active mode. + * false - Disable Core Low voltage detector in active mode. + * + * retval kStatus_Success Enable Core Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeCoreLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_CORE_LVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORE_LVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the Core Low Voltage Detector in Low Power mode. + * + * note If the Core VDD low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable Core HVD. + * true - Enable Core Low voltage detector in low power mode. + * false - Disable Core Low voltage detector in low power mode. + * + * retval kStatus_Success Enable Core Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeCoreLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_CORE_LVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_CORE_LVDE_MASK; + } + + return status; +} + +/*! + * brief Set system VDD Low-voltage level selection. + * + * This function selects the system VDD low-voltage level. Changing system VDD low-voltage level + * must be done after disabling the System VDD low voltage reset and interrupt. + * + * @deprecated In latest RM, reserved for all devices, will removed in next release. + * + * param base SPC peripheral base address. + * param level System VDD Low-Voltage level selection. See @ref spc_low_voltage_level_select_t for details. + */ +void SPC_SetSystemVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level) +{ + (void)level; + (void)base; + + /* + uint32_t reg; + + reg = base->VD_SYS_CFG; + + base->VD_SYS_CFG &= ~(SPC_VD_SYS_CFG_LVDRE_MASK | SPC_VD_SYS_CFG_LVDIE_MASK); + reg |= SPC_VD_SYS_CFG_LVSEL(level); + + base->VD_SYS_CFG = reg; */ +} + +/*! + * brief Configs SYS VDD voltage detect options. + * + * This function config SYS voltage detect options. + * Note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset only one is enabled. + * + * param base SPC peripheral base address. + * param config Pointer to spc_system_voltage_detect_config_t structure. + */ +void SPC_SetSystemVoltageDetectConfig(SPC_Type *base, const spc_system_voltage_detect_config_t *config) +{ + assert(config != NULL); + + uint32_t reg = 0UL; + + reg |= (config->option.HVDInterruptEnable) ? SPC_VD_SYS_CFG_HVDIE(1U) : SPC_VD_SYS_CFG_HVDIE(0U); + reg |= (config->option.LVDInterruptEnable) ? SPC_VD_SYS_CFG_LVDIE(1U) : SPC_VD_SYS_CFG_LVDIE(0U); + reg |= (config->option.HVDResetEnable) ? SPC_VD_SYS_CFG_HVDRE(1U) : SPC_VD_SYS_CFG_HVDRE(0U); + reg |= (config->option.LVDResetEnable) ? SPC_VD_SYS_CFG_LVDRE(1U) : SPC_VD_SYS_CFG_LVDRE(0U); + + base->VD_SYS_CFG = reg; + + (void)(config->level); + /* SPC_SetSystemVDDLowVoltageLevel(base, config->level); */ +} + +/*! + * brief Enables the System VDD High Voltage Detector in Active mode. + * + * note If the System_LDO high voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength of + * each regulator must not set to low in Active mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable System HVD. + * true - Enable System High voltage detector in active mode. + * false - Disable System High voltage detector in active mode. + * + * retval kStatus_Success Enable System High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeSystemHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_SYS_HVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_SYS_HVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the System VDD Low Voltage Detector in Active mode. + * + * note If the System_LDO low voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in Active mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable System LVD. + * true - Enable System Low voltage detector in active mode. + * false - Disable System Low voltage detector in active mode. + * + * retval kStatus_Success Enable the System Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeSystemLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_SYS_LVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_SYS_LVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the System VDD High Voltage Detector in Low Power mode. + * + * note If the System_LDO high voltage detect is enabled in low power mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in low power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable System HVD. + * true - Enable System High voltage detector in low power mode. + * false - Disable System High voltage detector in low power mode. + * + * retval kStatus_Success Enable System High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeSystemHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_SYS_HVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_SYS_HVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the System VDD Low Voltage Detector in Low Power mode. + * + * note If the System_LDO low voltage detect is enabled in Low Power mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in Low Power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable System HVD. + * true - Enable System Low voltage detector in low power mode. + * false - Disable System Low voltage detector in low power mode. + * + * retval kStatus_Success Enable System Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeSystemLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_SYS_LVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_SYS_LVDE_MASK; + } + + return status; +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) +/*! + * brief Set IO VDD Low-Voltage level selection. + * + * This function selects the IO VDD Low-voltage level. Changing IO VDD low-voltage level + * must be done after disabling the IO VDD low voltage reset and interrupt. + * + * param base SPC peripheral base address. + * param level IO VDD Low-voltage level selection. + */ +void SPC_SetIOVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level) +{ + uint32_t reg; + + reg = base->VD_IO_CFG; + + base->VD_IO_CFG &= ~(SPC_VD_IO_CFG_LVDRE_MASK | SPC_VD_IO_CFG_LVDIE_MASK | SPC_VD_IO_CFG_LVSEL_MASK); + reg |= SPC_VD_IO_CFG_LVSEL(level); + + base->VD_IO_CFG = reg; +} + +/*! + * brief Configs IO VDD voltage detect options. + * + * This function config IO voltage detect options. + * Note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset so only one is enabled. + * + * param base SPC peripheral base address. + * param config Pointer to spc_IO_voltage_detect_config_t structure. + */ +void SPC_SetIOVoltageDetectConfig(SPC_Type *base, const spc_io_voltage_detect_config_t *config) +{ + assert(config != NULL); + + uint32_t reg = 0UL; + + /* Set trip voltage level. */ + SPC_SetIOVDDLowVoltageLevel(base, config->level); + + reg = base->VD_IO_CFG; + reg &= ~(SPC_VD_IO_CFG_LVDRE_MASK | SPC_VD_IO_CFG_LVDIE_MASK | SPC_VD_IO_CFG_HVDRE_MASK | SPC_VD_IO_CFG_HVDIE_MASK); + + reg |= (config->option.HVDInterruptEnable) ? SPC_VD_IO_CFG_HVDIE(1U) : SPC_VD_IO_CFG_HVDIE(0U); + reg |= (config->option.LVDInterruptEnable) ? SPC_VD_IO_CFG_LVDIE(1U) : SPC_VD_IO_CFG_LVDIE(0U); + reg |= (config->option.HVDResetEnable) ? SPC_VD_IO_CFG_HVDRE(1U) : SPC_VD_IO_CFG_HVDRE(0U); + reg |= (config->option.LVDResetEnable) ? SPC_VD_IO_CFG_LVDRE(1U) : SPC_VD_IO_CFG_LVDRE(0U); + + base->VD_IO_CFG = reg; +} + +/*! + * brief Enables the IO VDD High Voltage Detector in Active mode. + * + * note If the IO high voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength + * of each regulator must not set to low in Active mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable IO HVD. + * true - Enable IO High voltage detector in active mode. + * false - Disable IO High voltage detector in active mode. + * + * retval kStatus_Success Enable IO High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeIOHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_IO_HVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_IO_HVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the IO VDD Low Voltage Detector in Active mode. + * + * note If the IO low voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength + * of each regulator must not set to low in Active mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable IO LVD. + * true - Enable IO Low voltage detector in active mode. + * false - Disable IO Low voltage detector in active mode. + * + * retval kStatus_Success Enable IO Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeIOLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_IO_LVDE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_IO_LVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the IO VDD High Voltage Detector in Low Power mode. + * + * note If the IO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable IO HVD. + * true - Enable IO High voltage detector in low power mode. + * false - Disable IO High voltage detector in low power mode. + * + * retval kStatus_Success Enable IO High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeIOHighVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_IO_HVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_IO_HVDE_MASK; + } + + return status; +} + +/*! + * brief Enables the IO VDD Low Voltage Detector in Low Power mode. + * + * note If the IO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * param base SPC peripheral base address. + * param enable Enable/Disable IO HVD. + * true - Enable IO Low voltage detector in low power mode. + * false - Disable IO Low voltage detector in low power mode. + * + * retval kStatus_Success Enable IO Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeIOLowVoltageDetect(SPC_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_IO_LVDE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_IO_LVDE_MASK; + } + + return status; +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + +/*! + * brief Configs external voltage domains + * + * This function configs external voltage domains isolation. + * + * param base SPC peripheral base address. + * param lowPowerIsoMask The mask of external domains isolate enable during low power mode. + * param IsoMask The mask of external domains isolate. + */ +void SPC_SetExternalVoltageDomainsConfig(SPC_Type *base, uint8_t lowPowerIsoMask, uint8_t IsoMask) +{ + uint32_t reg = 0UL; + + reg |= SPC_EVD_CFG_REG_EVDISO(IsoMask) | SPC_EVD_CFG_REG_EVDLPISO(lowPowerIsoMask); + base->EVD_CFG = reg; +} + +/*! + * brief Configs Core LDO Regulator in Active mode. + * + * @note The bandgap must be enabled before invoking this function. + * @note To set Core LDO as low drive strength, all HVDs/LVDs must be disabled previously. + * + * param base SPC peripheral base address. + * param option Pointer to the spc_active_mode_Core_LDO_option_t structure. + * + * retval kStatus_Success Config Core LDO regulator in Active power mode successful. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong Bandgap should be enabled before invoking this function. + * retval kStatus_SPC_CORELDOLowDriveStrengthIgnore To set Core LDO as low drive strength, + * all LVDs/HVDs must be disabled before invoking this function. + */ +status_t SPC_SetActiveModeCoreLDORegulatorConfig(SPC_Type *base, const spc_active_mode_core_ldo_option_t *option) +{ + assert(option != NULL); + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + return kStatus_SPC_Busy; + } + + /* Check input parameters. */ + /* 1. Bandgap must not be disabled. */ + if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + + /* 2. To set to low drive strength, all LVDs/HVDs must be disabled previously. */ + if ((SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) && + (option->CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength)) + { + return kStatus_SPC_CORELDOLowDriveStrengthIgnore; + } + + if ((uint8_t)SPC_GetActiveModeCoreLDOVDDVoltageLevel(base) != (uint8_t)(option->CoreLDOVoltage)) + { +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS + (void)SPC_SetActiveModeCoreLDORegulatorDriveStrength(base, kSPC_CoreLDO_NormalDriveStrength); +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + (void)SPC_SetActiveModeCoreLDORegulatorVoltageLevel(base, option->CoreLDOVoltage); + } + +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS + (void)SPC_SetActiveModeCoreLDORegulatorDriveStrength(base, option->CoreLDODriveStrength); +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + + return kStatus_Success; +} + +/*! + * brief Set Core LDO VDD Regulator Voltage level in Active mode. + * + * @note In active mode, the Core LDO voltage level should only be changed when the + * Core LDO is in normal drive strength. + * + * @note Update Core LDO voltage level will set Busy flag, + * this function return only when busy flag is cleared by hardware + * + * param base SPC peripheral base address. + * param voltageLevel Specify the voltage level of CORE LDO Regulator in Active mode, please + refer to @ref spc_core_ldo_voltage_level_t. + * + * retval kStatus_SPC_CORELDOVoltageSetFail Core LDO voltage level should only be + * changed when the CORE_LDO is in normal drive strength. + * retval kStatus_Success Set Core LDO regulator voltage level in Active power mode successful. + */ +status_t SPC_SetActiveModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel) +{ + if ((uint8_t)voltageLevel != (uint8_t)SPC_GetActiveModeCoreLDOVDDVoltageLevel(base)) + { +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) + if (SPC_GetActiveModeCoreLDODriveStrength(base) != kSPC_CoreLDO_NormalDriveStrength) + { + return kStatus_SPC_CORELDOVoltageSetFail; + } +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + + base->ACTIVE_CFG = + ((base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(voltageLevel)); + + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + } + return kStatus_Success; +} + +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS +/*! + * brief Set Core LDO VDD Regulator Drive Strength in Active mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the drive strength of CORE LDO Regulator in Active mode, please + refer to @ref spc_core_ldo_drive_strength_t. + * + * retval #kStatus_Success Set Core LDO regulator drive strength in Active power mode successful. + * retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore If any voltage detect enabled, + core_ldo's drive strength can not set to low. + * retval #kStatus_SPC_BandgapModeWrong The selected bandgap mode is not allowed. + */ +status_t SPC_SetActiveModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_CoreLDO_LowDriveStrength) + { + /* If any voltage detect feature is enabled in Active mode, then CORE_LDO's drive strength must not set to low. + */ + if (SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_CORELDOLowDriveStrengthIgnore; + } + } + + if (driveStrength == kSPC_CoreLDO_NormalDriveStrength) + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->ACTIVE_CFG = + ((base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) | SPC_ACTIVE_CFG_CORELDO_VDD_DS(driveStrength)); + + return kStatus_Success; +} +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + +/*! + * brief Configs CORE LDO Regulator in low power mode + * + * This function configs CORE LDO Regulator in Low Power mode. + * If CORE LDO VDD Drive Strength is set to Normal, the CORE LDO VDD regulator voltage + * level in Active mode must be equal to the voltage level in Low power mode. And the Bandgap + * must be programmed to select bandgap enabled. + * Core VDD voltage levels for the Core LDO low power regulator can only be changed when the CORE + * LDO Drive Strength is set as Normal. + * + * param base SPC peripheral base address. + * param option Pointer to the spc_lowpower_mode_Core_LDO_option_t structure. + * retval kStatus_Success Config Core LDO regulator in power mode successfully. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_CORELDOLowDriveStrengthIgnore HVDs/LVDs are not disabled before invoking this function. + * retval kStatus_SPC_BandgapModeWrong The bandgap is not enabled before invoking this function. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_core_ldo_option_t *option) +{ + status_t status = kStatus_Success; + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + status = SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(base, option->CoreLDODriveStrength); + if (status == kStatus_Success) + { + (void)SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(base, option->CoreLDOVoltage); + } + + return status; +} + +/*! + * brief Set Core LDO VDD Regulator Voltage level in Low power mode. + * + * @note If Core LDO's drive strengths are same in active and low power mode, the Core LDO's voltage must be set to the + * same value in active and low power mode. Application should take care of this limitation. + * + * @note Some devices require Core LDO and DCDC have the same voltage level even if Core LDO is off. Application should + * take care of this limitation. + * + * param base SPC peripheral base address. + * param voltageLevel Voltage level of CORE LDO Regulator in Low power mode, please + refer to @ref spc_core_ldo_voltage_level_t. + * + * retval #kStatus_SPC_Busy The SPC instance is busy to execute other operation. + * retval #kStatus_Success Set Core LDO regulator voltage level in Low power mode successful. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel) +{ + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + base->LP_CFG = ((base->LP_CFG & ~SPC_LP_CFG_CORELDO_VDD_LVL_MASK) | SPC_LP_CFG_CORELDO_VDD_LVL(voltageLevel)); + + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + + return kStatus_Success; +} + +/*! + * brief Set Core LDO VDD Regulator Drive Strength in Low power mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify drive strength of CORE LDO in low power mode. + * + * retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Some voltage detect enabled, CORE LDO's drive strength can not set + * as low. + * retval #kStatus_Success Set Core LDO regulator drive strength in Low power mode successful. + * retval #kStatus_SPC_BandgapModeWrong Bandgap is disabled when attempt to set CORE LDO work as normal drive strength. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_CoreLDO_LowDriveStrength) + { + /* If any voltage detect feature is enabled in Low Power mode, then CORE_LDO's drive strength must not set to + * low. + */ + if (SPC_GetLowPowerModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_CORELDOLowDriveStrengthIgnore; + } + } + else + { + /* To specify normal drive strength, the bandgap must be enabled in low power mode. */ + if (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->LP_CFG = ((base->LP_CFG & ~SPC_LP_CFG_CORELDO_VDD_DS_MASK) | SPC_LP_CFG_CORELDO_VDD_DS(driveStrength)); + + return kStatus_Success; +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * brief Configs System LDO VDD Regulator in Active mode. + * + * This function configs System LDO VDD Regulator in Active mode. + * If System LDO VDD Drive Strength is set to Normal, the Bandgap mode in Active mode must be programmed + * to a value that enable the bandgap. + * If any voltage detects are kept enabled, configuration to set System LDO VDD drive strength to low will + * be ignored. + * If select System LDO VDD Regulator voltage level to Over Drive Voltage, the Drive Strength of System LDO VDD + * Regulator must be set to Normal otherwise the regulator Drive Strength will be forced to Normal. + * If select System LDO VDD Regulator voltage level to Over Drive Voltage, the High voltage detect must be disabled. + * Otherwise it will be fail to regulator to Over Drive Voltage. + * + * param base SPC peripheral base address. + * param option Pointer to the spc_active_mode_Sys_LDO_option_t structure. + * retval kStatus_Success Config System LDO regulator in Active power mode successful. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong The bandgap is not enabled before invoking this function. + * retval kStatus_SPC_SYSLDOOverDriveVoltageFail HVD of System VDD is not disable before setting to Over Drive voltage. + * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set System LDO VDD regulator's driver strength to Low will be + * ignored. + */ +status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_active_mode_sys_ldo_option_t *option) +{ + assert(option != NULL); + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + /* Check input parameters before setting registers. */ + /* 1. To set to low DS, all LVDs/HVDs must be disabled previously. */ + if ((SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) && + (option->SysLDODriveStrength == kSPC_SysLDO_LowDriveStrength)) + { + return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; + } + /* 2. If specify normal drive strength, bandgap must not be disabled. */ + if ((SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) && + (option->SysLDODriveStrength == kSPC_SysLDO_NormalDriveStrength)) + { + return kStatus_SPC_BandgapModeWrong; + } + + /* 3. Must disable system LDO high voltage detector before specifing overdrive voltage. */ + if ((option->SysLDOVoltage == kSPC_SysLDO_OverDriveVoltage) && + ((SPC_GetActiveModeVoltageDetectStatus(base) & SPC_ACTIVE_CFG_SYS_HVDE_MASK) != 0UL)) + { + return kStatus_SPC_SYSLDOOverDriveVoltageFail; + } + + (void)SPC_SetActiveModeSystemLDORegulatorDriveStrength(base, option->SysLDODriveStrength); + (void)SPC_SetActiveModeSystemLDORegulatorVoltageLevel(base, option->SysLDOVoltage); + + return kStatus_Success; +} + +/*! + * brief Set System LDO Regulator voltage level in Active mode. + * + * @note The system LDO regulator can only operate at the overdrive voltage level for a limited amount of time for the + * life of chip. + * + * param base SPC peripheral base address. + * param voltageLevel Specify the voltage level of System LDO Regulator in Active mode. + * + * retval #kStatus_Success Set System LDO Regulator voltage level in Active mode successfully. + * retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Must disable system LDO high voltage detector before specifing + * overdrive voltage. + */ +status_t SPC_SetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base, spc_sys_ldo_voltage_level_t voltageLevel) +{ + if (voltageLevel == kSPC_SysLDO_OverDriveVoltage) + { + /* Must disable system LDO high voltage detector before specifing overdrive voltage. */ + if ((SPC_GetActiveModeVoltageDetectStatus(base) & SPC_ACTIVE_CFG_SYS_HVDE_MASK) != 0UL) + { + return kStatus_SPC_SYSLDOOverDriveVoltageFail; + } + } + + base->ACTIVE_CFG = + (base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK) | SPC_ACTIVE_CFG_SYSLDO_VDD_LVL(voltageLevel); + + return kStatus_Success; +} + +/*! + * brief Set System LDO Regulator Drive Strength in Active mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the drive strength of System LDO Regulator in Active mode. + * + * retval #kStatus_Success Set System LDO Regulator drive strength in Active mode successfully. + * retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any + voltage detect feature is enabled in active mode. + * retval #kStatus_SPC_BandgapModeWrong Bandgap mode in Active mode must be programmed to a value that enables + the bandgap if attempt to specify normal drive strength. + */ +status_t SPC_SetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_SysLDO_LowDriveStrength) + { + /* If enabled any LVDs or HVDs, SPC will ignore the attempt to specify low drive strength. */ + if (SPC_GetActiveModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; + } + } + + if (driveStrength == kSPC_SysLDO_NormalDriveStrength) + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->ACTIVE_CFG = + (base->ACTIVE_CFG & ~SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) | SPC_ACTIVE_CFG_SYSLDO_VDD_DS(driveStrength); + + return kStatus_Success; +} + +/*! + * brief Configs System LDO regulator in low power modes. + * + * This function configs System LDO regulator in low power modes. + * If System LDO VDD Regulator Drive strength is set to normal, bandgap mode in low power + * mode must be programmed to a value that enables the Bandgap. + * If any High voltage detectors or Low Voltage detectors are kept enabled, configuration + * to set System LDO Regulator drive strength as Low will be ignored. + * + * param base SPC peripheral base address. + * param option Pointer to spc_lowpower_mode_Sys_LDO_option_t structure. + * + * retval kStatus_Success Config System LDO regulator in Low Power Mode successfully. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power Mode is wrong. + * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + */ +status_t SPC_SetLowPowerModeSystemLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_sys_ldo_option_t *option) +{ + status_t status; + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + status = SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(base, option->SysLDODriveStrength); + + return status; +} + +/*! + * brief Set System LDO Regulator drive strength in Low Power Mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the drive strength of System LDO Regulator in Low Power Mode. + * + * retval #kStatus_Success Set System LDO Regulator drive strength in Low Power Mode successfully. + * retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any + voltage detect feature is enabled in low power mode. + * retval #kStatus_SPC_BandgapModeWrong Bandgap mode in low power mode must be programmed to a value that enables + the bandgap if attempt to specify normal drive strength. + */ +status_t SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_SysLDO_LowDriveStrength) + { + /* If enabled any LVDs or HVDs, SPC will ignore the attempt to specify low drive strength. */ + if (SPC_GetLowPowerModeVoltageDetectStatus(base) != 0UL) + { + return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; + } + } + else + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->LP_CFG = (base->LP_CFG & ~SPC_LP_CFG_SYSLDO_VDD_DS_MASK) | SPC_LP_CFG_SYSLDO_VDD_DS(driveStrength); + + return kStatus_Success; +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * brief Configs DCDC VDD Regulator in Active mode. + * + * note When changing the DCDC output voltage level, take care to change the CORE LDO voltage level. + * + * param base SPC peripheral base address. + * param option Pointer to the spc_active_mode_DCDC_option_t structure. + * + * retval kStatus_Success Config DCDC regulator in Active power mode successful. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Active mode is wrong. + */ +status_t SPC_SetActiveModeDCDCRegulatorConfig(SPC_Type *base, const spc_active_mode_dcdc_option_t *option) +{ + assert(option != NULL); + status_t status = kStatus_Success; + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + status = SPC_SetActiveModeDCDCRegulatorDriveStrength(base, option->DCDCDriveStrength); + + if (status == kStatus_Success) + { + SPC_SetActiveModeDCDCRegulatorVoltageLevel(base, option->DCDCVoltage); + } + + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + + return status; +} + +/*! + * brief Set DCDC VDD Regulator drive strength in Active mode. + * + * note To set DCDC drive strength as Normal, the bandgap must be enabled. + * + * param base SPC peripheral base address. + * param driveStrength Specify the DCDC VDD regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + * + * retval #kStatus_Success Set DCDC VDD Regulator drive strength in Active mode successfully. + * retval #kStatus_SPC_BandgapModeWrong Set DCDC VDD Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_DCDC_NormalDriveStrength) + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetActiveModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->ACTIVE_CFG = + ((base->ACTIVE_CFG) & (~SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK)) | SPC_ACTIVE_CFG_DCDC_VDD_DS(driveStrength); + + return kStatus_Success; +} + +/*! + * brief Configs DCDC VDD Regulator in Low power modes. + * + * If DCDC VDD Drive Strength is set to Normal, the Bandgap mode in Low Power mode must be programmed + * to a value that enables the Bandgap. + * In Deep Power Down mode, DCDC regulator is always turned off. + * + * param base SPC peripheral base address. + * param option Pointer to the spc_lowpower_mode_DCDC_option_t structure. + * + * retval kStatus_Success Config DCDC regulator in low power mode successfully. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_BandgapModeWrong The bandgap should be enabled before invoking this function. + */ +status_t SPC_SetLowPowerModeDCDCRegulatorConfig(SPC_Type *base, const spc_lowpower_mode_dcdc_option_t *option) +{ + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + /* + * $Line Coverage Justification$ + * $ref spc_c_ref_1$. + */ + return kStatus_SPC_Busy; + } + + /* Check input parameter before setting registers. */ + if ((option->DCDCDriveStrength == kSPC_DCDC_NormalDriveStrength) && + (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled)) + { + return kStatus_SPC_BandgapModeWrong; + } + + /* + 1. Configure to desired voltage level. + 2. Change to low drive strength. + 3. Configure same voltage level in active mode. + */ + SPC_SetLowPowerModeDCDCRegulatorVoltageLevel(base, option->DCDCVoltage); + + /* Change to desired drive strength. */ + if (option->DCDCDriveStrength != kSPC_DCDC_LowDriveStrength) + { + (void)SPC_SetLowPowerModeDCDCRegulatorDriveStrength(base, option->DCDCDriveStrength); + } + + /* + * $Branch Coverage Justification$ + * $ref spc_c_ref_1$. + */ + while ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + } + + return kStatus_Success; +} + +/*! + * brief Set DCDC VDD Regulator drive strength in Low power mode. + * + * param base SPC peripheral base address. + * param driveStrength Specify the DCDC VDD Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + * + * retval #kStatus_Success Set DCDC VDD Regulator drive strength in Low power mode successfully. + * retval #kStatus_SPC_BandgapModeWrong Set DCDC VDD Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength) +{ + if (driveStrength == kSPC_DCDC_NormalDriveStrength) + { + /* If specify normal drive strength, bandgap must not be disabled. */ + if (SPC_GetLowPowerModeBandgapMode(base) == kSPC_BandgapDisabled) + { + return kStatus_SPC_BandgapModeWrong; + } + } + + base->LP_CFG = ((base->LP_CFG) & (~SPC_LP_CFG_DCDC_VDD_DS_MASK)) | SPC_LP_CFG_DCDC_VDD_DS(driveStrength); + + return kStatus_Success; +} + +/*! + * brief Config DCDC Burst options + * + * param base SPC peripheral base address. + * param config Pointer to spc_DCDC_burst_config_t structure. + */ +void SPC_SetDCDCBurstConfig(SPC_Type *base, spc_dcdc_burst_config_t *config) +{ + assert(config != NULL); + uint32_t reg; + reg = base->DCDC_CFG; + reg &= ~(SPC_DCDC_CFG_FREQ_CNTRL_MASK | SPC_DCDC_CFG_FREQ_CNTRL_ON_MASK); + reg |= SPC_DCDC_CFG_FREQ_CNTRL(config->freq); + reg |= config->stabilizeBurstFreq ? SPC_DCDC_CFG_FREQ_CNTRL_ON(1U) : SPC_DCDC_CFG_FREQ_CNTRL_ON(0U); + base->DCDC_CFG = reg; + + /* Blocking until previous DCDC burst completed. */ + while ((base->DCDC_BURST_CFG & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) == 0UL) + { + } + + if ((config->sofwareBurstRequest) || (config->externalBurstRequest)) + { + /* Clear DCDC burst acknowledge flag. */ + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_ACK_MASK; + } + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_EXT_BURST_EN(config->externalBurstRequest); + + if (config->sofwareBurstRequest) + { + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_REQ_MASK; + } +} + +/*! + * brief Set the count value of the reference clock. + * + * This function set the count value of the reference clock to control the frequency + * of dcdc refresh when dcdc is configured in Pulse Refresh mode. + * + * param base SPC peripheral base address. + * param count The count value, 16 bit width. + */ +void SPC_SetDCDCRefreshCount(SPC_Type *base, uint16_t count) +{ + uint32_t reg; + + reg = base->DCDC_BURST_CFG; + reg &= ~SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT_MASK; + reg |= SPC_DCDC_BURST_CFG_PULSE_REFRESH_CNT(count); + + base->DCDC_BURST_CFG = reg; +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +/*! + * brief Configs all settings of regulators in Active mode at a time. + * + * @note This function is used to overwrite all settings of regulators(including bandgap mode, regulators' + * drive strength and voltage level) in active mode at a time. + * + * @note Enable/disable LVDs/HVDs before invoking this function. + * + * @note This function will check input parameters based on hardware restrictions before setting registers, if input + * parameters do not satisfy hardware restrictions the specific error will be reported. + * + * + * @note Some hardware restrictions not covered, application should be aware of this and follow this hardware + * restrictions otherwise some unkown issue may occur: + * 1. If Core LDO's drive strength are set to same value in both Active mode and low power mode, + * the voltage level should also set to same value. + * 2. When switching Core LDO's drive strength from low to normal, ensure the LDO_CORE high voltage level is set + * to same level that was set prior to switching to the LDO_CORE drive strength. Otherwise, if the LVDs are + * enabled, an unexpected LVD can occur. + * + * @note If this function can not satisfy some tricky settings, please invoke other low-level functions. + * + * param base SPC peripheral base address. + * param config Pointer to spc_active_mode_regulators_config_t structure. + * retval kStatus_Success Config regulators in Active power mode successful. + * retval kStatus_SPC_BandgapModeWrong The bandgap mode setting in Active mode is wrong. + * retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * retval kStatus_SPC_CORELDOVoltageWrong The selected voltage level in active mode is not allowed. + * retval kStatus_SPC_SYSLDOOverDriveVoltageFail Fail to regulator to Over Drive Voltage. + * retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to Low will be ignored. + * retval kStatus_SPC_DCDCLowDriveStrengthIgnore Set driver strength to Low will be ignored. + */ +status_t SPC_SetActiveModeRegulatorsConfig(SPC_Type *base, const spc_active_mode_regulators_config_t *config) +{ + assert(config != NULL); + + uint32_t activeModeVDValue = SPC_GetActiveModeVoltageDetectStatus(base); + + /* Check input parameters */ + /* 1. Bandgap should not be disabled if any of regulator in normal drive strength or + if any of LVDs/HVDs are enabled or if VDD CORE glitch detect are enabled. */ + if ((config->bandgapMode == kSPC_BandgapDisabled) && + ((activeModeVDValue != 0UL) +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) + || (SPC_CheckActiveModeVddCoreGlitchDetectEnabled(base) == true) +#endif /* FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + || (config->DCDCOption.DCDCDriveStrength == kSPC_DCDC_NormalDriveStrength) +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + || (config->SysLDOOption.SysLDODriveStrength == kSPC_SysLDO_NormalDriveStrength) +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) + || (config->CoreLDOOption.CoreLDODriveStrength == kSPC_CoreLDO_NormalDriveStrength) +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + )) + { + return kStatus_SPC_BandgapModeWrong; + } + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + /* 2. Must disable system LDO high voltage detector before specifing SysLDO to overdrive voltage */ + if (((activeModeVDValue & SPC_ACTIVE_CFG_SYS_HVDE_MASK) != 0UL) && + (config->SysLDOOption.SysLDOVoltage == kSPC_SysLDO_OverDriveVoltage)) + { + return kStatus_SPC_SYSLDOOverDriveVoltageFail; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + /* 3. To set System LDO's drive strength to low, all LVDs and HVDs must be disabled. */ + if ((activeModeVDValue != 0UL) && (config->SysLDOOption.SysLDODriveStrength == kSPC_SysLDO_LowDriveStrength)) + { + return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) + /* 4. To set Core LDO's drive strength to low, all LVDs and HVDs must be disabled. */ + if ((activeModeVDValue != 0UL) && (config->CoreLDOOption.CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength)) + { + return kStatus_SPC_CORELDOLowDriveStrengthIgnore; + } +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + /* 5. Core LDO and DCDC should have same voltage level. */ + if ((uint8_t)config->DCDCOption.DCDCVoltage != (uint8_t)config->CoreLDOOption.CoreLDOVoltage) + { + return kStatus_SPC_CORELDOVoltageWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + + if ((base->SC & SPC_SC_BUSY_MASK) != 0UL) + { + return kStatus_SPC_Busy; + } + + base->ACTIVE_CFG = + ((base->ACTIVE_CFG) & ~(SPC_ACTIVE_CFG_BGMODE_MASK)) | SPC_ACTIVE_CFG_BGMODE(config->bandgapMode); +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) + SPC_EnableActiveModeCMPBandgapBuffer(base, config->lpBuff); +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + (void)SPC_SetActiveModeSystemLDORegulatorConfig(base, &config->SysLDOOption); +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + (void)SPC_SetActiveModeDCDCRegulatorConfig(base, &config->DCDCOption); +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + + (void)SPC_SetActiveModeCoreLDORegulatorConfig(base, &config->CoreLDOOption); + + return kStatus_Success; +} + +/*! + * brief Configs regulators in Low Power mode. + * + * This function provides the method to config all on-chip regulators in Low Power mode. + * + * param base SPC peripheral base address. + * param config Pointer to spc_lowpower_mode_regulators_config_t structure. + * retval #kStatus_Success Config regulators in Low power mode successful. + * retval #kStatus_SPC_BandgapModeWrong The bandgap should not be disabled based on input settings. + * retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * retval #kStatus_SPC_CORELDOVoltageWrong Core LDO and System LDO do not have same voltage level. + */ +status_t SPC_SetLowPowerModeRegulatorsConfig(SPC_Type *base, const spc_lowpower_mode_regulators_config_t *config) +{ + assert(config != NULL); + uint32_t lpModeVDValue = SPC_GetLowPowerModeVoltageDetectStatus(base); + + /* Check input parameters */ + /* 1. Bandgap should not be disabled if any of regulator in normal drive strength or + if any of LVDs/HVDs are enabled or if VDD CORE glitch detect are enabled. */ + if ((config->bandgapMode == kSPC_BandgapDisabled) && + ((lpModeVDValue != 0UL) +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) + || (SPC_CheckLowPowerModeVddCoreGlitchDetectEnabled(base) == true) +#endif /* FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + || (config->DCDCOption.DCDCDriveStrength == kSPC_DCDC_NormalDriveStrength) +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + || (config->SysLDOOption.SysLDODriveStrength == kSPC_SysLDO_NormalDriveStrength) +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) + || (config->CoreLDOOption.CoreLDODriveStrength == kSPC_CoreLDO_NormalDriveStrength) +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + )) + { + return kStatus_SPC_BandgapModeWrong; + } + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + /* 2. To set System LDO's drive strength to low, all LVDs and HVDs must be disabled. */ + if ((lpModeVDValue != 0UL) && (config->SysLDOOption.SysLDODriveStrength == kSPC_SysLDO_LowDriveStrength)) + { + return kStatus_SPC_SYSLDOLowDriveStrengthIgnore; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) + /* 3. To set Core LDO's drive strength to low, all LVDs and HVDs must be disabled. */ + if ((lpModeVDValue != 0UL) && (config->CoreLDOOption.CoreLDODriveStrength == kSPC_CoreLDO_LowDriveStrength)) + { + return kStatus_SPC_CORELDOLowDriveStrengthIgnore; + } +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + /* 5. Core LDO and DCDC should have same voltage level. */ + if ((uint8_t)config->DCDCOption.DCDCVoltage != (uint8_t)config->CoreLDOOption.CoreLDOVoltage) + { + return kStatus_SPC_CORELDOVoltageWrong; + } +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + base->LP_CFG = ((base->LP_CFG) & ~(SPC_LP_CFG_BGMODE_MASK)) | SPC_LP_CFG_BGMODE(config->bandgapMode); +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) + SPC_EnableLowPowerModeCMPBandgapBuffer(base, config->lpBuff); +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) + SPC_EnableLowPowerModeCoreVDDInternalVoltageScaling(base, config->CoreIVS); +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT */ + SPC_EnableLowPowerModeLowPowerIREF(base, config->lpIREF); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + (void)SPC_SetLowPowerModeSystemLDORegulatorConfig(base, &config->SysLDOOption); +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + (void)SPC_SetLowPowerModeDCDCRegulatorConfig(base, &config->DCDCOption); +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + + (void)SPC_SetLowPowerModeCoreLDORegulatorConfig(base, &config->CoreLDOOption); + + return kStatus_Success; +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_spc.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_spc.h new file mode 100644 index 00000000000..52cb71c24db --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_spc.h @@ -0,0 +1,2433 @@ +/* + * Copyright 2022-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_SPC_H_ +#define FSL_SPC_H_ +#include "fsl_common.h" + +/*! + * @addtogroup mcx_spc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief SPC driver version 2.4.2. */ +#define FSL_SPC_DRIVER_VERSION (MAKE_VERSION(2, 4, 2)) +/*! @} */ + +#define SPC_EVD_CFG_REG_EVDISO_SHIFT 0UL +#define SPC_EVD_CFG_REG_EVDLPISO_SHIFT 8UL +#define SPC_EVD_CFG_REG_EVDSTAT_SHIFT 16UL + +#define SPC_EVD_CFG_REG_EVDISO(x) ((uint32_t)(x) << SPC_EVD_CFG_REG_EVDISO_SHIFT) +#define SPC_EVD_CFG_REG_EVDLPISO(x) ((uint32_t)(x) << SPC_EVD_CFG_REG_EVDLPISO_SHIFT) +#define SPC_EVD_CFG_REG_EVDSTAT(x) ((uint32_t)(x) << SPC_EVD_CFG_REG_EVDSTAT_SHIFT) + +#if (defined(SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK)) +#define VDD_CORE_GLITCH_DETECT_SC GLITCH_DETECT_SC +#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG SPC_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG +#define SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK SPC_GLITCH_DETECT_SC_LOCK_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT_MASK SPC_GLITCH_DETECT_SC_CNT_SELECT_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_CNT_SELECT SPC_GLITCH_DETECT_SC_CNT_SELECT +#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE_MASK SPC_GLITCH_DETECT_SC_RE_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_RE SPC_GLITCH_DETECT_SC_RE +#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT_MASK SPC_GLITCH_DETECT_SC_TIMEOUT_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_TIMEOUT SPC_GLITCH_DETECT_SC_TIMEOUT +#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE_MASK SPC_GLITCH_DETECT_SC_IE_MASK +#define SPC_VDD_CORE_GLITCH_DETECT_SC_IE SPC_GLITCH_DETECT_SC_IE +#endif + +/*! + * @brief SPC status enumeration. + * + * @note Some device(such as MCXA family) do not equip DCDC or System LDO, please refer to the reference manual + * to check. + */ +enum +{ + kStatus_SPC_Busy = MAKE_STATUS(kStatusGroup_SPC, 0U), /*!< The SPC instance is busy executing any + type of power mode transition. */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + kStatus_SPC_DCDCLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 1U), /*!< DCDC Low drive strength setting be + ignored for LVD/HVD enabled. */ + kStatus_SPC_DCDCPulseRefreshModeIgnore = MAKE_STATUS(kStatusGroup_SPC, 2U), /*!< DCDC Pulse Refresh Mode drive + strength setting be ignored for LVD/HVD enabled. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + kStatus_SPC_SYSLDOOverDriveVoltageFail = MAKE_STATUS(kStatusGroup_SPC, 3U), /*!< SYS LDO regulate to Over drive + voltage failed for SYS LDO HVD must be disabled. */ + kStatus_SPC_SYSLDOLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 4U), /*!< SYS LDO Low driver strength + setting be ignored for LDO LVD/HVD enabled. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + kStatus_SPC_CORELDOLowDriveStrengthIgnore = MAKE_STATUS(kStatusGroup_SPC, 5U), /*!< CORE LDO Low driver strength + setting be ignored for LDO LVD/HVD enabled. */ + kStatus_SPC_CORELDOVoltageWrong = MAKE_STATUS(kStatusGroup_SPC, 7U), /*!< Core LDO voltage is wrong. */ + kStatus_SPC_CORELDOVoltageSetFail = MAKE_STATUS(kStatusGroup_SPC, 8U), /*!< Core LDO voltage set fail. */ + kStatus_SPC_BandgapModeWrong = MAKE_STATUS(kStatusGroup_SPC, 6U), /*!< Selected Bandgap Mode wrong. */ +}; + +/*! + * @brief Voltage Detect Status Flags. + */ +enum _spc_voltage_detect_flags +{ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) + kSPC_IOVDDHighVoltageDetectFlag = SPC_VD_STAT_IOVDD_HVDF_MASK, /*!< IO VDD High-Voltage detect flag. */ + kSPC_IOVDDLowVoltageDetectFlag = SPC_VD_STAT_IOVDD_LVDF_MASK, /*!< IO VDD Low-Voltage detect flag. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + kSPC_SystemVDDHighVoltageDetectFlag = SPC_VD_STAT_SYSVDD_HVDF_MASK, /*!< System VDD High-Voltage detect flag. */ + kSPC_SystemVDDLowVoltageDetectFlag = SPC_VD_STAT_SYSVDD_LVDF_MASK, /*!< System VDD Low-Voltage detect flag. */ +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) + kSPC_CoreVDDHighVoltageDetectFlag = SPC_VD_STAT_COREVDD_HVDF_MASK, /*!< Core VDD High-Voltage detect flag. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + kSPC_CoreVDDLowVoltageDetectFlag = SPC_VD_STAT_COREVDD_LVDF_MASK, /*!< Core VDD Low-Voltage detect flag. */ +}; + +/*! + * @brief SPC power domain isolation status. + * @note Some devices(such as MCXA family) do not contain WAKE Power Domain, please refer to the reference manual to + * check. + */ +enum _spc_power_domains +{ + kSPC_MAINPowerDomainRetain = 1UL << 16U, /*!< Peripherals and IO pads retain in MAIN Power Domain. */ + kSPC_WAKEPowerDomainRetain = 1UL << 17U, /*!< Peripherals and IO pads retain in WAKE Power Domain. */ +}; + +/*! + * @brief The enumeration of all analog module that can be controlled by SPC in active or low-power modes. + * @anchor spc_analog_module_control + */ +enum _spc_analog_module_control +{ + kSPC_controlVref = 1UL << 0UL, /*!< Enable/disable VREF in active or low-power modes. */ + kSPC_controlUsb3vDet = 1UL << 1UL, /*!< Enable/disable USB3V_Det in active or low-power modes. */ + kSPC_controlDac0 = 1UL << 4UL, /*!< Enable/disable DAC0 in active or low-power modes. */ + kSPC_controlDac1 = 1UL << 5UL, /*!< Enable/disable DAC1 in active or low-power modes. */ + kSPC_controlDac2 = 1UL << 6UL, /*!< Enable/disable DAC2 in active or low-power modes. */ + kSPC_controlOpamp0 = 1UL << 8UL, /*!< Enable/disable OPAMP0 in active or low-power modes. */ + kSPC_controlOpamp1 = 1UL << 9UL, /*!< Enable/disable OPAMP1 in active or low-power modes. */ + kSPC_controlOpamp2 = 1UL << 10UL, /*!< Enable/disable OPAMP2 in active or low-power modes. */ + kSPC_controlCmp0 = 1UL << 16UL, /*!< Enable/disable CMP0 in active or low-power modes. */ + kSPC_controlCmp1 = 1UL << 17UL, /*!< Enable/disable CMP1 in active or low-power modes. */ + kSPC_controlCmp2 = 1UL << 18UL, /*!< Enable/disable CMP2 in active or low-power modes. */ + kSPC_controlCmp0Dac = 1UL << 20UL, /*!< Enable/disable CMP0_DAC in active or low-power modes. */ + kSPC_controlCmp1Dac = 1UL << 21UL, /*!< Enable/disable CMP1_DAC in active or low-power modes. */ + kSPC_controlCmp2Dac = 1UL << 22UL, /*!< Enable/disable CMP2_DAC in active or low-power modes. */ + kSPC_controlAllModules = 0x770773UL, /*!< Enable/disable all modules in active or low-power modes. */ +}; + +/*! + * @brief The enumeration of spc power domain, the connected power domain is chip specfic, please refer to chip's RM + * for details. + */ +typedef enum _spc_power_domain_id +{ + kSPC_PowerDomain0 = 0U, /*!< Power domain0, the connected power domain is chip specific. */ + kSPC_PowerDomain1 = 1U, /*!< Power domain1, the connected power domain is chip specific. */ +} spc_power_domain_id_t; + +/*! + * @brief The enumeration of Power domain's low power mode. + */ +typedef enum _spc_power_domain_low_power_mode +{ + kSPC_SleepWithSYSClockRunning = 0U, /*!< Power domain request SLEEP mode with SYS clock running. */ + kSPC_DeepSleepWithSysClockOff = 1U, /*!< Power domain request deep sleep mode with system clock off. */ + kSPC_PowerDownWithSysClockOff = 2U, /*!< Power domain request power down mode with system clock off. */ + kSPC_DeepPowerDownWithSysClockOff = 4U, /*!< Power domain request deep power down mode with system clock off. */ +} spc_power_domain_low_power_mode_t; + +/*! + * @brief SPC low power request output pin polarity. + */ +typedef enum _spc_lowPower_request_pin_polarity +{ + kSPC_HighTruePolarity = 0x0U, /*!< Control the High Polarity of the Low Power Reqest Pin. */ + kSPC_LowTruePolarity = 0x1U, /*!< Control the Low Polarity of the Low Power Reqest Pin. */ +} spc_lowpower_request_pin_polarity_t; + +/*! + * @brief SPC low power request output override. + */ +typedef enum _spc_lowPower_request_output_override +{ + kSPC_LowPowerRequestNotForced = 0x0U, /*!< Not Forced. */ + kSPC_LowPowerRequestReserved = 0x1U, /*!< Reserved. */ + kSPC_LowPowerRequestForcedLow = 0x2U, /*!< Forced Low (Ignore LowPower request output polarity setting.) */ + kSPC_LowPowerRequestForcedHigh = 0x3U, /*!< Forced High (Ignore LowPower request output polarity setting.) */ +} spc_lowpower_request_output_override_t; + +/*! + * @brief SPC Bandgap mode enumeration in Active mode or Low Power mode. + */ +typedef enum _spc_bandgap_mode +{ + kSPC_BandgapDisabled = 0x0U, /*!< Bandgap disabled. */ + kSPC_BandgapEnabledBufferDisabled = 0x1U, /*!< Bandgap enabled with Buffer disabled. */ + kSPC_BandgapEnabledBufferEnabled = 0x2U, /*!< Bandgap enabled with Buffer enabled. */ + kSPC_BandgapReserved = 0x3U, /*!< Reserved. */ +} spc_bandgap_mode_t; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * @brief DCDC regulator voltage level enumeration in Active mode or Low Power Mode. + * + * @note #kSPC_DCDC_RetentionVoltage not supported for all power modes. + */ +typedef enum _spc_dcdc_voltage_level +{ + kSPC_DCDC_RetentionVoltage = 0x0U, /*!< DCDC_CORE Regulator regulate to retention + Voltage(Only supportedin low power modes) */ + kSPC_DCDC_MidVoltage = 0x1U, /*!< DCDC_CORE Regulator regulate to Mid Voltage(1.0V). */ + kSPC_DCDC_NormalVoltage = 0x2U, /*!< DCDC_CORE Regulator regulate to Normal Voltage(1.1V). */ + kSPC_DCDC_OverdriveVoltage = 0x3U, /*!< DCDC_CORE Regulator regulate to Safe-Mode Voltage(1.2V). */ +} spc_dcdc_voltage_level_t; + +/*! + * @brief DCDC regulator Drive Strength enumeration in Active mode or Low Power Mode. + * + * @note Different drive strength differ in these DCDC characterstics: + * Maximum load current + * Quiescent current + * Transient response. + */ +typedef enum _spc_dcdc_drive_strength +{ + kSPC_DCDC_PulseRefreshMode = 0x0U, /*!< DCDC_CORE Regulator Drive Strength set to Pulse Refresh Mode, + * This enum member is only useful for Low Power Mode config, please + * note that pluse refresh mode is invalid in SLEEP mode. + */ + kSPC_DCDC_LowDriveStrength = 0x1U, /*!< DCDC_CORE regulator Drive Strength set to low. */ + kSPC_DCDC_NormalDriveStrength = 0x2U, /*!< DCDC_CORE regulator Drive Strength set to Normal. */ +} spc_dcdc_drive_strength_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * @brief SYS LDO regulator voltage level enumeration in Active mode. + */ +typedef enum _spc_sys_ldo_voltage_level +{ + kSPC_SysLDO_NormalVoltage = 0x0U, /*!< SYS LDO VDD Regulator regulate to Normal Voltage(1.8V). */ + kSPC_SysLDO_OverDriveVoltage = 0x1U, /*!< SYS LDO VDD Regulator regulate to Over Drive Voltage(2.5V). */ +} spc_sys_ldo_voltage_level_t; + +/*! + * @brief SYS LDO regulator Drive Strength enumeration in Active mode or Low Power mode. + */ +typedef enum _spc_sys_ldo_drive_strength +{ + kSPC_SysLDO_LowDriveStrength = 0x0U, /*!< SYS LDO VDD regulator Drive Strength set to low. */ + kSPC_SysLDO_NormalDriveStrength = 0x1U, /*!< SYS LDO VDD regulator Drive Strength set to Normal. */ +} spc_sys_ldo_drive_strength_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +/*! + * @brief Core LDO regulator voltage level enumeration in Active mode or Low Power mode. + */ +typedef enum _spc_core_ldo_voltage_level +{ + kSPC_CoreLDO_UnderDriveVoltage = 0x0U, /*!< @deprecated, to align with description of latest RM, please use + #kSPC_Core_LDO_RetentionVoltage as instead. */ + kSPC_Core_LDO_RetentionVoltage = 0x0U, /*!< Core LDO VDD regulator regulate to retention voltage, please note that + only useful in low power modes and not all devices support this options + please refer to devices' RM for details. */ + kSPC_CoreLDO_MidDriveVoltage = 0x1U, /*!< Core LDO VDD regulator regulate to Mid Drive Voltage. */ + kSPC_CoreLDO_NormalVoltage = 0x2U, /*!< Core LDO VDD regulator regulate to Normal Voltage. */ + kSPC_CoreLDO_OverDriveVoltage = 0x3U, /*!< Core LDO VDD regulator regulate to overdrive Voltage. */ +} spc_core_ldo_voltage_level_t; + +/*! + * @brief CORE LDO VDD regulator Drive Strength enumeration in Low Power mode. + */ +typedef enum _spc_core_ldo_drive_strength +{ + kSPC_CoreLDO_LowDriveStrength = 0x0U, /*!< Core LDO VDD regulator Drive Strength set to low. */ + kSPC_CoreLDO_NormalDriveStrength = 0x1U, /*!< Core LDO VDD regulator Drive Strength set to Normal. */ +} spc_core_ldo_drive_strength_t; + +/*! + * @brief IO VDD Low-Voltage Level Select. + */ +typedef enum _spc_low_voltage_level_select +{ + kSPC_LowVoltageNormalLevel = 0x0U, /*!< @deprecated, please use kSPC_LowVoltageHighRange as instead. */ + kSPC_LowVoltageSafeLevel = 0x1U, /*!< @deprecated, please use kSPC_LowVoltageLowRange as instead. */ + + kSPC_LowVoltageHighRange = 0x0U, /*!< High range LVD threshold. */ + kSPC_LowVoltageLowRange = 0x1U, /*!< Low range LVD threshold. */ +} spc_low_voltage_level_select_t; + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) +/*! + * @brief Used to select output of 4-bit ripple counter is used to monitor a glitch on VDD core. + */ +typedef enum _spc_vdd_core_glitch_ripple_counter_select +{ + kSPC_selectBit0Of4bitRippleCounter = 0x0U, /*!< Select bit-0 of 4-bit Ripple Counter + to detect glitch on VDD Core. */ + kSPC_selectBit1Of4bitRippleCounter = 0x1U, /*!< Select bit-1 of 4-bit Ripple Counter + to detect glitch on VDD Core. */ + kSPC_selectBit2Of4bitRippleCounter = 0x2U, /*!< Select bit-2 of 4-bit Ripple Counter + to detect glitch on VDD Core. */ + kSPC_selectBit3Of4bitRippleCounter = 0x3U, /*!< Select bit-3 of 4-bit Ripple Counter + to detect glitch on VDD Core. */ +} spc_vdd_core_glitch_ripple_counter_select_t; +#endif + +/*! + * @brief The list of the operating voltage for the SRAM's read/write timing margin. + */ +typedef enum _spc_sram_operate_voltage +{ + kSPC_sramOperateAt1P0V = 0x1U, /*!< SRAM configured for 1.0V operation. */ + kSPC_sramOperateAt1P1V = 0x2U, /*!< SRAM configured for 1.1V operation. */ + kSPC_sramOperateAt1P2V = 0x3U, /*!< SRAM configured for 1.2V operation. */ +} spc_sram_operate_voltage_t; + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) +/*! + * @brief The configuration of VDD Core glitch detector. + */ +typedef struct _spc_vdd_core_glitch_detector_config +{ + spc_vdd_core_glitch_ripple_counter_select_t rippleCounterSelect; /*!< Used to set ripple counter. */ + uint8_t resetTimeoutValue; /*!< The timeout value used to reset glitch detect/compare logic after an initial + glitch is detected. */ + bool enableReset; /*!< Used to enable/disable POR/LVD reset that caused by CORE VDD glitch detect error. */ + bool enableInterrupt; /*!< Used to enable/disable hardware interrupt if CORE VDD glitch detect error. */ +} spc_vdd_core_glitch_detector_config_t; +#endif + +typedef struct _spc_sram_voltage_config +{ + spc_sram_operate_voltage_t operateVoltage; /*!< Specifies the operating voltage for the SRAM's + read/write timing margin. */ + bool requestVoltageUpdate; /*!< Used to control whether request an SRAM trim value change. */ +} spc_sram_voltage_config_t; + +/*! + * @brief Low Power Request output pin configuration. + */ +typedef struct _spc_lowpower_request_config +{ + bool enable; /*!< Low Power Request Output enable. */ + spc_lowpower_request_pin_polarity_t polarity; /*!< Low Power Request Output pin polarity select. */ + spc_lowpower_request_output_override_t override; /*!< Low Power Request Output Override. */ +} spc_lowpower_request_config_t; + +/*! + * @brief Core LDO regulator options in Active mode. + */ +typedef struct _spc_active_mode_core_ldo_option +{ + spc_core_ldo_voltage_level_t CoreLDOVoltage; /*!< Core LDO Regulator Voltage Level selection in Active mode. */ +#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS + spc_core_ldo_drive_strength_t CoreLDODriveStrength; /*!< Core LDO Regulator Drive Strength + selection in Active mode */ +#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ +} spc_active_mode_core_ldo_option_t; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * @brief System LDO regulator options in Active mode. + */ +typedef struct _spc_active_mode_sys_ldo_option +{ + spc_sys_ldo_voltage_level_t SysLDOVoltage; /*!< System LDO Regulator Voltage Level selection in Active mode. */ + spc_sys_ldo_drive_strength_t SysLDODriveStrength; /*!< System LDO Regulator Drive Strength + selection in Active mode. */ +} spc_active_mode_sys_ldo_option_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * @brief DCDC regulator options in Active mode. + */ +typedef struct _spc_active_mode_dcdc_option +{ + spc_dcdc_voltage_level_t DCDCVoltage; /*!< DCDC Regulator Voltage Level selection in Active mode. */ + spc_dcdc_drive_strength_t DCDCDriveStrength; /*!< DCDC_CORE Regulator Drive Strength selection in Active mode. */ +} spc_active_mode_dcdc_option_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +/*! + * @brief Core LDO regulator options in Low Power mode. + */ +typedef struct _spc_lowpower_mode_core_ldo_option +{ + spc_core_ldo_voltage_level_t CoreLDOVoltage; /*!< Core LDO Regulator Voltage Level selection in Low Power mode. */ + spc_core_ldo_drive_strength_t CoreLDODriveStrength; /*!< Core LDO Regulator Drive Strength + selection in Low Power mode */ +} spc_lowpower_mode_core_ldo_option_t; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * @brief System LDO regulator options in Low Power mode. + */ +typedef struct _spc_lowpower_mode_sys_ldo_option +{ + spc_sys_ldo_drive_strength_t SysLDODriveStrength; /*!< System LDO Regulator Drive Strength + selection in Low Power mode. */ +} spc_lowpower_mode_sys_ldo_option_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * @brief DCDC regulator options in Low Power mode. + */ +typedef struct _spc_lowpower_mode_dcdc_option +{ + spc_dcdc_voltage_level_t DCDCVoltage; /*!< DCDC Regulator Voltage Level selection in Low Power mode. */ + spc_dcdc_drive_strength_t DCDCDriveStrength; /*!< DCDC_CORE Regulator Drive Strength selection in Low Power mode. */ +} spc_lowpower_mode_dcdc_option_t; + +/*! + * @brief DCDC Burst configuration. + * @deprecated Do not recommend to use this structure. + */ +typedef struct _spc_dcdc_burst_config +{ + bool sofwareBurstRequest; /*!< Enable/Disable DCDC Software Burst Request. */ + bool externalBurstRequest; /*!< Enable/Disable DCDC External Burst Request. */ + bool stabilizeBurstFreq; /*!< Enable/Disable DCDC frequency stabilization. */ + uint8_t freq; /*!< The frequency of the current burst. */ +} spc_dcdc_burst_config_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +/*! + * @brief CORE/SYS/IO VDD Voltage Detect options. + */ +typedef struct _spc_voltage_detect_option +{ + bool HVDInterruptEnable; /*!< CORE/SYS/IO VDD High Voltage Detect interrupt enable. */ + bool HVDResetEnable; /*!< CORE/SYS/IO VDD High Voltage Detect reset enable. */ + bool LVDInterruptEnable; /*!< CORE/SYS/IO VDD Low Voltage Detect interrupt enable. */ + bool LVDResetEnable; /*!< CORE/SYS/IO VDD Low Voltage Detect reset enable. */ +} spc_voltage_detect_option_t; + +/*! + * @brief Core Voltage Detect configuration. + */ +typedef struct _spc_core_voltage_detect_config +{ + spc_voltage_detect_option_t option; /*!< Core VDD Voltage Detect option. */ +} spc_core_voltage_detect_config_t; + +/*! + * @brief System Voltage Detect Configuration. + */ +typedef struct _spc_system_voltage_detect_config +{ + spc_voltage_detect_option_t option; /*!< System VDD Voltage Detect option. */ + spc_low_voltage_level_select_t level; /*!< @deprecated, reserved for all devices, will removed in next release. */ +} spc_system_voltage_detect_config_t; + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) +/*! + * @brief IO Voltage Detect Configuration. + */ +typedef struct _spc_io_voltage_detect_config +{ + spc_voltage_detect_option_t option; /*!< IO VDD Voltage Detect option. */ + spc_low_voltage_level_select_t level; /*!< IO VDD Low-voltage level selection. */ +} spc_io_voltage_detect_config_t; +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + +/*! + * @brief Active mode configuration. + */ +typedef struct _spc_active_mode_regulators_config +{ + spc_bandgap_mode_t bandgapMode; /*!< Specify bandgap mode in active mode. */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) + bool lpBuff; /*!< Enable/disable CMP bandgap buffer. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + spc_active_mode_dcdc_option_t DCDCOption; /*!< Specify DCDC configurations in active mode. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + spc_active_mode_sys_ldo_option_t SysLDOOption; /*!< Specify System LDO configurations in active mode. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + + spc_active_mode_core_ldo_option_t CoreLDOOption; /*!< Specify Core LDO configurations in active mode. */ +} spc_active_mode_regulators_config_t; + +/*! + * @brief Low Power Mode configuration. + */ +typedef struct _spc_lowpower_mode_regulators_config +{ + bool lpIREF; /*!< Enable/disable low power IREF in low power modes. */ + spc_bandgap_mode_t bandgapMode; /*!< Specify bandgap mode in low power modes. */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) + bool lpBuff; /*!< Enable/disable CMP bandgap buffer in low power modes. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) + bool CoreIVS; /*!< Enable/disable CORE VDD internal voltage scaling. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) + spc_lowpower_mode_dcdc_option_t DCDCOption; /*!< Specify DCDC configurations in low power modes. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) + spc_lowpower_mode_sys_ldo_option_t SysLDOOption; /*!< Specify system LDO configurations in low power modes. */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + + spc_lowpower_mode_core_ldo_option_t CoreLDOOption; /*!< Specify core LDO configurations in low power modes. */ +} spc_lowpower_mode_regulators_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name SPC Status + * @{ + */ +/*! + * @brief Gets Isolation status for each power domains. + * + * This function gets the status which indicates whether certain + * peripheral and the IO pads are in a latched state as a result + * of having been in POWERDOWN mode. + * + * @param base SPC peripheral base address. + * @return Current isolation status for each power domains. See @ref _spc_power_domains for details. + */ +uint8_t SPC_GetPeriphIOIsolationStatus(SPC_Type *base); + +/*! + * @brief Clears peripherals and I/O pads isolation flags for each power domains. + * + * This function clears peripherals and I/O pads isolation flags for each power domains. + * After recovering from the POWERDOWN mode, user must invoke this function to release the + * I/O pads and certain peripherals to their normal run mode state. Before invoking this + * function, user must restore chip configuration in particular pin configuration for enabled + * WUU wakeup pins. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_ClearPeriphIOIsolationFlag(SPC_Type *base) +{ + base->SC |= SPC_SC_ISO_CLR_MASK; +} + +/*! + * @brief Gets SPC busy status flag. + * + * This function gets SPC busy status flag. When SPC executing any type of power mode + * transition in ACTIVE mode or any of the SOC low power mode, the SPC busy status flag is set + * and this function returns true. When changing CORE LDO voltage level and DCDC voltage level + * in ACTIVE mode, the SPC busy status flag is set and this function return true. + * + * @param base SPC peripheral base address. + * @return Ack busy flag. + * true - SPC is busy. + * false - SPC is not busy. + */ +static inline bool SPC_GetBusyStatusFlag(SPC_Type *base) +{ + return ((base->SC & SPC_SC_BUSY_MASK) != 0UL); +} + +/*! + * @brief Checks system low power request. + * + * @note Only when all power domains request low power mode entry, the result of this function is true. That means when + * all power domains request low power mode entry, the SPC regulators will be controlled by LP_CFG register. + * + * @param base SPC peripheral base address. + * @return The system low power request check result. + * - \b true All power domains have requested low power mode and SPC has entered a low power state and power mode + * configuration are based on the LP_CFG configuration register. + * - \b false SPC in active mode and ACTIVE_CFG register control system power supply. + */ +static inline bool SPC_CheckLowPowerReqest(SPC_Type *base) +{ + return ((base->SC & SPC_SC_SPC_LP_REQ_MASK) == SPC_SC_SPC_LP_REQ_MASK); +} + +/*! + * @brief Clears system low power request, set SPC in active mode. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_ClearLowPowerRequest(SPC_Type *base) +{ + base->SC |= SPC_SC_SPC_LP_REQ_MASK; +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT) && FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT) +/*! + * @brief Checks whether the power switch is on. + * + * @param base SPC peripheral base address. + * + * @retval true The power switch is on. + * @retval false The power switch is off. + */ +static inline bool SPC_CheckSwitchState(SPC_Type *base) +{ + return ((base->SC & SPC_SC_SWITCH_STATE_MASK) != 0UL); +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT */ + +/*! + * @brief Gets selected power domain's requested low power mode. + * + * @param base SPC peripheral base address. + * @param powerDomainId Power Domain Id, please refer to @ref spc_power_domain_id_t. + * + * @return The selected power domain's requested low power mode, please refer to @ref spc_power_domain_low_power_mode_t. + */ +spc_power_domain_low_power_mode_t SPC_GetPowerDomainLowPowerMode(SPC_Type *base, spc_power_domain_id_t powerDomainId); + +/*! + * @brief Checks power domain's low power request. + * + * @param base SPC peripheral base address. + * @param powerDomainId Power Domain Id, please refer to @ref spc_power_domain_id_t. + * @return The result of power domain's low power request. + * - \b true The selected power domain requests low power mode entry. + * - \b false The selected power domain does not request low power mode entry. + */ +static inline bool SPC_CheckPowerDomainLowPowerRequest(SPC_Type *base, spc_power_domain_id_t powerDomainId) +{ + assert((uint8_t)powerDomainId < SPC_PD_STATUS_COUNT); + return ((base->PD_STATUS[(uint8_t)powerDomainId] & SPC_PD_STATUS_PWR_REQ_STATUS_MASK) == + SPC_PD_STATUS_PWR_REQ_STATUS_MASK); +} + +/*! + * @brief Clears selected power domain's low power request flag. + * + * @param base SPC peripheral base address. + * @param powerDomainId Power Domain Id, please refer to @ref spc_power_domain_id_t. + */ +static inline void SPC_ClearPowerDomainLowPowerRequestFlag(SPC_Type *base, spc_power_domain_id_t powerDomainId) +{ + assert((uint8_t)powerDomainId < SPC_PD_STATUS_COUNT); + base->PD_STATUS[(uint8_t)powerDomainId] |= SPC_PD_STATUS_PD_LP_REQ_MASK; +} + +/*! @} */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG) && FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG) +/*! + * @name SRAM Retention LDO Control APIs + * @{ + */ + +/*! + * @brief Trims SRAM retention regulator reference voltage, trim step is 12 mV, range is around 0.48V to 0.85V. + * + * @param base SPC peripheral base address. + * @param trimValue Reference voltage trim value. + */ +static inline void SPC_TrimSRAMLdoRefVoltage(SPC_Type *base, uint8_t trimValue) +{ + base->SRAMRETLDO_REFTRIM = + ((base->SRAMRETLDO_REFTRIM & ~SPC_SRAMRETLDO_REFTRIM_REFTRIM_MASK) | SPC_SRAMRETLDO_REFTRIM_REFTRIM(trimValue)); +} + +/*! + * @brief Enables/disables SRAM retention LDO. + * + * @param base SPC peripheral base address. + * @param enable Used to enable/disable SRAM LDO : + * - \b true Enable SRAM LDO; + * - \b false Disable SRAM LDO. + */ +static inline void SPC_EnableSRAMLdo(SPC_Type *base, bool enable) +{ + if (enable) + { + base->SRAMRETLDO_CNTRL |= SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK; + } + else + { + base->SRAMRETLDO_CNTRL &= ~SPC_SRAMRETLDO_CNTRL_SRAMLDO_ON_MASK; + } +} + +/*! + * @brief + * + * @todo Need to check. + * + * @param base SPC peripheral base address. + * @param mask The OR'ed value of SRAM Array. + */ +static inline void SPC_RetainSRAMArray(SPC_Type *base, uint8_t mask) +{ + base->SRAMRETLDO_CNTRL |= SPC_SRAMRETLDO_CNTRL_SRAM_RET_EN(mask); +} + +/*! @} */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG */ + +/*! + * @name Low Power Request configuration + * @{ + */ +/*! + * @brief Configs Low power request output pin. + * + * This function config the low power request output pin + * + * @param base SPC peripheral base address. + * @param config Pointer the @ref spc_lowpower_request_config_t structure. + */ +void SPC_SetLowPowerRequestConfig(SPC_Type *base, const spc_lowpower_request_config_t *config); + +/*! @} */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_CFG_REG) && FSL_FEATURE_MCX_SPC_HAS_CFG_REG) +/*! + * @name Integrated Power Switch Control APIs + * @{ + */ + +/*! + * @brief Enables/disables the integrated power switch manually. + * + * @param base SPC peripheral base address. + * @param enable Used to enable/disable the integrated power switch: + * - \b true Enable the integrated power switch; + * - \b false Disable the integrated power switch. + */ +static inline void SPC_EnableIntegratedPowerSwitchManually(SPC_Type *base, bool enable) +{ + if (enable) + { + base->CFG |= (SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN_MASK | SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN_MASK); + } + else + { + base->CFG &= ~(SPC_CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN_MASK | SPC_CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN_MASK); + } +} + +/*! + * @brief Enables/disables the integrated power switch automatically. + * + * To gate the integrated power switch when chip enter low power modes, and ungate the switch after wake-up from low + * power modes: + * @code + * SPC_EnableIntegratedPowerSwitchAutomatically(SPC, true, true); + * @endcode + * + * @param base SPC peripheral base address. + * @param sleepGate Enable the integrated power switch when chip enter low power modes: + * - \b true SPC asserts an output pin at low-power entry to power-gate the switch; + * - \b false SPC does not assert an output pin at low-power entry to power-gate the switch. + * @param wakeupUngate Enables the switch after wake-up from low power modes: + * - \b true SPC asserts an output pin at low-power exit to power-ungate the switch; + * - \b false SPC does not assert an output pin at low-power exit to power-ungate the switch. + */ +static inline void SPC_EnableIntegratedPowerSwitchAutomatically(SPC_Type *base, bool sleepGate, bool wakeupUngate) +{ + uint32_t tmp32 = ((base->CFG) & ~(SPC_CFG_INTG_PWSWTCH_SLEEP_EN_MASK | SPC_CFG_INTG_PWSWTCH_WKUP_EN_MASK)); + + tmp32 |= SPC_CFG_INTG_PWSWTCH_SLEEP_EN(sleepGate) | SPC_CFG_INTG_PWSWTCH_WKUP_EN(wakeupUngate); + + base->CFG = tmp32; +} + +/*! @} */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_CFG_REG */ + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) +/*! + * @name VDD Core Glitch Detector Control APIs + * @{ + */ + +/*! + * @brief Configures VDD Core Glitch detector, including ripple counter selection, timeout value and so on. + * + * @param base SPC peripheral base address. + * @param config Pointer to the structure in type of @ref spc_vdd_core_glitch_detector_config_t. + */ +void SPC_ConfigVddCoreGlitchDetector(SPC_Type *base, const spc_vdd_core_glitch_detector_config_t *config); + +/*! + * @brief Checks selected 4-bit glitch ripple counter's output. + * + * @param base SPC peripheral base address. + * @param rippleCounter The ripple counter to check, please refer to @ref spc_vdd_core_glitch_ripple_counter_select_t. + * + * @retval true The selected ripple counter output is 1, will generate interrupt or reset based on settings. + * @retval false The selected ripple counter output is 0. + */ + +static inline bool SPC_CheckGlitchRippleCounterOutput(SPC_Type *base, + spc_vdd_core_glitch_ripple_counter_select_t rippleCounter) +{ + return ((base->VDD_CORE_GLITCH_DETECT_SC & SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG_MASK) == + SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(1UL << (uint32_t)(rippleCounter))); +} + +/*! + * @brief Clears output of selected glitch ripple counter. + * + * @param base SPC peripheral base address. + * @param rippleCounter The ripple counter to check, please refer to @ref spc_vdd_core_glitch_ripple_counter_select_t. + */ +static inline void SPC_ClearGlitchRippleCounterOutput(SPC_Type *base, + spc_vdd_core_glitch_ripple_counter_select_t rippleCounter) +{ + base->VDD_CORE_GLITCH_DETECT_SC |= + SPC_VDD_CORE_GLITCH_DETECT_SC_GLITCH_DETECT_FLAG(1UL << (uint32_t)(rippleCounter)); +} + +/*! + * @brief After invoking this function, writes to SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register are ignored. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_LockVddCoreVoltageGlitchDetectResetControl(SPC_Type *base) +{ + base->VDD_CORE_GLITCH_DETECT_SC |= SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK; +} + +/*! + * @brief After invoking this function, writes to SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register are allowed. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_UnlockVddCoreVoltageGlitchDetectResetControl(SPC_Type *base) +{ + base->VDD_CORE_GLITCH_DETECT_SC &= ~SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK; +} + +/*! + * @brief Checks if SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register is writable. + * + * @param base SPC peripheral base address. + * + * @retval true SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register is writable. + * @retval false SPC_VDD_CORE_GLITCH_DETECT_SC[RE] register is not writable. + */ +static inline bool SPC_CheckVddCoreVoltageGlitchResetControlState(SPC_Type *base) +{ + return ((base->VDD_CORE_GLITCH_DETECT_SC & SPC_VDD_CORE_GLITCH_DETECT_SC_LOCK_MASK) != 0UL); +} + +/*! @} */ +#endif + +/*! + * @name SRAM Control APIs + * @{ + */ + +/*! + * @brief Set SRAM operate voltage. + * + * @param base SPC peripheral base address. + * @param config The pointer to @ref spc_sram_voltage_config_t, specifies the configuration of sram voltage. + */ +void SPC_SetSRAMOperateVoltage(SPC_Type *base, const spc_sram_voltage_config_t *config); + +/*! @} */ + +/*! + * @name Active Mode configuration + * @{ + */ + +/*! + * @brief Gets the Bandgap mode in Active mode. + * + * @param base SPC peripheral base address. + * @return Bandgap mode in the type of @ref spc_bandgap_mode_t enumeration. + */ +static inline spc_bandgap_mode_t SPC_GetActiveModeBandgapMode(SPC_Type *base) +{ + return (spc_bandgap_mode_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_BGMODE_MASK) >> + SPC_ACTIVE_CFG_BGMODE_SHIFT); +} + +/*! + * @brief Gets all voltage detectors status in Active mode. + * + * @param base SPC peripheral base address. + * @return All voltage detectors status in Active mode. + */ +static inline uint32_t SPC_GetActiveModeVoltageDetectStatus(SPC_Type *base) +{ + uint32_t state; + state = base->ACTIVE_CFG & + ( +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) + SPC_ACTIVE_CFG_IO_HVDE_MASK | SPC_ACTIVE_CFG_IO_LVDE_MASK | + +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + SPC_ACTIVE_CFG_SYS_HVDE_MASK | SPC_ACTIVE_CFG_SYS_LVDE_MASK | SPC_ACTIVE_CFG_CORE_LVDE_MASK + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) + | SPC_ACTIVE_CFG_CORE_HVDE_MASK + +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + ); + return state; +} + +/*! + * @brief Configs Bandgap mode in Active mode. + * + * @note To disable bandgap in Active mode: + * 1. Disable all LVD's and HVD's in active mode; + * 2. Disable Glitch detect; + * 3. Configrue LDO's and DCDC to low drive strength in active mode; + * 4. Invoke this function to disable bandgap in active mode; + * otherwise the error status will be reported. + * + * @note Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please + * take care of other system resources. + * + * @param base SPC peripheral base address. + * @param mode The Bandgap mode be selected. + * + * @retval #kStatus_SPC_BandgapModeWrong The Bandgap can not be disabled in active mode. + * @retval #kStatus_Success Config Bandgap mode in Active power mode successful. + */ +status_t SPC_SetActiveModeBandgapModeConfig(SPC_Type *base, spc_bandgap_mode_t mode); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) +/*! + * @brief Enables/Disable the CMP Bandgap Buffer in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable CMP Bandgap buffer. + * true - Enable Buffer Stored Reference voltage to CMP. + * false - Disable Buffer Stored Reference voltage to CMP. + */ +static inline void SPC_EnableActiveModeCMPBandgapBuffer(SPC_Type *base, bool enable) +{ + if (enable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_LPBUFF_EN_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_LPBUFF_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +/*! + * @brief Sets the delay when the regulators change voltage level in Active mode. + * + * @param base SPC peripheral base address. + * @param delay The number of SPC timer clock cycles. + */ +static inline void SPC_SetActiveModeVoltageTrimDelay(SPC_Type *base, uint16_t delay) +{ + base->ACTIVE_VDELAY = SPC_ACTIVE_VDELAY_ACTIVE_VDELAY(delay); +} + +/*! + * @brief Configs all settings of regulators in Active mode at a time. + * + * @note This function is used to overwrite all settings of regulators(including bandgap mode, regulators' + * drive strength and voltage level) in active mode at a time. + * + * @note Enable/disable LVDs/HVDs before invoking this function. + * + * @note This function will check input parameters based on hardware restrictions before setting registers, if input + * parameters do not satisfy hardware restrictions the specific error will be reported. + * + * + * @note Some hardware restrictions not covered, application should be aware of this and follow this hardware + * restrictions otherwise some unkown issue may occur: + * 1. If Core LDO's drive strength are set to same value in both Active mode and low power mode, + * the voltage level should also set to same value. + * 2. When switching Core LDO's drive strength from low to normal, ensure the LDO_CORE high voltage level is set + * to same level that was set prior to switching to the LDO_CORE drive strength. Otherwise, if the LVDs are + * enabled, an unexpected LVD can occur. + * + * @note If this function can not satisfy some tricky settings, please invoke other APIs in low-level function group. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_active_mode_regulators_config_t structure. + * + * @retval #kStatus_Success Config regulators in Active power mode successful. + * @retval #kStatus_SPC_BandgapModeWrong Based on input setting, bandgap can not be disabled. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Any of LVDs/HVDs kept enabled before invoking this function. + * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Fail to regulator to Over Drive Voltage due to + * System VDD HVD is not disabled. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Any of LVDs/HVDs kept enabled before invoking this function. + * @retval #kStatus_SPC_CORELDOVoltageWrong Core LDO and System LDO do not have same voltage level. + */ +status_t SPC_SetActiveModeRegulatorsConfig(SPC_Type *base, const spc_active_mode_regulators_config_t *config); + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) +/*! + * @brief Disables/Enables VDD Core Glitch Detect in Active mode. + * + * @note State of glitch detect disable feature will be ignored if bandgap is disabled and + * glitch detect hardware will be forced to OFF state. + * + * @param base SPC peripheral base address. + * @param disable Used to disable/enable VDD Core Glitch detect feature. + * - \b true Disable VDD Core Low Voltage detect; + * - \b false Enable VDD Core Low Voltage detect. + */ +static inline void SPC_DisableActiveModeVddCoreGlitchDetect(SPC_Type *base, bool disable) +{ + if (disable) + { + base->ACTIVE_CFG |= SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + } + else + { + base->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK; + } +} + +/*! + * @brief Check if Glitch detect hardware is enabled in active mode. + * + * @param base SPC peripheral base address. + * @return Indicate if Glitch detector is enabled. + */ +static inline bool SPC_CheckActiveModeVddCoreGlitchDetectEnabled(SPC_Type *base) +{ + if ((base->ACTIVE_CFG & SPC_ACTIVE_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL) + { + return true; + } + else + { + return false; + } +} + +#endif /* FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT */ + +/*! + * @brief Enables analog modules in active mode. + * + * @param base SPC peripheral base address. + * @param maskValue The mask of analog modules to enable in active mode, should be the OR'ed value + * of @ref spc_analog_module_control. + */ +static inline void SPC_EnableActiveModeAnalogModules(SPC_Type *base, uint32_t maskValue) +{ + base->ACTIVE_CFG1 |= SPC_ACTIVE_CFG1_SOC_CNTRL(maskValue); +} + +/*! + * @brief Disables analog modules in active mode. + * + * @param base SPC peripheral base address. + * @param maskValue The mask of analog modules to disable in active mode, should be the OR'ed value + * of @ref spc_analog_module_control. + */ +static inline void SPC_DisableActiveModeAnalogModules(SPC_Type *base, uint32_t maskValue) +{ + base->ACTIVE_CFG1 &= ~SPC_ACTIVE_CFG1_SOC_CNTRL(maskValue); +} + +/*! + * @brief Gets enabled analog modules that enabled in active mode. + * + * @param base SPC peripheral base address. + * + * @return The mask of enabled analog modules that enabled in active mode. + */ +static inline uint32_t SPC_GetActiveModeEnabledAnalogModules(SPC_Type *base) +{ + return base->ACTIVE_CFG1; +} + +/*! @} */ + +/*! + * @name Low Power mode configuration + * @{ + */ + +/*! + * @brief Gets the Bandgap mode in Low Power mode. + * + * @param base SPC peripheral base address. + * @return Bandgap mode in the type of @ref spc_bandgap_mode_t enumeration. + */ +static inline spc_bandgap_mode_t SPC_GetLowPowerModeBandgapMode(SPC_Type *base) +{ + return (spc_bandgap_mode_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_BGMODE_MASK) >> SPC_LP_CFG_BGMODE_SHIFT); +} + +/*! + * @brief Gets the status of all voltage detectors in Low Power mode. + * + * @param base SPC peripheral base address. + * @return The status of all voltage detectors in low power mode. + */ +static inline uint32_t SPC_GetLowPowerModeVoltageDetectStatus(SPC_Type *base) +{ + uint32_t state; + state = base->LP_CFG & ( +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) + SPC_LP_CFG_IO_HVDE_MASK | SPC_LP_CFG_IO_LVDE_MASK | + +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + SPC_LP_CFG_SYS_HVDE_MASK | SPC_LP_CFG_SYS_LVDE_MASK | SPC_LP_CFG_CORE_LVDE_MASK + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) + | SPC_LP_CFG_CORE_HVDE_MASK + +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + ); + return state; +} + +/*! + * @brief Enables/Disables Low Power IREF in low power modes. + * + * This function enables/disables Low Power IREF. Low Power IREF can only get + * disabled in Deep power down mode. In other low power modes, the Low Power IREF + * is always enabled. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Low Power IREF. + * true - Enable Low Power IREF for Low Power modes. + * false - Disable Low Power IREF for Deep Power Down mode. + */ +static inline void SPC_EnableLowPowerModeLowPowerIREF(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_LP_IREFEN_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_LP_IREFEN_MASK; + } +} + +/*! + * @brief Configs Bandgap mode in Low Power mode. + * + * @note To disable Bandgap in Low-power mode: + * 1. Disable all LVD's ad HVD's in low power mode; + * 2. Disable Glitch detect in low power mode; + * 3. Configure LDO's and DCDC to low drive strength in low power mode; + * 4. Disable bandgap in low power mode; + * Otherwise, the error status will be reported. + * + * @note Some other system resources(such as PLL, CMP) require bandgap to be enabled, to disable bandgap please + * take care of other system resources. + * + * @param base SPC peripheral base address. + * @param mode The Bandgap mode be selected. + * + * @retval #kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. + * @retval #kStatus_Success Config Bandgap mode in Low Power power mode successful. + */ +status_t SPC_SetLowPowerModeBandgapmodeConfig(SPC_Type *base, spc_bandgap_mode_t mode); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT) && FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT) +/*! + * @brief Enables/disables SRAM_LDO deep power low power IREF. + * + * @param base SPC peripheral base address. + * @param enable Used to enable/disable low power IREF : + * - \b true: Low Power IREF is enabled ; + * - \b false: Low Power IREF is disabled for power saving. + */ +static inline void SPC_EnableSRAMLdOLowPowerModeIREF(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_SRAMLDO_DPD_ON_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_SRAMLDO_DPD_ON_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT) +/*! + * @brief Enables/Disables CMP Bandgap Buffer. + * + * This function gates CMP bandgap buffer. CMP bandgap buffer is automatically disabled and turned off + * in Deep Power Down mode. + * + * @deprecated No longer used, please use SPC_EnableLowPowerModeCMPBandgapBuffer as instead. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable CMP Bandgap buffer. + * true - Enable Buffer Stored Reference Voltage to CMP. + * false - Disable Buffer Stored Reference Voltage to CMP. + */ +static inline void SPC_EnableLowPowerModeCMPBandgapBufferMode(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_LPBUFF_EN_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_LPBUFF_EN_MASK; + } +} + +/*! + * @brief Enables/Disables CMP Bandgap Buffer. + * + * This function gates CMP bandgap buffer. CMP bandgap buffer is automatically disabled and turned off + * in Deep Power Down mode. + * + * @deprecated No longer used. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable CMP Bandgap buffer. + * true - Enable Buffer Stored Reference Voltage to CMP. + * false - Disable Buffer Stored Reference Voltage to CMP. + */ +static inline void SPC_EnableLowPowerModeCMPBandgapBuffer(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_LPBUFF_EN_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_LPBUFF_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT) +/*! + * @brief Enables/Disables CORE VDD IVS(Internal Voltage Scaling) in power down modes. + * + * This function gates CORE VDD IVS. When enabled, the IVS regulator will scale the + * external input CORE VDD to a lower voltage level to reduce internal leakage. + * IVS is invalid in Sleep or Deep power down mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IVS. + * true - enable CORE VDD IVS in Power Down mode. + * false - disable CORE VDD IVS in Power Down mode. + */ +static inline void SPC_EnableLowPowerModeCoreVDDInternalVoltageScaling(SPC_Type *base, bool enable) +{ + if (enable) + { + base->LP_CFG |= SPC_LP_CFG_COREVDD_IVS_EN_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_COREVDD_IVS_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT */ + +/*! + * @brief Sets the delay when exit the low power modes. + * + * @param base SPC peripheral base address. + * @param delay The number of SPC timer clock cycles that the SPC waits on exit from low power modes. + */ +static inline void SPC_SetLowPowerWakeUpDelay(SPC_Type *base, uint16_t delay) +{ + base->LPWKUP_DELAY = SPC_LPWKUP_DELAY_LPWKUP_DELAY(delay); +} + +/*! + * @brief Configs all settings of regulators in Low power mode at a time. + * + * @note This function is used to overwrite all settings of regulators(including bandgap mode, regulators' + * drive strength and voltage level) in low power mode at a time. + * + * @note Enable/disable LVDs/HVDs before invoking this function. + * + * @note This function will check input parameters based on hardware restrictions before setting registers, if input + * parameters do not satisfy hardware restrictions the specific error will be reported. + * + * @note Some hardware restrictions not covered, application should be aware of this and follow this hardware + * restrictions otherwise some unkown issue may occur: + * 1. If Core LDO's drive strength are set to same value in both Active mode and low power mode, + * the voltage level should also set to same value. + * 2. When switching Core LDO's drive strength from low to normal, ensure the LDO_CORE high voltage level is set + * to same level that was set prior to switching to the LDO_CORE drive strength. Otherwise, if the LVDs are + * enabled, an unexpected LVD can occur. + * + * @note If this function can not satisfy some tricky settings, please invoke other APIs in low-level function group. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_lowpower_mode_regulators_config_t structure. + * @retval #kStatus_Success Config regulators in Low power mode successful. + * @retval #kStatus_SPC_BandgapModeWrong The bandgap should not be disabled based on input settings. + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * @retval #kStatus_SPC_CORELDOVoltageWrong Core LDO and System LDO do not have same voltage level. + */ +status_t SPC_SetLowPowerModeRegulatorsConfig(SPC_Type *base, const spc_lowpower_mode_regulators_config_t *config); + +#if !(defined(FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) && FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT) +/*! + * @brief Disable/Enable VDD Core Glitch Detect in low power mode. + * + * @note State of glitch detect disable feature will be ignored if bandgap is disabled and + * glitch detect hardware will be forced to OFF state. + * + * @param base SPC peripheral base address. + * @param disable Used to disable/enable VDD Core Glitch detect feature. + * - \b true Disable VDD Core Low Voltage detect; + * - \b false Enable VDD Core Low Voltage detect. + */ +static inline void SPC_DisableLowPowerModeVddCoreGlitchDetect(SPC_Type *base, bool disable) +{ + if (disable) + { + base->LP_CFG |= SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK; + } + else + { + base->LP_CFG &= ~SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK; + } +} + +/*! + * @brief Check if Glitch detect hardware is enabled in low power mode. + * + * @param base SPC peripheral base address. + * @return Indicate if Glitch detector is enabled. + */ +static inline bool SPC_CheckLowPowerModeVddCoreGlitchDetectEnabled(SPC_Type *base) +{ + if ((base->LP_CFG & SPC_LP_CFG_GLITCH_DETECT_DISABLE_MASK) == 0UL) + { + return true; + } + else + { + return false; + } +} +#endif + +/*! + * @brief Enables analog modules in low power modes. + * + * @param base SPC peripheral base address. + * @param maskValue The mask of analog modules to enable in low power modes, should be OR'ed value + of @ref spc_analog_module_control. + */ +static inline void SPC_EnableLowPowerModeAnalogModules(SPC_Type *base, uint32_t maskValue) +{ + base->LP_CFG1 |= SPC_LP_CFG1_SOC_CNTRL(maskValue); +} + +/*! + * @brief Disables analog modules in low power modes. + * + * @param base SPC peripheral base address. + * @param maskValue The mask of analog modules to disable in low power modes, should be OR'ed value + of @ref spc_analog_module_control. + */ +static inline void SPC_DisableLowPowerModeAnalogModules(SPC_Type *base, uint32_t maskValue) +{ + base->LP_CFG1 &= ~SPC_LP_CFG1_SOC_CNTRL(maskValue); +} + +/*! + * @brief Gets enabled analog modules that enabled in low power modes. + * + * @param base SPC peripheral base address. + * + * @return The mask of enabled analog modules that enabled in low power modes. + */ +static inline uint32_t SPC_GetLowPowerModeEnabledAnalogModules(SPC_Type *base) +{ + return base->LP_CFG1; +} + +/*! @} */ + +/*! + * @name Voltage Detect Status + * @{ + */ +/*! + * @brief Get Voltage Detect Status Flags. + * + * @param base SPC peripheral base address. + * @return Voltage Detect Status Flags. See @ref _spc_voltage_detect_flags for details. + */ +static inline uint8_t SPC_GetVoltageDetectStatusFlag(SPC_Type *base) +{ + return (uint8_t)(base->VD_STAT); +} + +/*! + * @brief Clear Voltage Detect Status Flags. + * + * @param base SPC peripheral base address. + * @param mask The mask of the voltage detect status flags. See @ref _spc_voltage_detect_flags for details. + */ +static inline void SPC_ClearVoltageDetectStatusFlag(SPC_Type *base, uint8_t mask) +{ + base->VD_STAT |= mask; +} + +/*! @} */ + +/*! + * @name Voltage Detect configuration for Core voltage domain. + * @{ + */ + +/*! + * @brief Configs CORE voltage detect options. + * + * @note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset so only one is enabled. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_core_voltage_detect_config_t structure. + */ +void SPC_SetCoreVoltageDetectConfig(SPC_Type *base, const spc_core_voltage_detect_config_t *config); + +/*! + * @brief Locks Core voltage detect reset setting. + * + * This function locks core voltage detect reset setting. After invoking this function + * any configuration of Core voltage detect reset will be ignored. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_LockCoreVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_CORE_CFG |= SPC_VD_CORE_CFG_LOCK_MASK; +} + +/*! + * @brief Unlocks Core voltage detect reset setting. + * + * This function unlocks core voltage detect reset setting. If locks the Core + * voltage detect reset setting, invoking this function to unlock. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_UnlockCoreVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_CORE_CFG &= ~SPC_VD_CORE_CFG_LOCK_MASK; +} + +/*! + * @brief Enables/Disables the Core Low Voltage Detector in Active mode. + * + * @note If the CORE_LDO low voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Core LVD. + * true - Enable Core Low voltage detector in active mode. + * false - Disable Core Low voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable Core Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeCoreLowVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the Core Low Voltage Detector in Low Power mode. + * + * This function enables/disables the Core Low Voltage Detector. + * If enabled the Core Low Voltage detector. The Bandgap mode in + * low power mode must be programmed so that Bandgap is enabled. + * + * @note If the CORE_LDO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Core HVD. + * true - Enable Core Low voltage detector in low power mode. + * false - Disable Core Low voltage detector in low power mode. + * + * @retval #kStatus_Success Enable/Disable Core Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeCoreLowVoltageDetect(SPC_Type *base, bool enable); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) && FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD) +/*! + * @brief Enables/Disables the Core High Voltage Detector in Active mode. + * + * @note If the CORE_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Core HVD. + * true - Enable Core High voltage detector in active mode. + * false - Disable Core High voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable Core High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeCoreHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the Core High Voltage Detector in Low Power mode. + * + * This function enables/disables the Core High Voltage Detector. + * If enabled the Core High Voltage detector. The Bandgap mode in + * low power mode must be programmed so that Bandgap is enabled. + * + * @note If the CORE_LDO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in low power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable Core HVD. + * true - Enable Core High voltage detector in low power mode. + * false - Disable Core High voltage detector in low power mode. + * + * @retval #kStatus_Success Enable/Disable Core High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeCoreHighVoltageDetect(SPC_Type *base, bool enable); +#endif /* FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD */ + +/*! @} */ + +/*! + * @name Voltage detect configuration for System Voltage domain + * @{ + */ +/*! + * @brief Set system VDD Low-voltage level selection. + * + * This function selects the system VDD low-voltage level. Changing system VDD low-voltage level + * must be done after disabling the System VDD low voltage reset and interrupt. + * + * @deprecated In latest RM, reserved for all devices, will removed in next release. + * + * @param base SPC peripheral base address. + * @param level System VDD Low-Voltage level selection. + */ +void SPC_SetSystemVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level); + +/*! + * @brief Configs SYS voltage detect options. + * + * This function config SYS voltage detect options. + * @note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset so only one is enabled. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_system_voltage_detect_config_t structure. + */ +void SPC_SetSystemVoltageDetectConfig(SPC_Type *base, const spc_system_voltage_detect_config_t *config); + +/*! + * @brief Lock System voltage detect reset setting. + * + * This function locks system voltage detect reset setting. After invoking this function + * any configuration of System Voltage detect reset will be ignored. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_LockSystemVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_SYS_CFG |= SPC_VD_SYS_CFG_LOCK_MASK; +} + +/*! + * @brief Unlock System voltage detect reset setting. + * + * This function unlocks system voltage detect reset setting. If locks the System + * voltage detect reset setting, invoking this function to unlock. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_UnlockSystemVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_SYS_CFG &= ~SPC_VD_SYS_CFG_LOCK_MASK; +} + +/*! + * @brief Enables/Disables the System High Voltage Detector in Active mode. + * + * @note If the System_LDO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System HVD. + * true - Enable System High voltage detector in active mode. + * false - Disable System High voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable System High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeSystemHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disable the System Low Voltage Detector in Active mode. + * + * @note If the System_LDO low voltage detect is enabled in Active mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System LVD. + * true - Enable System Low voltage detector in active mode. + * false - Disable System Low voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable the System Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeSystemLowVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the System High Voltage Detector in Low Power mode. + * + * @note If the System_LDO high voltage detect is enabled in Low Power mode, please note + * that the bandgap must be enabled and the drive strength of each regulator must + * not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System HVD. + * true - Enable System High voltage detector in low power mode. + * false - Disable System High voltage detector in low power mode. + * + * @retval #kStatus_Success Enable/Disable System High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeSystemHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the System Low Voltage Detector in Low Power mode. + * + * @note If the System_LDO low voltage detect is enabled in Low Power mode, + * please note that the bandgap must be enabled and the drive strength of each + * regulator must not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System HVD. + * true - Enable System Low voltage detector in low power mode. + * false - Disable System Low voltage detector in low power mode. + * + * @retval #kStatus_Success Enables System Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeSystemLowVoltageDetect(SPC_Type *base, bool enable); + +/*! @} */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) && FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD) +/*! + * @name Voltage detect configuration for IO voltage domain + * @{ + */ +/*! + * @brief Set IO VDD Low-Voltage level selection. + * + * This function selects the IO VDD Low-voltage level. Changing IO VDD low-voltage level + * must be done after disabling the IO VDD low voltage reset and interrupt. + * + * @param base SPC peripheral base address. + * @param level IO VDD Low-voltage level selection. + */ +void SPC_SetIOVDDLowVoltageLevel(SPC_Type *base, spc_low_voltage_level_select_t level); + +/*! + * @brief Configs IO voltage detect options. + * + * This function config IO voltage detect options. + * @note: Setting both the voltage detect interrupt and reset + * enable will cause interrupt to be generated on exit from reset. + * If those conditioned is not desired, interrupt/reset so only one is enabled. + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_voltage_detect_config_t structure. + */ +void SPC_SetIOVoltageDetectConfig(SPC_Type *base, const spc_io_voltage_detect_config_t *config); + +/*! + * @brief Lock IO Voltage detect reset setting. + * + * This function locks IO voltage detect reset setting. After invoking this function + * any configuration of system voltage detect reset will be ignored. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_LockIOVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_IO_CFG |= SPC_VD_IO_CFG_LOCK_MASK; +} + +/*! + * @brief Unlock IO voltage detect reset setting. + * + * This function unlocks IO voltage detect reset setting. If locks the IO + * voltage detect reset setting, invoking this function to unlock. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_UnlockIOVoltageDetectResetSetting(SPC_Type *base) +{ + base->VD_IO_CFG &= ~SPC_VD_IO_CFG_LOCK_MASK; +} + +/*! + * @brief Enables/Disables the IO High Voltage Detector in Active mode. + * + * @note If the IO high voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IO HVD. + * true - Enable IO High voltage detector in active mode. + * false - Disable IO High voltage detector in active mode. + * + * @retval #kStatus_Success Enable/Disable IO High Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeIOHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the IO Low Voltage Detector in Active mode. + * + * @note If the IO low voltage detect is enabled in Active mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Active mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IO LVD. + * true - Enable IO Low voltage detector in active mode. + * false - Disable IO Low voltage detector in active mode. + * + * @retval #kStatus_Success Enable IO Low Voltage Detect successfully. + */ +status_t SPC_EnableActiveModeIOLowVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the IO High Voltage Detector in Low Power mode. + * + * @note If the IO high voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IO HVD. + * true - Enable IO High voltage detector in low power mode. + * false - Disable IO High voltage detector in low power mode. + * + * @retval #kStatus_Success Enable IO High Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeIOHighVoltageDetect(SPC_Type *base, bool enable); + +/*! + * @brief Enables/Disables the IO Low Voltage Detector in Low Power mode. + * + * @note If the IO low voltage detect is enabled in Low Power mode, please note that the bandgap must be enabled + * and the drive strength of each regulator must not set to low in Low Power mode. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable IO LVD. + * true - Enable IO Low voltage detector in low power mode. + * false - Disable IO Low voltage detector in low power mode. + * + * @retval #kStatus_Success Enable/Disable IO Low Voltage Detect in low power mode successfully. + */ +status_t SPC_EnableLowPowerModeIOLowVoltageDetect(SPC_Type *base, bool enable); + +/*! @} */ + +#endif /* FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD */ + +/*! + * @name External Voltage domains configuration + * @{ + */ +/*! + * @brief Configs external voltage domains + * + * This function configs external voltage domains isolation. + * + * @param base SPC peripheral base address. + * @param lowPowerIsoMask The mask of external domains isolate enable during low power mode. Please read the Reference + * Manual for the Bitmap. + * @param IsoMask The mask of external domains isolate. Please read the Reference Manual for the Bitmap. + */ +void SPC_SetExternalVoltageDomainsConfig(SPC_Type *base, uint8_t lowPowerIsoMask, uint8_t IsoMask); + +/*! + * @brief Gets External Domains status. + * + * @param base SPC peripheral base address. + * @return The status of each external domain. + */ +static inline uint8_t SPC_GetExternalDomainsStatus(SPC_Type *base) +{ + return (uint8_t)(base->EVD_CFG >> SPC_EVD_CFG_REG_EVDSTAT_SHIFT); +} + +/*! @} */ + +/*! + * @name Low Level APIs To Set CORE LDO Regulator + * @{ + */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG) && FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG) +/*! + * @brief Enable/Disable Core LDO regulator. + * + * @note The CORE LDO enable bit is write-once. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable CORE LDO Regulator. + * true - Enable CORE LDO Regulator. + * false - Disable CORE LDO Regulator. + */ +static inline void SPC_EnableCoreLDORegulator(SPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTRL |= SPC_CNTRL_CORELDO_EN_MASK; + } + else + { + /* + * $Branch Coverage Justification$ + * If CORE_LDO is disabled, all RAMs data will powered off. + */ + base->CNTRL &= ~SPC_CNTRL_CORELDO_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT) && \ + FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT) +/*! + * @brief Enable/Disable the CORE LDO Regulator pull down in Deep Power Down. + * + * @note This function only useful when enabled the CORE LDO Regulator. + * + * @param base SPC peripheral base address. + * @param pulldown Enable/Disable CORE LDO pulldown in Deep Power Down mode. + * true - CORE LDO Regulator will discharge in Deep Power Down mode. + * false - CORE LDO Regulator will not discharge in Deep Power Down mode. + */ +static inline void SPC_PullDownCoreLDORegulator(SPC_Type *base, bool pulldown) +{ + if (pulldown) + { + base->CORELDO_CFG &= ~SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK; + } + else + { + base->CORELDO_CFG |= SPC_CORELDO_CFG_DPDOWN_PULLDOWN_DISABLE_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT */ + +/*! + * @brief Configs Core LDO Regulator in Active mode. + * + * @note The bandgap must be enabled before invoking this function. + * @note To set Core LDO as low drive strength, all HVDs/LVDs must be disabled previously. + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_active_mode_core_ldo_option_t structure. + * + * @retval kStatus_Success Config Core LDO regulator in Active power mode successful. + * @retval kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval kStatus_SPC_BandgapModeWrong Bandgap should be enabled before invoking this function. + * @retval kStatus_SPC_CORELDOLowDriveStrengthIgnore To set Core LDO as low drive strength, + * all LVDs/HVDs must be disabled before invoking this function. + */ +status_t SPC_SetActiveModeCoreLDORegulatorConfig(SPC_Type *base, const spc_active_mode_core_ldo_option_t *option); + +/*! + * @brief Set Core LDO Regulator Voltage level in Active mode. + * + * @param base SPC peripheral base address. + * @param voltageLevel Specify the voltage level of CORE LDO Regulator in Active mode, please + refer to @ref spc_core_ldo_voltage_level_t. + * + * @note In active mode, the Core LDO voltage level should only be changed when the + * Core LDO is in normal drive strength. + * + * @note Update Core LDO voltage level will set Busy flag, + * this function return only when busy flag is cleared by hardware + * + * @retval kStatus_SPC_CORELDOVoltageSetFail The drive strength of Core LDO is not normal. + * @retval kStatus_Success Set Core LDO regulator voltage level in Active power mode successful. + */ +status_t SPC_SetActiveModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel); + +/*! + * @brief Gets CORE LDO Regulator Voltage level. + * + * This function returns the voltage level of CORE LDO Regulator in Active mode. + * + * @param base SPC peripheral base address. + * @return Voltage level of CORE LDO in type of @ref spc_core_ldo_voltage_level_t enumeration. + */ +static inline spc_core_ldo_voltage_level_t SPC_GetActiveModeCoreLDOVDDVoltageLevel(SPC_Type *base) +{ + return (spc_core_ldo_voltage_level_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_LVL_MASK) >> + SPC_ACTIVE_CFG_CORELDO_VDD_LVL_SHIFT); +} + +#if (defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) +/*! + * @brief Set Core LDO VDD Regulator Drive Strength in Active mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the drive strength of CORE LDO Regulator in Active mode, please + refer to @ref spc_core_ldo_drive_strength_t. + * + * @retval #kStatus_Success Set Core LDO regulator drive strength in Active power mode successful. + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore If any voltage detect enabled, + core_ldo's drive strength can not set to low. + * @retval #kStatus_SPC_BandgapModeWrong The selected bandgap mode is not allowed. + */ +status_t SPC_SetActiveModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength); + +/*! + * @brief Gets CORE LDO VDD Regulator Drive Strength in Active mode. + * + * @param base SPC peripheral base address. + * @return Drive Strength of CORE LDO regulator in Active mode, please refer to @ref spc_core_ldo_drive_strength_t. + */ +static inline spc_core_ldo_drive_strength_t SPC_GetActiveModeCoreLDODriveStrength(SPC_Type *base) +{ + return (spc_core_ldo_drive_strength_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK) >> + SPC_ACTIVE_CFG_CORELDO_VDD_DS_SHIFT); +} +#endif /* defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */ + +/*! + * @brief Configs CORE LDO Regulator in low power mode + * + * This function configs CORE LDO Regulator in Low Power mode. + * If CORE LDO VDD Drive Strength is set to Normal, the CORE LDO VDD regulator voltage + * level in Active mode must be equal to the voltage level in Low power mode. And the Bandgap + * must be programmed to select bandgap enabled. + * Core VDD voltage levels for the Core LDO low power regulator can only be changed when the CORE + * LDO Drive Strength set as Normal. + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_lowpower_mode_core_ldo_option_t structure. + * + * @retval #kStatus_Success Config Core LDO regulator in power mode successfully. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + * @retval #kStatus_SPC_CORELDOVoltageSetFail. Fail to change Core LDO voltage level. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_core_ldo_option_t *option); + +/*! + * @brief Set Core LDO VDD Regulator Voltage level in Low power mode. + * + * @note If CORE LDO's drive strength is set to Normal, the CORE LDO VDD regulator voltage in active mode and low power + * mode must be same. + * @note Voltage level for the CORE LDO in low power mode can only be changed when the CORE LDO Drive Strength set as + * Normal. + * + * @param base SPC peripheral base address. + * @param voltageLevel Voltage level of CORE LDO Regulator in Low power mode, please + refer to @ref spc_core_ldo_voltage_level_t. + * + * @retval #kStatus_SPC_CORELDOVoltageWrong Voltage level in active mode and low power mode is not same. + * @retval #kStatus_Success Set Core LDO regulator voltage level in Low power mode successful. + * @retval #kStatus_SPC_CORELDOVoltageSetFail Fail to update voltage level because drive strength is incorrect. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorVoltageLevel(SPC_Type *base, spc_core_ldo_voltage_level_t voltageLevel); + +/*! + * @brief Gets the CORE LDO VDD Regulator Voltage Level for Low Power modes. + * + * @param base SPC peripheral base address. + * @return The CORE LDO VDD Regulator's voltage level. + */ +static inline spc_core_ldo_voltage_level_t SPC_GetLowPowerCoreLDOVDDVoltageLevel(SPC_Type *base) +{ + return ((spc_core_ldo_voltage_level_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_LVL_MASK) >> + SPC_LP_CFG_CORELDO_VDD_LVL_SHIFT)); +} + +/*! + * @brief Set Core LDO VDD Regulator Drive Strength in Low power mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify drive strength of CORE LDO in low power mode. + * + * @retval #kStatus_SPC_CORELDOLowDriveStrengthIgnore Some voltage detect enabled, CORE LDO's drive strength can not set + * as low. + * @retval #kStatus_Success Set Core LDO regulator drive strength in Low power mode successful. + * @retval #kStatus_SPC_BandgapModeWrong Bandgap is disabled when attempt to set CORE LDO work as normal drive strength. + */ +status_t SPC_SetLowPowerModeCoreLDORegulatorDriveStrength(SPC_Type *base, spc_core_ldo_drive_strength_t driveStrength); + +/*! + * @brief Gets CORE LDO VDD Drive Strength for Low Power modes. + * + * @param base SPC peripheral base address. + * @return The CORE LDO's VDD Drive Strength. + */ +static inline spc_core_ldo_drive_strength_t SPC_GetLowPowerCoreLDOVDDDriveStrength(SPC_Type *base) +{ + return (spc_core_ldo_drive_strength_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_CORELDO_VDD_DS_MASK) >> + SPC_LP_CFG_CORELDO_VDD_DS_SHIFT); +} + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) && FSL_FEATURE_MCX_SPC_HAS_SYS_LDO) +/*! + * @name Low Level APIs To Set System LDO Regulator + * @{ + */ + +/*! + * @brief Enable/Disable System LDO regulator. + * + * @note The SYSTEM LDO enable bit is write-once. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable System LDO Regulator. + * true - Enable System LDO Regulator. + * false - Disable System LDO Regulator. + */ +static inline void SPC_EnableSystemLDORegulator(SPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTRL |= SPC_CNTRL_SYSLDO_EN_MASK; + } + else + { + /* + * $Branch Coverage Justification$ + * If SYSTEM_LDO is disabled, may cause some unexpected issues. + */ + base->CNTRL &= ~SPC_CNTRL_SYSLDO_EN_MASK; + } +} + +/*! + * @brief Enable/Disable current sink feature of System LDO Regulator. + * + * @param base SPC peripheral base address. + * @param sink Enable/Disable current sink feature. + * true - Enable current sink feature of System LDO Regulator. + * false - Disable current sink feature of System LDO Regulator. + */ +static inline void SPC_EnableSystemLDOSinkFeature(SPC_Type *base, bool sink) +{ + if (sink) + { + base->SYSLDO_CFG |= SPC_SYSLDO_CFG_ISINKEN_MASK; + } + else + { + base->SYSLDO_CFG &= ~SPC_SYSLDO_CFG_ISINKEN_MASK; + } +} + +/*! + * @brief Configs System LDO VDD Regulator in Active mode. + * + * @note If System LDO VDD Drive Strength is set to Normal, the Bandgap mode in Active mode must be programmed + * to a value that enables the bandgap. + * @note If any voltage detects are kept enabled, configuration to set System LDO VDD drive strength to low will + * be ignored. + * @note If select System LDO VDD Regulator voltage level to Over Drive Voltage, the Drive Strength of System LDO VDD + * Regulator must be set to Normal otherwise the regulator Drive Strength will be forced to Normal. + * @note If select System LDO VDD Regulator voltage level to Over Drive Voltage, the High voltage detect must be + * disabled. Otherwise it will be fail to regulator to Over Drive Voltage. + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_active_mode_sys_ldo_option_t structure. + * + * @retval #kStatus_Success Config System LDO regulator in Active power mode successful. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_BandgapModeWrong The bandgap is not enabled before invoking this function. + * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail HVD of System VDD is not disable before setting to Over Drive + * voltage. + * @retval kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set System LDO VDD regulator's driver strength to Low will be + * ignored. + */ +status_t SPC_SetActiveModeSystemLDORegulatorConfig(SPC_Type *base, const spc_active_mode_sys_ldo_option_t *option); + +/*! + * @brief Set System LDO Regulator voltage level in Active mode. + * + * @note The system LDO regulator can only operate at the overdrive voltage level for a limited amount of time for the + * life of chip. + * + * @param base SPC peripheral base address. + * @param voltageLevel Specify the voltage level of System LDO Regulator in Active mode. + * + * @retval #kStatus_Success Set System LDO Regulator voltage level in Active mode successfully. + * @retval #kStatus_SPC_SYSLDOOverDriveVoltageFail Must disable system LDO high voltage detector before specifing + * overdrive voltage. + */ +status_t SPC_SetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base, spc_sys_ldo_voltage_level_t voltageLevel); + +/*! + * @brief Get System LDO Regulator voltage level in Active mode. + * + * @param base SPC peripheral base address. + * @return System LDO Regulator voltage level in Active mode, please refer to @ref spc_sys_ldo_voltage_level_t. + */ +static inline spc_sys_ldo_voltage_level_t SPC_GetActiveModeSystemLDORegulatorVoltageLevel(SPC_Type *base) +{ + return (spc_sys_ldo_voltage_level_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_MASK) >> + SPC_ACTIVE_CFG_SYSLDO_VDD_LVL_SHIFT); +} + +/*! + * @brief Set System LDO Regulator Drive Strength in Active mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the drive strength of System LDO Regulator in Active mode. + * + * @retval #kStatus_Success Set System LDO Regulator drive strength in Active mode successfully. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any + voltage detect feature is enabled in active mode. + * @retval #kStatus_SPC_BandgapModeWrong Bandgap mode in Active mode must be programmed to a value that enables + the bandgap if attempt to specify normal drive strength. + */ +status_t SPC_SetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength); + +/*! + * @brief Get System LDO Regulator Drive Strength in Active mode. + * + * @param base SPC peripheral base address. + * @return System LDO regulator drive strength in Active mode, please refer to @ref spc_sys_ldo_drive_strength_t. + */ +static inline spc_sys_ldo_drive_strength_t SPC_GetActiveModeSystemLDORegulatorDriveStrength(SPC_Type *base) +{ + return (spc_sys_ldo_drive_strength_t)(uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK) >> + SPC_ACTIVE_CFG_SYSLDO_VDD_DS_SHIFT); +} + +/*! + * @brief Configs System LDO regulator in low power modes. + * + * This function configs System LDO regulator in low power modes. + * If System LDO VDD Regulator Drive strength is set to normal, bandgap mode in low power + * mode must be programmed to a value that enables the Bandgap. + * If any High voltage detectors or Low Voltage detectors are kept enabled, configuration + * to set System LDO Regulator drive strength as Low will be ignored. + * + * @param base SPC peripheral base address. + * @param option Pointer to spc_lowpower_mode_sys_ldo_option_t structure. + * + * @retval #kStatus_Success Config System LDO regulator in Low Power Mode successfully. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Set driver strength to low will be ignored. + */ +status_t SPC_SetLowPowerModeSystemLDORegulatorConfig(SPC_Type *base, const spc_lowpower_mode_sys_ldo_option_t *option); + +/*! + * @brief Set System LDO Regulator drive strength in Low Power Mode. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the drive strength of System LDO Regulator in Low Power Mode. + * + * @retval #kStatus_Success Set System LDO Regulator drive strength in Low Power Mode successfully. + * @retval #kStatus_SPC_SYSLDOLowDriveStrengthIgnore Attempt to specify low drive strength is ignored due to any + voltage detect feature is enabled in low power mode. + * @retval #kStatus_SPC_BandgapModeWrong Bandgap mode in low power mode must be programmed to a value that enables + the bandgap if attempt to specify normal drive strength. + */ +status_t SPC_SetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base, spc_sys_ldo_drive_strength_t driveStrength); + +/*! + * @brief Get System LDO Regulator drive strength in Low Power Mode. + * + * @param base SPC peripheral base address. + * @return System LDO regulator drive strength in Low Power Mode, please refer to @ref spc_sys_ldo_drive_strength_t. + */ +static inline spc_sys_ldo_drive_strength_t SPC_GetLowPowerModeSystemLDORegulatorDriveStrength(SPC_Type *base) +{ + return (spc_sys_ldo_drive_strength_t)(uint32_t)((base->LP_CFG & SPC_LP_CFG_SYSLDO_VDD_DS_MASK) >> + SPC_LP_CFG_SYSLDO_VDD_DS_SHIFT); +} +/*! @} */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_SYS_LDO */ + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC) && FSL_FEATURE_MCX_SPC_HAS_DCDC) +/*! + * @name Low Level APIs To Set DCDC Regulator + * @{ + */ + +/*! + * @brief Enable/Disable DCDC Regulator. + * + * @note The DCDC enable bit is write-once, settings only reset after a POR, LVD, or HVD event. + * + * @param base SPC peripheral base address. + * @param enable Enable/Disable DCDC Regulator. + * true - Enable DCDC Regulator. + * false - Disable DCDC Regulator. + */ +static inline void SPC_EnableDCDCRegulator(SPC_Type *base, bool enable) +{ + if (enable) + { + base->CNTRL |= SPC_CNTRL_DCDC_EN_MASK; + } + else + { + /* + * $Branch Coverage Justification$ + * If DCDC is disabled, all RAMs data will powered off. + */ + base->CNTRL &= ~SPC_CNTRL_DCDC_EN_MASK; + } +} + +/*! + * @brief Config DCDC Burst options + * + * @param base SPC peripheral base address. + * @param config Pointer to spc_dcdc_burst_config_t structure. + */ +void SPC_SetDCDCBurstConfig(SPC_Type *base, spc_dcdc_burst_config_t *config); + +/*! + * @brief Trigger a software burst request to DCDC. + * + * @param base SPC peripheral base address. + */ +static inline void SPC_TriggerDCDCBurstRequest(SPC_Type *base) +{ + /* Blocking until previous DCDC burst completed. */ + while ((base->DCDC_BURST_CFG & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) == 0UL) + { + } + + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_REQ_MASK; +} + +/*! + * @brief Check if burst acknowlege flag is asserted. + * + * @param base SPC peripheral base address. + * + * @retval false DCDC burst not complete. + * @retval true DCDC burst complete. + */ +static inline bool SPC_CheckDCDCBurstAck(SPC_Type *base) +{ + return ((base->DCDC_BURST_CFG & SPC_DCDC_BURST_CFG_BURST_ACK_MASK) != 0UL); +} + +/*! + * @brief Clear DCDC busrt acknowledge flag. + * + * @param base SPC periphral base address. + */ +static inline void SPC_ClearDCDCBurstAckFlag(SPC_Type *base) +{ + base->DCDC_BURST_CFG |= SPC_DCDC_BURST_CFG_BURST_ACK_MASK; +} + +/*! + * @brief Set the count value of the reference clock to configure the period of DCDC not active. + * + * @note This function is only useful when DCDC's drive strength is set as pulse refresh. + * @note The pulse duration(time between on and off) is: reference clock period * (count + 2). + * + * @param base SPC peripheral base address. + * @param count The count value, 16 bit width. + */ +void SPC_SetDCDCRefreshCount(SPC_Type *base, uint16_t count); + +#if (defined(FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN) && FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN) +/*! + * @brief Enable a bleed resistor to discharge DCDC output when DCDC is disabled. + * + * @param base SPC peripheral base address. + * @param enable Used to enable/disable bleed resistor. + */ +static inline void SPC_EnableDCDCBleedResistor(SPC_Type *base, bool enable) +{ + if (enable) + { + base->DCDC_CFG |= SPC_DCDC_CFG_BLEED_EN_MASK; + } + else + { + base->DCDC_CFG &= ~SPC_DCDC_CFG_BLEED_EN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN */ + +/*! + * @brief Configs DCDC_CORE Regulator in Active mode. + * + * @note When changing the DCDC output voltage level, take care to change the CORE LDO voltage level. + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_active_mode_dcdc_option_t structure. + * + * @retval #kStatus_Success Config DCDC regulator in Active power mode successful. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_BandgapModeWrong Set DCDC_CORE Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetActiveModeDCDCRegulatorConfig(SPC_Type *base, const spc_active_mode_dcdc_option_t *option); + +/*! + * @brief Set DCDC_CORE Regulator voltage level in Active mode. + * + * @note When changing the DCDC output voltage level, take care to change the CORE LDO voltage level. + * + * @param base SPC peripheral base address. + * @param voltageLevel Specify the DCDC_CORE Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t. + */ +static inline void SPC_SetActiveModeDCDCRegulatorVoltageLevel(SPC_Type *base, spc_dcdc_voltage_level_t voltageLevel) +{ + base->ACTIVE_CFG = + (base->ACTIVE_CFG & (~SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK)) | SPC_ACTIVE_CFG_DCDC_VDD_LVL(voltageLevel); +} + +/*! + * @brief Get DCDC_CORE Regulator voltage level in Active mode. + * + * @param base SPC peripheral base address. + * @return DCDC_CORE Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t. + */ +static inline spc_dcdc_voltage_level_t SPC_GetActiveModeDCDCRegulatorVoltageLevel(SPC_Type *base) +{ + return (spc_dcdc_voltage_level_t)((uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_LVL_MASK) >> + SPC_ACTIVE_CFG_DCDC_VDD_LVL_SHIFT)); +} + +/*! + * @brief Set DCDC_CORE Regulator drive strength in Active mode. + * + * @note To set DCDC drive strength as Normal, the bandgap must be enabled. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the DCDC_CORE regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + * + * @retval #kStatus_Success Set DCDC_CORE Regulator drive strength in Active mode successfully. + * @retval #kStatus_SPC_BandgapModeWrong Set DCDC_CORE Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength); + +/*! + * @brief Get DCDC_CORE Regulator drive strength in Active mode. + * + * @param base SPC peripheral base address. + * @return DCDC_CORE Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + */ +static inline spc_dcdc_drive_strength_t SPC_GetActiveModeDCDCRegulatorDriveStrength(SPC_Type *base) +{ + return (spc_dcdc_drive_strength_t)((uint32_t)((base->ACTIVE_CFG & SPC_ACTIVE_CFG_DCDC_VDD_DS_MASK) >> + SPC_ACTIVE_CFG_DCDC_VDD_DS_SHIFT)); +} + +/*! + * @brief Configs DCDC_CORE Regulator in Low power modes. + * + * @note If DCDC_CORE Drive Strength is set to Normal, the Bandgap mode in Low Power mode must be programmed + * to a value that enables the Bandgap. + * @note In Deep Power Down mode, DCDC regulator is always turned off. + * + * @param base SPC peripheral base address. + * @param option Pointer to the spc_lowpower_mode_dcdc_option_t structure. + * + * @retval #kStatus_Success Config DCDC regulator in low power mode successfully. + * @retval #kStatus_SPC_Busy The SPC instance is busy to execute any type of power mode transition. + * @retval #kStatus_SPC_BandgapModeWrong The bandgap mode setting in Low Power mode is wrong. + */ +status_t SPC_SetLowPowerModeDCDCRegulatorConfig(SPC_Type *base, const spc_lowpower_mode_dcdc_option_t *option); + +/*! + * @brief Set DCDC_CORE Regulator drive strength in Low power mode. + * + * @note To set drive strength as normal, the bandgap must be enabled. + * + * @param base SPC peripheral base address. + * @param driveStrength Specify the DCDC_CORE Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + * + * @retval #kStatus_Success Set DCDC_CORE Regulator drive strength in Low power mode successfully. + * @retval #kStatus_SPC_BandgapModeWrong Set DCDC_CORE Regulator drive strength to Normal, the Bandgap must be enabled. + */ +status_t SPC_SetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base, spc_dcdc_drive_strength_t driveStrength); + +/*! + * @brief Get DCDC_CORE Regulator drive strength in Low power mode. + * + * @param base SPC peripheral base address. + * @return DCDC_CORE Regulator drive strength, please refer to @ref spc_dcdc_drive_strength_t. + */ +static inline spc_dcdc_drive_strength_t SPC_GetLowPowerModeDCDCRegulatorDriveStrength(SPC_Type *base) +{ + return (spc_dcdc_drive_strength_t)((uint32_t)((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_DS_MASK) >> + SPC_LP_CFG_DCDC_VDD_DS_SHIFT)); +} + +/*! + * @brief Set DCDC_CORE Regulator voltage level in Low power mode. + * + * @note To change DCDC level in Low-Power mode: + * 1. Configure LP_CFG[DCDC_VDD_LVL] to desired level; + * 2. Configure LP_CFG[DCDC_VDD_DS] to low driver strength; + * 3. Configure ACTIVE_CFG[DCDC_VDD_LVL] to same level programmed in #1. + * + * @note After invoking this function, the voltage level in active mode(wakeup from low power modes) also changed, + * if it is necessary, please invoke SPC_SetActiveModeDCDCRegulatorVoltageLevel() to change to desried voltage level. + * + * @param base SPC peripheral base address. + * @param voltageLevel Specify the DCDC_CORE Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t. + */ +static inline void SPC_SetLowPowerModeDCDCRegulatorVoltageLevel(SPC_Type *base, spc_dcdc_voltage_level_t voltageLevel) +{ + base->LP_CFG = (base->LP_CFG & (~SPC_LP_CFG_DCDC_VDD_LVL_MASK)) | SPC_LP_CFG_DCDC_VDD_LVL(voltageLevel); + (void)SPC_SetLowPowerModeDCDCRegulatorDriveStrength(base, kSPC_DCDC_LowDriveStrength); + SPC_SetActiveModeDCDCRegulatorVoltageLevel(base, voltageLevel); +} + +/*! + * @brief Get DCDC_CORE Regulator voltage level in Low power mode. + * + * @param base SPC peripheral base address. + * @return DCDC_CORE Regulator voltage level, please refer to @ref spc_dcdc_voltage_level_t. + */ +static inline spc_dcdc_voltage_level_t SPC_GetLowPowerModeDCDCRegulatorVoltageLevel(SPC_Type *base) +{ + return (spc_dcdc_voltage_level_t)((uint32_t)((base->LP_CFG & SPC_LP_CFG_DCDC_VDD_LVL_MASK) >> + SPC_LP_CFG_DCDC_VDD_LVL_SHIFT)); +} + +/*! @} */ +#endif /* FSL_FEATURE_MCX_SPC_HAS_DCDC */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* FSL_SPC_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_trdc.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_trdc.c new file mode 100644 index 00000000000..b94abe1afbc --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_trdc.c @@ -0,0 +1,854 @@ +/* + * Copyright 2022-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_trdc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.trdc1" +#endif + +/* The memory increment definition in byte of MBC and MRC configuration registers */ +#define TRDC_MRC_DOMAIN_INCREMENT 0x100UL +#define TRDC_MBC_DOMAIN_INCREMENT 0x200UL +/* In latest TRDC register definition this macro has been removed from device header file. Add this for backward + * compatability. */ +#ifndef TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL +#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL(x) ((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT)) +#endif +/* Get the memory increment in for each slave inside MBC */ +#define TRDC_MBC_SLAVE_INCREMENT(x) \ + (((x) == 0U) ? (0U) : (((x) == 1U) ? (0x140UL) : (((x) == 2U) ? (0x168UL) : (0x190UL)))) + +typedef union +{ +#if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT) && FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT + trdc_processor_domain_assignment_t _processor_domain_assignment; + trdc_non_processor_domain_assignment_t _non_processor_domain_assignment; + trdc_pid_config_t _pid_config; +#endif +#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG + trdc_idau_config_t _idau_config; +#endif +#if (defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC) || \ + (defined(FSL_FEATURE_TRDC_HAS_MRC) && FSL_FEATURE_TRDC_HAS_MRC) + trdc_memory_access_control_config_t _memory_access_control; +#endif +#if defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC + trdc_mbc_memory_block_config_t _mbc_memory_blk; + trdc_mbc_nse_update_config_t _mbc_nse_update; +#endif + uint32_t _u32; +} trdc_reg32_convert_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG +/*! + * brief Gets the TRDC hardware configuration. + * + * This function gets the TRDC hardware configurations, including number of bus + * masters, number of domains, number of MRCs and number of PACs. + * + * param base TRDC peripheral base address. + * param config Pointer to the structure to get the configuration. + */ +void TRDC_GetHardwareConfig(TRDC_Type *base, trdc_hardware_config_t *config) +{ + assert(NULL != config); + + config->masterNumber = + (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMSTR_MASK) >> TRDC_TRDC_HWCFG0_NMSTR_SHIFT); + config->domainNumber = + (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NDID_MASK) >> TRDC_TRDC_HWCFG0_NDID_SHIFT); + config->mbcNumber = + (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMBC_MASK) >> TRDC_TRDC_HWCFG0_NMBC_SHIFT); + config->mrcNumber = + (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMRC_MASK) >> TRDC_TRDC_HWCFG0_NMRC_SHIFT); +} +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC +/*! + * brief Gets the hardware configuration of the one of two slave memories within each MBC(memory block checker). + * + * param base TRDC peripheral base address. + * param config Pointer to the structure to get the configuration. + * param mbcIdx MBC number. + * param slvIdx Slave number. + */ +void TRDC_GetMbcHardwareConfig(TRDC_Type *base, + trdc_slave_memory_hardware_config_t *config, + uint8_t mbcIdx, + uint8_t slvIdx) +{ + assert(NULL != config); +#if defined(TRDC_MBC_COUNT) && TRDC_MBC_COUNT + assert(mbcIdx < (uint8_t)TRDC_MBC_COUNT); +#else + assert(mbcIdx < (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMBC_MASK) >> + TRDC_TRDC_HWCFG0_NMBC_SHIFT)); +#endif + assert(slvIdx < 4U); + + config->blockNum = TRDC_MBC_BASE(base, mbcIdx)->MBC_MEM_GLBCFG[slvIdx] & TRDC_MBC_MEM_GLBCFG_NBLKS_MASK; + config->blockSize = (TRDC_MBC_BASE(base, mbcIdx)->MBC_MEM_GLBCFG[slvIdx] & TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_MASK) >> + TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT; +} +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT) && FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT +/*! + * brief Gets the default master domain assignment for the processor bus master. + * + * This function gets the default master domain assignment for the processor bus master. + * It should only be used for the processor bus masters, such as CORE0. This function + * sets the assignment as follows: + * + * code + * assignment->domainId = 0U; + * assignment->domainIdSelect = kTRDC_DidMda; + * assignment->lock = 0U; + * endcode + * + * param domainAssignment Pointer to the assignment structure. + */ +void TRDC_GetDefaultProcessorDomainAssignment(trdc_processor_domain_assignment_t *domainAssignment) +{ + assert(NULL != domainAssignment); + + /* Initializes the configure structure to zero. */ + (void)memset(domainAssignment, 0, sizeof(*domainAssignment)); +} + +/*! + * brief Gets the default master domain assignment for non-processor bus master. + * + * This function gets the default master domain assignment for non-processor bus master. + * It should only be used for the non-processor bus masters, such as DMA. This function + * sets the assignment as follows: + * + * code + * assignment->domainId = 0U; + * assignment->privilegeAttr = kTRDC_ForceUser; + * assignment->secureAttr = kTRDC_ForceSecure; + * assignment->bypassDomainId = 0U; + * assignment->lock = 0U; + * endcode + * + * param domainAssignment Pointer to the assignment structure. + */ +void TRDC_GetDefaultNonProcessorDomainAssignment(trdc_non_processor_domain_assignment_t *domainAssignment) +{ + assert(NULL != domainAssignment); + + /* Initializes the configure structure to zero. */ + (void)memset(domainAssignment, 0, sizeof(*domainAssignment)); +} + +/*! + * brief Sets the processor bus master domain assignment. + * + * This function sets the processor master domain assignment as valid. + * One bus master might have multiple domain assignment registers. The parameter + * \p assignIndex specifies which assignment register to set. + * + * Example: Set domain assignment for core 0. + * + * code + * trdc_processor_domain_assignment_t processorAssignment; + * + * TRDC_GetDefaultProcessorDomainAssignment(&processorAssignment); + * + * processorAssignment.domainId = 0; + * processorAssignment.xxx = xxx; + * TRDC_SetMasterDomainAssignment(TRDC, 1, &processorAssignment); + * endcode + * + * param base TRDC peripheral base address. + * param master Which master to configure, refer to trdcx_master_t in processor header file, x is trdc instance. + * param regNum Which register to configure, processor master can have more than one register for the MDAC + * configuration. param domainAssignment Pointer to the assignment structure. + */ +void TRDC_SetProcessorDomainAssignment(TRDC_Type *base, + uint8_t master, + uint8_t regNum, + const trdc_processor_domain_assignment_t *domainAssignment) +{ + /* Make sure the master number does not exceed the max master count. */ + assert(master < + ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMSTR_MASK) >> TRDC_TRDC_HWCFG0_NMSTR_SHIFT)); + /* Make sure the master is a processor master. */ + assert(0U == (TRDC_GENERAL_BASE(base)->DACFG[master] & TRDC_DACFG_NCM_MASK)); + assert(NULL != domainAssignment); + assert(domainAssignment->domainId < + ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NDID_MASK) >> TRDC_TRDC_HWCFG0_NDID_SHIFT)); + + trdc_reg32_convert_t pid; + pid._processor_domain_assignment = *domainAssignment; + TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT0[master].MDA_W_DFMT0[regNum] = pid._u32 | TRDC_MDA_W_DFMT0_VLD_MASK; +} + +/*! + * brief Sets the non-processor bus master domain assignment. + * + * This function sets the non-processor master domain assignment as valid. + * One bus master might have multiple domain assignment registers. The parameter + * \p assignIndex specifies which assignment register to set. + * + * Example: Set domain assignment for DMA0. + * code + * trdc_non_processor_domain_assignment_t nonProcessorAssignment; + * + * TRDC_GetDefaultNonProcessorDomainAssignment(&nonProcessorAssignment); + * nonProcessorAssignment.domainId = 1; + * nonProcessorAssignment.xxx = xxx; + * + * TRDC_SetMasterDomainAssignment(TRDC, kTrdcMasterDma0, 0U, &nonProcessorAssignment); + * endcode + * + * param base TRDC peripheral base address. + * param master Which master to configure, refer to trdc_master_t in processor header file. + * param domainAssignment Pointer to the assignment structure. + */ +void TRDC_SetNonProcessorDomainAssignment(TRDC_Type *base, + uint8_t master, + const trdc_non_processor_domain_assignment_t *domainAssignment) +{ + /* The master number should be less than the master count. */ + assert(master < + ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMSTR_MASK) >> TRDC_TRDC_HWCFG0_NMSTR_SHIFT)); + /* Make sure the master is a non-CPU/non-processor master */ + assert(0U != (TRDC_GENERAL_BASE(base)->DACFG[master] & TRDC_DACFG_NCM_MASK)); + assert(NULL != domainAssignment); + assert(domainAssignment->domainId < + ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NDID_MASK) >> TRDC_TRDC_HWCFG0_NDID_SHIFT)); + + trdc_reg32_convert_t pid; + pid._non_processor_domain_assignment = *domainAssignment; + + TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT1[master].MDA_W_DFMT1[0] = pid._u32 | TRDC_MDA_W_DFMT1_VLD_MASK; +} + +/*! + * brief Sets the current Process identifier(PID) for processor core. + * + * Each processor has a corresponding process identifier (PID) which can be used to group tasks into different domains. + * Secure privileged software saves and restores the PID as part of any context switch. + * This data structure defines an array of 32-bit values, one per MDA module, that define the PID. Since this register + * resource is only applicable to processor cores, the data structure is typically sparsely populated. The HWCFG[2-3] + * registers provide a bitmap of the implemented PIDn registers. This data structure is indexed using the corresponding + * MDA instance number. Depending on the operating clock domain of each DAC instance, there may be optional information + * stored in the corresponding PIDm register to properly implement the LK2 = 2 functionality. + * + * param base TRDC peripheral base address. + * param master Which processor master to configure, refer to trdc_master_t in processor header file. + * param pidConfig Pointer to the configuration structure. + */ +void TRDC_SetPid(TRDC_Type *base, uint8_t master, const trdc_pid_config_t *pidConfig) +{ + assert(pidConfig != NULL); + /* The master number should be less than the master count. */ + assert(master < + ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMSTR_MASK) >> TRDC_TRDC_HWCFG0_NMSTR_SHIFT)); + /* This master has to be a processor master. */ + assert((TRDC_GENERAL_BASE(base)->DACFG[master] & TRDC_DACFG_NCM_MASK) == 0U); + + trdc_reg32_convert_t pid; + pid._pid_config = *pidConfig; + TRDC_DOMAIN_ASSIGNMENT_BASE(base)->PID[master] = pid._u32; +} +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG +/*! + * brief Gets the default IDAU(Implementation-Defined Attribution Unit) configuration. + * + * code + * config->lockSecureVTOR = false; + * config->lockNonsecureVTOR = false; + * config->lockSecureMPU = false; + * config->lockNonsecureMPU = false; + * config->lockSAU = false; + * endcode + * + * param domainAssignment Pointer to the configuration structure. + */ +void TRDC_GetDefaultIDAUConfig(trdc_idau_config_t *idauConfiguration) +{ + assert(NULL != idauConfiguration); + + /* Initializes the configure structure to zero. */ + (void)memset(idauConfiguration, 0, sizeof(*idauConfiguration)); +} + +/*! + * brief Sets the IDAU(Implementation-Defined Attribution Unit) control configuration. + * + * Example: Lock the secure and non-secure MPU registers. + * + * code + * trdc_idau_config_t idauConfiguration; + * + * TRDC_GetDefaultIDAUConfig(&idauConfiguration); + * + * idauConfiguration.lockSecureMPU = true; + * idauConfiguration.lockNonsecureMPU = true; + * TRDC_SetIDAU(TRDC, &idauConfiguration); + * endcode + * + * param base TRDC peripheral base address. + * param domainAssignment Pointer to the configuration structure. + */ +void TRDC_SetIDAU(TRDC_Type *base, const trdc_idau_config_t *idauConfiguration) +{ + assert(NULL != idauConfiguration); + + trdc_reg32_convert_t pid; + pid._idau_config = *idauConfiguration; + + TRDC_GENERAL_BASE(base)->TRDC_IDAU_CR = pid._u32 | TRDC_TRDC_IDAU_CR_VLD_MASK; +} +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_FLW) && FSL_FEATURE_TRDC_HAS_FLW +/*! + * brief Gets the default FLW(Flsh Logical Window) configuration. + * + * code + * config->blockCount = false; + * config->arrayBaseAddr = false; + * config->lock = false; + * config->enable = false; + * endcode + * + * param flwConfiguration Pointer to the configuration structure. + */ +void TRDC_GetDefaultFlashLogicalWindowConfig(trdc_flw_config_t *flwConfiguration) +{ + assert(NULL != flwConfiguration); + + /* Initializes the configure structure to zero. */ + (void)memset(flwConfiguration, 0, sizeof(*flwConfiguration)); + + flwConfiguration->enable = 0x1UL; +} + +/*! + * brief Sets the FLW function's configuration. + * + * code + * trdc_flw_config_t flwConfiguration; + * + * TRDC_GetDefaultIDAUConfig(&flwConfiguration); + * + * flwConfiguration.blockCount = 32U; + * flwConfiguration.arrayBaseAddr = 0xXXXXXXXX; + * TRDC_SetIDAU(TRDC, &flwConfiguration); + * endcode + * + * param base TRDC peripheral base address. + * param flwConfiguration Pointer to the configuration structure. + */ +void TRDC_SetFlashLogicalWindow(TRDC_Type *base, const trdc_flw_config_t *flwConfiguration) +{ + assert(NULL != flwConfiguration); + + TRDC_FLW_BASE(base)->TRDC_FLW_ABASE = flwConfiguration->arrayBaseAddr; + TRDC_FLW_BASE(base)->TRDC_FLW_BCNT = flwConfiguration->blockCount; + TRDC_FLW_BASE(base)->TRDC_FLW_CTL = + TRDC_TRDC_FLW_CTL_V(flwConfiguration->enable) | TRDC_TRDC_FLW_CTL_LK(flwConfiguration->lock); +} +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR) && FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR +#if (((__CORTEX_M == 0U) && (defined(__ICCARM__))) || (defined(__XTENSA__))) +/*! + * @brief Count the leading zeros. + * + * Count the leading zeros of an 32-bit data. This function is only defined + * for CM0 and CM0+ for IAR, because other cortex series have the clz instruction, + * KEIL and ARMGCC have toolchain build in function for this purpose. + * + * @param data The data to process. + * @return Count of the leading zeros. + */ +static uint8_t TRDC_CountLeadingZeros(uint32_t data) +{ + uint8_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count++; + mask >>= 1U; + } + + return count; +} +#endif +#endif + +/*! + * brief Initializes the TRDC module. + * + * This function enables the TRDC clock. + * + * param base TRDC peripheral base address. + */ +void TRDC_Init(TRDC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief De-initializes the TRDC module. + * + * This function disables the TRDC clock. + * + * param base TRDC peripheral base address. + */ +void TRDC_Deinit(TRDC_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +#if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR) && FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR +/*! + * brief Gets and clears the first domain error of the current domain. + * + * This function gets the first access violation information for the current domain + * and clears the pending flag. There might be multiple access violations pending + * for the current domain. This function only processes the first error. + * + * param base TRDC peripheral base address. + * param error Pointer to the error information. + * return If the access violation is captured, this function returns the kStatus_Success. + * The error information can be obtained from the parameter error. If no + * access violation is captured, this function returns the kStatus_NoData. + */ +status_t TRDC_GetAndClearFirstDomainError(TRDC_Type *base, trdc_domain_error_t *error) +{ + return TRDC_GetAndClearFirstSpecificDomainError(base, error, TRDC_GetCurrentMasterDomainId(base)); +} + +/*! + * brief Gets and clears the first domain error of the specific domain. + * + * This function gets the first access violation information for the specific domain + * and clears the pending flag. There might be multiple access violations pending + * for the current domain. This function only processes the first error. + * + * param base TRDC peripheral base address. + * param error Pointer to the error information. + * param domainId The error of which domain to get and clear. + * return If the access violation is captured, this function returns the kStatus_Success. + * The error information can be obtained from the parameter error. If no + * access violation is captured, this function returns the kStatus_NoData. + */ +status_t TRDC_GetAndClearFirstSpecificDomainError(TRDC_Type *base, trdc_domain_error_t *error, uint8_t domainId) +{ + assert(NULL != error); + + status_t status; + uint8_t errorIndex; /* The index of first domain error. */ + uint32_t errorBitMap; /* Domain error location bit map. */ + uint32_t regW1; /* To save TRDC_DERR_W1. */ + + /* Get the error bitmap. */ + errorBitMap = TRDC_DOMAIN_ERROR_BASE(base)->TRDC_DERRLOC[domainId]; + + if (0U == errorBitMap) /* No error captured. */ + { + status = kStatus_NoData; + } + else + { + /* Get the first error controller index. */ +#if (((__CORTEX_M == 0U) && (defined(__ICCARM__))) || (defined(__XTENSA__))) + errorIndex = 31U - TRDC_CountLeadingZeros(errorBitMap); +#else + errorIndex = 31U - __CLZ(errorBitMap); +#endif + + /* Must write TRDC_FDID[TRDC_FDID] with the domain ID before reading the Domain Error registers. */ + TRDC_DOMAIN_ERROR_BASE(base)->TRDC_FDID = TRDC_TRDC_FDID_FDID(domainId); + + /* Initializes the error structure to zero. */ + (void)memset(error, 0, sizeof(*error)); + + if (errorIndex > 15U) + { + /* Error in Memory Region Checker (MRC) */ + errorIndex -= 12U; + error->controller = (trdc_controller_t)errorIndex; + errorIndex -= 4U; + + /* Get the error information. */ + regW1 = TRDC_DOMAIN_ERROR_BASE(base)->MRC_DERR[errorIndex].W1; + error->address = TRDC_DOMAIN_ERROR_BASE(base)->MRC_DERR[errorIndex].W0; + /* Clear error pending. */ + TRDC_DOMAIN_ERROR_BASE(base)->MRC_DERR[errorIndex].W3 = TRDC_W3_RECR(0x01U); + } + else + { + /* Error in Memory Block Controller (MBC) */ + error->slaveMemoryIdx = errorIndex % 4U; + errorIndex /= 4U; + error->controller = (trdc_controller_t)errorIndex; + + /* Check if the MBC error index exceeds the module's max MBC index to avoid overrun access. */ + if (errorIndex >= + ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMBC_MASK) >> TRDC_TRDC_HWCFG0_NMBC_SHIFT)) + { + return kStatus_Fail; + } + + error->controller = (trdc_controller_t)errorIndex; + + /* Get the error information. */ + regW1 = TRDC_DOMAIN_ERROR_BASE(base)->MBC_DERR[errorIndex].W1; + error->address = TRDC_DOMAIN_ERROR_BASE(base)->MBC_DERR[errorIndex].W0; + /* Clear error pending. */ + TRDC_DOMAIN_ERROR_BASE(base)->MBC_DERR[errorIndex].W3 = TRDC_W3_RECR(0x01U); + } + + uint8_t tempVal = 0U; + error->domainId = (uint8_t)((regW1 & TRDC_W1_EDID_MASK) >> TRDC_W1_EDID_MASK); + tempVal = (uint8_t)((regW1 & TRDC_W1_EATR_MASK) >> TRDC_W1_EATR_SHIFT); + error->errorAttr = (trdc_error_attr_t)tempVal; + tempVal = (uint8_t)((regW1 & TRDC_W1_ERW_MASK) >> TRDC_W1_ERW_SHIFT); + error->errorType = (trdc_error_type_t)tempVal; + error->errorPort = (uint8_t)((regW1 & TRDC_W1_EPORT_MASK) >> TRDC_W1_EPORT_SHIFT); + tempVal = (uint8_t)((regW1 & TRDC_W1_EST_MASK) >> TRDC_W1_EST_SHIFT); + error->errorState = (trdc_error_state_t)tempVal; + + status = kStatus_Success; + } + + return status; +} +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_MRC) && FSL_FEATURE_TRDC_HAS_MRC +/*! + * brief Sets the memory access configuration for one of the access control register of one MRC. + * + * Example: Enable the secure operations and lock the configuration for MRC0 region 1. + * + * code + * trdc_memory_access_control_config_t config; + * + * config.securePrivX = true; + * config.securePrivW = true; + * config.securePrivR = true; + * config.lock = true; + * TRDC_SetMrcMemoryAccess(TRDC, &config, 0, 1); + * endcode + * + * param base TRDC peripheral base address. + * param config Pointer to the configuration structure. + * param mrcIdx MRC index. + * param regIdx Register number. + */ +void TRDC_MrcSetMemoryAccessConfig(TRDC_Type *base, + const trdc_memory_access_control_config_t *config, + uint8_t mrcIdx, + uint8_t regIdx) +{ + assert(NULL != base); + assert(NULL != config); + + trdc_reg32_convert_t pid; + + pid._memory_access_control = *config; + TRDC_MRC_BASE(base, mrcIdx)->MRC_GLBAC[regIdx] = pid._u32; +} + +/*! + * brief Enables the update of the selected domians. + * + * After the domians' update are enabled, their regions' NSE bits can be set or clear. + * + * param base TRDC peripheral base address. + * param mrcIdx MRC index. + * param domianMask Bit mask of the domains to be enabled. + * param enable True to enable, false to disable. + */ +void TRDC_MrcEnableDomainNseUpdate(TRDC_Type *base, uint8_t mrcIdx, uint16_t domianMask, bool enable) +{ + assert(NULL != base); + + if (enable) + { + TRDC_MRC_BASE(base, mrcIdx)->MRC_NSE_RGN_INDIRECT |= ((uint32_t)domianMask << 16U); + } + else + { + TRDC_MRC_BASE(base, mrcIdx)->MRC_NSE_RGN_INDIRECT &= ~((uint32_t)domianMask << 16U); + } +} + +/*! + * brief Sets the NSE bits of the selected regions for domains. + * + * This function sets the NSE bits for the selected regions for the domains whose update are enabled. + * + * param base TRDC peripheral base address. + * param mrcIdx MRC index. + * param regionMask Bit mask of the regions whose NSE bits to set. + */ +void TRDC_MrcRegionNseSet(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask) +{ + assert(NULL != base); + + TRDC_MRC_BASE(base, mrcIdx)->MRC_NSE_RGN_SET = ((uint32_t)regionMask); +} + +/*! + * brief Clears the NSE bits of the selected regions for domains. + * + * This function clears the NSE bits for the selected regions for the domains whose update are enabled. + * + * param base TRDC peripheral base address. + * param mrcIdx MRC index. + * param regionMask Bit mask of the regions whose NSE bits to clear. + */ +void TRDC_MrcRegionNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask) +{ + assert(NULL != base); + + TRDC_MRC_BASE(base, mrcIdx)->MRC_NSE_RGN_CLR = ((uint32_t)regionMask); +} + +/*! + * brief Clears the NSE bits for all the regions of the selected domains. + * + * This function clears the NSE bits for all regions of selected domains whose update are enabled. + * + * param base TRDC peripheral base address. + * param mrcIdx MRC index. + * param domainMask Bit mask of the domians whose NSE bits to clear. + */ +void TRDC_MrcDomainNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t domainMask) +{ + assert(NULL != base); + + uint8_t domainCount = + (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NDID_MASK) >> TRDC_TRDC_HWCFG0_NDID_SHIFT); + uint8_t maxDomainId = 0U; + uint16_t tmpDomainMask = domainMask; + + while (tmpDomainMask != 0U) + { + tmpDomainMask >>= 1U; + maxDomainId++; + } + + /* Check whether the domain mask contains invalid domain. */ + if (maxDomainId > domainCount) + { + assert(false); + } + + TRDC_MRC_BASE(base, mrcIdx)->MRC_NSE_RGN_CLR_ALL = ((uint32_t)domainMask << 16U); +} + +/*! + * brief Sets the configuration for one of the region descriptor per domain per MRC instnce. + * + * This function sets the configuration for one of the region descriptor, including the start + * and end address of the region, memory access control policy and valid. + * + * param base TRDC peripheral base address. + * param config Pointer to region descriptor configuration structure. + */ +void TRDC_MrcSetRegionDescriptorConfig(TRDC_Type *base, const trdc_mrc_region_descriptor_config_t *config) +{ + assert(NULL != base); + + uint32_t regAddr = (uint32_t) & (TRDC_MRC_BASE(base, config->mrcIdx)->MRC_DOM0_RGD_W[config->regionIdx][0]); + + regAddr += TRDC_MRC_DOMAIN_INCREMENT * config->domainIdx; + + /* Set configuration for word 0 */ + uint32_t data = TRDC_MRC_DOM0_RGD_W_MRACSEL(config->memoryAccessControlSelect) | + ((config->startAddr) & ~(TRDC_MRC_DOM0_RGD_W_MRACSEL_MASK)); + *(uint32_t *)regAddr = data; + + /* Set configuration for word 1 */ + regAddr += 4U; + data = TRDC_MRC_DOM0_RGD_W_VLD(config->valid) | TRDC_MRC_DOM0_RGD_W_NSE(config->nseEnable) | + ((config->endAddr) & ~(TRDC_MRC_DOM0_RGD_W_VLD_MASK | TRDC_MRC_DOM0_RGD_W_NSE_MASK)); + *(uint32_t *)regAddr = data; +} +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC +/*! + * brief Sets the NSR update configuration for one of the MBC instance. + * + * After set the NSE configuration, the configured memory area can be updateby NSE set/clear. + * + * param base TRDC peripheral base address. + * param config Pointer to NSE update configuration structure. + * param mbcIdx MBC index. + */ +void TRDC_MbcSetNseUpdateConfig(TRDC_Type *base, const trdc_mbc_nse_update_config_t *config, uint8_t mbcIdx) +{ + assert(base != NULL); + + trdc_reg32_convert_t pid; + + pid._mbc_nse_update = *config; + TRDC_MBC_BASE(base, mbcIdx)->MBC_NSE_BLK_INDEX = pid._u32; +} + +/*! + * brief Sets the NSE bits of the selected configuration words according to NSE update configuration. + * + * This function sets the NSE bits of the word for the configured regio, memory. + * + * param base TRDC peripheral base address. + * param mbcIdx MBC index. + * param bitMask Mask of the bits whose NSE bits to set. + */ +void TRDC_MbcWordNseSet(TRDC_Type *base, uint8_t mbcIdx, uint32_t bitMask) +{ + assert(NULL != base); + + TRDC_MBC_BASE(base, mbcIdx)->MBC_NSE_BLK_SET = ((uint32_t)bitMask); +} + +/*! + * brief Clears the NSE bits of the selected configuration words according to NSE update configuration. + * + * This function sets the NSE bits of the word for the configured regio, memory. + * + * param base TRDC peripheral base address. + * param mbcIdx MBC index. + * param bitMask Mask of the bits whose NSE bits to clear. + */ +void TRDC_MbcWordNseClear(TRDC_Type *base, uint8_t mbcIdx, uint32_t bitMask) +{ + assert(NULL != base); + + TRDC_MBC_BASE(base, mbcIdx)->MBC_NSE_BLK_CLR = ((uint32_t)bitMask); +} + +/*! + * brief Clears all configuration words' NSE bits of the selected domain and memory. + * + * param base TRDC peripheral base address. + * param mbcIdx MBC index. + * param domainMask Mask of the domains whose NSE bits to clear, 0b110 means clear domain 1&2. + * param slaveMask Mask of the slaves whose NSE bits to clear, 0x11 means clear all slave 0&1's NSE bits. + */ +void TRDC_MbcNseClearAll(TRDC_Type *base, uint8_t mbcIdx, uint16_t domainMask, uint8_t slave) +{ + assert(NULL != base); + +#if defined(FSL_FEATURE_TRDC_DOMAIN_COUNT) && FSL_FEATURE_TRDC_DOMAIN_COUNT + uint8_t dmainCount = FSL_FEATURE_TRDC_DOMAIN_COUNT; +#else + uint8_t dmainCount = + (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NDID_MASK) >> TRDC_TRDC_HWCFG0_NDID_SHIFT); +#endif + uint8_t maxDomainId = 0U; + uint16_t tmpDomainMask = domainMask; + + while (tmpDomainMask != 0U) + { + tmpDomainMask >>= 1U; + maxDomainId++; + } + + if (maxDomainId > dmainCount) + { + assert(false); + } + + TRDC_MBC_BASE(base, mbcIdx)->MBC_NSE_BLK_CLR_ALL = + TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL(domainMask) | TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL(slave); +} + +/*! + * brief Sets the memory access configuration for one of the region descriptor of one MBC. + * + * Example: Enable the secure operations and lock the configuration for MRC0 region 1. + * + * code + * trdc_memory_access_control_config_t config; + * + * config.securePrivX = true; + * config.securePrivW = true; + * config.securePrivR = true; + * config.lock = true; + * TRDC_SetMbcMemoryAccess(TRDC, &config, 0, 1); + * endcode + * + * param base TRDC peripheral base address. + * param config Pointer to the configuration structure. + * param mbcIdx MBC index. + * param rgdIdx Region descriptor number. + */ +void TRDC_MbcSetMemoryAccessConfig(TRDC_Type *base, + const trdc_memory_access_control_config_t *config, + uint8_t mbcIdx, + uint8_t rgdIdx) +{ + assert(NULL != base); + assert(NULL != config); + + trdc_reg32_convert_t pid; + + pid._memory_access_control = *config; + TRDC_MBC_BASE(base, mbcIdx)->MBC_MEMN_GLBAC[rgdIdx] = pid._u32; +} + +/*! + * brief Sets the configuration for one of the memory block per domain per MBC instnce. + * + * This function sets the configuration for one of the memory block, including the memory access + * control policy and nse enable. + * + * param base TRDC peripheral base address. + * param config Pointer to memory block configuration structure. + */ +void TRDC_MbcSetMemoryBlockConfig(TRDC_Type *base, const trdc_mbc_memory_block_config_t *config) +{ + assert(NULL != base); + + uint32_t shift = 4UL * (config->memoryBlockIdx % 8UL); + uint32_t regAddr = (uint32_t) & (TRDC_MBC_BASE(base, config->mbcIdx)->MBC_DOM0_MEM0_BLK_CFG_W[0]); + uint32_t configWord = 0U; + trdc_reg32_convert_t pid; + + pid._mbc_memory_blk = *config; + configWord = (pid._u32 & 0xFU) << shift; + + regAddr += (TRDC_MBC_DOMAIN_INCREMENT * config->domainIdx + TRDC_MBC_SLAVE_INCREMENT(config->slaveMemoryIdx)) + + ((uint32_t)config->memoryBlockIdx / 8U) * sizeof(uint32_t); + configWord = configWord | (*(uint32_t *)regAddr & ~(0xFUL << shift)); + *(uint32_t *)regAddr = configWord; +} +#endif diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_trdc.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_trdc.h new file mode 100644 index 00000000000..68d29530882 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_trdc.h @@ -0,0 +1,1131 @@ +/* + * Copyright 2022-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_TRDC_H_ +#define FSL_TRDC_H_ + +#include "fsl_common.h" +#include "fsl_trdc_core.h" + +/*! + * @addtogroup trdc + * @{ + */ + +/****************************************************************************** + * Definitions + *****************************************************************************/ +#define FSL_TRDC_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) + +#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG +/* Hardware configuration definitions */ +/*! + * @brief TRDC hardware configuration. + */ +typedef struct _trdc_hardware_config +{ + uint8_t masterNumber; /*!< Number of bus masters. */ + uint8_t domainNumber; /*!< Number of domains. */ + uint8_t mbcNumber; /*!< Number of MBCs. */ + uint8_t mrcNumber; /*!< Number of MRCs. */ +} trdc_hardware_config_t; +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC +/*! + * @brief Hardware configuration of the two slave memories within each MBC(memory block checker). + */ +typedef struct _trdc_slave_memory_hardware_config +{ + uint32_t blockNum; /*!< Number of blocks. */ + uint32_t blockSize; /*!< Block size. */ +} trdc_slave_memory_hardware_config_t; +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT) && FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT +/* Master domain assignment definitions */ +/*! + * @brief TRDC domain ID select method, the register bit TRDC_MDA_W0_0_DFMT0[DIDS], used for + * domain hit evaluation. + */ +typedef enum _trdc_did_sel +{ + kTRDC_DidMda, /*!< Use MDAn[2:0] as DID. */ + kTRDC_DidInput, /*!< Use the input DID (DID_in) as DID. */ + kTRDC_DidMdaAndInput, /*!< Use MDAn[2] concatenated with DID_in[1:0] as DID. */ + kTRDC_DidReserved /*!< Reserved. */ +} trdc_did_sel_t; + +/*! + * @brief TRDC secure attribute, the register bit TRDC_MDA_W0_0_DFMT0[SA], used for + * bus master domain assignment. + */ +typedef enum _trdc_secure_attr +{ + kTRDC_ForceSecure, /*!< Force the bus attribute for this master to secure. */ + kTRDC_ForceNonSecure, /*!< Force the bus attribute for this master to non-secure. */ + kTRDC_MasterSecure, /*!< Use the bus master's secure/nonsecure attribute directly. */ + kTRDC_MasterSecure1, /*!< Use the bus master's secure/nonsecure attribute directly. */ +} trdc_secure_attr_t; + +/*! + * @brief The configuration of domain hit evaluation of PID. + */ +typedef enum _trdc_pid_domain_hit_config +{ + kTRDC_pidDomainHitNone0, /*!< No PID is included in the domain hit evaluation. */ + kTRDC_pidDomainHitNone1, /*!< No PID is included in the domain hit evaluation. */ + kTRDC_pidDomainHitInclusive, /*!< The PID is included in the domain hit evaluation when (PID & ~PIDM). */ + kTRDC_pidDomainHitExclusive, /*!< The PID is included in the domain hit evaluation when ~(PID & ~PIDM). */ +} trdc_pid_domain_hit_config_t; + +/*! + * @brief Domain assignment for the processor bus master. + */ +typedef struct _trdc_processor_domain_assignment +{ + uint32_t domainId : 4U; /*!< Domain ID. */ + uint32_t domainIdSelect : 2U; /*!< Domain ID select method, see @ref trdc_did_sel_t. */ + uint32_t pidDomainHitConfig : 2U; /*!< The configuration of the domain hit evaluation for PID, see @ref + trdc_pid_domain_hit_config_t. */ + uint32_t pidMask : 6U; /*!< The mask combined with PID, so multiple PID can be included as part of the domain hit + determination. Set to 0 to disable. */ + uint32_t secureAttr : 2U; /*!< Secure attribute, see @ref trdc_secure_attr_t. */ + uint32_t pid : 6U; /*!< The process identifier, combined with pidMask to form the domain hit determination. */ + uint32_t : 8U; /*!< Reserved. */ + uint32_t lock : 1U; /*!< Lock the register. */ + uint32_t : 1U; /*!< Reserved. */ +} trdc_processor_domain_assignment_t; + +/*! + * @brief TRDC privileged attribute, the register bit TRDC_MDA_W0_x_DFMT1[PA], used for non-processor + * bus master domain assignment. + */ +typedef enum _trdc_privilege_attr +{ + kTRDC_ForceUser, /*!< Force the bus attribute for this master to user. */ + kTRDC_ForcePrivilege, /*!< Force the bus attribute for this master to privileged. */ + kTRDC_MasterPrivilege, /*!< Use the bus master's attribute directly. */ + kTRDC_MasterPrivilege1, /*!< Use the bus master's attribute directly. */ +} trdc_privilege_attr_t; + +/*! + * @brief Domain assignment for the non-processor bus master. + */ +typedef struct _trdc_non_processor_domain_assignment +{ + uint32_t domainId : 4U; /*!< Domain ID. */ + uint32_t privilegeAttr : 2U; /*!< Privileged attribute, see @ref trdc_privilege_attr_t. */ + uint32_t secureAttr : 2U; /*!< Secure attribute, see @ref trdc_secure_attr_t. */ + uint32_t bypassDomainId : 1U; /*!< Bypass domain ID. */ + uint32_t : 21U; /*!< Reserved. */ + uint32_t lock : 1U; /*!< Lock the register. */ + uint32_t : 1U; /*!< Reserved. */ +} trdc_non_processor_domain_assignment_t; + +/*! + * @brief PID lock configuration. + */ +typedef enum _trdc_pid_lock +{ + kTRDC_PidUnlocked0, /*!< The PID value can be updated by any secure priviledged write. */ + kTRDC_PidUnlocked1, /*!< The PID value can be updated by any secure priviledged write. */ + kTRDC_PidUnlocked2, /*!< The PID value can be updated by any secure priviledged write from the bus master that first + configured this register. */ + kTRDC_PidLocked, /*!< The PID value is locked until next reset. */ +} trdc_pid_lock_t; + +/*! + * @brief Process identifier(PID) configuration for processor cores. + */ +typedef struct _trdc_pid_config +{ + uint32_t pid : 6U; /*!< The process identifier of the executing task. The highest bit can be used to define + secure/nonsecure attribute of the task. */ + uint32_t : 23U; /*!< Reserved. */ + uint32_t lock : 2U; /*!< How to lock the register, see @ref trdc_pid_lock_t. */ + uint32_t : 1U; /*!< Reserved. */ +} trdc_pid_config_t; +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG +/* TZ-M congiguration definitions */ +/*! + * @brief IDAU(Implementation-Defined Attribution Unit) configuration for TZ-M function control. + */ +typedef struct _trdc_idau_config +{ + uint32_t : 8U; /*!< Reserved. */ + uint32_t lockSecureVTOR : 1U; /*!< Disable writes to secure VTOR(Vector Table Offset Register). */ + uint32_t lockNonsecureVTOR : 1U; /*!< Disable writes to non-secure VTOR, Application interrupt and Reset Control + Registers. */ + uint32_t lockSecureMPU : 1U; /*!< Disable writes to secure MPU(Memory Protection Unit) from software or from a debug + agent connected to the processor in Secure state. */ + uint32_t lockNonsecureMPU : 1U; /*!< Disable writes to non-secure MPU(Memory Protection Unit) from software or from + a debug agent connected to the processor. */ + uint32_t lockSAU : 1U; /*!< Disable writes to SAU(Security Attribution Unit) registers. */ + uint32_t : 19U; /*!< Reserved. */ +} trdc_idau_config_t; + +/* FLW(Flash Logical Window) configuration definitions */ +/*! + * @brief FLW(Flash Logical Window) configuration. + */ +typedef struct _trdc_flw_config +{ + uint16_t blockCount; /*!< Block count of the Flash Logic Window in 32KByte blocks. */ + uint32_t arrayBaseAddr; /*!< Flash array base address of the Flash Logical Window. */ + bool lock; /*!< Disable writes to FLW registers. */ + bool enable; /*!< Enable FLW function. */ +} trdc_flw_config_t; +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR) && FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR +/* Domain error check and clear definitions */ +/*! + * @brief TRDC controller definition for domain error check. Each TRDC instance may have different + * MRC or MBC count, call TRDC_GetHardwareConfig to get the actual count. + */ +typedef enum _trdc_controller +{ + kTRDC_MemBlockController0 = 0U, /*!< Memory block checker 0. */ + kTRDC_MemBlockController1 = 1U, /*!< Memory block checker 1. */ + kTRDC_MemBlockController2 = 2U, /*!< Memory block checker 2. */ + kTRDC_MemBlockController3 = 3U, /*!< Memory block checker 3. */ + kTRDC_MemRegionChecker0 = 4U, /*!< Memory region checker 0. */ + kTRDC_MemRegionChecker1 = 5U, /*!< Memory region checker 1. */ + kTRDC_MemRegionChecker2 = 6U, /*!< Memory region checker 2. */ + kTRDC_MemRegionChecker3 = 7U, /*!< Memory region checker 3. */ + kTRDC_MemRegionChecker4 = 8U, /*!< Memory region checker 4. */ + kTRDC_MemRegionChecker5 = 9U, /*!< Memory region checker 5. */ + kTRDC_MemRegionChecker6 = 10U, /*!< Memory region checker 6. */ +} trdc_controller_t; + +/*! + * @brief TRDC domain error state definition TRDC_MBCn_DERR_W1[EST] or TRDC_MRCn_DERR_W1[EST]. + */ +typedef enum _trdc_error_state +{ + kTRDC_ErrorStateNone = 0x00U, /*!< No access violation detected. */ + kTRDC_ErrorStateNone1 = 0x01U, /*!< No access violation detected. */ + kTRDC_ErrorStateSingle = 0x02U, /*!< Single access violation detected. */ + kTRDC_ErrorStateMulti = 0x03U /*!< Multiple access violation detected. */ +} trdc_error_state_t; + +/*! + * @brief TRDC domain error attribute definition TRDC_MBCn_DERR_W1[EATR] or TRDC_MRCn_DERR_W1[EATR]. + */ +typedef enum _trdc_error_attr +{ + kTRDC_ErrorSecureUserInst = 0x00U, /*!< Secure user mode, instruction fetch access. */ + kTRDC_ErrorSecureUserData = 0x01U, /*!< Secure user mode, data access. */ + kTRDC_ErrorSecurePrivilegeInst = 0x02U, /*!< Secure privileged mode, instruction fetch access. */ + kTRDC_ErrorSecurePrivilegeData = 0x03U, /*!< Secure privileged mode, data access. */ + kTRDC_ErrorNonSecureUserInst = 0x04U, /*!< NonSecure user mode, instruction fetch access. */ + kTRDC_ErrorNonSecureUserData = 0x05U, /*!< NonSecure user mode, data access. */ + kTRDC_ErrorNonSecurePrivilegeInst = 0x06U, /*!< NonSecure privileged mode, instruction fetch access. */ + kTRDC_ErrorNonSecurePrivilegeData = 0x07U /*!< NonSecure privileged mode, data access. */ +} trdc_error_attr_t; + +/*! + * @brief TRDC domain error access type definition TRDC_DERR_W1_n[ERW]. + */ +typedef enum _trdc_error_type +{ + kTRDC_ErrorTypeRead = 0x00U, /*!< Error occurs on read reference. */ + kTRDC_ErrorTypeWrite = 0x01U /*!< Error occurs on write reference. */ +} trdc_error_type_t; + +/*! + * @brief TRDC domain error definition. + */ +typedef struct _trdc_domain_error +{ + trdc_controller_t controller; /*!< Which controller captured access violation. */ + uint32_t address; /*!< Access address that generated access violation. */ + trdc_error_state_t errorState; /*!< Error state. */ + trdc_error_attr_t errorAttr; /*!< Error attribute. */ + trdc_error_type_t errorType; /*!< Error type. */ + uint8_t errorPort; /*!< Error port. */ + uint8_t domainId; /*!< Domain ID. */ + uint8_t slaveMemoryIdx; /*!< The slave memory index. Only apply when violation in MBC. */ +} trdc_domain_error_t; +#endif + +#if (defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC) || \ + (defined(FSL_FEATURE_TRDC_HAS_MRC) && FSL_FEATURE_TRDC_HAS_MRC) +/* Common definitions for MBC/MRC configuration */ +/*! + * @brief Memory access control configuration for MBC/MRC. + */ +typedef struct _trdc_memory_access_control_config +{ + uint32_t nonsecureUsrX : 1U; /*!< Allow nonsecure user execute access. */ + uint32_t nonsecureUsrW : 1U; /*!< Allow nonsecure user write access. */ + uint32_t nonsecureUsrR : 1U; /*!< Allow nonsecure user read access. */ + uint32_t : 1U; /*!< Reserved. */ + uint32_t nonsecurePrivX : 1U; /*!< Allow nonsecure privilege execute access. */ + uint32_t nonsecurePrivW : 1U; /*!< Allow nonsecure privilege write access. */ + uint32_t nonsecurePrivR : 1U; /*!< Allow nonsecure privilege read access. */ + uint32_t : 1U; /*!< Reserved. */ + uint32_t secureUsrX : 1U; /*!< Allow secure user execute access. */ + uint32_t secureUsrW : 1U; /*!< Allow secure user write access. */ + uint32_t secureUsrR : 1U; /*!< Allow secure user read access. */ + uint32_t : 1U; /*!< Reserved. */ + uint32_t securePrivX : 1U; /*!< Allownsecure privilege execute access. */ + uint32_t securePrivW : 1U; /*!< Allownsecure privilege write access. */ + uint32_t securePrivR : 1U; /*!< Allownsecure privilege read access. */ + uint32_t : 16U; /*!< Reserved. */ + uint32_t lock : 1U; /*!< Lock the configuration until next reset, only apply to access control register 0. */ +} trdc_memory_access_control_config_t; +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_MRC) && FSL_FEATURE_TRDC_HAS_MRC +/*! @brief The region descriptor enumeration, used to form a mask to set/clear the NSE bits for one or several regions. + */ +enum _trdc_region_descriptor +{ + kTRDC_RegionDescriptor0 = (1U << 0U), /*!< Region descriptor 0. */ + kTRDC_RegionDescriptor1 = (1U << 1U), /*!< Region descriptor 1. */ + kTRDC_RegionDescriptor2 = (1U << 2U), /*!< Region descriptor 2. */ + kTRDC_RegionDescriptor3 = (1U << 3U), /*!< Region descriptor 3. */ + kTRDC_RegionDescriptor4 = (1U << 4U), /*!< Region descriptor 4. */ + kTRDC_RegionDescriptor5 = (1U << 5U), /*!< Region descriptor 5. */ + kTRDC_RegionDescriptor6 = (1U << 6U), /*!< Region descriptor 6. */ + kTRDC_RegionDescriptor7 = (1U << 7U), /*!< Region descriptor 7. */ + kTRDC_RegionDescriptor8 = (1U << 8U), /*!< Region descriptor 8. */ + kTRDC_RegionDescriptor9 = (1U << 9U), /*!< Region descriptor 9. */ + kTRDC_RegionDescriptor10 = (1U << 10U), /*!< Region descriptor 10. */ + kTRDC_RegionDescriptor11 = (1U << 11U), /*!< Region descriptor 11. */ + kTRDC_RegionDescriptor12 = (1U << 12U), /*!< Region descriptor 12. */ + kTRDC_RegionDescriptor13 = (1U << 13U), /*!< Region descriptor 13. */ + kTRDC_RegionDescriptor14 = (1U << 14U), /*!< Region descriptor 14. */ + kTRDC_RegionDescriptor15 = (1U << 15U), /*!< Region descriptor 15. */ +}; + +/* MRC configuration definitions */ +/*! @brief The MRC domain enumeration, used to form a mask to enable/disable the update or clear all NSE bits of one or + * several domains. */ +enum _trdc_MRC_domain +{ + kTRDC_MrcDomain0 = (1U << 0U), /*!< Domain 0. */ + kTRDC_MrcDomain1 = (1U << 1U), /*!< Domain 1. */ + kTRDC_MrcDomain2 = (1U << 2U), /*!< Domain 2. */ + kTRDC_MrcDomain3 = (1U << 3U), /*!< Domain 3. */ + kTRDC_MrcDomain4 = (1U << 4U), /*!< Domain 4. */ + kTRDC_MrcDomain5 = (1U << 5U), /*!< Domain 5. */ + kTRDC_MrcDomain6 = (1U << 6U), /*!< Domain 6. */ + kTRDC_MrcDomain7 = (1U << 7U), /*!< Domain 7. */ + kTRDC_MrcDomain8 = (1U << 8U), /*!< Domain 8. */ + kTRDC_MrcDomain9 = (1U << 9U), /*!< Domain 9. */ + kTRDC_MrcDomain10 = (1U << 10U), /*!< Domain 10. */ + kTRDC_MrcDomain11 = (1U << 11U), /*!< Domain 11. */ + kTRDC_MrcDomain12 = (1U << 12U), /*!< Domain 12. */ + kTRDC_MrcDomain13 = (1U << 13U), /*!< Domain 13. */ + kTRDC_MrcDomain14 = (1U << 14U), /*!< Domain 14. */ + kTRDC_MrcDomain15 = (1U << 15U), /*!< Domain 15. */ +}; + +/*! + * @brief The configuration of each region descriptor per domain per MRC instance. + */ +typedef struct _trdc_mrc_region_descriptor_config +{ + uint8_t memoryAccessControlSelect; /*!< Select one of the 8 access control policies for this region, for + access cotrol policies see @ref trdc_memory_access_control_config_t. */ + uint32_t startAddr; /*!< Physical start address. */ + bool valid; /*!< Lock the register. */ + bool nseEnable; /*!< Enable non-secure accesses and disable secure accesses. */ + uint32_t endAddr; /*!< Physical start address. */ + uint8_t mrcIdx; /*!< The index of the MRC for this configuration to take effect. */ + uint8_t domainIdx; /*!< The index of the domain for this configuration to take effect. */ + uint8_t regionIdx; /*!< The index of the region for this configuration to take effect. */ +} trdc_mrc_region_descriptor_config_t; +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC +/* MBC configuration definitions */ +/*! + * @brief The configuration of MBC NSE update. + */ +#if defined(FSL_FEATURE_TRDC_DOMAIN_COUNT) && (FSL_FEATURE_TRDC_DOMAIN_COUNT > 0x8U) +typedef struct _trdc_mbc_nse_update_config +{ + uint32_t autoIncrement : 1U; /*!< Whether to increment the word index after current word is updated using this + configuration. */ + uint32_t : 1U; /*!< Reserved. */ + uint32_t wordIdx : 4U; /*!< MBC configuration word index to be updated. */ + uint32_t : 2U; /*!< Reserved. */ + uint32_t memorySelect : 4U; /*!< Bit mask of the selected memory to be updated. @ref _trdc_MBC_memory. */ + uint32_t : 4U; /*!< Reserved. */ + uint32_t domianSelect : 16U; /*!< Bit mask of the selected domain to be updated. @ref _trdc_MBC_domain. */ +} trdc_mbc_nse_update_config_t; +#else +typedef struct _trdc_mbc_nse_update_config +{ + uint32_t : 2U; /*!< Reserved. */ + uint32_t wordIdx : 4U; /*!< MBC configuration word index to be updated. */ + uint32_t : 2U; /*!< Reserved. */ + uint32_t memorySelect : 4U; /*!< Bit mask of the selected memory to be updated. @ref _trdc_MBC_memory. */ + uint32_t : 4U; /*!< Reserved. */ + uint32_t domianSelect : 8U; /*!< Bit mask of the selected domain to be updated. @ref _trdc_MBC_domain. */ + uint32_t : 7U; /*!< Reserved. */ + uint32_t autoIncrement : 1U; /*!< Whether to increment the word index after current word is updated using this + configuration. */ +} trdc_mbc_nse_update_config_t; +#endif + +/*! @brief The MBC domain enumeration, used to form a mask to enable/disable the update or clear NSE bits of one or + * several domains. */ +enum _trdc_MBC_domain +{ + kTRDC_MbcDomain0 = (1U << 0U), /*!< Domain 0. */ + kTRDC_MbcDomain1 = (1U << 1U), /*!< Domain 1. */ + kTRDC_MbcDomain2 = (1U << 2U), /*!< Domain 2. */ + kTRDC_MbcDomain3 = (1U << 3U), /*!< Domain 3. */ + kTRDC_MbcDomain4 = (1U << 4U), /*!< Domain 4. */ + kTRDC_MbcDomain5 = (1U << 5U), /*!< Domain 5. */ + kTRDC_MbcDomain6 = (1U << 6U), /*!< Domain 6. */ + kTRDC_MbcDomain7 = (1U << 7U), /*!< Domain 7. */ +}; + +/*! @brief The MBC slave memory enumeration, used to form a mask to enable/disable the update or clear NSE bits of one + * or several memory block. */ +enum _trdc_MBC_memory +{ + kTRDC_MbcSlaveMemory0 = (1U << 0U), /*!< Memory 0. */ + kTRDC_MbcSlaveMemory1 = (1U << 1U), /*!< Memory 1. */ + kTRDC_MbcSlaveMemory2 = (1U << 2U), /*!< Memory 2. */ + kTRDC_MbcSlaveMemory3 = (1U << 3U), /*!< Memory 3. */ +}; + +/*! @brief The MBC bit enumeration, used to form a mask to set/clear configured words' NSE. */ +enum _trdc_MBC_bit +{ + kTRDC_MbcBit0 = (1U << 0U), /*!< Bit 0. */ + kTRDC_MbcBit1 = (1U << 1U), /*!< Bit 1. */ + kTRDC_MbcBit2 = (1U << 2U), /*!< Bit 2. */ + kTRDC_MbcBit3 = (1U << 3U), /*!< Bit 3. */ + kTRDC_MbcBit4 = (1U << 4U), /*!< Bit 4. */ + kTRDC_MbcBit5 = (1U << 5U), /*!< Bit 5. */ + kTRDC_MbcBit6 = (1U << 6U), /*!< Bit 6. */ + kTRDC_MbcBit7 = (1U << 7U), /*!< Bit 7. */ + kTRDC_MbcBit8 = (1U << 8U), /*!< Bit 8. */ + kTRDC_MbcBit9 = (1U << 9U), /*!< Bit 9. */ + kTRDC_MbcBit10 = (1U << 10U), /*!< Bit 10. */ + kTRDC_MbcBit11 = (1U << 11U), /*!< Bit 11. */ + kTRDC_MbcBit12 = (1U << 12U), /*!< Bit 12. */ + kTRDC_MbcBit13 = (1U << 13U), /*!< Bit 13. */ + kTRDC_MbcBit14 = (1U << 14U), /*!< Bit 14. */ + kTRDC_MbcBit15 = (1U << 15U), /*!< Bit 15. */ + kTRDC_MbcBit16 = (1U << 16U), /*!< Bit 16. */ + kTRDC_MbcBit17 = (1U << 17U), /*!< Bit 17. */ + kTRDC_MbcBit18 = (1U << 18U), /*!< Bit 18. */ + kTRDC_MbcBit19 = (1U << 19U), /*!< Bit 19. */ + kTRDC_MbcBit20 = (1U << 20U), /*!< Bit 20. */ + kTRDC_MbcBit21 = (1U << 21U), /*!< Bit 21. */ + kTRDC_MbcBit22 = (1U << 22U), /*!< Bit 22. */ + kTRDC_MbcBit23 = (1U << 23U), /*!< Bit 23. */ + kTRDC_MbcBit24 = (1U << 24U), /*!< Bit 24. */ + kTRDC_MbcBit25 = (1U << 25U), /*!< Bit 25. */ + kTRDC_MbcBit26 = (1U << 26U), /*!< Bit 26. */ + kTRDC_MbcBit27 = (1U << 27U), /*!< Bit 27. */ + kTRDC_MbcBit28 = (1U << 28U), /*!< Bit 28. */ + kTRDC_MbcBit29 = (1U << 29U), /*!< Bit 29. */ + kTRDC_MbcBit30 = (1U << 30U), /*!< Bit 30. */ + kTRDC_MbcBit31 = (1U << 31U), /*!< Bit 31. */ +}; + +/*! + * @brief The configuration of each memory block per domain per MBC instance. + */ +typedef struct _trdc_mbc_memory_block_config +{ + uint32_t memoryAccessControlSelect : 3U; /*!< Select one of the 8 access control policies for this memory block, for + access cotrol policies see @ref trdc_memory_access_control_config_t. */ + uint32_t nseEnable : 1U; /*!< Enable non-secure accesses and disable secure accesses. */ + uint32_t mbcIdx : 4U; /*!< The index of the MBC for this configuration to take effect. */ + uint32_t domainIdx : 8U; /*!< The index of the domain for this configuration to take effect. */ + uint32_t slaveMemoryIdx : 8U; /*!< The index of the slave memory for this configuration to take effect. */ + uint32_t memoryBlockIdx : 8U; /*!< The index of the memory block for this configuration to take effect. */ +} trdc_mbc_memory_block_config_t; +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ +/*! + * @brief Initializes the TRDC module. + * + * This function enables the TRDC clock. + * + * @param base TRDC peripheral base address. + */ +void TRDC_Init(TRDC_Type *base); + +/*! + * @brief De-initializes the TRDC module. + * + * This function disables the TRDC clock. + * + * @param base TRDC peripheral base address. + */ +void TRDC_Deinit(TRDC_Type *base); +/*! @} */ + +#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG +/*! + * @name Hardware configuration + * @{ + */ +/*! + * @brief Gets the domain ID of the current bus master. + * + * @param base TRDC peripheral base address. + * @return Domain ID of current bus master. + */ +static inline uint8_t TRDC_GetCurrentMasterDomainId(TRDC_Type *base) +{ + return (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG1 & TRDC_TRDC_HWCFG1_DID_MASK) >> TRDC_TRDC_HWCFG1_DID_SHIFT); +} + +/*! + * @brief Gets the TRDC hardware configuration. + * + * This function gets the TRDC hardware configurations, including number of bus + * masters, number of domains, number of MRCs and number of PACs. + * + * @param base TRDC peripheral base address. + * @param config Pointer to the structure to get the configuration. + */ +void TRDC_GetHardwareConfig(TRDC_Type *base, trdc_hardware_config_t *config); +/*! @} */ +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT) && FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT +/*! + * @name Master domain assignment + * @{ + */ +/*! + * @brief Sets the TRDC DAC(Domain Assignment Controllers) global valid. + * + * Once enabled, it will remain enabled until next reset. + * + * @param base TRDC peripheral base address. + */ +static inline void TRDC_SetDacGlobalValid(TRDC_Type *base) +{ + TRDC_GENERAL_BASE(base)->TRDC_CR |= TRDC_TRDC_CR_GVLDM_MASK; +} + +/*! + * @brief Locks the bus master domain assignment register. + * + * This function locks the master domain assignment. After it is locked, the register can't be changed + * until next reset. + * + * @param base TRDC peripheral base address. + * @param master Which master to configure, refer to trdcx_master_t in processor header file, x is trdc instance. + * @param regNum Which register to configure, processor master can have more than one register for the MDAC + configuration. + * @param assignIndex Which assignment register to lock. + */ +static inline void TRDC_LockMasterDomainAssignment(TRDC_Type *base, uint8_t master, uint8_t regNum) +{ + /* Make sure in the master range. */ + assert((uint32_t)master < + ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMSTR_MASK) >> TRDC_TRDC_HWCFG0_NMSTR_SHIFT)); + if (0U == (TRDC_GENERAL_BASE(base)->DACFG[master] & TRDC_DACFG_NCM_MASK)) + { + TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT0[master].MDA_W_DFMT0[regNum] |= TRDC_MDA_W_DFMT0_LK1_MASK; + } + else + { + TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT1[master].MDA_W_DFMT1[0] |= TRDC_MDA_W_DFMT1_LK1_MASK; + } +} + +/*! + * @brief Sets the master domain assignment as valid or invalid. + * + * This function sets the master domain assignment as valid or invalid. + * + * @param base TRDC peripheral base address. + * @param master Which master to configure. + * @param regNum Which register to configure, processor master can have more than one register for the MDAC + * configuration. + * @param assignIndex Index for the domain assignment register. + * @param valid True to set valid, false to set invalid. + */ +static inline void TRDC_SetMasterDomainAssignmentValid(TRDC_Type *base, uint8_t master, uint8_t regNum, bool valid) +{ + /* Make sure in the master range. */ + assert((uint32_t)master < + ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMSTR_MASK) >> TRDC_TRDC_HWCFG0_NMSTR_SHIFT)); + if (valid) + { + if (0U == (TRDC_GENERAL_BASE(base)->DACFG[master] & TRDC_DACFG_NCM_MASK)) + { + TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT0[master].MDA_W_DFMT0[regNum] |= TRDC_MDA_W_DFMT0_VLD_MASK; + } + else + { + TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT1[master].MDA_W_DFMT1[0] |= TRDC_MDA_W_DFMT1_VLD_MASK; + } + } + else + { + if (0U == (TRDC_GENERAL_BASE(base)->DACFG[master] & TRDC_DACFG_NCM_MASK)) + { + TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT0[master].MDA_W_DFMT0[regNum] &= ~TRDC_MDA_W_DFMT0_VLD_MASK; + } + else + { + TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT1[master].MDA_W_DFMT1[0] &= ~TRDC_MDA_W_DFMT1_VLD_MASK; + } + } +} + +/*! + * @brief Gets the default master domain assignment for the processor bus master. + * + * This function gets the default master domain assignment for the processor bus master. + * It should only be used for the processor bus masters, such as CORE0. This function + * sets the assignment as follows: + * + * @code + * assignment->domainId = 0U; + * assignment->domainIdSelect = kTRDC_DidMda; + * assignment->lock = 0U; + * @endcode + * + * @param domainAssignment Pointer to the assignment structure. + */ +void TRDC_GetDefaultProcessorDomainAssignment(trdc_processor_domain_assignment_t *domainAssignment); + +/*! + * @brief Gets the default master domain assignment for non-processor bus master. + * + * This function gets the default master domain assignment for non-processor bus master. + * It should only be used for the non-processor bus masters, such as DMA. This function + * sets the assignment as follows: + * + * @code + * assignment->domainId = 0U; + * assignment->privilegeAttr = kTRDC_ForceUser; + * assignment->secureAttr = kTRDC_ForceSecure; + * assignment->bypassDomainId = 0U; + * assignment->lock = 0U; + * @endcode + * + * @param domainAssignment Pointer to the assignment structure. + */ +void TRDC_GetDefaultNonProcessorDomainAssignment(trdc_non_processor_domain_assignment_t *domainAssignment); + +/*! + * @brief Sets the processor bus master domain assignment. + * + * This function sets the processor master domain assignment as valid. + * One bus master might have multiple domain assignment registers. The parameter + * \p assignIndex specifies which assignment register to set. + * + * Example: Set domain assignment for core 0. + * + * @code + * trdc_processor_domain_assignment_t processorAssignment; + * + * TRDC_GetDefaultProcessorDomainAssignment(&processorAssignment); + * + * processorAssignment.domainId = 0; + * processorAssignment.xxx = xxx; + * TRDC_SetMasterDomainAssignment(TRDC, &processorAssignment); + * @endcode + * + * @param base TRDC peripheral base address. + * @param master Which master to configure, refer to trdc_master_t in processor header file. + * @param regNum Which register to configure, processor master can have more than one register for the MDAC + * configuration. + * @param domainAssignment Pointer to the assignment structure. + */ +void TRDC_SetProcessorDomainAssignment(TRDC_Type *base, + uint8_t master, + uint8_t regNum, + const trdc_processor_domain_assignment_t *domainAssignment); + +/*! + * @brief Sets the non-processor bus master domain assignment. + * + * This function sets the non-processor master domain assignment as valid. + * One bus master might have multiple domain assignment registers. The parameter + * \p assignIndex specifies which assignment register to set. + * + * Example: Set domain assignment for DMA0. + * @code + * trdc_non_processor_domain_assignment_t nonProcessorAssignment; + * + * TRDC_GetDefaultNonProcessorDomainAssignment(&nonProcessorAssignment); + * nonProcessorAssignment.domainId = 1; + * nonProcessorAssignment.xxx = xxx; + * + * TRDC_SetMasterDomainAssignment(TRDC, kTrdcMasterDma0, 0U, &nonProcessorAssignment); + * @endcode + * + * @param base TRDC peripheral base address. + * @param master Which master to configure, refer to trdc_master_t in processor header file. + * @param domainAssignment Pointer to the assignment structure. + */ +void TRDC_SetNonProcessorDomainAssignment(TRDC_Type *base, + uint8_t master, + const trdc_non_processor_domain_assignment_t *domainAssignment); + +/*! + * @brief Gets the bit map of the bus master(s) that is(are) sourcing a PID register. + * + * This function sets the non-processor master domain assignment as valid. + * + * @param base TRDC peripheral base address. + * @return the bit map of the master(s). Bit 1 sets indicates bus master 1. + */ +static inline uint64_t TRDC_GetActiveMasterPidMap(TRDC_Type *base) +{ + return ((uint64_t)TRDC_GENERAL_BASE(base)->TRDC_HWCFG3 << 32U) | (uint64_t)TRDC_GENERAL_BASE(base)->TRDC_HWCFG2; +} + +/*! + * @brief Sets the current Process identifier(PID) for processor core. + * + * Each processor has a corresponding process identifier (PID) which can be used to group tasks into different domains. + * Secure privileged software saves and restores the PID as part of any context switch. + * This data structure defines an array of 32-bit values, one per MDA module, that define the PID. Since this register + * resource is only applicable to processor cores, the data structure is typically sparsely populated. The HWCFG[2-3] + * registers provide a bitmap of the implemented PIDn registers. This data structure is indexed using the corresponding + * MDA instance number. Depending on the operating clock domain of each DAC instance, there may be optional information + * stored in the corresponding PIDm register to properly implement the LK2 = 2 functionality. + * + * @param base TRDC peripheral base address. + * @param master Which processor master to configure, refer to trdc_master_t in processor header file. + * @param pidConfig Pointer to the configuration structure. + */ +void TRDC_SetPid(TRDC_Type *base, uint8_t master, const trdc_pid_config_t *pidConfig); +/*! @} */ +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG +/*! + * @name TZ-M congiguration + * @{ + */ +/*! + * @brief Gets the default IDAU(Implementation-Defined Attribution Unit) configuration. + * + * @code + * config->lockSecureVTOR = false; + * config->lockNonsecureVTOR = false; + * config->lockSecureMPU = false; + * config->lockNonsecureMPU = false; + * config->lockSAU = false; + * @endcode + * + * @param domainAssignment Pointer to the configuration structure. + */ +void TRDC_GetDefaultIDAUConfig(trdc_idau_config_t *idauConfiguration); + +/*! + * @brief Sets the IDAU(Implementation-Defined Attribution Unit) control configuration. + * + * Example: Lock the secure and non-secure MPU registers. + * + * @code + * trdc_idau_config_t idauConfiguration; + * + * TRDC_GetDefaultIDAUConfig(&idauConfiguration); + * + * idauConfiguration.lockSecureMPU = true; + * idauConfiguration.lockNonsecureMPU = true; + * TRDC_SetIDAU(TRDC, &idauConfiguration); + * @endcode + * + * @param base TRDC peripheral base address. + * @param domainAssignment Pointer to the configuration structure. + */ +void TRDC_SetIDAU(TRDC_Type *base, const trdc_idau_config_t *idauConfiguration); +/*! @} */ +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_FLW) && FSL_FEATURE_TRDC_HAS_FLW +/*! + * @name FLW(Flash Logical Window) configuration + * @{ + */ +/*! + * @brief Enables/disables the FLW(flash logical window) function. + * + * @param base TRDC peripheral base address. + * @param enable True to enable, false to disable. + */ +static inline void TRDC_EnableFlashLogicalWindow(TRDC_Type *base, bool enable) +{ + if (enable) + { + TRDC_FLW_BASE(base)->TRDC_FLW_CTL |= TRDC_TRDC_FLW_CTL_V_MASK; + } + else + { + TRDC_FLW_BASE(base)->TRDC_FLW_CTL &= ~TRDC_TRDC_FLW_CTL_V_MASK; + } +} + +/*! + * @brief Locks FLW registers. Once locked the registers can noy be updated until next reset. + * + * @param base TRDC peripheral base address. + */ +static inline void TRDC_LockFlashLogicalWindow(TRDC_Type *base) +{ + TRDC_FLW_BASE(base)->TRDC_FLW_CTL |= TRDC_TRDC_FLW_CTL_LK_MASK; +} + +/*! + * @brief Gets the FLW physical base address. + * + * @param base TRDC peripheral base address. + * @return Physical address of the FLW function. + */ +static inline uint32_t TRDC_GetFlashLogicalWindowPbase(TRDC_Type *base) +{ + return TRDC_FLW_BASE(base)->TRDC_FLW_PBASE; +} + +/*! + * @brief Sets the FLW size. + * + * @param base TRDC peripheral base address. + * @param size Size of the FLW in unit of 32k bytes. + */ +static inline void TRDC_GetSetFlashLogicalWindowSize(TRDC_Type *base, uint16_t size) +{ + TRDC_FLW_BASE(base)->TRDC_FLW_BCNT = size; +} + +/*! + * @brief Gets the default FLW(Flsh Logical Window) configuration. + * + * @code + * config->blockCount = false; + * config->arrayBaseAddr = false; + * config->lock = false; + * config->enable = false; + * @endcode + * + * @param flwConfiguration Pointer to the configuration structure. + */ +void TRDC_GetDefaultFlashLogicalWindowConfig(trdc_flw_config_t *flwConfiguration); + +/*! + * @brief Sets the FLW function's configuration. + * + * @code + * trdc_flw_config_t flwConfiguration; + * + * TRDC_GetDefaultIDAUConfig(&flwConfiguration); + * + * flwConfiguration.blockCount = 32U; + * flwConfiguration.arrayBaseAddr = 0xXXXXXXXX; + * TRDC_SetIDAU(TRDC, &flwConfiguration); + * @endcode + * + * @param base TRDC peripheral base address. + * @param flwConfiguration Pointer to the configuration structure. + */ +void TRDC_SetFlashLogicalWindow(TRDC_Type *base, const trdc_flw_config_t *flwConfiguration); +/*! @} */ +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR) && FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR +/*! + * @name Domain error check and clear + * @{ + */ +/*! + * @brief Gets and clears the first domain error of the current domain. + * + * This function gets the first access violation information for the current domain + * and clears the pending flag. There might be multiple access violations pending + * for the current domain. This function only processes the first error. + * + * @param base TRDC peripheral base address. + * @param error Pointer to the error information. + * @return If the access violation is captured, this function returns the kStatus_Success. + * The error information can be obtained from the parameter error. If no + * access violation is captured, this function returns the kStatus_NoData. + */ +status_t TRDC_GetAndClearFirstDomainError(TRDC_Type *base, trdc_domain_error_t *error); + +/*! + * @brief Gets and clears the first domain error of the specific domain. + * + * This function gets the first access violation information for the specific domain + * and clears the pending flag. There might be multiple access violations pending + * for the current domain. This function only processes the first error. + * + * @param base TRDC peripheral base address. + * @param error Pointer to the error information. + * @param domainId The error of which domain to get and clear. + * @return If the access violation is captured, this function returns the kStatus_Success. + * The error information can be obtained from the parameter error. If no + * access violation is captured, this function returns the kStatus_NoData. + */ +status_t TRDC_GetAndClearFirstSpecificDomainError(TRDC_Type *base, trdc_domain_error_t *error, uint8_t domainId); +/*! @} */ +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_MRC) && FSL_FEATURE_TRDC_HAS_MRC +/*! + * @name MRC configuration + * @{ + */ +#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG +/*! + * @brief Sets the TRDC MRC(Memory Region Checkers) global valid. + * + * Once enabled, it will remain enabled until next reset. + * + * @param base TRDC peripheral base address. + */ +static inline void TRDC_SetMrcGlobalValid(TRDC_Type *base) +{ + TRDC_GENERAL_BASE(base)->TRDC_CR |= TRDC_TRDC_CR_GVLDR_MASK; +} +#endif + +/*! + * @brief Gets the TRDC MRC(Memory Region Checkers) region number valid. + * + * @param base TRDC peripheral base address. + * @return the region number of the given MRC instance + */ +static inline uint8_t TRDC_GetMrcRegionNumber(TRDC_Type *base, uint8_t mrcIdx) +{ + return (uint8_t)((TRDC_MRC_BASE(base, mrcIdx)->MRC_GLBCFG & TRDC_MRC_GLBCFG_NRGNS_MASK) >> + TRDC_MRC_GLBCFG_NRGNS_SHIFT); +} + +/*! + * @brief Sets the memory access configuration for one of the access control register of one MRC. + * + * Example: Enable the secure operations and lock the configuration for MRC0 region 1. + * + * @code + * trdc_memory_access_control_config_t config; + * + * config.securePrivX = true; + * config.securePrivW = true; + * config.securePrivR = true; + * config.lock = true; + * TRDC_SetMrcMemoryAccess(TRDC, &config, 0, 1); + * @endcode + * + * @param base TRDC peripheral base address. + * @param config Pointer to the configuration structure. + * @param mrcIdx MRC index. + * @param regIdx Register number. + */ +void TRDC_MrcSetMemoryAccessConfig(TRDC_Type *base, + const trdc_memory_access_control_config_t *config, + uint8_t mrcIdx, + uint8_t regIdx); + +/*! + * @brief Enables the update of the selected domians. + * + * After the domians' update are enabled, their regions' NSE bits can be set or clear. + * + * @param base TRDC peripheral base address. + * @param mrcIdx MRC index. + * @param domianMask Bit mask of the domains to be enabled. + * @param enable True to enable, false to disable. + */ +void TRDC_MrcEnableDomainNseUpdate(TRDC_Type *base, uint8_t mrcIdx, uint16_t domianMask, bool enable); + +/*! + * @brief Sets the NSE bits of the selected regions for domains. + * + * This function sets the NSE bits for the selected regions for the domains whose update are enabled. + * + * @param base TRDC peripheral base address. + * @param mrcIdx MRC index. + * @param regionMask Bit mask of the regions whose NSE bits to set. + */ +void TRDC_MrcRegionNseSet(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask); + +/*! + * @brief Clears the NSE bits of the selected regions for domains. + * + * This function clears the NSE bits for the selected regions for the domains whose update are enabled. + * + * @param base TRDC peripheral base address. + * @param mrcIdx MRC index. + * @param regionMask Bit mask of the regions whose NSE bits to clear. + */ +void TRDC_MrcRegionNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask); + +/*! + * @brief Clears the NSE bits for all the regions of the selected domains. + * + * This function clears the NSE bits for all regions of selected domains whose update are enabled. + * + * @param base TRDC peripheral base address. + * @param mrcIdx MRC index. + * @param domainMask Bit mask of the domians whose NSE bits to clear. + */ +void TRDC_MrcDomainNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t domainMask); + +/*! + * @brief Sets the configuration for one of the region descriptor per domain per MRC instnce. + * + * This function sets the configuration for one of the region descriptor, including the start + * and end address of the region, memory access control policy and valid. + * + * @param base TRDC peripheral base address. + * @param config Pointer to region descriptor configuration structure. + */ +void TRDC_MrcSetRegionDescriptorConfig(TRDC_Type *base, const trdc_mrc_region_descriptor_config_t *config); +/*! @} */ +#endif + +#if defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC +/*! + * @name MBC configuration + * @{ + */ +#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG +/*! + * @brief Sets the TRDC MBC(Memory Block Checkers) global valid. + * + * Once enabled, it will remain enabled until next reset. + * + * @param base TRDC peripheral base address. + */ +static inline void TRDC_SetMbcGlobalValid(TRDC_Type *base) +{ + TRDC_GENERAL_BASE(base)->TRDC_CR |= TRDC_TRDC_CR_GVLDB_MASK; +} +#endif + +/*! + * @brief Gets the hardware configuration of the one of two slave memories within each MBC(memory block checker). + * + * @param base TRDC peripheral base address. + * @param config Pointer to the structure to get the configuration. + * @param mbcIdx MBC number. + * @param slvIdx Slave number. + */ +void TRDC_GetMbcHardwareConfig(TRDC_Type *base, + trdc_slave_memory_hardware_config_t *config, + uint8_t mbcIdx, + uint8_t slvIdx); + +/*! + * @brief Sets the NSR update configuration for one of the MBC instance. + * + * After set the NSE configuration, the configured memory area can be updateby NSE set/clear. + * + * @param base TRDC peripheral base address. + * @param config Pointer to NSE update configuration structure. + * @param mbcIdx MBC index. + */ +void TRDC_MbcSetNseUpdateConfig(TRDC_Type *base, const trdc_mbc_nse_update_config_t *config, uint8_t mbcIdx); + +/*! + * @brief Sets the NSE bits of the selected configuration words according to NSE update configuration. + * + * This function sets the NSE bits of the word for the configured regio, memory. + * + * @param base TRDC peripheral base address. + * @param mbcIdx MBC index. + * @param bitMask Mask of the bits whose NSE bits to set. + */ +void TRDC_MbcWordNseSet(TRDC_Type *base, uint8_t mbcIdx, uint32_t bitMask); + +/*! + * @brief Clears the NSE bits of the selected configuration words according to NSE update configuration. + * + * This function sets the NSE bits of the word for the configured regio, memory. + * + * @param base TRDC peripheral base address. + * @param mbcIdx MBC index. + * @param bitMask Mask of the bits whose NSE bits to clear. + */ +void TRDC_MbcWordNseClear(TRDC_Type *base, uint8_t mbcIdx, uint32_t bitMask); + +/*! + * @brief Clears all configuration words' NSE bits of the selected domain and memory. + * + * @param base TRDC peripheral base address. + * @param mbcIdx MBC index. + * @param domainMask Mask of the domains whose NSE bits to clear, 0b110 means clear domain 1&2. + * @param slaveMask Mask of the slaves whose NSE bits to clear, 0x11 means clear all slave 0&1's NSE bits. + */ +void TRDC_MbcNseClearAll(TRDC_Type *base, uint8_t mbcIdx, uint16_t domainMask, uint8_t slave); + +/*! + * @brief Sets the memory access configuration for one of the region descriptor of one MBC. + * + * Example: Enable the secure operations and lock the configuration for MRC0 region 1. + * + * @code + * trdc_memory_access_control_config_t config; + * + * config.securePrivX = true; + * config.securePrivW = true; + * config.securePrivR = true; + * config.lock = true; + * TRDC_SetMbcMemoryAccess(TRDC, &config, 0, 1); + * @endcode + * + * @param base TRDC peripheral base address. + * @param config Pointer to the configuration structure. + * @param mbcIdx MBC index. + * @param rgdIdx Region descriptor number. + */ +void TRDC_MbcSetMemoryAccessConfig(TRDC_Type *base, + const trdc_memory_access_control_config_t *config, + uint8_t mbcIdx, + uint8_t rgdIdx); + +/*! + * @brief Sets the configuration for one of the memory block per domain per MBC instnce. + * + * This function sets the configuration for one of the memory block, including the memory access + * control policy and nse enable. + * + * @param base TRDC peripheral base address. + * @param config Pointer to memory block configuration structure. + */ +void TRDC_MbcSetMemoryBlockConfig(TRDC_Type *base, const trdc_mbc_memory_block_config_t *config); +/*! @} */ +#endif + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* FSL_TRDC_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_trdc_core.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_trdc_core.h new file mode 100644 index 00000000000..8c3e2a9b508 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_trdc_core.h @@ -0,0 +1,489 @@ +/* + * Copyright 2022-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_TRDC_CORE_H_ +#define FSL_TRDC_CORE_H_ + +#include "fsl_trdc_soc.h" + +/*! + * @addtogroup trdc_core + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*!@brief TRDC general configuration register definition. */ +typedef struct _TRDC_General_Type +{ + __IO uint32_t TRDC_CR; /**< TRDC Register, offset: 0x0 */ + uint8_t RESERVED_0[236]; + __I uint32_t TRDC_HWCFG0; /**< TRDC Hardware Configuration Register 0, offset: 0xF0 */ + __I uint32_t TRDC_HWCFG1; /**< TRDC Hardware Configuration Register 1, offset: 0xF4 */ + __I uint32_t TRDC_HWCFG2; /**< TRDC Hardware Configuration Register 2, offset: 0xF8 */ + __I uint32_t TRDC_HWCFG3; /**< TRDC Hardware Configuration Register 3, offset: 0xFC */ + __I uint8_t DACFG[8]; /**< Domain Assignment Configuration Register, array offset: 0x100, array step: 0x1 */ + uint8_t RESERVED_1[184]; + __IO uint32_t TRDC_IDAU_CR; /**< TRDC IDAU Control Register, offset: 0x1C0 */ +} TRDC_General_Type; + +/*!@brief TRDC flash logical control register definition. */ +typedef struct _TRDC_FLW_Type +{ + __IO uint32_t TRDC_FLW_CTL; /**< TRDC FLW Control, offset: 0x1E0 */ + __I uint32_t TRDC_FLW_PBASE; /**< TRDC FLW Physical Base, offset: 0x1E4 */ + __IO uint32_t TRDC_FLW_ABASE; /**< TRDC FLW Array Base, offset: 0x1E8 */ + __IO uint32_t TRDC_FLW_BCNT; /**< TRDC FLW Block Count, offset: 0x1EC */ +} TRDC_FLW_Type; + +/*!@brief TRDC domain error register definition. */ +typedef struct _TRDC_DomainError_Type +{ + __IO uint32_t TRDC_FDID; /**< TRDC Fault Domain ID, offset: 0x1FC */ + __I uint32_t TRDC_DERRLOC[16]; /**< TRDC Domain Error Location Register, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_4[448]; + struct + { /* offset: 0x400, array step: 0x10 */ + __I uint32_t W0; /**< MBC Domain Error Word0 Register, array offset: 0x400, array step: 0x10 */ + __I uint32_t W1; /**< MBC Domain Error Word1 Register, array offset: 0x404, array step: 0x10 */ + uint8_t RESERVED_0[4]; + __O uint32_t W3; /**< MBC Domain Error Word3 Register, array offset: 0x40C, array step: 0x10 */ + } MBC_DERR[8]; + struct + { /* offset: 0x480, array step: 0x10 */ + __I uint32_t W0; /**< MRC Domain Error Word0 Register, array offset: 0x480, array step: 0x10 */ + __I uint32_t W1; /**< MRC Domain Error Word1 Register, array offset: 0x484, array step: 0x10 */ + uint8_t RESERVED_0[4]; + __O uint32_t W3; /**< MRC Domain Error Word3 Register, array offset: 0x48C, array step: 0x10 */ + } MRC_DERR[8]; +} TRDC_DomainError_Type; + +/*!@brief TRDC master domain assignment register definition. */ +typedef struct _TRDC_DomainAssignment_Type +{ + __IO uint32_t PID[8]; /**< Process Identifier, array offset: 0x700, array step: 0x4 */ + uint8_t RESERVED_7[224]; + union + { + struct + { /* offset: 0x800, array step: 0x20 */ + __IO uint32_t MDA_W_DFMT0[8]; /**< DAC Master Domain Assignment Register, array offset: 0x800, array step: + index*0x20, index2*0x4 */ + } MDA_DFMT0[8]; + struct + { /* offset: 0x800, array step: 0x20 */ + __IO uint32_t MDA_W_DFMT1[1]; /**< DAC Master Domain Assignment Register, array offset: 0x800, array step: + index*0x20, index2*0x4 */ + uint8_t RESERVED_0[28]; + } MDA_DFMT1[8]; + }; +} TRDC_DomainAssignment_Type; + +/*!@brief TRDC MBC control register definition. */ +typedef struct _TRDC_MBC_Type +{ + __I uint32_t MBC_MEM_GLBCFG[4]; /**< MBC Global Configuration Register, array offset: 0x10000, array step: + index*0x2000, index2*0x4 */ + __IO uint32_t MBC_NSE_BLK_INDEX; /**< MBC NonSecure Enable Block Index, array offset: 0x10010, array step: 0x2000 */ + __O uint32_t MBC_NSE_BLK_SET; /**< MBC NonSecure Enable Block Set, array offset: 0x10014, array step: 0x2000 */ + __O uint32_t MBC_NSE_BLK_CLR; /**< MBC NonSecure Enable Block Clear, array offset: 0x10018, array step: 0x2000 */ + __O uint32_t + MBC_NSE_BLK_CLR_ALL; /**< MBC NonSecure Enable Block Clear All, array offset: 0x1001C, array step: 0x2000 */ + __IO uint32_t MBC_MEMN_GLBAC[8]; /**< MBC Global Access Control, array offset: 0x10020, array step: index*0x2000, + index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x10040, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10140, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10180, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x101A0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x101A8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x101C8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x101D0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM0_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x101F0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_0[72]; + __IO uint32_t MBC_DOM1_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x10240, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM1_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10340, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM1_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10380, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM1_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x103A0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM1_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x103A8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM1_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x103C8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM1_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x103D0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM1_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x103F0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_1[72]; + __IO uint32_t MBC_DOM2_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x10440, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM2_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10540, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM2_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10580, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM2_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x105A0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM2_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x105A8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM2_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x105C8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM2_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x105D0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM2_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x105F0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_2[72]; + __IO uint32_t MBC_DOM3_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x10640, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM3_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10740, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM3_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10780, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM3_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x107A0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM3_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x107A8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM3_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x107C8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM3_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x107D0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM3_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x107F0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_3[72]; + __IO uint32_t MBC_DOM4_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x10840, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM4_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10940, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM4_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10980, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM4_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x109A0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM4_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x109A8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM4_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x109C8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM4_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x109D0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM4_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x109F0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_4[72]; + __IO uint32_t MBC_DOM5_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x10A40, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM5_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10B40, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM5_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10B80, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM5_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10BA0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM5_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10BA8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM5_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10BC8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM5_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10BD0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM5_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10BF0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_5[72]; + __IO uint32_t MBC_DOM6_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x10C40, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM6_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10D40, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM6_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10D80, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM6_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10DA0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM6_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10DA8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM6_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10DC8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM6_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10DD0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM6_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10DF0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_7[72]; + __IO uint32_t MBC_DOM7_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x10E40, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM7_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10F40, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM7_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10F80, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM7_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10FA0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM7_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10FA8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM7_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10FC8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM7_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x10FD0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM7_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10FF0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_8[72]; + __IO uint32_t MBC_DOM8_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x11040, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM8_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11140, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM8_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11180, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM8_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x111A0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM8_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x111A8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM8_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x111C8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM8_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x111D0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM8_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x111F0, array + step: index*0x2000, index2*0x4 */ + + __IO uint32_t MBC_DOM9_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x11240, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM9_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11340, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM9_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11380, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM9_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x113A0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM9_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x113A8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM9_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x113C8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM9_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x113D0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM9_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x113F0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_9[72]; + __IO uint32_t MBC_DOM10_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x11440, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM10_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11540, + array step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM10_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11580, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM10_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x115A0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM10_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x115A8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM10_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x115C8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM10_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x115D0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM10_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x115F0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_10[72]; + __IO uint32_t MBC_DOM11_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x11640, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM11_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11740, + array step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM11_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11780, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM11_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x117A0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM11_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x117A8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM11_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x117C8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM11_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x117D0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM11_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x117F0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_11[72]; + __IO uint32_t MBC_DOM12_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x11840, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM12_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11940, + array step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM12_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11980, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM12_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x119A0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM12_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x119A8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM12_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x119C8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM12_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x119D0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM12_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x119F0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_12[72]; + __IO uint32_t MBC_DOM13_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x11A40, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM13_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11B40, + array step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM13_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11B80, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM13_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11BA0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM13_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11BA8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM13_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11BC8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM13_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11BD0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM13_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11BF0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_13[72]; + __IO uint32_t MBC_DOM14_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x11C40, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM14_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11D40, + array step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM14_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11D80, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM14_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11DA0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM14_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11DA8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM14_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11DC8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM14_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11DD0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM14_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11DF0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_14[72]; + __IO uint32_t MBC_DOM15_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x11E40, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM15_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11F40, + array step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM15_MEM1_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11F80, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM15_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11FA0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM15_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11FA8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM15_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11FC8, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM15_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11FD0, array + step: index*0x2000, index2*0x4 */ + __IO uint32_t MBC_DOM15_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11FF0, array + step: index*0x2000, index2*0x4 */ + uint8_t RESERVED_15[8]; +} TRDC_MBC_Type; + +/*!@brief TRDC MRC control register definition. MRC_DOM0_RGD_W[region][word] */ +typedef struct _TRDC_MRC_Type +{ + __I uint32_t MRC_GLBCFG; /**< MRC Global Configuration Register, array offset: 0x14000, array step: 0x1000 */ + uint8_t RESERVED_0[12]; + __IO uint32_t + MRC_NSE_RGN_INDIRECT; /**< MRC NonSecure Enable Region Indirect, array offset: 0x14010, array step: 0x1000 */ + __O uint32_t MRC_NSE_RGN_SET; /**< MRC NonSecure Enable Region Set, array offset: 0x14014, array step: 0x1000 */ + __O uint32_t MRC_NSE_RGN_CLR; /**< MRC NonSecure Enable Region Clear, array offset: 0x14018, array step: 0x1000 */ + __O uint32_t + MRC_NSE_RGN_CLR_ALL; /**< MRC NonSecure Enable Region Clear All, array offset: 0x1401C, array step: 0x1000 */ + __IO uint32_t + MRC_GLBAC[8]; /**< MRC Global Access Control, array offset: 0x14020, array step: index*0x1000, index2*0x4 */ + __IO uint32_t MRC_DOM0_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14040, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM0_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x140C0, array step: 0x1000 */ + uint8_t RESERVED_1[124]; + __IO uint32_t MRC_DOM1_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14140, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM1_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x141C0, array step: 0x1000 */ + uint8_t RESERVED_2[124]; + __IO uint32_t MRC_DOM2_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14240, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM2_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x142C0, array step: 0x1000 */ + uint8_t RESERVED_3[124]; + __IO uint32_t MRC_DOM3_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14340, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM3_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x143C0, array step: 0x1000 */ + uint8_t RESERVED_4[124]; + __IO uint32_t MRC_DOM4_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14440, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM4_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x144C0, array step: 0x1000 */ + uint8_t RESERVED_5[124]; + __IO uint32_t MRC_DOM5_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14540, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM5_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x145C0, array step: 0x1000 */ + uint8_t RESERVED_6[124]; + __IO uint32_t MRC_DOM6_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14640, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM6_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x146C0, array step: 0x1000 */ + uint8_t RESERVED_7[124]; + __IO uint32_t MRC_DOM7_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14740, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM7_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x147C0, array step: 0x1000 */ + uint8_t RESERVED_8[124]; + __IO uint32_t MRC_DOM8_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14840, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM8_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x148C0, array step: 0x1000 */ + uint8_t RESERVED_9[124]; + __IO uint32_t MRC_DOM9_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14940, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM9_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x149C0, array step: 0x1000 */ + uint8_t RESERVED_10[124]; + __IO uint32_t MRC_DOM10_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14A40, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM10_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14AC0, array step: 0x1000 */ + uint8_t RESERVED_11[124]; + __IO uint32_t MRC_DOM11_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14B40, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM11_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14BC0, array step: 0x1000 */ + uint8_t RESERVED_12[124]; + __IO uint32_t MRC_DOM12_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14C40, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM12_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14CC0, array step: 0x1000 */ + uint8_t RESERVED_13[124]; + __IO uint32_t MRC_DOM13_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14D40, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM13_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14DC0, array step: 0x1000 */ + uint8_t RESERVED_14[124]; + __IO uint32_t MRC_DOM14_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14E40, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM14_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14EC0, array step: 0x1000 */ + uint8_t RESERVED_15[124]; + __IO uint32_t MRC_DOM15_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset: + 0x14F40, array step: index*0x1000, index2*0x8, index3*0x4 */ + __IO uint32_t + MRC_DOM15_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14FC0, array step: 0x1000 */ +} TRDC_MRC_Type; + +/*!@brief TRDC base address convert macro */ +#define TRDC_GENERAL_BASE(base) ((TRDC_General_Type *)((base))) +#define TRDC_FLW_BASE(base) ((TRDC_FLW_Type *)(((uint32_t)(uintptr_t)(base) + (uint32_t)TRDC_FLW_OFFSET))) +#define TRDC_DOMAIN_ERROR_BASE(base) ((TRDC_DomainError_Type *)(((uint32_t)(uintptr_t)(base) + (uint32_t)TRDC_DOMAIN_ERROR_OFFSET))) +#define TRDC_DOMAIN_ASSIGNMENT_BASE(base) \ + ((TRDC_DomainAssignment_Type *)(((uint32_t)(uintptr_t)(base) + (uint32_t)TRDC_DOMAIN_ASSIGNMENT_OFFSET))) +#define TRDC_MBC_BASE(base, instance) \ + ((TRDC_MBC_Type *)((uint32_t)(uintptr_t)(base) + (uint32_t)TRDC_MBC_OFFSET(base) + (instance) * (uint32_t)TRDC_MBC_ARRAY_STEP)) +#define TRDC_MRC_BASE(base, instance) \ + ((TRDC_MRC_Type *)((uint32_t)(uintptr_t)(base) + (uint32_t)TRDC_MRC_OFFSET(base) + (instance) * (uint32_t)TRDC_MRC_ARRAY_STEP)) + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +/*! + * @} + */ + +#endif /* FSL_TRDC_CORE_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_trdc_soc.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_trdc_soc.h new file mode 100644 index 00000000000..978a2ef2200 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_trdc_soc.h @@ -0,0 +1,60 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_TRDC_SOC_H_ +#define _FSL_TRDC_SOC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup trdc_soc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + /* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.trdc_soc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief Driver version 2.0.0. */ +#define FSL_TRDC_SOC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +#define TRDC_MBC_MEM_GLBCFG_NBLKS_MASK 0x000003FFUL +#define TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_MASK 0x001F0000UL +#define TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT 16U +#define TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL(x) (((uint32_t)(x) & 0xFUL) << 8U) +#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL(x) (((uint32_t)(x) & 0x1UL) << 16U) + +/*!@brief TRDC feature */ +#define FSL_FEATURE_TRDC_DOMAIN_COUNT 1 + +/*!@brief TRDC base address convert macro */ +#define TRDC_MBC_COUNT 1 +#define TRDC_MBC_OFFSET(x) 0x0000 /* MBC register offset in TRDC_Type structure. */ +#define TRDC_MBC_ARRAY_STEP 0U /* Offset between two MBC control block, useless if there is only one. */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +/*! + * @} + */ + +#endif /* _FSL_TRDC_SOC_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_utick.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_utick.c new file mode 100644 index 00000000000..0eea419cd34 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_utick.c @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019, 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_utick.h" +#if !(defined(FSL_FEATURE_UTICK_HAS_NO_PDCFG) && FSL_FEATURE_UTICK_HAS_NO_PDCFG) +#include "fsl_power.h" +#endif +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.utick" +#endif + +/* Typedef for interrupt handler. */ +typedef void (*utick_isr_t)(UTICK_Type *base, utick_callback_t cb); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base UTICK peripheral base address + * + * @return The UTICK instance + */ +static uint32_t UTICK_GetInstance(UTICK_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of UTICK handle. */ +static utick_callback_t s_utickHandle[FSL_FEATURE_SOC_UTICK_COUNT]; +/* Array of UTICK peripheral base address. */ +static UTICK_Type *const s_utickBases[] = UTICK_BASE_PTRS; +/* Array of UTICK IRQ number. */ +static const IRQn_Type s_utickIRQ[] = UTICK_IRQS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of UTICK clock name. */ +static const clock_ip_name_t s_utickClock[] = UTICK_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_UTICK_HAS_NO_RESET) && FSL_FEATURE_UTICK_HAS_NO_RESET) +/*! @brief Pointers to UTICK resets for each instance. */ +static const reset_ip_name_t s_utickResets[] = UTICK_RSTS; +#endif + +/* UTICK ISR for transactional APIs. */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +static utick_isr_t s_utickIsr = (utick_isr_t)DefaultISR; +#else +static utick_isr_t s_utickIsr; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t UTICK_GetInstance(UTICK_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_utickBases); instance++) + { + if (s_utickBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_utickBases)); + + return instance; +} + +/*! + * brief Starts UTICK. + * + * This function starts a repeat/onetime countdown with an optional callback + * + * param base UTICK peripheral base address. + * param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) + * param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) + * param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) + * return none + */ +void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb) +{ + uint32_t instance; + + /* Get instance from peripheral base address. */ + instance = UTICK_GetInstance(base); + + /* Save the handle in global variables to support the double weak mechanism. */ + s_utickHandle[instance] = cb; +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) && \ + !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)) + EnableDeepSleepIRQ(s_utickIRQ[instance]); +#else + (void)EnableIRQ(s_utickIRQ[instance]); +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT && !FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ + base->CTRL = count | UTICK_CTRL_REPEAT(mode); +} + +/*! + * brief Initializes an UTICK by turning its bus clock on + * + */ +void UTICK_Init(UTICK_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable utick clock */ + CLOCK_EnableClock(s_utickClock[UTICK_GetInstance(base)]); +#endif + +#if !(defined(FSL_FEATURE_UTICK_HAS_NO_RESET) && FSL_FEATURE_UTICK_HAS_NO_RESET) + RESET_PeripheralReset(s_utickResets[UTICK_GetInstance(base)]); +#endif + +#if !(defined(FSL_FEATURE_UTICK_HAS_NO_PDCFG) && FSL_FEATURE_UTICK_HAS_NO_PDCFG) + /* Power up Watchdog oscillator*/ + POWER_DisablePD(kPDRUNCFG_PD_WDT_OSC); +#endif + + s_utickIsr = UTICK_HandleIRQ; +} + +/*! + * brief Deinitializes a UTICK instance. + * + * This function shuts down Utick bus clock + * + * param base UTICK peripheral base address. + */ +void UTICK_Deinit(UTICK_Type *base) +{ + /* Turn off utick */ + base->CTRL = 0; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable utick clock */ + CLOCK_DisableClock(s_utickClock[UTICK_GetInstance(base)]); +#endif +} + +/*! + * brief Get Status Flags. + * + * This returns the status flag + * + * param base UTICK peripheral base address. + * return status register value + */ +uint32_t UTICK_GetStatusFlags(UTICK_Type *base) +{ + return (base->STAT); +} + +/*! + * brief Clear Status Interrupt Flags. + * + * This clears intr status flag + * + * param base UTICK peripheral base address. + * return none + */ +void UTICK_ClearStatusFlags(UTICK_Type *base) +{ + base->STAT = UTICK_STAT_INTR_MASK; +} + +/*! + * brief UTICK Interrupt Service Handler. + * + * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request + * in UTICK_SetTick()). + * if no user callback is scheduled, the interrupt will simply be cleared. + * + * param base UTICK peripheral base address. + * param cb callback scheduled for this instance of UTICK + * return none + */ +void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb) +{ + UTICK_ClearStatusFlags(base); + if (cb != NULL) + { + cb(); + } +} + +#if defined(UTICK0) +void UTICK0_DriverIRQHandler(void); +void UTICK0_DriverIRQHandler(void) +{ + s_utickIsr(UTICK0, s_utickHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#if defined(UTICK1) +void UTICK1_DriverIRQHandler(void); +void UTICK1_DriverIRQHandler(void) +{ + s_utickIsr(UTICK1, s_utickHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#if defined(UTICK2) +void UTICK2_DriverIRQHandler(void); +void UTICK2_DriverIRQHandler(void) +{ + s_utickIsr(UTICK2, s_utickHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +#endif +#if defined(UTICK) +void UTICK_DriverIRQHandler(void); +void UTICK_DriverIRQHandler(void) +{ + s_utickIsr(UTICK, s_utickHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_utick.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_utick.h new file mode 100644 index 00000000000..a3b734eae47 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_utick.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019, 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_UTICK_H_ +#define FSL_UTICK_H_ + +#include "fsl_common.h" +/*! + * @addtogroup utick + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief UTICK driver version 2.0.5. */ +#define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) +/*! @} */ + +/*! @brief UTICK timer operational mode. */ +typedef enum _utick_mode +{ + kUTICK_Onetime = 0x0U, /*!< Trigger once*/ + kUTICK_Repeat = 0x1U, /*!< Trigger repeatedly */ +} utick_mode_t; + +/*! @brief UTICK callback function. */ +typedef void (*utick_callback_t)(void); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an UTICK by turning its bus clock on + * + */ +void UTICK_Init(UTICK_Type *base); + +/*! + * @brief Deinitializes a UTICK instance. + * + * This function shuts down Utick bus clock + * + * @param base UTICK peripheral base address. + */ +void UTICK_Deinit(UTICK_Type *base); +/*! + * @brief Get Status Flags. + * + * This returns the status flag + * + * @param base UTICK peripheral base address. + * @return status register value + */ +uint32_t UTICK_GetStatusFlags(UTICK_Type *base); +/*! + * @brief Clear Status Interrupt Flags. + * + * This clears intr status flag + * + * @param base UTICK peripheral base address. + * @return none + */ +void UTICK_ClearStatusFlags(UTICK_Type *base); + +/*! + * @brief Starts UTICK. + * + * This function starts a repeat/onetime countdown with an optional callback + * + * @param base UTICK peripheral base address. + * @param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) + * @param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat) + * @param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void)) + * @return none + */ +void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb); +/*! + * @brief UTICK Interrupt Service Handler. + * + * This function handles the interrupt and refers to the callback array in the driver to callback user (as per request + * in UTICK_SetTick()). + * if no user callback is scheduled, the interrupt will simply be cleared. + * + * @param base UTICK peripheral base address. + * @param cb callback scheduled for this instance of UTICK + * @return none + */ +void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_UTICK_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_vbat.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_vbat.c new file mode 100644 index 00000000000..60f97571576 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_vbat.c @@ -0,0 +1,498 @@ +/* + * Copyright 2022-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_vbat.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.mcx_vbat" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Configure internal 16kHz free running oscillator, including enabel FRO16k, gate FRO16k output. + * + * param base VBAT peripheral base address. + * param config Pointer to vbat_fro16k_config_t structure. + */ +void VBAT_ConfigFRO16k(VBAT_Type *base, const vbat_fro16k_config_t *config) +{ + assert(config != NULL); + + VBAT_EnableFRO16k(base, config->enableFRO16k); + VBAT_UngateFRO16k(base, config->enabledConnectionsMask); +} + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) +/*! + * brief Set 32k crystal oscillator mode and load capacitance for the XTAL/EXTAL pin. + * + * param base VBAT peripheral base address. + * param operateMode Specify the crystal oscillator mode, please refer to vbat_osc32k_operate_mode_t. + * param xtalCap Specify the internal capacitance for the XTAL pin from the capacitor bank. + * param extalCap Specify the internal capacitance for the EXTAL pin from the capacitor bank. + * + * retval kStatus_VBAT_WrongCapacitanceValue The load capacitance value to set is not align with operate mode's + * requirements. + * retval kStatus_Success Success to set operate mode and load capacitance. + */ +status_t VBAT_SetCrystalOsc32kModeAndLoadCapacitance(VBAT_Type *base, + vbat_osc32k_operate_mode_t operateMode, + vbat_osc32k_load_capacitance_select_t xtalCap, + vbat_osc32k_load_capacitance_select_t extalCap) +{ + if (operateMode == kVBAT_Osc32kEnabledToTransconductanceMode) + { + if (((uint8_t)extalCap & 0x1U) == 0U) + { + return kStatus_VBAT_WrongCapacitanceValue; + } + } + + if (operateMode == kVBAT_Osc32kEnabledToLowPowerSwitchedMode) + { + if ((extalCap != kVBAT_Osc32kCrystalLoadCap0pF) && (xtalCap != kVBAT_Osc32kCrystalLoadCap0pF)) + { + return kStatus_VBAT_WrongCapacitanceValue; + } + } + + if (operateMode == kVBAT_Osc32kEnabledToLowPowerBackupMode) + { + if (((uint8_t)extalCap & 0x1U) != 0U) + { + return kStatus_VBAT_WrongCapacitanceValue; + } + } + + if ((xtalCap != kVBAT_Osc32kCrystalLoadCapBankDisabled) && (extalCap != kVBAT_Osc32kCrystalLoadCapBankDisabled)) + { + base->OSCCTLA |= VBAT_OSCCTLA_CAP_SEL_EN_MASK; + base->OSCCTLB &= ~VBAT_OSCCTLA_CAP_SEL_EN_MASK; + base->OSCCTLA = ((base->OSCCTLA & ~(VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK | VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)) | + (VBAT_OSCCTLA_XTAL_CAP_SEL(xtalCap) | VBAT_OSCCTLA_EXTAL_CAP_SEL(extalCap))); + base->OSCCTLB = ((base->OSCCTLB & ~(VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK | VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)) | + VBAT_OSCCTLA_XTAL_CAP_SEL(~(uint32_t)xtalCap) | VBAT_OSCCTLA_EXTAL_CAP_SEL(~(uint32_t)extalCap)); + } + + base->OSCCTLA = (((base->OSCCTLA & ~VBAT_OSCCTLA_MODE_EN_MASK)) | VBAT_OSCCTLA_MODE_EN(operateMode)); + base->OSCCTLB = ((base->OSCCTLB & ~VBAT_OSCCTLA_MODE_EN_MASK) | VBAT_OSCCTLA_MODE_EN(~(uint32_t)operateMode)); + + return kStatus_Success; +} +#endif /* FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) +/*! + * brief Enable/disable Bandgap. + * + * note The FRO16K must be enabled before enableing the bandgap. + * note This setting can be locked by VBAT_LockRamLdoSettings() function. + * + * param base VBAT peripheral base address. + * param enable Used to enable/disable bandgap. + * - \b true Enable the bandgap. + * - \b false Disable the bandgap. + * + * retval kStatus_Success Success to enable/disable the bandgap. + * retval kStatus_VBAT_Fro16kNotEnabled Fail to enable the bandgap due to FRO16k is not enabled previously. + */ +status_t VBAT_EnableBandgap(VBAT_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + if (VBAT_CheckFRO16kEnabled(base)) + { + base->LDOCTLA |= VBAT_LDOCTLA_BG_EN_MASK; + base->LDOCTLB &= ~VBAT_LDOCTLA_BG_EN_MASK; + } + else + { + /* FRO16K must be enabled before enabling the Bandgap. */ + status = kStatus_VBAT_Fro16kNotEnabled; + } + } + else + { + base->LDOCTLA &= ~VBAT_LDOCTLA_BG_EN_MASK; + base->LDOCTLB |= VBAT_LDOCTLA_BG_EN_MASK; + } + + return status; +} + +/*! + * brief Enable/disable Backup RAM Regulator(RAM_LDO). + * + * note This setting can be locked by VBAT_LockRamLdoSettings() function. + * + * param base VBAT peripheral base address. + * param enable Used to enable/disable RAM_LDO. + * - \b true Enable backup SRAM regulator. + * - \b false Disable backup SRAM regulator. + * + * retval kStatusSuccess Success to enable/disable backup SRAM regulator. + * retval kStatus_VBAT_Fro16kNotEnabled Fail to enable backup SRAM regulator due to FRO16k is not enabled previously. + * retval kStatus_VBAT_BandgapNotEnabled Fail to enable backup SRAM regulator due to the bandgap is not enabled + * previously. + */ +status_t VBAT_EnableBackupSRAMRegulator(VBAT_Type *base, bool enable) +{ + status_t status = kStatus_Success; + + if (enable) + { + if (VBAT_CheckFRO16kEnabled(base)) + { + if (VBAT_CheckBandgapEnabled(base)) + { + base->LDOCTLA |= VBAT_LDOCTLA_LDO_EN_MASK; + base->LDOCTLB &= ~VBAT_LDOCTLA_LDO_EN_MASK; + /* Polling until LDO is enabled. */ + while ((base->STATUSA & VBAT_STATUSA_LDO_RDY_MASK) == 0UL) + { + } + } + else + { + /* The bandgap must be enabled previously. */ + status = kStatus_VBAT_BandgapNotEnabled; + } + } + else + { + /* FRO16k must be enabled previously. */ + status = kStatus_VBAT_Fro16kNotEnabled; + } + } + else + { + base->LDOCTLA &= ~VBAT_LDOCTLA_LDO_EN_MASK; + base->LDOCTLB |= VBAT_LDOCTLA_LDO_EN_MASK; + } + + return status; +} + +/*! + * brief Switch the SRAM to be powered by VBAT. + * + * param base VBAT peripheral base address. + * + * retval kStatusSuccess Success to Switch SRAM powered by VBAT. + * retval kStatus_VBAT_Fro16kNotEnabled Fail to switch SRAM powered by VBAT due to FRO16K not enabled previously. + */ +status_t VBAT_SwitchSRAMPowerByLDOSRAM(VBAT_Type *base) +{ + status_t status = kStatus_Success; + + status = VBAT_EnableBandgap(base, true); + + if (status == kStatus_Success) + { + VBAT_EnableBandgapRefreshMode(base, true); + (void)VBAT_EnableBackupSRAMRegulator(base, true); + + /* Isolate the SRAM array */ + base->LDORAMC |= VBAT_LDORAMC_ISO_MASK; + /* Switch the supply to VBAT LDO. */ + base->LDORAMC |= VBAT_LDORAMC_SWI_MASK; + } + + return status; +} +#endif /* FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) && FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) +/*! + * brief Enable/disable Bandgap timer. + * + * note The bandgap timer is available when the bandgap is enabled and are clocked by the FRO16k. + * + * param base VBAT peripheral base address. + * param enable Used to enable/disable bandgap timer. + * param timerIdMask The mask of bandgap timer Id, should be the OR'ed value of vbat_bandgap_timer_id_t. + * + * retval kStatus_Success Success to enable/disable selected bandgap timer. + * retval kStatus_VBAT_Fro16kNotEnabled Fail to enable/disable selected bandgap timer due to FRO16k not enabled + * previously. retval kStatus_VBAT_BandgapNotEnabled Fail to enable/disable selected bandgap timer due to bandgap not + * enabled previously. + */ +status_t VBAT_EnableBandgapTimer(VBAT_Type *base, bool enable, uint8_t timerIdMask) +{ + status_t status = kStatus_Success; + + if (enable) + { + if (VBAT_CheckFRO16kEnabled(base)) + { + if (VBAT_CheckBandgapEnabled(base)) + { + if ((timerIdMask & (uint8_t)kVBAT_BandgapTimer0) != 0U) + { + base->LDOTIMER0 |= VBAT_LDOTIMER0_TIMEN_MASK; + } + + if ((timerIdMask & (uint8_t)kVBAT_BandgapTimer1) != 0U) + { + base->LDOTIMER1 |= VBAT_LDOTIMER1_TIMEN_MASK; + } + } + else + { + /* Bandgap must be enabled previously. */ + status = kStatus_VBAT_BandgapNotEnabled; + } + } + else + { + /* FRO16K must be enabled previously. */ + status = kStatus_VBAT_Fro16kNotEnabled; + } + } + else + { + if ((timerIdMask & (uint8_t)kVBAT_BandgapTimer0) != 0U) + { + base->LDOTIMER0 &= ~VBAT_LDOTIMER0_TIMEN_MASK; + } + + if ((timerIdMask & (uint8_t)kVBAT_BandgapTimer1) != 0U) + { + base->LDOTIMER1 &= ~VBAT_LDOTIMER1_TIMEN_MASK; + } + } + + return status; +} + +/*! + * brief Set bandgap timer0 timeout value. + * + * param base VBAT peripheral base address. + * param timeoutPeriod Bandgap timer timeout value, please refer to vbat_bandgap_timer0_timeout_period_t. + */ +void VBAT_SetBandgapTimer0TimeoutValue(VBAT_Type *base, vbat_bandgap_timer0_timeout_period_t timeoutPeriod) +{ + bool timerEnabled = false; + + timerEnabled = ((base->LDOTIMER0 & VBAT_LDOTIMER0_TIMEN_MASK) != 0UL) ? true : false; + + if (timerEnabled) + { + base->LDOTIMER0 &= ~VBAT_LDOTIMER0_TIMEN_MASK; + } + + base->LDOTIMER0 = ((base->LDOTIMER0 & (~VBAT_LDOTIMER0_TIMCFG_MASK)) | VBAT_LDOTIMER0_TIMCFG(timeoutPeriod)); + + if (timerEnabled) + { + base->LDOTIMER0 |= VBAT_LDOTIMER0_TIMEN_MASK; + } +} + +/*! + * brief Set bandgap timer1 timeout value. + * + * note The timeout value can only be changed when the timer is disabled. + * + * param base VBAT peripheral base address. + * param timeoutPeriod The bandgap timerout 1 period, in number of seconds, ranging from 0 to 65535s. + */ +void VBAT_SetBandgapTimer1TimeoutValue(VBAT_Type *base, uint32_t timeoutPeriod) +{ + bool timerEnabled = false; + + timerEnabled = ((base->LDOTIMER1 & VBAT_LDOTIMER1_TIMEN_MASK) != 0UL) ? true : false; + + if (timerEnabled) + { + base->LDOTIMER1 &= ~VBAT_LDOTIMER1_TIMEN_MASK; + } + + base->LDOTIMER1 = ((base->LDOTIMER1 & (~VBAT_LDOTIMER1_TIMCFG_MASK)) | VBAT_LDOTIMER1_TIMCFG(timeoutPeriod)); + + if (timerEnabled) + { + base->LDOTIMER1 |= VBAT_LDOTIMER1_TIMEN_MASK; + } +} +#endif /* FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) && FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) +/*! + * brief Initializes the VBAT clock monitor, enable clock monitor and set the clock monitor configuration. + * + * note Both FRO16K and OSC32K should be enabled and stable before invoking this function. + * + * param base VBAT peripheral base address. + * param config Pointer to vbat_clock_monitor_config_t structure. + * + * retval kStatus_Success Clock monitor is initialized successfully. + * retval kStatus_VBAT_Fro16kNotEnabled FRO16K is not enabled. + * retval kStatus_VBAT_Osc32kNotReady OSC32K is not ready. + * retval kStatus_VBAT_ClockMonitorLocked Clock monitor is locked. + */ +status_t VBAT_InitClockMonitor(VBAT_Type *base, const vbat_clock_monitor_config_t *config) +{ + assert(config != NULL); + + status_t status = kStatus_Success; + + if (VBAT_CheckFRO16kEnabled(base)) + { + if ((VBAT_GetStatusFlags(base) & kVBAT_StatusFlagOsc32kReady) != 0UL) + { + if (VBAT_CheckClockMonitorControlLocked(base)) + { + status = kStatus_VBAT_ClockMonitorLocked; + } + else + { + /* Disable clock monitor before configuring clock monitor. */ + VBAT_EnableClockMonitor(base, false); + /* Set clock monitor divide trim value. */ + VBAT_SetClockMonitorDivideTrim(base, config->divideTrim); + /* Set clock monitor frequency trim value. */ + VBAT_SetClockMonitorFrequencyTrim(base, config->freqTrim); + /* Enable clock monitor. */ + VBAT_EnableClockMonitor(base, true); + + if (config->lock) + { + VBAT_LockClockMonitorControl(base); + } + } + } + else + { + status = kStatus_VBAT_OSC32KNotReady; + } + } + else + { + status = kStatus_VBAT_Fro16kNotEnabled; + } + + return status; +} + +/*! + * brief Deinitialize the VBAT clock monitor. + * + * param base VBAT peripheral base address. + * + * retval kStatus_Success Clock monitor is de-initialized successfully. + * retval kStatus_VBAT_ClockMonitorLocked Control of Clock monitor is locked. + */ +status_t VBAT_DeinitMonitor(VBAT_Type *base) +{ + if (VBAT_CheckClockMonitorControlLocked(base)) + { + return kStatus_VBAT_ClockMonitorLocked; + } + + VBAT_EnableClockMonitor(base, false); + + return kStatus_Success; +} +#endif /* FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) && FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) +/*! + * brief Initialize tamper control. + * + * note Both FRO16K and bandgap should be enabled before calling this function. + * + * param base VBAT peripheral base address. + * param config Pointer to vbat_tamper_config_t structure. + * + * retval kStatus_Success Tamper is initialized successfully. + * retval kStatus_VBAT_TamperLocked Tamper control is locked. + * retval kStatus_VBAT_BandgapNotEnabled Bandgap is not enabled. + * retval kStatus_VBAT_Fro16kNotEnabled FRO 16K is not enabled. + */ +status_t VBAT_InitTamper(VBAT_Type *base, const vbat_tamper_config_t *config) +{ + assert(config != NULL); + + status_t status = kStatus_Success; + + if (VBAT_CheckFRO16kEnabled(base)) + { + if (VBAT_CheckBandgapEnabled(base)) + { + if (VBAT_CheckTamperControlLocked(base)) + { + return kStatus_VBAT_TamperLocked; + } + else + { + base->TAMCTLA = ((base->TAMCTLA & (~VBAT_TAMCTLA_VOLT_EN_MASK | VBAT_TAMCTLA_TEMP_EN_MASK)) | + VBAT_TAMCTLA_VOLT_EN(config->enableVoltageDetect) | + VBAT_TAMCTLA_TEMP_EN(config->enableTemperatureDetect)); + base->TAMCTLB = ((base->TAMCTLB & (~VBAT_TAMCTLA_VOLT_EN_MASK | VBAT_TAMCTLA_TEMP_EN_MASK)) | + VBAT_TAMCTLA_VOLT_EN((config->enableVoltageDetect) ? 0U : 1U) | + VBAT_TAMCTLA_TEMP_EN((config->enableTemperatureDetect) ? 0U : 1U)); + + if (config->lock) + { + VBAT_LockTamperControl(base); + } + } + } + else + { + status = kStatus_VBAT_BandgapNotEnabled; + } + } + else + { + status = kStatus_VBAT_Fro16kNotEnabled; + } + + return status; +} + +/*! + * brief De-initialize tamper control. + * + * param base VBAT peripheral base address. + * + * retval kStatus_Success Tamper is de-initialized successfully. + * retval kStatus_VBAT_TamperLocked Tamper control is locked. + */ +status_t VBAT_DeinitTamper(VBAT_Type *base) +{ + if (VBAT_CheckTamperControlLocked(base)) + { + return kStatus_VBAT_TamperLocked; + } + + base->TAMCTLA &= ~(VBAT_TAMCTLA_VOLT_EN_MASK | VBAT_TAMCTLA_TEMP_EN_MASK); + base->TAMCTLB |= (VBAT_TAMCTLA_VOLT_EN_MASK | VBAT_TAMCTLA_TEMP_EN_MASK); + + return kStatus_Success; +} +#endif /* FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_vbat.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_vbat.h new file mode 100644 index 00000000000..5858b005eb9 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_vbat.h @@ -0,0 +1,1386 @@ +/* + * Copyright 2022-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef FSL_VBAT_H_ +#define FSL_VBAT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup mcx_vbat + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief VBAT driver version 2.3.1. */ +#define FSL_VBAT_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) +/*@}*/ + +#if !defined(VBAT_LDORAMC_RET_MASK) +#define VBAT_LDORAMC_RET_MASK (0xF00U) +#define VBAT_LDORAMC_RET_SHIFT (8U) +#define VBAT_LDORAMC_RET(x) (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET_SHIFT)) & VBAT_LDORAMC_RET_MASK) +#endif + +/*! + * @brief The enumeration of VBAT module status. + */ +enum +{ + kStatus_VBAT_Fro16kNotEnabled = MAKE_STATUS(kStatusGroup_VBAT, 0), /*!< Internal 16kHz free running + oscillator not enabled. */ + kStatus_VBAT_BandgapNotEnabled = MAKE_STATUS(kStatusGroup_VBAT, 1), /*!< Bandgap not enabled. */ + kStatus_VBAT_WrongCapacitanceValue = MAKE_STATUS(kStatusGroup_VBAT, 2), /*!< Wrong capacitance for + selected oscillator mode. */ + kStatus_VBAT_ClockMonitorLocked = MAKE_STATUS(kStatusGroup_VBAT, 3), /*!< Clock monitor locked. */ + kStatus_VBAT_OSC32KNotReady = MAKE_STATUS(kStatusGroup_VBAT, 4), /*!< OSC32K not ready. */ + kStatus_VBAT_LDONotReady = MAKE_STATUS(kStatusGroup_VBAT, 5), /*!< LDO not ready. */ + kStatus_VBAT_TamperLocked = MAKE_STATUS(kStatusGroup_VBAT, 6), /*!< Tamper locked. */ +}; + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG) && FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG) +/*! + * @brief The enumeration of VBAT status flags. + * + * @anchor vbat_status_flag_t + */ +enum _vbat_status_flag +{ + kVBAT_StatusFlagPORDetect = VBAT_STATUSA_POR_DET_MASK, /*!< VBAT domain has been reset */ + kVBAT_StatusFlagWakeupPin = VBAT_STATUSA_WAKEUP_FLAG_MASK, /*!< A falling edge is detected on the wakeup pin. */ + kVBAT_StatusFlagBandgapTimer0 = VBAT_STATUSA_TIMER0_FLAG_MASK, /*!< Bandgap Timer0 period reached. */ + kVBAT_StatusFlagBandgapTimer1 = VBAT_STATUSA_TIMER1_FLAG_MASK, /*!< Bandgap Timer1 period reached. */ + kVBAT_StatusFlagLdoReady = VBAT_STATUSA_LDO_RDY_MASK, /*!< LDO is enabled and ready. */ + kVBAT_StatusFlagOsc32kReady = VBAT_STATUSA_OSC_RDY_MASK, /*!< OSC32k is enabled and clock is ready. */ +#if defined(VBAT_STATUSA_CLOCK_DET_MASK) + kVBAT_StatusFlagClockDetect = VBAT_STATUSA_CLOCK_DET_MASK, /*!< The clock monitor has detected an error. */ +#endif /* VBAT_STATUSA_CLOCK_DET_MASK */ + kVBAT_StatusFlagConfigDetect = VBAT_STATUSA_CONFIG_DET_MASK, /*!< Configuration error detected. */ +#if defined(VBAT_STATUSA_VOLT_DET_MASK) + kVBAT_StatusFlagVoltageDetect = VBAT_STATUSA_VOLT_DET_MASK, /*!< Voltage monitor has detected + an error with VBAT supply. */ +#endif /* VBAT_STATUSA_VOLT_DET_MASK */ +#if defined(VBAT_STATUSA_TEMP_DET_MASK) + kVBAT_StatusFlagTemperatureDetect = VBAT_STATUSA_TEMP_DET_MASK, /*!< Temperature monitor has detected an error. */ +#endif /* VBAT_STATUSA_TEMP_DET_MASK */ +#if defined(VBAT_STATUSA_SEC0_DET_MASK) + kVBAT_StatusFlagSec0Detect = VBAT_STATUSA_SEC0_DET_MASK, /*!< Security input 0 has detected an error. */ +#endif /* VBAT_STATUSA_SEC0_DET_MASK */ + kVBAT_StatusFlagInterrupt0Detect = VBAT_STATUSA_IRQ0_DET_MASK, /*!< Interrupt 0 asserted. */ + kVBAT_StatusFlagInterrupt1Detect = VBAT_STATUSA_IRQ1_DET_MASK, /*!< Interrupt 1 asserted. */ + kVBAT_StatusFlagInterrupt2Detect = VBAT_STATUSA_IRQ2_DET_MASK, /*!< Interrupt 2 asserted. */ + kVBAT_StatusFlagInterrupt3Detect = VBAT_STATUSA_IRQ3_DET_MASK, /*!< Interrupt 2 asserted. */ +}; + +/*! + * @brief The enumeration of VBAT interrupt enable. + * + * @anchor vbat_interrupt_enable_t + */ +enum _vbat_interrupt_enable +{ + kVBAT_InterruptEnablePORDetect = VBAT_IRQENA_POR_DET_MASK, /*!< Enable POR detect interrupt. */ + kVBAT_InterruptEnableWakeupPin = VBAT_IRQENA_WAKEUP_FLAG_MASK, /*!< Enable the interrupt when a falling edge is + detected on the wakeup pin. */ + kVBAT_InterruptEnableBandgapTimer0 = VBAT_IRQENA_TIMER0_FLAG_MASK, /*!< Enable the interrupt if Bandgap + Timer0 period reached. */ + kVBAT_InterruptEnableBandgapTimer1 = VBAT_IRQENA_TIMER1_FLAG_MASK, /*!< Enable the interrupt if Bandgap + Timer1 period reached. */ + kVBAT_InterruptEnableLdoReady = VBAT_IRQENA_LDO_RDY_MASK, /*!< Enable LDO ready interrupt. */ + kVBAT_InterruptEnableOsc32kReady = VBAT_IRQENA_OSC_RDY_MASK, /*!< Enable OSC32K ready interrupt. */ +#if defined(VBAT_IRQENA_CLOCK_DET_MASK) + kVBAT_InterruptEnableClockDetect = VBAT_IRQENA_CLOCK_DET_MASK, /*!< Enable clock monitor detect interrupt. */ +#endif /* VBAT_IRQENA_CLOCK_DET_MASK */ + kVBAT_InterruptEnableConfigDetect = + VBAT_IRQENA_CONFIG_DET_MASK, /*!< Enable configuration error detected interrupt. */ +#if defined(VBAT_IRQENA_VOLT_DET_MASK) + kVBAT_InterruptEnableVoltageDetect = VBAT_IRQENA_VOLT_DET_MASK, /*!< Enable voltage monitor detect interrupt. */ +#endif /* VBAT_IRQENA_VOLT_DET_MASK */ +#if defined(VBAT_IRQENA_TEMP_DET_MASK) + kVBAT_InterruptEnableTemperatureDetect = VBAT_IRQENA_TEMP_DET_MASK, /*!< Enable temperature monitor detect + interrupt. */ +#endif /* VBAT_IRQENA_TEMP_DET_MASK */ +#if defined(VBAT_IRQENA_SEC0_DET_MASK) + kVBAT_InterruptEnableSec0Detect = VBAT_IRQENA_SEC0_DET_MASK, /*!< Enable security input 0 detect interrupt. */ +#endif /* VBAT_IRQENA_SEC0_DET_MASK */ + kVBAT_InterruptEnableInterrupt0 = VBAT_IRQENA_IRQ0_DET_MASK, /*!< Enable the interrupt0. */ + kVBAT_InterruptEnableInterrupt1 = VBAT_IRQENA_IRQ1_DET_MASK, /*!< Enable the interrupt1. */ + kVBAT_InterruptEnableInterrupt2 = VBAT_IRQENA_IRQ2_DET_MASK, /*!< Enable the interrupt2. */ + kVBAT_InterruptEnableInterrupt3 = VBAT_IRQENA_IRQ3_DET_MASK, /*!< Enable the interrupt3. */ + + kVBAT_AllInterruptsEnable = + (VBAT_IRQENA_POR_DET_MASK | VBAT_IRQENA_WAKEUP_FLAG_MASK | VBAT_IRQENA_TIMER0_FLAG_MASK | + VBAT_IRQENA_TIMER1_FLAG_MASK | VBAT_IRQENA_LDO_RDY_MASK | VBAT_IRQENA_OSC_RDY_MASK | + VBAT_IRQENA_CONFIG_DET_MASK | VBAT_IRQENA_IRQ0_DET_MASK | VBAT_IRQENA_IRQ1_DET_MASK | + VBAT_IRQENA_IRQ2_DET_MASK | VBAT_IRQENA_IRQ3_DET_MASK), /*!< Enable all interrupts. */ +}; + +/*! + * @brief The enumeration of VBAT wakeup enable. + * + * @anchor vbat_wakeup_enable_t + */ +enum _vbat_wakeup_enable +{ + kVBAT_WakeupEnablePORDetect = VBAT_WAKENA_POR_DET_MASK, /*!< Enable POR detect wakeup. */ + kVBAT_WakeupEnableWakeupPin = VBAT_WAKENA_WAKEUP_FLAG_MASK, /*!< Enable wakeup feature when a falling edge is + detected on the wakeup pin. */ + kVBAT_WakeupEnableBandgapTimer0 = VBAT_WAKENA_TIMER0_FLAG_MASK, /*!< Enable wakeup feature when bandgap + timer0 period reached. */ + kVBAT_WakeupEnableBandgapTimer1 = VBAT_WAKENA_TIMER1_FLAG_MASK, /*!< Enable wakeup feature when bandgap + timer1 period reached. */ + kVBAT_WakeupEnableLdoReady = VBAT_WAKENA_LDO_RDY_MASK, /*!< Enable wakeup when LDO ready. */ + kVBAT_WakeupEnableOsc32kReady = VBAT_WAKENA_OSC_RDY_MASK, /*!< Enable wakeup when OSC32k ready. */ +#if defined(VBAT_WAKENA_CLOCK_DET_MASK) + kVBAT_WakeupEnableClockDetect = + VBAT_WAKENA_CLOCK_DET_MASK, /*!< Enable wakeup when clock monitor detect an error. */ +#endif /* VBAT_WAKENA_CLOCK_DET_MASK */ + kVBAT_WakeupEnableConfigDetect = VBAT_WAKENA_CONFIG_DET_MASK, /*!< Enable wakeup when + configuration error detected. */ +#if defined(VBAT_WAKENA_VOLT_DET_MASK) + kVBAT_WakeupEnableVoltageDetect = VBAT_WAKENA_VOLT_DET_MASK, /*!< Enable wakeup when voltage monitor detect an + error. */ +#endif /* VBAT_WAKENA_VOLT_DET_MASK */ +#if defined(VBAT_WAKENA_TEMP_DET_MASK) + kVBAT_WakeupEnableTemperatureDetect = VBAT_WAKENA_TEMP_DET_MASK, /*!< Enable wakeup when temperature monitor + detect an error. */ +#endif /* VBAT_WAKENA_TEMP_DET_MASK */ +#if defined(VBAT_WAKENA_SEC0_DET_MASK) + kVBAT_WakeupEnableSec0Detect = VBAT_WAKENA_SEC0_DET_MASK, /*!< Enable wakeup when security input 0 detect an + error. */ +#endif /* VBAT_WAKENA_SEC0_DET_MASK */ + kVBAT_WakeupEnableInterrupt0 = VBAT_WAKENA_IRQ0_DET_MASK, /*!< Enable wakeup when interrupt0 asserted. */ + kVBAT_WakeupEnableInterrupt1 = VBAT_WAKENA_IRQ1_DET_MASK, /*!< Enable wakeup when interrupt1 asserted. */ + kVBAT_WakeupEnableInterrupt2 = VBAT_WAKENA_IRQ2_DET_MASK, /*!< Enable wakeup when interrupt2 asserted. */ + kVBAT_WakeupEnableInterrupt3 = VBAT_WAKENA_IRQ3_DET_MASK, /*!< Enable wakeup when interrupt3 asserted. */ + + kVBAT_AllWakeupsEnable = (VBAT_WAKENA_POR_DET_MASK | VBAT_WAKENA_WAKEUP_FLAG_MASK | VBAT_WAKENA_TIMER0_FLAG_MASK | + VBAT_WAKENA_TIMER1_FLAG_MASK | VBAT_WAKENA_LDO_RDY_MASK | VBAT_WAKENA_OSC_RDY_MASK | + VBAT_WAKENA_CONFIG_DET_MASK | VBAT_WAKENA_IRQ0_DET_MASK | VBAT_WAKENA_IRQ1_DET_MASK | + VBAT_WAKENA_IRQ2_DET_MASK | VBAT_WAKENA_IRQ3_DET_MASK + +#if defined(VBAT_WAKENA_CLOCK_DET_MASK) + | VBAT_WAKENA_CLOCK_DET_MASK + +#endif /* VBAT_WAKENA_CLOCK_DET_MASK */ +#if defined(VBAT_WAKENA_VOLT_DET_MASK) + | VBAT_WAKENA_VOLT_DET_MASK + +#endif /* VBAT_WAKENA_VOLT_DET_MASK */ +#if defined(VBAT_WAKENA_TEMP_DET_MASK) + | VBAT_WAKENA_TEMP_DET_MASK + +#endif /* VBAT_WAKENA_TEMP_DET_MASK */ +#if defined(VBAT_WAKENA_SEC0_DET_MASK) + | VBAT_WAKENA_SEC0_DET_MASK + +#endif /* VBAT_WAKENA_SEC0_DET_MASK */ + ), /*!< Enable all wakeup. */ +}; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) && FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) +/*! + * @brief The enumeration of VBAT tamper enable. + */ +enum _vbat_tamper_enable +{ + kVBAT_TamperEnablePOR = VBAT_TAMPERA_POR_DET_MASK, /*!< Enable tamper if POR asserted in STATUS register. */ + kVBAT_TamperEnableClockDetect = VBAT_TAMPERA_CLOCK_DET_MASK, /*!< Enable tamper if clock monitor detect an error. */ + kVBAT_TamperEnableConfigDetect = + VBAT_TAMPERA_CONFIG_DET_MASK, /*!< Enable tamper if configuration error detected. */ + kVBAT_TamperEnableVoltageDetect = VBAT_TAMPERA_VOLT_DET_MASK, /*!< Enable tamper if voltage monitor detect an + error. */ + kVBAT_TamperEnableTemperatureDetect = VBAT_TAMPERA_TEMP_DET_MASK, /*!< Enable tamper if temperature monitor + detect an error. */ + kVBAT_TamperEnableSec0Detect = VBAT_TAMPERA_SEC0_DET_MASK, /*!< Enable tamper if security input 0 detect an + error. */ +}; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) && FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) +/*! + * @brief The enumeration of bandgap timer id, VBAT support two bandgap timers. + * + * @anchor vbat_bandgap_timer_id_t + */ +enum _vbat_bandgap_timer_id +{ + kVBAT_BandgapTimer0 = 1U << 0U, /*!< Bandgap Timer0. */ + kVBAT_BandgapTimer1 = 1U << 1U, /*!< Bandgap Timer1. */ +}; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER */ + +/*! + * @brief The enumeration of connections for OSC32K/FRO32K output clock to other modules. + * + * @anchor vbat_clock_enable_t + */ +enum _vbat_clock_enable +{ + kVBAT_EnableClockToDomain0 = 1U << 0U, /*!< Enable clock to power domain0. */ + kVBAT_EnableClockToDomain1 = 1U << 1U, /*!< Enable clock to power domain1. */ + kVBAT_EnableClockToDomain2 = 1U << 2U, /*!< Enable clock to power domain2. */ + kVBAT_EnableClockToDomain3 = 1U << 3U, /*!< Enable clock to power domain3. */ +}; +#define kVBAT_EnableClockToVddBat kVBAT_EnableClockToDomain0 +#define kVBAT_EnableClockToVddSys kVBAT_EnableClockToDomain1 +#define kVBAT_EnableClockToVddWake kVBAT_EnableClockToDomain2 +#define kVBAT_EnableClockToVddMain kVBAT_EnableClockToDomain3 + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) +/*! + * @brief The enumeration of SRAM arrays that controlled by VBAT. + * @anchor vbat_ram_array_t + */ +enum _vbat_ram_array +{ + kVBAT_SramArray0 = 1U << 0U, /*!< Specify SRAM array0 that controlled by VBAT. */ + kVBAT_SramArray1 = 1U << 1U, /*!< Specify SRAM array1 that controlled by VBAT. */ + kVBAT_SramArray2 = 1U << 2U, /*!< Specify SRAM array2 that controlled by VBAT. */ + kVBAT_SramArray3 = 1U << 3U, /*!< Specify SRAM array3 that controlled by VBAT. */ +}; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG */ + +/*! + * @brief The enumeration of bandgap refresh period. + */ +typedef enum _vbat_bandgap_refresh_period +{ + kVBAT_BandgapRefresh7P8125ms = 0U, /*!< Bandgap refresh every 7.8125ms. */ + kVBAT_BandgapRefresh15P625ms = 1U, /*!< Bandgap refresh every 15.625ms. */ + kVBAT_BandgapRefresh31P25ms = 2U, /*!< Bandgap refresh every 31.25ms. */ + kVBAT_BandgapRefresh62P5ms = 3U, /*!< Bandgap refresh every 62.5ms. */ +} vbat_bandgap_refresh_period_t; + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) && FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) +/*! + * @brief The enumeration of bandgap timer0 timeout period. + */ +typedef enum _vbat_bandgap_timer0_timeout_period +{ + kVBAT_BangapTimer0Timeout1s = 0U, /*!< Bandgap timer0 timerout every 1s. */ + kVBAT_BangapTimer0Timeout500ms = 1U, /*!< Bandgap timer0 timerout every 500ms. */ + kVBAT_BangapTimer0Timeout250ms = 2U, /*!< Bandgap timer0 timerout every 250ms. */ + kVBAT_BangapTimer0Timeout125ms = 3U, /*!< Bandgap timer0 timerout every 125ms. */ + kVBAT_BangapTimer0Timeout62P5ms = 4U, /*!< Bandgap timer0 timerout every 62.5ms. */ + kVBAT_BangapTimer0Timeout31P25ms = 5U, /*!< Bandgap timer0 timerout every 31.25ms. */ +} vbat_bandgap_timer0_timeout_period_t; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) +/*! + * @brief The enumeration of osc32k operate mode, including Bypass mode, low power switched mode and so on. + */ +typedef enum _vbat_osc32k_operate_mode +{ + kVBAT_Osc32kEnabledToTransconductanceMode = 0U, /*!< Set to transconductance mode. */ + kVBAT_Osc32kEnabledToLowPowerBackupMode = 1U, /*!< Set to low power backup mode. */ + kVBAT_Osc32kEnabledToLowPowerSwitchedMode = 2U, /*!< Set to low power switched mode. */ +} vbat_osc32k_operate_mode_t; + +/*! + * @brief The enumeration of OSC32K load capacitance. + */ +typedef enum _vbat_osc32k_load_capacitance_select +{ + kVBAT_Osc32kCrystalLoadCap0pF = + 0U, /*!< Internal capacitance bank is enabled, set the internal capacitance to 0 pF. */ + kVBAT_Osc32kCrystalLoadCap2pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 2 pF. */ + kVBAT_Osc32kCrystalLoadCap4pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 4 pF. */ + kVBAT_Osc32kCrystalLoadCap6pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 6 pF. */ + kVBAT_Osc32kCrystalLoadCap8pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 8 pF. */ + kVBAT_Osc32kCrystalLoadCap10pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 10 pF. */ + kVBAT_Osc32kCrystalLoadCap12pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 12 pF. */ + kVBAT_Osc32kCrystalLoadCap14pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 14 pF. */ + kVBAT_Osc32kCrystalLoadCap16pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 16 pF. */ + kVBAT_Osc32kCrystalLoadCap18pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 18 pF. */ + kVBAT_Osc32kCrystalLoadCap20pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 20 pF. */ + kVBAT_Osc32kCrystalLoadCap22pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 22 pF. */ + kVBAT_Osc32kCrystalLoadCap24pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 24 pF. */ + kVBAT_Osc32kCrystalLoadCap26pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 26 pF. */ + kVBAT_Osc32kCrystalLoadCap28pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 28 pF. */ + kVBAT_Osc32kCrystalLoadCap30pF, /*!< Internal capacitance bank is enabled, set the internal capacitance to 30 pF. */ + kVBAT_Osc32kCrystalLoadCapBankDisabled = 0xF0U, /*!< Internal capacitance bank is disabled. */ +} vbat_osc32k_load_capacitance_select_t; + +/*! + * @brief The enumeration of start-up time of the oscillator. + */ +typedef enum _vbat_osc32k_start_up_time +{ + kVBAT_Osc32kStartUpTime8Sec = 0U, /*!< Configure the start-up time as 8 seconds. */ + kVBAT_Osc32kStartUpTime4Sec, /*!< Configure the start-up time as 4 seconds. */ + kVBAT_Osc32kStartUpTime2Sec, /*!< Configure the start-up time as 2 seconds. */ + kVBAT_Osc32kStartUpTime1Sec, /*!< Configure the start-up time as 1 seconds. */ + kVBAT_Osc32kStartUpTime0P5Sec, /*!< Configure the start-up time as 0.5 seconds. */ + kVBAT_Osc32kStartUpTime0P25Sec, /*!< Configure the start-up time as 0.25 seconds. */ + kVBAT_Osc32kStartUpTime0P125Sec, /*!< Configure the start-up time as 0.125 seconds. */ + kVBAT_Osc32kStartUpTime0P5MSec, /*!< Configure the start-up time as 0.5 milliseconds. */ +} vbat_osc32k_start_up_time_t; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG) +/*! + * @brief The enumeration of VBAT module supplies. + */ +typedef enum _vbat_internal_module_supply +{ + kVBAT_ModuleSuppliedByVddBat = 0U, /*!< VDD_BAT supplies VBAT modules. */ + kVBAT_ModuleSuppliedByVddSys = 1U, /*!< VDD_SYS supplies VBAT modules. */ +} vbat_internal_module_supply_t; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) && FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) +/*! + * @brief The enumeration of VBAT clock monitor divide trim value + */ +typedef enum _vbat_clock_monitor_divide_trim +{ + kVBAT_ClockMonitorOperateAt1kHz = 0U, /*!< Clock monitor operates at 1 kHz. */ + kVBAT_ClockMonitorOperateAt64Hz = 1U, /*!< Clock monitor operates at 64 Hz. */ +} vbat_clock_monitor_divide_trim_t; + +/*! + * @brief The enumeration of VBAT clock monitor frequency trim value used to adjust the clock monitor assert. + */ +typedef enum _vbat_clock_monitor_freq_trim +{ + kVBAT_ClockMonitorAssert2Cycle = 0U, /*!< Clock monitor assert 2 cycles after expected edge. */ + kVBAT_ClockMonitorAssert4Cycle = 1U, /*!< Clock monitor assert 4 cycles after expected edge. */ + kVBAT_ClockMonitorAssert6Cycle = 2U, /*!< Clock monitor assert 8 cycles after expected edge. */ + kVBAT_ClockMonitorAssert8Cycle = 3U, /*!< Clock monitor assert 8 cycles after expected edge. */ +} vbat_clock_monitor_freq_trim_t; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG */ + +/*! + * @brief The structure of internal 16kHz free running oscillator attributes. + */ +typedef struct _vbat_fro16k_config +{ + bool enableFRO16k; /*!< Enable/disable internal 16kHz free running oscillator. */ + uint8_t enabledConnectionsMask; /*!< The mask of connected modules to enable FRO16k clock output. */ +} vbat_fro16k_config_t; + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) && FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) +/*! + * @brief The structure of internal clock monitor, including divide trim and frequency trim. + */ +typedef struct _vbat_clock_monitor_config +{ + vbat_clock_monitor_divide_trim_t divideTrim : 1U; /* !< Divide trim value, please + refer to @ref vbat_clock_monitor_divide_trim_t */ + vbat_clock_monitor_freq_trim_t freqTrim : 2U; /*!< Frequency trim value used to adjust the clock monitor + assert, please refer to @ref vbat_clock_monitor_freq_trim_t. */ + bool lock : 1U; /*!< Lock the clock monitor control after enabled. */ +} vbat_clock_monitor_config_t; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) && FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) +/*! + * @brief The structure of Tamper configuration. + */ +typedef struct _vbat_tamper_config +{ + bool enableVoltageDetect : 1U; /*!< Enable/disable voltage detection. */ + bool enableTemperatureDetect : 1U; /*!< Enable/disable temperature detection. */ + bool lock : 1U; /*!< Lock the tamper control after enabled. */ +} vbat_tamper_config_t; +#endif /* FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name FRO16K Control Interfaces + * @{ + */ + +/*! + * @brief Configure internal 16kHz free running oscillator, including enabel FRO16k, gate FRO16k output. + * + * @param base VBAT peripheral base address. + * @param config Pointer to @ref vbat_fro16k_config_t structure. + */ +void VBAT_ConfigFRO16k(VBAT_Type *base, const vbat_fro16k_config_t *config); + +/*! + * @brief Enable/disable internal 16kHz free running oscillator. + * + * @param base VBAT peripheral base address. + * @param enable Used to enable/disable 16kHz FRO. + * - \b true Enable internal 16kHz free running oscillator. + * - \b false Disable internal 16kHz free running oscillator. + */ +static inline void VBAT_EnableFRO16k(VBAT_Type *base, bool enable) +{ + if (enable) + { + base->FROCTLA |= VBAT_FROCTLA_FRO_EN_MASK; +#if (defined(VBAT_FROCTLB_INVERSE_MASK)) + base->FROCTLB &= ~VBAT_FROCTLB_INVERSE_MASK; +#endif /* VBAT_FROCTLB_INVERSE_MASK */ + } + else + { + base->FROCTLA &= ~VBAT_FROCTLA_FRO_EN_MASK; +#if (defined(VBAT_FROCTLB_INVERSE_MASK)) + base->FROCTLB |= VBAT_FROCTLB_INVERSE_MASK; +#endif /* VBAT_FROCTLB_INVERSE_MASK */ + } +} + +/*! + * @brief Check if internal 16kHz free running oscillator is enabled. + * + * @param base VBAT peripheral base address. + * + * @retval true The internal 16kHz Free running oscillator is enabled. + * @retval false The internal 16kHz Free running oscillator is enabled. + */ +static inline bool VBAT_CheckFRO16kEnabled(VBAT_Type *base) +{ + return (bool)((base->FROCTLA & VBAT_FROCTLA_FRO_EN_MASK) == VBAT_FROCTLA_FRO_EN_MASK); +} + +/*! + * @brief Enable FRO16kHz output clock to selected modules. + * + * @param base VBAT peripheral base address. + * @param connectionsMask The mask of modules that FRO16k is connected, should be the OR'ed + * value of @ref vbat_clock_enable_t. + */ +static inline void VBAT_UngateFRO16k(VBAT_Type *base, uint8_t connectionsMask) +{ + base->FROCLKE |= VBAT_FROCLKE_CLKE(connectionsMask); +} + +/*! + * @brief Disable FRO16kHz output clock to selected modules. + * + * @param base VBAT peripheral base address. + * @param connectionsMask The OR'ed value of @ref vbat_clock_enable_t. + */ +static inline void VBAT_GateFRO16k(VBAT_Type *base, uint8_t connectionsMask) +{ + base->FROCLKE &= ~VBAT_FROCLKE_CLKE(connectionsMask); +} + +/*! + * @brief Lock settings of internal 16kHz free running oscillator, please note that if locked 16kHz FRO's settings can + * not be updated until the next POR. + * + * @note Please note that the operation to ungate/gate FRO 16kHz output clock can not be locked by this function. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_LockFRO16kSettings(VBAT_Type *base) +{ + base->FROLCKA |= VBAT_FROLCKA_LOCK_MASK; +#if (defined(VBAT_FROLCKB_LOCK_MASK)) + base->FROLCKB &= ~VBAT_FROLCKB_LOCK_MASK; +#endif /* VBAT_FROLCKB_LOCK_MASK */ +} + +/*! + * @brief Check if FRO16K settings are locked. + * + * @param base VBAT peripheral base address. + * + * @return @c true in case of FRO16k settings are locked, @c false in case of FRO16k settings are not locked. + */ +static inline bool VBAT_CheckFRO16kSettingsLocked(VBAT_Type *base) +{ + return ((base->FROLCKA & VBAT_FROLCKA_LOCK_MASK) != 0UL); +} + +/*! @} */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG) +/*! + * @name OSC32K Control Interfaces + * @{ + */ + +/*! + * @brief Enable/disable 32K Crystal Oscillator. + * + * @param base VBAT peripheral base address. + * @param enable Used to enable/disable 32k Crystal Oscillator: + * - \b true Enable crystal oscillator and polling status register to check clock is ready. + * - \b false Disable crystal oscillator. + */ +static inline void VBAT_EnableCrystalOsc32k(VBAT_Type *base, bool enable) +{ + if (enable) + { + base->OSCCTLA |= VBAT_OSCCTLA_OSC_EN_MASK; + base->OSCCTLB &= ~VBAT_OSCCTLA_OSC_EN_MASK; + + /* Polling status register to check clock is ready. */ + while ((base->STATUSA & VBAT_STATUSA_OSC_RDY_MASK) == 0UL) + {} + } + else + { + base->OSCCTLA &= ~VBAT_OSCCTLA_OSC_EN_MASK; + base->OSCCTLB |= VBAT_OSCCTLA_OSC_EN_MASK; + } +} + +/*! + * @brief Bypass 32k crystal oscillator, the clock is still output by oscillator but this clock is the same as clock + * provided on EXTAL pin. + * + * @note In bypass mode, oscillator must be enabled; To exit bypass mode, oscillator must be disabled. + * + * @param base VBAT peripheral base address. + * @param enableBypass Used to enter/exit bypass mode: + * - \b true Enter into bypass mode; + * - \b false Exit bypass mode. + */ +static inline void VBAT_BypassCrystalOsc32k(VBAT_Type *base, bool enableBypass) +{ + if (enableBypass) + { + base->OSCCTLA |= (VBAT_OSCCTLA_OSC_EN_MASK | VBAT_OSCCTLA_OSC_BYP_EN_MASK); + base->OSCCTLB &= ~(VBAT_OSCCTLA_OSC_EN_MASK | VBAT_OSCCTLA_OSC_BYP_EN_MASK); + } + else + { + base->OSCCTLA &= ~(VBAT_OSCCTLA_OSC_EN_MASK | VBAT_OSCCTLA_OSC_BYP_EN_MASK); + base->OSCCTLB |= (VBAT_OSCCTLA_OSC_EN_MASK | VBAT_OSCCTLA_OSC_BYP_EN_MASK); + } +} + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT) && FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT) +/*! + * @brief Adjust 32k crystal oscillator amplifier gain. + * + * @param base VBAT peripheral base address. + * @param coarse Specify amplifier coarse trim value. + * @param fine Specify amplifier fine trim value. + */ +static inline void VBAT_AdjustCrystalOsc32kAmplifierGain(VBAT_Type *base, uint8_t coarse, uint8_t fine) +{ + base->OSCCTLA = ((base->OSCCTLA & ~(VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK | VBAT_OSCCTLA_FINE_AMP_GAIN_MASK)) | + (VBAT_OSCCTLA_COARSE_AMP_GAIN(coarse) | VBAT_OSCCTLA_FINE_AMP_GAIN(fine))); + base->OSCCTLB = ((base->OSCCTLB & ~(VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK | VBAT_OSCCTLA_FINE_AMP_GAIN_MASK)) | + (VBAT_OSCCTLA_COARSE_AMP_GAIN(~coarse) | VBAT_OSCCTLA_FINE_AMP_GAIN(~fine))); +} +#else +/*! + * @brief Adjust 32k crystal oscillator amplifier gain. + * + * @param base VBAT peripheral base address. + * @param coarse Specify amplifier coarse trim value. + */ +static inline void VBAT_AdjustCrystalOsc32kAmplifierGain(VBAT_Type *base, uint8_t coarse) +{ + base->OSCCTLA = (base->OSCCTLA & ~VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK) | (VBAT_OSCCTLA_COARSE_AMP_GAIN(coarse)); + base->OSCCTLB = (base->OSCCTLB & ~VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK) | (VBAT_OSCCTLA_COARSE_AMP_GAIN(~(uint32_t)coarse)); +} + +#endif /* */ + +/*! + * @brief Set 32k crystal oscillator mode and load capacitance for the XTAL/EXTAL pin. + * + * @param base VBAT peripheral base address. + * @param operateMode Specify the crystal oscillator mode, please refer to @ref vbat_osc32k_operate_mode_t. + * @param xtalCap Specify the internal capacitance for the XTAL pin from the capacitor bank. + * @param extalCap Specify the internal capacitance for the EXTAL pin from the capacitor bank. + * + * @retval kStatus_VBAT_WrongCapacitanceValue The load capacitance value to set is not align with operate mode's + * requirements. + * @retval kStatus_Success Success to set operate mode and load capacitance. + */ +status_t VBAT_SetCrystalOsc32kModeAndLoadCapacitance(VBAT_Type *base, + vbat_osc32k_operate_mode_t operateMode, + vbat_osc32k_load_capacitance_select_t xtalCap, + vbat_osc32k_load_capacitance_select_t extalCap); + +/*! + * @brief Trim 32k crystal oscillator startup time. + * + * @param base VBAT peripheral base address. + * @param startupTime Specify the startup time of the oscillator. + */ +static inline void VBAT_TrimCrystalOsc32kStartupTime(VBAT_Type *base, vbat_osc32k_start_up_time_t startupTime) +{ + base->OSCCFGA = ((base->OSCCFGA & ~(VBAT_OSCCFGA_INIT_TRIM_MASK)) | VBAT_OSCCFGA_INIT_TRIM(startupTime)); + base->OSCCFGB = ((base->OSCCFGB & ~(VBAT_OSCCFGA_INIT_TRIM_MASK)) | VBAT_OSCCFGA_INIT_TRIM(~((uint32_t)startupTime))); +} + +/*! + * @brief Set crystal oscillator comparator trim value when oscillator is set as low power switch mode. + * + * @param base VBAT peripheral base address. + * @param comparatorTrimValue Comparator trim value, ranges from 0 to 7. + */ +static inline void VBAT_SetOsc32kSwitchModeComparatorTrimValue(VBAT_Type *base, uint8_t comparatorTrimValue) +{ + base->OSCCFGA = ((base->OSCCFGA & ~VBAT_OSCCFGA_CMP_TRIM_MASK) | VBAT_OSCCFGA_CMP_TRIM(comparatorTrimValue)); + base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_CMP_TRIM_MASK) | VBAT_OSCCFGA_CMP_TRIM(~((uint32_t)comparatorTrimValue))); +} + +/*! + * @brief Set crystal oscillator delay trim value when oscillator is set as low power switch mode. + * + * @param base VBAT peripheral base address. + * @param delayTrimValue Delay trim value, ranges from 0 to 15. + */ +static inline void VBAT_SetOsc32kSwitchModeDelayTrimValue(VBAT_Type *base, uint8_t delayTrimValue) +{ + base->OSCCFGA = ((base->OSCCFGA & ~VBAT_OSCCFGA_DLY_TRIM_MASK) | VBAT_OSCCFGA_DLY_TRIM(delayTrimValue)); + base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_DLY_TRIM_MASK) | VBAT_OSCCFGA_DLY_TRIM(~((uint32_t)delayTrimValue))); +} + +/*! + * @brief Set crystal oscillator capacitor trim value when oscillator is set as low power switch mode. + * + * @param base VBAT peripheral base address. + * @param capacitorTrimValue Capacitor value to trim, ranges from 0 to 3. + */ +static inline void VBAT_SetOsc32kSwitchModeCapacitorTrimValue(VBAT_Type *base, uint8_t capacitorTrimValue) +{ + base->OSCCFGA = ((base->OSCCFGA & ~VBAT_OSCCFGA_CAP_TRIM_MASK) | VBAT_OSCCFGA_CAP_TRIM(capacitorTrimValue)); + base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_CAP_TRIM_MASK) | VBAT_OSCCFGA_CAP_TRIM(~((uint32_t)capacitorTrimValue))); +} + +/*! + * @brief Lock Osc32k settings, after locked all writes to the Oscillator registers are blocked. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_LookOsc32kSettings(VBAT_Type *base) +{ + base->OSCLCKA |= VBAT_OSCLCKA_LOCK_MASK; + base->OSCLCKB &= ~VBAT_OSCLCKB_LOCK_MASK; +} + +/*! + * @brief Unlock Osc32k settings. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_UnlockOsc32kSettings(VBAT_Type *base) +{ + base->OSCLCKA &= ~VBAT_OSCLCKA_LOCK_MASK; + base->OSCLCKB |= VBAT_OSCLCKB_LOCK_MASK; +} + +/*! + * @brief Check if osc32k settings are locked. + * + * @param base VBAT peripheral base address. + * @return \c true in case of osc32k settings are locked, \c false in case of osc32k settings are not locked. + */ +static inline bool VBAT_CheckOsc32kSettingsLocked(VBAT_Type *base) +{ + return ((base->OSCLCKA & VBAT_OSCLCKA_LOCK_MASK) != 0UL); +} + +/*! + * @brief Enable OSC32k output clock to selected modules. + * + * @param base VBAT peripheral base address. + * @param connectionsMask The OR'ed value of @ref vbat_clock_enable_t. + */ +static inline void VBAT_UngateOsc32k(VBAT_Type *base, uint8_t connectionsMask) +{ + base->OSCCLKE |= VBAT_OSCCLKE_CLKE(connectionsMask); +} + +/*! + * @brief Disable OSC32k output clock to selected modules. + * + * @param base VBAT peripheral base address. + * @param connectionsMask The OR'ed value of @ref vbat_clock_enable_t. + */ +static inline void VBAT_GateOsc32k(VBAT_Type *base, uint8_t connectionsMask) +{ + base->OSCCLKE &= ~VBAT_OSCCLKE_CLKE(connectionsMask); +} + +/*! @} */ +#endif /* FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG) +/*! + * @name RAM_LDO Control Interfaces + * @{ + */ + +/*! + * @brief Enable/disable Bandgap. + * + * @note The FRO16K must be enabled before enabling the bandgap. + * @note This setting can be locked by VBAT_LockRamLdoSettings() function. + * + * @param base VBAT peripheral base address. + * @param enable Used to enable/disable bandgap. + * - \b true Enable the bandgap. + * - \b false Disable the bandgap. + * + * @retval kStatus_Success Success to enable/disable the bandgap. + * @retval kStatus_VBAT_Fro16kNotEnabled Fail to enable the bandgap due to FRO16k is not enabled previously. + */ +status_t VBAT_EnableBandgap(VBAT_Type *base, bool enable); + +/*! + * @brief Check if bandgap is enabled. + * + * @param base VBAT peripheral base address. + * + * @retval true The bandgap is enabled. + * @retval false The bandgap is disabled. + */ +static inline bool VBAT_CheckBandgapEnabled(VBAT_Type *base) +{ + return (bool)((base->LDOCTLA & VBAT_LDOCTLA_BG_EN_MASK) == VBAT_LDOCTLA_BG_EN_MASK); +} + +/*! + * @brief Enable/disable bandgap low power refresh mode. + * + * @note For lowest power consumption, refresh mode must be enabled. + * @note This setting can be locked by VBAT_LockRamLdoSettings() function. + * + * @param base VBAT peripheral base address. + * @param enableRefreshMode Used to enable/disable bandgap low power refresh mode. + * - \b true Enable bandgap low power refresh mode. + * - \b false Disable bandgap low power refresh mode. + */ +static inline void VBAT_EnableBandgapRefreshMode(VBAT_Type *base, bool enableRefreshMode) +{ + if (enableRefreshMode) + { + base->LDOCTLA |= VBAT_LDOCTLA_REFRESH_EN_MASK; + base->LDOCTLB &= ~VBAT_LDOCTLA_REFRESH_EN_MASK; + } + else + { + base->LDOCTLA &= ~VBAT_LDOCTLA_REFRESH_EN_MASK; + base->LDOCTLB |= VBAT_LDOCTLA_REFRESH_EN_MASK; + } +} + +/*! + * @brief Enable/disable Backup RAM Regulator(RAM_LDO). + * + * @note This setting can be locked by VBAT_LockRamLdoSettings() function. + * + * @param base VBAT peripheral base address. + * @param enable Used to enable/disable RAM_LDO. + * - \b true Enable backup SRAM regulator. + * - \b false Disable backup SRAM regulator. + * + * @retval kStatusSuccess Success to enable/disable backup SRAM regulator. + * @retval kStatus_VBAT_Fro16kNotEnabled Fail to enable backup SRAM regulator due to FRO16k is not enabled previously. + * @retval kStatus_VBAT_BandgapNotEnabled Fail to enable backup SRAM regulator due to the bandgap is not enabled + * previously. + */ +status_t VBAT_EnableBackupSRAMRegulator(VBAT_Type *base, bool enable); + +/*! + * @brief Lock settings of RAM_LDO, please note that if locked then RAM_LDO's settings + * can not be updated until the next POR. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_LockRamLdoSettings(VBAT_Type *base) +{ + base->LDOLCKA |= VBAT_LDOLCKA_LOCK_MASK; + base->LDOLCKB &= ~VBAT_LDOLCKA_LOCK_MASK; +} + +/*! + * @brief Check if RAM_LDO settings is locked. + * + * @param base VBAT peripheral base address. + * @return @c true in case of RAM_LDO settings are locked, @c false in case of RAM_LDO settings are unlocked. + */ +static inline bool VBAT_CheckRamLdoSettingsLocked(VBAT_Type *base) +{ + return ((base->LDOLCKA & VBAT_LDOLCKA_LOCK_MASK) != 0UL); +} + +/*! + * @brief Switch the SRAM to be powered by LDO_RAM. + * + * @note This function can be used to switch the SRAM to the VBAT retention supply at any time, but please note that the + * SRAM must not be accessed during this time. + * @note Invoke this function to switch power supply before switching off external power. + * @note RAM_LDO must be enabled before invoking this function. + * @note To access the SRAM arrays retained by the LDO_RAM, please invoke VBAT_SwitchSRAMPowerBySocSupply(), after + * external power is switched back on. + * + * @param base VBAT peripheral base address. + * + * @retval kStatusSuccess Success to Switch SRAM powered by VBAT. + * @retval kStatus_VBAT_Fro16kNotEnabled Fail to switch SRAM powered by VBAT due to FRO16K not enabled previously. + */ +status_t VBAT_SwitchSRAMPowerByLDOSRAM(VBAT_Type *base); + +/*! + * @brief Switch the RAM to be powered by Soc Supply in software mode. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_SwitchSRAMPowerBySocSupply(VBAT_Type *base) +{ + base->LDORAMC &= ~VBAT_LDORAMC_SWI_MASK; + base->LDORAMC &= ~VBAT_LDORAMC_ISO_MASK; +} + +/*! + * @brief Power off selected SRAM array in low power modes. + * + * @param base VBAT peripheral base address. + * @param sramMask The mask of SRAM array to power off, should be the OR'ed value of @ref vbat_ram_array_t. + */ +static inline void VBAT_PowerOffSRAMsInLowPowerModes(VBAT_Type *base, uint8_t sramMask) +{ + base->LDORAMC |= (uint32_t)VBAT_LDORAMC_RET(sramMask); +} + +/*! + * @brief Retain selected SRAM array in low power modes. + * + * @param base VBAT peripheral base address. + * @param sramMask The mask of SRAM array to retain, should be the OR'ed value of @ref vbat_ram_array_t. + */ +static inline void VBAT_RetainSRAMsInLowPowerModes(VBAT_Type *base, uint8_t sramMask) +{ + base->LDORAMC &= ~(uint32_t)VBAT_LDORAMC_RET(sramMask); +} + +/*! + * @brief Enable/disable SRAM isolation. + * + * @param base VBAT peripheral base address. + * @param enable Used to enable/disable SRAM violation. + * - \b true SRAM will be isolated. + * - \b false SRAM state follows the SoC power modes. + */ +static inline void VBAT_EnableSRAMIsolation(VBAT_Type *base, bool enable) +{ + if (enable) + { + base->LDORAMC |= VBAT_LDORAMC_ISO_MASK; + } + else + { + base->LDORAMC &= ~VBAT_LDORAMC_ISO_MASK; + } +} + +/*! @} */ +#endif /* FSL_FEATURE_MCX_VBAT_HAS_RAM_LDO */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) && FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER) +/*! @name Bandgap Timer Control Interfaces + * @{ + */ + +/*! + * @brief Enable/disable Bandgap timer. + * + * @note The bandgap timer is available when the bandgap is enabled and are clocked by the FRO16k. + * + * @param base VBAT peripheral base address. + * @param enable Used to enable/disable bandgap timer. + * @param timerIdMask The mask of bandgap timer Id, should be the OR'ed value of @ref vbat_bandgap_timer_id_t. + * + * @retval kStatus_Success Success to enable/disable selected bandgap timer. + * @retval kStatus_VBAT_Fro16kNotEnabled Fail to enable/disable selected bandgap timer due to FRO16k not enabled + * previously. + * @retval kStatus_VBAT_BandgapNotEnabled Fail to enable/disable selected bandgap timer due to bandgap not enabled + * previously. + */ +status_t VBAT_EnableBandgapTimer(VBAT_Type *base, bool enable, uint8_t timerIdMask); + +/*! + * @brief Set bandgap timer0 timeout value. + * + * @note The timeout value can only be changed when the timer is disabled. + * + * @param base VBAT peripheral base address. + * @param timeoutPeriod Bandgap timer timeout value, please refer to @ref vbat_bandgap_timer0_timeout_period_t. + */ +void VBAT_SetBandgapTimer0TimeoutValue(VBAT_Type *base, vbat_bandgap_timer0_timeout_period_t timeoutPeriod); + +/*! + * @brief Set bandgap timer1 timeout value. + * + * @note The timeout value can only be changed when the timer is disabled. + * + * @param base VBAT peripheral base address. + * @param timeoutPeriod The bandgap timerout 1 period, in number of seconds, ranging from 0 to 65535s. + */ +void VBAT_SetBandgapTimer1TimeoutValue(VBAT_Type *base, uint32_t timeoutPeriod); + +/*! @} */ +#endif /* FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG) && FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG) +/*! @name Switch Control Interfaces + * @{ + */ + +/*! + * @brief Control the VBAT internal switch in active mode, VBAT modules can be suppiled by VDD_BAT and VDD_SYS. + * + * @param base VBAT peripheral base address. + * @param supply Used to control the VBAT internal switch. + */ +static inline void VBAT_SwitchVBATModuleSupplyActiveMode(VBAT_Type *base, vbat_internal_module_supply_t supply) +{ + if (supply == kVBAT_ModuleSuppliedByVddBat) + { + base->SWICTLA &= ~VBAT_SWICTLA_SWI_EN_MASK; + base->SWICTLB |= VBAT_SWICTLA_SWI_EN_MASK; + } + else + { + base->SWICTLA |= VBAT_SWICTLA_SWI_EN_MASK; + base->SWICTLB &= ~VBAT_SWICTLA_SWI_EN_MASK; + } +} + +/*! + * @brief Get VBAT module supply in active mode. + * + * @param base VBAT peripheral base address. + * @return VDD_SYS supplies VBAT modules or VDD_BAT supplies VBAT modules, in type of @ref + * vbat_internal_module_supply_t. + */ +static inline vbat_internal_module_supply_t VBAT_GetVBATModuleSupply(VBAT_Type *base) +{ + return (vbat_internal_module_supply_t)(uint8_t)(base->SWICTLA & VBAT_SWICTLA_SWI_EN_MASK); +} + +/*! + * @brief Control the VBAT internal switch in low power modes. + * + * @note If VBAT modules are supplied by VDD_SYS in low power modes, VBAT module will also supplied by VDD_SYS in active + * mode. + * + * @param base VBAT peripheral base address. + * @param supply Used to specify which voltage input supply VBAT modules in low power mode. + */ +static inline void VBAT_SwitchVBATModuleSupplyLowPowerMode(VBAT_Type *base, vbat_internal_module_supply_t supply) +{ + if (supply == kVBAT_ModuleSuppliedByVddBat) + { + base->SWICTLA &= ~VBAT_SWICTLA_LP_EN_MASK; + base->SWICTLB |= VBAT_SWICTLA_LP_EN_MASK; + } + else + { + base->SWICTLA |= VBAT_SWICTLA_SWI_EN_MASK; + base->SWICTLB &= ~VBAT_SWICTLA_SWI_EN_MASK; + base->SWICTLA |= VBAT_SWICTLA_LP_EN_MASK; + base->SWICTLB &= ~VBAT_SWICTLA_LP_EN_MASK; + } +} + +/*! + * @brief Lock switch control, if locked all writes to the switch registers will be blocked. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_LockSwitchControl(VBAT_Type *base) +{ + base->SWILCKA |= VBAT_SWILCKA_LOCK_MASK; + base->SWILCKB &= ~VBAT_SWILCKB_LOCK_MASK; +} + +/*! + * @brief Unlock switch control. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_UnlockSwitchControl(VBAT_Type *base) +{ + base->SWILCKA &= ~VBAT_SWILCKA_LOCK_MASK; + base->SWILCKB |= VBAT_SWILCKB_LOCK_MASK; +} + +/*! + * @brief Check if switch control is locked. + * + * @param base VBAT peripheral base address. + * + * @retval false switch control is not locked. + * @retval true switch control is locked, any writes to related registers are blocked. + */ +static inline bool VBAT_CheckSwitchControlLocked(VBAT_Type *base) +{ + return ((base->SWILCKA & VBAT_SWILCKA_LOCK_MASK) != 0UL); +} + +/*! @} */ +#endif /* FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) && FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG) +/*! + * @name Clock Monitor Interfaces + * @{ + */ + +/*! + * @brief Initialize the VBAT clock monitor, enable clock monitor and set the clock monitor configuration. + * + * @note Both FRO16K and OSC32K should be enabled and stable before invoking this function. + * + * @param base VBAT peripheral base address. + * @param config Pointer to @ref vbat_clock_monitor_config_t structure. + * + * @retval kStatus_Success Clock monitor is initialized successfully. + * @retval kStatus_VBAT_Fro16kNotEnabled FRO16K is not enabled. + * @retval kStatus_VBAT_Osc32kNotReady OSC32K is not ready. + * @retval kStatus_VBAT_ClockMonitorLocked Clock monitor is locked. + */ +status_t VBAT_InitClockMonitor(VBAT_Type *base, const vbat_clock_monitor_config_t *config); + +/*! + * @brief Deinitialize the VBAT clock monitor. + * + * @param base VBAT peripheral base address. + * + * @retval kStatus_Success Clock monitor is de-initialized successfully. + * @retval kStatus_VBAT_ClockMonitorLocked Control of Clock monitor is locked. + */ +status_t VBAT_DeinitMonitor(VBAT_Type *base); + +/*! + * @brief Enable/disable clock monitor. + * + * @param base VBAT peripheral base address. + * @param enable Switcher to enable/disable clock monitor: + * - true: enable clock monitor; + * - false: disable clock monitor. + */ +static inline void VBAT_EnableClockMonitor(VBAT_Type *base, bool enable) +{ + if (enable) + { + base->MONCTLA |= VBAT_MONCTLA_MON_EN_MASK; + base->MONCTLB &= ~VBAT_MONCTLA_MON_EN_MASK; + } + else + { + base->MONCTLA &= ~VBAT_MONCTLA_MON_EN_MASK; + base->MONCTLB |= VBAT_MONCTLA_MON_EN_MASK; + } +} + +/*! + * @brief Set clock monitor's divide trim, avaiable value is #kVBAT_ClockMonitorOperateAt1kHz and + * #kVBAT_ClockMonitorOperateAt64Hz + * + * @param base VBAT peripheral base address. + * @param divideTrim Specify divide trim value, please refer to @ref vbat_clock_monitor_divide_trim_t. + */ +static inline void VBAT_SetClockMonitorDivideTrim(VBAT_Type *base, vbat_clock_monitor_divide_trim_t divideTrim) +{ + base->MONCFGA = (base->MONCFGA & ~VBAT_MONCFGA_DIVIDE_TRIM_MASK) | VBAT_MONCFGA_DIVIDE_TRIM(divideTrim); + base->MONCFGB = (base->MONCFGB & ~VBAT_MONCFGA_DIVIDE_TRIM_MASK) | VBAT_MONCFGA_DIVIDE_TRIM(~divideTrim); +} + +/*! + * @brief Set clock monitor's frequency trim, avaiable value is #kVBAT_ClockMonitorAssert2Cycle, + * #kVBAT_ClockMonitorAssert4Cycle, #kVBAT_ClockMonitorAssert6Cycle and #kVBAT_ClockMonitorAssert8Cycle. + * + * @param base VBAT peripheral base address. + * @param freqTrim Specify frequency trim value, please refer to @ref vbat_clock_monitor_freq_trim_t. + */ +static inline void VBAT_SetClockMonitorFrequencyTrim(VBAT_Type *base, vbat_clock_monitor_freq_trim_t freqTrim) +{ + base->MONCFGA = (base->MONCFGA & ~VBAT_MONCFGA_FREQ_TRIM_MASK) | VBAT_MONCFGA_FREQ_TRIM(freqTrim); + base->MONCFGB = (base->MONCFGB & ~VBAT_MONCFGA_FREQ_TRIM_MASK) | VBAT_MONCFGA_FREQ_TRIM(~freqTrim); +} + +/*! + * @brief Lock clock monitor enable/disable control. + * + * @note If locked, it is not allowed to change clock monitor enable/disable control. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_LockClockMonitorControl(VBAT_Type *base) +{ + base->MONLCKA |= VBAT_MONLCKA_LOCK_MASK; + base->MONLCKB &= ~VBAT_MONLCKA_LOCK_MASK; +} + +/*! + * @brief Unlock clock monitor enable/disable control. + * + * @param base VBTA peripheral base address. + */ +static inline void VBAT_UnlockClockMonitorControl(VBAT_Type *base) +{ + base->MONLCKA &= ~VBAT_MONLCKA_LOCK_MASK; + base->MONLCKB |= VBAT_MONLCKA_LOCK_MASK; +} + +/*! + * @brief Check if clock monitor enable/disable control is locked. + * + * @note If locked, it is not allowed to change clock monitor enable/disable control. + * + * @param base VBAT peripheral base address. + * + * @retval false clock monitor enable/disable control is not locked. + * @retval true clock monitor enable/disable control is locked, any writes to related registers are blocked. + */ +static inline bool VBAT_CheckClockMonitorControlLocked(VBAT_Type *base) +{ + return ((base->MONLCKA & VBAT_MONLCKA_LOCK_MASK) != 0UL); +} + +/*! @} */ +#endif /* FSL_FEATURE_VBAT_HAS_CLOCK_MONITOR */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) && FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG) +/*! @name Tamper Control Interfaces + * + */ + +/*! + * @brief Initialize tamper control. + * + * @note Both FRO16K and bandgap should be enabled before calling this function. + * + * @param base VBAT peripheral base address. + * @param config Pointer to @ref vbat_tamper_config_t structure. + * + * @retval kStatus_Success Tamper is initialized successfully. + * @retval kStatus_VBAT_TamperLocked Tamper control is locked. + * @retval kStatus_VBAT_BandgapNotEnabled Bandgap is not enabled. + * @retval kStatus_VBAT_Fro16kNotEnabled FRO 16K is not enabled. + */ +status_t VBAT_InitTamper(VBAT_Type *base, const vbat_tamper_config_t *config); + +/*! + * @brief De-initialize tamper control. + * + * @param base VBAT peripheral base address. + * + * @retval kStatus_Success Tamper is de-initialized successfully. + * @retval kStatus_VBAT_TamperLocked Tamper control is locked. + */ +status_t VBAT_DeinitTamper(VBAT_Type *base); + +/*! + * @brief Enable tampers for VBAT. + * + * @param base VBAT peripheral base address. + * @param tamperEnableMask Mask of tamper to be enabled, should be the OR'ed value of @ref _vbat_tamper_enable. + */ +static inline void VBAT_EnableTamper(VBAT_Type *base, uint32_t tamperEnableMask) +{ + base->TAMPERA |= tamperEnableMask; + base->TAMPERB &= ~tamperEnableMask; +} + +/*! + * @brief Disable tampers for VBAT. + * + * @param base VBAT peripheral base address. + * @param tamperEnableMask Mask of tamper to be disabled, should be the OR'ed value of @ref _vbat_tamper_enable. + */ +static inline void VBAT_DisableTamper(VBAT_Type *base, uint32_t tamperEnableMask) +{ + base->TAMPERA &= ~tamperEnableMask; + base->TAMPERB |= tamperEnableMask; +} + +/*! + * @brief Get tamper enable information. + * + * @param base VBAT peripheral base address. + * + * @return Mask of tamper enable information, should be the OR'ed value of @ref _vbat_tamper_enable. + */ +static inline uint32_t VBAT_GetTamperEnableInfo(VBAT_Type *base) +{ + return base->TAMPERA; +} + +/*! + * @brief Lock tamper control, if locked, it is not allowed to change tamper control. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_LockTamperControl(VBAT_Type *base) +{ + base->TAMLCKA |= VBAT_TAMLCKA_LOCK_MASK; + base->TAMLCKB &= ~VBAT_TAMLCKA_LOCK_MASK; +} + +/*! + * @brief Unlock tamper control. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_UnlockTamperControl(VBAT_Type *base) +{ + base->TAMLCKA &= ~VBAT_TAMLCKA_LOCK_MASK; + base->TAMLCKB |= VBAT_TAMLCKA_LOCK_MASK; +} + +/*! + * @brief Check if tamper control is locked. + * + * @param base VBAT peripheral base address. + * + * @retval false Tamper control is not locked. + * @retval true Tamper control is locked, any writes to related registers are blocked. + */ +static inline bool VBAT_CheckTamperControlLocked(VBAT_Type *base) +{ + return ((base->TAMLCKA & VBAT_TAMLCKA_LOCK_MASK) != 0UL); +} + +/*! @} */ +#endif /* FSL_FEATURE_VBAT_HAS_TAMPER */ + +#if (defined(FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG) && FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG) +/*! @name Status, Interrupt, Wakeup Control Interfaces + * @{ + */ + +/*! + * @brief Get VBAT status flags + * + * @param base VBAT peripheral base address. + * @return The asserted status flags, should be the OR'ed value of @ref vbat_status_flag_t. + */ +static inline uint32_t VBAT_GetStatusFlags(VBAT_Type *base) +{ + return (uint32_t)(base->STATUSA); +} + +/*! + * @brief Clear VBAT status flags. + * + * @param base VBAT peripheral base address. + * @param mask The mask of status flags to be cleared, should be the OR'ed value of @ref vbat_status_flag_t except + * @ref kVBAT_StatusFlagLdoReady, @ref kVBAT_StatusFlagOsc32kReady, @ref kVBAT_StatusFlagInterrupt0Detect, + * @ref kVBAT_StatusFlagInterrupt1Detect, @ref kVBAT_StatusFlagInterrupt2Detect, + * @ref kVBAT_StatusFlagInterrupt3Detect. + */ +static inline void VBAT_ClearStatusFlags(VBAT_Type *base, uint32_t mask) +{ + base->STATUSA = mask; + base->STATUSB = ~mask; +} + +/*! + * @brief Enable interrupts for the VBAT module, such as POR detect interrupt, Wakeup Pin interrupt and so on. + * + * @param base VBAT peripheral base address. + * @param mask The mask of interrupts to be enabled, should be the OR'ed value of @ref vbat_interrupt_enable_t. + */ +static inline void VBAT_EnableInterrupts(VBAT_Type *base, uint32_t mask) +{ + base->IRQENA |= mask; + base->IRQENB &= (uint32_t)~mask; +} + +/*! + * @brief Disable interrupts for the VBAT module, such as POR detect interrupt, wakeup pin interrupt and so on. + * + * @param base VBAT peripheral base address. + * @param mask The mask of interrupts to be disabled, should be the OR'ed value of @ref vbat_interrupt_enable_t. + */ +static inline void VBAT_DisableInterrupts(VBAT_Type *base, uint32_t mask) +{ + base->IRQENA &= ~mask; + base->IRQENB |= mask; +} + +/*! + * @brief Enable wakeup for the VBAT module, such as POR detect wakeup, wakeup pin wakeup and so on. + * + * @param base VBAT peripheral base address. + * @param mask The mask of enumerators in @ref vbat_wakeup_enable_t. + */ +static inline void VBAT_EnableWakeup(VBAT_Type *base, uint32_t mask) +{ + base->WAKENA |= mask; + base->WAKENB &= ~mask; +} + +/*! + * @brief Disable wakeup for VBAT module, such as POR detect wakeup, wakeup pin wakeup and so on. + * + * @param base VBAT peripheral base address. + * @param mask The mask of enumerators in @ref vbat_wakeup_enable_t. + */ +static inline void VBAT_DisableWakeup(VBAT_Type *base, uint32_t mask) +{ + base->WAKENA &= ~mask; + base->WAKENB |= mask; +} + +/*! + * @brief Lock VBAT interrupt and wakeup settings, please note that if locked the interrupt and wakeup settings can not + * be updated until the next POR. + * + * @param base VBAT peripheral base address. + */ +static inline void VBAT_LockInterruptWakeupSettings(VBAT_Type *base) +{ + base->LOCKA |= VBAT_LOCKA_LOCK_MASK; +} + +/*! + * @brief Set the default state of the WAKEUP_b pin output when no enabled wakeup source is asserted. + * + * @param base VBAT peripheral base address. + * @param assert Used to set default state of the WAKEUP_b pin output: + * - \b true WAKEUP_b output state is logic one; + * - \b false WAKEUP_b output state is logic zero. + */ +static inline void VBAT_SetWakeupPinDefaultState(VBAT_Type *base, bool assert) +{ + if (assert) + { + base->WAKECFG |= VBAT_WAKECFG_OUT_MASK; + } + else + { + base->WAKECFG &= ~VBAT_WAKECFG_OUT_MASK; + } +} + +/*! @} */ +#endif /* FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* FSL_VBAT_H__ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_waketimer.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_waketimer.c new file mode 100644 index 00000000000..d45699c605d --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_waketimer.c @@ -0,0 +1,253 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_waketimer.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.waketimer" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * brief Gets the instance from the base address + * + * param base WAKETIMER peripheral base address + * + * return The WAKETIMER instance + */ +static uint32_t WAKETIMER_GetInstance(WAKETIMER_Type *base); + +/*! + * brief WAKETIMER generic IRQ handle function. + * + * param index WAKETIMER peripheral instance index. + */ +static void WAKETIMER_GenericIRQHandler(WAKETIMER_Type *base, waketimer_callback_t callback); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Array of WAKETIMER peripheral base address. */ +static WAKETIMER_Type *const s_waketimerBases[] = WAKETIMER_BASE_PTRS; +/* Array of WAKETIMER ISR. */ +static waketimer_callback_t s_waketimerCallback[sizeof(s_waketimerBases) / sizeof(s_waketimerBases[0])]; +/* Array of WAKETIMER IRQ number. */ +static const IRQn_Type s_waketimerIRQ[] = WAKETIMER_IRQS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* brief Function for getting the instance number of Waketimer. */ +static uint32_t WAKETIMER_GetInstance(WAKETIMER_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_waketimerBases); instance++) + { + if (s_waketimerBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_waketimerBases)); + + return instance; +} + +/*! + * brief Initializes an WAKETIMER. + * param base WAKETIMER peripheral base address. + */ +void WAKETIMER_Init(WAKETIMER_Type *base, const waketimer_config_t *config) +{ + assert(NULL != base); + + uint32_t index = WAKETIMER_GetInstance(base); + + /* Halt timer */ + base->WAKE_TIMER_CTRL |= WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK; + + /* Set OSC divide */ + if (config->enableOSCDivide) + { + base->WAKE_TIMER_CTRL |= WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK; + } + else + { + base->WAKE_TIMER_CTRL &= ~WAKETIMER_WAKE_TIMER_CTRL_OSC_DIV_ENA_MASK; + } + + /* Set callback */ + s_waketimerCallback[index] = config->callback; + + /* Set interrupt */ + if (config->enableInterrupt) + { + base->WAKE_TIMER_CTRL |= WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_MASK; + (void)EnableIRQ(s_waketimerIRQ[index]); + } + else + { + base->WAKE_TIMER_CTRL &= ~WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_MASK; + (void)DisableIRQ(s_waketimerIRQ[index]); + } +} + +/*! + * brief Deinitializes a WAKETIMER instance. + * + * This function deinitializes the WAKETIMER. + * + * param base WAKETIMER peripheral base address. + */ +void WAKETIMER_Deinit(WAKETIMER_Type *base) +{ + assert(NULL != base); + + uint32_t index = WAKETIMER_GetInstance(base); + + /* Disable IRQ at NVIC Level */ + (void)DisableIRQ(s_waketimerIRQ[index]); +} + +/*! + * brief Fills in the WAKETIMER configuration structure with the default settings. + * + * The default values are: + * code + * config->enableInterrupt = true; + * config->enableOSCDivide = true; + * config->callback = NULL; + * endcode + * param config Pointer to the user configuration structure. + */ +void WAKETIMER_GetDefaultConfig(waketimer_config_t *config) +{ + config->enableInterrupt = true; + config->enableOSCDivide = true; + config->callback = NULL; +} + +/*! + * brief Enables the selected WAKETIMER interrupts. + * + * param base WAKETIMER peripheral base address + * param mask Mask value for interrupt events. See to #_waketimer_interrupt_enable + */ +void WAKETIMER_EnableInterrupts(WAKETIMER_Type *base, uint32_t mask) +{ + assert(NULL != base); + + if (0U != (mask & (uint32_t)kWAKETIMER_WakeInterruptEnable)) + { + base->WAKE_TIMER_CTRL |= WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_MASK; + } +} + +/*! + * brief Disable the selected WAKETIMER interrupts. + * + * param base WAKETIMER peripheral base address + * param mask Mask value for interrupt events. See to #_waketimer_interrupt_enable + */ +void WAKETIMER_DisableInterrupts(WAKETIMER_Type *base, uint32_t mask) +{ + assert(NULL != base); + + if (0U != (mask & (uint32_t)kWAKETIMER_WakeInterruptEnable)) + { + base->WAKE_TIMER_CTRL &= ~WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_MASK; + } +} + +/*! + * brief Clear Status Interrupt Flag. + * + * This clears intrrupt status flag. + * Currently, only match interrupt flag can be cleared. + * + * param base WAKETIMER peripheral base address. + * param mask Mask value for flags to be cleared. See to #_waketimer_status_flags. + * return none + */ +void WAKETIMER_ClearStatusFlags(WAKETIMER_Type *base, uint32_t mask) +{ + if (0U != (mask & (uint32_t)kWAKETIMER_WakeFlag)) + { + base->WAKE_TIMER_CTRL |= WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG_MASK; + } +} + +/*! + * brief Receive noticification when waketime countdown. + * + * If the interrupt for the waketime countdown is enabled, then a callback can be registered + * which will be invoked when the event is triggered + * + * param base WAKETIMER peripheral base address + * param callback Function to invoke when the event is triggered + */ +void WAKETIMER_SetCallback(WAKETIMER_Type *base, waketimer_callback_t callback) +{ + assert(NULL != base); + + uint32_t index = WAKETIMER_GetInstance(base); + s_waketimerCallback[index] = callback; +} + +/*! + * brief Get current timer count value from WAKETIMER. + * + * This function will get a decimal timer count value. + * The RAW value of timer count is gray code format, will be translated to decimal data internally. + * + * param base WAKETIMER peripheral base address. + * return Value of WAKETIMER which will formated to decimal value. + */ +uint32_t WAKETIMER_GetCurrentTimerValue(WAKETIMER_Type *base) +{ + uint32_t value1 = 0; + uint32_t value2 = 0; + + do + { + value1 = base->WAKE_TIMER_CNT; + value2 = base->WAKE_TIMER_CNT; + } while (value1 != value2); + + return value1; +} + +static void WAKETIMER_GenericIRQHandler(WAKETIMER_Type *base, waketimer_callback_t callback) +{ + /* Clear interrupt flag. */ + WAKETIMER_ClearStatusFlags(base, (uint32_t)kWAKETIMER_WakeFlag); + + if (callback != NULL) + { + callback(); + } +} + +#if defined(WAKETIMER0) +void WAKETIMER0_DriverIRQHandler(void); +void WAKETIMER0_DriverIRQHandler(void) +{ + WAKETIMER_GenericIRQHandler(WAKETIMER0, s_waketimerCallback[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_waketimer.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_waketimer.h new file mode 100644 index 00000000000..9913ff96672 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_waketimer.h @@ -0,0 +1,212 @@ +/* + * Copyright 2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_WAKETIMER_H_ +#define FSL_WAKETIMER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup waketimer + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief WAKETIMER driver version. */ +#define FSL_WAKETIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*! @} */ + +/*! + * @brief WAKETIMER status flags. + */ +enum _waketimer_status_flags +{ + kWAKETIMER_WakeFlag = + (WAKETIMER_WAKE_TIMER_CTRL_WAKE_FLAG_MASK), /*!< Wake Timer Status Flag, sets wake timer has timed out. */ +}; + +/*! + * @brief Define interrupt switchers of the module. + */ +enum _waketimer_interrupt_enable +{ + kWAKETIMER_WakeInterruptEnable = WAKETIMER_WAKE_TIMER_CTRL_INTR_EN_MASK, /*!< Generate interrupt + requests when WAKE_FLAG is asserted. */ +}; + +/*! @brief waketimer callback function. */ +typedef void (*waketimer_callback_t)(void); + +/*! + * @brief WAKETIMER configuration structure + * + * This structure holds the configuration settings for the WAKETIMER peripheral. To initialize this + * structure to reasonable defaults, call the WAKETIMER_GetDefaultConfig() function and pass a + * pointer to the configuration structure instance. + * + * The configuration structure can be made constant so as to reside in flash. + */ +typedef struct _waketimer_config +{ + bool enableOSCDivide; /*!< true: Enable OSC Divide. + false: Disable OSC Divide. */ + bool enableInterrupt; /*!< true: Enable interrupt. + false: Disable interrupt. */ + waketimer_callback_t callback; /*!< timer countdown callback. */ +} waketimer_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes an WAKETIMER + * + * This function initializes the WAKETIMER. + * + * @param base WAKETIMER peripheral base address. + * @param config Pointer to the user configuration structure. + */ +void WAKETIMER_Init(WAKETIMER_Type *base, const waketimer_config_t *config); + +/*! + * @brief Deinitializes a WAKETIMER instance. + * + * This function deinitialize the WAKETIMER. + * + * @param base WAKETIMER peripheral base address. + */ +void WAKETIMER_Deinit(WAKETIMER_Type *base); + +/*! + * @brief Fills in the WAKETIMER configuration structure with the default settings. + * + * The default values are: + * @code + * config->enableInterrupt = true; + * config->enableOSCDivide = true; + * config->callback = NULL; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void WAKETIMER_GetDefaultConfig(waketimer_config_t *config); + +/*! @}*/ + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected WAKETIMER interrupts. + * + * @param base WAKETIMER peripheral base address + * @param mask Mask value for interrupt events. See to #_waketimer_interrupt_enable + */ +void WAKETIMER_EnableInterrupts(WAKETIMER_Type *base, uint32_t mask); + +/*! + * @brief Enables the selected WAKETIMER interrupts. + * + * @param base WAKETIMER peripheral base address + * @param mask Mask value for interrupt events. See to #_waketimer_interrupt_enable + */ +void WAKETIMER_DisableInterrupts(WAKETIMER_Type *base, uint32_t mask); + +/*! + * @brief Clear Status Interrupt Flag. + * + * This clears intrrupt status flag. + * Currently, only match interrupt flag can be cleared. + * + * @param base WAKETIMER peripheral base address. + * @param mask Mask value for flags to be cleared. See to #_waketimer_status_flags. + * @return none + */ +void WAKETIMER_ClearStatusFlags(WAKETIMER_Type *base, uint32_t mask); + +/*! + * @brief Receive noticification when waketime countdown. + * + * If the interrupt for the waketime countdown is enabled, then a callback can be registered + * which will be invoked when the event is triggered + * + * @param base WAKETIMER peripheral base address + * @param callback Function to invoke when the event is triggered + */ +void WAKETIMER_SetCallback(WAKETIMER_Type *base, waketimer_callback_t callback); + +/*! @}*/ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Halt and clear timer counter. + * + * This halt and clear timer counter. + * + * @param base WAKETIMER peripheral base address. + * @return none + */ +static inline void WAKETIMER_HaltTimer(WAKETIMER_Type *base) +{ + base->WAKE_TIMER_CTRL |= WAKETIMER_WAKE_TIMER_CTRL_CLR_WAKE_TIMER_MASK; +} + +/*! + * @brief Set timer counter. + * + * This set the timer counter and start the timer countdown. + * + * @param base WAKETIMER peripheral base address. + * @param value countdown value. + * @return none + */ +static inline void WAKETIMER_StartTimer(WAKETIMER_Type *base, uint32_t value) +{ + base->WAKE_TIMER_CNT = value; +} + +/*! + * @brief Get current timer count value from WAKETIMER. + * + * This function will get a decimal timer count value. + * The RAW value of timer count is gray code format, will be translated to decimal data internally. + * + * @param base WAKETIMER peripheral base address. + * @return Value of WAKETIMER which will be formated to decimal value. + */ +uint32_t WAKETIMER_GetCurrentTimerValue(WAKETIMER_Type *base); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_WAKETIMER_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_wuu.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_wuu.c new file mode 100644 index 00000000000..214e7c07f08 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_wuu.c @@ -0,0 +1,312 @@ +/* + * Copyright 2019-2024 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_wuu.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.wuu" +#endif + +#define WUU_PE_REG_BIT_FIELD_MASK 0x03UL +#define WUU_PDC_REG_BIT_FIELD_MASK 0x03UL +#define WUU_PMC_REG_BIT_FIELD_MASK 0x01UL + +#define WUU_ME_REG_WUME_FIELD_MASK 0x01UL +#define WUU_DE_REG_WUME_FIELD_MASK 0x01UL + +#define WUU_FILT_REG_FILTE_FIELD_MASK 0x60U +#define WUU_FILT_REG_FILTSET_FIELD_MASK 0x1FU +#define WUU_FDC_REG_FILTC_FIELD_MASK 0x3U +#define WUU_FMC_REG_FILTM_FIELD_MASK 0x1U + +#define WUU_FILT_REG_FILTSET_FIELD(x) (((uint32_t)(x) << 5UL) & WUU_FILT_REG_FILTE_FIELD_MASK) +#define WUU_CLEAR_BIT_FIELD_IN_REG(mask, offset) (~((uint32_t)(mask) << (offset))) +#define WUU_SET_BIT_FIELD_IN_REG(val, offset) ((uint32_t)(val) << (offset)) +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Enables and Configs External WakeUp Pins. + * + * This function enables/disables the external pin as wakeup input. What's more this + * function configs pins options, including edge detection wakeup event and operate mode. + * + * param base MUU peripheral base address. + * param pinIndex The index of the external input pin. See Reference Manual for the details. + * param config Pointer to wuu_external_wakeup_pin_config_t structure. + */ +void WUU_SetExternalWakeUpPinsConfig(WUU_Type *base, uint8_t pinIndex, const wuu_external_wakeup_pin_config_t *config) +{ + assert(config != NULL); + + volatile uint32_t *edgeRegBase = NULL; + volatile uint32_t *eventRegBase = NULL; + uint32_t edgeReg; + uint32_t eventReg; + uint32_t modeReg; + uint8_t offset; + + /* Calculate offset. */ + offset = 2U * (pinIndex & 0xFU); + + if (config->edge != kWUU_ExternalPinDisable) + { + /* Based on pin index, get register base address. */ + if ((pinIndex >> 4U) != 0U) + { + edgeRegBase = &base->PE2; + eventRegBase = &base->PDC2; + } + else + { + edgeRegBase = &base->PE1; + eventRegBase = &base->PDC1; + } + + /* Enable and config the edge detection. */ + edgeReg = *edgeRegBase; + edgeReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_PE_REG_BIT_FIELD_MASK, offset); + edgeReg |= WUU_SET_BIT_FIELD_IN_REG(config->edge, offset); + *edgeRegBase = edgeReg; + + /* Config the wakeup event. */ + eventReg = *eventRegBase; + eventReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_PDC_REG_BIT_FIELD_MASK, offset); + eventReg |= WUU_SET_BIT_FIELD_IN_REG(config->event, offset); + *eventRegBase = eventReg; + + /* Config operate mode. */ + modeReg = base->PMC; + modeReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_PMC_REG_BIT_FIELD_MASK, pinIndex); + modeReg |= WUU_SET_BIT_FIELD_IN_REG(config->mode, pinIndex); + + base->PMC = modeReg; + } + else + { + /* Based on pin index, get register base address. */ + if ((pinIndex >> 4U) != 0U) + { + edgeRegBase = &base->PE2; + } + else + { + edgeRegBase = &base->PE1; + } + + edgeReg = *edgeRegBase; + edgeReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_PE_REG_BIT_FIELD_MASK, offset); + *edgeRegBase = edgeReg; + } +} + +/*! + * brief Disable and clear external wakeup pin settings. + * + * param base MUU peripheral base address. + * param pinIndex The index of the external input pin. + */ +void WUU_ClearExternalWakeupPinsConfig(WUU_Type *base, uint8_t pinIndex) +{ + if (pinIndex <= 15U) + { + base->PE1 &= ~(WUU_PE_REG_BIT_FIELD_MASK << (2UL * (uint32_t)pinIndex)); + base->PDC1 &= ~(WUU_PDC_REG_BIT_FIELD_MASK << (2UL * (uint32_t)pinIndex)); + } + else + { + base->PE1 &= ~(WUU_PE_REG_BIT_FIELD_MASK << (2UL * (uint32_t)((uint32_t)pinIndex % 16UL))); + base->PDC1 &= ~(WUU_PDC_REG_BIT_FIELD_MASK << (2UL * (uint32_t)((uint32_t)pinIndex % 16UL))); + } +} + +/*! + * brief Config Internal modules' event as the wake up soures. + * + * This function configs the internal modules event as the wake up sources. + * + * param base WUU peripheral base address. + * param moduleIndex The selected internal module. See the Reference Manual for the details. + * param event Select interrupt or DMA/Trigger of the internal module as the wake up source. + */ +void WUU_SetInternalWakeUpModulesConfig(WUU_Type *base, uint8_t moduleIndex, wuu_internal_wakeup_module_event_t event) +{ + switch (event) + { + case kWUU_InternalModuleInterrupt: + base->ME |= WUU_SET_BIT_FIELD_IN_REG(WUU_ME_REG_WUME_FIELD_MASK, moduleIndex); + break; + case kWUU_InternalModuleDMATrigger: + base->DE |= WUU_SET_BIT_FIELD_IN_REG(WUU_DE_REG_WUME_FIELD_MASK, moduleIndex); + break; + default: + assert(false); + break; + } +} + +/*! + * brief Disable an on-chip internal modules' event as the wakeup sources. + * + * param base WUU peripheral base address. + * param moduleIndex The selected internal module. See the Reference Manual for the details. + * param event The event(interrupt or DMA/trigger) of the internal module to disable. + */ +void WUU_ClearInternalWakeUpModulesConfig(WUU_Type *base, uint8_t moduleIndex, wuu_internal_wakeup_module_event_t event) +{ + switch(event) + { + case kWUU_InternalModuleInterrupt: + base->ME &= ~WUU_SET_BIT_FIELD_IN_REG(WUU_ME_REG_WUME_FIELD_MASK, moduleIndex); + break; + case kWUU_InternalModuleDMATrigger: + base->DE &= ~WUU_SET_BIT_FIELD_IN_REG(WUU_DE_REG_WUME_FIELD_MASK, moduleIndex); + break; + default: + assert(false); + break; + } +} + +/*! + * brief Configs and Enables Pin filters. + * + * This function configs Pin filter, including pin select, filer operate mode + * filer wakeup event and filter edge detection. + * + * param base WUU peripheral base address. + * param filterIndex The index of the pin filer. + * param config Pointer to wuu_pin_filter_config_t structure. + */ +void WUU_SetPinFilterConfig(WUU_Type *base, uint8_t filterIndex, const wuu_pin_filter_config_t *config) +{ + assert(config != NULL); + + uint8_t shift; + uint32_t filterReg; + uint32_t eventReg; + uint32_t modeReg; + + shift = (filterIndex - 1U) * 8U; + filterReg = base->FILT; + filterReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_FILT_REG_FILTE_FIELD_MASK, shift); + filterReg |= WUU_SET_BIT_FIELD_IN_REG(WUU_FILT_REG_FILTSET_FIELD(config->edge), shift); + + if (config->edge != kWUU_FilterDisabled) + { + filterReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_FILT_REG_FILTSET_FIELD_MASK, shift); + filterReg |= WUU_SET_BIT_FIELD_IN_REG(config->pinIndex, shift); + + /* Config wake up event. */ + shift = (filterIndex - 1U) * 2U; + eventReg = base->FDC; + eventReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_FDC_REG_FILTC_FIELD_MASK, shift); + eventReg |= WUU_SET_BIT_FIELD_IN_REG(config->event, shift); + base->FDC = eventReg; + + /* Config operate mode. */ + shift = (filterIndex - 1U) * 1U; + modeReg = base->FMC; + modeReg &= WUU_CLEAR_BIT_FIELD_IN_REG(WUU_FMC_REG_FILTM_FIELD_MASK, shift); + modeReg |= WUU_SET_BIT_FIELD_IN_REG(config->mode, shift); + base->FMC = modeReg; + } + + base->FILT = filterReg; +} + +/*! + * brief Gets the pin filter configuration. + * + * This function gets the pin filter flag. + * + * param base WUU peripheral base address. + * param filterIndex A pin filter index, which starts from 1. + * return True if the flag is a source of the existing low-leakage power mode. + */ +bool WUU_GetPinFilterFlag(WUU_Type *base, uint8_t filterIndex) +{ + bool ret = false; + + switch (filterIndex) + { + case 1: + ret = ((base->FILT & WUU_FILT_FILTF1_MASK) != 0U); + break; + case 2: + ret = ((base->FILT & WUU_FILT_FILTF2_MASK) != 0U); + break; + default: + ret = false; + break; + } + + return ret; +} + +/*! + * brief Clears the pin filter configuration. + * + * This function clears the pin filter flag. + * + * param base WUU peripheral base address. + * param filterIndex A pin filter index to clear the flag, starting from 1. + */ +void WUU_ClearPinFilterFlag(WUU_Type *base, uint8_t filterIndex) +{ + uint32_t reg; + + reg = base->FILT; + /* Clean the W1C bits, in case the flags are cleared by mistake. */ + reg &= ~(WUU_FILT_FILTF1_MASK | WUU_FILT_FILTF2_MASK); + + reg |= WUU_SET_BIT_FIELD_IN_REG(WUU_FILT_FILTF1_MASK, ((filterIndex - 1U) * 8U)); + + base->FILT = reg; +} + +/*! + * brief Gets the external wakeup source flag. + * + * This function checks the external pin flag to detect whether the MCU is + * woken up by the specific pin. + * + * param base WUU peripheral base address. + * param pinIndex A pin index, which starts from 0. + * return True if the specific pin is a wakeup source. + */ +bool WUU_GetExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex) +{ + return (0U != (base->PF & (1UL << pinIndex))); +} + +/*! + * brief Clears the external wakeup source flag. + * + * This function clears the external wakeup source flag for a specific pin. + * + * param base WUU peripheral base address. + * param pinIndex A pin index, which starts from 0. + */ +void WUU_ClearExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex) +{ + base->PF = (1UL << pinIndex); +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_wuu.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_wuu.h new file mode 100644 index 00000000000..bedfde56859 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_wuu.h @@ -0,0 +1,294 @@ +/* + * Copyright 2019-2024 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_WUU_H_ +#define FSL_WUU_H_ + +#include "fsl_common.h" + +/*! @addtogroup wuu */ +/*! @{ */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief Defines WUU driver version 2.4.0. */ +#define FSL_WUU_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) +/*! @} */ + +/*! + * @brief External WakeUp pin edge detection enumeration. + */ +typedef enum _wuu_external_pin_edge_detection +{ + kWUU_ExternalPinDisable = 0x0U, /*!< External input Pin disabled as wake up input. */ + kWUU_ExternalPinRisingEdge = 0x1U, /*!< External input Pin enabled with the rising edge detection. */ + kWUU_ExternalPinFallingEdge = 0x2U, /*!< External input Pin enabled with the falling edge detection. */ + kWUU_ExternalPinAnyEdge = 0x3U, /*!< External input Pin enabled with any change detection. */ +} wuu_external_pin_edge_detection_t; + +/*! + * @brief External input wake up pin event enumeration. + */ +typedef enum _wuu_external_wakeup_pin_event +{ + kWUU_ExternalPinInterrupt = 0x0U, /*!< External input Pin configured as interrupt. */ + kWUU_ExternalPinDMARequest = 0x1U, /*!< External input Pin configured as DMA request. */ + kWUU_ExternalPinTriggerEvent = 0x2U, /*!< External input Pin configured as Trigger event. */ +} wuu_external_wakeup_pin_event_t; + +/*! + * @brief External input wake up pin mode enumeration. + */ +typedef enum _wuu_external_wakeup_pin_mode +{ + kWUU_ExternalPinActiveDSPD = 0x0U, /*!< External input Pin is active only during Deep Sleep/Power Down Mode. */ + kWUU_ExternalPinActiveAlways = 0x1U, /*!< External input Pin is active during all power modes. */ +} wuu_external_wakeup_pin_mode_t; + +/*! + * @brief Internal module wake up event enumeration. + */ +typedef enum _wuu_internal_wakeup_module_event +{ + kWUU_InternalModuleInterrupt = 0x0U, /*!< Internal modules' interrupt as a wakeup source. */ + kWUU_InternalModuleDMATrigger = 0x1U, /*!< Internal modules' DMA/Trigger as a wakeup source. */ +} wuu_internal_wakeup_module_event_t; + +/*! + * @brief Pin filter edge enumeration. + */ +typedef enum _wuu_filter_edge +{ + kWUU_FilterDisabled = 0x0U, /*!< Filter disabled. */ + kWUU_FilterPosedgeEnable = 0x1U, /*!< Filter posedge detect enabled. */ + kWUU_FilterNegedgeEnable = 0x2U, /*!< Filter negedge detect enabled. */ + kWUU_FilterAnyEdge = 0x3U, /*!< Filter any edge detect enabled. */ +} wuu_filter_edge_t; + +/*! + * @brief Pin Filter event enumeration. + */ +typedef enum _wuu_filter_event +{ + kWUU_FilterInterrupt = 0x0U, /*!< Filter output configured as interrupt. */ + kWUU_FilterDMARequest = 0x1U, /*!< Filter output configured as DMA request. */ + kWUU_FilterTriggerEvent = 0x2U, /*!< Filter output configured as Trigger event. */ +} wuu_filter_event_t; + +/*! + * @brief Pin filter mode enumeration. + */ +typedef enum _wuu_filter_mode +{ + kWUU_FilterActiveDSPD = 0x0U, /*!< External input pin filter is active only during Deep Sleep/Power Down Mode. */ + kWUU_FilterActiveAlways = 0x1U, /*!< External input Pin filter is active during all power modes. */ +} wuu_filter_mode_t; + +/*! + * @brief External WakeUp pin configuration + */ +typedef struct _wuu_external_wakeup_pin_config +{ + wuu_external_pin_edge_detection_t edge; /*!< External Input pin edge detection. */ + wuu_external_wakeup_pin_event_t event; /*!< External Input wakeup Pin event */ + wuu_external_wakeup_pin_mode_t mode; /*!< External Input wakeup Pin operate mode. */ +} wuu_external_wakeup_pin_config_t; + +/*! + * @brief Pin Filter configuration. + */ +typedef struct _wuu_pin_filter_config +{ + uint32_t pinIndex; /*!< The index of wakeup pin to be muxxed into filter. */ + wuu_filter_edge_t edge; /*!< The edge of the pin digital filter. */ + wuu_filter_event_t event; /*!< The event of the filter output. */ + wuu_filter_mode_t mode; /*!< The mode of the filter operate. */ +} wuu_pin_filter_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name External Wake up Pins Control APIs. + * @{ + */ +/*! + * @brief Enables and Configs External WakeUp Pins. + * + * This function enables/disables the external pin as wakeup input. What's more this + * function configs pins options, including edge detection wakeup event and operate mode. + * + * @param base MUU peripheral base address. + * @param pinIndex The index of the external input pin. See Reference Manual for the details. + * @param config Pointer to wuu_external_wakeup_pin_config_t structure. + */ +void WUU_SetExternalWakeUpPinsConfig(WUU_Type *base, uint8_t pinIndex, const wuu_external_wakeup_pin_config_t *config); + +/*! + * @brief Disable and clear external wakeup pin settings. + * + * @param base MUU peripheral base address. + * @param pinIndex The index of the external input pin. + */ +void WUU_ClearExternalWakeupPinsConfig(WUU_Type *base, uint8_t pinIndex); + +/*! + * @brief Gets External Wakeup pin flags. + * + * This function return the external wakeup pin flags. + * + * @param base WUU peripheral base address. + * @return Wakeup flags for all external wakeup pins. + */ +static inline uint32_t WUU_GetExternalWakeUpPinsFlag(WUU_Type *base) +{ + return base->PF; +} + +/*! + * @brief Clears External WakeUp Pin flags. + * + * This function clears external wakeup pins flags based on the mask. + * + * @param base WUU peripheral base address. + * @param mask The mask of Wakeup pin index to be cleared. + */ +static inline void WUU_ClearExternalWakeUpPinsFlag(WUU_Type *base, uint32_t mask) +{ + base->PF = mask; +} +/*! @} */ + +/*! + * @name Internal Wakeup Module control APIs. + * @{ + */ + +/*! + * @brief Config Internal modules' event as the wake up soures. + * + * This function configs the internal modules event as the wake up sources. + * + * @param base WUU peripheral base address. + * @param moduleIndex The selected internal module. See the Reference Manual for the details. + * @param event Select interrupt or DMA/Trigger of the internal module as the wake up source. + */ +void WUU_SetInternalWakeUpModulesConfig(WUU_Type *base, uint8_t moduleIndex, wuu_internal_wakeup_module_event_t event); + +/*! + * @brief Disable an on-chip internal modules' event as the wakeup sources. + * + * @param base WUU peripheral base address. + * @param moduleIndex The selected internal module. See the Reference Manual for the details. + * @param event The event(interrupt or DMA/trigger) of the internal module to disable. + */ +void WUU_ClearInternalWakeUpModulesConfig(WUU_Type *base, uint8_t moduleIndex, wuu_internal_wakeup_module_event_t event); + +#if (defined(FSL_FEATURE_WUU_HAS_MF) && FSL_FEATURE_WUU_HAS_MF) +/*! + * @brief Get wakeup flags for internal wakeup modules. + * + * @param base WUU peripheral base address. + * @return Wakeup flags for all internal wakeup modules. + */ +static inline uint32_t WUU_GetModuleInterruptFlag(WUU_Type *base) +{ + return base->MF; +} + +/*! + * @brief Gets the internal module wakeup source flag. + * + * This function checks the flag to detect whether the system is + * woken up by specific on-chip module interrupt. + * + * @param base WWU peripheral base address. + * @param moduleIndex A module index, which starts from 0. + * @return True if the specific pin is a wake up source. + */ +static inline bool WUU_GetInternalWakeupModuleFlag(WUU_Type *base, uint32_t moduleIndex) +{ + return ((1UL << moduleIndex) == (WUU_GetModuleInterruptFlag(base) & (1UL << moduleIndex))); +} +#endif /* FSL_FEATURE_WUU_HAS_MF */ + +/*! @} */ + +/*! + * @name Pin Filter Control APIs + * @{ + */ +/*! + * @brief Configs and Enables Pin filters. + * + * This function configs Pin filter, including pin select, filer operate mode + * filer wakeup event and filter edge detection. + * + * @param base WUU peripheral base address. + * @param filterIndex The index of the pin filer. + * @param config Pointer to wuu_pin_filter_config_t structure. + */ +void WUU_SetPinFilterConfig(WUU_Type *base, uint8_t filterIndex, const wuu_pin_filter_config_t *config); + +/*! + * @brief Gets the pin filter configuration. + * + * This function gets the pin filter flag. + * + * @param base WUU peripheral base address. + * @param filterIndex A pin filter index, which starts from 1. + * @return True if the flag is a source of the existing low-leakage power mode. + */ +bool WUU_GetPinFilterFlag(WUU_Type *base, uint8_t filterIndex); + +/*! + * @brief Clears the pin filter configuration. + * + * This function clears the pin filter flag. + * + * @param base WUU peripheral base address. + * @param filterIndex A pin filter index to clear the flag, starting from 1. + */ +void WUU_ClearPinFilterFlag(WUU_Type *base, uint8_t filterIndex); + +/*! + * brief Gets the external wakeup source flag. + * + * This function checks the external pin flag to detect whether the MCU is + * woken up by the specific pin. + * + * param base WUU peripheral base address. + * param pinIndex A pin index, which starts from 0. + * return True if the specific pin is a wakeup source. + */ +bool WUU_GetExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex); + +/*! + * brief Clears the external wakeup source flag. + * + * This function clears the external wakeup source flag for a specific pin. + * + * param base WUU peripheral base address. + * param pinIndex A pin index, which starts from 0. + */ +void WUU_ClearExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex); +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /*FSL_WUU_H_*/ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_wwdt.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_wwdt.c new file mode 100644 index 00000000000..6680148acf7 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_wwdt.c @@ -0,0 +1,275 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_wwdt.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.wwdt" +#endif + +#define FREQUENCY_3MHZ (3000000U) +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/*! + * @brief Gets the instance from the base address + * + * @param base WWDT peripheral base address + * + * @return The WWDT instance + */ +static uint32_t WWDT_GetInstance(WWDT_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to WWDT bases for each instance. */ +static WWDT_Type *const s_wwdtBases[] = WWDT_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to WWDT clocks for each instance. */ +static const clock_ip_name_t s_wwdtClocks[] = WWDT_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) +/*! @brief Pointers to WWDT resets for each instance. */ +static const reset_ip_name_t s_wwdtResets[] = WWDT_RSTS; +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t WWDT_GetInstance(WWDT_Type *base) +{ + uint32_t instance; + uint32_t wwdtArrayCount = (sizeof(s_wwdtBases) / sizeof(s_wwdtBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < wwdtArrayCount; instance++) + { + if (s_wwdtBases[instance] == base) + { + break; + } + } + + assert(instance < wwdtArrayCount); + + return instance; +} + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Initializes WWDT configure structure. + * + * This function initializes the WWDT configure structure to default value. The default + * value are: + * code + * config->enableWwdt = true; + * config->enableWatchdogReset = false; + * config->enableWatchdogProtect = false; + * config->enableLockOscillator = false; + * config->windowValue = 0xFFFFFFU; + * config->timeoutValue = 0xFFFFFFU; + * config->warningValue = 0; + * endcode + * + * param config Pointer to WWDT config structure. + * see wwdt_config_t + */ +void WWDT_GetDefaultConfig(wwdt_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + /* Enable the watch dog */ + config->enableWwdt = true; + /* Disable the watchdog timeout reset */ + config->enableWatchdogReset = false; + /* Disable the watchdog protection for updating the timeout value */ + config->enableWatchdogProtect = false; +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) + /* Do not lock the watchdog oscillator */ + config->enableLockOscillator = false; +#endif + /* Windowing is not in effect */ + config->windowValue = 0xFFFFFFU; + /* Set the timeout value to the max */ + config->timeoutValue = 0xFFFFFFU; + /* No warning is provided */ + config->warningValue = 0; + /* Set clock frequency. */ + config->clockFreq_Hz = 0U; +} + +/*! + * brief Initializes the WWDT. + * + * This function initializes the WWDT. When called, the WWDT runs according to the configuration. + * + * Example: + * code + * wwdt_config_t config; + * WWDT_GetDefaultConfig(&config); + * config.timeoutValue = 0x7ffU; + * WWDT_Init(wwdt_base,&config); + * endcode + * + * param base WWDT peripheral base address + * param config The configuration of WWDT + */ +void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config) +{ + assert(NULL != config); + + uint32_t value = 0U; + uint32_t DelayUs = 0U; + uint32_t primaskValue = 0U; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the WWDT clock */ + CLOCK_EnableClock(s_wwdtClocks[WWDT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_RESET) && FSL_FEATURE_WWDT_HAS_NO_RESET) + /* Reset the module. */ + RESET_PeripheralReset(s_wwdtResets[WWDT_GetInstance(base)]); +#endif + +#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) + /* PMC RESETCAUSE: set bit to clear it by write 1. */ + PMC->RESETCAUSE = PMC_RESETCAUSE_WDTRESET_MASK; + /* Enable the watchdog reset event to affect the system in the Power Management Controller */ + PMC->CTRL |= PMC_CTRL_WDTRESETENABLE_MASK; +#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ + +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) + value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset) | + WWDT_MOD_LOCK(config->enableLockOscillator); +#else + value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset); +#endif + /* Clear legacy flag in the MOD register by software writing a "1" to this bit field.. */ + if (0U != (base->MOD & WWDT_MOD_WDINT_MASK)) + { + value |= WWDT_MOD_WDINT_MASK; + } + /* Set configuration */ + primaskValue = DisableGlobalIRQ(); + base->TC = WWDT_TC_COUNT(config->timeoutValue); + base->MOD = value; + base->WINDOW = WWDT_WINDOW_WINDOW(config->windowValue); + base->WARNINT = WWDT_WARNINT_WARNINT(config->warningValue); + /* Refreshes the WWDT timer. */ + base->FEED = WWDT_FIRST_WORD_OF_REFRESH; + base->FEED = WWDT_SECOND_WORD_OF_REFRESH; + EnableGlobalIRQ(primaskValue); + /* Read counter value to wait wwdt timer start*/ + if (config->enableWwdt) + { + while (base->TV == 0xFFUL) + { + } + } + + /* This WDPROTECT bit can be set once by software and is only cleared by a reset */ + if (config->enableWatchdogProtect && (0U == (base->MOD & WWDT_MOD_WDPROTECT_MASK))) + { + /* The config->clockFreq_Hz must be set in order to config the delay time. */ + assert(0U != config->clockFreq_Hz); + + /* Set the WDPROTECT bit after the Feed Sequence (0xAA, 0x55) with 3 WDCLK delay */ + DelayUs = FREQUENCY_3MHZ / config->clockFreq_Hz + 1U; + SDK_DelayAtLeastUs(DelayUs, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + base->MOD |= WWDT_MOD_WDPROTECT(1U); + } +} + +/*! + * brief Shuts down the WWDT. + * + * This function shuts down the WWDT. + * + * param base WWDT peripheral base address + */ +void WWDT_Deinit(WWDT_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the WWDT clock */ + CLOCK_DisableClock(s_wwdtClocks[WWDT_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Refreshes the WWDT timer. + * + * This function feeds the WWDT. + * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. + * + * param base WWDT peripheral base address + */ +void WWDT_Refresh(WWDT_Type *base) +{ + uint32_t primaskValue = 0U; + + /* Disable the global interrupt to protect refresh sequence */ + primaskValue = DisableGlobalIRQ(); + base->FEED = WWDT_FIRST_WORD_OF_REFRESH; + base->FEED = WWDT_SECOND_WORD_OF_REFRESH; + EnableGlobalIRQ(primaskValue); +} + +/*! + * brief Clear WWDT flag. + * + * This function clears WWDT status flag. + * + * Example for clearing warning flag: + * code + * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); + * endcode + * param base WWDT peripheral base address + * param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::_wwdt_status_flags_t + */ +void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask) +{ + /* Clear the WDINT bit so that we don't accidentally clear it */ + uint32_t reg = (base->MOD & (~WWDT_MOD_WDINT_MASK)); + + /* Clear timeout by writing a zero */ + if (0U != (mask & (uint32_t)kWWDT_TimeoutFlag)) + { + reg &= ~WWDT_MOD_WDTOF_MASK; +#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) + /* PMC RESETCAUSE: set bit to clear it */ + PMC->RESETCAUSE = PMC_RESETCAUSE_WDTRESET_MASK; +#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ + } + + /* Clear warning interrupt flag by writing a one */ + if (0U != (mask & (uint32_t)kWWDT_WarningFlag)) + { + reg |= WWDT_MOD_WDINT_MASK; + } + + base->MOD = reg; +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_wwdt.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_wwdt.h new file mode 100644 index 00000000000..40c90e48b38 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/drivers/fsl_wwdt.h @@ -0,0 +1,276 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef FSL_WWDT_H_ +#define FSL_WWDT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup wwdt + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @name Driver version */ +/*! @{ */ +/*! @brief Defines WWDT driver version. */ +#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 1, 9)) +/*! @} */ + +/*! @name Refresh sequence */ +/*! @{ */ +#define WWDT_FIRST_WORD_OF_REFRESH (0xAAU) /*!< First word of refresh sequence */ +#define WWDT_SECOND_WORD_OF_REFRESH (0x55U) /*!< Second word of refresh sequence */ +/*! @} */ + +/*! @brief Describes WWDT configuration structure. */ +typedef struct _wwdt_config +{ + bool enableWwdt; /*!< Enables or disables WWDT */ + bool enableWatchdogReset; /*!< true: Watchdog timeout will cause a chip reset + false: Watchdog timeout will not cause a chip reset */ + bool enableWatchdogProtect; /*!< true: Enable watchdog protect i.e timeout value can only be + changed after counter is below warning & window values + false: Disable watchdog protect; timeout value can be changed + at any time */ +#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) + bool enableLockOscillator; /*!< true: Disabling or powering down the watchdog oscillator is prevented + Once set, this bit can only be cleared by a reset + false: Do not lock oscillator */ +#endif + uint32_t windowValue; /*!< Window value, set this to 0xFFFFFF if windowing is not in effect */ + uint32_t timeoutValue; /*!< Timeout value */ + uint32_t warningValue; /*!< Watchdog time counter value that will generate a + warning interrupt. Set this to 0 for no warning */ + uint32_t clockFreq_Hz; /*!< Watchdog clock source frequency. */ +} wwdt_config_t; + +/*! + * @brief WWDT status flags. + * + * This structure contains the WWDT status flags for use in the WWDT functions. + */ +enum _wwdt_status_flags_t +{ + kWWDT_TimeoutFlag = WWDT_MOD_WDTOF_MASK, /*!< Time-out flag, set when the timer times out */ + kWWDT_WarningFlag = WWDT_MOD_WDINT_MASK /*!< Warning interrupt flag, set when timer is below the value WDWARNINT */ +}; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @name WWDT Initialization and De-initialization + * @{ + */ + +/*! + * @brief Initializes WWDT configure structure. + * + * This function initializes the WWDT configure structure to default value. The default + * value are: + * @code + * config->enableWwdt = true; + * config->enableWatchdogReset = false; + * config->enableWatchdogProtect = false; + * config->enableLockOscillator = false; + * config->windowValue = 0xFFFFFFU; + * config->timeoutValue = 0xFFFFFFU; + * config->warningValue = 0; + * @endcode + * + * @param config Pointer to WWDT config structure. + * @see wwdt_config_t + */ +void WWDT_GetDefaultConfig(wwdt_config_t *config); + +/*! + * @brief Initializes the WWDT. + * + * This function initializes the WWDT. When called, the WWDT runs according to the configuration. + * + * Example: + * @code + * wwdt_config_t config; + * WWDT_GetDefaultConfig(&config); + * config.timeoutValue = 0x7ffU; + * WWDT_Init(wwdt_base,&config); + * @endcode + * + * @param base WWDT peripheral base address + * @param config The configuration of WWDT + */ +void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config); + +/*! + * @brief Shuts down the WWDT. + * + * This function shuts down the WWDT. + * + * @param base WWDT peripheral base address + */ +void WWDT_Deinit(WWDT_Type *base); + +/*! @} */ + +/*! + * @name WWDT Functional Operation + * @{ + */ + +/*! + * @brief Enables the WWDT module. + * + * This function write value into WWDT_MOD register to enable the WWDT, it is a write-once bit; + * once this bit is set to one and a watchdog feed is performed, the watchdog timer will run + * permanently. + * + * @param base WWDT peripheral base address + */ +static inline void WWDT_Enable(WWDT_Type *base) +{ + base->MOD |= WWDT_MOD_WDEN_MASK; +} + +/*! + * @brief Disables the WWDT module. + * @deprecated Do not use this function. It will be deleted in next release version, for + * once the bit field of WDEN written with a 1, it can not be re-written with a 0. + * + * This function write value into WWDT_MOD register to disable the WWDT. + * + * @param base WWDT peripheral base address + */ +static inline void WWDT_Disable(WWDT_Type *base) +{ + base->MOD &= ~WWDT_MOD_WDEN_MASK; +} + +/*! + * @brief Gets all WWDT status flags. + * + * This function gets all status flags. + * + * Example for getting Timeout Flag: + * @code + * uint32_t status; + * status = WWDT_GetStatusFlags(wwdt_base) & kWWDT_TimeoutFlag; + * @endcode + * @param base WWDT peripheral base address + * @return The status flags. This is the logical OR of members of the + * enumeration ::_wwdt_status_flags_t + */ +static inline uint32_t WWDT_GetStatusFlags(WWDT_Type *base) +{ +#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) + uint32_t status; + /* WDTOF is not set in case of WD reset - get info from PMC instead */ + status = (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK)); + if (PMC->RESETCAUSE & PMC_RESETCAUSE_WDTRESET_MASK) + { + status |= kWWDT_TimeoutFlag; + } + return status; +#else + return (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK)); +#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ +} + +/*! + * @brief Clear WWDT flag. + * + * This function clears WWDT status flag. + * + * Example for clearing warning flag: + * @code + * WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag); + * @endcode + * @param base WWDT peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::_wwdt_status_flags_t + */ +void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask); + +/*! + * @brief Set the WWDT warning value. + * + * The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog + * interrupt. When the watchdog timer counter is no longer greater than the value defined by + * WARNINT, an interrupt will be generated after the subsequent WDCLK. + * + * @param base WWDT peripheral base address + * @param warningValue WWDT warning value. + */ +static inline void WWDT_SetWarningValue(WWDT_Type *base, uint32_t warningValue) +{ + base->WARNINT = WWDT_WARNINT_WARNINT(warningValue); +} + +/*! + * @brief Set the WWDT timeout value. + * + * This function sets the timeout value. Every time a feed sequence occurs the value in the TC + * register is loaded into the Watchdog timer. Writing a value below 0xFF will cause 0xFF to be + * loaded into the TC register. Thus the minimum time-out interval is TWDCLK*256*4. + * If enableWatchdogProtect flag is true in wwdt_config_t config structure, any attempt to change + * the timeout value before the watchdog counter is below the warning and window values + * will cause a watchdog reset and set the WDTOF flag. + * + * @param base WWDT peripheral base address + * @param timeoutCount WWDT timeout value, count of WWDT clock tick. + */ +static inline void WWDT_SetTimeoutValue(WWDT_Type *base, uint32_t timeoutCount) +{ + base->TC = WWDT_TC_COUNT(timeoutCount); +} + +/*! + * @brief Sets the WWDT window value. + * + * The WINDOW register determines the highest TV value allowed when a watchdog feed is performed. + * If a feed sequence occurs when timer value is greater than the value in WINDOW, a watchdog + * event will occur. To disable windowing, set windowValue to 0xFFFFFF (maximum possible timer + * value) so windowing is not in effect. + * + * @param base WWDT peripheral base address + * @param windowValue WWDT window value. + */ +static inline void WWDT_SetWindowValue(WWDT_Type *base, uint32_t windowValue) +{ + base->WINDOW = WWDT_WINDOW_WINDOW(windowValue); +} + +/*! + * @brief Refreshes the WWDT timer. + * + * This function feeds the WWDT. + * This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted. + * + * @param base WWDT peripheral base address + */ +void WWDT_Refresh(WWDT_Type *base); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* FSL_WWDT_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/fsl_device_registers.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/fsl_device_registers.h new file mode 100644 index 00000000000..03536b56623 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/fsl_device_registers.h @@ -0,0 +1,33 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2024 NXP + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_MCXA156VLL) || defined(CPU_MCXA156VMP) || defined(CPU_MCXA156VPJ)) + +#define MCXA156_SERIES + +/* CMSIS-style register definitions */ +#include "MCXA156.h" +/* CPU specific feature definitions */ +#include "MCXA156_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/gcc/MCXA156_flash.ld b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/gcc/MCXA156_flash.ld new file mode 100644 index 00000000000..efc24cbe150 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/gcc/MCXA156_flash.ld @@ -0,0 +1,200 @@ +/* +** ################################################################### +** Processors: MCXA156VLL +** MCXA156VMP +** MCXA156VPJ +** +** Compiler: GNU C Compiler +** Reference manual: MCXA18 User manual +** Version: rev. 1.0, 2022-03-29 +** Build: b240104 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000200 + m_text (RX) : ORIGIN = 0x00000200, LENGTH = 0x000FFE00 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x0001E000 + m_sramx0 (RW) : ORIGIN = 0x04000000, LENGTH = 0x00002000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/gcc/MCXA156_ram.ld b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/gcc/MCXA156_ram.ld new file mode 100644 index 00000000000..0abc11aca2c --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/gcc/MCXA156_ram.ld @@ -0,0 +1,199 @@ +/* +** ################################################################### +** Processors: MCXA156VLL +** MCXA156VMP +** MCXA156VPJ +** +** Compiler: GNU C Compiler +** Reference manual: MCXA18 User manual +** Version: rev. 1.0, 2022-03-29 +** Build: b240104 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x20000000, LENGTH = 0x00000200 + m_text (RX) : ORIGIN = 0x20000200, LENGTH = 0x00005E00 + m_data (RW) : ORIGIN = 0x20006000, LENGTH = 0x00018000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/gcc/startup_MCXA156.S b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/gcc/startup_MCXA156.S new file mode 100644 index 00000000000..22c1e7ae379 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/gcc/startup_MCXA156.S @@ -0,0 +1,1211 @@ +/* ------------------------------------------------------------------------- */ +/* @file: startup_MCXA156.s */ +/* @purpose: CMSIS Cortex-M33 Core Device Startup File */ +/* MCXA156 */ +/* @version: 1.0 */ +/* @date: 2022-3-29 */ +/* @build: b231107 */ +/* ------------------------------------------------------------------------- */ +/* */ +/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ +/* Copyright 2016-2023 NXP */ +/* SPDX-License-Identifier: BSD-3-Clause */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv8-m.main + + .section .isr_vector, "a" + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long SecureFault_Handler /* Secure Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long Reserved16_IRQHandler /* OR IRQ1 to IRQ53*/ + .long CMC_IRQHandler /* Core Mode Controller interrupt*/ + .long DMA_CH0_IRQHandler /* DMA3_0_CH0 error or transfer complete*/ + .long DMA_CH1_IRQHandler /* DMA3_0_CH1 error or transfer complete*/ + .long DMA_CH2_IRQHandler /* DMA3_0_CH2 error or transfer complete*/ + .long DMA_CH3_IRQHandler /* DMA3_0_CH3 error or transfer complete*/ + .long DMA_CH4_IRQHandler /* DMA3_0_CH4 error or transfer complete*/ + .long DMA_CH5_IRQHandler /* DMA3_0_CH5 error or transfer complete*/ + .long DMA_CH6_IRQHandler /* DMA3_0_CH6 error or transfer complete*/ + .long DMA_CH7_IRQHandler /* DMA3_0_CH7 error or transfer complete*/ + .long ERM0_SINGLE_BIT_IRQHandler /* ERM Single Bit error interrupt*/ + .long ERM0_MULTI_BIT_IRQHandler /* ERM Multi Bit error interrupt*/ + .long FMU0_IRQHandler /* Flash Management Unit interrupt*/ + .long GLIKEY0_IRQHandler /* GLIKEY Interrupt */ + .long MBC0_IRQHandler /* MBC secure violation interrupt*/ + .long SCG0_IRQHandler /* System Clock Generator interrupt*/ + .long SPC0_IRQHandler /* System Power Controller interrupt*/ + .long VBAT0_IRQHandler /* VBAT interrupt*/ + .long WUU0_IRQHandler /* Wake Up Unit interrupt*/ + .long CAN0_IRQHandler /* Controller Area Network 0 interrupt*/ + .long Reserved36_IRQHandler /* Reserved interrupt*/ + .long Reserved37_IRQHandler /* Reserved interrupt*/ + .long Reserved38_IRQHandler /* Reserved interrupt*/ + .long FLEXIO_IRQHandler /* Flexible Input/Output interrupt*/ + .long I3C0_IRQHandler /* Improved Inter Integrated Circuit interrupt 0*/ + .long Reserved41_IRQHandler /* Reserved interrupt*/ + .long LPI2C0_IRQHandler /* Low-Power Inter Integrated Circuit interrupt*/ + .long LPI2C1_IRQHandler /* Low-Power Inter Integrated Circuit interrupt*/ + .long LPSPI0_IRQHandler /* Low-Power Serial Peripheral Interface interrupt*/ + .long LPSPI1_IRQHandler /* Low-Power Serial Peripheral Interface interrupt*/ + .long Reserved46_IRQHandler /* Reserved interrupt*/ + .long LPUART0_IRQHandler /* Low-Power Universal Asynchronous Receive/Transmit interrupt*/ + .long LPUART1_IRQHandler /* Low-Power Universal Asynchronous Receive/Transmit interrupt*/ + .long LPUART2_IRQHandler /* Low-Power Universal Asynchronous Receive/Transmit interrupt*/ + .long LPUART3_IRQHandler /* Low-Power Universal Asynchronous Receive/Transmit interrupt*/ + .long LPUART4_IRQHandler /* Low-Power Universal Asynchronous Receive/Transmit interrupt*/ + .long USB0_IRQHandler /* Universal Serial Bus - Full Speed interrupt*/ + .long Reserved53_IRQHandler /* Reserved interrupt*/ + .long CDOG0_IRQHandler /* Code Watchdog Timer 0 interrupt*/ + .long CTIMER0_IRQHandler /* Standard counter/timer 0 interrupt*/ + .long CTIMER1_IRQHandler /* Standard counter/timer 1 interrupt*/ + .long CTIMER2_IRQHandler /* Standard counter/timer 2 interrupt*/ + .long CTIMER3_IRQHandler /* Standard counter/timer 3 interrupt*/ + .long CTIMER4_IRQHandler /* Standard counter/timer 4 interrupt*/ + .long FLEXPWM0_RELOAD_ERROR_IRQHandler /* FlexPWM0_reload_error interrupt*/ + .long FLEXPWM0_FAULT_IRQHandler /* FlexPWM0_fault interrupt*/ + .long FLEXPWM0_SUBMODULE0_IRQHandler /* FlexPWM0 Submodule 0 capture/compare/reload interrupt*/ + .long FLEXPWM0_SUBMODULE1_IRQHandler /* FlexPWM0 Submodule 1 capture/compare/reload interrupt*/ + .long FLEXPWM0_SUBMODULE2_IRQHandler /* FlexPWM0 Submodule 2 capture/compare/reload interrupt*/ + .long Reserved65_IRQHandler /* Reserved interrupt*/ + .long QDC0_COMPARE_IRQHandler /* Compare*/ + .long QDC0_HOME_IRQHandler /* Home*/ + .long QDC0_WATCHDOG_IRQHandler /* Watchdog / Simultaneous A and B Change*/ + .long QDC0_INDEX_IRQHandler /* Index / Roll Over / Roll Under*/ + .long FREQME0_IRQHandler /* Frequency Measurement interrupt*/ + .long LPTMR0_IRQHandler /* Low Power Timer 0 interrupt*/ + .long Reserved72_IRQHandler /* Reserved interrupt*/ + .long OS_EVENT_IRQHandler /* OS event timer interrupt*/ + .long WAKETIMER0_IRQHandler /* Wake Timer Interrupt*/ + .long UTICK0_IRQHandler /* Micro-Tick Timer interrupt*/ + .long WWDT0_IRQHandler /* Windowed Watchdog Timer 0 interrupt*/ + .long Reserved77_IRQHandler /* Reserved interrupt*/ + .long ADC0_IRQHandler /* Analog-to-Digital Converter interrupt*/ + .long ADC1_IRQHandler /* Analog-to-Digital Converter interrupt*/ + .long CMP0_IRQHandler /* Comparator interrupt*/ + .long CMP1_IRQHandler /* Comparator interrupt*/ + .long Reserved82_IRQHandler /* Reserved interrupt*/ + .long DAC0_IRQHandler /* Digital-to-Analog Converter 0 - General Purpose interrupt*/ + .long Reserved84_IRQHandler /* Reserved interrupt*/ + .long Reserved85_IRQHandler /* Reserved interrupt*/ + .long Reserved86_IRQHandler /* Reserved interrupt*/ + .long GPIO0_IRQHandler /* General Purpose Input/Output interrupt 0*/ + .long GPIO1_IRQHandler /* General Purpose Input/Output interrupt 1*/ + .long GPIO2_IRQHandler /* General Purpose Input/Output interrupt 2*/ + .long GPIO3_IRQHandler /* General Purpose Input/Output interrupt 3*/ + .long GPIO4_IRQHandler /* General Purpose Input/Output interrupt 4*/ + .long Reserved92_IRQHandler /* Reserved interrupt*/ + .long LPI2C2_IRQHandler /* Low-Power Inter Integrated Circuit interrupt*/ + .long LPI2C3_IRQHandler /* Low-Power Inter Integrated Circuit interrupt*/ + .long FLEXPWM1_RELOAD_ERROR_IRQHandler /* FlexPWM1_reload_error interrupt*/ + .long FLEXPWM1_FAULT_IRQHandler /* FlexPWM1_fault interrupt*/ + .long FLEXPWM1_SUBMODULE0_IRQHandler /* FlexPWM1 Submodule 0 capture/compare/reload interrupt*/ + .long FLEXPWM1_SUBMODULE1_IRQHandler /* FlexPWM1 Submodule 1 capture/compare/reload interrupt*/ + .long FLEXPWM1_SUBMODULE2_IRQHandler /* FlexPWM1 Submodule 2 capture/compare/reload interrupt*/ + .long Reserved100_IRQHandler /* Reserved interrupt*/ + .long QDC1_COMPARE_IRQHandler /* Compare*/ + .long QDC1_HOME_IRQHandler /* Home*/ + .long QDC1_WATCHDOG_IRQHandler /* Watchdog / Simultaneous A and B Change*/ + .long QDC1_INDEX_IRQHandler /* Index / Roll Over / Roll Under*/ + + .size __Vectors, . - __Vectors + + .text + .thumb + +#if defined (__cplusplus) +#ifdef __REDLIB__ +#error Redlib does not support C++ +#endif +#endif +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__Vectors + str r1, [r0] + ldr r2, [r1] + msr msp, r2 + ldr r0, =__StackLimit + msr msplim, r0 +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + +/* Add stack / heap initializaiton */ + movs r0, 0 + ldr r1, =__HeapBase + ldr r2, =__HeapLimit +.LC3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC3 + + ldr r1, =__StackLimit + ldr r2, =__StackTop +.LC4: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC4 + +/*End of stack / heap initializaiton */ + cpsie i /* Unmask interrupts */ +#ifndef __START +#ifdef __REDLIB__ +#define __START __main +#else +#define __START _start +#endif +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + + .align 1 + .thumb_func + .weak Reserved16_IRQHandler + .type Reserved16_IRQHandler, %function +Reserved16_IRQHandler: + ldr r0,=Reserved16_DriverIRQHandler + bx r0 + .size Reserved16_IRQHandler, . - Reserved16_IRQHandler + + .align 1 + .thumb_func + .weak CMC_IRQHandler + .type CMC_IRQHandler, %function +CMC_IRQHandler: + ldr r0,=CMC_DriverIRQHandler + bx r0 + .size CMC_IRQHandler, . - CMC_IRQHandler + + .align 1 + .thumb_func + .weak DMA_CH0_IRQHandler + .type DMA_CH0_IRQHandler, %function +DMA_CH0_IRQHandler: + ldr r0,=DMA_CH0_DriverIRQHandler + bx r0 + .size DMA_CH0_IRQHandler, . - DMA_CH0_IRQHandler + + .align 1 + .thumb_func + .weak DMA_CH1_IRQHandler + .type DMA_CH1_IRQHandler, %function +DMA_CH1_IRQHandler: + ldr r0,=DMA_CH1_DriverIRQHandler + bx r0 + .size DMA_CH1_IRQHandler, . - DMA_CH1_IRQHandler + + .align 1 + .thumb_func + .weak DMA_CH2_IRQHandler + .type DMA_CH2_IRQHandler, %function +DMA_CH2_IRQHandler: + ldr r0,=DMA_CH2_DriverIRQHandler + bx r0 + .size DMA_CH2_IRQHandler, . - DMA_CH2_IRQHandler + + .align 1 + .thumb_func + .weak DMA_CH3_IRQHandler + .type DMA_CH3_IRQHandler, %function +DMA_CH3_IRQHandler: + ldr r0,=DMA_CH3_DriverIRQHandler + bx r0 + .size DMA_CH3_IRQHandler, . - DMA_CH3_IRQHandler + + .align 1 + .thumb_func + .weak DMA_CH4_IRQHandler + .type DMA_CH4_IRQHandler, %function +DMA_CH4_IRQHandler: + ldr r0,=DMA_CH4_DriverIRQHandler + bx r0 + .size DMA_CH4_IRQHandler, . - DMA_CH4_IRQHandler + + .align 1 + .thumb_func + .weak DMA_CH5_IRQHandler + .type DMA_CH5_IRQHandler, %function +DMA_CH5_IRQHandler: + ldr r0,=DMA_CH5_DriverIRQHandler + bx r0 + .size DMA_CH5_IRQHandler, . - DMA_CH5_IRQHandler + + .align 1 + .thumb_func + .weak DMA_CH6_IRQHandler + .type DMA_CH6_IRQHandler, %function +DMA_CH6_IRQHandler: + ldr r0,=DMA_CH6_DriverIRQHandler + bx r0 + .size DMA_CH6_IRQHandler, . - DMA_CH6_IRQHandler + + .align 1 + .thumb_func + .weak DMA_CH7_IRQHandler + .type DMA_CH7_IRQHandler, %function +DMA_CH7_IRQHandler: + ldr r0,=DMA_CH7_DriverIRQHandler + bx r0 + .size DMA_CH7_IRQHandler, . - DMA_CH7_IRQHandler + + .align 1 + .thumb_func + .weak ERM0_SINGLE_BIT_IRQHandler + .type ERM0_SINGLE_BIT_IRQHandler, %function +ERM0_SINGLE_BIT_IRQHandler: + ldr r0,=ERM0_SINGLE_BIT_DriverIRQHandler + bx r0 + .size ERM0_SINGLE_BIT_IRQHandler, . - ERM0_SINGLE_BIT_IRQHandler + + .align 1 + .thumb_func + .weak ERM0_MULTI_BIT_IRQHandler + .type ERM0_MULTI_BIT_IRQHandler, %function +ERM0_MULTI_BIT_IRQHandler: + ldr r0,=ERM0_MULTI_BIT_DriverIRQHandler + bx r0 + .size ERM0_MULTI_BIT_IRQHandler, . - ERM0_MULTI_BIT_IRQHandler + + .align 1 + .thumb_func + .weak FMU0_IRQHandler + .type FMU0_IRQHandler, %function +FMU0_IRQHandler: + ldr r0,=FMU0_DriverIRQHandler + bx r0 + .size FMU0_IRQHandler, . - FMU0_IRQHandler + + .align 1 + .thumb_func + .weak GLIKEY0_IRQHandler + .type GLIKEY0_IRQHandler, %function +GLIKEY0_IRQHandler: + ldr r0,=GLIKEY0_DriverIRQHandler + bx r0 + .size GLIKEY0_IRQHandler, . - GLIKEY0_IRQHandler + + .align 1 + .thumb_func + .weak MBC0_IRQHandler + .type MBC0_IRQHandler, %function +MBC0_IRQHandler: + ldr r0,=MBC0_DriverIRQHandler + bx r0 + .size MBC0_IRQHandler, . - MBC0_IRQHandler + + .align 1 + .thumb_func + .weak SCG0_IRQHandler + .type SCG0_IRQHandler, %function +SCG0_IRQHandler: + ldr r0,=SCG0_DriverIRQHandler + bx r0 + .size SCG0_IRQHandler, . - SCG0_IRQHandler + + .align 1 + .thumb_func + .weak SPC0_IRQHandler + .type SPC0_IRQHandler, %function +SPC0_IRQHandler: + ldr r0,=SPC0_DriverIRQHandler + bx r0 + .size SPC0_IRQHandler, . - SPC0_IRQHandler + + .align 1 + .thumb_func + .weak VBAT0_IRQHandler + .type VBAT0_IRQHandler, %function +VBAT0_IRQHandler: + ldr r0,=VBAT0_DriverIRQHandler + bx r0 + .size VBAT0_IRQHandler, . - VBAT0_IRQHandler + + .align 1 + .thumb_func + .weak WUU0_IRQHandler + .type WUU0_IRQHandler, %function +WUU0_IRQHandler: + ldr r0,=WUU0_DriverIRQHandler + bx r0 + .size WUU0_IRQHandler, . - WUU0_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_IRQHandler + .type CAN0_IRQHandler, %function +CAN0_IRQHandler: + ldr r0,=CAN0_DriverIRQHandler + bx r0 + .size CAN0_IRQHandler, . - CAN0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved36_IRQHandler + .type Reserved36_IRQHandler, %function +Reserved36_IRQHandler: + ldr r0,=Reserved36_DriverIRQHandler + bx r0 + .size Reserved36_IRQHandler, . - Reserved36_IRQHandler + + .align 1 + .thumb_func + .weak Reserved37_IRQHandler + .type Reserved37_IRQHandler, %function +Reserved37_IRQHandler: + ldr r0,=Reserved37_DriverIRQHandler + bx r0 + .size Reserved37_IRQHandler, . - Reserved37_IRQHandler + + .align 1 + .thumb_func + .weak Reserved38_IRQHandler + .type Reserved38_IRQHandler, %function +Reserved38_IRQHandler: + ldr r0,=Reserved38_DriverIRQHandler + bx r0 + .size Reserved38_IRQHandler, . - Reserved38_IRQHandler + + .align 1 + .thumb_func + .weak FLEXIO_IRQHandler + .type FLEXIO_IRQHandler, %function +FLEXIO_IRQHandler: + ldr r0,=FLEXIO_DriverIRQHandler + bx r0 + .size FLEXIO_IRQHandler, . - FLEXIO_IRQHandler + + .align 1 + .thumb_func + .weak I3C0_IRQHandler + .type I3C0_IRQHandler, %function +I3C0_IRQHandler: + ldr r0,=I3C0_DriverIRQHandler + bx r0 + .size I3C0_IRQHandler, . - I3C0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved41_IRQHandler + .type Reserved41_IRQHandler, %function +Reserved41_IRQHandler: + ldr r0,=Reserved41_DriverIRQHandler + bx r0 + .size Reserved41_IRQHandler, . - Reserved41_IRQHandler + + .align 1 + .thumb_func + .weak LPI2C0_IRQHandler + .type LPI2C0_IRQHandler, %function +LPI2C0_IRQHandler: + ldr r0,=LPI2C0_DriverIRQHandler + bx r0 + .size LPI2C0_IRQHandler, . - LPI2C0_IRQHandler + + .align 1 + .thumb_func + .weak LPI2C1_IRQHandler + .type LPI2C1_IRQHandler, %function +LPI2C1_IRQHandler: + ldr r0,=LPI2C1_DriverIRQHandler + bx r0 + .size LPI2C1_IRQHandler, . - LPI2C1_IRQHandler + + .align 1 + .thumb_func + .weak LPSPI0_IRQHandler + .type LPSPI0_IRQHandler, %function +LPSPI0_IRQHandler: + ldr r0,=LPSPI0_DriverIRQHandler + bx r0 + .size LPSPI0_IRQHandler, . - LPSPI0_IRQHandler + + .align 1 + .thumb_func + .weak LPSPI1_IRQHandler + .type LPSPI1_IRQHandler, %function +LPSPI1_IRQHandler: + ldr r0,=LPSPI1_DriverIRQHandler + bx r0 + .size LPSPI1_IRQHandler, . - LPSPI1_IRQHandler + + .align 1 + .thumb_func + .weak Reserved46_IRQHandler + .type Reserved46_IRQHandler, %function +Reserved46_IRQHandler: + ldr r0,=Reserved46_DriverIRQHandler + bx r0 + .size Reserved46_IRQHandler, . - Reserved46_IRQHandler + + .align 1 + .thumb_func + .weak LPUART0_IRQHandler + .type LPUART0_IRQHandler, %function +LPUART0_IRQHandler: + ldr r0,=LPUART0_DriverIRQHandler + bx r0 + .size LPUART0_IRQHandler, . - LPUART0_IRQHandler + + .align 1 + .thumb_func + .weak LPUART1_IRQHandler + .type LPUART1_IRQHandler, %function +LPUART1_IRQHandler: + ldr r0,=LPUART1_DriverIRQHandler + bx r0 + .size LPUART1_IRQHandler, . - LPUART1_IRQHandler + + .align 1 + .thumb_func + .weak LPUART2_IRQHandler + .type LPUART2_IRQHandler, %function +LPUART2_IRQHandler: + ldr r0,=LPUART2_DriverIRQHandler + bx r0 + .size LPUART2_IRQHandler, . - LPUART2_IRQHandler + + .align 1 + .thumb_func + .weak LPUART3_IRQHandler + .type LPUART3_IRQHandler, %function +LPUART3_IRQHandler: + ldr r0,=LPUART3_DriverIRQHandler + bx r0 + .size LPUART3_IRQHandler, . - LPUART3_IRQHandler + + .align 1 + .thumb_func + .weak LPUART4_IRQHandler + .type LPUART4_IRQHandler, %function +LPUART4_IRQHandler: + ldr r0,=LPUART4_DriverIRQHandler + bx r0 + .size LPUART4_IRQHandler, . - LPUART4_IRQHandler + + .align 1 + .thumb_func + .weak USB0_IRQHandler + .type USB0_IRQHandler, %function +USB0_IRQHandler: + ldr r0,=USB0_DriverIRQHandler + bx r0 + .size USB0_IRQHandler, . - USB0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved53_IRQHandler + .type Reserved53_IRQHandler, %function +Reserved53_IRQHandler: + ldr r0,=Reserved53_DriverIRQHandler + bx r0 + .size Reserved53_IRQHandler, . - Reserved53_IRQHandler + + .align 1 + .thumb_func + .weak CDOG0_IRQHandler + .type CDOG0_IRQHandler, %function +CDOG0_IRQHandler: + ldr r0,=CDOG0_DriverIRQHandler + bx r0 + .size CDOG0_IRQHandler, . - CDOG0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER0_IRQHandler + .type CTIMER0_IRQHandler, %function +CTIMER0_IRQHandler: + ldr r0,=CTIMER0_DriverIRQHandler + bx r0 + .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER1_IRQHandler + .type CTIMER1_IRQHandler, %function +CTIMER1_IRQHandler: + ldr r0,=CTIMER1_DriverIRQHandler + bx r0 + .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER2_IRQHandler + .type CTIMER2_IRQHandler, %function +CTIMER2_IRQHandler: + ldr r0,=CTIMER2_DriverIRQHandler + bx r0 + .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER3_IRQHandler + .type CTIMER3_IRQHandler, %function +CTIMER3_IRQHandler: + ldr r0,=CTIMER3_DriverIRQHandler + bx r0 + .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER4_IRQHandler + .type CTIMER4_IRQHandler, %function +CTIMER4_IRQHandler: + ldr r0,=CTIMER4_DriverIRQHandler + bx r0 + .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_RELOAD_ERROR_IRQHandler + .type FLEXPWM0_RELOAD_ERROR_IRQHandler, %function +FLEXPWM0_RELOAD_ERROR_IRQHandler: + ldr r0,=FLEXPWM0_RELOAD_ERROR_DriverIRQHandler + bx r0 + .size FLEXPWM0_RELOAD_ERROR_IRQHandler, . - FLEXPWM0_RELOAD_ERROR_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_FAULT_IRQHandler + .type FLEXPWM0_FAULT_IRQHandler, %function +FLEXPWM0_FAULT_IRQHandler: + ldr r0,=FLEXPWM0_FAULT_DriverIRQHandler + bx r0 + .size FLEXPWM0_FAULT_IRQHandler, . - FLEXPWM0_FAULT_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_SUBMODULE0_IRQHandler + .type FLEXPWM0_SUBMODULE0_IRQHandler, %function +FLEXPWM0_SUBMODULE0_IRQHandler: + ldr r0,=FLEXPWM0_SUBMODULE0_DriverIRQHandler + bx r0 + .size FLEXPWM0_SUBMODULE0_IRQHandler, . - FLEXPWM0_SUBMODULE0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_SUBMODULE1_IRQHandler + .type FLEXPWM0_SUBMODULE1_IRQHandler, %function +FLEXPWM0_SUBMODULE1_IRQHandler: + ldr r0,=FLEXPWM0_SUBMODULE1_DriverIRQHandler + bx r0 + .size FLEXPWM0_SUBMODULE1_IRQHandler, . - FLEXPWM0_SUBMODULE1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM0_SUBMODULE2_IRQHandler + .type FLEXPWM0_SUBMODULE2_IRQHandler, %function +FLEXPWM0_SUBMODULE2_IRQHandler: + ldr r0,=FLEXPWM0_SUBMODULE2_DriverIRQHandler + bx r0 + .size FLEXPWM0_SUBMODULE2_IRQHandler, . - FLEXPWM0_SUBMODULE2_IRQHandler + + .align 1 + .thumb_func + .weak Reserved65_IRQHandler + .type Reserved65_IRQHandler, %function +Reserved65_IRQHandler: + ldr r0,=Reserved65_DriverIRQHandler + bx r0 + .size Reserved65_IRQHandler, . - Reserved65_IRQHandler + + .align 1 + .thumb_func + .weak QDC0_COMPARE_IRQHandler + .type QDC0_COMPARE_IRQHandler, %function +QDC0_COMPARE_IRQHandler: + ldr r0,=QDC0_COMPARE_DriverIRQHandler + bx r0 + .size QDC0_COMPARE_IRQHandler, . - QDC0_COMPARE_IRQHandler + + .align 1 + .thumb_func + .weak QDC0_HOME_IRQHandler + .type QDC0_HOME_IRQHandler, %function +QDC0_HOME_IRQHandler: + ldr r0,=QDC0_HOME_DriverIRQHandler + bx r0 + .size QDC0_HOME_IRQHandler, . - QDC0_HOME_IRQHandler + + .align 1 + .thumb_func + .weak QDC0_WATCHDOG_IRQHandler + .type QDC0_WATCHDOG_IRQHandler, %function +QDC0_WATCHDOG_IRQHandler: + ldr r0,=QDC0_WATCHDOG_DriverIRQHandler + bx r0 + .size QDC0_WATCHDOG_IRQHandler, . - QDC0_WATCHDOG_IRQHandler + + .align 1 + .thumb_func + .weak QDC0_INDEX_IRQHandler + .type QDC0_INDEX_IRQHandler, %function +QDC0_INDEX_IRQHandler: + ldr r0,=QDC0_INDEX_DriverIRQHandler + bx r0 + .size QDC0_INDEX_IRQHandler, . - QDC0_INDEX_IRQHandler + + .align 1 + .thumb_func + .weak FREQME0_IRQHandler + .type FREQME0_IRQHandler, %function +FREQME0_IRQHandler: + ldr r0,=FREQME0_DriverIRQHandler + bx r0 + .size FREQME0_IRQHandler, . - FREQME0_IRQHandler + + .align 1 + .thumb_func + .weak LPTMR0_IRQHandler + .type LPTMR0_IRQHandler, %function +LPTMR0_IRQHandler: + ldr r0,=LPTMR0_DriverIRQHandler + bx r0 + .size LPTMR0_IRQHandler, . - LPTMR0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved72_IRQHandler + .type Reserved72_IRQHandler, %function +Reserved72_IRQHandler: + ldr r0,=Reserved72_DriverIRQHandler + bx r0 + .size Reserved72_IRQHandler, . - Reserved72_IRQHandler + + .align 1 + .thumb_func + .weak OS_EVENT_IRQHandler + .type OS_EVENT_IRQHandler, %function +OS_EVENT_IRQHandler: + ldr r0,=OS_EVENT_DriverIRQHandler + bx r0 + .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler + + .align 1 + .thumb_func + .weak WAKETIMER0_IRQHandler + .type WAKETIMER0_IRQHandler, %function +WAKETIMER0_IRQHandler: + ldr r0,=WAKETIMER0_DriverIRQHandler + bx r0 + .size WAKETIMER0_IRQHandler, . - WAKETIMER0_IRQHandler + + .align 1 + .thumb_func + .weak UTICK0_IRQHandler + .type UTICK0_IRQHandler, %function +UTICK0_IRQHandler: + ldr r0,=UTICK0_DriverIRQHandler + bx r0 + .size UTICK0_IRQHandler, . - UTICK0_IRQHandler + + .align 1 + .thumb_func + .weak WWDT0_IRQHandler + .type WWDT0_IRQHandler, %function +WWDT0_IRQHandler: + ldr r0,=WWDT0_DriverIRQHandler + bx r0 + .size WWDT0_IRQHandler, . - WWDT0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved77_IRQHandler + .type Reserved77_IRQHandler, %function +Reserved77_IRQHandler: + ldr r0,=Reserved77_DriverIRQHandler + bx r0 + .size Reserved77_IRQHandler, . - Reserved77_IRQHandler + + .align 1 + .thumb_func + .weak ADC0_IRQHandler + .type ADC0_IRQHandler, %function +ADC0_IRQHandler: + ldr r0,=ADC0_DriverIRQHandler + bx r0 + .size ADC0_IRQHandler, . - ADC0_IRQHandler + + .align 1 + .thumb_func + .weak ADC1_IRQHandler + .type ADC1_IRQHandler, %function +ADC1_IRQHandler: + ldr r0,=ADC1_DriverIRQHandler + bx r0 + .size ADC1_IRQHandler, . - ADC1_IRQHandler + + .align 1 + .thumb_func + .weak CMP0_IRQHandler + .type CMP0_IRQHandler, %function +CMP0_IRQHandler: + ldr r0,=CMP0_DriverIRQHandler + bx r0 + .size CMP0_IRQHandler, . - CMP0_IRQHandler + + .align 1 + .thumb_func + .weak CMP1_IRQHandler + .type CMP1_IRQHandler, %function +CMP1_IRQHandler: + ldr r0,=CMP1_DriverIRQHandler + bx r0 + .size CMP1_IRQHandler, . - CMP1_IRQHandler + + .align 1 + .thumb_func + .weak Reserved82_IRQHandler + .type Reserved82_IRQHandler, %function +Reserved82_IRQHandler: + ldr r0,=Reserved82_DriverIRQHandler + bx r0 + .size Reserved82_IRQHandler, . - Reserved82_IRQHandler + + .align 1 + .thumb_func + .weak DAC0_IRQHandler + .type DAC0_IRQHandler, %function +DAC0_IRQHandler: + ldr r0,=DAC0_DriverIRQHandler + bx r0 + .size DAC0_IRQHandler, . - DAC0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved84_IRQHandler + .type Reserved84_IRQHandler, %function +Reserved84_IRQHandler: + ldr r0,=Reserved84_DriverIRQHandler + bx r0 + .size Reserved84_IRQHandler, . - Reserved84_IRQHandler + + .align 1 + .thumb_func + .weak Reserved85_IRQHandler + .type Reserved85_IRQHandler, %function +Reserved85_IRQHandler: + ldr r0,=Reserved85_DriverIRQHandler + bx r0 + .size Reserved85_IRQHandler, . - Reserved85_IRQHandler + + .align 1 + .thumb_func + .weak Reserved86_IRQHandler + .type Reserved86_IRQHandler, %function +Reserved86_IRQHandler: + ldr r0,=Reserved86_DriverIRQHandler + bx r0 + .size Reserved86_IRQHandler, . - Reserved86_IRQHandler + + .align 1 + .thumb_func + .weak GPIO0_IRQHandler + .type GPIO0_IRQHandler, %function +GPIO0_IRQHandler: + ldr r0,=GPIO0_DriverIRQHandler + bx r0 + .size GPIO0_IRQHandler, . - GPIO0_IRQHandler + + .align 1 + .thumb_func + .weak GPIO1_IRQHandler + .type GPIO1_IRQHandler, %function +GPIO1_IRQHandler: + ldr r0,=GPIO1_DriverIRQHandler + bx r0 + .size GPIO1_IRQHandler, . - GPIO1_IRQHandler + + .align 1 + .thumb_func + .weak GPIO2_IRQHandler + .type GPIO2_IRQHandler, %function +GPIO2_IRQHandler: + ldr r0,=GPIO2_DriverIRQHandler + bx r0 + .size GPIO2_IRQHandler, . - GPIO2_IRQHandler + + .align 1 + .thumb_func + .weak GPIO3_IRQHandler + .type GPIO3_IRQHandler, %function +GPIO3_IRQHandler: + ldr r0,=GPIO3_DriverIRQHandler + bx r0 + .size GPIO3_IRQHandler, . - GPIO3_IRQHandler + + .align 1 + .thumb_func + .weak GPIO4_IRQHandler + .type GPIO4_IRQHandler, %function +GPIO4_IRQHandler: + ldr r0,=GPIO4_DriverIRQHandler + bx r0 + .size GPIO4_IRQHandler, . - GPIO4_IRQHandler + + .align 1 + .thumb_func + .weak Reserved92_IRQHandler + .type Reserved92_IRQHandler, %function +Reserved92_IRQHandler: + ldr r0,=Reserved92_DriverIRQHandler + bx r0 + .size Reserved92_IRQHandler, . - Reserved92_IRQHandler + + .align 1 + .thumb_func + .weak LPI2C2_IRQHandler + .type LPI2C2_IRQHandler, %function +LPI2C2_IRQHandler: + ldr r0,=LPI2C2_DriverIRQHandler + bx r0 + .size LPI2C2_IRQHandler, . - LPI2C2_IRQHandler + + .align 1 + .thumb_func + .weak LPI2C3_IRQHandler + .type LPI2C3_IRQHandler, %function +LPI2C3_IRQHandler: + ldr r0,=LPI2C3_DriverIRQHandler + bx r0 + .size LPI2C3_IRQHandler, . - LPI2C3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_RELOAD_ERROR_IRQHandler + .type FLEXPWM1_RELOAD_ERROR_IRQHandler, %function +FLEXPWM1_RELOAD_ERROR_IRQHandler: + ldr r0,=FLEXPWM1_RELOAD_ERROR_DriverIRQHandler + bx r0 + .size FLEXPWM1_RELOAD_ERROR_IRQHandler, . - FLEXPWM1_RELOAD_ERROR_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_FAULT_IRQHandler + .type FLEXPWM1_FAULT_IRQHandler, %function +FLEXPWM1_FAULT_IRQHandler: + ldr r0,=FLEXPWM1_FAULT_DriverIRQHandler + bx r0 + .size FLEXPWM1_FAULT_IRQHandler, . - FLEXPWM1_FAULT_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_SUBMODULE0_IRQHandler + .type FLEXPWM1_SUBMODULE0_IRQHandler, %function +FLEXPWM1_SUBMODULE0_IRQHandler: + ldr r0,=FLEXPWM1_SUBMODULE0_DriverIRQHandler + bx r0 + .size FLEXPWM1_SUBMODULE0_IRQHandler, . - FLEXPWM1_SUBMODULE0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_SUBMODULE1_IRQHandler + .type FLEXPWM1_SUBMODULE1_IRQHandler, %function +FLEXPWM1_SUBMODULE1_IRQHandler: + ldr r0,=FLEXPWM1_SUBMODULE1_DriverIRQHandler + bx r0 + .size FLEXPWM1_SUBMODULE1_IRQHandler, . - FLEXPWM1_SUBMODULE1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXPWM1_SUBMODULE2_IRQHandler + .type FLEXPWM1_SUBMODULE2_IRQHandler, %function +FLEXPWM1_SUBMODULE2_IRQHandler: + ldr r0,=FLEXPWM1_SUBMODULE2_DriverIRQHandler + bx r0 + .size FLEXPWM1_SUBMODULE2_IRQHandler, . - FLEXPWM1_SUBMODULE2_IRQHandler + + .align 1 + .thumb_func + .weak Reserved100_IRQHandler + .type Reserved100_IRQHandler, %function +Reserved100_IRQHandler: + ldr r0,=Reserved100_DriverIRQHandler + bx r0 + .size Reserved100_IRQHandler, . - Reserved100_IRQHandler + + .align 1 + .thumb_func + .weak QDC1_COMPARE_IRQHandler + .type QDC1_COMPARE_IRQHandler, %function +QDC1_COMPARE_IRQHandler: + ldr r0,=QDC1_COMPARE_DriverIRQHandler + bx r0 + .size QDC1_COMPARE_IRQHandler, . - QDC1_COMPARE_IRQHandler + + .align 1 + .thumb_func + .weak QDC1_HOME_IRQHandler + .type QDC1_HOME_IRQHandler, %function +QDC1_HOME_IRQHandler: + ldr r0,=QDC1_HOME_DriverIRQHandler + bx r0 + .size QDC1_HOME_IRQHandler, . - QDC1_HOME_IRQHandler + + .align 1 + .thumb_func + .weak QDC1_WATCHDOG_IRQHandler + .type QDC1_WATCHDOG_IRQHandler, %function +QDC1_WATCHDOG_IRQHandler: + ldr r0,=QDC1_WATCHDOG_DriverIRQHandler + bx r0 + .size QDC1_WATCHDOG_IRQHandler, . - QDC1_WATCHDOG_IRQHandler + + .align 1 + .thumb_func + .weak QDC1_INDEX_IRQHandler + .type QDC1_INDEX_IRQHandler, %function +QDC1_INDEX_IRQHandler: + ldr r0,=QDC1_INDEX_DriverIRQHandler + bx r0 + .size QDC1_INDEX_IRQHandler, . - QDC1_INDEX_IRQHandler + + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm +/* Exception Handlers */ + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SecureFault_Handler + def_irq_handler DebugMon_Handler + def_irq_handler Reserved16_DriverIRQHandler + def_irq_handler CMC_DriverIRQHandler + def_irq_handler DMA_CH0_DriverIRQHandler + def_irq_handler DMA_CH1_DriverIRQHandler + def_irq_handler DMA_CH2_DriverIRQHandler + def_irq_handler DMA_CH3_DriverIRQHandler + def_irq_handler DMA_CH4_DriverIRQHandler + def_irq_handler DMA_CH5_DriverIRQHandler + def_irq_handler DMA_CH6_DriverIRQHandler + def_irq_handler DMA_CH7_DriverIRQHandler + def_irq_handler ERM0_SINGLE_BIT_DriverIRQHandler + def_irq_handler ERM0_MULTI_BIT_DriverIRQHandler + def_irq_handler FMU0_DriverIRQHandler + def_irq_handler GLIKEY0_DriverIRQHandler + def_irq_handler MBC0_DriverIRQHandler + def_irq_handler SCG0_DriverIRQHandler + def_irq_handler SPC0_DriverIRQHandler + def_irq_handler VBAT0_DriverIRQHandler + def_irq_handler WUU0_DriverIRQHandler + def_irq_handler CAN0_DriverIRQHandler + def_irq_handler Reserved36_DriverIRQHandler + def_irq_handler Reserved37_DriverIRQHandler + def_irq_handler Reserved38_DriverIRQHandler + def_irq_handler FLEXIO_DriverIRQHandler + def_irq_handler I3C0_DriverIRQHandler + def_irq_handler Reserved41_DriverIRQHandler + def_irq_handler LPI2C0_DriverIRQHandler + def_irq_handler LPI2C1_DriverIRQHandler + def_irq_handler LPSPI0_DriverIRQHandler + def_irq_handler LPSPI1_DriverIRQHandler + def_irq_handler Reserved46_DriverIRQHandler + def_irq_handler LPUART0_DriverIRQHandler + def_irq_handler LPUART1_DriverIRQHandler + def_irq_handler LPUART2_DriverIRQHandler + def_irq_handler LPUART3_DriverIRQHandler + def_irq_handler LPUART4_DriverIRQHandler + def_irq_handler USB0_DriverIRQHandler + def_irq_handler Reserved53_DriverIRQHandler + def_irq_handler CDOG0_DriverIRQHandler + def_irq_handler CTIMER0_DriverIRQHandler + def_irq_handler CTIMER1_DriverIRQHandler + def_irq_handler CTIMER2_DriverIRQHandler + def_irq_handler CTIMER3_DriverIRQHandler + def_irq_handler CTIMER4_DriverIRQHandler + def_irq_handler FLEXPWM0_RELOAD_ERROR_DriverIRQHandler + def_irq_handler FLEXPWM0_FAULT_DriverIRQHandler + def_irq_handler FLEXPWM0_SUBMODULE0_DriverIRQHandler + def_irq_handler FLEXPWM0_SUBMODULE1_DriverIRQHandler + def_irq_handler FLEXPWM0_SUBMODULE2_DriverIRQHandler + def_irq_handler Reserved65_DriverIRQHandler + def_irq_handler QDC0_COMPARE_DriverIRQHandler + def_irq_handler QDC0_HOME_DriverIRQHandler + def_irq_handler QDC0_WATCHDOG_DriverIRQHandler + def_irq_handler QDC0_INDEX_DriverIRQHandler + def_irq_handler FREQME0_DriverIRQHandler + def_irq_handler LPTMR0_DriverIRQHandler + def_irq_handler Reserved72_DriverIRQHandler + def_irq_handler OS_EVENT_DriverIRQHandler + def_irq_handler WAKETIMER0_DriverIRQHandler + def_irq_handler UTICK0_DriverIRQHandler + def_irq_handler WWDT0_DriverIRQHandler + def_irq_handler Reserved77_DriverIRQHandler + def_irq_handler ADC0_DriverIRQHandler + def_irq_handler ADC1_DriverIRQHandler + def_irq_handler CMP0_DriverIRQHandler + def_irq_handler CMP1_DriverIRQHandler + def_irq_handler Reserved82_DriverIRQHandler + def_irq_handler DAC0_DriverIRQHandler + def_irq_handler Reserved84_DriverIRQHandler + def_irq_handler Reserved85_DriverIRQHandler + def_irq_handler Reserved86_DriverIRQHandler + def_irq_handler GPIO0_DriverIRQHandler + def_irq_handler GPIO1_DriverIRQHandler + def_irq_handler GPIO2_DriverIRQHandler + def_irq_handler GPIO3_DriverIRQHandler + def_irq_handler GPIO4_DriverIRQHandler + def_irq_handler Reserved92_DriverIRQHandler + def_irq_handler LPI2C2_DriverIRQHandler + def_irq_handler LPI2C3_DriverIRQHandler + def_irq_handler FLEXPWM1_RELOAD_ERROR_DriverIRQHandler + def_irq_handler FLEXPWM1_FAULT_DriverIRQHandler + def_irq_handler FLEXPWM1_SUBMODULE0_DriverIRQHandler + def_irq_handler FLEXPWM1_SUBMODULE1_DriverIRQHandler + def_irq_handler FLEXPWM1_SUBMODULE2_DriverIRQHandler + def_irq_handler Reserved100_DriverIRQHandler + def_irq_handler QDC1_COMPARE_DriverIRQHandler + def_irq_handler QDC1_HOME_DriverIRQHandler + def_irq_handler QDC1_WATCHDOG_DriverIRQHandler + def_irq_handler QDC1_INDEX_DriverIRQHandler + + .end diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/iar/MCXA156_flash.icf b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/iar/MCXA156_flash.icf new file mode 100644 index 00000000000..028999f4904 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/iar/MCXA156_flash.icf @@ -0,0 +1,84 @@ +/* +** ################################################################### +** Processors: MCXA156VLL +** MCXA156VMP +** MCXA156VPJ +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: MCXA18 User manual +** Version: rev. 1.0, 2022-03-29 +** Build: b240104 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* Stack and Heap Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000001FF; + +define symbol m_text_start = 0x00000200; +define symbol m_text_end = 0x000FFFFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2001DFFF; + +define symbol m_sramx0_start = 0x04000000; +define symbol m_sramx0_end = 0x04001FFF; + +define memory mem with size = 4G; + +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__] + | mem:[from m_sramx0_start to m_sramx0_end]; + +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; +} + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; + + diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/iar/MCXA156_ram.icf b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/iar/MCXA156_ram.icf new file mode 100644 index 00000000000..a1b3e4274b1 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/iar/MCXA156_ram.icf @@ -0,0 +1,80 @@ +/* +** ################################################################### +** Processors: MCXA156VLL +** MCXA156VMP +** MCXA156VPJ +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: MCXA18 User manual +** Version: rev. 1.0, 2022-03-29 +** Build: b240104 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* Stack and Heap Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define symbol m_interrupts_start = 0x20000000; +define symbol m_interrupts_end = 0x200001FF; + +define symbol m_text_start = 0x20000200; +define symbol m_text_end = 0x20005FFF; + +define symbol m_data_start = 0x20006000; +define symbol m_data_end = 0x2001DFFF; + +define memory mem with size = 4G; + +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__]; + +define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; +if (isdefinedsymbol(__use_shmem__)) { + define region rpmsg_sh_mem_region = mem:[from rpmsg_sh_mem_start to rpmsg_sh_mem_end]; +} + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; + + diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/iar/startup_MCXA156.s b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/iar/startup_MCXA156.s new file mode 100644 index 00000000000..00d2bccea5a --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/iar/startup_MCXA156.s @@ -0,0 +1,953 @@ +; ------------------------------------------------------------------------- +; @file: startup_MCXA156.s +; @purpose: CMSIS Cortex-M33 Core Device Startup File +; MCXA156 +; @version: 1.0 +; @date: 2022-3-29 +; @build: b231107 +; ------------------------------------------------------------------------- +; +; Copyright 1997-2016 Freescale Semiconductor, Inc. +; Copyright 2016-2023 NXP +; SPDX-License-Identifier: BSD-3-Clause +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__iar_init$$done: ; The vector table is not needed + ; until after copy initialization is done + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler +__vector_table_0x1c + DCD SecureFault_Handler ;Secure Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD Reserved16_IRQHandler ;OR IRQ1 to IRQ53 + DCD CMC_IRQHandler ;Core Mode Controller interrupt + DCD DMA_CH0_IRQHandler ;DMA3_0_CH0 error or transfer complete + DCD DMA_CH1_IRQHandler ;DMA3_0_CH1 error or transfer complete + DCD DMA_CH2_IRQHandler ;DMA3_0_CH2 error or transfer complete + DCD DMA_CH3_IRQHandler ;DMA3_0_CH3 error or transfer complete + DCD DMA_CH4_IRQHandler ;DMA3_0_CH4 error or transfer complete + DCD DMA_CH5_IRQHandler ;DMA3_0_CH5 error or transfer complete + DCD DMA_CH6_IRQHandler ;DMA3_0_CH6 error or transfer complete + DCD DMA_CH7_IRQHandler ;DMA3_0_CH7 error or transfer complete + DCD ERM0_SINGLE_BIT_IRQHandler ;ERM Single Bit error interrupt + DCD ERM0_MULTI_BIT_IRQHandler ;ERM Multi Bit error interrupt + DCD FMU0_IRQHandler ;Flash Management Unit interrupt + DCD GLIKEY0_IRQHandler ;GLIKEY Interrupt + DCD MBC0_IRQHandler ;MBC secure violation interrupt + DCD SCG0_IRQHandler ;System Clock Generator interrupt + DCD SPC0_IRQHandler ;System Power Controller interrupt + DCD VBAT0_IRQHandler ;VBAT interrupt + DCD WUU0_IRQHandler ;Wake Up Unit interrupt + DCD CAN0_IRQHandler ;Controller Area Network 0 interrupt + DCD Reserved36_IRQHandler ;Reserved interrupt + DCD Reserved37_IRQHandler ;Reserved interrupt + DCD Reserved38_IRQHandler ;Reserved interrupt + DCD FLEXIO_IRQHandler ;Flexible Input/Output interrupt + DCD I3C0_IRQHandler ;Improved Inter Integrated Circuit interrupt 0 + DCD Reserved41_IRQHandler ;Reserved interrupt + DCD LPI2C0_IRQHandler ;Low-Power Inter Integrated Circuit interrupt + DCD LPI2C1_IRQHandler ;Low-Power Inter Integrated Circuit interrupt + DCD LPSPI0_IRQHandler ;Low-Power Serial Peripheral Interface interrupt + DCD LPSPI1_IRQHandler ;Low-Power Serial Peripheral Interface interrupt + DCD Reserved46_IRQHandler ;Reserved interrupt + DCD LPUART0_IRQHandler ;Low-Power Universal Asynchronous Receive/Transmit interrupt + DCD LPUART1_IRQHandler ;Low-Power Universal Asynchronous Receive/Transmit interrupt + DCD LPUART2_IRQHandler ;Low-Power Universal Asynchronous Receive/Transmit interrupt + DCD LPUART3_IRQHandler ;Low-Power Universal Asynchronous Receive/Transmit interrupt + DCD LPUART4_IRQHandler ;Low-Power Universal Asynchronous Receive/Transmit interrupt + DCD USB0_IRQHandler ;Universal Serial Bus - Full Speed interrupt + DCD Reserved53_IRQHandler ;Reserved interrupt + DCD CDOG0_IRQHandler ;Code Watchdog Timer 0 interrupt + DCD CTIMER0_IRQHandler ;Standard counter/timer 0 interrupt + DCD CTIMER1_IRQHandler ;Standard counter/timer 1 interrupt + DCD CTIMER2_IRQHandler ;Standard counter/timer 2 interrupt + DCD CTIMER3_IRQHandler ;Standard counter/timer 3 interrupt + DCD CTIMER4_IRQHandler ;Standard counter/timer 4 interrupt + DCD FLEXPWM0_RELOAD_ERROR_IRQHandler ;FlexPWM0_reload_error interrupt + DCD FLEXPWM0_FAULT_IRQHandler ;FlexPWM0_fault interrupt + DCD FLEXPWM0_SUBMODULE0_IRQHandler ;FlexPWM0 Submodule 0 capture/compare/reload interrupt + DCD FLEXPWM0_SUBMODULE1_IRQHandler ;FlexPWM0 Submodule 1 capture/compare/reload interrupt + DCD FLEXPWM0_SUBMODULE2_IRQHandler ;FlexPWM0 Submodule 2 capture/compare/reload interrupt + DCD Reserved65_IRQHandler ;Reserved interrupt + DCD QDC0_COMPARE_IRQHandler ;Compare + DCD QDC0_HOME_IRQHandler ;Home + DCD QDC0_WATCHDOG_IRQHandler ;Watchdog / Simultaneous A and B Change + DCD QDC0_INDEX_IRQHandler ;Index / Roll Over / Roll Under + DCD FREQME0_IRQHandler ;Frequency Measurement interrupt + DCD LPTMR0_IRQHandler ;Low Power Timer 0 interrupt + DCD Reserved72_IRQHandler ;Reserved interrupt + DCD OS_EVENT_IRQHandler ;OS event timer interrupt + DCD WAKETIMER0_IRQHandler ;Wake Timer Interrupt + DCD UTICK0_IRQHandler ;Micro-Tick Timer interrupt + DCD WWDT0_IRQHandler ;Windowed Watchdog Timer 0 interrupt + DCD Reserved77_IRQHandler ;Reserved interrupt + DCD ADC0_IRQHandler ;Analog-to-Digital Converter interrupt + DCD ADC1_IRQHandler ;Analog-to-Digital Converter interrupt + DCD CMP0_IRQHandler ;Comparator interrupt + DCD CMP1_IRQHandler ;Comparator interrupt + DCD Reserved82_IRQHandler ;Reserved interrupt + DCD DAC0_IRQHandler ;Digital-to-Analog Converter 0 - General Purpose interrupt + DCD Reserved84_IRQHandler ;Reserved interrupt + DCD Reserved85_IRQHandler ;Reserved interrupt + DCD Reserved86_IRQHandler ;Reserved interrupt + DCD GPIO0_IRQHandler ;General Purpose Input/Output interrupt 0 + DCD GPIO1_IRQHandler ;General Purpose Input/Output interrupt 1 + DCD GPIO2_IRQHandler ;General Purpose Input/Output interrupt 2 + DCD GPIO3_IRQHandler ;General Purpose Input/Output interrupt 3 + DCD GPIO4_IRQHandler ;General Purpose Input/Output interrupt 4 + DCD Reserved92_IRQHandler ;Reserved interrupt + DCD LPI2C2_IRQHandler ;Low-Power Inter Integrated Circuit interrupt + DCD LPI2C3_IRQHandler ;Low-Power Inter Integrated Circuit interrupt + DCD FLEXPWM1_RELOAD_ERROR_IRQHandler ;FlexPWM1_reload_error interrupt + DCD FLEXPWM1_FAULT_IRQHandler ;FlexPWM1_fault interrupt + DCD FLEXPWM1_SUBMODULE0_IRQHandler ;FlexPWM1 Submodule 0 capture/compare/reload interrupt + DCD FLEXPWM1_SUBMODULE1_IRQHandler ;FlexPWM1 Submodule 1 capture/compare/reload interrupt + DCD FLEXPWM1_SUBMODULE2_IRQHandler ;FlexPWM1 Submodule 2 capture/compare/reload interrupt + DCD Reserved100_IRQHandler ;Reserved interrupt + DCD QDC1_COMPARE_IRQHandler ;Compare + DCD QDC1_HOME_IRQHandler ;Home + DCD QDC1_WATCHDOG_IRQHandler ;Watchdog / Simultaneous A and B Change + DCD QDC1_INDEX_IRQHandler ;Index / Roll Over / Roll Under +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__vector_table + STR R1, [R0] + LDR R2, [R1] + MSR MSP, R2 + LDR R0, =sfb(CSTACK) + MSR MSPLIM, R0 + CPSIE I ; Unmask interrupts + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SecureFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SecureFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK Reserved16_IRQHandler + PUBWEAK Reserved16_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved16_IRQHandler + LDR R0, =Reserved16_DriverIRQHandler + BX R0 + + PUBWEAK CMC_IRQHandler + PUBWEAK CMC_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CMC_IRQHandler + LDR R0, =CMC_DriverIRQHandler + BX R0 + + PUBWEAK DMA_CH0_IRQHandler + PUBWEAK DMA_CH0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA_CH0_IRQHandler + LDR R0, =DMA_CH0_DriverIRQHandler + BX R0 + + PUBWEAK DMA_CH1_IRQHandler + PUBWEAK DMA_CH1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA_CH1_IRQHandler + LDR R0, =DMA_CH1_DriverIRQHandler + BX R0 + + PUBWEAK DMA_CH2_IRQHandler + PUBWEAK DMA_CH2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA_CH2_IRQHandler + LDR R0, =DMA_CH2_DriverIRQHandler + BX R0 + + PUBWEAK DMA_CH3_IRQHandler + PUBWEAK DMA_CH3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA_CH3_IRQHandler + LDR R0, =DMA_CH3_DriverIRQHandler + BX R0 + + PUBWEAK DMA_CH4_IRQHandler + PUBWEAK DMA_CH4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA_CH4_IRQHandler + LDR R0, =DMA_CH4_DriverIRQHandler + BX R0 + + PUBWEAK DMA_CH5_IRQHandler + PUBWEAK DMA_CH5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA_CH5_IRQHandler + LDR R0, =DMA_CH5_DriverIRQHandler + BX R0 + + PUBWEAK DMA_CH6_IRQHandler + PUBWEAK DMA_CH6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA_CH6_IRQHandler + LDR R0, =DMA_CH6_DriverIRQHandler + BX R0 + + PUBWEAK DMA_CH7_IRQHandler + PUBWEAK DMA_CH7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA_CH7_IRQHandler + LDR R0, =DMA_CH7_DriverIRQHandler + BX R0 + + PUBWEAK ERM0_SINGLE_BIT_IRQHandler + PUBWEAK ERM0_SINGLE_BIT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ERM0_SINGLE_BIT_IRQHandler + LDR R0, =ERM0_SINGLE_BIT_DriverIRQHandler + BX R0 + + PUBWEAK ERM0_MULTI_BIT_IRQHandler + PUBWEAK ERM0_MULTI_BIT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ERM0_MULTI_BIT_IRQHandler + LDR R0, =ERM0_MULTI_BIT_DriverIRQHandler + BX R0 + + PUBWEAK FMU0_IRQHandler + PUBWEAK FMU0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FMU0_IRQHandler + LDR R0, =FMU0_DriverIRQHandler + BX R0 + + PUBWEAK GLIKEY0_IRQHandler + PUBWEAK GLIKEY0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GLIKEY0_IRQHandler + LDR R0, =GLIKEY0_DriverIRQHandler + BX R0 + + PUBWEAK MBC0_IRQHandler + PUBWEAK MBC0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +MBC0_IRQHandler + LDR R0, =MBC0_DriverIRQHandler + BX R0 + + PUBWEAK SCG0_IRQHandler + PUBWEAK SCG0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SCG0_IRQHandler + LDR R0, =SCG0_DriverIRQHandler + BX R0 + + PUBWEAK SPC0_IRQHandler + PUBWEAK SPC0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPC0_IRQHandler + LDR R0, =SPC0_DriverIRQHandler + BX R0 + + PUBWEAK VBAT0_IRQHandler + PUBWEAK VBAT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +VBAT0_IRQHandler + LDR R0, =VBAT0_DriverIRQHandler + BX R0 + + PUBWEAK WUU0_IRQHandler + PUBWEAK WUU0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +WUU0_IRQHandler + LDR R0, =WUU0_DriverIRQHandler + BX R0 + + PUBWEAK CAN0_IRQHandler + PUBWEAK CAN0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_IRQHandler + LDR R0, =CAN0_DriverIRQHandler + BX R0 + + PUBWEAK Reserved36_IRQHandler + PUBWEAK Reserved36_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved36_IRQHandler + LDR R0, =Reserved36_DriverIRQHandler + BX R0 + + PUBWEAK Reserved37_IRQHandler + PUBWEAK Reserved37_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved37_IRQHandler + LDR R0, =Reserved37_DriverIRQHandler + BX R0 + + PUBWEAK Reserved38_IRQHandler + PUBWEAK Reserved38_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved38_IRQHandler + LDR R0, =Reserved38_DriverIRQHandler + BX R0 + + PUBWEAK FLEXIO_IRQHandler + PUBWEAK FLEXIO_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXIO_IRQHandler + LDR R0, =FLEXIO_DriverIRQHandler + BX R0 + + PUBWEAK I3C0_IRQHandler + PUBWEAK I3C0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I3C0_IRQHandler + LDR R0, =I3C0_DriverIRQHandler + BX R0 + + PUBWEAK Reserved41_IRQHandler + PUBWEAK Reserved41_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved41_IRQHandler + LDR R0, =Reserved41_DriverIRQHandler + BX R0 + + PUBWEAK LPI2C0_IRQHandler + PUBWEAK LPI2C0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPI2C0_IRQHandler + LDR R0, =LPI2C0_DriverIRQHandler + BX R0 + + PUBWEAK LPI2C1_IRQHandler + PUBWEAK LPI2C1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPI2C1_IRQHandler + LDR R0, =LPI2C1_DriverIRQHandler + BX R0 + + PUBWEAK LPSPI0_IRQHandler + PUBWEAK LPSPI0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPSPI0_IRQHandler + LDR R0, =LPSPI0_DriverIRQHandler + BX R0 + + PUBWEAK LPSPI1_IRQHandler + PUBWEAK LPSPI1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPSPI1_IRQHandler + LDR R0, =LPSPI1_DriverIRQHandler + BX R0 + + PUBWEAK Reserved46_IRQHandler + PUBWEAK Reserved46_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved46_IRQHandler + LDR R0, =Reserved46_DriverIRQHandler + BX R0 + + PUBWEAK LPUART0_IRQHandler + PUBWEAK LPUART0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART0_IRQHandler + LDR R0, =LPUART0_DriverIRQHandler + BX R0 + + PUBWEAK LPUART1_IRQHandler + PUBWEAK LPUART1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART1_IRQHandler + LDR R0, =LPUART1_DriverIRQHandler + BX R0 + + PUBWEAK LPUART2_IRQHandler + PUBWEAK LPUART2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART2_IRQHandler + LDR R0, =LPUART2_DriverIRQHandler + BX R0 + + PUBWEAK LPUART3_IRQHandler + PUBWEAK LPUART3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART3_IRQHandler + LDR R0, =LPUART3_DriverIRQHandler + BX R0 + + PUBWEAK LPUART4_IRQHandler + PUBWEAK LPUART4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART4_IRQHandler + LDR R0, =LPUART4_DriverIRQHandler + BX R0 + + PUBWEAK USB0_IRQHandler + PUBWEAK USB0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_IRQHandler + LDR R0, =USB0_DriverIRQHandler + BX R0 + + PUBWEAK Reserved53_IRQHandler + PUBWEAK Reserved53_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved53_IRQHandler + LDR R0, =Reserved53_DriverIRQHandler + BX R0 + + PUBWEAK CDOG0_IRQHandler + PUBWEAK CDOG0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CDOG0_IRQHandler + LDR R0, =CDOG0_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER0_IRQHandler + PUBWEAK CTIMER0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER0_IRQHandler + LDR R0, =CTIMER0_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER1_IRQHandler + PUBWEAK CTIMER1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER1_IRQHandler + LDR R0, =CTIMER1_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER2_IRQHandler + PUBWEAK CTIMER2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER2_IRQHandler + LDR R0, =CTIMER2_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER3_IRQHandler + PUBWEAK CTIMER3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER3_IRQHandler + LDR R0, =CTIMER3_DriverIRQHandler + BX R0 + + PUBWEAK CTIMER4_IRQHandler + PUBWEAK CTIMER4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER4_IRQHandler + LDR R0, =CTIMER4_DriverIRQHandler + BX R0 + + PUBWEAK FLEXPWM0_RELOAD_ERROR_IRQHandler + PUBWEAK FLEXPWM0_RELOAD_ERROR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM0_RELOAD_ERROR_IRQHandler + LDR R0, =FLEXPWM0_RELOAD_ERROR_DriverIRQHandler + BX R0 + + PUBWEAK FLEXPWM0_FAULT_IRQHandler + PUBWEAK FLEXPWM0_FAULT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM0_FAULT_IRQHandler + LDR R0, =FLEXPWM0_FAULT_DriverIRQHandler + BX R0 + + PUBWEAK FLEXPWM0_SUBMODULE0_IRQHandler + PUBWEAK FLEXPWM0_SUBMODULE0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM0_SUBMODULE0_IRQHandler + LDR R0, =FLEXPWM0_SUBMODULE0_DriverIRQHandler + BX R0 + + PUBWEAK FLEXPWM0_SUBMODULE1_IRQHandler + PUBWEAK FLEXPWM0_SUBMODULE1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM0_SUBMODULE1_IRQHandler + LDR R0, =FLEXPWM0_SUBMODULE1_DriverIRQHandler + BX R0 + + PUBWEAK FLEXPWM0_SUBMODULE2_IRQHandler + PUBWEAK FLEXPWM0_SUBMODULE2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM0_SUBMODULE2_IRQHandler + LDR R0, =FLEXPWM0_SUBMODULE2_DriverIRQHandler + BX R0 + + PUBWEAK Reserved65_IRQHandler + PUBWEAK Reserved65_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved65_IRQHandler + LDR R0, =Reserved65_DriverIRQHandler + BX R0 + + PUBWEAK QDC0_COMPARE_IRQHandler + PUBWEAK QDC0_COMPARE_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +QDC0_COMPARE_IRQHandler + LDR R0, =QDC0_COMPARE_DriverIRQHandler + BX R0 + + PUBWEAK QDC0_HOME_IRQHandler + PUBWEAK QDC0_HOME_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +QDC0_HOME_IRQHandler + LDR R0, =QDC0_HOME_DriverIRQHandler + BX R0 + + PUBWEAK QDC0_WATCHDOG_IRQHandler + PUBWEAK QDC0_WATCHDOG_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +QDC0_WATCHDOG_IRQHandler + LDR R0, =QDC0_WATCHDOG_DriverIRQHandler + BX R0 + + PUBWEAK QDC0_INDEX_IRQHandler + PUBWEAK QDC0_INDEX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +QDC0_INDEX_IRQHandler + LDR R0, =QDC0_INDEX_DriverIRQHandler + BX R0 + + PUBWEAK FREQME0_IRQHandler + PUBWEAK FREQME0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FREQME0_IRQHandler + LDR R0, =FREQME0_DriverIRQHandler + BX R0 + + PUBWEAK LPTMR0_IRQHandler + PUBWEAK LPTMR0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPTMR0_IRQHandler + LDR R0, =LPTMR0_DriverIRQHandler + BX R0 + + PUBWEAK Reserved72_IRQHandler + PUBWEAK Reserved72_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved72_IRQHandler + LDR R0, =Reserved72_DriverIRQHandler + BX R0 + + PUBWEAK OS_EVENT_IRQHandler + PUBWEAK OS_EVENT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +OS_EVENT_IRQHandler + LDR R0, =OS_EVENT_DriverIRQHandler + BX R0 + + PUBWEAK WAKETIMER0_IRQHandler + PUBWEAK WAKETIMER0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +WAKETIMER0_IRQHandler + LDR R0, =WAKETIMER0_DriverIRQHandler + BX R0 + + PUBWEAK UTICK0_IRQHandler + PUBWEAK UTICK0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UTICK0_IRQHandler + LDR R0, =UTICK0_DriverIRQHandler + BX R0 + + PUBWEAK WWDT0_IRQHandler + PUBWEAK WWDT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +WWDT0_IRQHandler + LDR R0, =WWDT0_DriverIRQHandler + BX R0 + + PUBWEAK Reserved77_IRQHandler + PUBWEAK Reserved77_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved77_IRQHandler + LDR R0, =Reserved77_DriverIRQHandler + BX R0 + + PUBWEAK ADC0_IRQHandler + PUBWEAK ADC0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_IRQHandler + LDR R0, =ADC0_DriverIRQHandler + BX R0 + + PUBWEAK ADC1_IRQHandler + PUBWEAK ADC1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC1_IRQHandler + LDR R0, =ADC1_DriverIRQHandler + BX R0 + + PUBWEAK CMP0_IRQHandler + PUBWEAK CMP0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CMP0_IRQHandler + LDR R0, =CMP0_DriverIRQHandler + BX R0 + + PUBWEAK CMP1_IRQHandler + PUBWEAK CMP1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CMP1_IRQHandler + LDR R0, =CMP1_DriverIRQHandler + BX R0 + + PUBWEAK Reserved82_IRQHandler + PUBWEAK Reserved82_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved82_IRQHandler + LDR R0, =Reserved82_DriverIRQHandler + BX R0 + + PUBWEAK DAC0_IRQHandler + PUBWEAK DAC0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DAC0_IRQHandler + LDR R0, =DAC0_DriverIRQHandler + BX R0 + + PUBWEAK Reserved84_IRQHandler + PUBWEAK Reserved84_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved84_IRQHandler + LDR R0, =Reserved84_DriverIRQHandler + BX R0 + + PUBWEAK Reserved85_IRQHandler + PUBWEAK Reserved85_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved85_IRQHandler + LDR R0, =Reserved85_DriverIRQHandler + BX R0 + + PUBWEAK Reserved86_IRQHandler + PUBWEAK Reserved86_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved86_IRQHandler + LDR R0, =Reserved86_DriverIRQHandler + BX R0 + + PUBWEAK GPIO0_IRQHandler + PUBWEAK GPIO0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GPIO0_IRQHandler + LDR R0, =GPIO0_DriverIRQHandler + BX R0 + + PUBWEAK GPIO1_IRQHandler + PUBWEAK GPIO1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GPIO1_IRQHandler + LDR R0, =GPIO1_DriverIRQHandler + BX R0 + + PUBWEAK GPIO2_IRQHandler + PUBWEAK GPIO2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GPIO2_IRQHandler + LDR R0, =GPIO2_DriverIRQHandler + BX R0 + + PUBWEAK GPIO3_IRQHandler + PUBWEAK GPIO3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GPIO3_IRQHandler + LDR R0, =GPIO3_DriverIRQHandler + BX R0 + + PUBWEAK GPIO4_IRQHandler + PUBWEAK GPIO4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GPIO4_IRQHandler + LDR R0, =GPIO4_DriverIRQHandler + BX R0 + + PUBWEAK Reserved92_IRQHandler + PUBWEAK Reserved92_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved92_IRQHandler + LDR R0, =Reserved92_DriverIRQHandler + BX R0 + + PUBWEAK LPI2C2_IRQHandler + PUBWEAK LPI2C2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPI2C2_IRQHandler + LDR R0, =LPI2C2_DriverIRQHandler + BX R0 + + PUBWEAK LPI2C3_IRQHandler + PUBWEAK LPI2C3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPI2C3_IRQHandler + LDR R0, =LPI2C3_DriverIRQHandler + BX R0 + + PUBWEAK FLEXPWM1_RELOAD_ERROR_IRQHandler + PUBWEAK FLEXPWM1_RELOAD_ERROR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM1_RELOAD_ERROR_IRQHandler + LDR R0, =FLEXPWM1_RELOAD_ERROR_DriverIRQHandler + BX R0 + + PUBWEAK FLEXPWM1_FAULT_IRQHandler + PUBWEAK FLEXPWM1_FAULT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM1_FAULT_IRQHandler + LDR R0, =FLEXPWM1_FAULT_DriverIRQHandler + BX R0 + + PUBWEAK FLEXPWM1_SUBMODULE0_IRQHandler + PUBWEAK FLEXPWM1_SUBMODULE0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM1_SUBMODULE0_IRQHandler + LDR R0, =FLEXPWM1_SUBMODULE0_DriverIRQHandler + BX R0 + + PUBWEAK FLEXPWM1_SUBMODULE1_IRQHandler + PUBWEAK FLEXPWM1_SUBMODULE1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM1_SUBMODULE1_IRQHandler + LDR R0, =FLEXPWM1_SUBMODULE1_DriverIRQHandler + BX R0 + + PUBWEAK FLEXPWM1_SUBMODULE2_IRQHandler + PUBWEAK FLEXPWM1_SUBMODULE2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXPWM1_SUBMODULE2_IRQHandler + LDR R0, =FLEXPWM1_SUBMODULE2_DriverIRQHandler + BX R0 + + PUBWEAK Reserved100_IRQHandler + PUBWEAK Reserved100_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved100_IRQHandler + LDR R0, =Reserved100_DriverIRQHandler + BX R0 + + PUBWEAK QDC1_COMPARE_IRQHandler + PUBWEAK QDC1_COMPARE_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +QDC1_COMPARE_IRQHandler + LDR R0, =QDC1_COMPARE_DriverIRQHandler + BX R0 + + PUBWEAK QDC1_HOME_IRQHandler + PUBWEAK QDC1_HOME_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +QDC1_HOME_IRQHandler + LDR R0, =QDC1_HOME_DriverIRQHandler + BX R0 + + PUBWEAK QDC1_WATCHDOG_IRQHandler + PUBWEAK QDC1_WATCHDOG_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +QDC1_WATCHDOG_IRQHandler + LDR R0, =QDC1_WATCHDOG_DriverIRQHandler + BX R0 + + PUBWEAK QDC1_INDEX_IRQHandler + PUBWEAK QDC1_INDEX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +QDC1_INDEX_IRQHandler + LDR R0, =QDC1_INDEX_DriverIRQHandler + BX R0 + +Reserved16_DriverIRQHandler +CMC_DriverIRQHandler +DMA_CH0_DriverIRQHandler +DMA_CH1_DriverIRQHandler +DMA_CH2_DriverIRQHandler +DMA_CH3_DriverIRQHandler +DMA_CH4_DriverIRQHandler +DMA_CH5_DriverIRQHandler +DMA_CH6_DriverIRQHandler +DMA_CH7_DriverIRQHandler +ERM0_SINGLE_BIT_DriverIRQHandler +ERM0_MULTI_BIT_DriverIRQHandler +FMU0_DriverIRQHandler +GLIKEY0_DriverIRQHandler +MBC0_DriverIRQHandler +SCG0_DriverIRQHandler +SPC0_DriverIRQHandler +VBAT0_DriverIRQHandler +WUU0_DriverIRQHandler +CAN0_DriverIRQHandler +Reserved36_DriverIRQHandler +Reserved37_DriverIRQHandler +Reserved38_DriverIRQHandler +FLEXIO_DriverIRQHandler +I3C0_DriverIRQHandler +Reserved41_DriverIRQHandler +LPI2C0_DriverIRQHandler +LPI2C1_DriverIRQHandler +LPSPI0_DriverIRQHandler +LPSPI1_DriverIRQHandler +Reserved46_DriverIRQHandler +LPUART0_DriverIRQHandler +LPUART1_DriverIRQHandler +LPUART2_DriverIRQHandler +LPUART3_DriverIRQHandler +LPUART4_DriverIRQHandler +USB0_DriverIRQHandler +Reserved53_DriverIRQHandler +CDOG0_DriverIRQHandler +CTIMER0_DriverIRQHandler +CTIMER1_DriverIRQHandler +CTIMER2_DriverIRQHandler +CTIMER3_DriverIRQHandler +CTIMER4_DriverIRQHandler +FLEXPWM0_RELOAD_ERROR_DriverIRQHandler +FLEXPWM0_FAULT_DriverIRQHandler +FLEXPWM0_SUBMODULE0_DriverIRQHandler +FLEXPWM0_SUBMODULE1_DriverIRQHandler +FLEXPWM0_SUBMODULE2_DriverIRQHandler +Reserved65_DriverIRQHandler +QDC0_COMPARE_DriverIRQHandler +QDC0_HOME_DriverIRQHandler +QDC0_WATCHDOG_DriverIRQHandler +QDC0_INDEX_DriverIRQHandler +FREQME0_DriverIRQHandler +LPTMR0_DriverIRQHandler +Reserved72_DriverIRQHandler +OS_EVENT_DriverIRQHandler +WAKETIMER0_DriverIRQHandler +UTICK0_DriverIRQHandler +WWDT0_DriverIRQHandler +Reserved77_DriverIRQHandler +ADC0_DriverIRQHandler +ADC1_DriverIRQHandler +CMP0_DriverIRQHandler +CMP1_DriverIRQHandler +Reserved82_DriverIRQHandler +DAC0_DriverIRQHandler +Reserved84_DriverIRQHandler +Reserved85_DriverIRQHandler +Reserved86_DriverIRQHandler +GPIO0_DriverIRQHandler +GPIO1_DriverIRQHandler +GPIO2_DriverIRQHandler +GPIO3_DriverIRQHandler +GPIO4_DriverIRQHandler +Reserved92_DriverIRQHandler +LPI2C2_DriverIRQHandler +LPI2C3_DriverIRQHandler +FLEXPWM1_RELOAD_ERROR_DriverIRQHandler +FLEXPWM1_FAULT_DriverIRQHandler +FLEXPWM1_SUBMODULE0_DriverIRQHandler +FLEXPWM1_SUBMODULE1_DriverIRQHandler +FLEXPWM1_SUBMODULE2_DriverIRQHandler +Reserved100_DriverIRQHandler +QDC1_COMPARE_DriverIRQHandler +QDC1_HOME_DriverIRQHandler +QDC1_WATCHDOG_DriverIRQHandler +QDC1_INDEX_DriverIRQHandler +DefaultISR + B . + + END diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/system_MCXA156.c b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/system_MCXA156.c new file mode 100644 index 00000000000..95d57e74b70 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/system_MCXA156.c @@ -0,0 +1,139 @@ +/* +** ################################################################### +** Processors: MCXA156VLL +** MCXA156VMP +** MCXA156VPJ +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXA18 User manual +** Version: rev. 1.0, 2022-03-29 +** Build: b240328 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-03-29) +** Initial version based on v0.1UM +** +** ################################################################### +*/ + +/*! + * @file MCXA156 + * @version 1.0 + * @date 2022-03-29 + * @brief Device specific configuration file for MCXA156 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + + + + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInit (void) { +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ + + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ + +#if defined(__MCUXPRESSO) + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; +#else + extern void *__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; +#endif + /* Enable the LPCAC */ + SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK; + SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK; + + /* Enable flash RWX when FLASH_ACL in IFR0 is invalid */ + if ((*((volatile const uint32_t *)(0x1000000)) == 0xFFFFFFFFU) || + ((*((volatile const uint32_t *)(0x1000000)) == 0x59630000U) && + (*((volatile const uint32_t *)(0x1000040)) == 0xFFFFFFFFU) && + (*((volatile const uint32_t *)(0x1000044)) == 0xFFFFFFFFU) && + (*((volatile const uint32_t *)(0x1000048)) == 0xFFFFFFFFU) && + (*((volatile const uint32_t *)(0x100004C)) == 0xFFFFFFFFU) && + (*((volatile const uint32_t *)(0x1000050)) == 0xFFFFFFFFU) && + (*((volatile const uint32_t *)(0x1000054)) == 0xFFFFFFFFU) && + (*((volatile const uint32_t *)(0x1000058)) == 0xFFFFFFFFU) && + (*((volatile const uint32_t *)(0x100005C)) == 0xFFFFFFFFU))) + { + /* Enable MBC register written with GLIKEY index15 */ + GLIKEY0->CTRL_0 = 0x00060000U; + GLIKEY0->CTRL_0 = 0x0002000FU; + GLIKEY0->CTRL_0 = 0x0001000FU; + GLIKEY0->CTRL_1 = 0x00290000U; + GLIKEY0->CTRL_0 = 0x0002000FU; + GLIKEY0->CTRL_1 = 0x00280000U; + GLIKEY0->CTRL_0 = 0x0000000FU; + + /* Enable RWX for GLBAC0 */ + MBC0->MBC_INDEX[0].MBC_MEMN_GLBAC[0] = 0x7700U; + + /* Use GLBAC0 for all flash block */ + for (uint8_t i = 0; i < 8U; i++) + { + MBC0->MBC_INDEX[0].MBC_DOM0_MEM0_BLK_CFG_W[i] = 0x00000000U; + } + + /* Disable MBC register written */ + GLIKEY0->CTRL_0 = 0x0002000FU; + } + SystemInitHook(); +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + +} + +/* ---------------------------------------------------------------------------- + -- SystemInitHook() + ---------------------------------------------------------------------------- */ + +__attribute__ ((weak)) void SystemInitHook (void) { + /* Void implementation of the weak function. */ +} diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/system_MCXA156.h b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/system_MCXA156.h new file mode 100644 index 00000000000..ab51c2cecb8 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/MCXA156/system_MCXA156.h @@ -0,0 +1,107 @@ +/* +** ################################################################### +** Processors: MCXA156VLL +** MCXA156VMP +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: MCXA18 User manual +** Version: rev. 1.0, 2022-03-29 +** Build: b230829 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2023 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2022-03-29) +** Initial version based on v0.1UM +** +** ################################################################### +*/ + +/*! + * @file MCXA156 + * @version 1.0 + * @date 2022-03-29 + * @brief Device specific configuration file for MCXA156 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_MCXA156_H_ +#define _SYSTEM_MCXA156_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ +#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_32MHZ 32000000u /* FRO 32 MHz (fro_32m) */ +#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ +#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +/** + * @brief SystemInit function hook. + * + * This weak function allows to call specific initialization code during the + * SystemInit() execution.This can be used when an application specific code needs + * to be called as close to the reset entry as possible (for example the Multicore + * Manager MCMGR_EarlyInit() function call). + * NOTE: No global r/w variables can be used in this hook function because the + * initialization of these variables happens after this function. + */ +void SystemInitHook (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_MCXA156_H_ */ diff --git a/bsp/nxp/mcx/mcxa/Libraries/MCXA156/SConscript b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/SConscript new file mode 100644 index 00000000000..4fd2f5dd8ce --- /dev/null +++ b/bsp/nxp/mcx/mcxa/Libraries/MCXA156/SConscript @@ -0,0 +1,54 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +path = [cwd + '/../CMSIS/Core/Include',cwd + '/components/codec', cwd + '/MCXA156', cwd + '/MCXA156/drivers', cwd + '/middleware/sdmmc/inc', cwd + '/middleware/sdmmc/port'] +src = Split(''' + MCXA156/system_MCXA156.c + ''') + +if rtconfig.PLATFORM in ['gcc']: + src += ['MCXA156/gcc/startup_MCXA156.S'] +elif rtconfig.PLATFORM in ['armcc', 'armclang']: + src += ['MCXA156/arm/startup_MCXA156.s'] +elif rtconfig.PLATFORM in ['iccarm']: + src += ['MCXA156/iar/startup_MCXA156.s'] + +src += ['MCXA156/drivers/fsl_aoi.c'] +src += ['MCXA156/drivers/fsl_clock.c'] +src += ['MCXA156/drivers/fsl_cmc.c'] +src += ['MCXA156/drivers/fsl_common.c'] +src += ['MCXA156/drivers/fsl_common_arm.c'] +src += ['MCXA156/drivers/fsl_crc.c'] +src += ['MCXA156/drivers/fsl_ctimer.c'] +src += ['MCXA156/drivers/fsl_edma.c'] +src += ['MCXA156/drivers/fsl_edma_soc.c'] +src += ['MCXA156/drivers/fsl_eim.c'] +src += ['MCXA156/drivers/fsl_eqdc.c'] +src += ['MCXA156/drivers/fsl_erm.c'] +src += ['MCXA156/drivers/fsl_freqme.c'] +src += ['MCXA156/drivers/fsl_glikey.c'] +src += ['MCXA156/drivers/fsl_gpio.c'] +src += ['MCXA156/drivers/fsl_i3c.c'] +src += ['MCXA156/drivers/fsl_i3c_edma.c'] +src += ['MCXA156/drivers/fsl_inputmux.c'] +src += ['MCXA156/drivers/fsl_lpadc.c'] +src += ['MCXA156/drivers/fsl_lpcmp.c'] +src += ['MCXA156/drivers/fsl_lpi2c.c'] +src += ['MCXA156/drivers/fsl_lpi2c_edma.c'] +src += ['MCXA156/drivers/fsl_lptmr.c'] +src += ['MCXA156/drivers/fsl_lpuart.c'] +src += ['MCXA156/drivers/fsl_lpuart_edma.c'] +src += ['MCXA156/drivers/fsl_ostimer.c'] +src += ['MCXA156/drivers/fsl_pwm.c'] +src += ['MCXA156/drivers/fsl_reset.c'] +src += ['MCXA156/drivers/fsl_spc.c'] +src += ['MCXA156/drivers/fsl_utick.c'] +src += ['MCXA156/drivers/fsl_vbat.c'] +src += ['MCXA156/drivers/fsl_waketimer.c'] +src += ['MCXA156/drivers/fsl_wuu.c'] +src += ['MCXA156/drivers/fsl_wwdt.c'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/.config b/bsp/nxp/mcx/mcxa/frdm-mcxa156/.config new file mode 100644 index 00000000000..58fca7b8af5 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/.config @@ -0,0 +1,1340 @@ +CONFIG_SOC_MCX=y + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER=y +CONFIG_RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER=y +# CONFIG_RT_KLIBC_USING_VSNPRINTF_MSVC_STYLE_INTEGER_SPECIFIERS is not set +CONFIG_RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE=32 +CONFIG_RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION=6 +CONFIG_RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL=9 +CONFIG_RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS=4 +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options + +# CONFIG_RT_UTEST_TC_USING_KLIBC is not set +# end of klibc options + +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50200 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_RT_USING_HW_ATOMIC=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_FPU=y +CONFIG_ARCH_ARM_CORTEX_SECURE=y +CONFIG_ARCH_ARM_CORTEX_M33=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +CONFIG_RT_USING_HWTIMER=y +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +CONFIG_RT_USING_ULOG=y +# CONFIG_ULOG_OUTPUT_LVL_A is not set +# CONFIG_ULOG_OUTPUT_LVL_E is not set +# CONFIG_ULOG_OUTPUT_LVL_W is not set +# CONFIG_ULOG_OUTPUT_LVL_I is not set +CONFIG_ULOG_OUTPUT_LVL_D=y +CONFIG_ULOG_OUTPUT_LVL=7 +# CONFIG_ULOG_USING_ISR_LOG is not set +CONFIG_ULOG_ASSERT_ENABLE=y +CONFIG_ULOG_LINE_BUF_SIZE=128 +# CONFIG_ULOG_USING_ASYNC_OUTPUT is not set + +# +# log format +# +CONFIG_ULOG_OUTPUT_FLOAT=y +# CONFIG_ULOG_USING_COLOR is not set +# CONFIG_ULOG_OUTPUT_TIME is not set +CONFIG_ULOG_OUTPUT_LEVEL=y +CONFIG_ULOG_OUTPUT_TAG=y +# CONFIG_ULOG_OUTPUT_THREAD_NAME is not set +# end of log format + +CONFIG_ULOG_BACKEND_USING_CONSOLE=y +# CONFIG_ULOG_BACKEND_USING_FILE is not set +# CONFIG_ULOG_USING_FILTER is not set +# CONFIG_ULOG_USING_SYSLOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +# +# Hardware Drivers Config +# +CONFIG_SOC_MCXA156=y + +# +# On-chip Peripheral Drivers +# +# CONFIG_BSP_USING_DMA is not set +CONFIG_BSP_USING_PIN=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_HWTIMER is not set +# CONFIG_BSP_USING_PWM is not set +# end of On-chip Peripheral Drivers + +# +# Board extended module Drivers +# +# end of Hardware Drivers Config diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/Kconfig b/bsp/nxp/mcx/mcxa/frdm-mcxa156/Kconfig new file mode 100644 index 00000000000..eb5f8d1f591 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/Kconfig @@ -0,0 +1,18 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../../../.. + +PKGS_DIR := packages + +config SOC_MCX + bool + select ARCH_ARM_CORTEX_M33 + select ARCH_ARM_CORTEX_SECURE + default y + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/SConscript b/bsp/nxp/mcx/mcxa/frdm-mcxa156/SConscript new file mode 100644 index 00000000000..c7ef7659ece --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/SConscript @@ -0,0 +1,14 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/SConstruct b/bsp/nxp/mcx/mcxa/frdm-mcxa156/SConstruct new file mode 100644 index 00000000000..ed0bfe11ffd --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/SConstruct @@ -0,0 +1,67 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +if rtconfig.PLATFORM == 'armcc': + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + # overwrite cflags, because cflags has '--C99' + CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES') +else: + env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/Libraries'): + libraries_path_prefix = SDK_ROOT + '/Libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/Libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# include cmsis +objs.extend(SConscript(os.path.join(libraries_path_prefix, rtconfig.BSP_LIBRARY_TYPE, 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/applications/SConscript b/bsp/nxp/mcx/mcxa/frdm-mcxa156/applications/SConscript new file mode 100644 index 00000000000..f11833c8d8d --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/applications/SConscript @@ -0,0 +1,15 @@ +from building import * +import os + +cwd = GetCurrentDir() +CPPPATH = [cwd] +src = Glob('*.c') + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/applications/main.c b/bsp/nxp/mcx/mcxa/frdm-mcxa156/applications/main.c new file mode 100644 index 00000000000..c539fd56652 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/applications/main.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-10-24 Magicoe first version + * 2020-01-10 Kevin/Karl Add PS demo + * 2020-09-21 supperthomas fix the main.c + * + */ + +#include +#include "drv_pin.h" + +#define LED_PIN ((3*32)+12) + +int main(void) +{ +#if defined(__CC_ARM) + rt_kprintf("using armcc, version: %d\n", __ARMCC_VERSION); +#elif defined(__clang__) + rt_kprintf("using armclang, version: %d\n", __ARMCC_VERSION); +#elif defined(__ICCARM__) + rt_kprintf("using iccarm, version: %d\n", __VER__); +#elif defined(__GNUC__) + rt_kprintf("using gcc, version: %d.%d\n", __GNUC__, __GNUC_MINOR__); +#endif + + while (1) + { + rt_thread_mdelay(1000); /* Delay 1S */ + rt_kprintf("MCXA156 HelloWorld\r\n"); + } +} + +// end file diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/Kconfig b/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/Kconfig new file mode 100644 index 00000000000..3b56d190ec5 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/Kconfig @@ -0,0 +1,173 @@ +menu "Hardware Drivers Config" + +config SOC_MCXA156 + bool + select SOC_MCXA156_SERIES + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Peripheral Drivers" + + config BSP_USING_DMA + bool "Enable DMA" + select RT_USING_DMA + default n + + config BSP_USING_PIN + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + config BSP_USING_UART + bool "Enable UART" + select RT_USING_UART + default y + + if BSP_USING_UART + config BSP_USING_UART0 + bool "Enable LPUART as UART" + default y + + endif + + + menuconfig BSP_USING_I2C + config BSP_USING_I2C + bool "Enable I2C" + select RT_USING_I2C + default y + + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable Flexcomm0 I2C" + default y + config BSP_USING_I2C1 + bool "Enable Flexcomm1 I2C" + default y + endif + + menuconfig BSP_USING_SPI + config BSP_USING_SPI + bool "Enable SPI" + select RT_USING_SPI + default y + + if BSP_USING_SPI + config BSP_USING_SPI3 + bool "Enable Flexcomm3 as SPI" + default n + + config BSP_USING_SPI8 + bool "Enable Flexcomm8 as High Speed SPI" + default y + endif + + menuconfig BSP_USING_ADC + config BSP_USING_ADC + bool "Enable ADC Channel" + select RT_USING_ADC + default y + + if BSP_USING_ADC + config BSP_USING_ADC0_CH0 + bool "Enable ADC0 Channel0" + default y + + config BSP_USING_ADC0_CH1 + bool "Enable ADC0 Channel1" + default n + + config BSP_USING_ADC0_CH8 + bool "Enable ADC0 Channel8" + default n + + + config BSP_USING_ADC0_CH13 + bool "Enable ADC0 Channel13" + default n + + + config BSP_USING_ADC0_CH26 + bool "Enable ADC0 Channel26" + default n + + endif + + config BSP_USING_SDIO + bool "Enable SDIO SD Card Interface" + select RT_USING_SDIO + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + default y + + config BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default y + + config BSP_USING_WDT + bool "Enable WatchDog" + select RT_USING_WDT + default n + + menuconfig BSP_USING_HWTIMER + config BSP_USING_HWTIMER + bool "Enable Timer" + select RT_USING_HWTIMER + default y + + if BSP_USING_HWTIMER + config BSP_USING_CTIMER0 + bool "Enable CIMER0" + default y + + config BSP_USING_CTIMER1 + bool "Enable CIMER1" + default n + + config BSP_USING_CTIMER3 + bool "Enable CIMER3" + default n + + config BSP_USING_CTIMER4 + bool "Enable CIMER4" + default n + endif + + menuconfig BSP_USING_PWM + config BSP_USING_PWM + bool "Enable PWM" + select RT_USING_PWM + default y + + if BSP_USING_PWM + config BSP_USING_CTIMER1_MAT0 + bool "Enable CIMER1 Match0 as PWM output" + default y + + config BSP_USING_CTIMER2_MAT0 + bool "Enable CIMER2 Match0 as PWM output" + default n + + config BSP_USING_CTIMER2_MAT1 + bool "Enable CIMER2 Match1 as PWM output" + default n + + config BSP_USING_CTIMER2_MAT2 + bool "Enable CIMER2 Match2 as PWM output" + default n + + config BSP_USING_CTIMER3_MAT2 + bool "Enable CIMER3 Match2 as PWM output" + default n + endif +endmenu + + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/MCUX_Config/board/clock_config.c b/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/MCUX_Config/board/clock_config.c new file mode 100644 index 00000000000..11699f77e11 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/MCUX_Config/board/clock_config.c @@ -0,0 +1,482 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ +/* + * How to setup clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Set up wait states of the flash. + * + * 3. Set up all dividers. + * + * 4. Set up all selectors to provide selected clocks. + * + */ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v13.0 +processor: MCXA156 +package_id: MCXA156VLL +mcu_data: ksdk2_0 +processor_version: 0.15.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +#include "fsl_clock.h" +#include "clock_config.h" +#include "fsl_spc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockFRO96M(); +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: CLK_1M_clock.outFreq, value: 1 MHz} +- {id: CPU_clock.outFreq, value: 12 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: MAIN_clock.outFreq, value: 12 MHz} +- {id: Slow_clock.outFreq, value: 3 MHz} +- {id: System_clock.outFreq, value: 12 MHz} +- {id: UTICK_clock.outFreq, value: 1 MHz} +settings: +- {id: SCGMode, value: SIRC} +- {id: FRO_HF_PERIPHERALS_EN_CFG, value: Disabled} +- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} +- {id: SCG.SCSSEL.sel, value: SCG.SIRC} +- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ + uint32_t coreFreq; + spc_active_mode_core_ldo_option_t ldoOption; + spc_sram_voltage_config_t sramOption; + + /* Get the CPU Core frequency */ + coreFreq = CLOCK_GetCoreSysClkFreq(); + + /* The flow of increasing voltage and frequency */ + if (coreFreq <= BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) { + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P0V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + } + + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ + + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO12M */ + + /* The flow of decreasing voltage and frequency */ + if (coreFreq > BOARD_BOOTCLOCKFRO12M_CORE_CLOCK) { + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P0V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + } + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + + /*!< Set up dividers */ + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +} +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO24M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO24M +outputs: +- {id: CLK_1M_clock.outFreq, value: 1 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: CPU_clock.outFreq, value: 24 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz} +- {id: FRO_HF_clock.outFreq, value: 48 MHz} +- {id: MAIN_clock.outFreq, value: 48 MHz} +- {id: Slow_clock.outFreq, value: 6 MHz} +- {id: System_clock.outFreq, value: 24 MHz} +- {id: UTICK_clock.outFreq, value: 1 MHz} +settings: +- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} +- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO24M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO24M configuration + ******************************************************************************/ +void BOARD_BootClockFRO24M(void) +{ + uint32_t coreFreq; + spc_active_mode_core_ldo_option_t ldoOption; + spc_sram_voltage_config_t sramOption; + + /* Get the CPU Core frequency */ + coreFreq = CLOCK_GetCoreSysClkFreq(); + + /* The flow of increasing voltage and frequency */ + if (coreFreq <= BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) { + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P0V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + } + + CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */ + + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ + + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */ + + /* The flow of decreasing voltage and frequency */ + if (coreFreq > BOARD_BOOTCLOCKFRO24M_CORE_CLOCK) { + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x0U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P0V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + } + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + + /*!< Set up dividers */ + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 2U); /* !< Set AHBCLKDIV divider to value 2 */ + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFRO24M_CORE_CLOCK; +} +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO48M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO48M +outputs: +- {id: CLK_1M_clock.outFreq, value: 1 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: CPU_clock.outFreq, value: 48 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_DIV_clock.outFreq, value: 48 MHz} +- {id: FRO_HF_clock.outFreq, value: 48 MHz} +- {id: MAIN_clock.outFreq, value: 48 MHz} +- {id: Slow_clock.outFreq, value: 12 MHz} +- {id: System_clock.outFreq, value: 48 MHz} +- {id: UTICK_clock.outFreq, value: 1 MHz} +settings: +- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO48M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO48M configuration + ******************************************************************************/ +void BOARD_BootClockFRO48M(void) +{ + uint32_t coreFreq; + spc_active_mode_core_ldo_option_t ldoOption; + spc_sram_voltage_config_t sramOption; + + /* Get the CPU Core frequency */ + coreFreq = CLOCK_GetCoreSysClkFreq(); + + /* The flow of increasing voltage and frequency */ + if (coreFreq <= BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) { + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P0V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + } + + CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */ + + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ + + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */ + + /* The flow of decreasing voltage and frequency */ + if (coreFreq > BOARD_BOOTCLOCKFRO48M_CORE_CLOCK) { + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P0V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + } + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + + /*!< Set up dividers */ + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFRO48M_CORE_CLOCK; +} +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO64M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO64M +outputs: +- {id: CLK_1M_clock.outFreq, value: 1 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: CPU_clock.outFreq, value: 64 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_DIV_clock.outFreq, value: 64 MHz} +- {id: FRO_HF_clock.outFreq, value: 64 MHz} +- {id: MAIN_clock.outFreq, value: 64 MHz} +- {id: Slow_clock.outFreq, value: 16 MHz} +- {id: System_clock.outFreq, value: 64 MHz} +- {id: UTICK_clock.outFreq, value: 1 MHz} +settings: +- {id: VDD_CORE, value: voltage_1v1} +- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FROHFDIV.scale, value: '1', locked: true} +- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} +- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true} +sources: +- {id: SCG.FIRC.outFreq, value: 64 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO64M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO64M configuration + ******************************************************************************/ +void BOARD_BootClockFRO64M(void) +{ + uint32_t coreFreq; + spc_active_mode_core_ldo_option_t ldoOption; + spc_sram_voltage_config_t sramOption; + + /* Get the CPU Core frequency */ + coreFreq = CLOCK_GetCoreSysClkFreq(); + + /* The flow of increasing voltage and frequency */ + if (coreFreq <= BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) { + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P1V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + } + + CLOCK_SetupFROHFClocking(64000000U); /*!< Enable FRO HF(64MHz) output */ + + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ + + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */ + + /* The flow of decreasing voltage and frequency */ + if (coreFreq > BOARD_BOOTCLOCKFRO64M_CORE_CLOCK) { + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P1V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + } + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + + /*!< Set up dividers */ + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFRO64M_CORE_CLOCK; +} +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO96M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO96M +called_from_default_init: true +outputs: +- {id: CLK_1M_clock.outFreq, value: 1 MHz} +- {id: CLK_48M_clock.outFreq, value: 48 MHz} +- {id: CPU_clock.outFreq, value: 96 MHz} +- {id: FRO_12M_clock.outFreq, value: 12 MHz} +- {id: FRO_HF_DIV_clock.outFreq, value: 96 MHz} +- {id: FRO_HF_clock.outFreq, value: 96 MHz} +- {id: MAIN_clock.outFreq, value: 96 MHz} +- {id: Slow_clock.outFreq, value: 24 MHz} +- {id: System_clock.outFreq, value: 96 MHz} +- {id: UTICK_clock.outFreq, value: 1 MHz} +settings: +- {id: VDD_CORE, value: voltage_1v1} +- {id: CLKOUTDIV_HALT, value: Enable} +- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0} +- {id: MRCC.FROHFDIV.scale, value: '1', locked: true} +- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1} +- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true} +sources: +- {id: SCG.FIRC.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO96M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO96M configuration + ******************************************************************************/ +void BOARD_BootClockFRO96M(void) +{ + uint32_t coreFreq; + spc_active_mode_core_ldo_option_t ldoOption; + spc_sram_voltage_config_t sramOption; + + /* Get the CPU Core frequency */ + coreFreq = CLOCK_GetCoreSysClkFreq(); + + /* The flow of increasing voltage and frequency */ + if (coreFreq <= BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) { + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P1V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + } + + CLOCK_SetupFROHFClocking(96000000U); /*!< Enable FRO HF(96MHz) output */ + + CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */ + + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */ + + /* The flow of decreasing voltage and frequency */ + if (coreFreq > BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) { + /* Configure Flash to support different voltage level and frequency */ + FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U)); + /* Specifies the operating voltage for the SRAM's read/write timing margin */ + sramOption.operateVoltage = kSPC_sramOperateAt1P1V; + sramOption.requestVoltageUpdate = true; + (void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption); + /* Set the LDO_CORE VDD regulator level */ + ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage; + ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength; + (void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption); + } + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + + /*!< Set up dividers */ + CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */ + + /* Set SystemCoreClock variable */ + SystemCoreClock = BOARD_BOOTCLOCKFRO96M_CORE_CLOCK; +} diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/MCUX_Config/board/clock_config.h b/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/MCUX_Config/board/clock_config.h new file mode 100644 index 00000000000..db80b79f34a --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/MCUX_Config/board/clock_config.h @@ -0,0 +1,170 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO24M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO24M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO24M_CORE_CLOCK 24000000U /*!< Core clock frequency: 24000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO24M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO24M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO48M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO48M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO48M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO48M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO64M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO64M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO64M_CORE_CLOCK 64000000U /*!< Core clock frequency: 64000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO64M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO64M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO96M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO96M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockFRO96M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO96M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/MCUX_Config/board/pin_mux.c b/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/MCUX_Config/board/pin_mux.c new file mode 100644 index 00000000000..c9be992461a --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/MCUX_Config/board/pin_mux.c @@ -0,0 +1,121 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v15.0 +processor: MCXA156 +package_id: MCXA156VLL +mcu_data: ksdk2_0 +processor_version: 0.15.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +#include "fsl_common.h" +#include "fsl_port.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'} +- pin_list: + - {pin_num: '78', peripheral: LPUART0, signal: RX, pin_signal: P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/FLEXIO0_D2, slew_rate: fast, open_drain: disable, + drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal} + - {pin_num: '79', peripheral: LPUART0, signal: TX, pin_signal: P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/FLEXIO0_D3/CMP0_OUT, slew_rate: fast, open_drain: disable, + drive_strength: low, pull_select: up, pull_enable: enable, input_buffer: enable, invert_input: normal} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) +{ + /* PORT0: Peripheral clock is enabled */ + CLOCK_EnableClock(kCLOCK_GatePORT0); + /* LPUART0 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn); + /* PORT0 peripheral is released from reset */ + RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn); + + const port_pin_config_t port0_2_pin78_config = {/* Internal pull-up resistor is enabled */ + kPORT_PullUp, + /* Low internal pull resistor value is selected. */ + kPORT_LowPullResistor, + /* Fast slew rate is configured */ + kPORT_FastSlewRate, + /* Passive input filter is disabled */ + kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + kPORT_OpenDrainDisable, + /* Low drive strength is configured */ + kPORT_LowDriveStrength, + /* Normal drive strength is configured */ + kPORT_NormalDriveStrength, + /* Pin is configured as LPUART0_RXD */ + kPORT_MuxAlt2, + /* Digital input enabled */ + kPORT_InputBufferEnable, + /* Digital input is not inverted */ + kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + kPORT_UnlockRegister}; + /* PORT0_2 (pin 78) is configured as LPUART0_RXD */ + PORT_SetPinConfig(PORT0, 2U, &port0_2_pin78_config); + + const port_pin_config_t port0_3_pin79_config = {/* Internal pull-up resistor is enabled */ + kPORT_PullUp, + /* Low internal pull resistor value is selected. */ + kPORT_LowPullResistor, + /* Fast slew rate is configured */ + kPORT_FastSlewRate, + /* Passive input filter is disabled */ + kPORT_PassiveFilterDisable, + /* Open drain output is disabled */ + kPORT_OpenDrainDisable, + /* Low drive strength is configured */ + kPORT_LowDriveStrength, + /* Normal drive strength is configured */ + kPORT_NormalDriveStrength, + /* Pin is configured as LPUART0_TXD */ + kPORT_MuxAlt2, + /* Digital input enabled */ + kPORT_InputBufferEnable, + /* Digital input is not inverted */ + kPORT_InputNormal, + /* Pin Control Register fields [15:0] are not locked */ + kPORT_UnlockRegister}; + /* PORT0_3 (pin 79) is configured as LPUART0_TXD */ + PORT_SetPinConfig(PORT0, 3U, &port0_3_pin79_config); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/MCUX_Config/board/pin_mux.h b/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/MCUX_Config/board/pin_mux.h new file mode 100644 index 00000000000..fb7d1fc04c7 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/MCUX_Config/board/pin_mux.h @@ -0,0 +1,51 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/SConscript b/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/SConscript new file mode 100644 index 00000000000..660c64b385c --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/SConscript @@ -0,0 +1,17 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +board.c +MCUX_Config/board/clock_config.c +MCUX_Config/board/pin_mux.c +""") + +CPPPATH = [cwd, cwd + '/MCUX_Config/board'] +CPPDEFINES = ['DEBUG', 'CPU_MCXA156VLL'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/board.c b/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/board.c new file mode 100644 index 00000000000..41b2e58f457 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/board.c @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-06 yandld first implementation + */ + +#include +#include + +#include "board.h" +#include "clock_config.h" +#include "drv_uart.h" + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initial board. + */ +void rt_hw_board_init() +{ + BOARD_InitBootPins(); + + /* This init has finished in secure side of TF-M */ + BOARD_InitBootClocks(); + + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + /* set pend exception priority */ + NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1); + + /*init uart device*/ + rt_hw_uart_init(); + +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + /* initialization board with RT-Thread Components */ + rt_components_board_init(); +#endif + +#ifdef RT_USING_HEAP + rt_kprintf("sram heap, begin: 0x%p, end: 0x%p\n", HEAP_BEGIN, HEAP_END); + rt_system_heap_init((void *)HEAP_BEGIN, (void *)(HEAP_END)); +#endif +} + +/** + * This function will called when memory fault. + */ +void MemManage_Handler(void) +{ + extern void HardFault_Handler(void); + + rt_kprintf("Memory Fault!\n"); + HardFault_Handler(); +} + +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/board.h b/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/board.h new file mode 100644 index 00000000000..bdbcbdd8f53 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/board.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + * 2010-02-04 Magicoe add board.h to LPC176x bsp + * 2013-12-18 Bernard porting to LPC4088 bsp + * 2017-08-02 XiaoYang porting to LPC54608 bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + + +#include + +#include + +#include "clock_config.h" +#include "fsl_common.h" +#include "fsl_reset.h" +#include "fsl_gpio.h" +#include "pin_mux.h" +#include "fsl_edma.h" + +// + +// +#if defined(__ARMCC_VERSION) +extern int Image$$ARM_LIB_HEAP$$ZI$$Base; +extern int Image$$ARM_LIB_STACK$$ZI$$Base; +#define HEAP_BEGIN ((void *)&Image$$ARM_LIB_HEAP$$ZI$$Base) +#define HEAP_END ((void*)&Image$$ARM_LIB_STACK$$ZI$$Base) +#elif defined(__ICCARM__) +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +extern void __RTT_HEAP_END; +#define HEAP_END (&__RTT_HEAP_END) +#elif defined(__GNUC__) +extern int __HeapBase; +extern int __HeapLimit; +#define HEAP_BEGIN ((void *)&__HeapBase) +#define HEAP_END ((void *)&__HeapLimit) +#endif + +void rt_hw_board_init(void); + + +#endif + + diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/linker_scripts/MCXA156_flash.ld b/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/linker_scripts/MCXA156_flash.ld new file mode 100644 index 00000000000..efc24cbe150 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/linker_scripts/MCXA156_flash.ld @@ -0,0 +1,200 @@ +/* +** ################################################################### +** Processors: MCXA156VLL +** MCXA156VMP +** MCXA156VPJ +** +** Compiler: GNU C Compiler +** Reference manual: MCXA18 User manual +** Version: rev. 1.0, 2022-03-29 +** Build: b240104 +** +** Abstract: +** Linker file for the GNU C Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + + +/* Entry Point */ +ENTRY(Reset_Handler) + +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800; + +/* Specify the memory areas */ +MEMORY +{ + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000200 + m_text (RX) : ORIGIN = 0x00000200, LENGTH = 0x000FFE00 + m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x0001E000 + m_sramx0 (RW) : ORIGIN = 0x04000000, LENGTH = 0x00002000 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into internal flash */ + .interrupts : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + /* The program code and other data goes into internal flash */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(4); + } > m_text + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > m_text + + .ARM : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > m_text + + .ctors : + { + __CTOR_LIST__ = .; + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + } > m_text + + .dtors : + { + __DTOR_LIST__ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + } > m_text + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } > m_text + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } > m_text + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } > m_text + + __etext = .; /* define a global symbol at end of code */ + __DATA_ROM = .; /* Symbol is used by startup for data initialization */ + + .data : AT(__DATA_ROM) + { + . = ALIGN(4); + __DATA_RAM = .; + __data_start__ = .; /* create a global symbol at data start */ + *(.ramfunc*) /* for functions in ram */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + KEEP(*(.jcr*)) + . = ALIGN(4); + __data_end__ = .; /* define a global symbol at data end */ + } > m_data + + __DATA_END = __DATA_ROM + (__data_end__ - __data_start__); + text_end = ORIGIN(m_text) + LENGTH(m_text); + ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data") + + /* Uninitialized data section */ + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + . = ALIGN(4); + __START_BSS = .; + __bss_start__ = .; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + __END_BSS = .; + } > m_data + + .heap : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + __HeapBase = .; + . += HEAP_SIZE; + __HeapLimit = .; + __heap_limit = .; /* Add for _sbrk */ + } > m_data + + .stack : + { + . = ALIGN(8); + . += STACK_SIZE; + } > m_data + + + /* Initializes stack on the end of block */ + __StackTop = ORIGIN(m_data) + LENGTH(m_data); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + .ARM.attributes 0 : { *(.ARM.attributes) } + + ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap") +} diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/linker_scripts/MCXA156_flash.scf b/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/linker_scripts/MCXA156_flash.scf new file mode 100644 index 00000000000..265cd9533cc --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/board/linker_scripts/MCXA156_flash.scf @@ -0,0 +1,71 @@ +#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c +/* +** ################################################################### +** Processors: MCXA156VLL +** MCXA156VMP +** MCXA156VPJ +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: MCXA18 User manual +** Version: rev. 1.0, 2022-03-29 +** Build: b240104 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2024 NXP +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#define m_interrupts_start 0x00000000 +#define m_interrupts_size 0x00000200 + +#define m_text_start 0x00000200 +#define m_text_size 0x000FFE00 + +#define m_data_start 0x20000000 +#define m_data_size 0x0001E000 + +#define m_sramx0_start 0x04000000; +#define m_sramx0_size 0x00002000; + +LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region + + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (.isr_vector,+FIRST) + } + + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } + +} diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/project.uvoptx b/bsp/nxp/mcx/mcxa/frdm-mcxa156/project.uvoptx new file mode 100644 index 00000000000..41ae9542dc6 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/project.uvoptx @@ -0,0 +1,1355 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread-frdm-mcxa156 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 13 + + + + + + + + + + + BIN\UL2V8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0MCXA15X_1024 -FS00 -FL0100000 -FP0($$Device:MCXA156VLL$devices\MCXA156\arm\MCXA15X_1024.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 5000000 + + + + + + Applications + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + Compiler + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 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..\..\..\..\..\components\utilities\ulog\backend\console_be.c + console_be.c + 0 + 0 + + + 9 + 92 + 1 + 0 + 0 + 0 + ..\..\..\..\..\components\utilities\ulog\ulog.c + ulog.c + 0 + 0 + + + + diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/project.uvprojx b/bsp/nxp/mcx/mcxa/frdm-mcxa156/project.uvprojx new file mode 100644 index 00000000000..4e8d74e1291 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/project.uvprojx @@ -0,0 +1,2387 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread-frdm-mcxa156 + 0x4 + ARM-ADS + 6180000::V6.18::ARMCLANG + 1 + + + MCXA156VLL + NXP + NXP.MCXA156_DFP.19.0.0 + https://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x20000000,0x01e000) IRAM2(0x04000000,0x3000) IROM(0x03000000,0x2000) IROM2(0x00000000,0x100000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP CLOCK(12000000) ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0MCXA15X_1024 -FS00 -FL0100000 -FP0($$Device:MCXA156VLL$devices\MCXA156\arm\MCXA15X_1024.FLM)) + 0 + $$Device:MCXA156VLL$devices\MCXA156\fsl_device_registers.h + + + + + + + + + + $$Device:MCXA156VLL$devices\MCXA156\MCXA156.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4102 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 1 + 1 + 16 + 0 + 0 + 0 + 0 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x1e000 + + + 1 + 0x3000000 + 0x2000 + + + 1 + 0x4002000 + 0x1000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x3000000 + 0x2000 + + + 1 + 0x0 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x1e000 + + + 0 + 0x4000000 + 0x3000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + --target=arm-arm-none-eabi + __RTTHREAD__, RT_USING_ARMLIBC, DEBUG, __STDC_LIMIT_MACROS, CPU_MCXA156VLL, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND + + 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..\Libraries\MCXA156\MCXA156\drivers\fsl_aoi.c + + + fsl_lpcmp.c + 1 + ..\Libraries\MCXA156\MCXA156\drivers\fsl_lpcmp.c + + + fsl_clock.c + 1 + ..\Libraries\MCXA156\MCXA156\drivers\fsl_clock.c + + + + + Utilities + + + console_be.c + 1 + ..\..\..\..\..\components\utilities\ulog\backend\console_be.c + + + ulog.c + 1 + ..\..\..\..\..\components\utilities\ulog\ulog.c + + + + + + + + + + + + + + + + + template + 1 + + + + + diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/rtconfig.h b/bsp/nxp/mcx/mcxa/frdm-mcxa156/rtconfig.h new file mode 100644 index 00000000000..0a801c8a32f --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/rtconfig.h @@ -0,0 +1,420 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +#define SOC_MCX + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +#define RT_KLIBC_USING_VSNPRINTF_LONGLONG +#define RT_KLIBC_USING_VSNPRINTF_STANDARD +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_EXPONENTIAL_SPECIFIERS +#define RT_KLIBC_USING_VSNPRINTF_WRITEBACK_SPECIFIER +#define RT_KLIBC_USING_VSNPRINTF_CHECK_NUL_IN_FORMAT_SPECIFIER +#define RT_KLIBC_USING_VSNPRINTF_INTEGER_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_DECIMAL_BUFFER_SIZE 32 +#define RT_KLIBC_USING_VSNPRINTF_FLOAT_PRECISION 6 +#define RT_KLIBC_USING_VSNPRINTF_MAX_INTEGRAL_DIGITS_FOR_DECIMAL 9 +#define RT_KLIBC_USING_VSNPRINTF_LOG10_TAYLOR_TERMS 4 +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 8 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice options */ + +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50200 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_HW_ATOMIC +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_FPU +#define ARCH_ARM_CORTEX_SECURE +#define ARCH_ARM_CORTEX_M33 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +#define RT_USING_HWTIMER +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +#define RT_USING_ULOG +#define ULOG_OUTPUT_LVL_D +#define ULOG_OUTPUT_LVL 7 +#define ULOG_ASSERT_ENABLE +#define ULOG_LINE_BUF_SIZE 128 + +/* log format */ + +#define ULOG_OUTPUT_FLOAT +#define ULOG_OUTPUT_LEVEL +#define ULOG_OUTPUT_TAG +/* end of log format */ +#define ULOG_BACKEND_USING_CONSOLE +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ + +/* Hardware Drivers Config */ + +#define SOC_MCXA156 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_PIN +#define BSP_USING_UART +#define BSP_USING_UART0 +/* end of On-chip Peripheral Drivers */ + +/* Board extended module Drivers */ + +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/rtconfig.py b/bsp/nxp/mcx/mcxa/frdm-mcxa156/rtconfig.py new file mode 100644 index 00000000000..d33db80d7ca --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/rtconfig.py @@ -0,0 +1,198 @@ +import os +import sys + +# toolchains options +ARCH='arm' +CPU='cortex-m33' +CROSS_TOOL='gcc' +BOARD_NAME = 'frdm-mcxa156' +BSP_LIBRARY_TYPE = 'MCXA156' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armclang' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:\Program Files\IAR Systems\Embedded Workbench 9.1' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +#BUILD = 'release' + +if PLATFORM == 'gcc': + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + DEVICE = ' -mcpu=' + CPU + '+nodsp' + ' -mthumb -mfloat-abi=soft -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Wall' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -D__START=entry -D__STARTUP_CLEAR_BSS' + LFLAGS = DEVICE + ' -specs=nano.specs -specs=nosys.specs -Wl,--defsym=__heap_size__=0x2000,--gc-sections,-Map=rtthread.map,--print-memory-usage -Tboard/linker_scripts/MCXA156_flash.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + else: + CFLAGS += ' -O2 -Os' + + POST_ACTION = OBJCPY + ' -O binary --remove-section=.boot_data --remove-section=.image_vertor_table --remove-section=.ncache $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti' + CXXFLAGS += CFLAGS + + M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' + M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' + M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ + ' -shared -fPIC -nostartfiles -static-libgcc' + M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu ' + CPU + '.fp.sp' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '/ARM/ARMCC/lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "./MCXA156_flash.scf" ' + + LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' + + CFLAGS += ' --diag_suppress=66,1296,186,6134' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' --c99' + + POST_ACTION = 'fromelf -z $TARGET' + # POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M33 ' + CFLAGS = ' --target=arm-arm-none-eabi' + CFLAGS += ' -mcpu=' + CPU + CFLAGS += ' -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\MCXA156_flash.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D__FPU_PRESENT' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=' + CPU + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu ' + CPU + AFLAGS += ' --fpu None' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/MCXA156_flash.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) + diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/template.uvoptx b/bsp/nxp/mcx/mcxa/frdm-mcxa156/template.uvoptx new file mode 100644 index 00000000000..5d08ddb8408 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/template.uvoptx @@ -0,0 +1,179 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rtthread-frdm-mcxa153 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 8 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 13 + + + + + + + + + + + BIN\UL2V8M.DLL + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0MCXA15X_1024 -FL0100000 -FS00 -FP0($$Device:MCXA156VLL$devices\MCXA156\arm\MCXA15X_1024.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 1 + 0 + 2 + 5000000 + + + + + diff --git a/bsp/nxp/mcx/mcxa/frdm-mcxa156/template.uvprojx b/bsp/nxp/mcx/mcxa/frdm-mcxa156/template.uvprojx new file mode 100644 index 00000000000..6d4efbd7883 --- /dev/null +++ b/bsp/nxp/mcx/mcxa/frdm-mcxa156/template.uvprojx @@ -0,0 +1,401 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rtthread-frdm-mcxa156 + 0x4 + ARM-ADS + 6190000::V6.19::ARMCLANG + 1 + + + MCXA156VLL + NXP + NXP.MCXA156_DFP.19.0.0 + https://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x20000000,0x01e000) IRAM2(0x04000000,0x3000) IROM(0x03000000,0x2000) IROM2(0x00000000,0x100000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP CLOCK(12000000) ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0MCXA15X_1024 -FS00 -FL0100000 -FP0($$Device:MCXA156VLL$devices\MCXA156\arm\MCXA15X_1024.FLM)) + 0 + $$Device:MCXA156VLL$devices\MCXA156\fsl_device_registers.h + + + + + + + + + + $$Device:MCXA156VLL$devices\MCXA156\MCXA156.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + + + + SARMV8M.DLL + + TCM.DLL + -pCM33 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4102 + + 1 + BIN\UL2V8M.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M33" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 1 + 1 + 16 + 0 + 0 + 0 + 0 + 4 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x1e000 + + + 1 + 0x3000000 + 0x2000 + + + 1 + 0x4002000 + 0x1000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x3000000 + 0x2000 + + + 1 + 0x0 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x1e000 + + + 0 + 0x4000000 + 0x3000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + --target=arm-arm-none-eabi + CPU_MCXA156VLL, ARM_MATH_CM33, RT_USING_ARM_LIBC + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + -x assembler-with-cpp + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x02000000 + + .\board\linker_scripts\MCXA156_flash.scf + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) + + + + + + + + + + + + + + + + + + template + 1 + + + + +