+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M4
+ @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M (4U) /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_FP
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TI_ARM__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000U
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __VTOR_PRESENT
+ #define __VTOR_PRESENT 1U
+ #warning "__VTOR_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:1; /*!< bit: 9 Reserved */
+ uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit */
+ uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RESERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[32U];
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES 4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
+#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+ #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+ #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+ #endif
+ #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
+ #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
+ #define NVIC_EnableIRQ __NVIC_EnableIRQ
+ #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
+ #define NVIC_DisableIRQ __NVIC_DisableIRQ
+ #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
+ #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
+ #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
+ #define NVIC_GetActive __NVIC_GetActive
+ #define NVIC_SetPriority __NVIC_SetPriority
+ #define NVIC_GetPriority __NVIC_GetPriority
+ #define NVIC_SystemReset __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+ #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+ #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+ #endif
+ #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+ #define NVIC_SetVector __NVIC_SetVector
+ #define NVIC_GetVector __NVIC_GetVector
+#endif /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET 16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
+#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
+#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
+#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
+
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable Interrupt
+ \details Enables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ __COMPILER_BARRIER();
+ NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __COMPILER_BARRIER();
+ }
+}
+
+
+/**
+ \brief Get Interrupt Enable status
+ \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt is not enabled.
+ \return 1 Interrupt is enabled.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Disable Interrupt
+ \details Disables a device specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ __DSB();
+ __ISB();
+ }
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+ \param [in] IRQn Device specific interrupt number.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ }
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+ \param [in] IRQn Device specific interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ \note IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+ }
+ else
+ {
+ return(0U);
+ }
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of a device specific interrupt or a processor exception.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) >= 0)
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief Set Interrupt Vector
+ \details Sets an interrupt vector in SRAM based interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ VTOR must been relocated to SRAM before.
+ \param [in] IRQn Interrupt number
+ \param [in] vector Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+ /* ARM Application Note 321 states that the M4 does not require the architectural barrier */
+}
+
+
+/**
+ \brief Get Interrupt Vector
+ \details Reads an interrupt vector from interrupt vector table.
+ The interrupt number can be positive to specify a device specific interrupt,
+ or negative to specify a processor exception.
+ \param [in] IRQn Interrupt number.
+ \return Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+ uint32_t *vectors = (uint32_t *)SCB->VTOR;
+ return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## MPU functions #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ########################## FPU functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \brief get FPU type
+ \details returns the FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = FPU->MVFR0;
+ if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+ {
+ return 1U; /* Single precision FPU */
+ }
+ else
+ {
+ return 0U; /* No FPU */
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/basic_math_functions.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/basic_math_functions.h
new file mode 100644
index 00000000000..1733cb50b46
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/basic_math_functions.h
@@ -0,0 +1,880 @@
+/******************************************************************************
+ * @file basic_math_functions.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _BASIC_MATH_FUNCTIONS_H_
+#define _BASIC_MATH_FUNCTIONS_H_
+
+#include "arm_math_types.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+
+/**
+ * @brief Floating-point vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_mult_f64(
+const float64_t * pSrcA,
+const float64_t * pSrcB,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+
+/**
+ * @brief Floating-point vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_f64(
+ const float64_t * pSrcA,
+ const float64_t * pSrcB,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_f64(
+ const float64_t * pSrcA,
+ const float64_t * pSrcB,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_f32(
+ const float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_f64(
+ const float64_t * pSrc,
+ float64_t scale,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q7(
+ const q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q15(
+ const q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_q31(
+ const q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q7(
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+
+/**
+ * @brief Floating-point vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_abs_f64(
+const float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+
+
+/**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+void arm_dot_prod_f64(
+const float64_t * pSrcA,
+const float64_t * pSrcB,
+ uint32_t blockSize,
+ float64_t * result);
+
+
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q7(
+ const q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q15(
+ const q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_shift_q31(
+ const q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_offset_f64(
+const float64_t * pSrc,
+ float64_t offset,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_f32(
+ const float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q7(
+ const q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q15(
+ const q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_q31(
+ const q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+
+/**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_negate_f64(
+const float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q7(
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Compute the logical bitwise AND of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_and_u16(
+ const uint16_t * pSrcA,
+ const uint16_t * pSrcB,
+ uint16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise AND of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_and_u32(
+ const uint32_t * pSrcA,
+ const uint32_t * pSrcB,
+ uint32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise AND of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_and_u8(
+ const uint8_t * pSrcA,
+ const uint8_t * pSrcB,
+ uint8_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise OR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_or_u16(
+ const uint16_t * pSrcA,
+ const uint16_t * pSrcB,
+ uint16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise OR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_or_u32(
+ const uint32_t * pSrcA,
+ const uint32_t * pSrcB,
+ uint32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise OR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_or_u8(
+ const uint8_t * pSrcA,
+ const uint8_t * pSrcB,
+ uint8_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise NOT of a fixed-point vector.
+ * @param[in] pSrc points to input vector
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_not_u16(
+ const uint16_t * pSrc,
+ uint16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise NOT of a fixed-point vector.
+ * @param[in] pSrc points to input vector
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_not_u32(
+ const uint32_t * pSrc,
+ uint32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise NOT of a fixed-point vector.
+ * @param[in] pSrc points to input vector
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_not_u8(
+ const uint8_t * pSrc,
+ uint8_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Compute the logical bitwise XOR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_xor_u16(
+ const uint16_t * pSrcA,
+ const uint16_t * pSrcB,
+ uint16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise XOR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_xor_u32(
+ const uint32_t * pSrcA,
+ const uint32_t * pSrcB,
+ uint32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Compute the logical bitwise XOR of two fixed-point vectors.
+ * @param[in] pSrcA points to input vector A
+ * @param[in] pSrcB points to input vector B
+ * @param[out] pDst points to output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_xor_u8(
+ const uint8_t * pSrcA,
+ const uint8_t * pSrcB,
+ uint8_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ @brief Elementwise floating-point clipping
+ @param[in] pSrc points to input values
+ @param[out] pDst points to output clipped values
+ @param[in] low lower bound
+ @param[in] high higher bound
+ @param[in] numSamples number of samples to clip
+ @return none
+ */
+
+void arm_clip_f32(const float32_t * pSrc,
+ float32_t * pDst,
+ float32_t low,
+ float32_t high,
+ uint32_t numSamples);
+
+ /**
+ @brief Elementwise fixed-point clipping
+ @param[in] pSrc points to input values
+ @param[out] pDst points to output clipped values
+ @param[in] low lower bound
+ @param[in] high higher bound
+ @param[in] numSamples number of samples to clip
+ @return none
+ */
+
+void arm_clip_q31(const q31_t * pSrc,
+ q31_t * pDst,
+ q31_t low,
+ q31_t high,
+ uint32_t numSamples);
+
+ /**
+ @brief Elementwise fixed-point clipping
+ @param[in] pSrc points to input values
+ @param[out] pDst points to output clipped values
+ @param[in] low lower bound
+ @param[in] high higher bound
+ @param[in] numSamples number of samples to clip
+ @return none
+ */
+
+void arm_clip_q15(const q15_t * pSrc,
+ q15_t * pDst,
+ q15_t low,
+ q15_t high,
+ uint32_t numSamples);
+
+ /**
+ @brief Elementwise fixed-point clipping
+ @param[in] pSrc points to input values
+ @param[out] pDst points to output clipped values
+ @param[in] low lower bound
+ @param[in] high higher bound
+ @param[in] numSamples number of samples to clip
+ @return none
+ */
+
+void arm_clip_q7(const q7_t * pSrc,
+ q7_t * pDst,
+ q7_t low,
+ q7_t high,
+ uint32_t numSamples);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _BASIC_MATH_FUNCTIONS_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/basic_math_functions_f16.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/basic_math_functions_f16.h
new file mode 100644
index 00000000000..9389e2aeac7
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/basic_math_functions_f16.h
@@ -0,0 +1,168 @@
+/******************************************************************************
+ * @file basic_math_functions_f16.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _BASIC_MATH_FUNCTIONS_F16_H_
+#define _BASIC_MATH_FUNCTIONS_F16_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "arm_math_types_f16.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+
+
+#if defined(ARM_FLOAT16_SUPPORTED)
+
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_add_f16(
+ const float16_t * pSrcA,
+ const float16_t * pSrcB,
+ float16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_sub_f16(
+ const float16_t * pSrcA,
+ const float16_t * pSrcB,
+ float16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_scale_f16(
+ const float16_t * pSrc,
+ float16_t scale,
+ float16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_abs_f16(
+ const float16_t * pSrc,
+ float16_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_offset_f16(
+ const float16_t * pSrc,
+ float16_t offset,
+ float16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+ void arm_dot_prod_f16(
+ const float16_t * pSrcA,
+ const float16_t * pSrcB,
+ uint32_t blockSize,
+ float16_t * result);
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+ void arm_mult_f16(
+ const float16_t * pSrcA,
+ const float16_t * pSrcB,
+ float16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+ void arm_negate_f16(
+ const float16_t * pSrc,
+ float16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ @brief Elementwise floating-point clipping
+ @param[in] pSrc points to input values
+ @param[out] pDst points to output clipped values
+ @param[in] low lower bound
+ @param[in] high higher bound
+ @param[in] numSamples number of samples to clip
+ @return none
+ */
+
+void arm_clip_f16(const float16_t * pSrc,
+ float16_t * pDst,
+ float16_t low,
+ float16_t high,
+ uint32_t numSamples);
+
+#endif /* defined(ARM_FLOAT16_SUPPORTED)*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _BASIC_MATH_FUNCTIONS_F16_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/bayes_functions.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/bayes_functions.h
new file mode 100644
index 00000000000..de94f36f675
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/bayes_functions.h
@@ -0,0 +1,89 @@
+/******************************************************************************
+ * @file bayes_functions.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _BAYES_FUNCTIONS_H_
+#define _BAYES_FUNCTIONS_H_
+
+#include "arm_math_types.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+
+#include "dsp/statistics_functions.h"
+
+/**
+ * @defgroup groupBayes Bayesian estimators
+ *
+ * Implement the naive gaussian Bayes estimator.
+ * The training must be done from scikit-learn.
+ *
+ * The parameters can be easily
+ * generated from the scikit-learn object. Some examples are given in
+ * DSP/Testing/PatternGeneration/Bayes.py
+ */
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * @brief Instance structure for Naive Gaussian Bayesian estimator.
+ */
+typedef struct
+{
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ uint32_t numberOfClasses; /**< Number of different classes */
+ const float32_t *theta; /**< Mean values for the Gaussians */
+ const float32_t *sigma; /**< Variances for the Gaussians */
+ const float32_t *classPriors; /**< Class prior probabilities */
+ float32_t epsilon; /**< Additive value to variances */
+} arm_gaussian_naive_bayes_instance_f32;
+
+/**
+ * @brief Naive Gaussian Bayesian Estimator
+ *
+ * @param[in] S points to a naive bayes instance structure
+ * @param[in] in points to the elements of the input vector.
+ * @param[out] *pOutputProbabilities points to a buffer of length numberOfClasses containing estimated probabilities
+ * @param[out] *pBufferB points to a temporary buffer of length numberOfClasses
+ * @return The predicted class
+ *
+ */
+
+
+uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S,
+ const float32_t * in,
+ float32_t *pOutputProbabilities,
+ float32_t *pBufferB);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _BAYES_FUNCTIONS_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/bayes_functions_f16.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/bayes_functions_f16.h
new file mode 100644
index 00000000000..97cb06a0dbd
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/bayes_functions_f16.h
@@ -0,0 +1,80 @@
+/******************************************************************************
+ * @file bayes_functions_f16.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _BAYES_FUNCTIONS_F16_H_
+#define _BAYES_FUNCTIONS_F16_H_
+
+#include "arm_math_types_f16.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+
+#include "dsp/statistics_functions_f16.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#if defined(ARM_FLOAT16_SUPPORTED)
+
+/**
+ * @brief Instance structure for Naive Gaussian Bayesian estimator.
+ */
+typedef struct
+{
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ uint32_t numberOfClasses; /**< Number of different classes */
+ const float16_t *theta; /**< Mean values for the Gaussians */
+ const float16_t *sigma; /**< Variances for the Gaussians */
+ const float16_t *classPriors; /**< Class prior probabilities */
+ float16_t epsilon; /**< Additive value to variances */
+} arm_gaussian_naive_bayes_instance_f16;
+
+/**
+ * @brief Naive Gaussian Bayesian Estimator
+ *
+ * @param[in] S points to a naive bayes instance structure
+ * @param[in] in points to the elements of the input vector.
+ * @param[out] *pOutputProbabilities points to a buffer of length numberOfClasses containing estimated probabilities
+ * @param[out] *pBufferB points to a temporary buffer of length numberOfClasses
+ * @return The predicted class
+ *
+ */
+
+
+uint32_t arm_gaussian_naive_bayes_predict_f16(const arm_gaussian_naive_bayes_instance_f16 *S,
+ const float16_t * in,
+ float16_t *pOutputProbabilities,
+ float16_t *pBufferB);
+
+#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _BAYES_FUNCTIONS_F16_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/complex_math_functions.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/complex_math_functions.h
new file mode 100644
index 00000000000..871c0020d7f
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/complex_math_functions.h
@@ -0,0 +1,345 @@
+/******************************************************************************
+ * @file complex_math_functions.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _COMPLEX_MATH_FUNCTIONS_H_
+#define _COMPLEX_MATH_FUNCTIONS_H_
+
+#include "arm_math_types.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+#include "dsp/fast_math_functions.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_f64(
+ const float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Floating-point complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Floating-point complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_f64(
+ const float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_fast_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q15(
+ const q15_t * pSrcCmplx,
+ const q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_q31(
+ const q31_t * pSrcCmplx,
+ const q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_f32(
+ const float32_t * pSrcCmplx,
+ const float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+
+/**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void arm_cmplx_mult_cmplx_f64(
+const float64_t * pSrcA,
+const float64_t * pSrcB,
+ float64_t * pDst,
+ uint32_t numSamples);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _COMPLEX_MATH_FUNCTIONS_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/complex_math_functions_f16.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/complex_math_functions_f16.h
new file mode 100644
index 00000000000..941fbaf7da8
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/complex_math_functions_f16.h
@@ -0,0 +1,123 @@
+/******************************************************************************
+ * @file complex_math_functions_f16.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _COMPLEX_MATH_FUNCTIONS_F16_H_
+#define _COMPLEX_MATH_FUNCTIONS_F16_H_
+
+#include "arm_math_types_f16.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+#include "dsp/fast_math_functions_f16.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#if defined(ARM_FLOAT16_SUPPORTED)
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_conj_f16(
+ const float16_t * pSrc,
+ float16_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_squared_f16(
+ const float16_t * pSrc,
+ float16_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+ void arm_cmplx_mag_f16(
+ const float16_t * pSrc,
+ float16_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+ void arm_cmplx_dot_prod_f16(
+ const float16_t * pSrcA,
+ const float16_t * pSrcB,
+ uint32_t numSamples,
+ float16_t * realResult,
+ float16_t * imagResult);
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+ void arm_cmplx_mult_real_f16(
+ const float16_t * pSrcCmplx,
+ const float16_t * pSrcReal,
+ float16_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+ void arm_cmplx_mult_cmplx_f16(
+ const float16_t * pSrcA,
+ const float16_t * pSrcB,
+ float16_t * pDst,
+ uint32_t numSamples);
+
+#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _COMPLEX_MATH_FUNCTIONS_F16_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/controller_functions.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/controller_functions.h
new file mode 100644
index 00000000000..97f6288ba47
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/controller_functions.h
@@ -0,0 +1,791 @@
+/******************************************************************************
+ * @file controller_functions.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _CONTROLLER_FUNCTIONS_H_
+#define _CONTROLLER_FUNCTIONS_H_
+
+#include "arm_math_types.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+
+#define CONTROLLER_Q31_SHIFT (32 - 9)
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @addtogroup SinCos
+ * @{
+ */
+
+/**
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cos output.
+ */
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal);
+
+
+ /**
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cosine output.
+ */
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+ /**
+ * @} end of SinCos group
+ */
+
+ /**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * S points to an instance of the PID control data structure. in
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ *
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd
+ *
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#if !defined (ARM_MATH_DSP)
+ q15_t A1; /**< The derived gain A1 = -Kp - 2Kd */
+ q15_t A2; /**< The derived gain A1 = Kd. */
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the q15 PID Control structure
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return processed output sample.
+ */
+ __STATIC_FORCEINLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+ {
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+/**
+ @brief Process function for the Q31 PID Control.
+ @param[in,out] S points to an instance of the Q31 PID Control structure
+ @param[in] in input sample to process
+ @return processed output sample.
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using an internal 64-bit accumulator.
+ The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ Thus, if the accumulator result overflows it wraps around rather than clip.
+ In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+__STATIC_FORCEINLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+ {
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31U);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+
+/**
+ @brief Process function for the Q15 PID Control.
+ @param[in,out] S points to an instance of the Q15 PID Control structure
+ @param[in] in input sample to process
+ @return processed output sample.
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using a 64-bit internal accumulator.
+ Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+__STATIC_FORCEINLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+ {
+ q63_t acc;
+ q15_t out;
+
+#if defined (ARM_MATH_DSP)
+ /* Implementation of PID controller */
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc);
+#else
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((q31_t)(acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+ }
+
+ /**
+ * @} end of PID group
+ */
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where Ialpha and Ibeta are the stator vector components,
+ * pId and pIq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+ __STATIC_FORCEINLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+ }
+
+
+/**
+ @brief Park transform for Q31 version
+ @param[in] Ialpha input two-phase vector coordinate alpha
+ @param[in] Ibeta input two-phase vector coordinate beta
+ @param[out] pId points to output rotor reference frame d
+ @param[out] pIq points to output rotor reference frame q
+ @param[in] sinVal sine value of rotation angle theta
+ @param[in] cosVal cosine value of rotation angle theta
+ @return none
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+__STATIC_FORCEINLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where pIalpha and pIbeta are the stator vector components,
+ * Id and Iq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none
+ */
+ __STATIC_FORCEINLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+ }
+
+
+/**
+ @brief Inverse Park transform for Q31 version
+ @param[in] Id input coordinate of rotor reference frame d
+ @param[in] Iq input coordinate of rotor reference frame q
+ @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ @param[in] sinVal sine value of rotation angle theta
+ @param[in] cosVal cosine value of rotation angle theta
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ There is saturation on the addition, hence there is no risk of overflow.
+ */
+__STATIC_FORCEINLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+/**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents
+ * in the two-phase orthogonal stator axis Ialpha and Ibeta.
+ * When Ialpha is superposed with Ia as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta
+ * can be calculated using only Ia and Ib.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where Ia and Ib are the instantaneous stator phases and
+ * pIalpha and pIbeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none
+ */
+ __STATIC_FORCEINLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta = (0.57735026919f * Ia + 1.15470053838f * Ib);
+ }
+
+
+/**
+ @brief Clarke transform for Q31 version
+ @param[in] Ia input three-phase coordinate a
+ @param[in] Ib input three-phase coordinate b
+ @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ @return none
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ There is saturation on the addition, hence there is no risk of overflow.
+ */
+__STATIC_FORCEINLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where pIa and pIb are the instantaneous stator phases and
+ * Ialpha and Ibeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate a
+ * @param[out] pIb points to output three-phase coordinate b
+ * @return none
+ */
+ __STATIC_FORCEINLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+ }
+
+
+/**
+ @brief Inverse Clarke transform for Q31 version
+ @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ @param[in] Ibeta input two-phase orthogonal vector axis beta
+ @param[out] pIa points to output three-phase coordinate a
+ @param[out] pIb points to output three-phase coordinate b
+ @return none
+
+ \par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+__STATIC_FORCEINLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _CONTROLLER_FUNCTIONS_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/controller_functions_f16.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/controller_functions_f16.h
new file mode 100644
index 00000000000..549de85f2af
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/controller_functions_f16.h
@@ -0,0 +1,41 @@
+/******************************************************************************
+ * @file controller_functions_f16.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _CONTROLLER_FUNCTIONS_F16_H_
+#define _CONTROLLER_FUNCTIONS_F16_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#if defined(ARM_FLOAT16_SUPPORTED)
+#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _CONTROLLER_FUNCTIONS_F16_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/distance_functions.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/distance_functions.h
new file mode 100644
index 00000000000..62136803a7e
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/distance_functions.h
@@ -0,0 +1,341 @@
+/******************************************************************************
+ * @file distance_functions.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _DISTANCE_FUNCTIONS_H_
+#define _DISTANCE_FUNCTIONS_H_
+
+#include "arm_math_types.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+
+#include "dsp/statistics_functions.h"
+#include "dsp/basic_math_functions.h"
+#include "dsp/fast_math_functions.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/**
+ * @defgroup groupDistance Distance functions
+ *
+ * Distance functions for use with clustering algorithms.
+ * There are distance functions for float vectors and boolean vectors.
+ *
+ */
+
+/* 6.14 bug */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) && (__ARMCC_VERSION < 6150001)
+
+__attribute__((weak)) float __powisf2(float a, int b);
+
+#endif
+
+/**
+ * @brief Euclidean distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Euclidean distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+float64_t arm_euclidean_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Bray-Curtis distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Canberra distance between two vectors
+ *
+ * This function may divide by zero when samples pA[i] and pB[i] are both zero.
+ * The result of the computation will be correct. So the division per zero may be
+ * ignored.
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+
+/**
+ * @brief Chebyshev distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+
+/**
+ * @brief Chebyshev distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float64_t arm_chebyshev_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize);
+
+
+/**
+ * @brief Cityblock (Manhattan) distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Cityblock (Manhattan) distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float64_t arm_cityblock_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Correlation distance between two vectors
+ *
+ * The input vectors are modified in place !
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float32_t arm_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Cosine distance between two vectors
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+float32_t arm_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Cosine distance between two vectors
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+float64_t arm_cosine_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Jensen-Shannon distance between two vectors
+ *
+ * This function is assuming that elements of second vector are > 0
+ * and 0 only when the corresponding element of first vector is 0.
+ * Otherwise the result of the computation does not make sense
+ * and for speed reasons, the cases returning NaN or Infinity are not
+ * managed.
+ *
+ * When the function is computing x log (x / y) with x 0 and y 0,
+ * it will compute the right value (0) but a division per zero will occur
+ * and shoudl be ignored in client code.
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB,uint32_t blockSize);
+
+/**
+ * @brief Minkowski distance between two vectors
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] n Norm order (>= 2)
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+
+
+float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize);
+
+/**
+ * @brief Dice distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] order Distance order
+ * @param[in] blockSize Number of samples
+ * @return distance
+ *
+ */
+
+
+float32_t arm_dice_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Hamming distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_hamming_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Jaccard distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_jaccard_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Kulsinski distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_kulsinski_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Roger Stanimoto distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Russell-Rao distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_russellrao_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Sokal-Michener distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Sokal-Sneath distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_sokalsneath_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+/**
+ * @brief Yule distance between two vectors
+ *
+ * @param[in] pA First vector of packed booleans
+ * @param[in] pB Second vector of packed booleans
+ * @param[in] numberOfBools Number of booleans
+ * @return distance
+ *
+ */
+
+float32_t arm_yule_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _DISTANCE_FUNCTIONS_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/distance_functions_f16.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/distance_functions_f16.h
new file mode 100644
index 00000000000..a454a701acc
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/distance_functions_f16.h
@@ -0,0 +1,180 @@
+/******************************************************************************
+ * @file distance_functions_f16.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _DISTANCE_FUNCTIONS_F16_H_
+#define _DISTANCE_FUNCTIONS_F16_H_
+
+#include "arm_math_types_f16.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+
+/* 6.14 bug */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) && (__ARMCC_VERSION < 6150001)
+/* Defined in minkowski_f32 */
+__attribute__((weak)) float __powisf2(float a, int b);
+#endif
+
+#include "dsp/statistics_functions_f16.h"
+#include "dsp/basic_math_functions_f16.h"
+
+#include "dsp/fast_math_functions_f16.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#if defined(ARM_FLOAT16_SUPPORTED)
+
+/**
+ * @brief Euclidean distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+float16_t arm_euclidean_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Bray-Curtis distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float16_t arm_braycurtis_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Canberra distance between two vectors
+ *
+ * This function may divide by zero when samples pA[i] and pB[i] are both zero.
+ * The result of the computation will be correct. So the division per zero may be
+ * ignored.
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float16_t arm_canberra_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize);
+
+
+/**
+ * @brief Chebyshev distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float16_t arm_chebyshev_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize);
+
+
+/**
+ * @brief Cityblock (Manhattan) distance between two vectors
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float16_t arm_cityblock_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Correlation distance between two vectors
+ *
+ * The input vectors are modified in place !
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+float16_t arm_correlation_distance_f16(float16_t *pA,float16_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Cosine distance between two vectors
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+float16_t arm_cosine_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize);
+
+/**
+ * @brief Jensen-Shannon distance between two vectors
+ *
+ * This function is assuming that elements of second vector are > 0
+ * and 0 only when the corresponding element of first vector is 0.
+ * Otherwise the result of the computation does not make sense
+ * and for speed reasons, the cases returning NaN or Infinity are not
+ * managed.
+ *
+ * When the function is computing x log (x / y) with x 0 and y 0,
+ * it will compute the right value (0) but a division per zero will occur
+ * and shoudl be ignored in client code.
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+float16_t arm_jensenshannon_distance_f16(const float16_t *pA,const float16_t *pB,uint32_t blockSize);
+
+/**
+ * @brief Minkowski distance between two vectors
+ *
+ * @param[in] pA First vector
+ * @param[in] pB Second vector
+ * @param[in] n Norm order (>= 2)
+ * @param[in] blockSize vector length
+ * @return distance
+ *
+ */
+
+
+
+float16_t arm_minkowski_distance_f16(const float16_t *pA,const float16_t *pB, int32_t order, uint32_t blockSize);
+
+
+#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _DISTANCE_FUNCTIONS_F16_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/fast_math_functions.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/fast_math_functions.h
new file mode 100644
index 00000000000..dc3e4cac3a3
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/fast_math_functions.h
@@ -0,0 +1,389 @@
+/******************************************************************************
+ * @file fast_math_functions.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _FAST_MATH_FUNCTIONS_H_
+#define _FAST_MATH_FUNCTIONS_H_
+
+#include "arm_math_types.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+
+#include "dsp/basic_math_functions.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define FAST_MATH_TABLE_SIZE 512
+#define FAST_MATH_Q31_SHIFT (32 - 10)
+#define FAST_MATH_Q15_SHIFT (16 - 10)
+
+#ifndef PI
+ #define PI 3.14159265358979f
+#endif
+
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+/**
+ @addtogroup sin
+ @{
+ */
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+ float32_t arm_sin_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q31_t arm_sin_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+ q15_t arm_sin_q15(
+ q15_t x);
+
+/**
+ @} end of sin group
+ */
+
+/**
+ @addtogroup cos
+ @{
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+ float32_t arm_cos_f32(
+ float32_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q31_t arm_cos_q31(
+ q31_t x);
+
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+ q15_t arm_cos_q15(
+ q15_t x);
+
+/**
+ @} end of cos group
+ */
+
+
+/**
+ @brief Floating-point vector of log values.
+ @param[in] pSrc points to the input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+ void arm_vlog_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+
+/**
+ @brief Floating-point vector of log values.
+ @param[in] pSrc points to the input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+ void arm_vlog_f64(
+ const float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief q31 vector of log values.
+ * @param[in] pSrc points to the input vector in q31
+ * @param[out] pDst points to the output vector in q5.26
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_vlog_q31(const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief q15 vector of log values.
+ * @param[in] pSrc points to the input vector in q15
+ * @param[out] pDst points to the output vector in q4.11
+ * @param[in] blockSize number of samples in each vector
+ * @return none
+ */
+ void arm_vlog_q15(const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+/**
+ @brief Floating-point vector of exp values.
+ @param[in] pSrc points to the input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+ void arm_vexp_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+
+/**
+ @brief Floating-point vector of exp values.
+ @param[in] pSrc points to the input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+ void arm_vexp_f64(
+ const float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ *
+ * x1 = x0 - f(x0)/f'(x0)
+ *
+ * where x1 is the current estimate,
+ * x0 is the previous estimate, and
+ * f'(x0) is the derivative of f() evaluated at x0.
+ * For the square root function, the algorithm reduces to:
+ *
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ *
+ */
+
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+/**
+ @brief Floating-point square root function.
+ @param[in] in input value
+ @param[out] pOut square root of input value
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : input value is positive
+ - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
+ */
+__STATIC_FORCEINLINE arm_status arm_sqrt_f32(
+ const float32_t in,
+ float32_t * pOut)
+ {
+ if (in >= 0.0f)
+ {
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ *pOut = __sqrtf(in);
+ #else
+ *pOut = sqrtf(in);
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+ #else
+ *pOut = sqrtf(in);
+ #endif
+
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+ }
+
+
+/**
+ @brief Q31 square root function.
+ @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF
+ @param[out] pOut points to square root of input value
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : input value is positive
+ - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
+ */
+arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+
+/**
+ @brief Q15 square root function.
+ @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF
+ @param[out] pOut points to square root of input value
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : input value is positive
+ - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
+ */
+arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+
+
+ /**
+ * @} end of SQRT group
+ */
+
+ /**
+ @brief Fixed point division
+ @param[in] numerator Numerator
+ @param[in] denominator Denominator
+ @param[out] quotient Quotient value normalized between -1.0 and 1.0
+ @param[out] shift Shift left value to get the unnormalized quotient
+ @return error status
+
+ When dividing by 0, an error ARM_MATH_NANINF is returned. And the quotient is forced
+ to the saturated negative or positive value.
+ */
+
+arm_status arm_divide_q15(q15_t numerator,
+ q15_t denominator,
+ q15_t *quotient,
+ int16_t *shift);
+
+ /**
+ @brief Fixed point division
+ @param[in] numerator Numerator
+ @param[in] denominator Denominator
+ @param[out] quotient Quotient value normalized between -1.0 and 1.0
+ @param[out] shift Shift left value to get the unnormalized quotient
+ @return error status
+
+ When dividing by 0, an error ARM_MATH_NANINF is returned. And the quotient is forced
+ to the saturated negative or positive value.
+ */
+
+arm_status arm_divide_q31(q31_t numerator,
+ q31_t denominator,
+ q31_t *quotient,
+ int16_t *shift);
+
+
+
+ /**
+ @brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant.
+ @param[in] y y coordinate
+ @param[in] x x coordinate
+ @param[out] result Result
+ @return error status.
+ */
+ arm_status arm_atan2_f32(float32_t y,float32_t x,float32_t *result);
+
+
+ /**
+ @brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant.
+ @param[in] y y coordinate
+ @param[in] x x coordinate
+ @param[out] result Result in Q2.29
+ @return error status.
+ */
+ arm_status arm_atan2_q31(q31_t y,q31_t x,q31_t *result);
+
+ /**
+ @brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant.
+ @param[in] y y coordinate
+ @param[in] x x coordinate
+ @param[out] result Result in Q2.13
+ @return error status.
+ */
+ arm_status arm_atan2_q15(q15_t y,q15_t x,q15_t *result);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _FAST_MATH_FUNCTIONS_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/fast_math_functions_f16.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/fast_math_functions_f16.h
new file mode 100644
index 00000000000..02d8b6754ea
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/fast_math_functions_f16.h
@@ -0,0 +1,125 @@
+/******************************************************************************
+ * @file fast_math_functions_f16.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _FAST_MATH_FUNCTIONS_F16_H_
+#define _FAST_MATH_FUNCTIONS_F16_H_
+
+#include "arm_math_types_f16.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+
+/* For sqrt_f32 */
+#include "dsp/fast_math_functions.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#if defined(ARM_FLOAT16_SUPPORTED)
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+/**
+ @brief Floating-point square root function.
+ @param[in] in input value
+ @param[out] pOut square root of input value
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : input value is positive
+ - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
+ */
+__STATIC_FORCEINLINE arm_status arm_sqrt_f16(
+ float16_t in,
+ float16_t * pOut)
+ {
+ float32_t r;
+ arm_status status;
+ status=arm_sqrt_f32((float32_t)in,&r);
+ *pOut=(float16_t)r;
+ return(status);
+ }
+
+
+/**
+ @} end of SQRT group
+ */
+
+/**
+ @brief Floating-point vector of log values.
+ @param[in] pSrc points to the input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+ void arm_vlog_f16(
+ const float16_t * pSrc,
+ float16_t * pDst,
+ uint32_t blockSize);
+
+/**
+ @brief Floating-point vector of exp values.
+ @param[in] pSrc points to the input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+ void arm_vexp_f16(
+ const float16_t * pSrc,
+ float16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ @brief Floating-point vector of inverse values.
+ @param[in] pSrc points to the input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+ void arm_vinverse_f16(
+ const float16_t * pSrc,
+ float16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ @brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant.
+ @param[in] y y coordinate
+ @param[in] x x coordinate
+ @param[out] result Result
+ @return error status.
+ */
+ arm_status arm_atan2_f16(float16_t y,float16_t x,float16_t *result);
+
+#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _FAST_MATH_FUNCTIONS_F16_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/filtering_functions.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/filtering_functions.h
new file mode 100644
index 00000000000..b53196c01f8
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/filtering_functions.h
@@ -0,0 +1,2529 @@
+/******************************************************************************
+ * @file filtering_functions.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _FILTERING_FUNCTIONS_H_
+#define _FILTERING_FUNCTIONS_H_
+
+#include "arm_math_types.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+
+#include "dsp/support_functions.h"
+#include "dsp/fast_math_functions.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+
+#define DELTA_Q31 ((q31_t)(0x100))
+#define DELTA_Q15 ((q15_t)0x5)
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float64_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ const float64_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f64;
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] S points to an instance of the Q7 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ *
+ * For the MVE version, the coefficient length must be a multiple of 16.
+ * You can pad with zeros if you have less coefficients.
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ const q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] S points to an instance of the Q15 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter (fast version).
+ * @param[in] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns either
+ * ARM_MATH_SUCCESS if initialization was successful or
+ * ARM_MATH_ARGUMENT_ERROR if numTaps is not a supported value.
+ *
+ * For the MVE version, the coefficient length must be a multiple of 8.
+ * You can pad with zeros if you have less coefficients.
+ *
+ */
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter (fast version).
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ *
+ * For the MVE version, the coefficient length must be a multiple of 4.
+ * You can pad with zeros if you have less coefficients.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] S points to an instance of the floating-point FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] S points to an instance of the floating-point FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_f64(
+ const arm_fir_instance_f64 * S,
+ const float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_f64(
+ arm_fir_instance_f64 * S,
+ uint16_t numTaps,
+ const float64_t * pCoeffs,
+ float64_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ const q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q15;
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ const q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ const float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_casd_df1_inst_f32;
+
+#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
+ /**
+ * @brief Instance structure for the modified Biquad coefs required by vectorized code.
+ */
+ typedef struct
+ {
+ float32_t coeffs[8][4]; /**< Points to the array of modified coefficients. The array is of length 32. There is one per stage */
+ } arm_biquad_mod_coef_f32;
+#endif
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pCoeffsMod points to the modified filter coefficients (only MVE version).
+ * @param[in] pState points to the state buffer.
+ */
+#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
+ void arm_biquad_cascade_df1_mve_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ arm_biquad_mod_coef_f32 * pCoeffsMod,
+ float32_t * pState);
+#endif
+
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_f32(
+ const float32_t * pSrcA,
+ uint32_t srcALen,
+ const float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+ void arm_conv_fast_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_fast_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_conv_opt_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+ void arm_conv_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_f32(
+ const float32_t * pSrcA,
+ uint32_t srcALen,
+ const float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_fast_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_opt_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+ arm_status arm_conv_partial_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q31;
+
+/**
+ @brief Instance structure for floating-point FIR decimator.
+ */
+typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_f32;
+
+
+/**
+ @brief Processing function for floating-point FIR decimator.
+ @param[in] S points to an instance of the floating-point FIR decimator structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ */
+void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ @brief Initialization function for the floating-point FIR decimator.
+ @param[in,out] S points to an instance of the floating-point FIR decimator structure
+ @param[in] numTaps number of coefficients in the filter
+ @param[in] M decimation factor
+ @param[in] pCoeffs points to the filter coefficients
+ @param[in] pState points to the state buffer
+ @param[in] blockSize number of input samples to process per call
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M
+ */
+arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_decimate_fast_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ const q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ */
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ const q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ const float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f64;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64 * S,
+ const float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+#if defined(ARM_MATH_NEON)
+/**
+ @brief Compute new coefficient arrays for use in vectorized filter (Neon only).
+ @param[in] numStages number of 2nd order stages in the filter.
+ @param[in] pCoeffs points to the original filter coefficients.
+ @param[in] pComputedCoeffs points to the new computed coefficients for the vectorized version.
+ @return none
+*/
+void arm_biquad_cascade_df2T_compute_coefs_f32(
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pComputedCoeffs);
+#endif
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64 * S,
+ uint8_t numStages,
+ const float64_t * pCoeffs,
+ float64_t * pState);
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ const q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ const q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ */
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ const q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ const q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_f32(
+ const float32_t * pSrcA,
+ uint32_t srcALen,
+ const float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_f64(
+ const float64_t * pSrcA,
+ uint32_t srcALen,
+ const float64_t * pSrcB,
+ uint32_t srcBLen,
+ float64_t * pDst);
+
+
+/**
+ @brief Correlation of Q15 sequences
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+*/
+void arm_correlate_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+/**
+ @brief Correlation of Q15 sequences.
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+/**
+ @brief Correlation of Q15 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ @return none
+ */
+void arm_correlate_fast_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+/**
+ @brief Correlation of Q15 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence.
+ @param[in] srcALen length of the first input sequence.
+ @param[in] pSrcB points to the second input sequence.
+ @param[in] srcBLen length of the second input sequence.
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+void arm_correlate_fast_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+/**
+ @brief Correlation of Q31 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_fast_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+ void arm_correlate_opt_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ const q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ const q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+
+
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+ __STATIC_FORCEINLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ __STATIC_FORCEINLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t rOffset;
+ int32_t* dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = dst_base + dst_length;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+ __STATIC_FORCEINLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ __STATIC_FORCEINLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset;
+ q15_t* dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = dst_base + dst_length;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+ __STATIC_FORCEINLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0U;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if (wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ __STATIC_FORCEINLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset;
+ q7_t* dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = dst_base + dst_length;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while (i > 0U)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if (dst == dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if (rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+/**
+ @brief Levinson Durbin
+ @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1)
+ @param[out] a autoregressive coefficients
+ @param[out] err prediction error (variance)
+ @param[in] nbCoefs number of autoregressive coefficients
+ @return none
+ */
+void arm_levinson_durbin_f32(const float32_t *phi,
+ float32_t *a,
+ float32_t *err,
+ int nbCoefs);
+
+
+/**
+ @brief Levinson Durbin
+ @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1)
+ @param[out] a autoregressive coefficients
+ @param[out] err prediction error (variance)
+ @param[in] nbCoefs number of autoregressive coefficients
+ @return none
+ */
+void arm_levinson_durbin_q31(const q31_t *phi,
+ q31_t *a,
+ q31_t *err,
+ int nbCoefs);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _FILTERING_FUNCTIONS_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/filtering_functions_f16.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/filtering_functions_f16.h
new file mode 100644
index 00000000000..b47adfa399d
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/filtering_functions_f16.h
@@ -0,0 +1,237 @@
+/******************************************************************************
+ * @file filtering_functions_f16.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _FILTERING_FUNCTIONS_F16_H_
+#define _FILTERING_FUNCTIONS_F16_H_
+
+#include "arm_math_types_f16.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#if defined(ARM_FLOAT16_SUPPORTED)
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float16_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ const float16_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f16;
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+ void arm_fir_init_f16(
+ arm_fir_instance_f16 * S,
+ uint16_t numTaps,
+ const float16_t * pCoeffs,
+ float16_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] S points to an instance of the floating-point FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_fir_f16(
+ const arm_fir_instance_f16 * S,
+ const float16_t * pSrc,
+ float16_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float16_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ const float16_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_casd_df1_inst_f16;
+
+#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
+ /**
+ * @brief Instance structure for the modified Biquad coefs required by vectorized code.
+ */
+ typedef struct
+ {
+ float16_t coeffs[12][8]; /**< Points to the array of modified coefficients. The array is of length 32. There is one per stage */
+ } arm_biquad_mod_coef_f16;
+#endif
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df1_f16(
+ const arm_biquad_casd_df1_inst_f16 * S,
+ const float16_t * pSrc,
+ float16_t * pDst,
+ uint32_t blockSize);
+
+#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
+ void arm_biquad_cascade_df1_mve_init_f16(
+ arm_biquad_casd_df1_inst_f16 * S,
+ uint8_t numStages,
+ const float16_t * pCoeffs,
+ arm_biquad_mod_coef_f16 * pCoeffsMod,
+ float16_t * pState);
+#endif
+
+ void arm_biquad_cascade_df1_init_f16(
+ arm_biquad_casd_df1_inst_f16 * S,
+ uint8_t numStages,
+ const float16_t * pCoeffs,
+ float16_t * pState);
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float16_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ const float16_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f16;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float16_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ const float16_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_stereo_df2T_instance_f16;
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_df2T_f16(
+ const arm_biquad_cascade_df2T_instance_f16 * S,
+ const float16_t * pSrc,
+ float16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_biquad_cascade_stereo_df2T_f16(
+ const arm_biquad_cascade_stereo_df2T_instance_f16 * S,
+ const float16_t * pSrc,
+ float16_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_df2T_init_f16(
+ arm_biquad_cascade_df2T_instance_f16 * S,
+ uint8_t numStages,
+ const float16_t * pCoeffs,
+ float16_t * pState);
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+ void arm_biquad_cascade_stereo_df2T_init_f16(
+ arm_biquad_cascade_stereo_df2T_instance_f16 * S,
+ uint8_t numStages,
+ const float16_t * pCoeffs,
+ float16_t * pState);
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+ void arm_correlate_f16(
+ const float16_t * pSrcA,
+ uint32_t srcALen,
+ const float16_t * pSrcB,
+ uint32_t srcBLen,
+ float16_t * pDst);
+
+
+/**
+ @brief Levinson Durbin
+ @param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1)
+ @param[out] a autoregressive coefficients
+ @param[out] err prediction error (variance)
+ @param[in] nbCoefs number of autoregressive coefficients
+ @return none
+ */
+void arm_levinson_durbin_f16(const float16_t *phi,
+ float16_t *a,
+ float16_t *err,
+ int nbCoefs);
+
+#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _FILTERING_FUNCTIONS_F16_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/interpolation_functions.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/interpolation_functions.h
new file mode 100644
index 00000000000..09d61086ec8
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/interpolation_functions.h
@@ -0,0 +1,319 @@
+/******************************************************************************
+ * @file interpolation_functions.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _INTERPOLATION_FUNCTIONS_H_
+#define _INTERPOLATION_FUNCTIONS_H_
+
+#include "arm_math_types.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Struct for specifying cubic spline type
+ */
+ typedef enum
+ {
+ ARM_SPLINE_NATURAL = 0, /**< Natural spline */
+ ARM_SPLINE_PARABOLIC_RUNOUT = 1 /**< Parabolic runout spline */
+ } arm_spline_type;
+
+ /**
+ * @brief Instance structure for the floating-point cubic spline interpolation.
+ */
+ typedef struct
+ {
+ arm_spline_type type; /**< Type (boundary conditions) */
+ const float32_t * x; /**< x values */
+ const float32_t * y; /**< y values */
+ uint32_t n_x; /**< Number of known data points */
+ float32_t * coeffs; /**< Coefficients buffer (b,c, and d) */
+ } arm_spline_instance_f32;
+
+
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @addtogroup SplineInterpolate
+ * @{
+ */
+
+
+ /**
+ * @brief Processing function for the floating-point cubic spline interpolation.
+ * @param[in] S points to an instance of the floating-point spline structure.
+ * @param[in] xq points to the x values ot the interpolated data points.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples of output data.
+ */
+ void arm_spline_f32(
+ arm_spline_instance_f32 * S,
+ const float32_t * xq,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point cubic spline interpolation.
+ * @param[in,out] S points to an instance of the floating-point spline structure.
+ * @param[in] type type of cubic spline interpolation (boundary conditions)
+ * @param[in] x points to the x values of the known data points.
+ * @param[in] y points to the y values of the known data points.
+ * @param[in] n number of known data points.
+ * @param[in] coeffs coefficients array for b, c, and d
+ * @param[in] tempBuffer buffer array for internal computations
+ */
+ void arm_spline_init_f32(
+ arm_spline_instance_f32 * S,
+ arm_spline_type type,
+ const float32_t * x,
+ const float32_t * y,
+ uint32_t n,
+ float32_t * coeffs,
+ float32_t * tempBuffer);
+
+
+ /**
+ * @} end of SplineInterpolate group
+ */
+
+
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+ float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x);
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ q31_t arm_linear_interp_q31(
+ const q31_t * pYData,
+ q31_t x,
+ uint32_t nValues);
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+ q15_t arm_linear_interp_q15(
+ const q15_t * pYData,
+ q31_t x,
+ uint32_t nValues);
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+q7_t arm_linear_interp_q7(
+ const q7_t * pYData,
+ q31_t x,
+ uint32_t nValues);
+
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+
+ /**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+ float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y);
+
+ /**
+ * @brief Q31 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y);
+
+
+ /**
+ * @brief Q15 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y);
+
+ /**
+ * @brief Q7 bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+ q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y);
+ /**
+ * @} end of BilinearInterpolate group
+ */
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _INTERPOLATION_FUNCTIONS_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/interpolation_functions_f16.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/interpolation_functions_f16.h
new file mode 100644
index 00000000000..36996549bf3
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/interpolation_functions_f16.h
@@ -0,0 +1,107 @@
+/******************************************************************************
+ * @file interpolation_functions_f16.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _INTERPOLATION_FUNCTIONS_F16_H_
+#define _INTERPOLATION_FUNCTIONS_F16_H_
+
+#include "arm_math_types_f16.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#if defined(ARM_FLOAT16_SUPPORTED)
+
+typedef struct
+{
+ uint32_t nValues; /**< nValues */
+ float16_t x1; /**< x1 */
+ float16_t xSpacing; /**< xSpacing */
+ float16_t *pYData; /**< pointer to the table of Y values */
+} arm_linear_interp_instance_f16;
+
+/**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+typedef struct
+{
+ uint16_t numRows;/**< number of rows in the data table. */
+ uint16_t numCols;/**< number of columns in the data table. */
+ float16_t *pData; /**< points to the data table. */
+} arm_bilinear_interp_instance_f16;
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+ float16_t arm_linear_interp_f16(
+ arm_linear_interp_instance_f16 * S,
+ float16_t x);
+
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+/**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+ float16_t arm_bilinear_interp_f16(
+ const arm_bilinear_interp_instance_f16 * S,
+ float16_t X,
+ float16_t Y);
+
+
+ /**
+ * @} end of BilinearInterpolate group
+ */
+#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _INTERPOLATION_FUNCTIONS_F16_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/matrix_functions.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/matrix_functions.h
new file mode 100644
index 00000000000..f0a51f207d1
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/matrix_functions.h
@@ -0,0 +1,757 @@
+/******************************************************************************
+ * @file matrix_functions.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _MATRIX_FUNCTIONS_H_
+#define _MATRIX_FUNCTIONS_H_
+
+#include "arm_math_types.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows; // number of rows of the matrix.
+ * uint16_t numCols; // number of columns of the matrix.
+ * float32_t *pData; // points to the data of the matrix.
+ * } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data. The array is of size numRows X numCols
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ *
+ * pData[i*numCols + j]
+ *
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to \ref arm_mat_init_f32(), \ref arm_mat_init_q31() and \ref arm_mat_init_q15()
+ * for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ *
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns
+ * specifies the number of columns, and pData points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ *
+ * ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return
+ *
+ * ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ *
+ * ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return ARM_MATH_SUCCESS.
+ */
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float64_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f64;
+
+ /**
+ * @brief Instance structure for the Q7 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q7_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_q31;
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pScratch);
+
+ /**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+/**
+ * @brief Floating-point matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_f64(
+ const arm_matrix_instance_f64 * pSrc,
+ arm_matrix_instance_f64 * pDst);
+
+ /**
+ * @brief Floating-point complex matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q15 complex matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q7 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_q7(
+ const arm_matrix_instance_q7 * pSrc,
+ arm_matrix_instance_q7 * pDst);
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Q31 complex matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_f64(
+ const arm_matrix_instance_f64 * pSrcA,
+ const arm_matrix_instance_f64 * pSrcB,
+ arm_matrix_instance_f64 * pDst);
+
+ /**
+ * @brief Floating-point matrix and vector multiplication
+ * @param[in] pSrcMat points to the input matrix structure
+ * @param[in] pVec points to vector
+ * @param[out] pDst points to output vector
+ */
+void arm_mat_vec_mult_f32(
+ const arm_matrix_instance_f32 *pSrcMat,
+ const float32_t *pVec,
+ float32_t *pDst);
+
+ /**
+ * @brief Q7 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_q7(
+ const arm_matrix_instance_q7 * pSrcA,
+ const arm_matrix_instance_q7 * pSrcB,
+ arm_matrix_instance_q7 * pDst,
+ q7_t * pState);
+
+ /**
+ * @brief Q7 matrix and vector multiplication
+ * @param[in] pSrcMat points to the input matrix structure
+ * @param[in] pVec points to vector
+ * @param[out] pDst points to output vector
+ */
+void arm_mat_vec_mult_q7(
+ const arm_matrix_instance_q7 *pSrcMat,
+ const q7_t *pVec,
+ q7_t *pDst);
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q15 matrix and vector multiplication
+ * @param[in] pSrcMat points to the input matrix structure
+ * @param[in] pVec points to vector
+ * @param[out] pDst points to output vector
+ */
+void arm_mat_vec_mult_q15(
+ const arm_matrix_instance_q15 *pSrcMat,
+ const q15_t *pVec,
+ q15_t *pDst);
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_opt_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst,
+ q31_t *pState);
+
+ /**
+ * @brief Q31 matrix and vector multiplication
+ * @param[in] pSrcMat points to the input matrix structure
+ * @param[in] pVec points to vector
+ * @param[out] pDst points to output vector
+ */
+void arm_mat_vec_mult_q31(
+ const arm_matrix_instance_q31 *pSrcMat,
+ const q31_t *pVec,
+ q31_t *pDst);
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_f64(
+ const arm_matrix_instance_f64 * pSrcA,
+ const arm_matrix_instance_f64 * pSrcB,
+ arm_matrix_instance_f64 * pDst);
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f64(
+ const arm_matrix_instance_f64 * src,
+ arm_matrix_instance_f64 * dst);
+
+ /**
+ * @brief Floating-point Cholesky decomposition of Symmetric Positive Definite Matrix.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE.
+ * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition.
+ * The decomposition is returning a lower triangular matrix.
+ */
+ arm_status arm_mat_cholesky_f64(
+ const arm_matrix_instance_f64 * src,
+ arm_matrix_instance_f64 * dst);
+
+ /**
+ * @brief Floating-point Cholesky decomposition of Symmetric Positive Definite Matrix.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE.
+ * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition.
+ * The decomposition is returning a lower triangular matrix.
+ */
+ arm_status arm_mat_cholesky_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+ /**
+ * @brief Solve UT . X = A where UT is an upper triangular matrix
+ * @param[in] ut The upper triangular matrix
+ * @param[in] a The matrix a
+ * @param[out] dst The solution X of UT . X = A
+ * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved.
+ */
+ arm_status arm_mat_solve_upper_triangular_f32(
+ const arm_matrix_instance_f32 * ut,
+ const arm_matrix_instance_f32 * a,
+ arm_matrix_instance_f32 * dst);
+
+ /**
+ * @brief Solve LT . X = A where LT is a lower triangular matrix
+ * @param[in] lt The lower triangular matrix
+ * @param[in] a The matrix a
+ * @param[out] dst The solution X of LT . X = A
+ * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved.
+ */
+ arm_status arm_mat_solve_lower_triangular_f32(
+ const arm_matrix_instance_f32 * lt,
+ const arm_matrix_instance_f32 * a,
+ arm_matrix_instance_f32 * dst);
+
+
+ /**
+ * @brief Solve UT . X = A where UT is an upper triangular matrix
+ * @param[in] ut The upper triangular matrix
+ * @param[in] a The matrix a
+ * @param[out] dst The solution X of UT . X = A
+ * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved.
+ */
+ arm_status arm_mat_solve_upper_triangular_f64(
+ const arm_matrix_instance_f64 * ut,
+ const arm_matrix_instance_f64 * a,
+ arm_matrix_instance_f64 * dst);
+
+ /**
+ * @brief Solve LT . X = A where LT is a lower triangular matrix
+ * @param[in] lt The lower triangular matrix
+ * @param[in] a The matrix a
+ * @param[out] dst The solution X of LT . X = A
+ * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved.
+ */
+ arm_status arm_mat_solve_lower_triangular_f64(
+ const arm_matrix_instance_f64 * lt,
+ const arm_matrix_instance_f64 * a,
+ arm_matrix_instance_f64 * dst);
+
+
+ /**
+ * @brief Floating-point LDL decomposition of Symmetric Positive Semi-Definite Matrix.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] l points to the instance of the output floating-point triangular matrix structure.
+ * @param[out] d points to the instance of the output floating-point diagonal matrix structure.
+ * @param[out] p points to the instance of the output floating-point permutation vector.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE.
+ * The decomposition is returning a lower triangular matrix.
+ */
+ arm_status arm_mat_ldlt_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * l,
+ arm_matrix_instance_f32 * d,
+ uint16_t * pp);
+
+ /**
+ * @brief Floating-point LDL decomposition of Symmetric Positive Semi-Definite Matrix.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] l points to the instance of the output floating-point triangular matrix structure.
+ * @param[out] d points to the instance of the output floating-point diagonal matrix structure.
+ * @param[out] p points to the instance of the output floating-point permutation vector.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE.
+ * The decomposition is returning a lower triangular matrix.
+ */
+ arm_status arm_mat_ldlt_f64(
+ const arm_matrix_instance_f64 * src,
+ arm_matrix_instance_f64 * l,
+ arm_matrix_instance_f64 * d,
+ uint16_t * pp);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _MATRIX_FUNCTIONS_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/matrix_functions_f16.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/matrix_functions_f16.h
new file mode 100644
index 00000000000..a7e618aa721
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/matrix_functions_f16.h
@@ -0,0 +1,221 @@
+/******************************************************************************
+ * @file matrix_functions_f16.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _MATRIX_FUNCTIONS_F16_H_
+#define _MATRIX_FUNCTIONS_F16_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+#include "arm_math_types_f16.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+
+#if defined(ARM_FLOAT16_SUPPORTED)
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float16_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f16;
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_add_f16(
+ const arm_matrix_instance_f16 * pSrcA,
+ const arm_matrix_instance_f16 * pSrcB,
+ arm_matrix_instance_f16 * pDst);
+
+ /**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_f16(
+ const arm_matrix_instance_f16 * pSrcA,
+ const arm_matrix_instance_f16 * pSrcB,
+ arm_matrix_instance_f16 * pDst);
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_f16(
+ const arm_matrix_instance_f16 * pSrc,
+ arm_matrix_instance_f16 * pDst);
+
+ /**
+ * @brief Floating-point complex matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_trans_f16(
+ const arm_matrix_instance_f16 * pSrc,
+ arm_matrix_instance_f16 * pDst);
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_f16(
+ const arm_matrix_instance_f16 * pSrcA,
+ const arm_matrix_instance_f16 * pSrcB,
+ arm_matrix_instance_f16 * pDst);
+ /**
+ * @brief Floating-point matrix and vector multiplication
+ * @param[in] pSrcMat points to the input matrix structure
+ * @param[in] pVec points to vector
+ * @param[out] pDst points to output vector
+ */
+void arm_mat_vec_mult_f16(
+ const arm_matrix_instance_f16 *pSrcMat,
+ const float16_t *pVec,
+ float16_t *pDst);
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_f16(
+ const arm_matrix_instance_f16 * pSrcA,
+ const arm_matrix_instance_f16 * pSrcB,
+ arm_matrix_instance_f16 * pDst);
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_f16(
+ const arm_matrix_instance_f16 * pSrc,
+ float16_t scale,
+ arm_matrix_instance_f16 * pDst);
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_f16(
+ arm_matrix_instance_f16 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float16_t * pData);
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+ arm_status arm_mat_inverse_f16(
+ const arm_matrix_instance_f16 * src,
+ arm_matrix_instance_f16 * dst);
+
+
+ /**
+ * @brief Floating-point Cholesky decomposition of Symmetric Positive Definite Matrix.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE.
+ * If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition.
+ * The decomposition is returning a lower triangular matrix.
+ */
+ arm_status arm_mat_cholesky_f16(
+ const arm_matrix_instance_f16 * src,
+ arm_matrix_instance_f16 * dst);
+
+ /**
+ * @brief Solve UT . X = A where UT is an upper triangular matrix
+ * @param[in] ut The upper triangular matrix
+ * @param[in] a The matrix a
+ * @param[out] dst The solution X of UT . X = A
+ * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved.
+ */
+ arm_status arm_mat_solve_upper_triangular_f16(
+ const arm_matrix_instance_f16 * ut,
+ const arm_matrix_instance_f16 * a,
+ arm_matrix_instance_f16 * dst);
+
+ /**
+ * @brief Solve LT . X = A where LT is a lower triangular matrix
+ * @param[in] lt The lower triangular matrix
+ * @param[in] a The matrix a
+ * @param[out] dst The solution X of LT . X = A
+ * @return The function returns ARM_MATH_SINGULAR, if the system can't be solved.
+ */
+ arm_status arm_mat_solve_lower_triangular_f16(
+ const arm_matrix_instance_f16 * lt,
+ const arm_matrix_instance_f16 * a,
+ arm_matrix_instance_f16 * dst);
+
+
+
+#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _MATRIX_FUNCTIONS_F16_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/none.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/none.h
new file mode 100644
index 00000000000..4bcb234cfa2
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/none.h
@@ -0,0 +1,576 @@
+/******************************************************************************
+ * @file none.h
+ * @brief Intrinsincs when no DSP extension available
+ * @version V1.9.0
+ * @date 20. July 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+
+Definitions in this file are allowing to reuse some versions of the
+CMSIS-DSP to build on a core (M0 for instance) or a host where
+DSP extension are not available.
+
+Ideally a pure C version should have been used instead.
+But those are not always available or use a restricted set
+of intrinsics.
+
+*/
+
+#ifndef _NONE_H_
+#define _NONE_H_
+
+#include "arm_math_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+
+/*
+
+Normally those kind of definitions are in a compiler file
+in Core or Core_A.
+
+But for MSVC compiler it is a bit special. The goal is very specific
+to CMSIS-DSP and only to allow the use of this library from other
+systems like Python or Matlab.
+
+MSVC is not going to be used to cross-compile to ARM. So, having a MSVC
+compiler file in Core or Core_A would not make sense.
+
+*/
+#if defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) || defined(__APPLE_CC__)
+ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data)
+ {
+ if (data == 0U) { return 32U; }
+
+ uint32_t count = 0U;
+ uint32_t mask = 0x80000000U;
+
+ while ((data & mask) == 0U)
+ {
+ count += 1U;
+ mask = mask >> 1U;
+ }
+ return count;
+ }
+
+ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+ {
+ if ((sat >= 1U) && (sat <= 32U))
+ {
+ const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+ const int32_t min = -1 - max ;
+ if (val > max)
+ {
+ return max;
+ }
+ else if (val < min)
+ {
+ return min;
+ }
+ }
+ return val;
+ }
+
+ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+ {
+ if (sat <= 31U)
+ {
+ const uint32_t max = ((1U << sat) - 1U);
+ if (val > (int32_t)max)
+ {
+ return max;
+ }
+ else if (val < 0)
+ {
+ return 0U;
+ }
+ }
+ return (uint32_t)val;
+ }
+
+ /**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ op2 %= 32U;
+ if (op2 == 0U)
+ {
+ return op1;
+ }
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+#endif
+
+/**
+ * @brief Clips Q63 to Q31 values.
+ */
+ __STATIC_FORCEINLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ __STATIC_FORCEINLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ __STATIC_FORCEINLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ __STATIC_FORCEINLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+ __STATIC_FORCEINLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y) ) );
+ }
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+#ifndef ARM_MATH_DSP
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+ #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+ #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+#endif
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+ #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+ #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+#endif
+
+
+
+
+/*
+ * @brief C custom defined intrinsic functions
+ */
+#if !defined (ARM_MATH_DSP)
+
+
+ /*
+ * @brief C custom defined QADD8
+ */
+ __STATIC_FORCEINLINE uint32_t __QADD8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB8
+ */
+ __STATIC_FORCEINLINE uint32_t __QSUB8(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QADD16
+ */
+ __STATIC_FORCEINLINE uint32_t __QADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
+ q31_t r = 0, s = 0;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHADD16
+ */
+ __STATIC_FORCEINLINE uint32_t __SHADD16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB16
+ */
+ __STATIC_FORCEINLINE uint32_t __QSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSUB16
+ */
+ __STATIC_FORCEINLINE uint32_t __SHSUB16(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QASX
+ */
+ __STATIC_FORCEINLINE uint32_t __QASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHASX
+ */
+ __STATIC_FORCEINLINE uint32_t __SHASX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined QSAX
+ */
+ __STATIC_FORCEINLINE uint32_t __QSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SHSAX
+ */
+ __STATIC_FORCEINLINE uint32_t __SHSAX(
+ uint32_t x,
+ uint32_t y)
+ {
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSDX
+ */
+ __STATIC_FORCEINLINE uint32_t __SMUSDX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+ /*
+ * @brief C custom defined SMUADX
+ */
+ __STATIC_FORCEINLINE uint32_t __SMUADX(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined QADD
+ */
+ __STATIC_FORCEINLINE int32_t __QADD(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined QSUB
+ */
+ __STATIC_FORCEINLINE int32_t __QSUB(
+ int32_t x,
+ int32_t y)
+ {
+ return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+ }
+
+
+ /*
+ * @brief C custom defined SMLAD
+ */
+ __STATIC_FORCEINLINE uint32_t __SMLAD(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLADX
+ */
+ __STATIC_FORCEINLINE uint32_t __SMLADX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLSDX
+ */
+ __STATIC_FORCEINLINE uint32_t __SMLSDX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALD
+ */
+ __STATIC_FORCEINLINE uint64_t __SMLALD(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMLALDX
+ */
+ __STATIC_FORCEINLINE uint64_t __SMLALDX(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+ {
+/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUAD
+ */
+ __STATIC_FORCEINLINE uint32_t __SMUAD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SMUSD
+ */
+ __STATIC_FORCEINLINE uint32_t __SMUSD(
+ uint32_t x,
+ uint32_t y)
+ {
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+ }
+
+
+ /*
+ * @brief C custom defined SXTB16
+ */
+ __STATIC_FORCEINLINE uint32_t __SXTB16(
+ uint32_t x)
+ {
+ return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+ ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
+ }
+
+ /*
+ * @brief C custom defined SMMLA
+ */
+ __STATIC_FORCEINLINE int32_t __SMMLA(
+ int32_t x,
+ int32_t y,
+ int32_t sum)
+ {
+ return (sum + (int32_t) (((int64_t) x * y) >> 32));
+ }
+
+#endif /* !defined (ARM_MATH_DSP) */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _TRANSFORM_FUNCTIONS_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/quaternion_math_functions.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/quaternion_math_functions.h
new file mode 100644
index 00000000000..33364c326a1
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/quaternion_math_functions.h
@@ -0,0 +1,159 @@
+/******************************************************************************
+ * @file quaternion_math_functions.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ *
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _QUATERNION_MATH_FUNCTIONS_H_
+#define _QUATERNION_MATH_FUNCTIONS_H_
+
+#include "arm_math_types.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * @defgroup groupQuaternionMath Quaternion Math Functions
+ * Functions to operates on quaternions and convert between a
+ * rotation and quaternion representation.
+ */
+
+
+/**
+ @brief Floating-point quaternion Norm.
+ @param[in] pInputQuaternions points to the input vector of quaternions
+ @param[out] pNorms points to the output vector of norms
+ @param[in] nbQuaternions number of quaternions in each vector
+ @return none
+ */
+
+
+
+void arm_quaternion_norm_f32(const float32_t *pInputQuaternions,
+ float32_t *pNorms,
+ uint32_t nbQuaternions);
+
+
+/**
+ @brief Floating-point quaternion inverse.
+ @param[in] pInputQuaternions points to the input vector of quaternions
+ @param[out] pInverseQuaternions points to the output vector of inverse quaternions
+ @param[in] nbQuaternions number of quaternions in each vector
+ @return none
+ */
+
+void arm_quaternion_inverse_f32(const float32_t *pInputQuaternions,
+ float32_t *pInverseQuaternions,
+ uint32_t nbQuaternions);
+
+/**
+ @brief Floating-point quaternion conjugates.
+ @param[in] pInputQuaternions points to the input vector of quaternions
+ @param[out] pConjugateQuaternions points to the output vector of conjugate quaternions
+ @param[in] nbQuaternions number of quaternions in each vector
+ @return none
+ */
+void arm_quaternion_conjugate_f32(const float32_t *inputQuaternions,
+ float32_t *pConjugateQuaternions,
+ uint32_t nbQuaternions);
+
+/**
+ @brief Floating-point normalization of quaternions.
+ @param[in] pInputQuaternions points to the input vector of quaternions
+ @param[out] pNormalizedQuaternions points to the output vector of normalized quaternions
+ @param[in] nbQuaternions number of quaternions in each vector
+ @return none
+ */
+void arm_quaternion_normalize_f32(const float32_t *inputQuaternions,
+ float32_t *pNormalizedQuaternions,
+ uint32_t nbQuaternions);
+
+
+/**
+ @brief Floating-point product of two quaternions.
+ @param[in] qa First quaternion
+ @param[in] qb Second quaternion
+ @param[out] r Product of two quaternions
+ @return none
+ */
+void arm_quaternion_product_single_f32(const float32_t *qa,
+ const float32_t *qb,
+ float32_t *r);
+
+/**
+ @brief Floating-point elementwise product two quaternions.
+ @param[in] qa First array of quaternions
+ @param[in] qb Second array of quaternions
+ @param[out] r Elementwise product of quaternions
+ @param[in] nbQuaternions Number of quaternions in the array
+ @return none
+ */
+void arm_quaternion_product_f32(const float32_t *qa,
+ const float32_t *qb,
+ float32_t *r,
+ uint32_t nbQuaternions);
+
+/**
+ * @brief Conversion of quaternion to equivalent rotation matrix.
+ * @param[in] pInputQuaternions points to an array of normalized quaternions
+ * @param[out] pOutputRotations points to an array of 3x3 rotations (in row order)
+ * @param[in] nbQuaternions in the array
+ * @return none.
+ *
+ * Format of rotation matrix
+ * \par
+ * The quaternion a + ib + jc + kd is converted into rotation matrix:
+ * a^2 + b^2 - c^2 - d^2 2bc - 2ad 2bd + 2ac
+ * 2bc + 2ad a^2 - b^2 + c^2 - d^2 2cd - 2ab
+ * 2bd - 2ac 2cd + 2ab a^2 - b^2 - c^2 + d^2
+ *
+ * Rotation matrix is saved in row order : R00 R01 R02 R10 R11 R12 R20 R21 R22
+ */
+void arm_quaternion2rotation_f32(const float32_t *pInputQuaternions,
+ float32_t *pOutputRotations,
+ uint32_t nbQuaternions);
+
+/**
+ * @brief Conversion of a rotation matrix to equivalent quaternion.
+ * @param[in] pInputRotations points to an array 3x3 rotation matrix (in row order)
+ * @param[out] pOutputQuaternions points to an array of quaternions
+ * @param[in] nbQuaternions in the array
+ * @return none.
+*/
+void arm_rotation2quaternion_f32(const float32_t *pInputRotations,
+ float32_t *pOutputQuaternions,
+ uint32_t nbQuaternions);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _QUATERNION_MATH_FUNCTIONS_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/statistics_functions.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/statistics_functions.h
new file mode 100644
index 00000000000..6af8a524b77
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/statistics_functions.h
@@ -0,0 +1,977 @@
+/******************************************************************************
+ * @file statistics_functions.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _STATISTICS_FUNCTIONS_H_
+#define _STATISTICS_FUNCTIONS_H_
+
+#include "arm_math_types.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+
+#include "dsp/basic_math_functions.h"
+#include "dsp/fast_math_functions.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+
+/**
+ * @brief Computation of the LogSumExp
+ *
+ * In probabilistic computations, the dynamic of the probability values can be very
+ * wide because they come from gaussian functions.
+ * To avoid underflow and overflow issues, the values are represented by their log.
+ * In this representation, multiplying the original exp values is easy : their logs are added.
+ * But adding the original exp values is requiring some special handling and it is the
+ * goal of the LogSumExp function.
+ *
+ * If the values are x1...xn, the function is computing:
+ *
+ * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that
+ * rounding issues are minimised.
+ *
+ * The max xm of the values is extracted and the function is computing:
+ * xm + ln(exp(x1 - xm) + ... + exp(xn - xm))
+ *
+ * @param[in] *in Pointer to an array of input values.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return LogSumExp
+ *
+ */
+
+
+float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize);
+
+/**
+ * @brief Dot product with log arithmetic
+ *
+ * Vectors are containing the log of the samples
+ *
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[in] pTmpBuffer temporary buffer of length blockSize
+ * @return The log of the dot product .
+ *
+ */
+
+
+float32_t arm_logsumexp_dot_prod_f32(const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t *pTmpBuffer);
+
+/**
+ * @brief Entropy
+ *
+ * @param[in] pSrcA Array of input values.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Entropy -Sum(p ln p)
+ *
+ */
+
+
+float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize);
+
+
+/**
+ * @brief Entropy
+ *
+ * @param[in] pSrcA Array of input values.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Entropy -Sum(p ln p)
+ *
+ */
+
+
+float64_t arm_entropy_f64(const float64_t * pSrcA, uint32_t blockSize);
+
+
+/**
+ * @brief Kullback-Leibler
+ *
+ * @param[in] pSrcA Pointer to an array of input values for probability distribution A.
+ * @param[in] pSrcB Pointer to an array of input values for probability distribution B.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Kullback-Leibler Divergence D(A || B)
+ *
+ */
+float32_t arm_kullback_leibler_f32(const float32_t * pSrcA
+ ,const float32_t * pSrcB
+ ,uint32_t blockSize);
+
+
+/**
+ * @brief Kullback-Leibler
+ *
+ * @param[in] pSrcA Pointer to an array of input values for probability distribution A.
+ * @param[in] pSrcB Pointer to an array of input values for probability distribution B.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Kullback-Leibler Divergence D(A || B)
+ *
+ */
+float64_t arm_kullback_leibler_f64(const float64_t * pSrcA,
+ const float64_t * pSrcB,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_f64(
+ const float64_t * pSrc,
+ uint32_t blockSize,
+ float64_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_f64(
+ const float64_t * pSrc,
+ uint32_t blockSize,
+ float64_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_f64(
+ const float64_t * pSrc,
+ uint32_t blockSize,
+ float64_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_f64(
+ const float64_t * pSrc,
+ uint32_t blockSize,
+ float64_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+ /**
+ * @brief Minimum value of absolute values of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ */
+ void arm_absmin_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+ /**
+ * @brief Minimum value of absolute values of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] result is output pointer
+ */
+ void arm_absmin_no_idx_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result);
+
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[in] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Minimum value of absolute values of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[in] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_absmin_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of absolute values of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ */
+ void arm_absmin_no_idx_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of absolute values of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_absmin_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of absolute values of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ */
+ void arm_absmin_no_idx_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of absolute values of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_absmin_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of absolute values of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ */
+ void arm_absmin_no_idx_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_f64(
+ const float64_t * pSrc,
+ uint32_t blockSize,
+ float64_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of absolute values of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_absmin_f64(
+ const float64_t * pSrc,
+ uint32_t blockSize,
+ float64_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of absolute values of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ */
+ void arm_absmin_no_idx_f64(
+ const float64_t * pSrc,
+ uint32_t blockSize,
+ float64_t * pResult);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of absolute values of a Q7 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_absmax_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of absolute values of a Q7 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ */
+ void arm_absmax_no_idx_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of absolute values of a Q15 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_absmax_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Maximum value of absolute values of a Q15 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ */
+ void arm_absmax_no_idx_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of absolute values of a Q31 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_absmax_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Maximum value of absolute values of a Q31 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ */
+ void arm_absmax_no_idx_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of absolute values of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_absmax_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Maximum value of absolute values of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ */
+ void arm_absmax_no_idx_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_f64(
+ const float64_t * pSrc,
+ uint32_t blockSize,
+ float64_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of absolute values of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_absmax_f64(
+ const float64_t * pSrc,
+ uint32_t blockSize,
+ float64_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of absolute values of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ */
+ void arm_absmax_no_idx_f64(
+ const float64_t * pSrc,
+ uint32_t blockSize,
+ float64_t * pResult);
+
+ /**
+ @brief Maximum value of a floating-point vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult maximum value returned here
+ @return none
+ */
+ void arm_max_no_idx_f32(
+ const float32_t *pSrc,
+ uint32_t blockSize,
+ float32_t *pResult);
+
+ /**
+ @brief Minimum value of a floating-point vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult minimum value returned here
+ @return none
+ */
+ void arm_min_no_idx_f32(
+ const float32_t *pSrc,
+ uint32_t blockSize,
+ float32_t *pResult);
+
+ /**
+ @brief Maximum value of a floating-point vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult maximum value returned here
+ @return none
+ */
+ void arm_max_no_idx_f64(
+ const float64_t *pSrc,
+ uint32_t blockSize,
+ float64_t *pResult);
+
+ /**
+ @brief Maximum value of a q31 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult maximum value returned here
+ @return none
+ */
+ void arm_max_no_idx_q31(
+ const q31_t *pSrc,
+ uint32_t blockSize,
+ q31_t *pResult);
+
+ /**
+ @brief Maximum value of a q15 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult maximum value returned here
+ @return none
+ */
+ void arm_max_no_idx_q15(
+ const q15_t *pSrc,
+ uint32_t blockSize,
+ q15_t *pResult);
+
+ /**
+ @brief Maximum value of a q7 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult maximum value returned here
+ @return none
+ */
+ void arm_max_no_idx_q7(
+ const q7_t *pSrc,
+ uint32_t blockSize,
+ q7_t *pResult);
+
+ /**
+ @brief Minimum value of a floating-point vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult minimum value returned here
+ @return none
+ */
+ void arm_min_no_idx_f64(
+ const float64_t *pSrc,
+ uint32_t blockSize,
+ float64_t *pResult);
+
+/**
+ @brief Minimum value of a q31 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult minimum value returned here
+ @return none
+ */
+ void arm_min_no_idx_q31(
+ const q31_t *pSrc,
+ uint32_t blockSize,
+ q31_t *pResult);
+
+ /**
+ @brief Minimum value of a q15 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult minimum value returned here
+ @return none
+ */
+ void arm_min_no_idx_q15(
+ const q15_t *pSrc,
+ uint32_t blockSize,
+ q15_t *pResult);
+
+ /**
+ @brief Minimum value of a q7 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult minimum value returned here
+ @return none
+ */
+ void arm_min_no_idx_q7(
+ const q7_t *pSrc,
+ uint32_t blockSize,
+ q7_t *pResult);
+
+/**
+ @brief Mean square error between two Q7 vectors.
+ @param[in] pSrcA points to the first input vector
+ @param[in] pSrcB points to the second input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult mean square error
+ @return none
+*/
+
+void arm_mse_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+/**
+ @brief Mean square error between two Q15 vectors.
+ @param[in] pSrcA points to the first input vector
+ @param[in] pSrcB points to the second input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult mean square error
+ @return none
+*/
+
+void arm_mse_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+/**
+ @brief Mean square error between two Q31 vectors.
+ @param[in] pSrcA points to the first input vector
+ @param[in] pSrcB points to the second input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult mean square error
+ @return none
+*/
+
+void arm_mse_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+/**
+ @brief Mean square error between two single precision float vectors.
+ @param[in] pSrcA points to the first input vector
+ @param[in] pSrcB points to the second input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult mean square error
+ @return none
+*/
+
+void arm_mse_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+/**
+ @brief Mean square error between two double precision float vectors.
+ @param[in] pSrcA points to the first input vector
+ @param[in] pSrcB points to the second input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult mean square error
+ @return none
+*/
+
+void arm_mse_f64(
+ const float64_t * pSrcA,
+ const float64_t * pSrcB,
+ uint32_t blockSize,
+ float64_t * pResult);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _STATISTICS_FUNCTIONS_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/statistics_functions_f16.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/statistics_functions_f16.h
new file mode 100644
index 00000000000..f4e7cc51eed
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/statistics_functions_f16.h
@@ -0,0 +1,266 @@
+/******************************************************************************
+ * @file statistics_functions_f16.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _STATISTICS_FUNCTIONS_F16_H_
+#define _STATISTICS_FUNCTIONS_F16_H_
+
+#include "arm_math_types_f16.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+
+#include "dsp/basic_math_functions_f16.h"
+#include "dsp/fast_math_functions_f16.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#if defined(ARM_FLOAT16_SUPPORTED)
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_power_f16(
+ const float16_t * pSrc,
+ uint32_t blockSize,
+ float16_t * pResult);
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_mean_f16(
+ const float16_t * pSrc,
+ uint32_t blockSize,
+ float16_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_var_f16(
+ const float16_t * pSrc,
+ uint32_t blockSize,
+ float16_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_rms_f16(
+ const float16_t * pSrc,
+ uint32_t blockSize,
+ float16_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+ void arm_std_f16(
+ const float16_t * pSrc,
+ uint32_t blockSize,
+ float16_t * pResult);
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_min_f16(
+ const float16_t * pSrc,
+ uint32_t blockSize,
+ float16_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of absolute values of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+ void arm_absmin_f16(
+ const float16_t * pSrc,
+ uint32_t blockSize,
+ float16_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_max_f16(
+ const float16_t * pSrc,
+ uint32_t blockSize,
+ float16_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of absolute values of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+ void arm_absmax_f16(
+ const float16_t * pSrc,
+ uint32_t blockSize,
+ float16_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of absolute values of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ */
+ void arm_absmin_no_idx_f16(
+ const float16_t * pSrc,
+ uint32_t blockSize,
+ float16_t * pResult);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ */
+ void arm_absmax_no_idx_f16(
+ const float16_t * pSrc,
+ uint32_t blockSize,
+ float16_t * pResult);
+
+
+/**
+ * @brief Entropy
+ *
+ * @param[in] pSrcA Array of input values.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Entropy -Sum(p ln p)
+ *
+ */
+
+
+float16_t arm_entropy_f16(const float16_t * pSrcA,uint32_t blockSize);
+
+float16_t arm_logsumexp_f16(const float16_t *in, uint32_t blockSize);
+
+/**
+ * @brief Dot product with log arithmetic
+ *
+ * Vectors are containing the log of the samples
+ *
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[in] pTmpBuffer temporary buffer of length blockSize
+ * @return The log of the dot product .
+ *
+ */
+
+
+float16_t arm_logsumexp_dot_prod_f16(const float16_t * pSrcA,
+ const float16_t * pSrcB,
+ uint32_t blockSize,
+ float16_t *pTmpBuffer);
+
+/**
+ * @brief Kullback-Leibler
+ *
+ * @param[in] pSrcA Pointer to an array of input values for probability distribution A.
+ * @param[in] pSrcB Pointer to an array of input values for probability distribution B.
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Kullback-Leibler Divergence D(A || B)
+ *
+ */
+float16_t arm_kullback_leibler_f16(const float16_t * pSrcA
+ ,const float16_t * pSrcB
+ ,uint32_t blockSize);
+
+/**
+ @brief Maximum value of a floating-point vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult maximum value returned here
+ @return none
+ */
+ void arm_max_no_idx_f16(
+ const float16_t *pSrc,
+ uint32_t blockSize,
+ float16_t *pResult);
+
+/**
+ @brief Minimum value of a floating-point vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult minimum value returned here
+ @return none
+ */
+ void arm_min_no_idx_f16(
+ const float16_t *pSrc,
+ uint32_t blockSize,
+ float16_t *pResult);
+
+/**
+ @brief Mean square error between two half precision float vectors.
+ @param[in] pSrcA points to the first input vector
+ @param[in] pSrcB points to the second input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult mean square error
+ @return none
+*/
+
+void arm_mse_f16(
+ const float16_t * pSrcA,
+ const float16_t * pSrcB,
+ uint32_t blockSize,
+ float16_t * pResult);
+
+#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _STATISTICS_FUNCTIONS_F16_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/support_functions.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/support_functions.h
new file mode 100644
index 00000000000..dc34c6da1e8
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/support_functions.h
@@ -0,0 +1,453 @@
+/******************************************************************************
+ * @file support_functions.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _SUPPORT_FUNCTIONS_H_
+#define _SUPPORT_FUNCTIONS_H_
+
+#include "arm_math_types.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q31(
+ const float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q15(
+ const float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ */
+ void arm_float_to_q7(
+ const float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_float(
+ const q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q15(
+ const q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q31_to_q7(
+ const q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_float(
+ const q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q31(
+ const q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q15_to_q7(
+ const q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+ void arm_q7_to_float(
+ const q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q31(
+ const q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_q7_to_q15(
+ const q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+
+
+ /**
+ * @brief Struct for specifying sorting algorithm
+ */
+ typedef enum
+ {
+ ARM_SORT_BITONIC = 0,
+ /**< Bitonic sort */
+ ARM_SORT_BUBBLE = 1,
+ /**< Bubble sort */
+ ARM_SORT_HEAP = 2,
+ /**< Heap sort */
+ ARM_SORT_INSERTION = 3,
+ /**< Insertion sort */
+ ARM_SORT_QUICK = 4,
+ /**< Quick sort */
+ ARM_SORT_SELECTION = 5
+ /**< Selection sort */
+ } arm_sort_alg;
+
+ /**
+ * @brief Struct for specifying sorting algorithm
+ */
+ typedef enum
+ {
+ ARM_SORT_DESCENDING = 0,
+ /**< Descending order (9 to 0) */
+ ARM_SORT_ASCENDING = 1
+ /**< Ascending order (0 to 9) */
+ } arm_sort_dir;
+
+ /**
+ * @brief Instance structure for the sorting algorithms.
+ */
+ typedef struct
+ {
+ arm_sort_alg alg; /**< Sorting algorithm selected */
+ arm_sort_dir dir; /**< Sorting order (direction) */
+ } arm_sort_instance_f32;
+
+ /**
+ * @param[in] S points to an instance of the sorting structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_sort_f32(
+ const arm_sort_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @param[in,out] S points to an instance of the sorting structure.
+ * @param[in] alg Selected algorithm.
+ * @param[in] dir Sorting order.
+ */
+ void arm_sort_init_f32(
+ arm_sort_instance_f32 * S,
+ arm_sort_alg alg,
+ arm_sort_dir dir);
+
+ /**
+ * @brief Instance structure for the sorting algorithms.
+ */
+ typedef struct
+ {
+ arm_sort_dir dir; /**< Sorting order (direction) */
+ float32_t * buffer; /**< Working buffer */
+ } arm_merge_sort_instance_f32;
+
+ /**
+ * @param[in] S points to an instance of the sorting structure.
+ * @param[in,out] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+ void arm_merge_sort_f32(
+ const arm_merge_sort_instance_f32 * S,
+ float32_t *pSrc,
+ float32_t *pDst,
+ uint32_t blockSize);
+
+ /**
+ * @param[in,out] S points to an instance of the sorting structure.
+ * @param[in] dir Sorting order.
+ * @param[in] buffer Working buffer.
+ */
+ void arm_merge_sort_init_f32(
+ arm_merge_sort_instance_f32 * S,
+ arm_sort_dir dir,
+ float32_t * buffer);
+
+
+
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_f64(
+ const float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q7(
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_copy_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_f64(
+ float64_t value,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+
+
+
+
+
+/**
+ * @brief Weighted sum
+ *
+ *
+ * @param[in] *in Array of input values.
+ * @param[in] *weigths Weights
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Weighted sum
+ *
+ */
+float32_t arm_weighted_sum_f32(const float32_t *in
+ , const float32_t *weigths
+ , uint32_t blockSize);
+
+
+/**
+ * @brief Barycenter
+ *
+ *
+ * @param[in] in List of vectors
+ * @param[in] weights Weights of the vectors
+ * @param[out] out Barycenter
+ * @param[in] nbVectors Number of vectors
+ * @param[in] vecDim Dimension of space (vector dimension)
+ * @return None
+ *
+ */
+void arm_barycenter_f32(const float32_t *in
+ , const float32_t *weights
+ , float32_t *out
+ , uint32_t nbVectors
+ , uint32_t vecDim);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _SUPPORT_FUNCTIONS_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/support_functions_f16.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/support_functions_f16.h
new file mode 100644
index 00000000000..463acee2c37
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/support_functions_f16.h
@@ -0,0 +1,187 @@
+/******************************************************************************
+ * @file support_functions_f16.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _SUPPORT_FUNCTIONS_F16_H_
+#define _SUPPORT_FUNCTIONS_F16_H_
+
+#include "arm_math_types_f16.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#if defined(ARM_FLOAT16_SUPPORTED)
+
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_copy_f16(const float16_t * pSrc, float16_t * pDst, uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_fill_f16(float16_t value, float16_t * pDst, uint32_t blockSize);
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] pSrc points to the f16 input vector
+ * @param[out] pDst points to the q15 output vector
+ * @param[in] blockSize length of the input vector
+ */
+void arm_f16_to_q15(const float16_t * pSrc, q15_t * pDst, uint32_t blockSize);
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] pSrc points to the q15 input vector
+ * @param[out] pDst points to the f16 output vector
+ * @param[in] blockSize length of the input vector
+ */
+void arm_q15_to_f16(const q15_t * pSrc, float16_t * pDst, uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] pSrc points to the f32 input vector
+ * @param[out] pDst points to the f16 output vector
+ * @param[in] blockSize length of the input vector
+ */
+void arm_float_to_f16(const float32_t * pSrc, float16_t * pDst, uint32_t blockSize);
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] pSrc points to the f16 input vector
+ * @param[out] pDst points to the f32 output vector
+ * @param[in] blockSize length of the input vector
+ */
+void arm_f16_to_float(const float16_t * pSrc, float32_t * pDst, uint32_t blockSize);
+
+/**
+ * @brief Weighted sum
+ *
+ *
+ * @param[in] *in Array of input values.
+ * @param[in] *weigths Weights
+ * @param[in] blockSize Number of samples in the input array.
+ * @return Weighted sum
+ *
+ */
+float16_t arm_weighted_sum_f16(const float16_t *in
+ , const float16_t *weigths
+ , uint32_t blockSize);
+
+/**
+ * @brief Barycenter
+ *
+ *
+ * @param[in] in List of vectors
+ * @param[in] weights Weights of the vectors
+ * @param[out] out Barycenter
+ * @param[in] nbVectors Number of vectors
+ * @param[in] vecDim Dimension of space (vector dimension)
+ * @return None
+ *
+ */
+void arm_barycenter_f16(const float16_t *in
+ , const float16_t *weights
+ , float16_t *out
+ , uint32_t nbVectors
+ , uint32_t vecDim);
+
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ * @defgroup typecast Typecasting
+ */
+
+/**
+ @addtogroup typecast
+ @{
+ */
+
+/**
+ * @brief Interpret a f16 as an s16 value
+ * @param[in] x input value.
+ * @return return value.
+ *
+ * @par Description
+ * It is a typecast. No conversion of the float to int is done.
+ * The memcpy will be optimized out by the compiler.
+ * memcpy is used to prevent type punning issues.
+ * With gcc, -fno-builtins MUST not be used or the
+ * memcpy will not be optimized out.
+ */
+__STATIC_INLINE int16_t arm_typecast_s16_f16(float16_t x)
+{
+ int16_t res;
+ res=*(int16_t*)memcpy((char*)&res,(char*)&x,sizeof(float16_t));
+ return(res);
+}
+
+/**
+ * @brief Interpret an s16 as an f16 value
+ * @param[in] x input value.
+ * @return return value.
+ *
+ * @par Description
+ * It is a typecast. No conversion of the int to float is done.
+ * The memcpy will be optimized out by the compiler.
+ * memcpy is used to prevent type punning issues.
+ * With gcc, -fno-builtins MUST not be used or the
+ * memcpy will not be optimized out.
+ */
+__STATIC_INLINE float16_t arm_typecast_f16_s16(int16_t x)
+{
+ float16_t res;
+ res=*(float16_t*)memcpy((char*)&res,(char*)&x,sizeof(int16_t));
+ return(res);
+}
+
+
+/**
+ @} end of typecast group
+ */
+
+
+#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _SUPPORT_FUNCTIONS_F16_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/svm_defines.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/svm_defines.h
new file mode 100644
index 00000000000..5f3b2ba3e7d
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/svm_defines.h
@@ -0,0 +1,46 @@
+/******************************************************************************
+ * @file svm_defines.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ *
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _SVM_DEFINES_H_
+#define _SVM_DEFINES_H_
+
+/**
+ * @brief Struct for specifying SVM Kernel
+ */
+typedef enum
+{
+ ARM_ML_KERNEL_LINEAR = 0,
+ /**< Linear kernel */
+ ARM_ML_KERNEL_POLYNOMIAL = 1,
+ /**< Polynomial kernel */
+ ARM_ML_KERNEL_RBF = 2,
+ /**< Radial Basis Function kernel */
+ ARM_ML_KERNEL_SIGMOID = 3
+ /**< Sigmoid kernel */
+} arm_ml_kernel_type;
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/svm_functions.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/svm_functions.h
new file mode 100644
index 00000000000..a979a548429
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/svm_functions.h
@@ -0,0 +1,299 @@
+/******************************************************************************
+ * @file svm_functions.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _SVM_FUNCTIONS_H_
+#define _SVM_FUNCTIONS_H_
+
+#include "arm_math_types.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+#include "dsp/svm_defines.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define STEP(x) (x) <= 0 ? 0 : 1
+
+/**
+ * @defgroup groupSVM SVM Functions
+ * This set of functions is implementing SVM classification on 2 classes.
+ * The training must be done from scikit-learn. The parameters can be easily
+ * generated from the scikit-learn object. Some examples are given in
+ * DSP/Testing/PatternGeneration/SVM.py
+ *
+ * If more than 2 classes are needed, the functions in this folder
+ * will have to be used, as building blocks, to do multi-class classification.
+ *
+ * No multi-class classification is provided in this SVM folder.
+ *
+ */
+
+/**
+ * @brief Integer exponentiation
+ * @param[in] x value
+ * @param[in] nb integer exponent >= 1
+ * @return x^nb
+ *
+ */
+__STATIC_INLINE float32_t arm_exponent_f32(float32_t x, int32_t nb)
+{
+ float32_t r = x;
+ nb --;
+ while(nb > 0)
+ {
+ r = r * x;
+ nb--;
+ }
+ return(r);
+}
+
+
+
+
+
+/**
+ * @brief Instance structure for linear SVM prediction function.
+ */
+typedef struct
+{
+ uint32_t nbOfSupportVectors; /**< Number of support vectors */
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ float32_t intercept; /**< Intercept */
+ const float32_t *dualCoefficients; /**< Dual coefficients */
+ const float32_t *supportVectors; /**< Support vectors */
+ const int32_t *classes; /**< The two SVM classes */
+} arm_svm_linear_instance_f32;
+
+
+/**
+ * @brief Instance structure for polynomial SVM prediction function.
+ */
+typedef struct
+{
+ uint32_t nbOfSupportVectors; /**< Number of support vectors */
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ float32_t intercept; /**< Intercept */
+ const float32_t *dualCoefficients; /**< Dual coefficients */
+ const float32_t *supportVectors; /**< Support vectors */
+ const int32_t *classes; /**< The two SVM classes */
+ int32_t degree; /**< Polynomial degree */
+ float32_t coef0; /**< Polynomial constant */
+ float32_t gamma; /**< Gamma factor */
+} arm_svm_polynomial_instance_f32;
+
+/**
+ * @brief Instance structure for rbf SVM prediction function.
+ */
+typedef struct
+{
+ uint32_t nbOfSupportVectors; /**< Number of support vectors */
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ float32_t intercept; /**< Intercept */
+ const float32_t *dualCoefficients; /**< Dual coefficients */
+ const float32_t *supportVectors; /**< Support vectors */
+ const int32_t *classes; /**< The two SVM classes */
+ float32_t gamma; /**< Gamma factor */
+} arm_svm_rbf_instance_f32;
+
+/**
+ * @brief Instance structure for sigmoid SVM prediction function.
+ */
+typedef struct
+{
+ uint32_t nbOfSupportVectors; /**< Number of support vectors */
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ float32_t intercept; /**< Intercept */
+ const float32_t *dualCoefficients; /**< Dual coefficients */
+ const float32_t *supportVectors; /**< Support vectors */
+ const int32_t *classes; /**< The two SVM classes */
+ float32_t coef0; /**< Independent constant */
+ float32_t gamma; /**< Gamma factor */
+} arm_svm_sigmoid_instance_f32;
+
+/**
+ * @brief SVM linear instance init function
+ * @param[in] S Parameters for SVM functions
+ * @param[in] nbOfSupportVectors Number of support vectors
+ * @param[in] vectorDimension Dimension of vector space
+ * @param[in] intercept Intercept
+ * @param[in] dualCoefficients Array of dual coefficients
+ * @param[in] supportVectors Array of support vectors
+ * @param[in] classes Array of 2 classes ID
+ * @return none.
+ *
+ */
+
+
+void arm_svm_linear_init_f32(arm_svm_linear_instance_f32 *S,
+ uint32_t nbOfSupportVectors,
+ uint32_t vectorDimension,
+ float32_t intercept,
+ const float32_t *dualCoefficients,
+ const float32_t *supportVectors,
+ const int32_t *classes);
+
+/**
+ * @brief SVM linear prediction
+ * @param[in] S Pointer to an instance of the linear SVM structure.
+ * @param[in] in Pointer to input vector
+ * @param[out] pResult Decision value
+ * @return none.
+ *
+ */
+
+void arm_svm_linear_predict_f32(const arm_svm_linear_instance_f32 *S,
+ const float32_t * in,
+ int32_t * pResult);
+
+
+/**
+ * @brief SVM polynomial instance init function
+ * @param[in] S points to an instance of the polynomial SVM structure.
+ * @param[in] nbOfSupportVectors Number of support vectors
+ * @param[in] vectorDimension Dimension of vector space
+ * @param[in] intercept Intercept
+ * @param[in] dualCoefficients Array of dual coefficients
+ * @param[in] supportVectors Array of support vectors
+ * @param[in] classes Array of 2 classes ID
+ * @param[in] degree Polynomial degree
+ * @param[in] coef0 coeff0 (scikit-learn terminology)
+ * @param[in] gamma gamma (scikit-learn terminology)
+ * @return none.
+ *
+ */
+
+
+void arm_svm_polynomial_init_f32(arm_svm_polynomial_instance_f32 *S,
+ uint32_t nbOfSupportVectors,
+ uint32_t vectorDimension,
+ float32_t intercept,
+ const float32_t *dualCoefficients,
+ const float32_t *supportVectors,
+ const int32_t *classes,
+ int32_t degree,
+ float32_t coef0,
+ float32_t gamma
+ );
+
+/**
+ * @brief SVM polynomial prediction
+ * @param[in] S Pointer to an instance of the polynomial SVM structure.
+ * @param[in] in Pointer to input vector
+ * @param[out] pResult Decision value
+ * @return none.
+ *
+ */
+void arm_svm_polynomial_predict_f32(const arm_svm_polynomial_instance_f32 *S,
+ const float32_t * in,
+ int32_t * pResult);
+
+
+/**
+ * @brief SVM radial basis function instance init function
+ * @param[in] S points to an instance of the polynomial SVM structure.
+ * @param[in] nbOfSupportVectors Number of support vectors
+ * @param[in] vectorDimension Dimension of vector space
+ * @param[in] intercept Intercept
+ * @param[in] dualCoefficients Array of dual coefficients
+ * @param[in] supportVectors Array of support vectors
+ * @param[in] classes Array of 2 classes ID
+ * @param[in] gamma gamma (scikit-learn terminology)
+ * @return none.
+ *
+ */
+
+void arm_svm_rbf_init_f32(arm_svm_rbf_instance_f32 *S,
+ uint32_t nbOfSupportVectors,
+ uint32_t vectorDimension,
+ float32_t intercept,
+ const float32_t *dualCoefficients,
+ const float32_t *supportVectors,
+ const int32_t *classes,
+ float32_t gamma
+ );
+
+/**
+ * @brief SVM rbf prediction
+ * @param[in] S Pointer to an instance of the rbf SVM structure.
+ * @param[in] in Pointer to input vector
+ * @param[out] pResult decision value
+ * @return none.
+ *
+ */
+void arm_svm_rbf_predict_f32(const arm_svm_rbf_instance_f32 *S,
+ const float32_t * in,
+ int32_t * pResult);
+
+/**
+ * @brief SVM sigmoid instance init function
+ * @param[in] S points to an instance of the rbf SVM structure.
+ * @param[in] nbOfSupportVectors Number of support vectors
+ * @param[in] vectorDimension Dimension of vector space
+ * @param[in] intercept Intercept
+ * @param[in] dualCoefficients Array of dual coefficients
+ * @param[in] supportVectors Array of support vectors
+ * @param[in] classes Array of 2 classes ID
+ * @param[in] coef0 coeff0 (scikit-learn terminology)
+ * @param[in] gamma gamma (scikit-learn terminology)
+ * @return none.
+ *
+ */
+
+void arm_svm_sigmoid_init_f32(arm_svm_sigmoid_instance_f32 *S,
+ uint32_t nbOfSupportVectors,
+ uint32_t vectorDimension,
+ float32_t intercept,
+ const float32_t *dualCoefficients,
+ const float32_t *supportVectors,
+ const int32_t *classes,
+ float32_t coef0,
+ float32_t gamma
+ );
+
+/**
+ * @brief SVM sigmoid prediction
+ * @param[in] S Pointer to an instance of the rbf SVM structure.
+ * @param[in] in Pointer to input vector
+ * @param[out] pResult Decision value
+ * @return none.
+ *
+ */
+void arm_svm_sigmoid_predict_f32(const arm_svm_sigmoid_instance_f32 *S,
+ const float32_t * in,
+ int32_t * pResult);
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _SVM_FUNCTIONS_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/svm_functions_f16.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/svm_functions_f16.h
new file mode 100644
index 00000000000..1d11924f5d4
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/svm_functions_f16.h
@@ -0,0 +1,281 @@
+/******************************************************************************
+ * @file svm_functions_f16.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _SVM_FUNCTIONS_F16_H_
+#define _SVM_FUNCTIONS_F16_H_
+
+#include "arm_math_types_f16.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+#include "dsp/svm_defines.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#if defined(ARM_FLOAT16_SUPPORTED)
+
+#define STEP(x) (x) <= 0 ? 0 : 1
+
+/**
+ * @defgroup groupSVM SVM Functions
+ * This set of functions is implementing SVM classification on 2 classes.
+ * The training must be done from scikit-learn. The parameters can be easily
+ * generated from the scikit-learn object. Some examples are given in
+ * DSP/Testing/PatternGeneration/SVM.py
+ *
+ * If more than 2 classes are needed, the functions in this folder
+ * will have to be used, as building blocks, to do multi-class classification.
+ *
+ * No multi-class classification is provided in this SVM folder.
+ *
+ */
+
+
+
+/**
+ * @brief Instance structure for linear SVM prediction function.
+ */
+typedef struct
+{
+ uint32_t nbOfSupportVectors; /**< Number of support vectors */
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ float16_t intercept; /**< Intercept */
+ const float16_t *dualCoefficients; /**< Dual coefficients */
+ const float16_t *supportVectors; /**< Support vectors */
+ const int32_t *classes; /**< The two SVM classes */
+} arm_svm_linear_instance_f16;
+
+
+/**
+ * @brief Instance structure for polynomial SVM prediction function.
+ */
+typedef struct
+{
+ uint32_t nbOfSupportVectors; /**< Number of support vectors */
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ float16_t intercept; /**< Intercept */
+ const float16_t *dualCoefficients; /**< Dual coefficients */
+ const float16_t *supportVectors; /**< Support vectors */
+ const int32_t *classes; /**< The two SVM classes */
+ int32_t degree; /**< Polynomial degree */
+ float16_t coef0; /**< Polynomial constant */
+ float16_t gamma; /**< Gamma factor */
+} arm_svm_polynomial_instance_f16;
+
+/**
+ * @brief Instance structure for rbf SVM prediction function.
+ */
+typedef struct
+{
+ uint32_t nbOfSupportVectors; /**< Number of support vectors */
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ float16_t intercept; /**< Intercept */
+ const float16_t *dualCoefficients; /**< Dual coefficients */
+ const float16_t *supportVectors; /**< Support vectors */
+ const int32_t *classes; /**< The two SVM classes */
+ float16_t gamma; /**< Gamma factor */
+} arm_svm_rbf_instance_f16;
+
+/**
+ * @brief Instance structure for sigmoid SVM prediction function.
+ */
+typedef struct
+{
+ uint32_t nbOfSupportVectors; /**< Number of support vectors */
+ uint32_t vectorDimension; /**< Dimension of vector space */
+ float16_t intercept; /**< Intercept */
+ const float16_t *dualCoefficients; /**< Dual coefficients */
+ const float16_t *supportVectors; /**< Support vectors */
+ const int32_t *classes; /**< The two SVM classes */
+ float16_t coef0; /**< Independent constant */
+ float16_t gamma; /**< Gamma factor */
+} arm_svm_sigmoid_instance_f16;
+
+/**
+ * @brief SVM linear instance init function
+ * @param[in] S Parameters for SVM functions
+ * @param[in] nbOfSupportVectors Number of support vectors
+ * @param[in] vectorDimension Dimension of vector space
+ * @param[in] intercept Intercept
+ * @param[in] dualCoefficients Array of dual coefficients
+ * @param[in] supportVectors Array of support vectors
+ * @param[in] classes Array of 2 classes ID
+ * @return none.
+ *
+ */
+
+
+void arm_svm_linear_init_f16(arm_svm_linear_instance_f16 *S,
+ uint32_t nbOfSupportVectors,
+ uint32_t vectorDimension,
+ float16_t intercept,
+ const float16_t *dualCoefficients,
+ const float16_t *supportVectors,
+ const int32_t *classes);
+
+/**
+ * @brief SVM linear prediction
+ * @param[in] S Pointer to an instance of the linear SVM structure.
+ * @param[in] in Pointer to input vector
+ * @param[out] pResult Decision value
+ * @return none.
+ *
+ */
+
+void arm_svm_linear_predict_f16(const arm_svm_linear_instance_f16 *S,
+ const float16_t * in,
+ int32_t * pResult);
+
+
+/**
+ * @brief SVM polynomial instance init function
+ * @param[in] S points to an instance of the polynomial SVM structure.
+ * @param[in] nbOfSupportVectors Number of support vectors
+ * @param[in] vectorDimension Dimension of vector space
+ * @param[in] intercept Intercept
+ * @param[in] dualCoefficients Array of dual coefficients
+ * @param[in] supportVectors Array of support vectors
+ * @param[in] classes Array of 2 classes ID
+ * @param[in] degree Polynomial degree
+ * @param[in] coef0 coeff0 (scikit-learn terminology)
+ * @param[in] gamma gamma (scikit-learn terminology)
+ * @return none.
+ *
+ */
+
+
+void arm_svm_polynomial_init_f16(arm_svm_polynomial_instance_f16 *S,
+ uint32_t nbOfSupportVectors,
+ uint32_t vectorDimension,
+ float16_t intercept,
+ const float16_t *dualCoefficients,
+ const float16_t *supportVectors,
+ const int32_t *classes,
+ int32_t degree,
+ float16_t coef0,
+ float16_t gamma
+ );
+
+/**
+ * @brief SVM polynomial prediction
+ * @param[in] S Pointer to an instance of the polynomial SVM structure.
+ * @param[in] in Pointer to input vector
+ * @param[out] pResult Decision value
+ * @return none.
+ *
+ */
+void arm_svm_polynomial_predict_f16(const arm_svm_polynomial_instance_f16 *S,
+ const float16_t * in,
+ int32_t * pResult);
+
+
+/**
+ * @brief SVM radial basis function instance init function
+ * @param[in] S points to an instance of the polynomial SVM structure.
+ * @param[in] nbOfSupportVectors Number of support vectors
+ * @param[in] vectorDimension Dimension of vector space
+ * @param[in] intercept Intercept
+ * @param[in] dualCoefficients Array of dual coefficients
+ * @param[in] supportVectors Array of support vectors
+ * @param[in] classes Array of 2 classes ID
+ * @param[in] gamma gamma (scikit-learn terminology)
+ * @return none.
+ *
+ */
+
+void arm_svm_rbf_init_f16(arm_svm_rbf_instance_f16 *S,
+ uint32_t nbOfSupportVectors,
+ uint32_t vectorDimension,
+ float16_t intercept,
+ const float16_t *dualCoefficients,
+ const float16_t *supportVectors,
+ const int32_t *classes,
+ float16_t gamma
+ );
+
+/**
+ * @brief SVM rbf prediction
+ * @param[in] S Pointer to an instance of the rbf SVM structure.
+ * @param[in] in Pointer to input vector
+ * @param[out] pResult decision value
+ * @return none.
+ *
+ */
+void arm_svm_rbf_predict_f16(const arm_svm_rbf_instance_f16 *S,
+ const float16_t * in,
+ int32_t * pResult);
+
+/**
+ * @brief SVM sigmoid instance init function
+ * @param[in] S points to an instance of the rbf SVM structure.
+ * @param[in] nbOfSupportVectors Number of support vectors
+ * @param[in] vectorDimension Dimension of vector space
+ * @param[in] intercept Intercept
+ * @param[in] dualCoefficients Array of dual coefficients
+ * @param[in] supportVectors Array of support vectors
+ * @param[in] classes Array of 2 classes ID
+ * @param[in] coef0 coeff0 (scikit-learn terminology)
+ * @param[in] gamma gamma (scikit-learn terminology)
+ * @return none.
+ *
+ */
+
+void arm_svm_sigmoid_init_f16(arm_svm_sigmoid_instance_f16 *S,
+ uint32_t nbOfSupportVectors,
+ uint32_t vectorDimension,
+ float16_t intercept,
+ const float16_t *dualCoefficients,
+ const float16_t *supportVectors,
+ const int32_t *classes,
+ float16_t coef0,
+ float16_t gamma
+ );
+
+/**
+ * @brief SVM sigmoid prediction
+ * @param[in] S Pointer to an instance of the rbf SVM structure.
+ * @param[in] in Pointer to input vector
+ * @param[out] pResult Decision value
+ * @return none.
+ *
+ */
+void arm_svm_sigmoid_predict_f16(const arm_svm_sigmoid_instance_f16 *S,
+ const float16_t * in,
+ int32_t * pResult);
+
+
+
+#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _SVM_FUNCTIONS_F16_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/transform_functions.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/transform_functions.h
new file mode 100644
index 00000000000..70d8ef5ba9f
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/transform_functions.h
@@ -0,0 +1,735 @@
+/******************************************************************************
+ * @file transform_functions.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _TRANSFORM_FUNCTIONS_H_
+#define _TRANSFORM_FUNCTIONS_H_
+
+#include "arm_math_types.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+
+#include "dsp/basic_math_functions.h"
+#include "dsp/complex_math_functions.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
+ const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \
+ const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \
+ const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \
+ const q15_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \
+ const q15_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \
+ const q15_t *rearranged_twiddle_stride3;
+#endif
+ } arm_cfft_instance_q15;
+
+arm_status arm_cfft_init_q15(
+ arm_cfft_instance_q15 * S,
+ uint16_t fftLen);
+
+void arm_cfft_q15(
+ const arm_cfft_instance_q15 * S,
+ q15_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
+ const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \
+ const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \
+ const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \
+ const q31_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \
+ const q31_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \
+ const q31_t *rearranged_twiddle_stride3;
+#endif
+ } arm_cfft_instance_q31;
+
+arm_status arm_cfft_init_q31(
+ arm_cfft_instance_q31 * S,
+ uint16_t fftLen);
+
+void arm_cfft_q31(
+ const arm_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
+ const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \
+ const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \
+ const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \
+ const float32_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \
+ const float32_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \
+ const float32_t *rearranged_twiddle_stride3;
+#endif
+ } arm_cfft_instance_f32;
+
+
+
+ arm_status arm_cfft_init_f32(
+ arm_cfft_instance_f32 * S,
+ uint16_t fftLen);
+
+ void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+
+ /**
+ * @brief Instance structure for the Double Precision Floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float64_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_f64;
+
+ arm_status arm_cfft_init_f64(
+ arm_cfft_instance_f64 * S,
+ uint16_t fftLen);
+
+ void arm_cfft_f64(
+ const arm_cfft_instance_f64 * S,
+ float64_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ const q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ const q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
+ arm_cfft_instance_q15 cfftInst;
+#else
+ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+#endif
+ } arm_rfft_instance_q15;
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ const q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ const q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
+ arm_cfft_instance_q31 cfftInst;
+#else
+ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+#endif
+ } arm_rfft_instance_q31;
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ const float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ const float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the Double Precision Floating-point RFFT/RIFFT function.
+ */
+typedef struct
+ {
+ arm_cfft_instance_f64 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ const float64_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f64 ;
+
+arm_status arm_rfft_fast_init_f64 (
+ arm_rfft_fast_instance_f64 * S,
+ uint16_t fftLen);
+
+
+void arm_rfft_fast_f64(
+ arm_rfft_fast_instance_f64 * S,
+ float64_t * p, float64_t * pOut,
+ uint8_t ifftFlag);
+
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct
+ {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ const float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen);
+
+
+ void arm_rfft_fast_f32(
+ const arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ const float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ const float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
+ */
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ const q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ const q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q31 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ const q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ const q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q15 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+ /**
+ * @brief Instance structure for the Floating-point MFCC function.
+ */
+typedef struct
+ {
+ const float32_t *dctCoefs; /**< Internal DCT coefficients */
+ const float32_t *filterCoefs; /**< Internal Mel filter coefficients */
+ const float32_t *windowCoefs; /**< Windowing coefficients */
+ const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */
+ const uint32_t *filterLengths; /**< Internal Mel filter lengths */
+ uint32_t fftLen; /**< FFT length */
+ uint32_t nbMelFilters; /**< Number of Mel filters */
+ uint32_t nbDctOutputs; /**< Number of DCT outputs */
+#if defined(ARM_MFCC_CFFT_BASED)
+ /* Implementation of the MFCC is using a CFFT */
+ arm_cfft_instance_f32 cfft; /**< Internal CFFT instance */
+#else
+ /* Implementation of the MFCC is using a RFFT (default) */
+ arm_rfft_fast_instance_f32 rfft;
+#endif
+ } arm_mfcc_instance_f32 ;
+
+arm_status arm_mfcc_init_f32(
+ arm_mfcc_instance_f32 * S,
+ uint32_t fftLen,
+ uint32_t nbMelFilters,
+ uint32_t nbDctOutputs,
+ const float32_t *dctCoefs,
+ const uint32_t *filterPos,
+ const uint32_t *filterLengths,
+ const float32_t *filterCoefs,
+ const float32_t *windowCoefs
+ );
+
+
+/**
+ @brief MFCC F32
+ @param[in] S points to the mfcc instance structure
+ @param[in] pSrc points to the input samples
+ @param[out] pDst points to the output MFCC values
+ @param[inout] pTmp points to a temporary buffer of complex
+ @return none
+ */
+ void arm_mfcc_f32(
+ const arm_mfcc_instance_f32 * S,
+ float32_t *pSrc,
+ float32_t *pDst,
+ float32_t *pTmp
+ );
+
+typedef struct
+ {
+ const q31_t *dctCoefs; /**< Internal DCT coefficients */
+ const q31_t *filterCoefs; /**< Internal Mel filter coefficients */
+ const q31_t *windowCoefs; /**< Windowing coefficients */
+ const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */
+ const uint32_t *filterLengths; /**< Internal Mel filter lengths */
+ uint32_t fftLen; /**< FFT length */
+ uint32_t nbMelFilters; /**< Number of Mel filters */
+ uint32_t nbDctOutputs; /**< Number of DCT outputs */
+#if defined(ARM_MFCC_CFFT_BASED)
+ /* Implementation of the MFCC is using a CFFT */
+ arm_cfft_instance_q31 cfft; /**< Internal CFFT instance */
+#else
+ /* Implementation of the MFCC is using a RFFT (default) */
+ arm_rfft_instance_q31 rfft;
+#endif
+ } arm_mfcc_instance_q31 ;
+
+arm_status arm_mfcc_init_q31(
+ arm_mfcc_instance_q31 * S,
+ uint32_t fftLen,
+ uint32_t nbMelFilters,
+ uint32_t nbDctOutputs,
+ const q31_t *dctCoefs,
+ const uint32_t *filterPos,
+ const uint32_t *filterLengths,
+ const q31_t *filterCoefs,
+ const q31_t *windowCoefs
+ );
+
+
+/**
+ @brief MFCC Q31
+ @param[in] S points to the mfcc instance structure
+ @param[in] pSrc points to the input samples
+ @param[out] pDst points to the output MFCC values
+ @param[inout] pTmp points to a temporary buffer of complex
+ @return none
+ */
+ arm_status arm_mfcc_q31(
+ const arm_mfcc_instance_q31 * S,
+ q31_t *pSrc,
+ q31_t *pDst,
+ q31_t *pTmp
+ );
+
+typedef struct
+ {
+ const q15_t *dctCoefs; /**< Internal DCT coefficients */
+ const q15_t *filterCoefs; /**< Internal Mel filter coefficients */
+ const q15_t *windowCoefs; /**< Windowing coefficients */
+ const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */
+ const uint32_t *filterLengths; /**< Internal Mel filter lengths */
+ uint32_t fftLen; /**< FFT length */
+ uint32_t nbMelFilters; /**< Number of Mel filters */
+ uint32_t nbDctOutputs; /**< Number of DCT outputs */
+#if defined(ARM_MFCC_CFFT_BASED)
+ /* Implementation of the MFCC is using a CFFT */
+ arm_cfft_instance_q15 cfft; /**< Internal CFFT instance */
+#else
+ /* Implementation of the MFCC is using a RFFT (default) */
+ arm_rfft_instance_q15 rfft;
+#endif
+ } arm_mfcc_instance_q15 ;
+
+arm_status arm_mfcc_init_q15(
+ arm_mfcc_instance_q15 * S,
+ uint32_t fftLen,
+ uint32_t nbMelFilters,
+ uint32_t nbDctOutputs,
+ const q15_t *dctCoefs,
+ const uint32_t *filterPos,
+ const uint32_t *filterLengths,
+ const q15_t *filterCoefs,
+ const q15_t *windowCoefs
+ );
+
+
+/**
+ @brief MFCC Q15
+ @param[in] S points to the mfcc instance structure
+ @param[in] pSrc points to the input samples
+ @param[out] pDst points to the output MFCC values in q8.7 format
+ @param[inout] pTmp points to a temporary buffer of complex
+ @return error status
+ */
+ arm_status arm_mfcc_q15(
+ const arm_mfcc_instance_q15 * S,
+ q15_t *pSrc,
+ q15_t *pDst,
+ q31_t *pTmp
+ );
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _TRANSFORM_FUNCTIONS_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/transform_functions_f16.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/transform_functions_f16.h
new file mode 100644
index 00000000000..ee1911136c1
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/transform_functions_f16.h
@@ -0,0 +1,208 @@
+/******************************************************************************
+ * @file transform_functions_f16.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.10.0
+ * @date 08 July 2021
+ * Target Processor: Cortex-M and Cortex-A cores
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _TRANSFORM_FUNCTIONS_F16_H_
+#define _TRANSFORM_FUNCTIONS_F16_H_
+
+#include "arm_math_types_f16.h"
+#include "arm_math_memory.h"
+
+#include "dsp/none.h"
+#include "dsp/utils.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+
+#if defined(ARM_FLOAT16_SUPPORTED)
+
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const float16_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float16_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f16;
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ const float16_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float16_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f16;
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float16_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
+ const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \
+ const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \
+ const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \
+ const float16_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \
+ const float16_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \
+ const float16_t *rearranged_twiddle_stride3;
+#endif
+ } arm_cfft_instance_f16;
+
+
+ arm_status arm_cfft_init_f16(
+ arm_cfft_instance_f16 * S,
+ uint16_t fftLen);
+
+ void arm_cfft_f16(
+ const arm_cfft_instance_f16 * S,
+ float16_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct
+ {
+ arm_cfft_instance_f16 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ const float16_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f16 ;
+
+arm_status arm_rfft_fast_init_f16 (
+ arm_rfft_fast_instance_f16 * S,
+ uint16_t fftLen);
+
+
+ void arm_rfft_fast_f16(
+ const arm_rfft_fast_instance_f16 * S,
+ float16_t * p, float16_t * pOut,
+ uint8_t ifftFlag);
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_f16(
+ arm_cfft_radix4_instance_f16 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_f16(
+ const arm_cfft_radix4_instance_f16 * S,
+ float16_t * pSrc);
+
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_f16(
+ arm_cfft_radix2_instance_f16 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_f16(
+ const arm_cfft_radix2_instance_f16 * S,
+ float16_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Floating-point MFCC function.
+ */
+typedef struct
+ {
+ const float16_t *dctCoefs; /**< Internal DCT coefficients */
+ const float16_t *filterCoefs; /**< Internal Mel filter coefficients */
+ const float16_t *windowCoefs; /**< Windowing coefficients */
+ const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */
+ const uint32_t *filterLengths; /**< Internal Mel filter lengths */
+ uint32_t fftLen; /**< FFT length */
+ uint32_t nbMelFilters; /**< Number of Mel filters */
+ uint32_t nbDctOutputs; /**< Number of DCT outputs */
+#if defined(ARM_MFCC_CFFT_BASED)
+ /* Implementation of the MFCC is using a CFFT */
+ arm_cfft_instance_f16 cfft; /**< Internal CFFT instance */
+#else
+ /* Implementation of the MFCC is using a RFFT (default) */
+ arm_rfft_fast_instance_f16 rfft;
+#endif
+ } arm_mfcc_instance_f16 ;
+
+arm_status arm_mfcc_init_f16(
+ arm_mfcc_instance_f16 * S,
+ uint32_t fftLen,
+ uint32_t nbMelFilters,
+ uint32_t nbDctOutputs,
+ const float16_t *dctCoefs,
+ const uint32_t *filterPos,
+ const uint32_t *filterLengths,
+ const float16_t *filterCoefs,
+ const float16_t *windowCoefs
+ );
+
+
+/**
+ @brief MFCC F16
+ @param[in] S points to the mfcc instance structure
+ @param[in] pSrc points to the input samples
+ @param[out] pDst points to the output MFCC values
+ @param[inout] pTmp points to a temporary buffer of complex
+ @return none
+ */
+ void arm_mfcc_f16(
+ const arm_mfcc_instance_f16 * S,
+ float16_t *pSrc,
+ float16_t *pDst,
+ float16_t *pTmp
+ );
+
+
+#endif /* defined(ARM_FLOAT16_SUPPORTED)*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef _TRANSFORM_FUNCTIONS_F16_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/utils.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/utils.h
new file mode 100644
index 00000000000..7f5acb3747e
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/dsp/utils.h
@@ -0,0 +1,240 @@
+/******************************************************************************
+ * @file arm_math_utils.h
+ * @brief Public header file for CMSIS DSP Library
+ * @version V1.9.0
+ * @date 20. July 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_MATH_UTILS_H_
+
+#define _ARM_MATH_UTILS_H_
+
+#include "arm_math_types.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define INDEX_MASK 0x0000003F
+
+
+#define SQ(x) ((x) * (x))
+
+#define ROUND_UP(N, S) ((((N) + (S) - 1) / (S)) * (S))
+
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+ __STATIC_FORCEINLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ const q31_t * pRecipTable)
+ {
+ q31_t out;
+ uint32_t tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if (in > 0)
+ {
+ signBits = ((uint32_t) (__CLZ( in) - 1));
+ }
+ else
+ {
+ signBits = ((uint32_t) (__CLZ(-in) - 1));
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 24);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0U; i < 2U; i++)
+ {
+ tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+ tempVal = 0x7FFFFFFFu - tempVal;
+ /* 1.31 with exp 1 */
+ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+ out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1U);
+ }
+
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+ __STATIC_FORCEINLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ const q15_t * pRecipTable)
+ {
+ q15_t out = 0;
+ uint32_t tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if (in > 0)
+ {
+ signBits = ((uint32_t)(__CLZ( in) - 17));
+ }
+ else
+ {
+ signBits = ((uint32_t)(__CLZ(-in) - 17));
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 8);
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0U; i < 2U; i++)
+ {
+ tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFFu - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+ }
+
+
+/**
+ * @brief 64-bit to 32-bit unsigned normalization
+ * @param[in] in is input unsigned long long value
+ * @param[out] normalized is the 32-bit normalized value
+ * @param[out] norm is norm scale
+ */
+__STATIC_INLINE void arm_norm_64_to_32u(uint64_t in, int32_t * normalized, int32_t *norm)
+{
+ int32_t n1;
+ int32_t hi = (int32_t) (in >> 32);
+ int32_t lo = (int32_t) ((in << 32) >> 32);
+
+ n1 = __CLZ(hi) - 32;
+ if (!n1)
+ {
+ /*
+ * input fits in 32-bit
+ */
+ n1 = __CLZ(lo);
+ if (!n1)
+ {
+ /*
+ * MSB set, need to scale down by 1
+ */
+ *norm = -1;
+ *normalized = (((uint32_t) lo) >> 1);
+ } else
+ {
+ if (n1 == 32)
+ {
+ /*
+ * input is zero
+ */
+ *norm = 0;
+ *normalized = 0;
+ } else
+ {
+ /*
+ * 32-bit normalization
+ */
+ *norm = n1 - 1;
+ *normalized = lo << *norm;
+ }
+ }
+ } else
+ {
+ /*
+ * input fits in 64-bit
+ */
+ n1 = 1 - n1;
+ *norm = -n1;
+ /*
+ * 64 bit normalization
+ */
+ *normalized = (((uint32_t) lo) >> n1) | (hi << (32 - n1));
+ }
+}
+
+__STATIC_INLINE q31_t arm_div_q63_to_q31(q63_t num, q31_t den)
+{
+ q31_t result;
+ uint64_t absNum;
+ int32_t normalized;
+ int32_t norm;
+
+ /*
+ * if sum fits in 32bits
+ * avoid costly 64-bit division
+ */
+ absNum = num > 0 ? num : -num;
+ arm_norm_64_to_32u(absNum, &normalized, &norm);
+ if (norm > 0)
+ /*
+ * 32-bit division
+ */
+ result = (q31_t) num / den;
+ else
+ /*
+ * 64-bit division
+ */
+ result = (q31_t) (num / den);
+
+ return result;
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*ifndef _ARM_MATH_UTILS_H_ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/mpu_armv7.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/mpu_armv7.h
new file mode 100644
index 00000000000..9909f83990b
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/mpu_armv7.h
@@ -0,0 +1,275 @@
+/******************************************************************************
+ * @file mpu_armv7.h
+ * @brief CMSIS MPU API for Armv7-M MPU
+ * @version V5.1.2
+ * @date 25. May 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+ (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
+ ((Region) & MPU_RBAR_REGION_Msk) | \
+ (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+*
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
+ ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
+ (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
+ (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
+ (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
+ ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
+ (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
+ (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
+ (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
+ (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
+ (((MPU_RASR_ENABLE_Msk))))
+
+/**
+* MPU Region Attribute and Size Register Value
+*
+* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable Region is shareable between multiple bus masters.
+* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable Sub-region disable field.
+* \param Size Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+* - TEX: 000b
+* - Shareable
+* - Non-cacheable
+* - Non-bufferable
+*/
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+* - TEX: 000b (if shareable) or 010b (if non-shareable)
+* - Shareable or non-shareable
+* - Non-cacheable
+* - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+* - TEX: 1BBb (reflecting outer cacheability rules)
+* - Shareable or non-shareable
+* - Cacheable or non-cacheable (reflecting inner cacheability rules)
+* - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; //!< The region base address register value (RBAR)
+ uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ __DMB();
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ __DSB();
+ __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+ __DSB();
+ __ISB();
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ MPU->RNR = rnr;
+ MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rasr Value for RASR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rasr Value for RASR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+ MPU->RNR = rnr;
+ MPU->RBAR = rbar;
+ MPU->RASR = rasr;
+}
+
+/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ while (cnt > MPU_TYPE_RALIASES) {
+ ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+ table += MPU_TYPE_RALIASES;
+ cnt -= MPU_TYPE_RALIASES;
+ }
+ ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/mpu_armv8.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/mpu_armv8.h
new file mode 100644
index 00000000000..19855b9667c
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/mpu_armv8.h
@@ -0,0 +1,352 @@
+/******************************************************************************
+ * @file mpu_armv8.h
+ * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
+ * @version V5.1.3
+ * @date 03. February 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+ ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable */
+#define ARM_MPU_SH_NON (0U)
+
+/** \brief Normal memory outer shareable */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+ (((BASE) & MPU_RBAR_BASE_Msk) | \
+ (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+ (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+ (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+ (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+ (MPU_RLAR_EN_Msk))
+
+#if defined(MPU_RLAR_PXN_Pos)
+
+/** \brief Region Limit Address Register with PXN value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
+ (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+ (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
+ (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+ (MPU_RLAR_EN_Msk))
+
+#endif
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+ uint32_t RBAR; /*!< Region Base Address Register value */
+ uint32_t RLAR; /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+ __DMB();
+ MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ __DSB();
+ __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+ __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+ __DSB();
+ __ISB();
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+ __DMB();
+ MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ __DSB();
+ __ISB();
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+ __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+ SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+ MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
+ __DSB();
+ __ISB();
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+ const uint8_t reg = idx / 4U;
+ const uint32_t pos = ((idx % 4U) * 8U);
+ const uint32_t mask = 0xFFU << pos;
+
+ if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+ return; // invalid index
+ }
+
+ mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+ ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+ ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+ mpu->RNR = rnr;
+ mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+ ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{
+ ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ mpu->RNR = rnr;
+ mpu->RBAR = rbar;
+ mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+ ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
+}
+#endif
+
+/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+ uint32_t i;
+ for (i = 0U; i < len; ++i)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+ if (cnt == 1U) {
+ mpu->RNR = rnr;
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+ } else {
+ uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
+ uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+
+ mpu->RNR = rnrBase;
+ while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+ uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+ table += c;
+ cnt -= c;
+ rnrOffset = 0U;
+ rnrBase += MPU_TYPE_RALIASES;
+ mpu->RNR = rnrBase;
+ }
+
+ ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+ }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
+{
+ ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/pmu_armv8.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/pmu_armv8.h
new file mode 100644
index 00000000000..aa53bb47c1f
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/core_support/pmu_armv8.h
@@ -0,0 +1,337 @@
+/******************************************************************************
+ * @file pmu_armv8.h
+ * @brief CMSIS PMU API for Armv8.1-M PMU
+ * @version V1.0.1
+ * @date 15. April 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef ARM_PMU_ARMV8_H
+#define ARM_PMU_ARMV8_H
+
+/**
+ * \brief PMU Events
+ * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
+ * */
+
+#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
+#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */
+#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */
+#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */
+#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */
+#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */
+#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */
+#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */
+#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */
+#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
+#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */
+#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */
+#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
+#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */
+#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */
+#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */
+#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */
+#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */
+#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */
+#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */
+#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */
+#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */
+#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */
+#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */
+#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */
+#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */
+#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
+#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */
+#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */
+#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */
+#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */
+#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */
+#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */
+#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */
+#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */
+#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */
+#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */
+#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */
+#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */
+#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */
+#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */
+#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */
+#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */
+#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */
+#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */
+#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */
+#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
+#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */
+#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */
+#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */
+#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */
+#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */
+#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */
+#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */
+#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */
+#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */
+#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */
+#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */
+#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */
+#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */
+#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */
+#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */
+#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */
+#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */
+#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */
+#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */
+#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */
+#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */
+#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */
+#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
+#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
+#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */
+#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */
+#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */
+#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */
+#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */
+#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */
+#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */
+#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */
+#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */
+#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */
+#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */
+#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */
+#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */
+#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */
+#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */
+#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */
+#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */
+#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */
+#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */
+#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */
+#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */
+#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */
+#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */
+#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */
+#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */
+#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */
+#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */
+#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */
+#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */
+#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */
+#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */
+#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */
+#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */
+#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */
+#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */
+#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */
+#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */
+#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */
+#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
+#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */
+#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */
+#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */
+#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */
+#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */
+#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */
+#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */
+#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */
+#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */
+#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */
+#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */
+#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */
+#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */
+
+/** \brief PMU Functions */
+
+__STATIC_INLINE void ARM_PMU_Enable(void);
+__STATIC_INLINE void ARM_PMU_Disable(void);
+
+__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
+
+__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
+__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
+
+__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
+__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
+
+__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
+__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
+
+__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
+__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
+
+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
+
+__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
+
+/**
+ \brief Enable the PMU
+*/
+__STATIC_INLINE void ARM_PMU_Enable(void)
+{
+ PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
+}
+
+/**
+ \brief Disable the PMU
+*/
+__STATIC_INLINE void ARM_PMU_Disable(void)
+{
+ PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
+}
+
+/**
+ \brief Set event to count for PMU eventer counter
+ \param [in] num Event counter (0-30) to configure
+ \param [in] type Event to count
+*/
+__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
+{
+ PMU->EVTYPER[num] = type;
+}
+
+/**
+ \brief Reset cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
+{
+ PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
+}
+
+/**
+ \brief Reset all event counters
+*/
+__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
+{
+ PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
+}
+
+/**
+ \brief Enable counters
+ \param [in] mask Counters to enable
+ \note Enables one or more of the following:
+ - event counters (0-30)
+ - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
+{
+ PMU->CNTENSET = mask;
+}
+
+/**
+ \brief Disable counters
+ \param [in] mask Counters to enable
+ \note Disables one or more of the following:
+ - event counters (0-30)
+ - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
+{
+ PMU->CNTENCLR = mask;
+}
+
+/**
+ \brief Read cycle counter
+ \return Cycle count
+*/
+__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
+{
+ return PMU->CCNTR;
+}
+
+/**
+ \brief Read event counter
+ \param [in] num Event counter (0-30) to read
+ \return Event count
+*/
+__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
+{
+ return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num];
+}
+
+/**
+ \brief Read counter overflow status
+ \return Counter overflow status bits for the following:
+ - event counters (0-30)
+ - cycle counter
+*/
+__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
+{
+ return PMU->OVSSET;
+}
+
+/**
+ \brief Clear counter overflow status
+ \param [in] mask Counter overflow status bits to clear
+ \note Clears overflow status bits for one or more of the following:
+ - event counters (0-30)
+ - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
+{
+ PMU->OVSCLR = mask;
+}
+
+/**
+ \brief Enable counter overflow interrupt request
+ \param [in] mask Counter overflow interrupt request bits to set
+ \note Sets overflow interrupt request bits for one or more of the following:
+ - event counters (0-30)
+ - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
+{
+ PMU->INTENSET = mask;
+}
+
+/**
+ \brief Disable counter overflow interrupt request
+ \param [in] mask Counter overflow interrupt request bits to clear
+ \note Clears overflow interrupt request bits for one or more of the following:
+ - event counters (0-30)
+ - cycle counter
+*/
+__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
+{
+ PMU->INTENCLR = mask;
+}
+
+/**
+ \brief Software increment event counter
+ \param [in] mask Counters to increment
+ \note Software increment bits for one or more event counters (0-30)
+*/
+__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
+{
+ PMU->SWINC = mask;
+}
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/at32f45x.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/at32f45x.h
new file mode 100644
index 00000000000..73327e19707
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/at32f45x.h
@@ -0,0 +1,953 @@
+/**
+ **************************************************************************
+ * @file at32f45x.h
+ * @brief at32f45x header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#ifndef __AT32F45x_H
+#define __AT32F45x_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined (__CC_ARM)
+ #pragma anon_unions
+#endif
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup AT32F45x
+ * @{
+ */
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/**
+ * tip: to avoid modifying this file each time you need to switch between these
+ * devices, you can define the device in your toolchain compiler preprocessor.
+ */
+
+#if !defined (AT32F455CCT7) && !defined (AT32F455CET7) && !defined (AT32F455CCU7) && \
+ !defined (AT32F455CEU7) && !defined (AT32F455RCT7) && !defined (AT32F455RET7) && \
+ !defined (AT32F455VCT7) && !defined (AT32F455VET7) && !defined (AT32F455ZCT7) && \
+ !defined (AT32F455ZET7) && \
+ !defined (AT32F456CCT7) && !defined (AT32F456CET7) && !defined (AT32F456CCU7) && \
+ !defined (AT32F456CEU7) && !defined (AT32F456RCT7) && !defined (AT32F456RET7) && \
+ !defined (AT32F456VCT7) && !defined (AT32F456VET7) && !defined (AT32F456ZCT7) && \
+ !defined (AT32F456ZET7) && \
+ !defined (AT32F457RCT7) && !defined (AT32F457RET7) && !defined (AT32F457VCT7) && \
+ !defined (AT32F457VET7) && !defined (AT32F457ZCT7) && !defined (AT32F457ZET7)
+
+ #error "Please select first the target device used in your application (in at32f45x.h file)"
+#endif
+
+#if defined (AT32F455CCT7) || defined (AT32F455CET7) || defined (AT32F455CCU7) || \
+ defined (AT32F455CEU7) || defined (AT32F455RCT7) || defined (AT32F455RET7) || \
+ defined (AT32F455VCT7) || defined (AT32F455VET7) || defined (AT32F455ZCT7) || \
+ defined (AT32F455ZET7)
+
+ #define AT32F455xx
+#endif
+
+#if defined (AT32F456CCT7) || defined (AT32F456CET7) || defined (AT32F456CCU7) || \
+ defined (AT32F456CEU7) || defined (AT32F456RCT7) || defined (AT32F456RET7) || \
+ defined (AT32F456VCT7) || defined (AT32F456VET7) || defined (AT32F456ZCT7) || \
+ defined (AT32F456ZET7)
+
+ #define AT32F456xx
+#endif
+
+#if defined (AT32F457RCT7) || defined (AT32F457RET7) || defined (AT32F457VCT7) || \
+ defined (AT32F457VET7) || defined (AT32F457ZCT7) || defined (AT32F457ZET7)
+
+ #define AT32F457xx
+#endif
+
+/**
+ * define with package
+ */
+#if defined (AT32F455CCT7) || defined (AT32F455CET7) || defined (AT32F455CCU7) || \
+ defined (AT32F455CEU7)
+
+ #define AT32F455Cx
+#endif
+
+#if defined (AT32F455RCT7) || defined (AT32F455RET7)
+
+ #define AT32F455Rx
+#endif
+
+#if defined (AT32F455VCT7) || defined (AT32F455VET7)
+
+ #define AT32F455Vx
+#endif
+
+#if defined (AT32F455ZCT7) || defined (AT32F455ZET7)
+
+ #define AT32F455Zx
+#endif
+
+#if defined (AT32F456CCT7) || defined (AT32F456CET7) || defined (AT32F456CCU7) || \
+ defined (AT32F456CEU7)
+
+ #define AT32F456Cx
+#endif
+
+#if defined (AT32F456RCT7) || defined (AT32F456RET7)
+
+ #define AT32F456Rx
+#endif
+
+#if defined (AT32F456VCT7) || defined (AT32F456VET7)
+
+ #define AT32F456Vx
+#endif
+
+#if defined (AT32F456ZCT7) || defined (AT32F456ZET7)
+
+ #define AT32F456Zx
+#endif
+
+#if defined (AT32F457RCT7) || defined (AT32F457RET7)
+
+ #define AT32F457Rx
+#endif
+
+#if defined (AT32F457VCT7) || defined (AT32F457VET7)
+
+ #define AT32F457Vx
+#endif
+
+#if defined (AT32F457ZCT7) || defined (AT32F457ZET7)
+
+ #define AT32F457Zx
+#endif
+
+/**
+ * define with memory density
+ */
+#if defined (AT32F455CCT7) || defined (AT32F455CCU7) || defined (AT32F455RCT7) || \
+ defined (AT32F455VCT7) || defined (AT32F455ZCT7)
+
+ #define AT32F455xC
+#endif
+
+#if defined (AT32F455CET7) || defined (AT32F455CEU7) || defined (AT32F455RET7) || \
+ defined (AT32F455VET7) || defined (AT32F455ZET7)
+
+ #define AT32F455xE
+#endif
+
+#if defined (AT32F456CCT7) || defined (AT32F456CCU7) || defined (AT32F456RCT7) || \
+ defined (AT32F456VCT7) || defined (AT32F456ZCT7)
+
+ #define AT32F456xC
+#endif
+
+#if defined (AT32F456CET7) || defined (AT32F456CEU7) || defined (AT32F456RET7) || \
+ defined (AT32F456VET7) || defined (AT32F456ZET7)
+
+ #define AT32F456xE
+#endif
+
+#if defined (AT32F457RCT7) || defined (AT32F457VCT7) || defined (AT32F457ZCT7)
+
+ #define AT32F457xC
+#endif
+
+#if defined (AT32F457RET7) || defined (AT32F457VET7) || defined (AT32F457ZET7)
+
+ #define AT32F457xE
+#endif
+
+#ifndef USE_STDPERIPH_DRIVER
+/**
+ * @brief comment the line below if you will not use the peripherals drivers.
+ * in this case, these drivers will not be included and the application code will
+ * be based on direct access to peripherals registers
+ */
+ #ifdef _RTE_
+ #include "RTE_Components.h"
+ #ifdef RTE_DEVICE_STDPERIPH_FRAMEWORK
+ #define USE_STDPERIPH_DRIVER
+ #endif
+ #endif
+#endif
+
+/**
+ * @brief at32f45x standard peripheral library version number
+ */
+#define __AT32F45x_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */
+#define __AT32F45x_LIBRARY_VERSION_MIDDLE (0x00) /*!< [23:16] middle version */
+#define __AT32F45x_LIBRARY_VERSION_MINOR (0x00) /*!< [15:8] minor version */
+#define __AT32F45x_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __AT32F45x_LIBRARY_VERSION ((__AT32F45x_LIBRARY_VERSION_MAJOR << 24) | \
+ (__AT32F45x_LIBRARY_VERSION_MIDDLE << 16) | \
+ (__AT32F45x_LIBRARY_VERSION_MINOR << 8) | \
+ (__AT32F45x_LIBRARY_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup configuration_section_for_cmsis
+ * @{
+ */
+
+/**
+ * @brief configuration of the cortex-m4 processor and core peripherals
+ */
+#define __CM4_REV 0x0001U /*!< core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< mpu present */
+#define __NVIC_PRIO_BITS 4 /*!< at32 uses 4 bits for the priority levels */
+#define __Vendor_SysTickConfig 0 /*!< set to 1 if different systick config is used */
+#define __FPU_PRESENT 1U /*!< fpu present */
+
+/**
+ * @brief at32f45x interrupt number definition, according to the selected device
+ * in @ref library_configuration_section
+ */
+typedef enum IRQn
+{
+ /****** cortex-m4 processor exceptions numbers ***************************************************/
+ Reset_IRQn = -15, /*!< 1 reset vector, invoked on power up and warm reset */
+ NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */
+ HardFault_IRQn = -13, /*!< 3 hard fault, all classes of fault */
+ MemoryManagement_IRQn = -12, /*!< 4 cortex-m4 memory management interrupt */
+ BusFault_IRQn = -11, /*!< 5 cortex-m4 bus fault interrupt */
+ UsageFault_IRQn = -10, /*!< 6 cortex-m4 usage fault interrupt */
+ SVCall_IRQn = -5, /*!< 11 cortex-m4 sv call interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 cortex-m4 debug monitor interrupt */
+ PendSV_IRQn = -2, /*!< 14 cortex-m4 pend sv interrupt */
+ SysTick_IRQn = -1, /*!< 15 cortex-m4 system tick interrupt */
+
+ /****** at32 specific interrupt numbers *********************************************************/
+ WWDT_IRQn = 0, /*!< window watchdog timer interrupt */
+ PVM_IRQn = 1, /*!< pvm through exint line detection interrupt */
+ TAMP_STAMP_IRQn = 2, /*!< tamper and timestamp interrupts through the exint line */
+ ERTC_WKUP_IRQn = 3, /*!< ertc wakeup through the exint line */
+ FLASH_IRQn = 4, /*!< flash global interrupt */
+ CRM_IRQn = 5, /*!< crm global interrupt */
+ EXINT0_IRQn = 6, /*!< exint line0 interrupt */
+ EXINT1_IRQn = 7, /*!< exint line1 interrupt */
+ EXINT2_IRQn = 8, /*!< exint line2 interrupt */
+ EXINT3_IRQn = 9, /*!< exint line3 interrupt */
+ EXINT4_IRQn = 10, /*!< exint line4 interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< dma1 channel 1 global interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< dma1 channel 2 global interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< dma1 channel 3 global interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< dma1 channel 4 global interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< dma1 channel 5 global interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< dma1 channel 6 global interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< dma1 channel 7 global interrupt */
+
+#if defined (AT32F455xx)
+ ADC1_2_IRQn = 18, /*!< adc1 and adc2 global interrupt */
+ CAN1_TX_IRQn = 19, /*!< can1 tx interrupts */
+ CAN1_RX_IRQn = 20, /*!< can1 rx interrupts */
+ CAN1_STAT_IRQn = 21, /*!< can1 state interrupt */
+ CAN1_ERR_IRQn = 22, /*!< can1 error interrupt */
+ EXINT9_5_IRQn = 23, /*!< external line[9:5] interrupts */
+ TMR1_BRK_TMR9_IRQn = 24, /*!< tmr1 brake and tmr9 interrupt */
+ TMR1_OVF_TMR10_IRQn = 25, /*!< tmr1 overflow and tmr10 interrupt */
+ TMR1_TRG_HALL_TMR11_IRQn = 26, /*!< tmr1 trigger and hall and tmr11 interrupt */
+ TMR1_CH_IRQn = 27, /*!< tmr1 channel interrupt */
+ TMR2_GLOBAL_IRQn = 28, /*!< tmr2 global interrupt */
+ TMR3_GLOBAL_IRQn = 29, /*!< tmr3 global interrupt */
+ TMR4_GLOBAL_IRQn = 30, /*!< tmr4 global interrupt */
+ I2C1_EVT_IRQn = 31, /*!< i2c1 event interrupt */
+ I2C1_ERR_IRQn = 32, /*!< i2c1 error interrupt */
+ I2C2_EVT_IRQn = 33, /*!< i2c2 event interrupt */
+ I2C2_ERR_IRQn = 34, /*!< i2c2 error interrupt */
+ SPI1_IRQn = 35, /*!< spi1 global interrupt */
+ SPI2_I2S2EXT_IRQn = 36, /*!< spi2_i2s2ext global interrupt */
+ USART1_IRQn = 37, /*!< usart1 global interrupt */
+ USART2_IRQn = 38, /*!< usart2 global interrupt */
+ USART3_IRQn = 39, /*!< usart3 global interrupt */
+ EXINT15_10_IRQn = 40, /*!< external line[15:10] interrupts */
+ ERTCAlarm_IRQn = 41, /*!< ertc alarm through exint line interrupt */
+ OTGFS1_WKUP_IRQn = 42, /*!< otgfs1 wakeup from suspend through exint line interrupt */
+ TMR8_BRK_TMR12_IRQn = 43, /*!< tmr8 brake and tmr12 interrupt */
+ TMR8_OVF_TMR13_IRQn = 44, /*!< tmr8 overflow and tmr13 interrupt */
+ TMR8_TRG_HALL_TMR14_IRQn = 45, /*!< tmr8 trigger and hall and tmr14 interrupt */
+ TMR8_CH_IRQn = 46, /*!< tmr8 channel interrupt */
+ XMC_IRQn = 48, /*!< xmc global interrupt */
+ SDIO1_IRQn = 49, /*!< sdio global interrupt */
+ TMR5_GLOBAL_IRQn = 50, /*!< tmr5 global interrupt */
+ SPI3_I2S3EXT_IRQn = 51, /*!< spi3_i2s3ext global interrupt */
+ USART4_IRQn = 52, /*!< usart4 global interrupt */
+ USART5_IRQn = 53, /*!< usart5 global interrupt */
+ TMR6_DAC_GLOBAL_IRQn = 54, /*!< tmr6 and dac global interrupt */
+ TMR7_GLOBAL_IRQn = 55, /*!< tmr7 global interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< dma2 channel 1 global interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< dma2 channel 2 global interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< dma2 channel 3 global interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< dma2 channel 4 global interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< dma2 channel 5 global interrupt */
+ CAN2_TX_IRQn = 63, /*!< can2 tx interrupt */
+ CAN2_RX_IRQn = 64, /*!< can2 rx interrupt */
+ CAN2_STAT_IRQn = 65, /*!< can2 state interrupt */
+ CAN2_ERR_IRQn = 66, /*!< can2 error interrupt */
+ OTGFS1_IRQn = 67, /*!< otgfs1 interrupt */
+ DMA2_Channel6_IRQn = 68, /*!< dma2 channel 6 global interrupt */
+ DMA2_Channel7_IRQn = 69, /*!< dma2 channel 7 global interrupt */
+ USART6_IRQn = 71, /*!< usart6 interrupt */
+ I2C3_EVT_IRQn = 72, /*!< i2c3 event interrupt */
+ I2C3_ERR_IRQn = 73, /*!< i2c3 error interrupt */
+ CAN3_TX_IRQn = 74, /*!< can3 tx interrupt */
+ CAN3_RX_IRQn = 75, /*!< can3 rx interrupt */
+ CAN3_STAT_IRQn = 76, /*!< can3 state interrupt */
+ CAN3_ERR_IRQn = 77, /*!< can3 error interrupt */
+ AES_IRQn = 79, /*!< aes interrupt */
+ TRNG_IRQn = 80, /*!< trng interrupt */
+ FPU_IRQn = 81, /*!< fpu interrupt */
+ USART7_IRQn = 82, /*!< usart7 interrupt */
+ USART8_IRQn = 83, /*!< usart8 interrupt */
+ SPI4_IRQn = 84, /*!< spi4 global interrupt */
+ I2SF5_IRQn = 85, /*!< i2sf5 global interrupt */
+ QSPI1_IRQn = 92, /*!< qspi1 global interrupt */
+ DMAMUX_IRQn = 94, /*!< dmamux interrupt */
+ ACC_IRQn = 103, /*!< acc interrupt */
+#endif
+
+#if defined (AT32F456xx)
+ ADC1_2_IRQn = 18, /*!< adc1 and adc2 global interrupt */
+ CAN1_TX_IRQn = 19, /*!< can1 tx interrupts */
+ CAN1_RX_IRQn = 20, /*!< can1 rx interrupts */
+ CAN1_STAT_IRQn = 21, /*!< can1 state interrupt */
+ CAN1_ERR_IRQn = 22, /*!< can1 error interrupt */
+ EXINT9_5_IRQn = 23, /*!< external line[9:5] interrupts */
+ TMR1_BRK_TMR9_IRQn = 24, /*!< tmr1 brake and tmr9 interrupt */
+ TMR1_OVF_TMR10_IRQn = 25, /*!< tmr1 overflow and tmr10 interrupt */
+ TMR1_TRG_HALL_TMR11_IRQn = 26, /*!< tmr1 trigger and hall and tmr11 interrupt */
+ TMR1_CH_IRQn = 27, /*!< tmr1 channel interrupt */
+ TMR2_GLOBAL_IRQn = 28, /*!< tmr2 global interrupt */
+ TMR3_GLOBAL_IRQn = 29, /*!< tmr3 global interrupt */
+ TMR4_GLOBAL_IRQn = 30, /*!< tmr4 global interrupt */
+ I2C1_EVT_IRQn = 31, /*!< i2c1 event interrupt */
+ I2C1_ERR_IRQn = 32, /*!< i2c1 error interrupt */
+ I2C2_EVT_IRQn = 33, /*!< i2c2 event interrupt */
+ I2C2_ERR_IRQn = 34, /*!< i2c2 error interrupt */
+ SPI1_IRQn = 35, /*!< spi1 global interrupt */
+ SPI2_I2S2EXT_IRQn = 36, /*!< spi2_i2s2ext global interrupt */
+ USART1_IRQn = 37, /*!< usart1 global interrupt */
+ USART2_IRQn = 38, /*!< usart2 global interrupt */
+ USART3_IRQn = 39, /*!< usart3 global interrupt */
+ EXINT15_10_IRQn = 40, /*!< external line[15:10] interrupts */
+ ERTCAlarm_IRQn = 41, /*!< ertc alarm through exint line interrupt */
+ OTGFS1_WKUP_IRQn = 42, /*!< otgfs1 wakeup from suspend through exint line interrupt */
+ TMR8_BRK_TMR12_IRQn = 43, /*!< tmr8 brake and tmr12 interrupt */
+ TMR8_OVF_TMR13_IRQn = 44, /*!< tmr8 overflow and tmr13 interrupt */
+ TMR8_TRG_HALL_TMR14_IRQn = 45, /*!< tmr8 trigger and hall and tmr14 interrupt */
+ TMR8_CH_IRQn = 46, /*!< tmr8 channel interrupt */
+ XMC_IRQn = 48, /*!< xmc global interrupt */
+ SDIO1_IRQn = 49, /*!< sdio global interrupt */
+ TMR5_GLOBAL_IRQn = 50, /*!< tmr5 global interrupt */
+ SPI3_I2S3EXT_IRQn = 51, /*!< spi3_i2s3ext global interrupt */
+ USART4_IRQn = 52, /*!< usart4 global interrupt */
+ USART5_IRQn = 53, /*!< usart5 global interrupt */
+ TMR6_DAC_GLOBAL_IRQn = 54, /*!< tmr6 and dac global interrupt */
+ TMR7_GLOBAL_IRQn = 55, /*!< tmr7 global interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< dma2 channel 1 global interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< dma2 channel 2 global interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< dma2 channel 3 global interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< dma2 channel 4 global interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< dma2 channel 5 global interrupt */
+ CAN2_TX_IRQn = 63, /*!< can2 tx interrupt */
+ CAN2_RX_IRQn = 64, /*!< can2 rx interrupt */
+ CAN2_STAT_IRQn = 65, /*!< can2 state interrupt */
+ CAN2_ERR_IRQn = 66, /*!< can2 error interrupt */
+ OTGFS1_IRQn = 67, /*!< otgfs1 interrupt */
+ DMA2_Channel6_IRQn = 68, /*!< dma2 channel 6 global interrupt */
+ DMA2_Channel7_IRQn = 69, /*!< dma2 channel 7 global interrupt */
+ USART6_IRQn = 71, /*!< usart6 interrupt */
+ I2C3_EVT_IRQn = 72, /*!< i2c3 event interrupt */
+ I2C3_ERR_IRQn = 73, /*!< i2c3 error interrupt */
+ CAN3_TX_IRQn = 74, /*!< can3 tx interrupt */
+ CAN3_RX_IRQn = 75, /*!< can3 rx interrupt */
+ CAN3_STAT_IRQn = 76, /*!< can3 state interrupt */
+ CAN3_ERR_IRQn = 77, /*!< can3 error interrupt */
+ AES_IRQn = 79, /*!< aes interrupt */
+ TRNG_IRQn = 80, /*!< trng interrupt */
+ FPU_IRQn = 81, /*!< fpu interrupt */
+ USART7_IRQn = 82, /*!< usart7 interrupt */
+ USART8_IRQn = 83, /*!< usart8 interrupt */
+ SPI4_IRQn = 84, /*!< spi4 global interrupt */
+ I2SF5_IRQn = 85, /*!< i2sf5 global interrupt */
+ QSPI1_IRQn = 92, /*!< qspi1 global interrupt */
+ DMAMUX_IRQn = 94, /*!< dmamux interrupt */
+ ACC_IRQn = 103, /*!< acc interrupt */
+#endif
+
+#if defined (AT32F457xx)
+ ADC1_2_IRQn = 18, /*!< adc1 and adc2 global interrupt */
+ CAN1_TX_IRQn = 19, /*!< can1 tx interrupts */
+ CAN1_RX_IRQn = 20, /*!< can1 rx interrupts */
+ CAN1_STAT_IRQn = 21, /*!< can1 state interrupt */
+ CAN1_ERR_IRQn = 22, /*!< can1 error interrupt */
+ EXINT9_5_IRQn = 23, /*!< external line[9:5] interrupts */
+ TMR1_BRK_TMR9_IRQn = 24, /*!< tmr1 brake and tmr9 interrupt */
+ TMR1_OVF_TMR10_IRQn = 25, /*!< tmr1 overflow and tmr10 interrupt */
+ TMR1_TRG_HALL_TMR11_IRQn = 26, /*!< tmr1 trigger and hall and tmr11 interrupt */
+ TMR1_CH_IRQn = 27, /*!< tmr1 channel interrupt */
+ TMR2_GLOBAL_IRQn = 28, /*!< tmr2 global interrupt */
+ TMR3_GLOBAL_IRQn = 29, /*!< tmr3 global interrupt */
+ TMR4_GLOBAL_IRQn = 30, /*!< tmr4 global interrupt */
+ I2C1_EVT_IRQn = 31, /*!< i2c1 event interrupt */
+ I2C1_ERR_IRQn = 32, /*!< i2c1 error interrupt */
+ I2C2_EVT_IRQn = 33, /*!< i2c2 event interrupt */
+ I2C2_ERR_IRQn = 34, /*!< i2c2 error interrupt */
+ SPI1_IRQn = 35, /*!< spi1 global interrupt */
+ SPI2_I2S2EXT_IRQn = 36, /*!< spi2_i2s2ext global interrupt */
+ USART1_IRQn = 37, /*!< usart1 global interrupt */
+ USART2_IRQn = 38, /*!< usart2 global interrupt */
+ USART3_IRQn = 39, /*!< usart3 global interrupt */
+ EXINT15_10_IRQn = 40, /*!< external line[15:10] interrupts */
+ ERTCAlarm_IRQn = 41, /*!< ertc alarm through exint line interrupt */
+ OTGFS1_WKUP_IRQn = 42, /*!< otgfs1 wakeup from suspend through exint line interrupt */
+ TMR8_BRK_TMR12_IRQn = 43, /*!< tmr8 brake and tmr12 interrupt */
+ TMR8_OVF_TMR13_IRQn = 44, /*!< tmr8 overflow and tmr13 interrupt */
+ TMR8_TRG_HALL_TMR14_IRQn = 45, /*!< tmr8 trigger and hall and tmr14 interrupt */
+ TMR8_CH_IRQn = 46, /*!< tmr8 channel interrupt */
+ XMC_IRQn = 48, /*!< xmc global interrupt */
+ SDIO1_IRQn = 49, /*!< sdio global interrupt */
+ TMR5_GLOBAL_IRQn = 50, /*!< tmr5 global interrupt */
+ SPI3_I2S3EXT_IRQn = 51, /*!< spi3_i2s3ext global interrupt */
+ USART4_IRQn = 52, /*!< usart4 global interrupt */
+ USART5_IRQn = 53, /*!< usart5 global interrupt */
+ TMR6_DAC_GLOBAL_IRQn = 54, /*!< tmr6 and dac global interrupt */
+ TMR7_GLOBAL_IRQn = 55, /*!< tmr7 global interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< dma2 channel 1 global interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< dma2 channel 2 global interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< dma2 channel 3 global interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< dma2 channel 4 global interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< dma2 channel 5 global interrupt */
+ EMAC_IRQn = 61, /*!< emac interrupt */
+ EMAC_WKUP_IRQn = 62, /*!< emac wakeup interrupt */
+ CAN2_TX_IRQn = 63, /*!< can2 tx interrupt */
+ CAN2_RX_IRQn = 64, /*!< can2 rx interrupt */
+ CAN2_STAT_IRQn = 65, /*!< can2 state interrupt */
+ CAN2_ERR_IRQn = 66, /*!< can2 error interrupt */
+ OTGFS1_IRQn = 67, /*!< otgfs1 interrupt */
+ DMA2_Channel6_IRQn = 68, /*!< dma2 channel 6 global interrupt */
+ DMA2_Channel7_IRQn = 69, /*!< dma2 channel 7 global interrupt */
+ USART6_IRQn = 71, /*!< usart6 interrupt */
+ I2C3_EVT_IRQn = 72, /*!< i2c3 event interrupt */
+ I2C3_ERR_IRQn = 73, /*!< i2c3 error interrupt */
+ CAN3_TX_IRQn = 74, /*!< can3 tx interrupt */
+ CAN3_RX_IRQn = 75, /*!< can3 rx interrupt */
+ CAN3_STAT_IRQn = 76, /*!< can3 state interrupt */
+ CAN3_ERR_IRQn = 77, /*!< can3 error interrupt */
+ AES_IRQn = 79, /*!< aes interrupt */
+ TRNG_IRQn = 80, /*!< trng interrupt */
+ FPU_IRQn = 81, /*!< fpu interrupt */
+ USART7_IRQn = 82, /*!< usart7 interrupt */
+ USART8_IRQn = 83, /*!< usart8 interrupt */
+ SPI4_IRQn = 84, /*!< spi4 global interrupt */
+ I2SF5_IRQn = 85, /*!< i2sf5 global interrupt */
+ QSPI1_IRQn = 92, /*!< qspi1 global interrupt */
+ DMAMUX_IRQn = 94, /*!< dmamux interrupt */
+ ACC_IRQn = 103, /*!< acc interrupt */
+#endif
+
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h"
+#include "system_at32f45x.h"
+#include
+
+/** @addtogroup Exported_types
+ * @{
+ */
+
+typedef int32_t INT32;
+typedef int16_t INT16;
+typedef int8_t INT8;
+typedef uint32_t UINT32;
+typedef uint16_t UINT16;
+typedef uint8_t UINT8;
+
+typedef int32_t s32;
+typedef int16_t s16;
+typedef int8_t s8;
+
+typedef const int32_t sc32; /*!< read only */
+typedef const int16_t sc16; /*!< read only */
+typedef const int8_t sc8; /*!< read only */
+
+typedef __IO int32_t vs32;
+typedef __IO int16_t vs16;
+typedef __IO int8_t vs8;
+
+typedef __I int32_t vsc32; /*!< read only */
+typedef __I int16_t vsc16; /*!< read only */
+typedef __I int8_t vsc8; /*!< read only */
+
+typedef uint32_t u32;
+typedef uint16_t u16;
+typedef uint8_t u8;
+
+typedef const uint32_t uc32; /*!< read only */
+typedef const uint16_t uc16; /*!< read only */
+typedef const uint8_t uc8; /*!< read only */
+
+typedef __IO uint32_t vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t vu8;
+
+typedef __I uint32_t vuc32; /*!< read only */
+typedef __I uint16_t vuc16; /*!< read only */
+typedef __I uint8_t vuc8; /*!< read only */
+
+typedef enum {RESET = 0, SET = !RESET} flag_status;
+typedef enum {FALSE = 0, TRUE = !FALSE} confirm_state;
+typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+#define REG8(addr) *(volatile uint8_t *)(addr)
+#define REG16(addr) *(volatile uint16_t *)(addr)
+#define REG32(addr) *(volatile uint32_t *)(addr)
+
+#define MAKE_VALUE(reg_offset, bit_num) (((reg_offset) << 16) | (bit_num & 0x1f))
+
+#define PERIPH_REG(periph_base, value) REG32((periph_base + (value >> 16)))
+#define PERIPH_REG_BIT(value) (0x1u << (value & 0x1f))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+#define XMC_SDRAM_MEM_BASE ((uint32_t)0xC0000000)
+#define XMC_CARD_MEM_BASE ((uint32_t)0xA8000000)
+#define QSPI1_REG_BASE ((uint32_t)0xA0001000)
+#define XMC_REG_BASE ((uint32_t)0xA0000000)
+#define XMC_BANK1_REG_BASE (XMC_REG_BASE + 0x0000)
+#define XMC_BANK2_REG_BASE (XMC_REG_BASE + 0x0060)
+#define XMC_BANK3_REG_BASE (XMC_REG_BASE + 0x0080)
+#define XMC_BANK4_REG_BASE (XMC_REG_BASE + 0x00A0)
+#define XMC_SDRAM_REG_BASE (XMC_REG_BASE + 0x0140)
+#define XMC_MEM_BASE ((uint32_t)0x60000000)
+#define QSPI1_REG_BASE ((uint32_t)0xA0001000)
+#define QSPI1_MEM_BASE ((uint32_t)0x90000000)
+#define PERIPH_BASE ((uint32_t)0x40000000)
+#define SRAM_BB_BASE ((uint32_t)0x22000000)
+#define PERIPH_BB_BASE ((uint32_t)0x42000000)
+#define SRAM_BASE ((uint32_t)0x20000000)
+#define USD_BASE ((uint32_t)0x1FFFF800)
+#define OTP_DATA_BASE ((uint32_t)0x1FFFE400)
+#define OTP_LOCK_BASE ((uint32_t)0x1FFFF500)
+#define FLASH_BASE ((uint32_t)0x08000000)
+
+#define DEBUG_BASE ((uint32_t)0xE0042000)
+
+#define APB1PERIPH_BASE (PERIPH_BASE)
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH1_BASE (PERIPH_BASE + 0x20000)
+#define AHBPERIPH2_BASE (PERIPH_BASE + 0x10000000)
+
+#if defined (AT32F455xx)
+/* apb1 bus base address */
+#define USART8_BASE (APB1PERIPH_BASE + 0x7C00)
+#define USART7_BASE (APB1PERIPH_BASE + 0x7800)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+#define PWC_BASE (APB1PERIPH_BASE + 0x7000)
+#define CAN3_BASE (APB1PERIPH_BASE + 0x6C00)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define USART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define USART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define WDT_BASE (APB1PERIPH_BASE + 0x3000)
+#define WWDT_BASE (APB1PERIPH_BASE + 0x2C00)
+#define ERTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define TMR14_BASE (APB1PERIPH_BASE + 0x2000)
+#define TMR13_BASE (APB1PERIPH_BASE + 0x1C00)
+#define TMR12_BASE (APB1PERIPH_BASE + 0x1800)
+#define TMR7_BASE (APB1PERIPH_BASE + 0x1400)
+#define TMR6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TMR5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TMR4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TMR3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TMR2_BASE (APB1PERIPH_BASE + 0x0000)
+/* apb2 bus base address */
+#define I2S2EXT_BASE (APB2PERIPH_BASE + 0x7800)
+#define I2S3EXT_BASE (APB2PERIPH_BASE + 0x7C00)
+#define ACC_BASE (APB2PERIPH_BASE + 0x7400)
+#define I2SF5_BASE (APB2PERIPH_BASE + 0x5000)
+#define TMR11_BASE (APB2PERIPH_BASE + 0x4800)
+#define TMR10_BASE (APB2PERIPH_BASE + 0x4400)
+#define TMR9_BASE (APB2PERIPH_BASE + 0x4000)
+#define EXINT_BASE (APB2PERIPH_BASE + 0x3C00)
+#define SCFG_BASE (APB2PERIPH_BASE + 0x3800)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
+#define ADCCOM_BASE (APB2PERIPH_BASE + 0x2300)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
+#define TMR8_BASE (APB2PERIPH_BASE + 0x0400)
+#define TMR1_BASE (APB2PERIPH_BASE + 0x0000)
+/* ahb bus base address */
+#define SDIO1_BASE (AHBPERIPH1_BASE + 0x4C00)
+#define GPIOH_BASE (AHBPERIPH1_BASE + 0x1C00)
+#define GPIOG_BASE (AHBPERIPH1_BASE + 0x1800)
+#define GPIOF_BASE (AHBPERIPH1_BASE + 0x1400)
+#define GPIOE_BASE (AHBPERIPH1_BASE + 0x1000)
+#define GPIOD_BASE (AHBPERIPH1_BASE + 0x0C00)
+#define GPIOC_BASE (AHBPERIPH1_BASE + 0x0800)
+#define GPIOB_BASE (AHBPERIPH1_BASE + 0x0400)
+#define GPIOA_BASE (AHBPERIPH1_BASE + 0x0000)
+
+#define DMA1_BASE (AHBPERIPH1_BASE + 0x6000)
+#define DMA1_CHANNEL1_BASE (DMA1_BASE + 0x0008)
+#define DMA1_CHANNEL2_BASE (DMA1_BASE + 0x001C)
+#define DMA1_CHANNEL3_BASE (DMA1_BASE + 0x0030)
+#define DMA1_CHANNEL4_BASE (DMA1_BASE + 0x0044)
+#define DMA1_CHANNEL5_BASE (DMA1_BASE + 0x0058)
+#define DMA1_CHANNEL6_BASE (DMA1_BASE + 0x006C)
+#define DMA1_CHANNEL7_BASE (DMA1_BASE + 0x0080)
+
+#define DMA1MUX_BASE (DMA1_BASE + 0x0104)
+#define DMA1MUX_CHANNEL1_BASE (DMA1MUX_BASE)
+#define DMA1MUX_CHANNEL2_BASE (DMA1MUX_BASE + 0x0004)
+#define DMA1MUX_CHANNEL3_BASE (DMA1MUX_BASE + 0x0008)
+#define DMA1MUX_CHANNEL4_BASE (DMA1MUX_BASE + 0x000C)
+#define DMA1MUX_CHANNEL5_BASE (DMA1MUX_BASE + 0x0010)
+#define DMA1MUX_CHANNEL6_BASE (DMA1MUX_BASE + 0x0014)
+#define DMA1MUX_CHANNEL7_BASE (DMA1MUX_BASE + 0x0018)
+
+#define DMA1MUX_GENERATOR1_BASE (DMA1_BASE + 0x0120)
+#define DMA1MUX_GENERATOR2_BASE (DMA1_BASE + 0x0124)
+#define DMA1MUX_GENERATOR3_BASE (DMA1_BASE + 0x0128)
+#define DMA1MUX_GENERATOR4_BASE (DMA1_BASE + 0x012C)
+
+#define DMA2_BASE (AHBPERIPH1_BASE + 0x6400)
+#define DMA2_CHANNEL1_BASE (DMA2_BASE + 0x0008)
+#define DMA2_CHANNEL2_BASE (DMA2_BASE + 0x001C)
+#define DMA2_CHANNEL3_BASE (DMA2_BASE + 0x0030)
+#define DMA2_CHANNEL4_BASE (DMA2_BASE + 0x0044)
+#define DMA2_CHANNEL5_BASE (DMA2_BASE + 0x0058)
+#define DMA2_CHANNEL6_BASE (DMA2_BASE + 0x006C)
+#define DMA2_CHANNEL7_BASE (DMA2_BASE + 0x0080)
+
+#define DMA2MUX_BASE (DMA2_BASE + 0x0104)
+#define DMA2MUX_CHANNEL1_BASE (DMA2MUX_BASE)
+#define DMA2MUX_CHANNEL2_BASE (DMA2MUX_BASE + 0x0004)
+#define DMA2MUX_CHANNEL3_BASE (DMA2MUX_BASE + 0x0008)
+#define DMA2MUX_CHANNEL4_BASE (DMA2MUX_BASE + 0x000C)
+#define DMA2MUX_CHANNEL5_BASE (DMA2MUX_BASE + 0x0010)
+#define DMA2MUX_CHANNEL6_BASE (DMA2MUX_BASE + 0x0014)
+#define DMA2MUX_CHANNEL7_BASE (DMA2MUX_BASE + 0x0018)
+
+#define DMA2MUX_GENERATOR1_BASE (DMA2_BASE + 0x0120)
+#define DMA2MUX_GENERATOR2_BASE (DMA2_BASE + 0x0124)
+#define DMA2MUX_GENERATOR3_BASE (DMA2_BASE + 0x0128)
+#define DMA2MUX_GENERATOR4_BASE (DMA2_BASE + 0x012C)
+
+#define FLASH_REG_BASE (AHBPERIPH1_BASE + 0x3C00)
+#define CRM_BASE (AHBPERIPH1_BASE + 0x3800)
+#define CRC_BASE (AHBPERIPH1_BASE + 0x3000)
+#define OTGFS1_BASE (AHBPERIPH2_BASE + 0x00000)
+#define AES_BASE (AHBPERIPH2_BASE + 0x60000)
+#define TRNG_BASE (AHBPERIPH2_BASE + 0x60800)
+#endif
+
+#if defined (AT32F456xx)
+/* apb1 bus base address */
+#define USART8_BASE (APB1PERIPH_BASE + 0x7C00)
+#define USART7_BASE (APB1PERIPH_BASE + 0x7800)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+#define PWC_BASE (APB1PERIPH_BASE + 0x7000)
+#define CAN3_BASE (APB1PERIPH_BASE + 0x6C00)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define USART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define USART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define WDT_BASE (APB1PERIPH_BASE + 0x3000)
+#define WWDT_BASE (APB1PERIPH_BASE + 0x2C00)
+#define ERTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define TMR14_BASE (APB1PERIPH_BASE + 0x2000)
+#define TMR13_BASE (APB1PERIPH_BASE + 0x1C00)
+#define TMR12_BASE (APB1PERIPH_BASE + 0x1800)
+#define TMR7_BASE (APB1PERIPH_BASE + 0x1400)
+#define TMR6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TMR5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TMR4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TMR3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TMR2_BASE (APB1PERIPH_BASE + 0x0000)
+/* apb2 bus base address */
+#define I2S2EXT_BASE (APB2PERIPH_BASE + 0x7800)
+#define I2S3EXT_BASE (APB2PERIPH_BASE + 0x7C00)
+#define ACC_BASE (APB2PERIPH_BASE + 0x7400)
+#define I2SF5_BASE (APB2PERIPH_BASE + 0x5000)
+#define TMR11_BASE (APB2PERIPH_BASE + 0x4800)
+#define TMR10_BASE (APB2PERIPH_BASE + 0x4400)
+#define TMR9_BASE (APB2PERIPH_BASE + 0x4000)
+#define EXINT_BASE (APB2PERIPH_BASE + 0x3C00)
+#define SCFG_BASE (APB2PERIPH_BASE + 0x3800)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
+#define ADCCOM_BASE (APB2PERIPH_BASE + 0x2300)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
+#define TMR8_BASE (APB2PERIPH_BASE + 0x0400)
+#define TMR1_BASE (APB2PERIPH_BASE + 0x0000)
+/* ahb bus base address */
+#define SDIO1_BASE (AHBPERIPH1_BASE + 0x4C00)
+#define GPIOH_BASE (AHBPERIPH1_BASE + 0x1C00)
+#define GPIOG_BASE (AHBPERIPH1_BASE + 0x1800)
+#define GPIOF_BASE (AHBPERIPH1_BASE + 0x1400)
+#define GPIOE_BASE (AHBPERIPH1_BASE + 0x1000)
+#define GPIOD_BASE (AHBPERIPH1_BASE + 0x0C00)
+#define GPIOC_BASE (AHBPERIPH1_BASE + 0x0800)
+#define GPIOB_BASE (AHBPERIPH1_BASE + 0x0400)
+#define GPIOA_BASE (AHBPERIPH1_BASE + 0x0000)
+
+#define DMA1_BASE (AHBPERIPH1_BASE + 0x6000)
+#define DMA1_CHANNEL1_BASE (DMA1_BASE + 0x0008)
+#define DMA1_CHANNEL2_BASE (DMA1_BASE + 0x001C)
+#define DMA1_CHANNEL3_BASE (DMA1_BASE + 0x0030)
+#define DMA1_CHANNEL4_BASE (DMA1_BASE + 0x0044)
+#define DMA1_CHANNEL5_BASE (DMA1_BASE + 0x0058)
+#define DMA1_CHANNEL6_BASE (DMA1_BASE + 0x006C)
+#define DMA1_CHANNEL7_BASE (DMA1_BASE + 0x0080)
+
+#define DMA1MUX_BASE (DMA1_BASE + 0x0104)
+#define DMA1MUX_CHANNEL1_BASE (DMA1MUX_BASE)
+#define DMA1MUX_CHANNEL2_BASE (DMA1MUX_BASE + 0x0004)
+#define DMA1MUX_CHANNEL3_BASE (DMA1MUX_BASE + 0x0008)
+#define DMA1MUX_CHANNEL4_BASE (DMA1MUX_BASE + 0x000C)
+#define DMA1MUX_CHANNEL5_BASE (DMA1MUX_BASE + 0x0010)
+#define DMA1MUX_CHANNEL6_BASE (DMA1MUX_BASE + 0x0014)
+#define DMA1MUX_CHANNEL7_BASE (DMA1MUX_BASE + 0x0018)
+
+#define DMA1MUX_GENERATOR1_BASE (DMA1_BASE + 0x0120)
+#define DMA1MUX_GENERATOR2_BASE (DMA1_BASE + 0x0124)
+#define DMA1MUX_GENERATOR3_BASE (DMA1_BASE + 0x0128)
+#define DMA1MUX_GENERATOR4_BASE (DMA1_BASE + 0x012C)
+
+#define DMA2_BASE (AHBPERIPH1_BASE + 0x6400)
+#define DMA2_CHANNEL1_BASE (DMA2_BASE + 0x0008)
+#define DMA2_CHANNEL2_BASE (DMA2_BASE + 0x001C)
+#define DMA2_CHANNEL3_BASE (DMA2_BASE + 0x0030)
+#define DMA2_CHANNEL4_BASE (DMA2_BASE + 0x0044)
+#define DMA2_CHANNEL5_BASE (DMA2_BASE + 0x0058)
+#define DMA2_CHANNEL6_BASE (DMA2_BASE + 0x006C)
+#define DMA2_CHANNEL7_BASE (DMA2_BASE + 0x0080)
+
+#define DMA2MUX_BASE (DMA2_BASE + 0x0104)
+#define DMA2MUX_CHANNEL1_BASE (DMA2MUX_BASE)
+#define DMA2MUX_CHANNEL2_BASE (DMA2MUX_BASE + 0x0004)
+#define DMA2MUX_CHANNEL3_BASE (DMA2MUX_BASE + 0x0008)
+#define DMA2MUX_CHANNEL4_BASE (DMA2MUX_BASE + 0x000C)
+#define DMA2MUX_CHANNEL5_BASE (DMA2MUX_BASE + 0x0010)
+#define DMA2MUX_CHANNEL6_BASE (DMA2MUX_BASE + 0x0014)
+#define DMA2MUX_CHANNEL7_BASE (DMA2MUX_BASE + 0x0018)
+
+#define DMA2MUX_GENERATOR1_BASE (DMA2_BASE + 0x0120)
+#define DMA2MUX_GENERATOR2_BASE (DMA2_BASE + 0x0124)
+#define DMA2MUX_GENERATOR3_BASE (DMA2_BASE + 0x0128)
+#define DMA2MUX_GENERATOR4_BASE (DMA2_BASE + 0x012C)
+
+#define FLASH_REG_BASE (AHBPERIPH1_BASE + 0x3C00)
+#define CRM_BASE (AHBPERIPH1_BASE + 0x3800)
+#define CRC_BASE (AHBPERIPH1_BASE + 0x3000)
+#define OTGFS1_BASE (AHBPERIPH2_BASE + 0x00000)
+#define AES_BASE (AHBPERIPH2_BASE + 0x60000)
+#define TRNG_BASE (AHBPERIPH2_BASE + 0x60800)
+#endif
+
+#if defined (AT32F457xx)
+/* apb1 bus base address */
+#define USART8_BASE (APB1PERIPH_BASE + 0x7C00)
+#define USART7_BASE (APB1PERIPH_BASE + 0x7800)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+#define PWC_BASE (APB1PERIPH_BASE + 0x7000)
+#define CAN3_BASE (APB1PERIPH_BASE + 0x6C00)
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define USART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define USART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define WDT_BASE (APB1PERIPH_BASE + 0x3000)
+#define WWDT_BASE (APB1PERIPH_BASE + 0x2C00)
+#define ERTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define TMR14_BASE (APB1PERIPH_BASE + 0x2000)
+#define TMR13_BASE (APB1PERIPH_BASE + 0x1C00)
+#define TMR12_BASE (APB1PERIPH_BASE + 0x1800)
+#define TMR7_BASE (APB1PERIPH_BASE + 0x1400)
+#define TMR6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TMR5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TMR4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TMR3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TMR2_BASE (APB1PERIPH_BASE + 0x0000)
+/* apb2 bus base address */
+#define I2S2EXT_BASE (APB2PERIPH_BASE + 0x7800)
+#define I2S3EXT_BASE (APB2PERIPH_BASE + 0x7C00)
+#define ACC_BASE (APB2PERIPH_BASE + 0x7400)
+#define I2SF5_BASE (APB2PERIPH_BASE + 0x5000)
+#define TMR11_BASE (APB2PERIPH_BASE + 0x4800)
+#define TMR10_BASE (APB2PERIPH_BASE + 0x4400)
+#define TMR9_BASE (APB2PERIPH_BASE + 0x4000)
+#define EXINT_BASE (APB2PERIPH_BASE + 0x3C00)
+#define SCFG_BASE (APB2PERIPH_BASE + 0x3800)
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
+#define ADCCOM_BASE (APB2PERIPH_BASE + 0x2300)
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
+#define TMR8_BASE (APB2PERIPH_BASE + 0x0400)
+#define TMR1_BASE (APB2PERIPH_BASE + 0x0000)
+/* ahb bus base address */
+#define SDIO1_BASE (AHBPERIPH1_BASE + 0x4C00)
+#define GPIOH_BASE (AHBPERIPH1_BASE + 0x1C00)
+#define GPIOG_BASE (AHBPERIPH1_BASE + 0x1800)
+#define GPIOF_BASE (AHBPERIPH1_BASE + 0x1400)
+#define GPIOE_BASE (AHBPERIPH1_BASE + 0x1000)
+#define GPIOD_BASE (AHBPERIPH1_BASE + 0x0C00)
+#define GPIOC_BASE (AHBPERIPH1_BASE + 0x0800)
+#define GPIOB_BASE (AHBPERIPH1_BASE + 0x0400)
+#define GPIOA_BASE (AHBPERIPH1_BASE + 0x0000)
+
+#define DMA1_BASE (AHBPERIPH1_BASE + 0x6000)
+#define DMA1_CHANNEL1_BASE (DMA1_BASE + 0x0008)
+#define DMA1_CHANNEL2_BASE (DMA1_BASE + 0x001C)
+#define DMA1_CHANNEL3_BASE (DMA1_BASE + 0x0030)
+#define DMA1_CHANNEL4_BASE (DMA1_BASE + 0x0044)
+#define DMA1_CHANNEL5_BASE (DMA1_BASE + 0x0058)
+#define DMA1_CHANNEL6_BASE (DMA1_BASE + 0x006C)
+#define DMA1_CHANNEL7_BASE (DMA1_BASE + 0x0080)
+
+#define DMA1MUX_BASE (DMA1_BASE + 0x0104)
+#define DMA1MUX_CHANNEL1_BASE (DMA1MUX_BASE)
+#define DMA1MUX_CHANNEL2_BASE (DMA1MUX_BASE + 0x0004)
+#define DMA1MUX_CHANNEL3_BASE (DMA1MUX_BASE + 0x0008)
+#define DMA1MUX_CHANNEL4_BASE (DMA1MUX_BASE + 0x000C)
+#define DMA1MUX_CHANNEL5_BASE (DMA1MUX_BASE + 0x0010)
+#define DMA1MUX_CHANNEL6_BASE (DMA1MUX_BASE + 0x0014)
+#define DMA1MUX_CHANNEL7_BASE (DMA1MUX_BASE + 0x0018)
+
+#define DMA1MUX_GENERATOR1_BASE (DMA1_BASE + 0x0120)
+#define DMA1MUX_GENERATOR2_BASE (DMA1_BASE + 0x0124)
+#define DMA1MUX_GENERATOR3_BASE (DMA1_BASE + 0x0128)
+#define DMA1MUX_GENERATOR4_BASE (DMA1_BASE + 0x012C)
+
+#define DMA2_BASE (AHBPERIPH1_BASE + 0x6400)
+#define DMA2_CHANNEL1_BASE (DMA2_BASE + 0x0008)
+#define DMA2_CHANNEL2_BASE (DMA2_BASE + 0x001C)
+#define DMA2_CHANNEL3_BASE (DMA2_BASE + 0x0030)
+#define DMA2_CHANNEL4_BASE (DMA2_BASE + 0x0044)
+#define DMA2_CHANNEL5_BASE (DMA2_BASE + 0x0058)
+#define DMA2_CHANNEL6_BASE (DMA2_BASE + 0x006C)
+#define DMA2_CHANNEL7_BASE (DMA2_BASE + 0x0080)
+
+#define DMA2MUX_BASE (DMA2_BASE + 0x0104)
+#define DMA2MUX_CHANNEL1_BASE (DMA2MUX_BASE)
+#define DMA2MUX_CHANNEL2_BASE (DMA2MUX_BASE + 0x0004)
+#define DMA2MUX_CHANNEL3_BASE (DMA2MUX_BASE + 0x0008)
+#define DMA2MUX_CHANNEL4_BASE (DMA2MUX_BASE + 0x000C)
+#define DMA2MUX_CHANNEL5_BASE (DMA2MUX_BASE + 0x0010)
+#define DMA2MUX_CHANNEL6_BASE (DMA2MUX_BASE + 0x0014)
+#define DMA2MUX_CHANNEL7_BASE (DMA2MUX_BASE + 0x0018)
+
+#define DMA2MUX_GENERATOR1_BASE (DMA2_BASE + 0x0120)
+#define DMA2MUX_GENERATOR2_BASE (DMA2_BASE + 0x0124)
+#define DMA2MUX_GENERATOR3_BASE (DMA2_BASE + 0x0128)
+#define DMA2MUX_GENERATOR4_BASE (DMA2_BASE + 0x012C)
+
+#define FLASH_REG_BASE (AHBPERIPH1_BASE + 0x3C00)
+#define CRM_BASE (AHBPERIPH1_BASE + 0x3800)
+#define CRC_BASE (AHBPERIPH1_BASE + 0x3000)
+#define EMAC_BASE (AHBPERIPH1_BASE + 0x8000)
+#define OTGFS1_BASE (AHBPERIPH2_BASE + 0x00000)
+#define AES_BASE (AHBPERIPH2_BASE + 0x60000)
+#define TRNG_BASE (AHBPERIPH2_BASE + 0x60800)
+
+#define EMAC_MAC_BASE (EMAC_BASE)
+#define EMAC_MMC_BASE (EMAC_BASE + 0x0100)
+#define EMAC_PTP_BASE (EMAC_BASE + 0x0700)
+#define EMAC_DMA_BASE (EMAC_BASE + 0x1000)
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#include "at32f45x_def.h"
+#include "at32f45x_conf.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/at32f45x_conf_template.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/at32f45x_conf_template.h
new file mode 100644
index 00000000000..5c1ca553106
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/at32f45x_conf_template.h
@@ -0,0 +1,173 @@
+/**
+ **************************************************************************
+ * @file at32f45x_conf.h
+ * @brief at32f45x config header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_CONF_H
+#define __AT32F45x_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief in the following line adjust the value of high speed external crystal (hext)
+ * used in your application
+ *
+ * tip: to avoid modifying this file each time you need to use different hext, you
+ * can define the hext value in your toolchain compiler preprocessor.
+ *
+ */
+#if !defined HEXT_VALUE
+#define HEXT_VALUE ((uint32_t)8000000) /*!< value of the high speed external crystal in hz */
+#endif
+
+/**
+ * @brief in the following line adjust the high speed external crystal (hext) startup
+ * timeout value
+ */
+#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
+#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
+#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed external clock in hz */
+
+/* module define -------------------------------------------------------------*/
+#define ACC_MODULE_ENABLED
+#define ADC_MODULE_ENABLED
+#define AES_MODULE_ENABLED
+#define CAN_MODULE_ENABLED
+#define CRC_MODULE_ENABLED
+#define CRM_MODULE_ENABLED
+#define DAC_MODULE_ENABLED
+#define DEBUG_MODULE_ENABLED
+#define DMA_MODULE_ENABLED
+#define EMAC_MODULE_ENABLED
+#define ERTC_MODULE_ENABLED
+#define EXINT_MODULE_ENABLED
+#define FLASH_MODULE_ENABLED
+#define GPIO_MODULE_ENABLED
+#define I2C_MODULE_ENABLED
+#define MISC_MODULE_ENABLED
+#define PWC_MODULE_ENABLED
+#define QSPI_MODULE_ENABLED
+#define SCFG_MODULE_ENABLED
+#define SDIO_MODULE_ENABLED
+#define SPI_MODULE_ENABLED
+#define TMR_MODULE_ENABLED
+#define TRNG_MODULE_ENABLED
+#define USART_MODULE_ENABLED
+#define USB_MODULE_ENABLED
+#define WWDT_MODULE_ENABLED
+#define WDT_MODULE_ENABLED
+#define XMC_MODULE_ENABLED
+
+/* includes ------------------------------------------------------------------*/
+#ifdef ACC_MODULE_ENABLED
+#include "at32f45x_acc.h"
+#endif
+#ifdef ADC_MODULE_ENABLED
+#include "at32f45x_adc.h"
+#endif
+#ifdef AES_MODULE_ENABLED
+#include "at32f45x_aes.h"
+#endif
+#ifdef CAN_MODULE_ENABLED
+#include "at32f45x_can.h"
+#endif
+#ifdef CRC_MODULE_ENABLED
+#include "at32f45x_crc.h"
+#endif
+#ifdef CRM_MODULE_ENABLED
+#include "at32f45x_crm.h"
+#endif
+#ifdef DAC_MODULE_ENABLED
+#include "at32f45x_dac.h"
+#endif
+#ifdef DEBUG_MODULE_ENABLED
+#include "at32f45x_debug.h"
+#endif
+#ifdef DMA_MODULE_ENABLED
+#include "at32f45x_dma.h"
+#endif
+#ifdef EMAC_MODULE_ENABLED
+#include "at32f45x_emac.h"
+#endif
+#ifdef ERTC_MODULE_ENABLED
+#include "at32f45x_ertc.h"
+#endif
+#ifdef EXINT_MODULE_ENABLED
+#include "at32f45x_exint.h"
+#endif
+#ifdef FLASH_MODULE_ENABLED
+#include "at32f45x_flash.h"
+#endif
+#ifdef GPIO_MODULE_ENABLED
+#include "at32f45x_gpio.h"
+#endif
+#ifdef I2C_MODULE_ENABLED
+#include "at32f45x_i2c.h"
+#endif
+#ifdef MISC_MODULE_ENABLED
+#include "at32f45x_misc.h"
+#endif
+#ifdef PWC_MODULE_ENABLED
+#include "at32f45x_pwc.h"
+#endif
+#ifdef QSPI_MODULE_ENABLED
+#include "at32f45x_qspi.h"
+#endif
+#ifdef SCFG_MODULE_ENABLED
+#include "at32f45x_scfg.h"
+#endif
+#ifdef SDIO_MODULE_ENABLED
+#include "at32f45x_sdio.h"
+#endif
+#ifdef SPI_MODULE_ENABLED
+#include "at32f45x_spi.h"
+#endif
+#ifdef TMR_MODULE_ENABLED
+#include "at32f45x_tmr.h"
+#endif
+#ifdef TRNG_MODULE_ENABLED
+#include "at32f45x_trng.h"
+#endif
+#ifdef USART_MODULE_ENABLED
+#include "at32f45x_usart.h"
+#endif
+#ifdef USB_MODULE_ENABLED
+#include "at32f45x_usb.h"
+#endif
+#ifdef WDT_MODULE_ENABLED
+#include "at32f45x_wdt.h"
+#endif
+#ifdef WWDT_MODULE_ENABLED
+#include "at32f45x_wwdt.h"
+#endif
+#ifdef XMC_MODULE_ENABLED
+#include "at32f45x_xmc.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/gcc/linker/AT32F455xC_FLASH.ld b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/gcc/linker/AT32F455xC_FLASH.ld
new file mode 100644
index 00000000000..d66c113c186
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/gcc/linker/AT32F455xC_FLASH.ld
@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+** File : AT32F455xC_FLASH.ld
+**
+** Abstract : Linker script for AT32F455xC Device with
+** 256KByte FLASH, 108KByte RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : Artery Tek AT32
+**
+** Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x2001B000; /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 108K
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/gcc/linker/AT32F455xE_FLASH.ld b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/gcc/linker/AT32F455xE_FLASH.ld
new file mode 100644
index 00000000000..348bf88c5d6
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/gcc/linker/AT32F455xE_FLASH.ld
@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+** File : AT32F455xE_FLASH.ld
+**
+** Abstract : Linker script for AT32F455xE Device with
+** 512KByte FLASH, 144KByte RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : Artery Tek AT32
+**
+** Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20024000; /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 144K
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/gcc/linker/AT32F456xC_FLASH.ld b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/gcc/linker/AT32F456xC_FLASH.ld
new file mode 100644
index 00000000000..ef709dc9cd2
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/gcc/linker/AT32F456xC_FLASH.ld
@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+** File : AT32F456xC_FLASH.ld
+**
+** Abstract : Linker script for AT32F456xC Device with
+** 256KByte FLASH, 108KByte RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : Artery Tek AT32
+**
+** Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x2001B000; /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 108K
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/gcc/linker/AT32F456xE_FLASH.ld b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/gcc/linker/AT32F456xE_FLASH.ld
new file mode 100644
index 00000000000..2fd05b75dc0
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/gcc/linker/AT32F456xE_FLASH.ld
@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+** File : AT32F456xE_FLASH.ld
+**
+** Abstract : Linker script for AT32F456xE Device with
+** 512KByte FLASH, 144KByte RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : Artery Tek AT32
+**
+** Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20024000; /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 144K
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/gcc/linker/AT32F457xC_FLASH.ld b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/gcc/linker/AT32F457xC_FLASH.ld
new file mode 100644
index 00000000000..3fa46f539ec
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/gcc/linker/AT32F457xC_FLASH.ld
@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+** File : AT32F457xC_FLASH.ld
+**
+** Abstract : Linker script for AT32F457xC Device with
+** 256KByte FLASH, 108KByte RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : Artery Tek AT32
+**
+** Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x2001B000; /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 108K
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/gcc/linker/AT32F457xE_FLASH.ld b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/gcc/linker/AT32F457xE_FLASH.ld
new file mode 100644
index 00000000000..5179c8b6794
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/gcc/linker/AT32F457xE_FLASH.ld
@@ -0,0 +1,154 @@
+/*
+*****************************************************************************
+**
+** File : AT32F457xE_FLASH.ld
+**
+** Abstract : Linker script for AT32F457xE Device with
+** 512KByte FLASH, 144KByte RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used.
+**
+** Target : Artery Tek AT32
+**
+** Environment : Arm gcc toolchain
+**
+*****************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = 0x20024000; /* end of RAM */
+
+/* Generate a link error if heap and stack don't fit into RAM */
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
+RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 144K
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into FLASH */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data goes into FLASH */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data goes into FLASH */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } >FLASH
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH
+
+ /* used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss secion */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the standard libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/gcc/startup_at32f45x.s b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/gcc/startup_at32f45x.s
new file mode 100644
index 00000000000..902d01eccda
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/gcc/startup_at32f45x.s
@@ -0,0 +1,528 @@
+/**
+ ******************************************************************************
+ * @file startup_at32f45x.s
+ * @brief at32f45x devices vector table for gcc toolchain.
+ * this module performs:
+ * - set the initial sp
+ * - set the initial pc == reset_handler,
+ * - set the vector table entries with the exceptions isr address
+ * - configure the clock system and the external sram to
+ * be used as data memory (optional, to be enabled by user)
+ * - branches to main in the c library (which eventually
+ * calls main()).
+ * after reset the cortex-m4 processor is in thread mode,
+ * priority is privileged, and the stack is set to main.
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+// bl __libc_init_array
+/* Call the application's entry point.*/
+ bl entry
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDT_IRQHandler /* Window Watchdog Timer */
+ .word PVM_IRQHandler /* PVM through EXINT Line detect */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXINT line */
+ .word ERTC_WKUP_IRQHandler /* ERTC Wakeup through the EXINT line */
+ .word FLASH_IRQHandler /* Flash */
+ .word CRM_IRQHandler /* CRM */
+ .word EXINT0_IRQHandler /* EXINT Line 0 */
+ .word EXINT1_IRQHandler /* EXINT Line 1 */
+ .word EXINT2_IRQHandler /* EXINT Line 2 */
+ .word EXINT3_IRQHandler /* EXINT Line 3 */
+ .word EXINT4_IRQHandler /* EXINT Line 4 */
+ .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
+ .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
+ .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
+ .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
+ .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
+ .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
+ .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
+ .word ADC1_2_IRQHandler /* ADC1 & ADC2 */
+ .word CAN1_TX_IRQHandler /* CAN1 TX */
+ .word CAN1_RX_IRQHandler /* CAN1 RX */
+ .word CAN1_STAT_IRQHandler /* CAN1 State */
+ .word CAN1_ERR_IRQHandler /* CAN1 Error */
+ .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */
+ .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */
+ .word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */
+ .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */
+ .word TMR1_CH_IRQHandler /* TMR1 Channel */
+ .word TMR2_GLOBAL_IRQHandler /* TMR2 */
+ .word TMR3_GLOBAL_IRQHandler /* TMR3 */
+ .word TMR4_GLOBAL_IRQHandler /* TMR4 */
+ .word I2C1_EVT_IRQHandler /* I2C1 Event */
+ .word I2C1_ERR_IRQHandler /* I2C1 Error */
+ .word I2C2_EVT_IRQHandler /* I2C2 Event */
+ .word I2C2_ERR_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_I2S2EXT_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */
+ .word ERTCAlarm_IRQHandler /* ERTC Alarm through EXINT Line */
+ .word OTGFS1_WKUP_IRQHandler /* OTGFS1 Wakeup from suspend */
+ .word TMR8_BRK_TMR12_IRQHandler /* TMR8 Brake and TMR12 */
+ .word TMR8_OVF_TMR13_IRQHandler /* TMR8 Overflow and TMR13 */
+ .word TMR8_TRG_HALL_TMR14_IRQHandler /* TMR8 Trigger and hall and TMR14 */
+ .word TMR8_CH_IRQHandler /* TMR8 Channel */
+ .word 0 /* Reserved */
+ .word XMC_IRQHandler /* XMC */
+ .word SDIO1_IRQHandler /* SDIO1 */
+ .word TMR5_GLOBAL_IRQHandler /* TMR5 */
+ .word SPI3_I2S3EXT_IRQHandler /* SPI3 */
+ .word USART4_IRQHandler /* USART4 */
+ .word USART5_IRQHandler /* USART5 */
+ .word TMR6_DAC_GLOBAL_IRQHandler /* TMR6 & DAC */
+ .word TMR7_GLOBAL_IRQHandler /* TMR7 */
+ .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */
+ .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */
+ .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */
+ .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */
+ .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */
+ .word EMAC_IRQHandler /* EMAC */
+ .word EMAC_WKUP_IRQHandler /* EMAC Wakeup */
+ .word CAN2_TX_IRQHandler /* CAN2 TX */
+ .word CAN2_RX_IRQHandler /* CAN2 RX */
+ .word CAN2_STAT_IRQHandler /* CAN2 State */
+ .word CAN2_ERR_IRQHandler /* CAN2 Error */
+ .word OTGFS1_IRQHandler /* OTGFS1 */
+ .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */
+ .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */
+ .word 0 /* Reserved */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EVT_IRQHandler /* I2C3 Event */
+ .word I2C3_ERR_IRQHandler /* I2C3 Error */
+ .word CAN3_TX_IRQHandler /* CAN3 TX */
+ .word CAN3_RX_IRQHandler /* CAN3 RX */
+ .word CAN3_STAT_IRQHandler /* CAN3 State */
+ .word CAN3_ERR_IRQHandler /* CAN3 Error */
+ .word 0 /* Reserved */
+ .word AES_IRQHandler /* AES */
+ .word TRNG_IRQHandler /* TRNG */
+ .word FPU_IRQHandler /* FPU */
+ .word USART7_IRQHandler /* USART7 */
+ .word USART8_IRQHandler /* USART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word I2SF5_IRQHandler /* I2SF5 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word QSPI1_IRQHandler /* QSPI1 */
+ .word 0 /* Reserved */
+ .word DMAMUX_IRQHandler /* DMAMUX */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word ACC_IRQHandler /* ACC */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDT_IRQHandler
+ .thumb_set WWDT_IRQHandler,Default_Handler
+
+ .weak PVM_IRQHandler
+ .thumb_set PVM_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak ERTC_WKUP_IRQHandler
+ .thumb_set ERTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak CRM_IRQHandler
+ .thumb_set CRM_IRQHandler,Default_Handler
+
+ .weak EXINT0_IRQHandler
+ .thumb_set EXINT0_IRQHandler,Default_Handler
+
+ .weak EXINT1_IRQHandler
+ .thumb_set EXINT1_IRQHandler,Default_Handler
+
+ .weak EXINT2_IRQHandler
+ .thumb_set EXINT2_IRQHandler,Default_Handler
+
+ .weak EXINT3_IRQHandler
+ .thumb_set EXINT3_IRQHandler,Default_Handler
+
+ .weak EXINT4_IRQHandler
+ .thumb_set EXINT4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak CAN1_TX_IRQHandler
+ .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+ .weak CAN1_RX_IRQHandler
+ .thumb_set CAN1_RX_IRQHandler,Default_Handler
+
+ .weak CAN1_STAT_IRQHandler
+ .thumb_set CAN1_STAT_IRQHandler,Default_Handler
+
+ .weak CAN1_ERR_IRQHandler
+ .thumb_set CAN1_ERR_IRQHandler,Default_Handler
+
+ .weak EXINT9_5_IRQHandler
+ .thumb_set EXINT9_5_IRQHandler,Default_Handler
+
+ .weak TMR1_BRK_TMR9_IRQHandler
+ .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
+
+ .weak TMR1_OVF_TMR10_IRQHandler
+ .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler
+
+ .weak TMR1_TRG_HALL_TMR11_IRQHandler
+ .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler
+
+ .weak TMR1_CH_IRQHandler
+ .thumb_set TMR1_CH_IRQHandler,Default_Handler
+
+ .weak TMR2_GLOBAL_IRQHandler
+ .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
+
+ .weak TMR3_GLOBAL_IRQHandler
+ .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
+
+ .weak TMR4_GLOBAL_IRQHandler
+ .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
+
+ .weak I2C1_EVT_IRQHandler
+ .thumb_set I2C1_EVT_IRQHandler,Default_Handler
+
+ .weak I2C1_ERR_IRQHandler
+ .thumb_set I2C1_ERR_IRQHandler,Default_Handler
+
+ .weak I2C2_EVT_IRQHandler
+ .thumb_set I2C2_EVT_IRQHandler,Default_Handler
+
+ .weak I2C2_ERR_IRQHandler
+ .thumb_set I2C2_ERR_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_I2S2EXT_IRQHandler
+ .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXINT15_10_IRQHandler
+ .thumb_set EXINT15_10_IRQHandler,Default_Handler
+
+ .weak ERTCAlarm_IRQHandler
+ .thumb_set ERTCAlarm_IRQHandler,Default_Handler
+
+ .weak OTGFS1_WKUP_IRQHandler
+ .thumb_set OTGFS1_WKUP_IRQHandler,Default_Handler
+
+ .weak TMR8_BRK_TMR12_IRQHandler
+ .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
+
+ .weak TMR8_OVF_TMR13_IRQHandler
+ .thumb_set TMR8_OVF_TMR13_IRQHandler,Default_Handler
+
+ .weak TMR8_TRG_HALL_TMR14_IRQHandler
+ .thumb_set TMR8_TRG_HALL_TMR14_IRQHandler,Default_Handler
+
+ .weak TMR8_CH_IRQHandler
+ .thumb_set TMR8_CH_IRQHandler,Default_Handler
+
+ .weak XMC_IRQHandler
+ .thumb_set XMC_IRQHandler,Default_Handler
+
+ .weak SDIO1_IRQHandler
+ .thumb_set SDIO1_IRQHandler,Default_Handler
+
+ .weak TMR5_GLOBAL_IRQHandler
+ .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
+
+ .weak SPI3_I2S3EXT_IRQHandler
+ .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler
+
+ .weak USART4_IRQHandler
+ .thumb_set USART4_IRQHandler,Default_Handler
+
+ .weak USART5_IRQHandler
+ .thumb_set USART5_IRQHandler,Default_Handler
+
+ .weak TMR6_DAC_GLOBAL_IRQHandler
+ .thumb_set TMR6_DAC_GLOBAL_IRQHandler,Default_Handler
+
+ .weak TMR7_GLOBAL_IRQHandler
+ .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak EMAC_IRQHandler
+ .thumb_set EMAC_IRQHandler,Default_Handler
+
+ .weak EMAC_WKUP_IRQHandler
+ .thumb_set EMAC_WKUP_IRQHandler,Default_Handler
+
+ .weak CAN2_TX_IRQHandler
+ .thumb_set CAN2_TX_IRQHandler,Default_Handler
+
+ .weak CAN2_RX_IRQHandler
+ .thumb_set CAN2_RX_IRQHandler,Default_Handler
+
+ .weak CAN2_STAT_IRQHandler
+ .thumb_set CAN2_STAT_IRQHandler,Default_Handler
+
+ .weak CAN2_ERR_IRQHandler
+ .thumb_set CAN2_ERR_IRQHandler,Default_Handler
+
+ .weak OTGFS1_IRQHandler
+ .thumb_set OTGFS1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel6_IRQHandler
+ .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel7_IRQHandler
+ .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EVT_IRQHandler
+ .thumb_set I2C3_EVT_IRQHandler,Default_Handler
+
+ .weak I2C3_ERR_IRQHandler
+ .thumb_set I2C3_ERR_IRQHandler,Default_Handler
+
+ .weak CAN3_TX_IRQHandler
+ .thumb_set CAN3_TX_IRQHandler,Default_Handler
+
+ .weak CAN3_RX_IRQHandler
+ .thumb_set CAN3_RX_IRQHandler,Default_Handler
+
+ .weak CAN3_STAT_IRQHandler
+ .thumb_set CAN3_STAT_IRQHandler,Default_Handler
+
+ .weak CAN3_ERR_IRQHandler
+ .thumb_set CAN3_ERR_IRQHandler,Default_Handler
+
+ .weak AES_IRQHandler
+ .thumb_set AES_IRQHandler,Default_Handler
+
+ .weak TRNG_IRQHandler
+ .thumb_set TRNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak USART7_IRQHandler
+ .thumb_set USART7_IRQHandler,Default_Handler
+
+ .weak USART8_IRQHandler
+ .thumb_set USART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak I2SF5_IRQHandler
+ .thumb_set I2SF5_IRQHandler,Default_Handler
+
+ .weak QSPI1_IRQHandler
+ .thumb_set QSPI1_IRQHandler,Default_Handler
+
+ .weak DMAMUX_IRQHandler
+ .thumb_set DMAMUX_IRQHandler,Default_Handler
+
+ .weak ACC_IRQHandler
+ .thumb_set ACC_IRQHandler,Default_Handler
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F455xC.icf b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F455xC.icf
new file mode 100644
index 00000000000..d376dc0ce7f
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F455xC.icf
@@ -0,0 +1,30 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001AFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x1000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F455xE.icf b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F455xE.icf
new file mode 100644
index 00000000000..0c6fa12edcf
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F455xE.icf
@@ -0,0 +1,30 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20023FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x1000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F456xC.icf b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F456xC.icf
new file mode 100644
index 00000000000..d376dc0ce7f
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F456xC.icf
@@ -0,0 +1,30 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001AFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x1000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F456xE.icf b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F456xE.icf
new file mode 100644
index 00000000000..0c6fa12edcf
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F456xE.icf
@@ -0,0 +1,30 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20023FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x1000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F457xC.icf b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F457xC.icf
new file mode 100644
index 00000000000..d376dc0ce7f
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F457xC.icf
@@ -0,0 +1,30 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x2001AFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x1000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F457xE.icf b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F457xE.icf
new file mode 100644
index 00000000000..0c6fa12edcf
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/iar/linker/AT32F457xE.icf
@@ -0,0 +1,30 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20023FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x1000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
\ No newline at end of file
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/iar/startup_at32f45x.s b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/iar/startup_at32f45x.s
new file mode 100644
index 00000000000..fca3baa6e2a
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/iar/startup_at32f45x.s
@@ -0,0 +1,639 @@
+;**************************************************************************
+;* @file startup_at32f45x.s
+;* @brief at32f45x startup file for IAR Systems
+;**************************************************************************
+;
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDT_IRQHandler ; Window Watchdog Timer
+ DCD PVM_IRQHandler ; PVM through EXINT Line detect
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXINT line
+ DCD ERTC_WKUP_IRQHandler ; ERTC Wakeup through the EXINT line
+ DCD FLASH_IRQHandler ; Flash
+ DCD CRM_IRQHandler ; CRM
+ DCD EXINT0_IRQHandler ; EXINT Line 0
+ DCD EXINT1_IRQHandler ; EXINT Line 1
+ DCD EXINT2_IRQHandler ; EXINT Line 2
+ DCD EXINT3_IRQHandler ; EXINT Line 3
+ DCD EXINT4_IRQHandler ; EXINT Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 & ADC2
+ DCD CAN1_TX_IRQHandler ; CAN1 TX
+ DCD CAN1_RX_IRQHandler ; CAN1 RX
+ DCD CAN1_STAT_IRQHandler ; CAN1 State
+ DCD CAN1_ERR_IRQHandler ; CAN1 Error
+ DCD EXINT9_5_IRQHandler ; EXINT Line [9:5]
+ DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Brake and TMR9
+ DCD TMR1_OVF_TMR10_IRQHandler ; TMR1 Overflow and TMR10
+ DCD TMR1_TRG_HALL_TMR11_IRQHandler ; TMR1 Trigger and hall and TMR11
+ DCD TMR1_CH_IRQHandler ; TMR1 Channel
+ DCD TMR2_GLOBAL_IRQHandler ; TMR2
+ DCD TMR3_GLOBAL_IRQHandler ; TMR3
+ DCD TMR4_GLOBAL_IRQHandler ; TMR4
+ DCD I2C1_EVT_IRQHandler ; I2C1 Event
+ DCD I2C1_ERR_IRQHandler ; I2C1 Error
+ DCD I2C2_EVT_IRQHandler ; I2C2 Event
+ DCD I2C2_ERR_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_I2S2EXT_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXINT15_10_IRQHandler ; EXINT Line [15:10]
+ DCD ERTCAlarm_IRQHandler ; ERTC Alarm through EXINT Line
+ DCD OTGFS1_WKUP_IRQHandler ; OTGFS1 Wakeup from suspend
+ DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Brake and TMR12
+ DCD TMR8_OVF_TMR13_IRQHandler ; TMR8 Overflow and TMR13
+ DCD TMR8_TRG_HALL_TMR14_IRQHandler ; TMR8 Trigger and hall and TMR14
+ DCD TMR8_CH_IRQHandler ; TMR8 Channel
+ DCD 0 ; Reserved
+ DCD XMC_IRQHandler ; XMC
+ DCD SDIO1_IRQHandler ; SDIO1
+ DCD TMR5_GLOBAL_IRQHandler ; TMR5
+ DCD SPI3_I2S3EXT_IRQHandler ; SPI3
+ DCD USART4_IRQHandler ; USART4
+ DCD USART5_IRQHandler ; USART5
+ DCD TMR6_DAC_GLOBAL_IRQHandler ; TMR6 & DAC
+ DCD TMR7_GLOBAL_IRQHandler ; TMR7
+ DCD DMA2_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA2_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA2_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA2_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA2_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD EMAC_IRQHandler ; EMAC
+ DCD EMAC_WKUP_IRQHandler ; EMAC Wakeup
+ DCD CAN2_TX_IRQHandler ; CAN2 TX
+ DCD CAN2_RX_IRQHandler ; CAN2 RX
+ DCD CAN2_STAT_IRQHandler ; CAN2 State
+ DCD CAN2_ERR_IRQHandler ; CAN2 Error
+ DCD OTGFS1_IRQHandler ; OTGFS1
+ DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
+ DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
+ DCD 0 ; Reserved
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EVT_IRQHandler ; I2C3 Event
+ DCD I2C3_ERR_IRQHandler ; I2C3 Error
+ DCD CAN3_TX_IRQHandler ; CAN3 TX
+ DCD CAN3_RX_IRQHandler ; CAN3 RX
+ DCD CAN3_STAT_IRQHandler ; CAN3 State
+ DCD CAN3_ERR_IRQHandler ; CAN3 Error
+ DCD 0 ; Reserved
+ DCD AES_IRQHandler ; AES
+ DCD TRNG_IRQHandler ; TRNG
+ DCD FPU_IRQHandler ; FPU
+ DCD USART7_IRQHandler ; USART7
+ DCD USART8_IRQHandler ; USART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD I2SF5_IRQHandler ; I2SF5
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD QSPI1_IRQHandler ; QSPI1
+ DCD 0 ; Reserved
+ DCD DMAMUX_IRQHandler ; DMAMUX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD ACC_IRQHandler ; ACC
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDT_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+WWDT_IRQHandler
+ B WWDT_IRQHandler
+
+ PUBWEAK PVM_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+PVM_IRQHandler
+ B PVM_IRQHandler
+
+ PUBWEAK TAMP_STAMP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TAMP_STAMP_IRQHandler
+ B TAMP_STAMP_IRQHandler
+
+ PUBWEAK ERTC_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ERTC_WKUP_IRQHandler
+ B ERTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK CRM_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CRM_IRQHandler
+ B CRM_IRQHandler
+
+ PUBWEAK EXINT0_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXINT0_IRQHandler
+ B EXINT0_IRQHandler
+
+ PUBWEAK EXINT1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXINT1_IRQHandler
+ B EXINT1_IRQHandler
+
+ PUBWEAK EXINT2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXINT2_IRQHandler
+ B EXINT2_IRQHandler
+
+ PUBWEAK EXINT3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXINT3_IRQHandler
+ B EXINT3_IRQHandler
+
+ PUBWEAK EXINT4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXINT4_IRQHandler
+ B EXINT4_IRQHandler
+
+ PUBWEAK DMA1_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel1_IRQHandler
+ B DMA1_Channel1_IRQHandler
+
+ PUBWEAK DMA1_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel2_IRQHandler
+ B DMA1_Channel2_IRQHandler
+
+ PUBWEAK DMA1_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel3_IRQHandler
+ B DMA1_Channel3_IRQHandler
+
+ PUBWEAK DMA1_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel4_IRQHandler
+ B DMA1_Channel4_IRQHandler
+
+ PUBWEAK DMA1_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel5_IRQHandler
+ B DMA1_Channel5_IRQHandler
+
+ PUBWEAK DMA1_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel6_IRQHandler
+ B DMA1_Channel6_IRQHandler
+
+ PUBWEAK DMA1_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel7_IRQHandler
+ B DMA1_Channel7_IRQHandler
+
+ PUBWEAK ADC1_2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ADC1_2_IRQHandler
+ B ADC1_2_IRQHandler
+
+ PUBWEAK CAN1_TX_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_TX_IRQHandler
+ B CAN1_TX_IRQHandler
+
+ PUBWEAK CAN1_RX_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_RX_IRQHandler
+ B CAN1_RX_IRQHandler
+
+ PUBWEAK CAN1_STAT_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_STAT_IRQHandler
+ B CAN1_STAT_IRQHandler
+
+ PUBWEAK CAN1_ERR_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN1_ERR_IRQHandler
+ B CAN1_ERR_IRQHandler
+
+ PUBWEAK EXINT9_5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXINT9_5_IRQHandler
+ B EXINT9_5_IRQHandler
+
+ PUBWEAK TMR1_BRK_TMR9_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_BRK_TMR9_IRQHandler
+ B TMR1_BRK_TMR9_IRQHandler
+
+ PUBWEAK TMR1_OVF_TMR10_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_OVF_TMR10_IRQHandler
+ B TMR1_OVF_TMR10_IRQHandler
+
+ PUBWEAK TMR1_TRG_HALL_TMR11_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_TRG_HALL_TMR11_IRQHandler
+ B TMR1_TRG_HALL_TMR11_IRQHandler
+
+ PUBWEAK TMR1_CH_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_CH_IRQHandler
+ B TMR1_CH_IRQHandler
+
+ PUBWEAK TMR2_GLOBAL_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR2_GLOBAL_IRQHandler
+ B TMR2_GLOBAL_IRQHandler
+
+ PUBWEAK TMR3_GLOBAL_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR3_GLOBAL_IRQHandler
+ B TMR3_GLOBAL_IRQHandler
+
+ PUBWEAK TMR4_GLOBAL_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR4_GLOBAL_IRQHandler
+ B TMR4_GLOBAL_IRQHandler
+
+ PUBWEAK I2C1_EVT_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_EVT_IRQHandler
+ B I2C1_EVT_IRQHandler
+
+ PUBWEAK I2C1_ERR_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_ERR_IRQHandler
+ B I2C1_ERR_IRQHandler
+
+ PUBWEAK I2C2_EVT_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_EVT_IRQHandler
+ B I2C2_EVT_IRQHandler
+
+ PUBWEAK I2C2_ERR_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_ERR_IRQHandler
+ B I2C2_ERR_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_I2S2EXT_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI2_I2S2EXT_IRQHandler
+ B SPI2_I2S2EXT_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXINT15_10_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EXINT15_10_IRQHandler
+ B EXINT15_10_IRQHandler
+
+ PUBWEAK ERTCAlarm_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ERTCAlarm_IRQHandler
+ B ERTCAlarm_IRQHandler
+
+ PUBWEAK OTGFS1_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+OTGFS1_WKUP_IRQHandler
+ B OTGFS1_WKUP_IRQHandler
+
+ PUBWEAK TMR8_BRK_TMR12_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR8_BRK_TMR12_IRQHandler
+ B TMR8_BRK_TMR12_IRQHandler
+
+ PUBWEAK TMR8_OVF_TMR13_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR8_OVF_TMR13_IRQHandler
+ B TMR8_OVF_TMR13_IRQHandler
+
+ PUBWEAK TMR8_TRG_HALL_TMR14_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR8_TRG_HALL_TMR14_IRQHandler
+ B TMR8_TRG_HALL_TMR14_IRQHandler
+
+ PUBWEAK TMR8_CH_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR8_CH_IRQHandler
+ B TMR8_CH_IRQHandler
+
+ PUBWEAK XMC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+XMC_IRQHandler
+ B XMC_IRQHandler
+
+ PUBWEAK SDIO1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SDIO1_IRQHandler
+ B SDIO1_IRQHandler
+
+ PUBWEAK TMR5_GLOBAL_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR5_GLOBAL_IRQHandler
+ B TMR5_GLOBAL_IRQHandler
+
+ PUBWEAK SPI3_I2S3EXT_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI3_I2S3EXT_IRQHandler
+ B SPI3_I2S3EXT_IRQHandler
+
+ PUBWEAK USART4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART4_IRQHandler
+ B USART4_IRQHandler
+
+ PUBWEAK USART5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART5_IRQHandler
+ B USART5_IRQHandler
+
+ PUBWEAK TMR6_DAC_GLOBAL_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR6_DAC_GLOBAL_IRQHandler
+ B TMR6_DAC_GLOBAL_IRQHandler
+
+ PUBWEAK TMR7_GLOBAL_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TMR7_GLOBAL_IRQHandler
+ B TMR7_GLOBAL_IRQHandler
+
+ PUBWEAK DMA2_Channel1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel1_IRQHandler
+ B DMA2_Channel1_IRQHandler
+
+ PUBWEAK DMA2_Channel2_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel2_IRQHandler
+ B DMA2_Channel2_IRQHandler
+
+ PUBWEAK DMA2_Channel3_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel3_IRQHandler
+ B DMA2_Channel3_IRQHandler
+
+ PUBWEAK DMA2_Channel4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel4_IRQHandler
+ B DMA2_Channel4_IRQHandler
+
+ PUBWEAK DMA2_Channel5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel5_IRQHandler
+ B DMA2_Channel5_IRQHandler
+
+ PUBWEAK EMAC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EMAC_IRQHandler
+ B EMAC_IRQHandler
+
+ PUBWEAK EMAC_WKUP_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+EMAC_WKUP_IRQHandler
+ B EMAC_WKUP_IRQHandler
+
+ PUBWEAK CAN2_TX_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_TX_IRQHandler
+ B CAN2_TX_IRQHandler
+
+ PUBWEAK CAN2_RX_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_RX_IRQHandler
+ B CAN2_RX_IRQHandler
+
+ PUBWEAK CAN2_STAT_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_STAT_IRQHandler
+ B CAN2_STAT_IRQHandler
+
+ PUBWEAK CAN2_ERR_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN2_ERR_IRQHandler
+ B CAN2_ERR_IRQHandler
+
+ PUBWEAK OTGFS1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+OTGFS1_IRQHandler
+ B OTGFS1_IRQHandler
+
+ PUBWEAK DMA2_Channel6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel6_IRQHandler
+ B DMA2_Channel6_IRQHandler
+
+ PUBWEAK DMA2_Channel7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMA2_Channel7_IRQHandler
+ B DMA2_Channel7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EVT_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C3_EVT_IRQHandler
+ B I2C3_EVT_IRQHandler
+
+ PUBWEAK I2C3_ERR_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2C3_ERR_IRQHandler
+ B I2C3_ERR_IRQHandler
+
+ PUBWEAK CAN3_TX_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN3_TX_IRQHandler
+ B CAN3_TX_IRQHandler
+
+ PUBWEAK CAN3_RX_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN3_RX_IRQHandler
+ B CAN3_RX_IRQHandler
+
+ PUBWEAK CAN3_STAT_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN3_STAT_IRQHandler
+ B CAN3_STAT_IRQHandler
+
+ PUBWEAK CAN3_ERR_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+CAN3_ERR_IRQHandler
+ B CAN3_ERR_IRQHandler
+
+ PUBWEAK AES_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+AES_IRQHandler
+ B AES_IRQHandler
+
+ PUBWEAK TRNG_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+TRNG_IRQHandler
+ B TRNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK USART7_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART7_IRQHandler
+ B USART7_IRQHandler
+
+ PUBWEAK USART8_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+USART8_IRQHandler
+ B USART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK I2SF5_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+I2SF5_IRQHandler
+ B I2SF5_IRQHandler
+
+ PUBWEAK QSPI1_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+QSPI1_IRQHandler
+ B QSPI1_IRQHandler
+
+ PUBWEAK DMAMUX_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+DMAMUX_IRQHandler
+ B DMAMUX_IRQHandler
+
+ PUBWEAK ACC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ACC_IRQHandler
+ B ACC_IRQHandler
+
+ END
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/mdk/startup_at32f45x.s b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/mdk/startup_at32f45x.s
new file mode 100644
index 00000000000..c80fd2d1a36
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/startup/mdk/startup_at32f45x.s
@@ -0,0 +1,429 @@
+;**************************************************************************
+;* @file startup_at32f45x.s
+;* @brief at32f45x startup file for keil
+;* <<< Use Configuration Wizard in Context Menu >>>
+;**************************************************************************
+;
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000200
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDT_IRQHandler ; Window Watchdog Timer
+ DCD PVM_IRQHandler ; PVM through EXINT Line detect
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXINT line
+ DCD ERTC_WKUP_IRQHandler ; ERTC Wakeup through the EXINT line
+ DCD FLASH_IRQHandler ; Flash
+ DCD CRM_IRQHandler ; CRM
+ DCD EXINT0_IRQHandler ; EXINT Line 0
+ DCD EXINT1_IRQHandler ; EXINT Line 1
+ DCD EXINT2_IRQHandler ; EXINT Line 2
+ DCD EXINT3_IRQHandler ; EXINT Line 3
+ DCD EXINT4_IRQHandler ; EXINT Line 4
+ DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
+ DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
+ DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
+ DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
+ DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
+ DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
+ DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
+ DCD ADC1_2_IRQHandler ; ADC1 & ADC2
+ DCD CAN1_TX_IRQHandler ; CAN1 TX
+ DCD CAN1_RX_IRQHandler ; CAN1 RX
+ DCD CAN1_STAT_IRQHandler ; CAN1 State
+ DCD CAN1_ERR_IRQHandler ; CAN1 Error
+ DCD EXINT9_5_IRQHandler ; EXINT Line [9:5]
+ DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Brake and TMR9
+ DCD TMR1_OVF_TMR10_IRQHandler ; TMR1 Overflow and TMR10
+ DCD TMR1_TRG_HALL_TMR11_IRQHandler ; TMR1 Trigger and hall and TMR11
+ DCD TMR1_CH_IRQHandler ; TMR1 Channel
+ DCD TMR2_GLOBAL_IRQHandler ; TMR2
+ DCD TMR3_GLOBAL_IRQHandler ; TMR3
+ DCD TMR4_GLOBAL_IRQHandler ; TMR4
+ DCD I2C1_EVT_IRQHandler ; I2C1 Event
+ DCD I2C1_ERR_IRQHandler ; I2C1 Error
+ DCD I2C2_EVT_IRQHandler ; I2C2 Event
+ DCD I2C2_ERR_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_I2S2EXT_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXINT15_10_IRQHandler ; EXINT Line [15:10]
+ DCD ERTCAlarm_IRQHandler ; ERTC Alarm through EXINT Line
+ DCD OTGFS1_WKUP_IRQHandler ; OTGFS1 Wakeup from suspend
+ DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Brake and TMR12
+ DCD TMR8_OVF_TMR13_IRQHandler ; TMR8 Overflow and TMR13
+ DCD TMR8_TRG_HALL_TMR14_IRQHandler ; TMR8 Trigger and hall and TMR14
+ DCD TMR8_CH_IRQHandler ; TMR8 Channel
+ DCD 0 ; Reserved
+ DCD XMC_IRQHandler ; XMC
+ DCD SDIO1_IRQHandler ; SDIO1
+ DCD TMR5_GLOBAL_IRQHandler ; TMR5
+ DCD SPI3_I2S3EXT_IRQHandler ; SPI3
+ DCD USART4_IRQHandler ; USART4
+ DCD USART5_IRQHandler ; USART5
+ DCD TMR6_DAC_GLOBAL_IRQHandler ; TMR6 & DAC
+ DCD TMR7_GLOBAL_IRQHandler ; TMR7
+ DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
+ DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
+ DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
+ DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
+ DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
+ DCD EMAC_IRQHandler ; EMAC
+ DCD EMAC_WKUP_IRQHandler ; EMAC Wakeup
+ DCD CAN2_TX_IRQHandler ; CAN2 TX
+ DCD CAN2_RX_IRQHandler ; CAN2 RX
+ DCD CAN2_STAT_IRQHandler ; CAN2 State
+ DCD CAN2_ERR_IRQHandler ; CAN2 Error
+ DCD OTGFS1_IRQHandler ; OTGFS1
+ DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
+ DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
+ DCD 0 ; Reserved
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EVT_IRQHandler ; I2C3 Event
+ DCD I2C3_ERR_IRQHandler ; I2C3 Error
+ DCD CAN3_TX_IRQHandler ; CAN3 TX
+ DCD CAN3_RX_IRQHandler ; CAN3 RX
+ DCD CAN3_STAT_IRQHandler ; CAN3 State
+ DCD CAN3_ERR_IRQHandler ; CAN3 Error
+ DCD 0 ; Reserved
+ DCD AES_IRQHandler ; AES
+ DCD TRNG_IRQHandler ; TRNG
+ DCD FPU_IRQHandler ; FPU
+ DCD USART7_IRQHandler ; USART7
+ DCD USART8_IRQHandler ; USART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD I2SF5_IRQHandler ; I2SF5
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD QSPI1_IRQHandler ; QSPI1
+ DCD 0 ; Reserved
+ DCD DMAMUX_IRQHandler ; DMAMUX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD ACC_IRQHandler ; ACC
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ IMPORT SystemInit
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT WWDT_IRQHandler [WEAK]
+ EXPORT PVM_IRQHandler [WEAK]
+ EXPORT TAMP_STAMP_IRQHandler [WEAK]
+ EXPORT ERTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT CRM_IRQHandler [WEAK]
+ EXPORT EXINT0_IRQHandler [WEAK]
+ EXPORT EXINT1_IRQHandler [WEAK]
+ EXPORT EXINT2_IRQHandler [WEAK]
+ EXPORT EXINT3_IRQHandler [WEAK]
+ EXPORT EXINT4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel1_IRQHandler [WEAK]
+ EXPORT DMA1_Channel2_IRQHandler [WEAK]
+ EXPORT DMA1_Channel3_IRQHandler [WEAK]
+ EXPORT DMA1_Channel4_IRQHandler [WEAK]
+ EXPORT DMA1_Channel5_IRQHandler [WEAK]
+ EXPORT DMA1_Channel6_IRQHandler [WEAK]
+ EXPORT DMA1_Channel7_IRQHandler [WEAK]
+ EXPORT ADC1_2_IRQHandler [WEAK]
+ EXPORT CAN1_TX_IRQHandler [WEAK]
+ EXPORT CAN1_RX_IRQHandler [WEAK]
+ EXPORT CAN1_STAT_IRQHandler [WEAK]
+ EXPORT CAN1_ERR_IRQHandler [WEAK]
+ EXPORT EXINT9_5_IRQHandler [WEAK]
+ EXPORT TMR1_BRK_TMR9_IRQHandler [WEAK]
+ EXPORT TMR1_OVF_TMR10_IRQHandler [WEAK]
+ EXPORT TMR1_TRG_HALL_TMR11_IRQHandler [WEAK]
+ EXPORT TMR1_CH_IRQHandler [WEAK]
+ EXPORT TMR2_GLOBAL_IRQHandler [WEAK]
+ EXPORT TMR3_GLOBAL_IRQHandler [WEAK]
+ EXPORT TMR4_GLOBAL_IRQHandler [WEAK]
+ EXPORT I2C1_EVT_IRQHandler [WEAK]
+ EXPORT I2C1_ERR_IRQHandler [WEAK]
+ EXPORT I2C2_EVT_IRQHandler [WEAK]
+ EXPORT I2C2_ERR_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_I2S2EXT_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXINT15_10_IRQHandler [WEAK]
+ EXPORT ERTCAlarm_IRQHandler [WEAK]
+ EXPORT OTGFS1_WKUP_IRQHandler [WEAK]
+ EXPORT TMR8_BRK_TMR12_IRQHandler [WEAK]
+ EXPORT TMR8_OVF_TMR13_IRQHandler [WEAK]
+ EXPORT TMR8_TRG_HALL_TMR14_IRQHandler [WEAK]
+ EXPORT TMR8_CH_IRQHandler [WEAK]
+ EXPORT XMC_IRQHandler [WEAK]
+ EXPORT SDIO1_IRQHandler [WEAK]
+ EXPORT TMR5_GLOBAL_IRQHandler [WEAK]
+ EXPORT SPI3_I2S3EXT_IRQHandler [WEAK]
+ EXPORT USART4_IRQHandler [WEAK]
+ EXPORT USART5_IRQHandler [WEAK]
+ EXPORT TMR6_DAC_GLOBAL_IRQHandler [WEAK]
+ EXPORT TMR7_GLOBAL_IRQHandler [WEAK]
+ EXPORT DMA2_Channel1_IRQHandler [WEAK]
+ EXPORT DMA2_Channel2_IRQHandler [WEAK]
+ EXPORT DMA2_Channel3_IRQHandler [WEAK]
+ EXPORT DMA2_Channel4_IRQHandler [WEAK]
+ EXPORT DMA2_Channel5_IRQHandler [WEAK]
+ EXPORT EMAC_IRQHandler [WEAK]
+ EXPORT EMAC_WKUP_IRQHandler [WEAK]
+ EXPORT CAN2_TX_IRQHandler [WEAK]
+ EXPORT CAN2_RX_IRQHandler [WEAK]
+ EXPORT CAN2_STAT_IRQHandler [WEAK]
+ EXPORT CAN2_ERR_IRQHandler [WEAK]
+ EXPORT OTGFS1_IRQHandler [WEAK]
+ EXPORT DMA2_Channel6_IRQHandler [WEAK]
+ EXPORT DMA2_Channel7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EVT_IRQHandler [WEAK]
+ EXPORT I2C3_ERR_IRQHandler [WEAK]
+ EXPORT CAN3_TX_IRQHandler [WEAK]
+ EXPORT CAN3_RX_IRQHandler [WEAK]
+ EXPORT CAN3_STAT_IRQHandler [WEAK]
+ EXPORT CAN3_ERR_IRQHandler [WEAK]
+ EXPORT AES_IRQHandler [WEAK]
+ EXPORT TRNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT USART7_IRQHandler [WEAK]
+ EXPORT USART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT I2SF5_IRQHandler [WEAK]
+ EXPORT QSPI1_IRQHandler [WEAK]
+ EXPORT DMAMUX_IRQHandler [WEAK]
+ EXPORT ACC_IRQHandler [WEAK]
+WWDT_IRQHandler
+PVM_IRQHandler
+TAMP_STAMP_IRQHandler
+ERTC_WKUP_IRQHandler
+FLASH_IRQHandler
+CRM_IRQHandler
+EXINT0_IRQHandler
+EXINT1_IRQHandler
+EXINT2_IRQHandler
+EXINT3_IRQHandler
+EXINT4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_2_IRQHandler
+CAN1_TX_IRQHandler
+CAN1_RX_IRQHandler
+CAN1_STAT_IRQHandler
+CAN1_ERR_IRQHandler
+EXINT9_5_IRQHandler
+TMR1_BRK_TMR9_IRQHandler
+TMR1_OVF_TMR10_IRQHandler
+TMR1_TRG_HALL_TMR11_IRQHandler
+TMR1_CH_IRQHandler
+TMR2_GLOBAL_IRQHandler
+TMR3_GLOBAL_IRQHandler
+TMR4_GLOBAL_IRQHandler
+I2C1_EVT_IRQHandler
+I2C1_ERR_IRQHandler
+I2C2_EVT_IRQHandler
+I2C2_ERR_IRQHandler
+SPI1_IRQHandler
+SPI2_I2S2EXT_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXINT15_10_IRQHandler
+ERTCAlarm_IRQHandler
+OTGFS1_WKUP_IRQHandler
+TMR8_BRK_TMR12_IRQHandler
+TMR8_OVF_TMR13_IRQHandler
+TMR8_TRG_HALL_TMR14_IRQHandler
+TMR8_CH_IRQHandler
+XMC_IRQHandler
+SDIO1_IRQHandler
+TMR5_GLOBAL_IRQHandler
+SPI3_I2S3EXT_IRQHandler
+USART4_IRQHandler
+USART5_IRQHandler
+TMR6_DAC_GLOBAL_IRQHandler
+TMR7_GLOBAL_IRQHandler
+DMA2_Channel1_IRQHandler
+DMA2_Channel2_IRQHandler
+DMA2_Channel3_IRQHandler
+DMA2_Channel4_IRQHandler
+DMA2_Channel5_IRQHandler
+EMAC_IRQHandler
+EMAC_WKUP_IRQHandler
+CAN2_TX_IRQHandler
+CAN2_RX_IRQHandler
+CAN2_STAT_IRQHandler
+CAN2_ERR_IRQHandler
+OTGFS1_IRQHandler
+DMA2_Channel6_IRQHandler
+DMA2_Channel7_IRQHandler
+USART6_IRQHandler
+I2C3_EVT_IRQHandler
+I2C3_ERR_IRQHandler
+CAN3_TX_IRQHandler
+CAN3_RX_IRQHandler
+CAN3_STAT_IRQHandler
+CAN3_ERR_IRQHandler
+AES_IRQHandler
+TRNG_IRQHandler
+FPU_IRQHandler
+USART7_IRQHandler
+USART8_IRQHandler
+SPI4_IRQHandler
+I2SF5_IRQHandler
+QSPI1_IRQHandler
+DMAMUX_IRQHandler
+ACC_IRQHandler
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, = (Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+ END
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/system_at32f45x.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/system_at32f45x.c
new file mode 100644
index 00000000000..4b92ed984fb
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/system_at32f45x.c
@@ -0,0 +1,187 @@
+/**
+ **************************************************************************
+ * @file system_at32f45x.c
+ * @brief contains all the functions for cmsis cortex-m4 system source file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup AT32F45x_system
+ * @{
+ */
+
+#include "at32f45x.h"
+
+/** @addtogroup AT32F45x_system_private_defines
+ * @{
+ */
+#define VECT_TAB_OFFSET 0x0 /*!< vector table base offset field. this value must be a multiple of 0x200. */
+/**
+ * @}
+ */
+
+/** @addtogroup AT32F45x_system_private_variables
+ * @{
+ */
+unsigned int system_core_clock = HICK_VALUE; /*!< system clock frequency (core clock) */
+/**
+ * @}
+ */
+
+/** @addtogroup AT32F45x_system_private_functions
+ * @{
+ */
+
+/**
+ * @brief setup the microcontroller system
+ * initialize the flash interface.
+ * @note this function should be used only after reset.
+ * @param none
+ * @retval none
+ */
+void SystemInit (void)
+{
+#if defined (__FPU_USED) && (__FPU_USED == 1U)
+ SCB->CPACR |= ((3U << 10U * 2U) | /* set cp10 full access */
+ (3U << 11U * 2U) ); /* set cp11 full access */
+#endif
+
+ /* reset the crm clock configuration to the default reset state(for debug purpose) */
+ /* enable auto step mode */
+ crm_auto_step_mode_enable(TRUE);
+
+ /* set hicken bit */
+ CRM->ctrl_bit.hicken = TRUE;
+
+ /* wait hick stable */
+ while(CRM->ctrl_bit.hickstbl != SET);
+
+ /* hick used as system clock */
+ CRM->cfg_bit.sclksel = CRM_SCLK_HICK;
+
+ /* wait sclk switch status */
+ while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK);
+
+ /* reset hexten, hextbyps, cfden and pllen bits */
+ CRM->ctrl &= ~(0x010D0000U);
+
+ /* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv, clkout bits */
+ CRM->cfg = 0x40000000U;
+
+ /* reset pllms pllns pllfp pllrcs bits */
+ CRM->pllcfg = 0x000007C1U;
+
+ /* reset clkout_sel, clkoutdiv */
+ CRM->misc1 = 0x000F1000;
+
+ /* disable all interrupts enable and clear pending bits */
+ CRM->clkint = 0x009F0000U;
+
+ /* disable auto step mode */
+ crm_auto_step_mode_enable(FALSE);
+
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* vector table relocation in internal sram. */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* vector table relocation in internal flash. */
+#endif
+}
+
+/**
+ * @brief update system_core_clock variable according to clock register values.
+ * the system_core_clock variable contains the core clock (hclk), it can
+ * be used by the user application to setup the systick timer or configure
+ * other parameters.
+ * @param none
+ * @retval none
+ */
+void system_core_clock_update(void)
+{
+ uint32_t pll_ns = 0, pll_ms = 0, pll_fp = 0, pll_clock_source = 0, pllrcsfreq = 0;
+ uint32_t temp = 0, div_value = 0;
+ crm_sclk_type sclk_source;
+
+ static const uint8_t sys_ahb_div_table[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+ static const uint8_t pll_fp_table[16] = {1, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30};
+
+ /* get sclk source */
+ sclk_source = crm_sysclk_switch_status_get();
+
+ switch(sclk_source)
+ {
+ case CRM_SCLK_HICK:
+ if((CRM->misc1_bit.hick_to_sclk) != RESET)
+ system_core_clock = HICK_VALUE * 6;
+ else
+ system_core_clock = HICK_VALUE;
+ break;
+ case CRM_SCLK_HEXT:
+ system_core_clock = HEXT_VALUE;
+ break;
+ case CRM_SCLK_PLL:
+ /* get pll clock source */
+ pll_clock_source = CRM->pllcfg_bit.pllrcs;
+
+ /* get multiplication factor */
+ pll_ns = CRM->pllcfg_bit.pllns;
+ pll_ms = CRM->pllcfg_bit.pllms;
+ pll_fp = pll_fp_table[CRM->pllcfg_bit.pllfp];
+
+ if (pll_clock_source == CRM_PLL_SOURCE_HICK)
+ {
+ /* hick selected as pll clock entry */
+ pllrcsfreq = HICK_VALUE;
+ }
+ else
+ {
+ /* hext selected as pll clock entry */
+ pllrcsfreq = HEXT_VALUE;
+ }
+
+ system_core_clock = (uint32_t)(((uint64_t)pllrcsfreq * pll_ns) / (pll_ms * pll_fp));
+ break;
+ default:
+ system_core_clock = HICK_VALUE;
+ break;
+ }
+
+ /* compute sclk, ahbclk frequency */
+ /* get ahb division */
+ temp = CRM->cfg_bit.ahbdiv;
+ div_value = sys_ahb_div_table[temp];
+ /* ahbclk frequency */
+ system_core_clock = system_core_clock >> div_value;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/system_at32f45x.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/system_at32f45x.h
new file mode 100644
index 00000000000..60fb4645784
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/cmsis/cm4/device_support/system_at32f45x.h
@@ -0,0 +1,74 @@
+/**
+ **************************************************************************
+ * @file system_at32f45x.h
+ * @brief cmsis cortex-m4 system header file.
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#ifndef __SYSTEM_AT32F45x_H
+#define __SYSTEM_AT32F45x_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup AT32F45x_system
+ * @{
+ */
+
+/** @defgroup AT32F45x_system_exported_variables
+ * @{
+ */
+extern unsigned int system_core_clock; /*!< system clock frequency (core clock) */
+
+/**
+ * @}
+ */
+
+/** @defgroup AT32F45x_system_exported_functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void system_core_clock_update(void);
+extern void reduce_power_consumption(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_acc.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_acc.h
new file mode 100644
index 00000000000..714c5504b31
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_acc.h
@@ -0,0 +1,201 @@
+/**
+ **************************************************************************
+ * @file at32f45x_acc.h
+ * @brief at32f45x acc header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_ACC_H
+#define __AT32F45x_ACC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f45x.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @addtogroup ACC
+ * @{
+ */
+
+/** @defgroup ACC_exported_constants
+ * @{
+ */
+
+#define ACC_CAL_HICKCAL ((uint16_t)0x0000) /*!< acc hick calibration */
+#define ACC_CAL_HICKTRIM ((uint16_t)0x0002) /*!< acc hick trim */
+
+#define ACC_RSLOST_FLAG ((uint16_t)0x0002) /*!< acc reference signal lost error flag */
+#define ACC_CALRDY_FLAG ((uint16_t)0x0001) /*!< acc internal high-speed clock calibration ready error flag */
+
+#define ACC_CALRDYIEN_INT ((uint16_t)0x0020) /*!< acc internal high-speed clock calibration ready interrupt enable */
+#define ACC_EIEN_INT ((uint16_t)0x0010) /*!< acc reference signal lost interrupt enable */
+
+
+/**
+ * @}
+ */
+
+/** @defgroup ACC_exported_types
+ * @{
+ */
+
+/**
+ * @brief type define acc register all
+ */
+typedef struct
+{
+
+ /**
+ * @brief acc sts register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t calrdy : 1; /* [0] */
+ __IO uint32_t rslost : 1; /* [1] */
+ __IO uint32_t reserved1 : 30;/* [31:2] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief acc ctrl1 register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t ctrl1;
+ struct
+ {
+ __IO uint32_t calon : 1; /* [0] */
+ __IO uint32_t entrim : 1; /* [1] */
+ __IO uint32_t reserved1 : 2; /* [3:2] */
+ __IO uint32_t eien : 1; /* [4] */
+ __IO uint32_t calrdyien : 1; /* [5] */
+ __IO uint32_t reserved2 : 2; /* [7:6] */
+ __IO uint32_t step : 4; /* [11:8] */
+ __IO uint32_t reserved3 : 20;/* [31:12] */
+ } ctrl1_bit;
+ };
+
+ /**
+ * @brief acc ctrl2 register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t ctrl2;
+ struct
+ {
+ __IO uint32_t hickcal : 8; /* [7:0] */
+ __IO uint32_t hicktrim : 6; /* [13:8] */
+ __IO uint32_t reserved1 : 18;/* [31:14] */
+ } ctrl2_bit;
+ };
+
+ /**
+ * @brief acc acc_c1 register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t c1;
+ struct
+ {
+ __IO uint32_t c1 : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } c1_bit;
+ };
+
+ /**
+ * @brief acc acc_c2 register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t c2;
+ struct
+ {
+ __IO uint32_t c2 : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } c2_bit;
+ };
+
+ /**
+ * @brief acc acc_c3 register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t c3;
+ struct
+ {
+ __IO uint32_t c3 : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } c3_bit;
+ };
+} acc_type;
+
+/**
+ * @}
+ */
+
+#define ACC ((acc_type *) ACC_BASE)
+
+/** @defgroup ACC_exported_functions
+ * @{
+ */
+
+void acc_calibration_mode_enable(uint16_t acc_trim, confirm_state new_state);
+void acc_step_set(uint8_t step_value);
+void acc_interrupt_enable(uint16_t acc_int, confirm_state new_state);
+uint8_t acc_hicktrim_get(void);
+uint8_t acc_hickcal_get(void);
+void acc_write_c1(uint16_t acc_c1_value);
+void acc_write_c2(uint16_t acc_c2_value);
+void acc_write_c3(uint16_t acc_c3_value);
+uint16_t acc_read_c1(void);
+uint16_t acc_read_c2(void);
+uint16_t acc_read_c3(void);
+flag_status acc_flag_get(uint16_t acc_flag);
+flag_status acc_interrupt_flag_get(uint16_t acc_flag);
+void acc_flag_clear(uint16_t acc_flag);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_adc.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_adc.h
new file mode 100644
index 00000000000..67d2153e20c
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_adc.h
@@ -0,0 +1,903 @@
+/**
+ **************************************************************************
+ * @file at32f45x_adc.h
+ * @brief at32f45x adc header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_ADC_H
+#define __AT32F45x_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f45x.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/** @defgroup ADC_interrupts_definition
+ * @brief adc interrupt
+ * @{
+ */
+
+#define ADC_OCCE_INT ((uint32_t)0x00000020) /*!< ordinary channels conversion end interrupt */
+#define ADC_VMOR_INT ((uint32_t)0x00000040) /*!< voltage monitoring out of range interrupt */
+#define ADC_PCCE_INT ((uint32_t)0x00000080) /*!< preempt channels conversion end interrupt */
+#define ADC_OCCO_INT ((uint32_t)0x04000000) /*!< ordinary channel conversion overflow interrupt */
+#define ADC_TCF_INT ((uint32_t)0x08000000) /*!< trigger convert fail interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_flags_definition
+ * @brief adc flag
+ * @{
+ */
+
+#define ADC_VMOR_FLAG ((uint8_t)0x01) /*!< voltage monitoring out of range flag */
+#define ADC_OCCE_FLAG ((uint8_t)0x02) /*!< ordinary channels conversion end flag */
+#define ADC_PCCE_FLAG ((uint8_t)0x04) /*!< preempt channels conversion end flag */
+#define ADC_PCCS_FLAG ((uint8_t)0x08) /*!< preempt channel conversion start flag */
+#define ADC_OCCS_FLAG ((uint8_t)0x10) /*!< ordinary channel conversion start flag */
+#define ADC_OCCO_FLAG ((uint8_t)0x20) /*!< ordinary channel conversion overflow flag */
+#define ADC_RDY_FLAG ((uint8_t)0x40) /*!< adc ready to conversion flag */
+#define ADC_TCF_FLAG ((uint8_t)0x80) /*!< trigger convert fail flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup ADC_exported_types
+ * @{
+ */
+
+/**
+ * @brief adc division type
+ */
+typedef enum
+{
+ ADC_HCLK_DIV_2 = 0x00, /*!< adcclk is hclk/2 */
+ ADC_HCLK_DIV_3 = 0x01, /*!< adcclk is hclk/3 */
+ ADC_HCLK_DIV_4 = 0x02, /*!< adcclk is hclk/4 */
+ ADC_HCLK_DIV_5 = 0x03, /*!< adcclk is hclk/5 */
+ ADC_HCLK_DIV_6 = 0x04, /*!< adcclk is hclk/6 */
+ ADC_HCLK_DIV_7 = 0x05, /*!< adcclk is hclk/7 */
+ ADC_HCLK_DIV_8 = 0x06, /*!< adcclk is hclk/8 */
+ ADC_HCLK_DIV_9 = 0x07, /*!< adcclk is hclk/9 */
+ ADC_HCLK_DIV_10 = 0x08, /*!< adcclk is hclk/10 */
+ ADC_HCLK_DIV_11 = 0x09, /*!< adcclk is hclk/11 */
+ ADC_HCLK_DIV_12 = 0x0A, /*!< adcclk is hclk/12 */
+ ADC_HCLK_DIV_13 = 0x0B, /*!< adcclk is hclk/13 */
+ ADC_HCLK_DIV_14 = 0x0C, /*!< adcclk is hclk/14 */
+ ADC_HCLK_DIV_15 = 0x0D, /*!< adcclk is hclk/15 */
+ ADC_HCLK_DIV_16 = 0x0E, /*!< adcclk is hclk/16 */
+ ADC_HCLK_DIV_17 = 0x0F /*!< adcclk is hclk/17 */
+} adc_div_type;
+
+/**
+ * @brief adc combine mode type
+ */
+typedef enum
+{
+ ADC_INDEPENDENT_MODE = 0x00, /*!< independent mode */
+ ADC_ORDINARY_SMLT_PREEMPT_SMLT_ONESLAVE_MODE = 0x01, /*!< single slaver combined ordinary simultaneous + preempt simultaneous mode */
+ ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_ONESLAVE_MODE = 0x02, /*!< single slaver combined ordinary simultaneous + preempt interleaved trigger mode */
+ ADC_PREEMPT_SMLT_ONLY_ONESLAVE_MODE = 0x05, /*!< single slaver preempt simultaneous mode only */
+ ADC_ORDINARY_SMLT_ONLY_ONESLAVE_MODE = 0x06, /*!< single slaver ordinary simultaneous mode only */
+ ADC_ORDINARY_SHIFT_ONLY_ONESLAVE_MODE = 0x07, /*!< single slaver ordinary shifting mode only */
+ ADC_PREEMPT_INTERLTRIG_ONLY_ONESLAVE_MODE = 0x09, /*!< single slaver preempt interleaved trigger mode only */
+} adc_combine_mode_type;
+
+/**
+ * @brief adc common dma mode type
+ */
+typedef enum
+{
+ ADC_COMMON_DMAMODE_DISABLE = 0x00, /*!< dma mode disabled */
+ ADC_COMMON_DMAMODE_1 = 0x01, /*!< dma mode1: each dma request trans a half-word data(reference manual account the rule of data package) */
+ ADC_COMMON_DMAMODE_2 = 0x02, /*!< dma mode2: each dma request trans two half-word data(reference manual account the rule of data package) */
+ ADC_COMMON_DMAMODE_3 = 0x03, /*!< dma mode3: each dma request trans two bytes data(reference manual account the rule of data package) */
+} adc_common_dma_mode_type;
+
+/**
+ * @brief adc common sampling interval type
+ */
+typedef enum
+{
+ ADC_SAMPLING_INTERVAL_5CYCLES = 0x00, /*!< ordinary shifting mode adjacent adc sampling interval 5 adcclk */
+ ADC_SAMPLING_INTERVAL_6CYCLES = 0x01, /*!< ordinary shifting mode adjacent adc sampling interval 6 adcclk */
+ ADC_SAMPLING_INTERVAL_7CYCLES = 0x02, /*!< ordinary shifting mode adjacent adc sampling interval 7 adcclk */
+ ADC_SAMPLING_INTERVAL_8CYCLES = 0x03, /*!< ordinary shifting mode adjacent adc sampling interval 8 adcclk */
+ ADC_SAMPLING_INTERVAL_9CYCLES = 0x04, /*!< ordinary shifting mode adjacent adc sampling interval 9 adcclk */
+ ADC_SAMPLING_INTERVAL_10CYCLES = 0x05, /*!< ordinary shifting mode adjacent adc sampling interval 10 adcclk */
+ ADC_SAMPLING_INTERVAL_11CYCLES = 0x06, /*!< ordinary shifting mode adjacent adc sampling interval 11 adcclk */
+ ADC_SAMPLING_INTERVAL_12CYCLES = 0x07, /*!< ordinary shifting mode adjacent adc sampling interval 12 adcclk */
+ ADC_SAMPLING_INTERVAL_13CYCLES = 0x08, /*!< ordinary shifting mode adjacent adc sampling interval 13 adcclk */
+ ADC_SAMPLING_INTERVAL_14CYCLES = 0x09, /*!< ordinary shifting mode adjacent adc sampling interval 14 adcclk */
+ ADC_SAMPLING_INTERVAL_15CYCLES = 0x0A, /*!< ordinary shifting mode adjacent adc sampling interval 15 adcclk */
+ ADC_SAMPLING_INTERVAL_16CYCLES = 0x0B, /*!< ordinary shifting mode adjacent adc sampling interval 16 adcclk */
+ ADC_SAMPLING_INTERVAL_17CYCLES = 0x0C, /*!< ordinary shifting mode adjacent adc sampling interval 17 adcclk */
+ ADC_SAMPLING_INTERVAL_18CYCLES = 0x0D, /*!< ordinary shifting mode adjacent adc sampling interval 18 adcclk */
+ ADC_SAMPLING_INTERVAL_19CYCLES = 0x0E, /*!< ordinary shifting mode adjacent adc sampling interval 19 adcclk */
+ ADC_SAMPLING_INTERVAL_20CYCLES = 0x0F /*!< ordinary shifting mode adjacent adc sampling interval 20 adcclk */
+} adc_sampling_interval_type;
+
+/**
+ * @brief adc conversion resolution type
+ */
+typedef enum
+{
+ ADC_RESOLUTION_12B = 0x00, /*!< conversion resolution 12 bit */
+ ADC_RESOLUTION_10B = 0x01, /*!< conversion resolution 10 bit */
+ ADC_RESOLUTION_8B = 0x02, /*!< conversion resolution 8 bit */
+ ADC_RESOLUTION_6B = 0x03 /*!< conversion resolution 6 bit */
+} adc_resolution_type;
+
+/**
+ * @brief adc data align type
+ */
+typedef enum
+{
+ ADC_RIGHT_ALIGNMENT = 0x00, /*!< data right alignment */
+ ADC_LEFT_ALIGNMENT = 0x01 /*!< data left alignment */
+} adc_data_align_type;
+
+/**
+ * @brief adc channel select type
+ */
+typedef enum
+{
+ ADC_CHANNEL_0 = 0x00, /*!< adc channel 0 */
+ ADC_CHANNEL_1 = 0x01, /*!< adc channel 1 */
+ ADC_CHANNEL_2 = 0x02, /*!< adc channel 2 */
+ ADC_CHANNEL_3 = 0x03, /*!< adc channel 3 */
+ ADC_CHANNEL_4 = 0x04, /*!< adc channel 4 */
+ ADC_CHANNEL_5 = 0x05, /*!< adc channel 5 */
+ ADC_CHANNEL_6 = 0x06, /*!< adc channel 6 */
+ ADC_CHANNEL_7 = 0x07, /*!< adc channel 7 */
+ ADC_CHANNEL_8 = 0x08, /*!< adc channel 8 */
+ ADC_CHANNEL_9 = 0x09, /*!< adc channel 9 */
+ ADC_CHANNEL_10 = 0x0A, /*!< adc channel 10 */
+ ADC_CHANNEL_11 = 0x0B, /*!< adc channel 11 */
+ ADC_CHANNEL_12 = 0x0C, /*!< adc channel 12 */
+ ADC_CHANNEL_13 = 0x0D, /*!< adc channel 13 */
+ ADC_CHANNEL_14 = 0x0E, /*!< adc channel 14 */
+ ADC_CHANNEL_15 = 0x0F, /*!< adc channel 15 */
+ ADC_CHANNEL_16 = 0x10, /*!< adc channel 16 */
+ ADC_CHANNEL_17 = 0x11, /*!< adc channel 17 */
+ ADC_CHANNEL_18 = 0x12 /*!< adc channel 18 */
+} adc_channel_select_type;
+
+/**
+ * @brief adc sampletime select type
+ */
+typedef enum
+{
+ ADC_SAMPLETIME_2_5 = 0x00, /*!< adc sample time 2.5 cycle */
+ ADC_SAMPLETIME_6_5 = 0x01, /*!< adc sample time 6.5 cycle */
+ ADC_SAMPLETIME_12_5 = 0x02, /*!< adc sample time 12.5 cycle */
+ ADC_SAMPLETIME_24_5 = 0x03, /*!< adc sample time 24.5 cycle */
+ ADC_SAMPLETIME_47_5 = 0x04, /*!< adc sample time 47.5 cycle */
+ ADC_SAMPLETIME_92_5 = 0x05, /*!< adc sample time 92.5 cycle */
+ ADC_SAMPLETIME_247_5 = 0x06, /*!< adc sample time 247.5 cycle */
+ ADC_SAMPLETIME_640_5 = 0x07 /*!< adc sample time 640.5 cycle */
+} adc_sampletime_select_type;
+
+/**
+ * @brief adc ordinary group trigger event select type
+ */
+typedef enum
+{
+ ADC_ORDINARY_TRIG_TMR1CH1 = 0x00, /*!< timer1 ch1 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR1CH2 = 0x01, /*!< timer1 ch2 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR1CH3 = 0x02, /*!< timer1 ch3 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR2CH2 = 0x03, /*!< timer2 ch2 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR2CH3 = 0x04, /*!< timer2 ch3 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR2CH4 = 0x05, /*!< timer2 ch4 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR2TRGOUT = 0x06, /*!< timer2 trgout event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR3CH1 = 0x07, /*!< timer3 ch1 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR3TRGOUT = 0x08, /*!< timer3 trgout event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR4CH4 = 0x09, /*!< timer4 ch4 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR5CH1 = 0x0A, /*!< timer5 ch1 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR5CH2 = 0x0B, /*!< timer5 ch2 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR5CH3 = 0x0C, /*!< timer5 ch3 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR8CH1 = 0x0D, /*!< timer8 ch1 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR8TRGOUT = 0x0E, /*!< timer8 trgout event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_EXINT11 = 0x0F, /*!< exint line11 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR8TRGOUT2 = 0x15, /*!< timer8 trgout2 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR1TRGOUT2 = 0x16, /*!< timer1 trgout2 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR4TRGOUT = 0x17, /*!< timer4 trgout event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR6TRGOUT = 0x18, /*!< timer6 trgout event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR3CH4 = 0x19, /*!< timer3 ch4 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR4CH1 = 0x1A, /*!< timer4 ch1 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR1TRGOUT = 0x1B, /*!< timer1 trgout event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR2CH1 = 0x1C, /*!< timer2 ch1 event as trigger source of ordinary sequence */
+ ADC_ORDINARY_TRIG_TMR7TRGOUT = 0x1E /*!< timer7 trgout event as trigger source of ordinary sequence */
+} adc_ordinary_trig_select_type;
+
+/**
+ * @brief adc ordinary channel conversion's external_trigger_edge type
+ */
+typedef enum
+{
+ ADC_ORDINARY_TRIG_EDGE_NONE = 0x00, /*!< ordinary channels trigger detection disabled */
+ ADC_ORDINARY_TRIG_EDGE_RISING = 0x01, /*!< ordinary channels trigger detection on the rising edge */
+ ADC_ORDINARY_TRIG_EDGE_FALLING = 0x02, /*!< ordinary channels trigger detection on the falling edge */
+ ADC_ORDINARY_TRIG_EDGE_RISING_FALLING = 0x03 /*!< ordinary channels trigger detection on both the rising and falling edges */
+} adc_ordinary_trig_edge_type;
+
+/**
+ * @brief adc preempt group external trigger event select type
+ */
+typedef enum
+{
+ ADC_PREEMPT_TRIG_TMR1CH4 = 0x00, /*!< timer1 ch4 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR1TRGOUT = 0x01, /*!< timer1 trgout event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR2CH1 = 0x02, /*!< timer2 ch1 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR2TRGOUT = 0x03, /*!< timer2 trgout event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR3CH2 = 0x04, /*!< timer3 ch2 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR3CH4 = 0x05, /*!< timer3 ch4 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR4CH1 = 0x06, /*!< timer4 ch1 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR4CH2 = 0x07, /*!< timer4 ch2 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR4CH3 = 0x08, /*!< timer4 ch3 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR4TRGOUT = 0x09, /*!< timer4 trgout event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR5CH4 = 0x0A, /*!< timer5 ch4 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR5TRGOUT = 0x0B, /*!< timer5 trgout event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR8CH2 = 0x0C, /*!< timer8 ch2 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR8CH3 = 0x0D, /*!< timer8 ch3 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR8CH4 = 0x0E, /*!< timer8 ch4 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_EXINT15 = 0x0F, /*!< exint line15 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR1TRGOUT2 = 0x13, /*!< timer1 trgout2 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR8TRGOUT = 0x14, /*!< timer8 trgout event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR8TRGOUT2 = 0x15, /*!< timer8 trgout2 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR3CH3 = 0x16, /*!< timer3 ch3 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR3TRGOUT = 0x17, /*!< timer3 trgout event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR3CH1 = 0x18, /*!< timer3 ch1 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR6TRGOUT = 0x19, /*!< timer6 trgout event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR4CH4 = 0x1A, /*!< timer4 ch4 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR1CH3 = 0x1B, /*!< timer1 ch3 event as trigger source of preempt sequence */
+ ADC_PREEMPT_TRIG_TMR7TRGOUT = 0x1E /*!< timer7 trgout event as trigger source of preempt sequence */
+} adc_preempt_trig_select_type;
+
+/**
+ * @brief adc preempt channel conversion's external_trigger_edge type
+ */
+typedef enum
+{
+ ADC_PREEMPT_TRIG_EDGE_NONE = 0x00, /*!< preempt channels trigger detection disabled */
+ ADC_PREEMPT_TRIG_EDGE_RISING = 0x01, /*!< preempt channels trigger detection on the rising edge */
+ ADC_PREEMPT_TRIG_EDGE_FALLING = 0x02, /*!< preempt channels trigger detection on the falling edge */
+ ADC_PREEMPT_TRIG_EDGE_RISING_FALLING = 0x03 /*!< preempt channels trigger detection on both the rising and falling edges */
+} adc_preempt_trig_edge_type;
+
+/**
+ * @brief adc preempt channel type
+ */
+typedef enum
+{
+ ADC_PREEMPT_CHANNEL_1 = 0x00, /*!< adc preempt channel 1 */
+ ADC_PREEMPT_CHANNEL_2 = 0x01, /*!< adc preempt channel 2 */
+ ADC_PREEMPT_CHANNEL_3 = 0x02, /*!< adc preempt channel 3 */
+ ADC_PREEMPT_CHANNEL_4 = 0x03 /*!< adc preempt channel 4 */
+} adc_preempt_channel_type;
+
+/**
+ * @brief adc voltage_monitoring type
+ */
+typedef enum
+{
+ ADC_VMONITOR_SINGLE_ORDINARY = 0x00800200, /*!< voltage_monitoring on a single ordinary channel */
+ ADC_VMONITOR_SINGLE_PREEMPT = 0x00400200, /*!< voltage_monitoring on a single preempt channel */
+ ADC_VMONITOR_SINGLE_ORDINARY_PREEMPT = 0x00C00200, /*!< voltage_monitoring on a single ordinary or preempt channel */
+ ADC_VMONITOR_ALL_ORDINARY = 0x00800000, /*!< voltage_monitoring on all ordinary channel */
+ ADC_VMONITOR_ALL_PREEMPT = 0x00400000, /*!< voltage_monitoring on all preempt channel */
+ ADC_VMONITOR_ALL_ORDINARY_PREEMPT = 0x00C00000, /*!< voltage_monitoring on all ordinary and preempt channel */
+ ADC_VMONITOR_NONE = 0x00000000 /*!< no channel guarded by the voltage_monitoring */
+} adc_voltage_monitoring_type;
+
+/**
+ * @brief adc oversample ratio type
+ */
+typedef enum
+{
+ ADC_OVERSAMPLE_RATIO_2 = 0x00, /*!< adc oversample ratio 2 */
+ ADC_OVERSAMPLE_RATIO_4 = 0x01, /*!< adc oversample ratio 4 */
+ ADC_OVERSAMPLE_RATIO_8 = 0x02, /*!< adc oversample ratio 8 */
+ ADC_OVERSAMPLE_RATIO_16 = 0x03, /*!< adc oversample ratio 16 */
+ ADC_OVERSAMPLE_RATIO_32 = 0x04, /*!< adc oversample ratio 32 */
+ ADC_OVERSAMPLE_RATIO_64 = 0x05, /*!< adc oversample ratio 64 */
+ ADC_OVERSAMPLE_RATIO_128 = 0x06, /*!< adc oversample ratio 128 */
+ ADC_OVERSAMPLE_RATIO_256 = 0x07 /*!< adc oversample ratio 256 */
+} adc_oversample_ratio_type;
+
+/**
+ * @brief adc oversample shift type
+ */
+typedef enum
+{
+ ADC_OVERSAMPLE_SHIFT_0 = 0x00, /*!< adc oversample shift 0 */
+ ADC_OVERSAMPLE_SHIFT_1 = 0x01, /*!< adc oversample shift 1 */
+ ADC_OVERSAMPLE_SHIFT_2 = 0x02, /*!< adc oversample shift 2 */
+ ADC_OVERSAMPLE_SHIFT_3 = 0x03, /*!< adc oversample shift 3 */
+ ADC_OVERSAMPLE_SHIFT_4 = 0x04, /*!< adc oversample shift 4 */
+ ADC_OVERSAMPLE_SHIFT_5 = 0x05, /*!< adc oversample shift 5 */
+ ADC_OVERSAMPLE_SHIFT_6 = 0x06, /*!< adc oversample shift 6 */
+ ADC_OVERSAMPLE_SHIFT_7 = 0x07, /*!< adc oversample shift 7 */
+ ADC_OVERSAMPLE_SHIFT_8 = 0x08 /*!< adc oversample shift 8 */
+} adc_oversample_shift_type;
+
+/**
+ * @brief adc ordinary oversample recover type
+ */
+typedef enum
+{
+ ADC_OVERSAMPLE_CONTINUE = 0x00, /*!< continue mode:when preempt triggered,oversampling is temporary stopped and continued after preempt sequence */
+ ADC_OVERSAMPLE_RESTART = 0x01 /*!< restart mode:when preempt triggered,oversampling is aborted and resumed from start after preempt sequence */
+} adc_ordinary_oversample_restart_type;
+
+/**
+ * @brief adc common config type
+ */
+typedef struct
+{
+ adc_combine_mode_type combine_mode; /*!< adc combine mode select */
+ adc_div_type div; /*!< adc division select */
+ adc_common_dma_mode_type common_dma_mode; /*!< adc common dma mode select */
+ confirm_state common_dma_request_repeat_state; /*!< adc common dma repeat state */
+ adc_sampling_interval_type sampling_interval; /*!< ordinary shifting mode adjacent adc sampling interval select */
+ confirm_state tempervintrv_state; /*!< adc temperature sensor and vintrv state */
+ confirm_state vbat_state; /*!< adc voltage battery state */
+} adc_common_config_type;
+
+/**
+ * @brief adc base config type
+ */
+typedef struct
+{
+ confirm_state sequence_mode; /*!< adc sequence mode */
+ confirm_state repeat_mode; /*!< adc repeat mode */
+ adc_data_align_type data_align; /*!< adc data alignment */
+ uint8_t ordinary_channel_length; /*!< adc ordinary channel sequence length*/
+} adc_base_config_type;
+
+/**
+ * @brief type define adc register all
+ */
+typedef struct
+{
+
+ /**
+ * @brief adc sts register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t vmor : 1; /* [0] */
+ __IO uint32_t occe : 1; /* [1] */
+ __IO uint32_t pcce : 1; /* [2] */
+ __IO uint32_t pccs : 1; /* [3] */
+ __IO uint32_t occs : 1; /* [4] */
+ __IO uint32_t occo : 1; /* [5] */
+ __IO uint32_t rdy : 1; /* [6] */
+ __IO uint32_t tcf : 1; /* [7] */
+ __IO uint32_t reserved1 : 24;/* [31:8] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief adc ctrl1 register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t ctrl1;
+ struct
+ {
+ __IO uint32_t vmcsel : 5; /* [4:0] */
+ __IO uint32_t occeien : 1; /* [5] */
+ __IO uint32_t vmorien : 1; /* [6] */
+ __IO uint32_t pcceien : 1; /* [7] */
+ __IO uint32_t sqen : 1; /* [8] */
+ __IO uint32_t vmsgen : 1; /* [9] */
+ __IO uint32_t pcautoen : 1; /* [10] */
+ __IO uint32_t ocpen : 1; /* [11] */
+ __IO uint32_t pcpen : 1; /* [12] */
+ __IO uint32_t ocpcnt : 3; /* [15:13] */
+ __IO uint32_t reserved1 : 6; /* [21:16] */
+ __IO uint32_t pcvmen : 1; /* [22] */
+ __IO uint32_t ocvmen : 1; /* [23] */
+ __IO uint32_t crsel : 2; /* [25:24] */
+ __IO uint32_t occoien : 1; /* [26] */
+ __IO uint32_t tcfien : 1; /* [27] */
+ __IO uint32_t tcfaca : 1; /* [28] */
+ __IO uint32_t reserved2 : 3; /* [31:29] */
+ } ctrl1_bit;
+ };
+
+ /**
+ * @brief adc ctrl2 register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t ctrl2;
+ struct
+ {
+ __IO uint32_t adcen : 1; /* [0] */
+ __IO uint32_t rpen : 1; /* [1] */
+ __IO uint32_t adcal : 1; /* [2] */
+ __IO uint32_t adcalinit : 1; /* [3] */
+ __IO uint32_t adabrt : 1; /* [4] */
+ __IO uint32_t reserved1 : 3; /* [7:5] */
+ __IO uint32_t ocdmaen : 1; /* [8] */
+ __IO uint32_t ocdrcen : 1; /* [9] */
+ __IO uint32_t eocsfen : 1; /* [10] */
+ __IO uint32_t dtalign : 1; /* [11] */
+ __IO uint32_t reserved2 : 4; /* [15:12] */
+ __IO uint32_t pctesel_l : 4; /* [19:16] */
+ __IO uint32_t pcete : 2; /* [21:20] */
+ __IO uint32_t pcswtrg : 1; /* [22] */
+ __IO uint32_t pctesel_h : 1; /* [23] */
+ __IO uint32_t octesel_l : 4; /* [27:24] */
+ __IO uint32_t ocete : 2; /* [29:28] */
+ __IO uint32_t ocswtrg : 1; /* [30] */
+ __IO uint32_t octesel_h : 1; /* [31] */
+ } ctrl2_bit;
+ };
+
+ /**
+ * @brief adc spt1 register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t spt1;
+ struct
+ {
+ __IO uint32_t cspt10 : 3; /* [2:0] */
+ __IO uint32_t cspt11 : 3; /* [5:3] */
+ __IO uint32_t cspt12 : 3; /* [8:6] */
+ __IO uint32_t cspt13 : 3; /* [11:9] */
+ __IO uint32_t cspt14 : 3; /* [14:12] */
+ __IO uint32_t cspt15 : 3; /* [17:15] */
+ __IO uint32_t cspt16 : 3; /* [20:18] */
+ __IO uint32_t cspt17 : 3; /* [23:21] */
+ __IO uint32_t cspt18 : 3; /* [26:24] */
+ __IO uint32_t reserved1 : 5;/* [31:27] */
+ } spt1_bit;
+ };
+
+ /**
+ * @brief adc spt2 register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t spt2;
+ struct
+ {
+ __IO uint32_t cspt0 : 3;/* [2:0] */
+ __IO uint32_t cspt1 : 3;/* [5:3] */
+ __IO uint32_t cspt2 : 3;/* [8:6] */
+ __IO uint32_t cspt3 : 3;/* [11:9] */
+ __IO uint32_t cspt4 : 3;/* [14:12] */
+ __IO uint32_t cspt5 : 3;/* [17:15] */
+ __IO uint32_t cspt6 : 3;/* [20:18] */
+ __IO uint32_t cspt7 : 3;/* [23:21] */
+ __IO uint32_t cspt8 : 3;/* [26:24] */
+ __IO uint32_t cspt9 : 3;/* [29:27] */
+ __IO uint32_t reserved1 : 2;/* [31:30] */
+ } spt2_bit;
+ };
+
+ /**
+ * @brief adc pcdto1 register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t pcdto1;
+ struct
+ {
+ __IO uint32_t pcdto1 : 12; /* [11:0] */
+ __IO uint32_t reserved1 : 20; /* [31:12] */
+ } pcdto1_bit;
+ };
+
+ /**
+ * @brief adc pcdto2 register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t pcdto2;
+ struct
+ {
+ __IO uint32_t pcdto2 : 12; /* [11:0] */
+ __IO uint32_t reserved1 : 20; /* [31:12] */
+ } pcdto2_bit;
+ };
+
+ /**
+ * @brief adc pcdto3 register, offset:0x1C
+ */
+ union
+ {
+ __IO uint32_t pcdto3;
+ struct
+ {
+ __IO uint32_t pcdto3 : 12; /* [11:0] */
+ __IO uint32_t reserved1 : 20; /* [31:12] */
+ } pcdto3_bit;
+ };
+
+ /**
+ * @brief adc pcdto4 register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t pcdto4;
+ struct
+ {
+ __IO uint32_t pcdto4 : 12; /* [11:0] */
+ __IO uint32_t reserved1 : 20; /* [31:12] */
+ } pcdto4_bit;
+ };
+
+ /**
+ * @brief adc vmhb register, offset:0x24
+ */
+ union
+ {
+ __IO uint32_t vmhb;
+ struct
+ {
+ __IO uint32_t vmhb : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } vmhb_bit;
+ };
+
+ /**
+ * @brief adc vmlb register, offset:0x28
+ */
+ union
+ {
+ __IO uint32_t vmlb;
+ struct
+ {
+ __IO uint32_t vmlb : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } vmlb_bit;
+ };
+
+ /**
+ * @brief adc osq1 register, offset:0x2C
+ */
+ union
+ {
+ __IO uint32_t osq1;
+ struct
+ {
+ __IO uint32_t osn13 : 5; /* [4:0] */
+ __IO uint32_t osn14 : 5; /* [9:5] */
+ __IO uint32_t osn15 : 5; /* [14:10] */
+ __IO uint32_t osn16 : 5; /* [19:15] */
+ __IO uint32_t oclen : 4; /* [23:20] */
+ __IO uint32_t reserved1 : 8; /* [31:24] */
+ } osq1_bit;
+ };
+
+ /**
+ * @brief adc osq2 register, offset:0x30
+ */
+ union
+ {
+ __IO uint32_t osq2;
+ struct
+ {
+ __IO uint32_t osn7 : 5; /* [4:0] */
+ __IO uint32_t osn8 : 5; /* [9:5] */
+ __IO uint32_t osn9 : 5; /* [14:10] */
+ __IO uint32_t osn10 : 5; /* [19:15] */
+ __IO uint32_t osn11 : 5; /* [24:20] */
+ __IO uint32_t osn12 : 5; /* [29:25] */
+ __IO uint32_t reserved1 : 2; /* [31:30] */
+ } osq2_bit;
+ };
+
+ /**
+ * @brief adc osq3 register, offset:0x34
+ */
+ union
+ {
+ __IO uint32_t osq3;
+ struct
+ {
+ __IO uint32_t osn1 : 5; /* [4:0] */
+ __IO uint32_t osn2 : 5; /* [9:5] */
+ __IO uint32_t osn3 : 5; /* [14:10] */
+ __IO uint32_t osn4 : 5; /* [19:15] */
+ __IO uint32_t osn5 : 5; /* [24:20] */
+ __IO uint32_t osn6 : 5; /* [29:25] */
+ __IO uint32_t reserved1 : 2; /* [31:30] */
+ } osq3_bit;
+ };
+
+ /**
+ * @brief adc psq register, offset:0x38
+ */
+ union
+ {
+ __IO uint32_t psq;
+ struct
+ {
+ __IO uint32_t psn1 : 5; /* [4:0] */
+ __IO uint32_t psn2 : 5; /* [9:5] */
+ __IO uint32_t psn3 : 5; /* [14:10] */
+ __IO uint32_t psn4 : 5; /* [19:15] */
+ __IO uint32_t pclen : 2; /* [21:20] */
+ __IO uint32_t reserved1 : 10;/* [31:22] */
+ } psq_bit;
+ };
+
+ /**
+ * @brief adc pdt1 register, offset:0x3C
+ */
+ union
+ {
+ __IO uint32_t pdt1;
+ struct
+ {
+ __IO uint32_t pdt1 : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } pdt1_bit;
+ };
+
+ /**
+ * @brief adc pdt2 register, offset:0x40
+ */
+ union
+ {
+ __IO uint32_t pdt2;
+ struct
+ {
+ __IO uint32_t pdt2 : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } pdt2_bit;
+ };
+
+ /**
+ * @brief adc pdt3 register, offset:0x44
+ */
+ union
+ {
+ __IO uint32_t pdt3;
+ struct
+ {
+ __IO uint32_t pdt3 : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } pdt3_bit;
+ };
+
+ /**
+ * @brief adc pdt4 register, offset:0x48
+ */
+ union
+ {
+ __IO uint32_t pdt4;
+ struct
+ {
+ __IO uint32_t pdt4 : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } pdt4_bit;
+ };
+
+ /**
+ * @brief adc odt register, offset:0x4C
+ */
+ union
+ {
+ __IO uint32_t odt;
+ struct
+ {
+ __IO uint32_t odt : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } odt_bit;
+ };
+
+ __IO uint32_t reserved1[12];
+
+ /**
+ * @brief adc ovsp register, offset:0x80
+ */
+ union
+ {
+ __IO uint32_t ovsp;
+ struct
+ {
+ __IO uint32_t oosen : 1; /* [0] */
+ __IO uint32_t posen : 1; /* [1] */
+ __IO uint32_t osrsel : 3; /* [4:2] */
+ __IO uint32_t osssel : 4; /* [8:5] */
+ __IO uint32_t oostren : 1; /* [9] */
+ __IO uint32_t oosrsel : 1; /* [10] */
+ __IO uint32_t reserved1 : 21; /* [31:11] */
+ } ovsp_bit;
+ };
+} adc_type;
+
+/**
+ * @brief type define adc register all
+ */
+typedef struct
+{
+
+ /**
+ * @brief adc csts register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t csts;
+ struct
+ {
+ __IO uint32_t vmor1 : 1; /* [0] */
+ __IO uint32_t occe1 : 1; /* [1] */
+ __IO uint32_t pcce1 : 1; /* [2] */
+ __IO uint32_t pccs1 : 1; /* [3] */
+ __IO uint32_t occs1 : 1; /* [4] */
+ __IO uint32_t occo1 : 1; /* [5] */
+ __IO uint32_t rdy1 : 1; /* [6] */
+ __IO uint32_t tcf1 : 1; /* [7] */
+ __IO uint32_t vmor2 : 1; /* [8] */
+ __IO uint32_t occe2 : 1; /* [9] */
+ __IO uint32_t pcce2 : 1; /* [10] */
+ __IO uint32_t pccs2 : 1; /* [11] */
+ __IO uint32_t occs2 : 1; /* [12] */
+ __IO uint32_t occo2 : 1; /* [13] */
+ __IO uint32_t rdy2 : 1; /* [14] */
+ __IO uint32_t tcf2 : 1; /* [15] */
+ __IO uint32_t reserved3 : 16; /* [31:16] */
+ } csts_bit;
+ };
+
+ /**
+ * @brief adc cctrl register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t cctrl;
+ struct
+ {
+ __IO uint32_t mssel : 5; /* [4_0] */
+ __IO uint32_t reserved1 : 3; /* [7:5] */
+ __IO uint32_t asisel : 4; /* [11:8] */
+ __IO uint32_t reserved2 : 1; /* [12] */
+ __IO uint32_t msdrcen : 1; /* [13] */
+ __IO uint32_t msdmasel_l : 2; /* [15:14] */
+ __IO uint32_t adcdiv : 4; /* [19:16] */
+ __IO uint32_t reserved3 : 2; /* [21:20] */
+ __IO uint32_t vbaten : 1; /* [22] */
+ __IO uint32_t itsrven : 1; /* [23] */
+ __IO uint32_t reserved4 : 4; /* [27:24] */
+ __IO uint32_t msdmasel_h : 1; /* [28] */
+ __IO uint32_t reserved5 : 3; /* [31:29] */
+ } cctrl_bit;
+ };
+
+ /**
+ * @brief adc codt register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t codt;
+ struct
+ {
+ __IO uint32_t codtl : 16; /* [15:0] */
+ __IO uint32_t codth : 16; /* [31:16] */
+ } codt_bit;
+ };
+} adccom_type;
+
+/**
+ * @}
+ */
+
+#define ADC1 ((adc_type *) ADC1_BASE)
+#define ADC2 ((adc_type *) ADC2_BASE)
+#define ADCCOM ((adccom_type *) ADCCOM_BASE)
+
+/** @defgroup ADC_exported_functions
+ * @{
+ */
+
+void adc_reset(void);
+void adc_enable(adc_type *adc_x, confirm_state new_state);
+void adc_base_default_para_init(adc_base_config_type *adc_base_struct);
+void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct);
+void adc_common_default_para_init(adc_common_config_type *adc_common_struct);
+void adc_common_config(adc_common_config_type *adc_common_struct);
+void adc_combine_mode_set(adc_combine_mode_type combine_mode);
+uint32_t adc_combine_mode_get(void);
+void adc_voltage_battery_enable(confirm_state new_state);
+void adc_resolution_set(adc_type *adc_x, adc_resolution_type resolution);
+void adc_dma_mode_enable(adc_type *adc_x, confirm_state new_state);
+void adc_dma_request_repeat_enable(adc_type *adc_x, confirm_state new_state);
+void adc_interrupt_enable(adc_type *adc_x, uint32_t adc_int, confirm_state new_state);
+void adc_calibration_init(adc_type *adc_x);
+flag_status adc_calibration_init_status_get(adc_type *adc_x);
+void adc_calibration_start(adc_type *adc_x);
+flag_status adc_calibration_status_get(adc_type *adc_x);
+void adc_voltage_monitor_enable(adc_type *adc_x, adc_voltage_monitoring_type adc_voltage_monitoring);
+void adc_voltage_monitor_threshold_value_set(adc_type *adc_x, uint16_t adc_high_threshold, uint16_t adc_low_threshold);
+void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_select_type adc_channel);
+void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
+void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght);
+void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
+void adc_ordinary_conversion_trigger_set(adc_type *adc_x, adc_ordinary_trig_select_type adc_ordinary_trig, adc_ordinary_trig_edge_type adc_ordinary_trig_edge);
+void adc_preempt_conversion_trigger_set(adc_type *adc_x, adc_preempt_trig_select_type adc_preempt_trig, adc_preempt_trig_edge_type adc_preempt_trig_edge);
+void adc_preempt_offset_value_set(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel, uint16_t adc_offset_value);
+void adc_ordinary_part_count_set(adc_type *adc_x, uint8_t adc_channel_count);
+void adc_ordinary_part_mode_enable(adc_type *adc_x, confirm_state new_state);
+void adc_preempt_part_mode_enable(adc_type *adc_x, confirm_state new_state);
+void adc_preempt_auto_mode_enable(adc_type *adc_x, confirm_state new_state);
+void adc_conversion_stop(adc_type *adc_x);
+flag_status adc_conversion_stop_status_get(adc_type *adc_x);
+void adc_occe_each_conversion_enable(adc_type *adc_x, confirm_state new_state);
+void adc_ordinary_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
+flag_status adc_ordinary_software_trigger_status_get(adc_type *adc_x);
+void adc_preempt_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
+flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x);
+uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x);
+uint32_t adc_combine_ordinary_conversion_data_get(void);
+uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel);
+flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag);
+flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag);
+void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag);
+void adc_ordinary_oversample_enable(adc_type *adc_x, confirm_state new_state);
+void adc_preempt_oversample_enable(adc_type *adc_x, confirm_state new_state);
+void adc_oversample_ratio_shift_set(adc_type *adc_x, adc_oversample_ratio_type adc_oversample_ratio, adc_oversample_shift_type adc_oversample_shift);
+void adc_ordinary_oversample_trig_enable(adc_type *adc_x, confirm_state new_state);
+void adc_ordinary_oversample_restart_set(adc_type *adc_x, adc_ordinary_oversample_restart_type adc_ordinary_oversample_restart);
+void adc_convert_fail_auto_abort_enable(adc_type *adc_x, confirm_state new_state);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_aes.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_aes.h
new file mode 100644
index 00000000000..8049df2cfd6
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_aes.h
@@ -0,0 +1,369 @@
+/**
+ **************************************************************************
+ * @file at32f45x_aes.h
+ * @brief at32f45x aes header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_AES_H
+#define __AT32F45x_AES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f45x.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @addtogroup AES
+ * @{
+ */
+
+/** @defgroup AES_flags_definition
+ * @brief aes flag
+ * @{
+ */
+
+#define AES_PDFS_FLAG ((uint32_t)0x00000001) /*!< processing done flag */
+#define AES_REFS_FLAG ((uint32_t)0x00000002) /*!< read error flag */
+#define AES_WEFS_FLAG ((uint32_t)0x00000004) /*!< write error flag */
+#define AES_PBS_FLAG ((uint32_t)0x00000008) /*!< busy flag status */
+#define AES_NZDFS_FLAG ((uint32_t)0x00000010) /*!< non-zero dummy data processed flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup AES_interrupts_definition
+ * @brief aes interrupt
+ * @{
+ */
+
+#define AES_PDIE_INT ((uint32_t)0x00000200) /*!< processing done interrupt */
+#define AES_RWEIE_INT ((uint32_t)0x00000400) /*!< read and write error interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup AES_exported_types
+ * @{
+ */
+
+/**
+ * @brief aes key length type
+ */
+typedef enum
+{
+ AES_KEY_LENGTH_128 = 0, /*!< aes-128 */
+ AES_KEY_LENGTH_192 = 1, /*!< aes-192 */
+ AES_KEY_LENGTH_256 = 2 /*!< aes-256 */
+} aes_key_length_type;
+
+/**
+ * @brief aes operate mode type
+ */
+typedef enum
+{
+ AES_OPMODE_ENCRYPT = 0, /*!< encryption */
+ AES_OPMODE_KEY_SCHEDULING = 1, /*!< key expansion */
+ AES_OPMODE_DECRYPT = 2, /*!< decryption */
+ AES_OPMODE_KEY_SCHEDULING_DECRYPT = 3 /*!< key expansion and decryption */
+} aes_operate_mode_type;
+
+/**
+ * @brief aes data swap type
+ */
+typedef enum
+{
+ AES_SWAP_TYPE_NONE = 0, /*!< no swap */
+ AES_SWAP_TYPE_HALF_WROD = 1, /*!< half-word exchange on word */
+ AES_SWAP_TYPE_BYTE = 2, /*!< byte exchange on word */
+ AES_SWAP_TYPE_BIT = 3 /*!< bit exchange on word */
+} aes_data_swap_type;
+
+/**
+ * @brief aes chaining mode type
+ */
+typedef enum
+{
+ AES_CHMODE_ECB = 0, /*!< ecb */
+ AES_CHMODE_CBC = 1, /*!< cbc */
+ AES_CHMODE_CTR = 2, /*!< ctr */
+ AES_CHMODE_GCM = 3, /*!< gcm */
+ AES_CHMODE_CCM = 4 /*!< ccm */
+} aes_chaining_mode_type;
+
+/**
+ * @brief aes gcm/ccm processing stage type
+ */
+typedef enum
+{
+ AES_PRC_INIT = 0, /*!< initial stage */
+ AES_PRC_ASSOC = 1, /*!< assoc data stage */
+ AES_PRC_DATA = 2, /*!< data stage */
+ AES_PRC_TAG = 3 /*!< tag stage */
+} aes_processing_stage_type;
+
+/**
+ * @brief aes initial structure type
+ */
+typedef struct
+{
+ aes_operate_mode_type operate_mode; /*!< aes operation mode */
+ aes_chaining_mode_type chaining_mode; /*!< aes chaining mode */
+ aes_key_length_type key_len; /*!< aes key length */
+ uint32_t *key_buf; /*!< aes key value */
+ aes_data_swap_type data_swap_mode;/*!< aes data swap type */
+} aes_init_type;
+
+/**
+ * @brief type define aes register all
+ */
+typedef struct
+{
+ /**
+ * @brief aes ctrl register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t ctrl;
+ struct
+ {
+ __IO uint32_t aesen :1; /* [0] */
+ __IO uint32_t swp :2; /* [2:1] */
+ __IO uint32_t opr :2; /* [4:3] */
+ __IO uint32_t chn :3; /* [7:5] */
+ __IO uint32_t reserved1 :1; /* [8] */
+ __IO uint32_t pdie :1; /* [9] */
+ __IO uint32_t rweie :1; /* [10] */
+ __IO uint32_t dmawe :1; /* [11] */
+ __IO uint32_t dmare :1; /* [12] */
+ __IO uint32_t prc :2; /* [14:13] */
+ __IO uint32_t reserved2 :1; /* [15] */
+ __IO uint32_t reserved3 :1; /* [16] */
+ __IO uint32_t kl :2; /* [18:17] */
+ __IO uint32_t reserved4 :1; /* [19] */
+ __IO uint32_t ndd :4; /* [23:20] */
+ __IO uint32_t lst :1; /* [24] */
+ __IO uint32_t reserved5 :7; /* [31:25] */
+ } ctrl_bit;
+ };
+
+ /**
+ * @brief aes sts register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t pdfs :1; /* [0] */
+ __IO uint32_t refs :1; /* [1] */
+ __IO uint32_t wefs :1; /* [2] */
+ __IO uint32_t pbs :1; /* [3] */
+ __IO uint32_t nzdfs :1; /* [4] */
+ __IO uint32_t reserved1 :27;/* [31:5] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief aes idt register, offset:0x08
+ */
+ __IO uint32_t idt;
+
+ /**
+ * @brief aes odt register, offset:0x0C
+ */
+ __IO uint32_t odt;
+
+ /**
+ * @brief aes key0 register, offset:0x10
+ */
+ __IO uint32_t key0;
+
+ /**
+ * @brief aes key1 register, offset:0x14
+ */
+ __IO uint32_t key1;
+
+ /**
+ * @brief aes key2 register, offset:0x18
+ */
+ __IO uint32_t key2;
+
+ /**
+ * @brief aes key3 register, offset:0x1C
+ */
+ __IO uint32_t key3;
+
+ /**
+ * @brief aes iv0 register, offset:0x20
+ */
+ __IO uint32_t iv0;
+
+ /**
+ * @brief aes iv1 register, offset:0x24
+ */
+ __IO uint32_t iv1;
+
+ /**
+ * @brief aes iv2 register, offset:0x28
+ */
+ __IO uint32_t iv2;
+
+ /**
+ * @brief aes iv3 register, offset:0x2C
+ */
+ __IO uint32_t iv3;
+
+ /**
+ * @brief aes key4 register, offset:0x30
+ */
+ __IO uint32_t key4;
+
+ /**
+ * @brief aes key5 register, offset:0x34
+ */
+ __IO uint32_t key5;
+
+ /**
+ * @brief aes key6 register, offset:0x38
+ */
+ __IO uint32_t key6;
+
+ /**
+ * @brief aes key7 register, offset:0x3C
+ */
+ __IO uint32_t key7;
+
+ /**
+ * @brief aes si0 register, offset:0x40
+ */
+ __IO uint32_t si0;
+
+ /**
+ * @brief aes si1 register, offset:0x44
+ */
+ __IO uint32_t si1;
+
+ /**
+ * @brief aes si2 register, offset:0x48
+ */
+ __IO uint32_t si2;
+
+ /**
+ * @brief aes si3 register, offset:0x4C
+ */
+ __IO uint32_t si3;
+
+ /**
+ * @brief aes si4 register, offset:0x50
+ */
+ __IO uint32_t si4;
+
+ /**
+ * @brief aes si5 register, offset:0x54
+ */
+ __IO uint32_t si5;
+
+ /**
+ * @brief aes si6 register, offset:0x58
+ */
+ __IO uint32_t si6;
+
+ /**
+ * @brief aes si7 register, offset:0x5C
+ */
+ __IO uint32_t si7;
+
+ /**
+ * @brief aes fclr register, offset:0x60
+ */
+ union
+ {
+ __IO uint32_t fclr;
+ struct
+ {
+ __IO uint32_t pdfc :1; /* [0] */
+ __IO uint32_t refc :1; /* [1] */
+ __IO uint32_t wefc :1; /* [2] */
+ __IO uint32_t reserved1 :1; /* [3] */
+ __IO uint32_t nzdfc :1; /* [4] */
+ __IO uint32_t reserved2 :27;/* [31:5] */
+ } fclr_bit;
+ };
+
+} aes_type;
+
+/**
+ * @}
+ */
+
+#define AES ((aes_type*)AES_BASE)
+
+/** @defgroup AES_exported_functions
+ * @{
+ */
+
+void aes_reset(void);
+void aes_key_set(aes_key_length_type aes_kl, uint32_t* aes_key);
+void aes_iv_set(uint32_t* aes_iv);
+void aes_dummy_data_num_set(uint8_t num);
+void aes_processing_stage_set(aes_processing_stage_type prc_type);
+void aes_default_para_init(aes_init_type* aes_init_struct);
+void aes_init(aes_init_type* aes_init_struct);
+void aes_suspend_info_init(void);
+void aes_suspend_info_set(uint32_t* si_buf);
+void aes_operate_mode_set(aes_operate_mode_type op_mode);
+void aes_enable(confirm_state new_state);
+void aes_dma_in_enable(confirm_state new_state);
+void aes_dma_out_enable(confirm_state new_state);
+void aes_last_block_enable(confirm_state new_state);
+void aes_interrupt_enable(uint32_t aes_int, confirm_state new_state);
+flag_status aes_interrupt_flag_get(uint32_t flag);
+flag_status aes_flag_get(uint32_t flag);
+void aes_flag_clear(uint32_t flag);
+void aes_data_input(uint32_t* input_ptr);
+void aes_data_output(uint32_t* output_ptr);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_can.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_can.h
new file mode 100644
index 00000000000..657960c9133
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_can.h
@@ -0,0 +1,1200 @@
+/**
+ **************************************************************************
+ * @file at32f45x_can.h
+ * @brief at32f45x can header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_CAN_H
+#define __AT32F45x_CAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f45x.h"
+
+/* AT32F456xx and AT32F457xx support can-fd */
+#if defined (AT32F456xx) || defined (AT32F457xx)
+#define SUPPORT_CAN_FD
+#endif
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @{
+ */
+
+/** @defgroup CAN_interrupts_definition
+ * @brief can interrupt
+ * @{
+ */
+
+#define CAN_AIE_INT ((uint32_t)0x00000001) /*!< abort interrupt */
+#define CAN_EIE_INT ((uint32_t)0x00000002) /*!< error interrupt */
+#define CAN_TSIE_INT ((uint32_t)0x00000004) /*!< transmission of the secondary transmit buffer completed interrupt */
+#define CAN_TPIE_INT ((uint32_t)0x00000008) /*!< transmission of the primary transmit buffer completed interrupt */
+#define CAN_RAFIE_INT ((uint32_t)0x00000010) /*!< rxbuf almost full interrupt */
+#define CAN_RFIE_INT ((uint32_t)0x00000020) /*!< rxbuf full interrupt */
+#define CAN_ROIE_INT ((uint32_t)0x00000040) /*!< rxbuf overflow interrupt */
+#define CAN_RIE_INT ((uint32_t)0x00000080) /*!< receiver interrupt */
+#define CAN_BEIE_INT ((uint32_t)0x00000100) /*!< bus error interrupt */
+#define CAN_ALIE_INT ((uint32_t)0x00000200) /*!< arbitration lost interrupt */
+#define CAN_EPIE_INT ((uint32_t)0x00000400) /*!< error passive interrupt */
+#define CAN_TTIE_INT ((uint32_t)0x00000800) /*!< time trigger interrupt */
+#define CAN_TEIE_INT ((uint32_t)0x00001000) /*!< trigger error interrupt */
+#define CAN_WTIE_INT ((uint32_t)0x00002000) /*!< watch trigger interrupt */
+#define CAN_ALL_INT ((uint32_t)0xFFFFFFFF) /*!< all interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_flags_definition
+ * @brief can flag
+ * @{
+ */
+
+#define CAN_AIF_FLAG ((uint32_t)0x00000001) /*!< abort interrupt flag */
+#define CAN_EIF_FLAG ((uint32_t)0x00000002) /*!< error interrupt flag: error warning or busoff. */
+#define CAN_TSIF_FLAG ((uint32_t)0x00000004) /*!< transmission of the secondary transmit buffer be completed interrupt flag */
+#define CAN_TPIF_FLAG ((uint32_t)0x00000008) /*!< transmission of the primary transmit buffer be completed interrupt flag */
+#define CAN_RAFIF_FLAG ((uint32_t)0x00000010) /*!< rxbuf almost full interrupt flag */
+#define CAN_RFIF_FLAG ((uint32_t)0x00000020) /*!< rxbuf full interrupt flag */
+#define CAN_ROIF_FLAG ((uint32_t)0x00000040) /*!< rxbuf overflow interrupt flag */
+#define CAN_RIF_FLAG ((uint32_t)0x00000080) /*!< receiver interrupt flag */
+#define CAN_BEIF_FLAG ((uint32_t)0x00000100) /*!< bus error interrupt flag */
+#define CAN_ALIF_FLAG ((uint32_t)0x00000200) /*!< arbitration lost interrupt flag */
+#define CAN_EPIF_FLAG ((uint32_t)0x00000400) /*!< error passive interrupt flag */
+#define CAN_TTIF_FLAG ((uint32_t)0x00000800) /*!< time trigger interrupt flag */
+#define CAN_TEIF_FLAG ((uint32_t)0x00001000) /*!< trigger error interrupt flag */
+#define CAN_WTIF_FLAG ((uint32_t)0x00002000) /*!< watch trigger interrupt flag */
+#define CAN_EPASS_FLAG ((uint32_t)0x40000000) /*!< error passive status flag */
+#define CAN_EWARN_FLAG ((uint32_t)0x80000000) /*!< error warning limit reached status flag */
+#define CAN_ALL_FLAG ((uint32_t)0xFFFFFFFF) /*!< all interrupt and status flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @brief can identifier type
+ */
+typedef enum
+{
+ CAN_ID_STANDARD = 0x00, /*!< standard Id */
+ CAN_ID_EXTENDED = 0x01 /*!< extended Id */
+} can_identifier_type;
+
+/**
+ * @brief can frame type
+ */
+typedef enum
+{
+ CAN_FRAME_DATA = 0x00, /*!< data frame */
+ CAN_FRAME_REMOTE = 0x01 /*!< remote frame */
+} can_frame_type;
+
+#ifdef SUPPORT_CAN_FD
+/**
+ * @brief can format type
+ */
+typedef enum
+{
+ CAN_FORMAT_CLASSIC = 0x00, /*!< CLASSIC-CAN format */
+ CAN_FORMAT_FD = 0x01 /*!< FD-CAN format */
+} can_format_type;
+
+/**
+ * @brief can bitrate switch type
+ */
+typedef enum
+{
+ CAN_BRS_OFF = 0x00, /*!< bit rate switch off */
+ CAN_BRS_ON = 0x01 /*!< bit rate switch on */
+} can_rate_switch_type;
+
+/**
+ * @brief can error state indicator type
+ */
+typedef enum
+{
+ CAN_ESI_ACTIVE = 0x00, /*!< error_state_indicator active */
+ CAN_ESI_PASSIVE = 0x01 /*!< error_state_indicator passive */
+} can_error_state_type;
+#endif
+
+/**
+ * @brief can data length type
+ */
+typedef enum
+{
+ CAN_DLC_BYTES_0 = 0x00, /*!< 0 bytes data field */
+ CAN_DLC_BYTES_1 = 0x01, /*!< 1 bytes data field */
+ CAN_DLC_BYTES_2 = 0x02, /*!< 2 bytes data field */
+ CAN_DLC_BYTES_3 = 0x03, /*!< 3 bytes data field */
+ CAN_DLC_BYTES_4 = 0x04, /*!< 4 bytes data field */
+ CAN_DLC_BYTES_5 = 0x05, /*!< 5 bytes data field */
+ CAN_DLC_BYTES_6 = 0x06, /*!< 6 bytes data field */
+ CAN_DLC_BYTES_7 = 0x07, /*!< 7 bytes data field */
+ CAN_DLC_BYTES_8 = 0x08, /*!< 8 bytes data field */
+#ifdef SUPPORT_CAN_FD
+ CAN_DLC_BYTES_12 = 0x09, /*!< 12 bytes data field */
+ CAN_DLC_BYTES_16 = 0x0A, /*!< 16 bytes data field */
+ CAN_DLC_BYTES_20 = 0x0B, /*!< 20 bytes data field */
+ CAN_DLC_BYTES_24 = 0x0C, /*!< 24 bytes data field */
+ CAN_DLC_BYTES_32 = 0x0D, /*!< 32 bytes data field */
+ CAN_DLC_BYTES_48 = 0x0E, /*!< 48 bytes data field */
+ CAN_DLC_BYTES_64 = 0x0F /*!< 64 bytes data field */
+#endif
+} can_data_length_type;
+
+/**
+ * @brief can txbuf select type
+ */
+typedef enum
+{
+ CAN_TXBUF_PTB = 0x00, /*!< the primary transmit buffer (high priority) */
+ CAN_TXBUF_STB = 0x01 /*!< the secondary transmit buffer (low priority) */
+} can_txbuf_select_type;
+
+/**
+ * @brief can txbuf transmit type
+ */
+typedef enum
+{
+ CAN_TRANSMIT_PTB = 0x10, /*!< transmit the primary transmit buffer */
+ CAN_TRANSMIT_STB_ONE = 0x04, /*!< transmit one frame of the secondary transmit buffer */
+ CAN_TRANSMIT_STB_ALL = 0x02 /*!< transmit all frames of the secondary transmit buffer */
+} can_txbuf_transmit_type;
+
+/**
+ * @brief can abort transmit type
+ */
+typedef enum
+{
+ CAN_ABORT_TRANSMIT_PTB = 0x08, /*!< abort transmit of the primary transmit buffer */
+ CAN_ABORT_TRANSMIT_STB = 0x01 /*!< abort transmit of the secondary transmit buffer */
+} can_abort_transmit_type;
+
+/**
+ * @brief can clear the secondary transmit buffer type
+ */
+typedef enum
+{
+ CAN_CLEAR_STB_ONE = 0x05, /*!< clear one frame of the secondary transmit buffer */
+ CAN_CLEAR_STB_ALL = 0x03 /*!< clear all frames of the secondary transmit buffer */
+} can_clear_stb_type;
+
+/**
+ * @brief can the secondary transmit buffer transmit mode type
+ */
+typedef enum
+{
+ CAN_STB_TRANSMIT_BY_FIFO = 0x00, /*!< the secondary transmit buffer transmit by fifo */
+ CAN_STB_TRANSMIT_BY_ID = 0x01 /*!< the secondary transmit buffer transmit by id */
+} can_stb_transmit_mode_type;
+
+/**
+ * @brief can the secondary transmit buffer status type
+ */
+typedef enum
+{
+ CAN_STB_STATUS_EMPTY = 0x00, /*!< the secondary transmit buffer(0) is empty */
+ CAN_STB_STATUS_LESS = 0x01, /*!< the secondary transmit buffer(1) is less than or equal to half full */
+ CAN_STB_STATUS_MORE = 0x02, /*!< the secondary transmit buffer(2) is more than half full */
+ CAN_STB_STATUS_FULL = 0x03 /*!< the secondary transmit buffer(3) is full */
+} can_stb_status_type;
+
+/**
+ * @brief can rxbuf status type
+ */
+typedef enum
+{
+ CAN_RXBUF_STATUS_EMPTY = 0x00, /*!< rxbuf: empty */
+ CAN_RXBUF_STATUS_LESS = 0x01, /*!< rxbuf: > empty and < almost full(AFWL) */
+ CAN_RXBUF_STATUS_ALMOST = 0x02, /*!< rxbuf: >= almost full (programmable threshold by AFWL) but not full and no overflow */
+ CAN_RXBUF_STATUS_FULL = 0x03, /*!< rxbuf: full */
+ CAN_RXBUF_STATUS_OVERFLOW = 0x04 /*!< rxbuf: overflow */
+} can_rxbuf_status_type;
+
+/**
+ * @brief can rxbuf overflow mode type
+ */
+typedef enum
+{
+ CAN_RXBUF_OVERFLOW_BE_OVWR = 0x00, /*!< the oldest frame will be overwritten. */
+ CAN_RXBUF_OVERFLOW_BE_LOSE = 0x01 /*!< the new frame will not be stored. */
+} can_rxbuf_overflow_mode_type;
+
+/**
+ * @brief can timestamp position type
+ */
+typedef enum
+{
+ CAN_TIMESTAMP_AT_SOF = 0x00, /*!< time stamping position at sof */
+ CAN_TIMESTAMP_AT_EOF = 0x01 /*!< time stamping position at eof */
+} can_timestamp_position_type;
+
+/**
+ * @brief can error state indicator type
+ */
+typedef enum
+{
+ CAN_KOER_NOERR = 0x00, /*!< kind_of_error: no error */
+ CAN_KOER_BIT = 0x01, /*!< kind_of_error: bit error */
+ CAN_KOER_FORM = 0x02, /*!< kind_of_error: form error */
+ CAN_KOER_STUFF = 0x03, /*!< kind_of_error: stuff error */
+ CAN_KOER_ACK = 0x04, /*!< kind_of_error: ack error */
+ CAN_KOER_CRC = 0x05, /*!< kind_of_error: crc error */
+ CAN_KOER_OTHER = 0x06, /*!< kind_of_error: other error */
+ CAN_KOER_PCRC = 0x07 /*!< kind_of_error: pcrc error (can-xl only) */
+} can_error_type;
+
+/**
+ * @brief can receive frame type
+ */
+typedef enum
+{
+ CAN_RECV_NORMAL = 0x00, /*!< receive normal frame */
+ CAN_RECV_LOOPBACK = 0x01 /*!< receive loop back frame */
+} can_recv_frame_type;
+
+/**
+ * @brief can time_trigger_can timer_div type
+ */
+typedef enum
+{
+ CAN_TTCAN_TIMER_DIV_1 = 0x00, /*!< classic-can bit time div1 to ttcan timer */
+ CAN_TTCAN_TIMER_DIV_2 = 0x01, /*!< classic-can bit time div2 to ttcan timer */
+ CAN_TTCAN_TIMER_DIV_4 = 0x02, /*!< classic-can bit time div4 to ttcan timer */
+ CAN_TTCAN_TIMER_DIV_8 = 0x03, /*!< classic-can bit time div8 to ttcan timer */
+} can_ttcan_timer_div_type;
+
+/**
+ * @brief can time_trigger_can trigger type
+ */
+typedef enum
+{
+ CAN_TTCAN_TRIGGER_IMMEDIATE = 0x00, /*!< immediate trigger for immediate transmission */
+ CAN_TTCAN_TRIGGER_TIME = 0x01, /*!< time trigger for receive triggers */
+ CAN_TTCAN_TRIGGER_SINGLE_TRANSMIT = 0x02, /*!< single shot transmit trigger for exclusive time windows */
+ CAN_TTCAN_TRIGGER_TRANSMIT_START = 0x03, /*!< transmit start trigger for merged arbitrating time windows */
+ CAN_TTCAN_TRIGGER_TRANSMIT_STOP = 0x04, /*!< transmit stop trigger for merged arbitrating time windows */
+} can_ttcan_trigger_type;
+
+/**
+ * @brief can ttcan txbuf slot status type
+ */
+typedef enum
+{
+ CAN_TTCAN_TXBUF_EMPTY = 0x00, /*!< set ttcan txbuf slot to "empty" */
+ CAN_TTCAN_TXBUF_FILLED = 0x01, /*!< set ttcan txbuf slot to "filled" */
+} can_ttcan_txbuf_status_type;
+
+/**
+ * @brief can re-transmission times type
+ */
+typedef enum
+{
+ CAN_RE_TRANS_TIMES_0 = 0x00, /*!< re-transmission 0 times */
+ CAN_RE_TRANS_TIMES_1 = 0x01, /*!< re-transmission 1 times */
+ CAN_RE_TRANS_TIMES_2 = 0x02, /*!< re-transmission 2 times */
+ CAN_RE_TRANS_TIMES_3 = 0x03, /*!< re-transmission 3 times */
+ CAN_RE_TRANS_TIMES_4 = 0x04, /*!< re-transmission 4 times */
+ CAN_RE_TRANS_TIMES_5 = 0x05, /*!< re-transmission 5 times */
+ CAN_RE_TRANS_TIMES_6 = 0x06, /*!< re-transmission 6 times */
+ CAN_RE_TRANS_TIMES_UNLIMIT = 0x07 /*!< re-transmission unlimited times */
+} can_retransmission_times_type;
+
+/**
+ * @brief can re-arbitration times type
+ */
+typedef enum
+{
+ CAN_RE_ARBI_TIMES_0 = 0x00, /*!< re-arbitration 0 times */
+ CAN_RE_ARBI_TIMES_1 = 0x01, /*!< re-arbitration 1 times */
+ CAN_RE_ARBI_TIMES_2 = 0x02, /*!< re-arbitration 2 times */
+ CAN_RE_ARBI_TIMES_3 = 0x03, /*!< re-arbitration 3 times */
+ CAN_RE_ARBI_TIMES_4 = 0x04, /*!< re-arbitration 4 times */
+ CAN_RE_ARBI_TIMES_5 = 0x05, /*!< re-arbitration 5 times */
+ CAN_RE_ARBI_TIMES_6 = 0x06, /*!< re-arbitration 6 times */
+ CAN_RE_ARBI_TIMES_UNLIMIT = 0x07 /*!< re-arbitration unlimited times */
+} can_rearbitration_times_type;
+
+/**
+ * @brief can mode type
+ */
+typedef enum
+{
+ CAN_MODE_COMMUNICATE = 0x00, /*!< normal communication mode */
+ CAN_MODE_EXT_LOOPBACK = 0x01, /*!< external loopback mode */
+ CAN_MODE_EXT_LOOPBACK_ACK = 0x02, /*!< external loopback mode with self-ack */
+ CAN_MODE_INT_LOOPBACK = 0x03, /*!< internal loopback mode */
+ CAN_MODE_LISTENONLY = 0x04, /*!< listen-only mode */
+ CAN_MODE_LISTENONLY_EXT = 0x05, /*!< listen-only combined with external loopback mode */
+ CAN_MODE_LISTENONLY_EXT_ACK = 0x06 /*!< listen-only combined with external loopback mode with self-ack */
+} can_mode_type;
+
+/**
+ * @brief can transmit state encoding type
+ */
+typedef enum
+{
+ CAN_TSTAT_IDLE = 0x00, /*!< no transmission in progress */
+ CAN_TSTAT_ONGOING = 0x01, /*!< transmission active without any issues */
+ CAN_TSTAT_LOST_ARBITRATION = 0x02, /*!< arbitration lost. re-arbitration may take place with respect to REALIM. */
+ CAN_TSTAT_TRANSMITTED = 0x03, /*!< transmission successfully completed */
+ CAN_TSTAT_ABORTED = 0x04, /*!< transmission aborted */
+ CAN_TSTAT_DISTURBED = 0x05, /*!< transmission error. retransmission may take place with respect to RETLIM. */
+ CAN_TSTAT_REJECTED = 0x06 /*!< misconfiguration of the frame format in the LLC frame. */
+} can_tstat_encoding_type;
+
+/**
+ * @brief can filter type
+ */
+typedef enum
+{
+ CAN_FILTER_NUM_0 = 0x00, /*!< can filter number 0 */
+ CAN_FILTER_NUM_1 = 0x01, /*!< can filter number 1 */
+ CAN_FILTER_NUM_2 = 0x02, /*!< can filter number 2 */
+ CAN_FILTER_NUM_3 = 0x03, /*!< can filter number 3 */
+ CAN_FILTER_NUM_4 = 0x04, /*!< can filter number 4 */
+ CAN_FILTER_NUM_5 = 0x05, /*!< can filter number 5 */
+ CAN_FILTER_NUM_6 = 0x06, /*!< can filter number 6 */
+ CAN_FILTER_NUM_7 = 0x07, /*!< can filter number 7 */
+ CAN_FILTER_NUM_8 = 0x08, /*!< can filter number 8 */
+ CAN_FILTER_NUM_9 = 0x09, /*!< can filter number 9 */
+ CAN_FILTER_NUM_10 = 0x0A, /*!< can filter number 10 */
+ CAN_FILTER_NUM_11 = 0x0B, /*!< can filter number 11 */
+ CAN_FILTER_NUM_12 = 0x0C, /*!< can filter number 12 */
+ CAN_FILTER_NUM_13 = 0x0D, /*!< can filter number 13 */
+ CAN_FILTER_NUM_14 = 0x0E, /*!< can filter number 14 */
+ CAN_FILTER_NUM_15 = 0x0F, /*!< can filter number 15 */
+} can_filter_type;
+
+/**
+ * @brief can ttcan txbuf type
+ */
+typedef enum
+{
+ CAN_TTCAN_TXBUF_NUM_0 = 0x00, /*!< can ttcan txbuf number 0 */
+ CAN_TTCAN_TXBUF_NUM_1 = 0x01, /*!< can ttcan txbuf number 1 */
+ CAN_TTCAN_TXBUF_NUM_2 = 0x02, /*!< can ttcan txbuf number 2 */
+ CAN_TTCAN_TXBUF_NUM_3 = 0x03, /*!< can ttcan txbuf number 3 */
+} can_ttcan_txbuf_type;
+
+/**
+ * @brief can transmit status structure definition
+ */
+typedef struct
+{
+ uint8_t current_handle; /*!< specifies current handle for frame identification. */
+
+ can_tstat_encoding_type current_tstat; /*!< specifies current transmission status of transmit frame.*/
+
+ uint8_t final_handle; /*!< specifies final handle for frame identification. */
+
+ can_tstat_encoding_type final_tstat; /*!< specifies final transmission status of transmit frame.*/
+
+} can_transmit_status_type;
+
+/**
+ * @brief can transmit buffer structure definition
+ */
+typedef struct
+{
+ uint32_t id; /*!< specifies the 11 or 29 bits standard or extended identifier.
+ this parameter can be a value between 0 to 0x7FF or 0 to 0x1FFFFFFF. */
+
+ can_identifier_type id_type; /*!< specifies identifier type for the transmit buffer. */
+
+ can_frame_type frame_type; /*!< specifies frame type for the transmit buffer. */
+
+ can_data_length_type data_length; /*!< specifies the frame data length that will be transmitted. */
+
+#ifdef SUPPORT_CAN_FD
+ can_format_type fd_format; /*!< specifies format for the transmit buffer. */
+
+ can_rate_switch_type fd_rate_switch; /*!< specifies bit rate switch for the transmit buffer. */
+
+ uint8_t data[64]; /*!< contains the transmit data. it ranges from 0 to 0xFF. */
+#else
+ uint8_t data[8]; /*!< contains the transmit data. it ranges from 0 to 0xFF. */
+#endif
+
+ confirm_state tx_timestamp; /*!< specifies get transmit timestamp for the transmit buffer. */
+
+ uint8_t handle; /*!< The purpose of the handle is frame identification using TSTAT(transmit status). */
+
+} can_txbuf_type;
+
+/**
+ * @brief can receive buffer structure definition
+ */
+typedef struct
+{
+ uint32_t id; /*!< specifies the 11 or 29 bits standard or extended identifier.
+ this parameter can be a value between 0 to 0x7FF or 0 to 0x1FFFFFFF. */
+
+ can_identifier_type id_type; /*!< specifies identifier type for the receive buffer. */
+
+ can_frame_type frame_type; /*!< specifies frame type for the receive buffer. */
+
+ can_data_length_type data_length; /*!< specifies the frame data length that will be received. */
+
+#ifdef SUPPORT_CAN_FD
+ can_format_type fd_format; /*!< specifies format for the receive buffer. */
+
+ can_rate_switch_type fd_rate_switch; /*!< specifies bit rate switch for the receive buffer. */
+
+ can_error_state_type fd_error_state; /*!< specifies error state indicator type for the receive buffer. */
+
+ uint8_t data[64]; /*!< contains the receive data. it ranges from 0 to 0xFF. */
+#else
+ uint8_t data[8]; /*!< contains the receive data. it ranges from 0 to 0xFF. */
+#endif
+
+ can_recv_frame_type recv_frame; /*!< specifies receive frame mode for the receive buffer. */
+
+ can_error_type kind_error; /*!< specifies kind of error type for the receive buffer. */
+
+ uint32_t rx_timestamp; /*!< specifies the timestamp for the receive buffer. */
+
+ uint16_t cycle_time; /*!< specifies the cycle time for the receive buffer using TTCAN(Time-Triggered CAN). */
+
+} can_rxbuf_type;
+
+/**
+ * @brief can filter code type
+ */
+typedef struct
+{
+ uint32_t id; /*!< specifies the 11 or 29 bits standard or extended identifier.
+ this parameter can be a value between 0 to 0x7FF or 0 to 0x1FFFFFFF. */
+
+ can_identifier_type id_type; /*!< specifies identifier type for the filter code. */
+
+ can_frame_type frame_type; /*!< specifies frame type for the filter code. */
+
+ uint8_t data_length; /*!< specifies frame data length for the filter code. */
+
+#ifdef SUPPORT_CAN_FD
+ can_format_type fd_format; /*!< specifies format for the filter code. */
+
+ can_rate_switch_type fd_rate_switch; /*!< specifies bit rate switch for the filter code. */
+
+ can_error_state_type fd_error_state; /*!< specifies error state indicator for the filter code. */
+#endif
+
+ can_recv_frame_type recv_frame; /*!< specifies receive frame mode for the filter code. */
+
+} can_filter_code_type;
+
+/**
+ * @brief can filter mask type
+ */
+typedef struct
+{
+ uint32_t id; /*!< specifies the 11 or 29 bits standard or extended identifier.
+ this parameter can be a value between 0 to 0x7FF or 0 to 0x1FFFFFFF. */
+
+ confirm_state id_type; /*!< specifies identifier type for the filter mask. */
+
+ confirm_state frame_type; /*!< specifies frame type for the filter mask. */
+
+ uint8_t data_length; /*!< specifies frame data length for the filter mask. */
+
+#ifdef SUPPORT_CAN_FD
+ confirm_state fd_format; /*!< specifies format for the filter mask. */
+
+ confirm_state fd_rate_switch; /*!< specifies bit rate switch for the filter mask. */
+
+ confirm_state fd_error_state; /*!< specifies error state indicator for the filter mask. */
+#endif
+
+ confirm_state recv_frame; /*!< specifies receive frame mode for the filter mask. */
+
+} can_filter_mask_type;
+
+/**
+ * @brief can filter config type
+ */
+typedef struct
+{
+ can_filter_code_type code_para; /*!< specifies the filter code type. */
+
+ can_filter_mask_type mask_para; /*!< specifies the filter mask type. */
+
+} can_filter_config_type;
+
+/**
+ * @brief can baudrate structure definition
+ */
+typedef struct
+{
+ uint8_t bittime_div; /*!< bittime division, this parameter can be 0x01~0x20. */
+
+ uint8_t ac_rsaw_size; /*!< classic-can resynchronization adjust width, this parameter can be 0x01~0x80. */
+
+ uint16_t ac_bts1_size; /*!< classic-can bit time segment 1, this parameter can be 0x02~0x201. */
+
+ uint8_t ac_bts2_size; /*!< classic-can bit time segment 2, this parameter can be 0x01~0x80. */
+
+#ifdef SUPPORT_CAN_FD
+ uint8_t fd_rsaw_size; /*!< can-fd resynchronization adjust width, this parameter can be 0x01~0x80. */
+
+ uint16_t fd_bts1_size; /*!< can-fd bit time segment 1, this parameter can be 0x02~0x101. */
+
+ uint8_t fd_bts2_size; /*!< can-fd bit time segment 2, this parameter can be 0x01~0x80. */
+
+ uint8_t fd_ssp_offset; /*!< can-fd secondary sample point offset, this parameter can be 0x00~0xFF. */
+#endif
+
+} can_bittime_type;
+
+/**
+ * @brief type define can register all
+ */
+typedef struct
+{
+ /**
+ * @brief can tncfg register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t tncfg;
+ struct
+ {
+ __IO uint32_t reserved1 : 17;/* [16:0] */
+ __IO uint32_t rop : 1; /* [17] */
+ __IO uint32_t reserved2 : 6; /* [23:18] */
+ __IO uint32_t tsen : 1; /* [24] */
+ __IO uint32_t tspos : 1; /* [25] */
+ __IO uint32_t reserved3 : 6; /* [31:26] */
+ } tncfg_bit;
+ };
+
+ /**
+ * @brief can actime register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t actime;
+ struct
+ {
+ __IO uint32_t ac_seg_1 : 9; /* [8:0] */
+ __IO uint32_t reserved1 : 7; /* [15:9] */
+ __IO uint32_t ac_seg_2 : 7; /* [22:16] */
+ __IO uint32_t reserved2 : 1; /* [23] */
+ __IO uint32_t ac_sjw : 7; /* [30:24] */
+ __IO uint32_t reserved3 : 1; /* [31] */
+ } actime_bit;
+ };
+
+ /**
+ * @brief can fdtime register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t fdtime;
+ struct
+ {
+ __IO uint32_t fd_seg_1 : 8; /* [7:0] */
+ __IO uint32_t reserved1 : 8; /* [15:8] */
+ __IO uint32_t fd_seg_2 : 7; /* [22:16] */
+ __IO uint32_t reserved2 : 1; /* [23] */
+ __IO uint32_t fd_sjw : 7; /* [30:24] */
+ __IO uint32_t reserved3 : 1; /* [31] */
+ } fdtime_bit;
+ };
+
+ /**
+ * @brief can reserved1 register, offset:0x0C
+ */
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief can lbtcfg register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t lbtcfg;
+ struct
+ {
+ __IO uint32_t presc : 5; /* [4:0] */
+ __IO uint32_t reserved1 : 3; /* [7:5] */
+ __IO uint32_t fd_sspoff : 8; /* [15:8] */
+ __IO uint32_t reserved2 : 8; /* [23:16] */
+ __IO uint32_t realim : 3; /* [26:24] */
+ __IO uint32_t reserved3 : 1; /* [27] */
+ __IO uint32_t retlim : 3; /* [30:28] */
+ __IO uint32_t reserved4 : 1; /* [31] */
+ } lbtcfg_bit;
+ };
+
+ /**
+ * @brief can sts register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t aif : 1; /* [0] */
+ __IO uint32_t eif : 1; /* [1] */
+ __IO uint32_t tsif : 1; /* [2] */
+ __IO uint32_t tpif : 1; /* [3] */
+ __IO uint32_t rafif : 1; /* [4] */
+ __IO uint32_t rfif : 1; /* [5] */
+ __IO uint32_t roif : 1; /* [6] */
+ __IO uint32_t rif : 1; /* [7] */
+ __IO uint32_t beif : 1; /* [8] */
+ __IO uint32_t alif : 1; /* [9] */
+ __IO uint32_t epif : 1; /* [10] */
+ __IO uint32_t ttif : 1; /* [11] */
+ __IO uint32_t teif : 1; /* [12] */
+ __IO uint32_t wtif : 1; /* [13] */
+ __IO uint32_t reserved1 : 16; /* [29:14] */
+ __IO uint32_t epass : 1; /* [30] */
+ __IO uint32_t ewarn : 1; /* [31] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief can reserved register, offset:0x18
+ */
+ __IO uint32_t reserved2;
+
+ /**
+ * @brief can tstat register, offset:0x1C
+ */
+ union
+ {
+ __IO uint32_t tstat;
+ struct
+ {
+ __IO uint32_t handle_1 : 8; /* [7:0] */
+ __IO uint32_t tstat_1 : 3; /* [10:8] */
+ __IO uint32_t reserved1 : 5; /* [15:11] */
+ __IO uint32_t handle_2 : 8; /* [23:16] */
+ __IO uint32_t tstat_2 : 3; /* [26:24] */
+ __IO uint32_t reserved2 : 5; /* [31:27] */
+ } tstat_bit;
+ };
+
+ /**
+ * @brief can tts register, offset:0x20
+ */
+ __IO uint32_t tts;
+
+ /**
+ * @brief can reserved register, offset:0x24
+ */
+ __IO uint32_t reserved3;
+
+ /**
+ * @brief can ctrlstat register, offset:0x28
+ */
+ union
+ {
+ __IO uint32_t ctrlstat;
+ struct
+ {
+ __IO uint32_t busoff : 1; /* [0] */
+ __IO uint32_t reserved1 : 4; /* [4:1] */
+ __IO uint32_t lbmi : 1; /* [5] */
+ __IO uint32_t lbme : 1; /* [6] */
+ __IO uint32_t reset : 1; /* [7] */
+ __IO uint32_t tsa : 1; /* [8] */
+ __IO uint32_t tsall : 1; /* [9] */
+ __IO uint32_t tsone : 1; /* [10] */
+ __IO uint32_t tpa : 1; /* [11] */
+ __IO uint32_t tpe : 1; /* [12] */
+ __IO uint32_t stby : 1; /* [13] */
+ __IO uint32_t lom : 1; /* [14] */
+ __IO uint32_t tbsel : 1; /* [15] */
+ __IO uint32_t tsstat : 2; /* [17:16] */
+ __IO uint32_t tsff : 1; /* [18] */
+ __IO uint32_t reserved2 : 1; /* [19] */
+ __IO uint32_t tttbm : 1; /* [20] */
+ __IO uint32_t tsmode : 1; /* [21] */
+ __IO uint32_t tsnext : 1; /* [22] */
+ __IO uint32_t fd_iso : 1; /* [23] */
+ __IO uint32_t rstat : 2; /* [25:24] */
+ __IO uint32_t reserved3 : 1; /* [26] */
+ __IO uint32_t rball : 1; /* [27] */
+ __IO uint32_t rrel : 1; /* [28] */
+ __IO uint32_t rov : 1; /* [29] */
+ __IO uint32_t rom : 1; /* [30] */
+ __IO uint32_t sack : 1; /* [31] */
+ } ctrlstat_bit;
+ };
+
+ /**
+ * @brief can err register, offset:0x2C
+ */
+ union
+ {
+ __IO uint32_t err;
+ struct
+ {
+ __IO uint32_t ewl : 4; /* [3:0] */
+ __IO uint32_t afwl : 4; /* [7:4] */
+ __IO uint32_t alc : 5; /* [12:8] */
+ __IO uint32_t koer : 3; /* [15:13] */
+ __IO uint32_t recnt : 8; /* [23:16] */
+ __IO uint32_t tecnt : 8; /* [31:24] */
+ } err_bit;
+ };
+
+ /**
+ * @brief can refmsg register, offset:0x30
+ */
+ union
+ {
+ __IO uint32_t refmsg;
+ struct
+ {
+ __IO uint32_t ref_id : 29; /* [28:0] */
+ __IO uint32_t reserved1 : 2; /* [30:29] */
+ __IO uint32_t ref_ide : 1; /* [31] */
+ } refmsg_bit;
+ };
+
+ /**
+ * @brief can ttcfg register, offset:0x34
+ */
+ union
+ {
+ __IO uint32_t ttcfg;
+ struct
+ {
+ __IO uint32_t ttptr : 6; /* [5:0] */
+ __IO uint32_t reserved1 : 2; /* [7:6] */
+ __IO uint32_t ttype : 3; /* [10:8] */
+ __IO uint32_t reserved2 : 1; /* [11] */
+ __IO uint32_t tew : 4; /* [15:12] */
+ __IO uint32_t tbptr : 6; /* [21:16] */
+ __IO uint32_t tbf : 1; /* [22] */
+ __IO uint32_t tbe : 1; /* [23] */
+ __IO uint32_t tten : 1; /* [24] */
+ __IO uint32_t t_presc : 2; /* [26:25] */
+ __IO uint32_t reserved3 : 5; /* [31:27] */
+ } ttcfg_bit;
+ };
+
+ /**
+ * @brief can tttrig register, offset:0x38
+ */
+ union
+ {
+ __IO uint32_t tttrig;
+ struct
+ {
+ __IO uint32_t tttrig : 16; /* [15:0] */
+ __IO uint32_t ttwtrig : 16; /* [31:16] */
+ } tttrig_bit;
+ };
+
+ /**
+ * @brief can reserved register, offset:0x3C-0x40
+ */
+ __IO uint32_t reserved4[2];
+
+ /**
+ * @brief can acfctrl register, offset:0x44
+ */
+ union
+ {
+ __IO uint32_t acfctrl;
+ struct
+ {
+ __IO uint32_t acfadr : 4; /* [3:0] */
+ __IO uint32_t reserved1 : 12; /* [15:4] */
+ __IO uint32_t ae_x : 16; /* [31:16] */
+ } acfctrl_bit;
+ };
+
+ /**
+ * @brief can fcid register, offset:0x48
+ */
+ __IO uint32_t fcid;
+
+ /**
+ * @brief can fcfmt register, offset:0x4C
+ */
+ union
+ {
+ __IO uint32_t fcfmt;
+ struct
+ {
+ __IO uint32_t dlc : 4; /* [3:0] */
+ __IO uint32_t reserved1 : 12; /* [15:4] */
+ __IO uint32_t ide : 1; /* [16] */
+ __IO uint32_t fdf : 1; /* [17] */
+ __IO uint32_t brs : 1; /* [18] */
+ __IO uint32_t xlf : 1; /* [19] */
+ __IO uint32_t rmf : 1; /* [20] */
+ __IO uint32_t sec : 1; /* [21] */
+ __IO uint32_t reserved2 : 2; /* [23:22] */
+ __IO uint32_t koer : 3; /* [26:24] */
+ __IO uint32_t esi : 1; /* [27] */
+ __IO uint32_t lbf : 1; /* [28] */
+ __IO uint32_t reserved3 : 3; /* [31:29] */
+ } fcfmt_bit;
+ };
+
+ /**
+ * @brief can fctyp register, offset:0x50
+ */
+ union
+ {
+ __IO uint32_t fctyp;
+ struct
+ {
+ __IO uint32_t sdt : 8; /* [7:0] */
+ __IO uint32_t vcid : 8; /* [15:8] */
+ __IO uint32_t reserved1 : 8; /* [23:16] */
+ __IO uint32_t handle : 8; /* [31:24] */
+ } fctyp_bit;
+ };
+
+ /**
+ * @brief can reserved register, offset:0x54
+ */
+ __IO uint32_t reserved5;
+
+ /**
+ * @brief can fmid register, offset:0x58
+ */
+ __IO uint32_t fmid;
+
+ /**
+ * @brief can fmfmt register, offset:0x5C
+ */
+ union
+ {
+ __IO uint32_t fmfmt;
+ struct
+ {
+ __IO uint32_t dlc : 4; /* [3:0] */
+ __IO uint32_t reserved1 : 12; /* [15:4] */
+ __IO uint32_t ide : 1; /* [16] */
+ __IO uint32_t fdf : 1; /* [17] */
+ __IO uint32_t brs : 1; /* [18] */
+ __IO uint32_t xlf : 1; /* [19] */
+ __IO uint32_t rmf : 1; /* [20] */
+ __IO uint32_t sec : 1; /* [21] */
+ __IO uint32_t reserved2 : 2; /* [23:22] */
+ __IO uint32_t koer : 3; /* [26:24] */
+ __IO uint32_t esi : 1; /* [27] */
+ __IO uint32_t lbf : 1; /* [28] */
+ __IO uint32_t reserved3 : 3; /* [31:29] */
+ } fmfmt_bit;
+ };
+
+ /**
+ * @brief can fmtyp register, offset:0x60
+ */
+ union
+ {
+ __IO uint32_t fmtyp;
+ struct
+ {
+ __IO uint32_t sdt : 8; /* [7:0] */
+ __IO uint32_t vcid : 8; /* [15:8] */
+ __IO uint32_t reserved1 : 8; /* [23:16] */
+ __IO uint32_t handle : 8; /* [31:24] */
+ } fmtyp_bit;
+ };
+
+ /**
+ * @brief can reserved register, offset:0x64-0x6C
+ */
+ __IO uint32_t reserved6[3];
+
+ /**
+ * @brief can rbid register, offset:0x70
+ */
+ __IO uint32_t rbid;
+
+ /**
+ * @brief can rbfmt register, offset:0x74
+ */
+ union
+ {
+ __IO uint32_t rbfmt;
+ struct
+ {
+ __IO uint32_t dlc : 4; /* [3:0] */
+ __IO uint32_t reserved1 : 12; /* [15:4] */
+ __IO uint32_t ide : 1; /* [16] */
+ __IO uint32_t fdf : 1; /* [17] */
+ __IO uint32_t brs : 1; /* [18] */
+ __IO uint32_t xlf : 1; /* [19] */
+ __IO uint32_t rmf : 1; /* [20] */
+ __IO uint32_t sec : 1; /* [21] */
+ __IO uint32_t reserved2 : 2; /* [23:22] */
+ __IO uint32_t koer : 3; /* [26:24] */
+ __IO uint32_t esi : 1; /* [27] */
+ __IO uint32_t lbf : 1; /* [28] */
+ __IO uint32_t reserved3 : 3; /* [31:29] */
+ } rbfmt_bit;
+ };
+
+ /**
+ * @brief can rbtyp register, offset:0x78
+ */
+ union
+ {
+ __IO uint32_t rbtyp;
+ struct
+ {
+ __IO uint32_t sdt : 8; /* [7:0] */
+ __IO uint32_t vcid : 8; /* [15:8] */
+ __IO uint32_t reserved1 : 8; /* [23:16] */
+ __IO uint32_t handle : 8; /* [31:24] */
+ } rbtyp_bit;
+ };
+
+ /**
+ * @brief can reserved register, offset:0x7C
+ */
+ __IO uint32_t reserved7;
+
+ /**
+ * @brief can rbdat register, offset:0x80-0xC8
+ */
+ __IO uint32_t rbdat[19];
+
+ /**
+ * @brief can tbid register, offset:0xCC
+ */
+ __IO uint32_t tbid;
+
+ /**
+ * @brief can tbfmt register, offset:0xD0
+ */
+ union
+ {
+ __IO uint32_t tbfmt;
+ struct
+ {
+ __IO uint32_t dlc : 4; /* [3:0] */
+ __IO uint32_t reserved1 : 12; /* [15:4] */
+ __IO uint32_t ide : 1; /* [16] */
+ __IO uint32_t fdf : 1; /* [17] */
+ __IO uint32_t brs : 1; /* [18] */
+ __IO uint32_t xlf : 1; /* [19] */
+ __IO uint32_t rmf : 1; /* [20] */
+ __IO uint32_t sec : 1; /* [21] */
+ __IO uint32_t reserved2 : 2; /* [23:22] */
+ __IO uint32_t koer : 3; /* [26:24] */
+ __IO uint32_t esi : 1; /* [27] */
+ __IO uint32_t lbf : 1; /* [28] */
+ __IO uint32_t reserved3 : 3; /* [31:29] */
+ } tbfmt_bit;
+ };
+
+ /**
+ * @brief can tbtyp register, offset:0xD4
+ */
+ union
+ {
+ __IO uint32_t tbtyp;
+ struct
+ {
+ __IO uint32_t sdt : 8; /* [7:0] */
+ __IO uint32_t vcid : 8; /* [15:8] */
+ __IO uint32_t reserved1 : 8; /* [23:16] */
+ __IO uint32_t handle : 8; /* [31:24] */
+ } tbtyp_bit;
+ };
+
+ /**
+ * @brief can reserved register, offset:0xD8
+ */
+ __IO uint32_t reserved8;
+
+ /**
+ * @brief can tbdat register, offset:0xDC-0x118
+ */
+ __IO uint32_t tbdat[16];
+
+ /**
+ * @brief can reserved register, offset:0x11C-0x120
+ */
+ __IO uint32_t reserved9[2];
+
+ /**
+ * @brief can llcformat register, offset:0x124
+ */
+ __IO uint32_t llcformat;
+
+ /**
+ * @brief can llcsize register, offset:0x128
+ */
+ union
+ {
+ __IO uint32_t llcsize;
+ struct
+ {
+ __IO uint32_t llcpbytes : 16; /* [15:0] */
+ __IO uint32_t llcaot : 16; /* [31:16] */
+ } llcsize_bit;
+ };
+
+ /**
+ * @brief can reserved register, offset:0x12C-0x13C
+ */
+ __IO uint32_t reserved10[5];
+
+ /**
+ * @brief can inten register, offset:0x140
+ */
+ union
+ {
+ __IO uint32_t inten;
+ struct
+ {
+ __IO uint32_t aien : 1; /* [0] */
+ __IO uint32_t eien : 1; /* [1] */
+ __IO uint32_t tsien : 1; /* [2] */
+ __IO uint32_t tpien : 1; /* [3] */
+ __IO uint32_t rafien : 1; /* [4] */
+ __IO uint32_t rfien : 1; /* [5] */
+ __IO uint32_t roien : 1; /* [6] */
+ __IO uint32_t rien : 1; /* [7] */
+ __IO uint32_t beien : 1; /* [8] */
+ __IO uint32_t alien : 1; /* [9] */
+ __IO uint32_t epien : 1; /* [10] */
+ __IO uint32_t ttien : 1; /* [11] */
+ __IO uint32_t teien : 1; /* [12] */
+ __IO uint32_t wtien : 1; /* [13] */
+ __IO uint32_t reserved1 : 18; /* [31:14] */
+ } inten_bit;
+ };
+} can_type;
+
+#define CAN1 ((can_type *) CAN1_BASE)
+#define CAN2 ((can_type *) CAN2_BASE)
+#define CAN3 ((can_type *) CAN3_BASE)
+
+/** @defgroup CAN_exported_functions
+ * @{
+ */
+
+void can_reset(can_type* can_x);
+void can_software_reset(can_type* can_x, confirm_state new_state);
+#ifdef SUPPORT_CAN_FD
+void can_fd_iso_mode_enable(can_type* can_x, confirm_state new_state);
+#endif
+void can_mode_set(can_type* can_x, can_mode_type mode_selection);
+error_status can_standby_mode_enable(can_type* can_x, confirm_state new_state);
+void can_restricted_operation_enable(can_type* can_x, confirm_state new_state);
+void can_bittime_default_para_init(can_bittime_type* can_bittime_struct);
+void can_bittime_set(can_type* can_x, can_bittime_type* can_bittime_struct);
+void can_retransmission_limit_set(can_type* can_x, can_retransmission_times_type re_trans_times);
+void can_rearbitration_limit_set(can_type* can_x, can_rearbitration_times_type re_arbi_times);
+void can_timestamp_enable(can_type* can_x, confirm_state new_state);
+void can_timestamp_position_set(can_type* can_x, can_timestamp_position_type timestamp_position);
+
+uint32_t can_transmit_timestamp_get(can_type* can_x);
+error_status can_txbuf_write(can_type* can_x, can_txbuf_select_type txbuf_type, can_txbuf_type* can_txbuf_struct);
+error_status can_txbuf_transmit(can_type* can_x, can_txbuf_transmit_type transmit_type);
+void can_transmit_abort(can_type* can_x, can_abort_transmit_type abort_type);
+void can_stb_transmit_mode_set(can_type* can_x, can_stb_transmit_mode_type stb_transmit_mode);
+can_stb_status_type can_stb_status_get(can_type* can_x);
+void can_transmit_status_get(can_type* can_x, can_transmit_status_type* transmit_status_struct);
+error_status can_stb_clear(can_type* can_x, can_clear_stb_type clear_type);
+
+void can_rxbuf_overflow_mode_set(can_type* can_x, can_rxbuf_overflow_mode_type rxbuf_overflow_mode);
+void can_receive_all_enable(can_type* can_x, confirm_state new_state);
+error_status can_rxbuf_read(can_type* can_x, can_rxbuf_type* can_rxbuf_struct);
+error_status can_rxbuf_release(can_type* can_x);
+can_rxbuf_status_type can_rxbuf_status_get(can_type* can_x);
+
+void can_filter_enable(can_type* can_x, can_filter_type filter_number, confirm_state new_state);
+void can_filter_default_para_init(can_filter_config_type* filter_config_struct);
+void can_filter_set(can_type* can_x, can_filter_type filter_number, can_filter_config_type* filter_config_struct);
+
+uint8_t can_arbitration_lost_position_get(can_type* can_x);
+void can_rxbuf_warning_set(can_type* can_x, uint8_t warning_value);
+void can_error_warning_set(can_type* can_x, uint8_t warning_value);
+can_error_type can_kind_error_get(can_type* can_x);
+uint8_t can_receive_error_counter_get(can_type* can_x);
+uint8_t can_transmit_error_counter_get(can_type* can_x);
+flag_status can_busoff_get(can_type* can_x);
+void can_busoff_reset(can_type* can_x);
+
+void can_ttcan_ref_message_set(can_type* can_x, can_identifier_type id_type, uint32_t id);
+void can_ttcan_timer_div_set(can_type* can_x, can_ttcan_timer_div_type div_value);
+void can_ttcan_enable(can_type* can_x, confirm_state new_state);
+void can_ttcan_trigger_type_set(can_type* can_x, can_ttcan_trigger_type trigger_type);
+void can_ttcan_trigger_set(can_type* can_x, uint16_t trigger_time);
+void can_ttcan_watch_trigger_set(can_type* can_x, uint16_t watch_trigger_time);
+void can_ttcan_transmit_window_set(can_type* can_x, uint8_t window_ticks);
+void can_ttcan_txbuf_enable(can_type* can_x, confirm_state new_state);
+void can_ttcan_txbuf_status_set(can_type* can_x, can_ttcan_txbuf_type txbuf_number, can_ttcan_txbuf_status_type status_type);
+can_ttcan_txbuf_status_type can_ttcan_txbuf_status_get(can_type* can_x, can_ttcan_txbuf_type txbuf_number);
+void can_ttcan_txbuf_transmit_set(can_type* can_x, can_ttcan_txbuf_type txbuf_number);
+error_status can_ttcan_txbuf_write(can_type* can_x, can_ttcan_txbuf_type txbuf_number, can_txbuf_type* can_txbuf_struct);
+
+void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state);
+flag_status can_flag_get(can_type* can_x, uint32_t can_flag);
+flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag);
+void can_flag_clear(can_type* can_x, uint32_t can_flag);
+
+/*
+note:
+the following functions is only support can-fd.
+ - can_fd_iso_mode_enable
+the following functions is support classic-can and can-fd.
+ - can_bittime_default_para_init
+ - can_bittime_set
+ - can_txbuf_write
+ - can_rxbuf_read
+ - can_filter_default_para_init
+ - can_filter_set
+ - can_ttcan_txbuf_write
+*/
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_crc.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_crc.h
new file mode 100644
index 00000000000..14327b25998
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_crc.h
@@ -0,0 +1,198 @@
+/**
+ **************************************************************************
+ * @file at32f45x_crc.h
+ * @brief at32f45x crc header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_CRC_H
+#define __AT32F45x_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f45x.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @addtogroup CRC
+ * @{
+ */
+
+/** @defgroup CRC_exported_types
+ * @{
+ */
+
+/**
+ * @brief crc reverse input data
+ */
+typedef enum
+{
+ CRC_REVERSE_INPUT_NO_AFFECTE = 0x00, /*!< input data no reverse */
+ CRC_REVERSE_INPUT_BY_BYTE = 0x01, /*!< input data reverse by byte */
+ CRC_REVERSE_INPUT_BY_HALFWORD = 0x02, /*!< input data reverse by half word */
+ CRC_REVERSE_INPUT_BY_WORD = 0x03 /*!< input data reverse by word */
+} crc_reverse_input_type;
+
+/**
+ * @brief crc reverse output data
+ */
+typedef enum
+{
+ CRC_REVERSE_OUTPUT_NO_AFFECTE = 0x00, /*!< output data no reverse */
+ CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */
+} crc_reverse_output_type;
+
+/**
+ * @brief crc polynomial size
+ */
+typedef enum
+{
+ CRC_POLY_SIZE_32B = 0x00, /*!< polynomial size 32 bits */
+ CRC_POLY_SIZE_16B = 0x01, /*!< polynomial size 16 bits */
+ CRC_POLY_SIZE_8B = 0x02, /*!< polynomial size 8 bits */
+ CRC_POLY_SIZE_7B = 0x03 /*!< polynomial size 7 bits */
+} crc_poly_size_type;
+
+/**
+ * @brief type define crc register all
+ */
+typedef struct
+{
+ /**
+ * @brief crc dt register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t dt;
+ struct
+ {
+ __IO uint32_t dt : 32; /* [31:0] */
+ } dt_bit;
+ };
+
+ /**
+ * @brief crc cdt register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t cdt;
+ struct
+ {
+ __IO uint32_t cdt : 8 ; /* [7:0] */
+ __IO uint32_t reserved1 : 24 ;/* [31:8] */
+ } cdt_bit;
+ };
+
+ /**
+ * @brief crc ctrl register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t ctrl;
+ struct
+ {
+ __IO uint32_t rst : 1 ; /* [0] */
+ __IO uint32_t reserved1 : 2 ; /* [2:1] */
+ __IO uint32_t poly_size : 2 ; /* [4:3] */
+ __IO uint32_t revid : 2 ; /* [6:5] */
+ __IO uint32_t revod : 1 ; /* [7] */
+ __IO uint32_t reserved2 : 24 ;/* [31:8] */
+ } ctrl_bit;
+ };
+
+ /**
+ * @brief crm reserved1 register, offset:0x0C
+ */
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief crc idt register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t idt;
+ struct
+ {
+ __IO uint32_t idt : 32; /* [31:0] */
+ } idt_bit;
+ };
+
+ /**
+ * @brief crc polynomial register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t poly;
+ struct
+ {
+ __IO uint32_t poly : 32; /* [31:0] */
+ } poly_bit;
+ };
+
+} crc_type;
+
+/**
+ * @}
+ */
+
+#define CRC ((crc_type *) CRC_BASE)
+
+/** @defgroup CRC_exported_functions
+ * @{
+ */
+
+void crc_data_reset(void);
+uint32_t crc_one_word_calculate(uint32_t data);
+uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length);
+uint32_t crc_data_get(void);
+void crc_common_data_set(uint8_t cdt_value);
+uint8_t crc_common_data_get(void);
+void crc_init_data_set(uint32_t value);
+void crc_reverse_input_data_set(crc_reverse_input_type value);
+void crc_reverse_output_data_set(crc_reverse_output_type value);
+void crc_poly_value_set(uint32_t value);
+uint32_t crc_poly_value_get(void);
+void crc_poly_size_set(crc_poly_size_type size);
+crc_poly_size_type crc_poly_size_get(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_crm.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_crm.h
new file mode 100644
index 00000000000..4e266d032e7
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_crm.h
@@ -0,0 +1,1370 @@
+/**
+ **************************************************************************
+ * @file at32f45x_crm.h
+ * @brief at32f45x crm header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_CRM_H
+#define __AT32F45x_CRM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f45x.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @addtogroup CRM
+ * @{
+ */
+
+#define CRM_REG(value) PERIPH_REG(CRM_BASE, value)
+#define CRM_REG_BIT(value) PERIPH_REG_BIT(value)
+
+/** @defgroup CRM_flags_definition
+ * @brief crm flag
+ * @{
+ */
+
+#define CRM_HICK_STABLE_FLAG MAKE_VALUE(0x00, 1) /*!< high speed internal clock stable flag */
+#define CRM_HEXT_STABLE_FLAG MAKE_VALUE(0x00, 17) /*!< high speed external crystal stable flag */
+#define CRM_PLL_STABLE_FLAG MAKE_VALUE(0x00, 25) /*!< phase locking loop stable flag */
+#define CRM_PLLU_STABLE_FLAG MAKE_VALUE(0x00, 26) /*!< phase locking loop usb path stable flag */
+#define CRM_LEXT_STABLE_FLAG MAKE_VALUE(0x70, 1) /*!< low speed external crystal stable flag */
+#define CRM_LICK_STABLE_FLAG MAKE_VALUE(0x74, 1) /*!< low speed internal clock stable flag */
+#define CRM_ALL_RESET_FLAG MAKE_VALUE(0x74, 24) /*!< all reset flag */
+#define CRM_NRST_RESET_FLAG MAKE_VALUE(0x74, 26) /*!< nrst pin reset flag */
+#define CRM_POR_RESET_FLAG MAKE_VALUE(0x74, 27) /*!< power on reset flag */
+#define CRM_SW_RESET_FLAG MAKE_VALUE(0x74, 28) /*!< software reset flag */
+#define CRM_WDT_RESET_FLAG MAKE_VALUE(0x74, 29) /*!< watchdog timer reset flag */
+#define CRM_WWDT_RESET_FLAG MAKE_VALUE(0x74, 30) /*!< window watchdog timer reset flag */
+#define CRM_LOWPOWER_RESET_FLAG MAKE_VALUE(0x74, 31) /*!< low-power reset flag */
+#define CRM_LICK_READY_INT_FLAG MAKE_VALUE(0x0C, 0) /*!< low speed internal clock stable interrupt ready flag */
+#define CRM_LEXT_READY_INT_FLAG MAKE_VALUE(0x0C, 1) /*!< low speed external crystal stable interrupt ready flag */
+#define CRM_HICK_READY_INT_FLAG MAKE_VALUE(0x0C, 2) /*!< high speed internal clock stable interrupt ready flag */
+#define CRM_HEXT_READY_INT_FLAG MAKE_VALUE(0x0C, 3) /*!< high speed external crystal stable interrupt ready flag */
+#define CRM_PLL_READY_INT_FLAG MAKE_VALUE(0x0C, 4) /*!< phase locking loop stable interrupt ready flag */
+#define CRM_CLOCK_FAILURE_INT_FLAG MAKE_VALUE(0x0C, 7) /*!< clock failure interrupt ready flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRM_interrupts_definition
+ * @brief crm interrupt
+ * @{
+ */
+
+#define CRM_LICK_STABLE_INT ((uint32_t)0x00000100) /*!< low speed internal clock stable interrupt */
+#define CRM_LEXT_STABLE_INT ((uint32_t)0x00000200) /*!< low speed external crystal stable interrupt */
+#define CRM_HICK_STABLE_INT ((uint32_t)0x00000400) /*!< high speed internal clock stable interrupt */
+#define CRM_HEXT_STABLE_INT ((uint32_t)0x00000800) /*!< high speed external crystal stable interrupt */
+#define CRM_PLL_STABLE_INT ((uint32_t)0x00001000) /*!< phase locking loop stable interrupt */
+#define CRM_CLOCK_FAILURE_INT ((uint32_t)0x00800000) /*!< clock failure interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup CRM_exported_types
+ * @{
+ */
+
+/**
+ * @brief crm periph clock
+ */
+typedef enum
+{
+ /* ahb periph1 */
+ CRM_GPIOA_PERIPH_CLOCK = MAKE_VALUE(0x30, 0), /*!< gpioa periph clock */
+ CRM_GPIOB_PERIPH_CLOCK = MAKE_VALUE(0x30, 1), /*!< gpiob periph clock */
+ CRM_GPIOC_PERIPH_CLOCK = MAKE_VALUE(0x30, 2), /*!< gpioc periph clock */
+ CRM_GPIOD_PERIPH_CLOCK = MAKE_VALUE(0x30, 3), /*!< gpiod periph clock */
+ CRM_GPIOE_PERIPH_CLOCK = MAKE_VALUE(0x30, 4), /*!< gpioe periph clock */
+ CRM_GPIOF_PERIPH_CLOCK = MAKE_VALUE(0x30, 5), /*!< gpiof periph clock */
+ CRM_GPIOG_PERIPH_CLOCK = MAKE_VALUE(0x30, 6), /*!< gpiog periph clock */
+ CRM_GPIOH_PERIPH_CLOCK = MAKE_VALUE(0x30, 7), /*!< gpioh periph clock */
+ CRM_CRC_PERIPH_CLOCK = MAKE_VALUE(0x30, 12), /*!< crc periph clock */
+ CRM_DMA1_PERIPH_CLOCK = MAKE_VALUE(0x30, 22), /*!< dma1 periph clock */
+ CRM_DMA2_PERIPH_CLOCK = MAKE_VALUE(0x30, 24), /*!< dma2 periph clock */
+ CRM_EMAC_PERIPH_CLOCK = MAKE_VALUE(0x30, 25), /*!< emac periph clock */
+ CRM_EMACTX_PERIPH_CLOCK = MAKE_VALUE(0x30, 26), /*!< emactx periph clock */
+ CRM_EMACRX_PERIPH_CLOCK = MAKE_VALUE(0x30, 27), /*!< emacrx periph clock */
+ CRM_EMACPTP_PERIPH_CLOCK = MAKE_VALUE(0x30, 28), /*!< emacptp periph clock */
+ /* ahb periph2 */
+ CRM_AES_PERIPH_CLOCK = MAKE_VALUE(0x34, 4), /*!< aes periph clock */
+ CRM_TRNG_PERIPH_CLOCK = MAKE_VALUE(0x34, 6), /*!< trng periph clock */
+ CRM_OTGFS1_PERIPH_CLOCK = MAKE_VALUE(0x34, 7), /*!< otgfs1 periph clock */
+ CRM_SDIO1_PERIPH_CLOCK = MAKE_VALUE(0x34, 15), /*!< sdio1 periph clock */
+ /* ahb periph3 */
+ CRM_XMC_PERIPH_CLOCK = MAKE_VALUE(0x38, 0), /*!< xmc periph clock */
+ CRM_QSPI1_PERIPH_CLOCK = MAKE_VALUE(0x38, 1), /*!< qspi1 periph clock */
+ /* apb1 periph */
+ CRM_TMR2_PERIPH_CLOCK = MAKE_VALUE(0x40, 0), /*!< tmr2 periph clock */
+ CRM_TMR3_PERIPH_CLOCK = MAKE_VALUE(0x40, 1), /*!< tmr3 periph clock */
+ CRM_TMR4_PERIPH_CLOCK = MAKE_VALUE(0x40, 2), /*!< tmr4 periph clock */
+ CRM_TMR5_PERIPH_CLOCK = MAKE_VALUE(0x40, 3), /*!< tmr5 periph clock */
+ CRM_TMR6_PERIPH_CLOCK = MAKE_VALUE(0x40, 4), /*!< tmr6 periph clock */
+ CRM_TMR7_PERIPH_CLOCK = MAKE_VALUE(0x40, 5), /*!< tmr7 periph clock */
+ CRM_TMR12_PERIPH_CLOCK = MAKE_VALUE(0x40, 6), /*!< tmr12 periph clock */
+ CRM_TMR13_PERIPH_CLOCK = MAKE_VALUE(0x40, 7), /*!< tmr13 periph clock */
+ CRM_TMR14_PERIPH_CLOCK = MAKE_VALUE(0x40, 8), /*!< tmr14 periph clock */
+ CRM_WWDT_PERIPH_CLOCK = MAKE_VALUE(0x40, 11), /*!< wwdt periph clock */
+ CRM_SPI2_PERIPH_CLOCK = MAKE_VALUE(0x40, 14), /*!< spi2 periph clock */
+ CRM_SPI3_PERIPH_CLOCK = MAKE_VALUE(0x40, 15), /*!< spi3 periph clock */
+ CRM_USART2_PERIPH_CLOCK = MAKE_VALUE(0x40, 17), /*!< usart2 periph clock */
+ CRM_USART3_PERIPH_CLOCK = MAKE_VALUE(0x40, 18), /*!< usart3 periph clock */
+ CRM_USART4_PERIPH_CLOCK = MAKE_VALUE(0x40, 19), /*!< usart4 periph clock */
+ CRM_USART5_PERIPH_CLOCK = MAKE_VALUE(0x40, 20), /*!< usart5 periph clock */
+ CRM_I2C1_PERIPH_CLOCK = MAKE_VALUE(0x40, 21), /*!< i2c1 periph clock */
+ CRM_I2C2_PERIPH_CLOCK = MAKE_VALUE(0x40, 22), /*!< i2c2 periph clock */
+ CRM_I2C3_PERIPH_CLOCK = MAKE_VALUE(0x40, 23), /*!< i2c3 periph clock */
+ CRM_CAN1_PERIPH_CLOCK = MAKE_VALUE(0x40, 25), /*!< can1 periph clock */
+ CRM_CAN2_PERIPH_CLOCK = MAKE_VALUE(0x40, 26), /*!< can2 periph clock */
+ CRM_CAN3_PERIPH_CLOCK = MAKE_VALUE(0x40, 27), /*!< can3 periph clock */
+ CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x40, 28), /*!< pwc periph clock */
+ CRM_DAC_PERIPH_CLOCK = MAKE_VALUE(0x40, 29), /*!< dac periph clock */
+ CRM_USART7_PERIPH_CLOCK = MAKE_VALUE(0x40, 30), /*!< usart7 periph clock */
+ CRM_USART8_PERIPH_CLOCK = MAKE_VALUE(0x40, 31), /*!< usart8 periph clock */
+ /* apb2 periph */
+ CRM_TMR1_PERIPH_CLOCK = MAKE_VALUE(0x44, 0), /*!< tmr1 periph clock */
+ CRM_TMR8_PERIPH_CLOCK = MAKE_VALUE(0x44, 1), /*!< tmr8 periph clock */
+ CRM_USART1_PERIPH_CLOCK = MAKE_VALUE(0x44, 4), /*!< usart1 periph clock */
+ CRM_USART6_PERIPH_CLOCK = MAKE_VALUE(0x44, 5), /*!< usart6 periph clock */
+ CRM_ADC2_PERIPH_CLOCK = MAKE_VALUE(0x44, 9), /*!< adc2 periph clock */
+ CRM_ADC1_PERIPH_CLOCK = MAKE_VALUE(0x44, 8), /*!< adc1 periph clock */
+ CRM_SPI1_PERIPH_CLOCK = MAKE_VALUE(0x44, 12), /*!< spi1 periph clock */
+ CRM_SPI4_PERIPH_CLOCK = MAKE_VALUE(0x44, 13), /*!< spi4 periph clock */
+ CRM_SCFG_PERIPH_CLOCK = MAKE_VALUE(0x44, 14), /*!< scfg periph clock */
+ CRM_TMR9_PERIPH_CLOCK = MAKE_VALUE(0x44, 16), /*!< tmr9 periph clock */
+ CRM_TMR10_PERIPH_CLOCK = MAKE_VALUE(0x44, 17), /*!< tmr10 periph clock */
+ CRM_TMR11_PERIPH_CLOCK = MAKE_VALUE(0x44, 18), /*!< tmr11 periph clock */
+ CRM_I2SF5_PERIPH_CLOCK = MAKE_VALUE(0x44, 20), /*!< i2sf5 periph clock */
+ CRM_ACC_PERIPH_CLOCK = MAKE_VALUE(0x44, 29), /*!< acc periph clock */
+ CRM_I2S2EXT_PERIPH_CLOCK = MAKE_VALUE(0x44, 30), /*!< i2s2ext periph clock */
+ CRM_I2S3EXT_PERIPH_CLOCK = MAKE_VALUE(0x44, 31) /*!< i2s3ext periph clock */
+
+} crm_periph_clock_type;
+
+/**
+ * @brief crm periph reset
+ */
+typedef enum
+{
+ /* ahb periph1 */
+ CRM_GPIOA_PERIPH_RESET = MAKE_VALUE(0x10, 0), /*!< gpioa periph reset */
+ CRM_GPIOB_PERIPH_RESET = MAKE_VALUE(0x10, 1), /*!< gpiob periph reset */
+ CRM_GPIOC_PERIPH_RESET = MAKE_VALUE(0x10, 2), /*!< gpioc periph reset */
+ CRM_GPIOD_PERIPH_RESET = MAKE_VALUE(0x10, 3), /*!< gpiod periph reset */
+ CRM_GPIOE_PERIPH_RESET = MAKE_VALUE(0x10, 4), /*!< gpioe periph reset */
+ CRM_GPIOF_PERIPH_RESET = MAKE_VALUE(0x10, 5), /*!< gpiof periph reset */
+ CRM_GPIOG_PERIPH_RESET = MAKE_VALUE(0x10, 6), /*!< gpiog periph reset */
+ CRM_GPIOH_PERIPH_RESET = MAKE_VALUE(0x10, 7), /*!< gpioh periph reset */
+ CRM_CRC_PERIPH_RESET = MAKE_VALUE(0x10, 12), /*!< crc periph reset */
+ CRM_DMA1_PERIPH_RESET = MAKE_VALUE(0x10, 22), /*!< dma1 periph reset */
+ CRM_DMA2_PERIPH_RESET = MAKE_VALUE(0x10, 24), /*!< dma2 periph reset */
+ CRM_EMAC_PERIPH_RESET = MAKE_VALUE(0x10, 25), /*!< emac periph reset */
+ /* ahb periph2 */
+ CRM_AES_PERIPH_RESET = MAKE_VALUE(0x14, 4), /*!< aes periph clock reset */
+ CRM_TRNG_PERIPH_RESET = MAKE_VALUE(0x14, 6), /*!< trng periph clock reset */
+ CRM_OTGFS1_PERIPH_RESET = MAKE_VALUE(0x14, 7), /*!< otgfs1 periph reset */
+ CRM_SDIO1_PERIPH_RESET = MAKE_VALUE(0x14, 15), /*!< sdio1 periph reset */
+ /* ahb periph3 */
+ CRM_XMC_PERIPH_RESET = MAKE_VALUE(0x18, 0), /*!< xmc periph reset */
+ CRM_QSPI1_PERIPH_RESET = MAKE_VALUE(0x18, 1), /*!< qspi1 periph reset */
+ /* apb1 periph */
+ CRM_TMR2_PERIPH_RESET = MAKE_VALUE(0x20, 0), /*!< tmr2 periph reset */
+ CRM_TMR3_PERIPH_RESET = MAKE_VALUE(0x20, 1), /*!< tmr3 periph reset */
+ CRM_TMR4_PERIPH_RESET = MAKE_VALUE(0x20, 2), /*!< tmr4 periph reset */
+ CRM_TMR5_PERIPH_RESET = MAKE_VALUE(0x20, 3), /*!< tmr5 periph reset */
+ CRM_TMR6_PERIPH_RESET = MAKE_VALUE(0x20, 4), /*!< tmr6 periph reset */
+ CRM_TMR7_PERIPH_RESET = MAKE_VALUE(0x20, 5), /*!< tmr7 periph reset */
+ CRM_TMR12_PERIPH_RESET = MAKE_VALUE(0x20, 6), /*!< tmr12 periph reset */
+ CRM_TMR13_PERIPH_RESET = MAKE_VALUE(0x20, 7), /*!< tmr13 periph reset */
+ CRM_TMR14_PERIPH_RESET = MAKE_VALUE(0x20, 8), /*!< tmr14 periph reset */
+ CRM_WWDT_PERIPH_RESET = MAKE_VALUE(0x20, 11), /*!< wwdt periph reset */
+ CRM_SPI2_PERIPH_RESET = MAKE_VALUE(0x20, 14), /*!< spi2 periph reset */
+ CRM_SPI3_PERIPH_RESET = MAKE_VALUE(0x20, 15), /*!< spi3 periph reset */
+ CRM_USART2_PERIPH_RESET = MAKE_VALUE(0x20, 17), /*!< usart2 periph reset */
+ CRM_USART3_PERIPH_RESET = MAKE_VALUE(0x20, 18), /*!< usart3 periph reset */
+ CRM_USART4_PERIPH_RESET = MAKE_VALUE(0x20, 19), /*!< usart4 periph reset */
+ CRM_USART5_PERIPH_RESET = MAKE_VALUE(0x20, 20), /*!< usart5 periph reset */
+ CRM_I2C1_PERIPH_RESET = MAKE_VALUE(0x20, 21), /*!< i2c1 periph reset */
+ CRM_I2C2_PERIPH_RESET = MAKE_VALUE(0x20, 22), /*!< i2c2 periph reset */
+ CRM_I2C3_PERIPH_RESET = MAKE_VALUE(0x20, 23), /*!< i2c3 periph reset */
+ CRM_CAN1_PERIPH_RESET = MAKE_VALUE(0x20, 25), /*!< can1 periph reset */
+ CRM_CAN2_PERIPH_RESET = MAKE_VALUE(0x20, 26), /*!< can2 periph reset */
+ CRM_CAN3_PERIPH_RESET = MAKE_VALUE(0x20, 27), /*!< can3 periph reset */
+ CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x20, 28), /*!< pwc periph reset */
+ CRM_DAC_PERIPH_RESET = MAKE_VALUE(0x20, 29), /*!< dac periph reset */
+ CRM_USART7_PERIPH_RESET = MAKE_VALUE(0x20, 30), /*!< usart7 periph reset */
+ CRM_USART8_PERIPH_RESET = MAKE_VALUE(0x20, 31), /*!< usart8 periph reset */
+ /* apb2 periph */
+ CRM_TMR1_PERIPH_RESET = MAKE_VALUE(0x24, 0), /*!< tmr1 periph reset */
+ CRM_TMR8_PERIPH_RESET = MAKE_VALUE(0x24, 1), /*!< tmr8 periph reset */
+ CRM_USART1_PERIPH_RESET = MAKE_VALUE(0x24, 4), /*!< usart1 periph reset */
+ CRM_USART6_PERIPH_RESET = MAKE_VALUE(0x24, 5), /*!< usart6 periph reset */
+ CRM_ADC_PERIPH_RESET = MAKE_VALUE(0x24, 8), /*!< adc periph reset */
+ CRM_SPI1_PERIPH_RESET = MAKE_VALUE(0x24, 12), /*!< spi1 periph reset */
+ CRM_SPI4_PERIPH_RESET = MAKE_VALUE(0x24, 13), /*!< spi4 periph reset */
+ CRM_SCFG_PERIPH_RESET = MAKE_VALUE(0x24, 14), /*!< scfg periph reset */
+ CRM_TMR9_PERIPH_RESET = MAKE_VALUE(0x24, 16), /*!< tmr9 periph reset */
+ CRM_TMR10_PERIPH_RESET = MAKE_VALUE(0x24, 17), /*!< tmr10 periph reset */
+ CRM_TMR11_PERIPH_RESET = MAKE_VALUE(0x24, 18), /*!< tmr11 periph reset */
+ CRM_I2SF5_PERIPH_RESET = MAKE_VALUE(0x24, 20), /*!< i2sf5 periph reset */
+ CRM_ACC_PERIPH_RESET = MAKE_VALUE(0x24, 29), /*!< acc periph reset */
+ CRM_I2S2EXT_PERIPH_RESET = MAKE_VALUE(0x24, 30), /*!< i2s2ext periph reset */
+ CRM_I2S3EXT_PERIPH_RESET = MAKE_VALUE(0x24, 31) /*!< i2s3ext periph reset */
+
+} crm_periph_reset_type;
+
+/**
+ * @brief crm periph clock in low power mode
+ */
+typedef enum
+{
+ /* ahb periph1 */
+ CRM_GPIOA_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 0), /*!< gpioa sleep mode periph clock */
+ CRM_GPIOB_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 1), /*!< gpiob sleep mode periph clock */
+ CRM_GPIOC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 2), /*!< gpioc sleep mode periph clock */
+ CRM_GPIOD_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 3), /*!< gpiod sleep mode periph clock */
+ CRM_GPIOE_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 4), /*!< gpioe sleep mode periph clock */
+ CRM_GPIOF_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 5), /*!< gpiof sleep mode periph clock */
+ CRM_GPIOG_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 6), /*!< gpiog sleep mode periph clock */
+ CRM_GPIOH_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 7), /*!< gpioh sleep mode periph clock */
+ CRM_CRC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 12), /*!< crc sleep mode periph clock */
+ CRM_FLASH_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 15), /*!< flash sleep mode periph clock */
+ CRM_SRAM_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 16), /*!< sram sleep mode periph clock */
+ CRM_DMA1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 22), /*!< dma1 sleep mode periph clock */
+ CRM_DMA2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 24), /*!< dma2 sleep mode periph clock */
+ CRM_EMAC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 25), /*!< emac sleep mode periph clock */
+ CRM_EMACTX_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 26), /*!< emactx sleep mode periph clock */
+ CRM_EMACRX_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 27), /*!< emacrx sleep mode periph clock */
+ CRM_EMACPTP_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 28), /*!< emacptp sleep mode periph clock */
+ /* ahb periph2 */
+ CRM_AES_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 4), /*!< aes sleep mode periph clock */
+ CRM_TRNG_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 6), /*!< trng sleep mode periph clock */
+ CRM_OTGFS1_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 7), /*!< otgfs1 sleep mode periph clock */
+ CRM_SDIO1_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 15), /*!< sdio1 sleep mode periph clock */
+ /* ahb periph3 */
+ CRM_XMC_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 0), /*!< xmc sleep mode periph clock */
+ CRM_QSPI1_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 1), /*!< qspi1 sleep mode periph clock */
+ /* apb1 periph */
+ CRM_TMR2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 0), /*!< tmr2 sleep mode periph clock */
+ CRM_TMR3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 1), /*!< tmr3 sleep mode periph clock */
+ CRM_TMR4_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 2), /*!< tmr4 sleep mode periph clock */
+ CRM_TMR5_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 3), /*!< tmr5 sleep mode periph clock */
+ CRM_TMR6_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 4), /*!< tmr6 sleep mode periph clock */
+ CRM_TMR7_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 5), /*!< tmr7 sleep mode periph clock */
+ CRM_TMR12_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 6), /*!< tmr12 sleep mode periph clock */
+ CRM_TMR13_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 7), /*!< tmr13 sleep mode periph clock */
+ CRM_TMR14_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 8), /*!< tmr14 sleep mode periph clock */
+ CRM_WWDT_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 11), /*!< wwdt sleep mode periph clock */
+ CRM_SPI2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 14), /*!< spi2 sleep mode periph clock */
+ CRM_SPI3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 15), /*!< spi3 sleep mode periph clock */
+ CRM_USART2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 17), /*!< usart2 sleep mode periph clock */
+ CRM_USART3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 18), /*!< usart3 sleep mode periph clock */
+ CRM_USART4_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 19), /*!< usart4 sleep mode periph clock */
+ CRM_USART5_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 20), /*!< usart5 sleep mode periph clock */
+ CRM_I2C1_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 21), /*!< i2c1 sleep mode periph clock */
+ CRM_I2C2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 22), /*!< i2c2 sleep mode periph clock */
+ CRM_I2C3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 23), /*!< i2c3 sleep mode periph clock */
+ CRM_CAN1_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 25), /*!< can1 sleep mode periph clock */
+ CRM_CAN2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 26), /*!< can2 sleep mode periph clock */
+ CRM_CAN3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 27), /*!< can3 sleep mode periph clock */
+ CRM_PWC_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 28), /*!< pwc sleep mode periph clock */
+ CRM_DAC_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 29), /*!< dac sleep mode periph clock */
+ CRM_USART7_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 30), /*!< usart7 sleep mode periph clock */
+ CRM_USART8_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 31), /*!< usart8 sleep mode periph clock */
+ /* apb2 periph */
+ CRM_TMR1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 0), /*!< tmr1 sleep mode periph clock */
+ CRM_TMR8_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 1), /*!< tmr8 sleep mode periph clock */
+ CRM_USART1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 4), /*!< usart1 sleep mode periph clock */
+ CRM_USART6_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 5), /*!< usart6 sleep mode periph clock */
+ CRM_ADC2_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 9), /*!< adc2 sleep mode periph clock */
+ CRM_ADC1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 8), /*!< adc1 sleep mode periph clock */
+ CRM_SPI1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 12), /*!< spi1 sleep mode periph clock */
+ CRM_SPI4_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 13), /*!< spi4 sleep mode periph clock */
+ CRM_SCFG_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 14), /*!< scfg sleep mode periph clock */
+ CRM_TMR9_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 16), /*!< tmr9 sleep mode periph clock */
+ CRM_TMR10_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 17), /*!< tmr10 sleep mode periph clock */
+ CRM_TMR11_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 18), /*!< tmr11 sleep mode periph clock */
+ CRM_I2SF5_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 20), /*!< i2sf5 sleep mode periph clock */
+ CRM_ACC_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 29), /*!< acc sleep mode periph clock */
+ CRM_I2S2EXT_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 30), /*!< i2s2ext sleep mode periph clock */
+ CRM_I2S3EXT_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 31) /*!< i2s3ext sleep mode periph clock */
+
+} crm_periph_clock_lowpower_type;
+
+/**
+ * @brief crm pll clock source
+ */
+typedef enum
+{
+ CRM_PLL_SOURCE_HICK = 0x00, /*!< high speed internal clock as pll reference clock source */
+ CRM_PLL_SOURCE_HEXT = 0x01 /*!< high speed external crystal as pll reference clock source */
+} crm_pll_clock_source_type;
+
+/**
+ * @brief crm pll fu
+ */
+typedef enum
+{
+ CRM_PLL_FU_11 = 0x00, /*!< pll fu-division div11 */
+ CRM_PLL_FU_12 = 0x01, /*!< pll fu-division div12 */
+ CRM_PLL_FU_13 = 0x02, /*!< pll fu-division div13 */
+ CRM_PLL_FU_14 = 0x03, /*!< pll fu-division div14 */
+ CRM_PLL_FU_16 = 0x04, /*!< pll fu-division div16 */
+ CRM_PLL_FU_18 = 0x05, /*!< pll fu-division div18 */
+ CRM_PLL_FU_20 = 0x06 /*!< pll fu-division div20 */
+} crm_pll_fu_type;
+
+/**
+ * @brief crm pll fp
+ */
+typedef enum
+{
+ CRM_PLL_FP_1 = 0x00, /*!< pll fp-division div1 */
+ CRM_PLL_FP_2 = 0x01, /*!< pll fp-division div2 */
+ CRM_PLL_FP_4 = 0x02, /*!< pll fp-division div4 */
+ CRM_PLL_FP_6 = 0x03, /*!< pll fp-division div6 */
+ CRM_PLL_FP_8 = 0x04, /*!< pll fp-division div8 */
+ CRM_PLL_FP_10 = 0x05, /*!< pll fp-division div10 */
+ CRM_PLL_FP_12 = 0x06, /*!< pll fp-division div12 */
+ CRM_PLL_FP_14 = 0x07, /*!< pll fp-division div14 */
+ CRM_PLL_FP_16 = 0x08, /*!< pll fp-division div16 */
+ CRM_PLL_FP_18 = 0x09, /*!< pll fp-division div18 */
+ CRM_PLL_FP_20 = 0x0A, /*!< pll fp-division div20 */
+ CRM_PLL_FP_22 = 0x0B, /*!< pll fp-division div22 */
+ CRM_PLL_FP_24 = 0x0C, /*!< pll fp-division div24 */
+ CRM_PLL_FP_26 = 0x0D, /*!< pll fp-division div26 */
+ CRM_PLL_FP_28 = 0x0E, /*!< pll fp-division div28 */
+ CRM_PLL_FP_30 = 0x0F /*!< pll fp-division div30 */
+} crm_pll_fp_type;
+
+/**
+ * @brief crm clock source
+ */
+typedef enum
+{
+ CRM_CLOCK_SOURCE_HICK = 0x00, /*!< high speed internal clock */
+ CRM_CLOCK_SOURCE_HEXT = 0x01, /*!< high speed external crystal */
+ CRM_CLOCK_SOURCE_PLL = 0x02, /*!< phase locking loop */
+ CRM_CLOCK_SOURCE_LEXT = 0x03, /*!< low speed external crystal */
+ CRM_CLOCK_SOURCE_LICK = 0x04 /*!< low speed internal clock */
+} crm_clock_source_type;
+
+/**
+ * @brief crm ahb division
+ */
+typedef enum
+{
+ CRM_AHB_DIV_1 = 0x00, /*!< sclk div1 to ahbclk */
+ CRM_AHB_DIV_2 = 0x08, /*!< sclk div2 to ahbclk */
+ CRM_AHB_DIV_4 = 0x09, /*!< sclk div4 to ahbclk */
+ CRM_AHB_DIV_8 = 0x0A, /*!< sclk div8 to ahbclk */
+ CRM_AHB_DIV_16 = 0x0B, /*!< sclk div16 to ahbclk */
+ CRM_AHB_DIV_64 = 0x0C, /*!< sclk div64 to ahbclk */
+ CRM_AHB_DIV_128 = 0x0D, /*!< sclk div128 to ahbclk */
+ CRM_AHB_DIV_256 = 0x0E, /*!< sclk div256 to ahbclk */
+ CRM_AHB_DIV_512 = 0x0F /*!< sclk div512 to ahbclk */
+} crm_ahb_div_type;
+
+/**
+ * @brief crm apb1 division
+ */
+typedef enum
+{
+ CRM_APB1_DIV_1 = 0x00, /*!< ahbclk div1 to apb1clk */
+ CRM_APB1_DIV_2 = 0x04, /*!< ahbclk div2 to apb1clk */
+ CRM_APB1_DIV_4 = 0x05, /*!< ahbclk div4 to apb1clk */
+ CRM_APB1_DIV_8 = 0x06, /*!< ahbclk div8 to apb1clk */
+ CRM_APB1_DIV_16 = 0x07 /*!< ahbclk div16 to apb1clk */
+} crm_apb1_div_type;
+
+/**
+ * @brief crm apb2 division
+ */
+typedef enum
+{
+ CRM_APB2_DIV_1 = 0x00, /*!< ahbclk div1 to apb2clk */
+ CRM_APB2_DIV_2 = 0x04, /*!< ahbclk div2 to apb2clk */
+ CRM_APB2_DIV_4 = 0x05, /*!< ahbclk div4 to apb2clk */
+ CRM_APB2_DIV_8 = 0x06, /*!< ahbclk div8 to apb2clk */
+ CRM_APB2_DIV_16 = 0x07 /*!< ahbclk div16 to apb2clk */
+} crm_apb2_div_type;
+
+/**
+ * @brief crm apb3 division
+ */
+typedef enum
+{
+ CRM_APB3_DIV_1 = 0x00, /*!< ahbclk div1 to apb3clk */
+ CRM_APB3_DIV_2 = 0x04, /*!< ahbclk div2 to apb3clk */
+ CRM_APB3_DIV_4 = 0x05, /*!< ahbclk div4 to apb3clk */
+ CRM_APB3_DIV_8 = 0x06, /*!< ahbclk div8 to apb3clk */
+ CRM_APB3_DIV_16 = 0x07 /*!< ahbclk div16 to apb3clk */
+} crm_apb3_div_type;
+
+/**
+ * @brief crm vbat ahb division
+ */
+typedef enum
+{
+ CRM_VBATH_DIV_1 = 0x00, /*!< ahbclk div1 to vbatclk */
+ CRM_VBATH_DIV_2 = 0x02, /*!< ahbclk div2 to vbatclk */
+ CRM_VBATH_DIV_4 = 0x03 /*!< ahbclk div4 to vbatclk */
+} crm_vbath_div_type;
+
+/**
+ * @brief crm hext to sysclk division
+ */
+typedef enum
+{
+ CRM_HEXT_SCLK_DIV_1 = 0x00, /*!< hext div1 to sysclk */
+ CRM_HEXT_SCLK_DIV_2 = 0x01, /*!< hext div2 to sysclk */
+ CRM_HEXT_SCLK_DIV_4 = 0x02, /*!< hext div4 to sysclk */
+ CRM_HEXT_SCLK_DIV_8 = 0x03, /*!< hext div8 to sysclk */
+ CRM_HEXT_SCLK_DIV_16 = 0x04, /*!< hext div16 to sysclk */
+ CRM_HEXT_SCLK_DIV_32 = 0x05 /*!< hext div32 to sysclk */
+} crm_hext_sclk_div_type;
+
+/**
+ * @brief crm hick to sysclk division
+ */
+typedef enum
+{
+ CRM_HICK_SCLK_DIV_1 = 0x00, /*!< hick div1 to sysclk */
+ CRM_HICK_SCLK_DIV_2 = 0x01, /*!< hick div2 to sysclk */
+ CRM_HICK_SCLK_DIV_4 = 0x02, /*!< hick div4 to sysclk */
+ CRM_HICK_SCLK_DIV_8 = 0x03, /*!< hick div8 to sysclk */
+ CRM_HICK_SCLK_DIV_16 = 0x04 /*!< hick div16 to sysclk */
+} crm_hick_sclk_div_type;
+
+/**
+ * @brief crm ertc clock
+ */
+typedef enum
+{
+ CRM_ERTC_CLOCK_NOCLK = 0x000, /*!< no clock as ertc clock source */
+ CRM_ERTC_CLOCK_LEXT = 0x001, /*!< low speed external crystal as ertc clock source */
+ CRM_ERTC_CLOCK_LICK = 0x002, /*!< low speed internal clock as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_2 = 0x023, /*!< high speed external crystal div2 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_3 = 0x033, /*!< high speed external crystal div3 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_4 = 0x043, /*!< high speed external crystal div4 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_5 = 0x053, /*!< high speed external crystal div5 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_6 = 0x063, /*!< high speed external crystal div6 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_7 = 0x073, /*!< high speed external crystal div7 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_8 = 0x083, /*!< high speed external crystal div8 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_9 = 0x093, /*!< high speed external crystal div9 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_10 = 0x0A3, /*!< high speed external crystal div10 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_11 = 0x0B3, /*!< high speed external crystal div11 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_12 = 0x0C3, /*!< high speed external crystal div12 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_13 = 0x0D3, /*!< high speed external crystal div13 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_14 = 0x0E3, /*!< high speed external crystal div14 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_15 = 0x0F3, /*!< high speed external crystal div15 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_16 = 0x103, /*!< high speed external crystal div16 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_17 = 0x113, /*!< high speed external crystal div17 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_18 = 0x123, /*!< high speed external crystal div18 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_19 = 0x133, /*!< high speed external crystal div19 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_20 = 0x143, /*!< high speed external crystal div20 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_21 = 0x153, /*!< high speed external crystal div21 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_22 = 0x163, /*!< high speed external crystal div22 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_23 = 0x173, /*!< high speed external crystal div23 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_24 = 0x183, /*!< high speed external crystal div24 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_25 = 0x193, /*!< high speed external crystal div25 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_26 = 0x1A3, /*!< high speed external crystal div26 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_27 = 0x1B3, /*!< high speed external crystal div27 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_28 = 0x1C3, /*!< high speed external crystal div28 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_29 = 0x1D3, /*!< high speed external crystal div29 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_30 = 0x1E3, /*!< high speed external crystal div30 as ertc clock source */
+ CRM_ERTC_CLOCK_HEXT_DIV_31 = 0x1F3 /*!< high speed external crystal div31 as ertc clock source */
+} crm_ertc_clock_type;
+
+/**
+ * @brief crm sclk select
+ */
+typedef enum
+{
+ CRM_SCLK_HICK = 0x00, /*!< select high speed internal clock as sclk */
+ CRM_SCLK_HEXT = 0x01, /*!< select high speed external crystal as sclk */
+ CRM_SCLK_PLL = 0x02 /*!< select phase locking loop clock as sclk */
+} crm_sclk_type;
+
+/**
+ * @brief crm clkout select
+ */
+typedef enum
+{
+ CRM_CLKOUT_SCLK = 0x00, /*!< output system clock to clkout pin */
+ CRM_CLKOUT_HEXT = 0x02, /*!< output high speed external crystal to clkout pin */
+ CRM_CLKOUT_PLL = 0x03, /*!< output phase locking loop P clock to clkout pin */
+ CRM_CLKOUT_USB = 0x10, /*!< output usbclk to clkout pin */
+ CRM_CLKOUT_ADC = 0x11, /*!< output adcclk to clkout pin */
+ CRM_CLKOUT_HICK = 0x12, /*!< output high speed internal clock to clkout pin */
+ CRM_CLKOUT_LICK = 0x13, /*!< output low speed internal clock to clkout pin */
+ CRM_CLKOUT_LEXT = 0x14 /*!< output low speed external crystal to clkout pin */
+} crm_clkout_select_type;
+
+/**
+ * @brief crm clkout division1
+ */
+typedef enum
+{
+ CRM_CLKOUT_DIV1_1 = 0x00, /*!< clkout division1 div1 */
+ CRM_CLKOUT_DIV1_2 = 0x04, /*!< clkout division1 div2 */
+ CRM_CLKOUT_DIV1_3 = 0x05, /*!< clkout division1 div3 */
+ CRM_CLKOUT_DIV1_4 = 0x06, /*!< clkout division1 div4 */
+ CRM_CLKOUT_DIV1_5 = 0x07 /*!< clkout division1 div5 */
+} crm_clkout_div1_type;
+
+/**
+ * @brief crm clkout division2
+ */
+typedef enum
+{
+ CRM_CLKOUT_DIV2_1 = 0x00, /*!< clkout division2 div1 */
+ CRM_CLKOUT_DIV2_2 = 0x08, /*!< clkout division2 div2 */
+ CRM_CLKOUT_DIV2_4 = 0x09, /*!< clkout division2 div4 */
+ CRM_CLKOUT_DIV2_8 = 0x0A, /*!< clkout division2 div8 */
+ CRM_CLKOUT_DIV2_16 = 0x0B, /*!< clkout division2 div16 */
+ CRM_CLKOUT_DIV2_64 = 0x0C, /*!< clkout division2 div64 */
+ CRM_CLKOUT_DIV2_128 = 0x0D, /*!< clkout division2 div128 */
+ CRM_CLKOUT_DIV2_256 = 0x0E, /*!< clkout division2 div256 */
+ CRM_CLKOUT_DIV2_512 = 0x0F /*!< clkout division2 div512 */
+} crm_clkout_div2_type;
+
+/**
+ * @brief crm auto step mode
+ */
+typedef enum
+{
+ CRM_AUTO_STEP_MODE_DISABLE = 0x00, /*!< disable auto step mode */
+ CRM_AUTO_STEP_MODE_ENABLE = 0x03 /*!< enable auto step mode */
+} crm_auto_step_mode_type;
+
+/**
+ * @brief crm can index
+ */
+typedef enum
+{
+ CRM_CAN1 = 0x00, /*!< can1 */
+ CRM_CAN2 = 0x01, /*!< can2 */
+ CRM_CAN3 = 0x02 /*!< can3 */
+} crm_can_type;
+
+/**
+ * @brief crm usart clock source
+ */
+typedef enum
+{
+ CRM_CAN_CLOCK_SOURCE_HEXT = 0x00, /*!< select hext clock as can clock source */
+ CRM_CAN_CLOCK_SOURCE_PLLU = 0x01, /*!< select pllu clock as can clock source */
+ CRM_CAN_CLOCK_SOURCE_PCLK = 0x02 /*!< select high speed external clock as can clock source */
+} crm_can_clock_source_type;
+
+/**
+ * @brief crm i2sf5 clock source select
+ */
+typedef enum
+{
+ CRM_I2SF5_CLOCK_SOURCE_SCLK = 0x00, /*!< select system clock clock as i2sf5 clock source */
+ CRM_I2SF5_CLOCK_SOURCE_PLLP = 0x01, /*!< select phase locking loop clock as i2sf5 clock source */
+ CRM_I2SF5_CLOCK_SOURCE_HICK = 0x02, /*!< select high speed internal clock as i2sf5 clock source */
+ CRM_I2SF5_CLOCK_SOURCE_EXTERNAL = 0x03 /*!< select external clock as i2sf5 clock source */
+} crm_i2sf5_clock_source_type;
+/**
+ * @brief crm usb 48 mhz clock source select
+ */
+typedef enum
+{
+ CRM_USB_CLOCK_SOURCE_PLLU = 0x00, /*!< select phase locking loop clock as usb clock source */
+ CRM_USB_CLOCK_SOURCE_HICK = 0x01 /*!< select high speed internal clock as usb clock source */
+} crm_usb_clock_source_type;
+
+/**
+ * @brief crm hick as system clock frequency select
+ */
+typedef enum
+{
+ CRM_HICK_SCLK_8MHZ = 0x00, /*!< fixed 8 mhz when hick is selected as sclk */
+ CRM_HICK_SCLK_48MHZ = 0x01 /*!< 8 mhz or 48 mhz depend on hickdiv when hick is selected as sclk */
+} crm_hick_sclk_frequency_type;
+
+/**
+ * @brief crm external crystal driving strength
+ */
+typedef enum
+{
+ CRM_DRV_STRENGTH_LOW = 0x00, /*!< driving strength low */
+ CRM_DRV_STRENGTH_MEDIUM_LOW = 0x01, /*!< driving strength medium low */
+ CRM_DRV_STRENGTH_MEDIUM_HIGH = 0x02, /*!< driving strength medium high */
+ CRM_DRV_STRENGTH_HIGH = 0x03 /*!< driving strength high */
+} crm_drv_strength_type;
+
+/**
+ * @brief crm emac output pulse width
+ */
+typedef enum
+{
+ CRM_EMAC_PULSE_125MS = 0x00, /*!< emac output pulse width 125ms */
+ CRM_EMAC_PULSE_1SCLK = 0x01 /*!< emac output pulse width 1 system clock */
+} crm_emac_output_pulse_type;
+
+/**
+ * @brief crm clocks freqency structure
+ */
+typedef struct
+{
+ uint32_t sclk_freq; /*!< system clock frequency */
+ uint32_t ahb_freq; /*!< ahb bus clock frequency */
+ uint32_t apb2_freq; /*!< apb2 bus clock frequency */
+ uint32_t apb1_freq; /*!< apb1 bus clock frequency */
+} crm_clocks_freq_type;
+
+/**
+ * @brief type define crm register all
+ */
+typedef struct
+{
+ /**
+ * @brief crm ctrl register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t ctrl;
+ struct
+ {
+ __IO uint32_t hicken : 1; /* [0] */
+ __IO uint32_t hickstbl : 1; /* [1] */
+ __IO uint32_t hicktrim : 6; /* [7:2] */
+ __IO uint32_t hickcal : 8; /* [15:8] */
+ __IO uint32_t hexten : 1; /* [16] */
+ __IO uint32_t hextstbl : 1; /* [17] */
+ __IO uint32_t hextbyps : 1; /* [18] */
+ __IO uint32_t cfden : 1; /* [19] */
+ __IO uint32_t reserved1 : 4; /* [23:20] */
+ __IO uint32_t pllen : 1; /* [24] */
+ __IO uint32_t pllstbl : 1; /* [25] */
+ __IO uint32_t pllustbl : 1; /* [26] */
+ __IO uint32_t reserved2 : 5; /* [31:27] */
+ } ctrl_bit;
+ };
+
+ /**
+ * @brief crm pllcfg register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t pllcfg;
+ struct
+ {
+ __IO uint32_t pllms : 4; /* [3:0] */
+ __IO uint32_t reserved1 : 2; /* [5:4] */
+ __IO uint32_t pllns : 9; /* [14:6] */
+ __IO uint32_t reserved2 : 1; /* [15] */
+ __IO uint32_t pllfp : 4; /* [19:16] */
+ __IO uint32_t pllfu : 3; /* [22:20] */
+ __IO uint32_t reserved3 : 6; /* [28:23] */
+ __IO uint32_t plluen : 1; /* [29] */
+ __IO uint32_t pllrcs : 1; /* [30] */
+ __IO uint32_t reserved4 : 1; /* [31] */
+ } pllcfg_bit;
+ };
+
+ /**
+ * @brief crm cfg register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t cfg;
+ struct
+ {
+ __IO uint32_t sclksel : 2; /* [1:0] */
+ __IO uint32_t sclksts : 2; /* [3:2] */
+ __IO uint32_t ahbdiv : 4; /* [7:4] */
+ __IO uint32_t reserved1 : 2; /* [9:8] */
+ __IO uint32_t apb1div : 3; /* [12:10] */
+ __IO uint32_t apb2div : 3; /* [15:13] */
+ __IO uint32_t ertcdiv : 5; /* [20:16] */
+ __IO uint32_t reserved2 : 1; /* [21] */
+ __IO uint32_t i2sf5clksel : 2; /* [23:22] */
+ __IO uint32_t reserved3 : 3; /* [26:24] */
+ __IO uint32_t clkoutdiv1 : 3; /* [29:27] */
+ __IO uint32_t clkout_sel1 : 2; /* [31:30] */
+ } cfg_bit;
+ };
+
+ /**
+ * @brief crm clkint register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t clkint;
+ struct
+ {
+ __IO uint32_t lickstblf : 1; /* [0] */
+ __IO uint32_t lextstblf : 1; /* [1] */
+ __IO uint32_t hickstblf : 1; /* [2] */
+ __IO uint32_t hextstblf : 1; /* [3] */
+ __IO uint32_t pllstblf : 1; /* [4] */
+ __IO uint32_t reserved1 : 2; /* [6:5] */
+ __IO uint32_t cfdf : 1; /* [7] */
+ __IO uint32_t lickstblien : 1; /* [8] */
+ __IO uint32_t lextstblien : 1; /* [9] */
+ __IO uint32_t hickstblien : 1; /* [10] */
+ __IO uint32_t hextstblien : 1; /* [11] */
+ __IO uint32_t pllstblien : 1; /* [12] */
+ __IO uint32_t reserved2 : 3; /* [15:13] */
+ __IO uint32_t lickstblfc : 1; /* [16] */
+ __IO uint32_t lextstblfc : 1; /* [17] */
+ __IO uint32_t hickstblfc : 1; /* [18] */
+ __IO uint32_t hextstblfc : 1; /* [19] */
+ __IO uint32_t pllstblfc : 1; /* [20] */
+ __IO uint32_t reserved3 : 2; /* [22:21] */
+ __IO uint32_t cfdfc : 1; /* [23] */
+ __IO uint32_t reserved4 : 8; /* [31:24] */
+ } clkint_bit;
+ };
+
+ /**
+ * @brief crm ahbrst1 register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t ahbrst1;
+ struct
+ {
+ __IO uint32_t gpioarst : 1; /* [0] */
+ __IO uint32_t gpiobrst : 1; /* [1] */
+ __IO uint32_t gpiocrst : 1; /* [2] */
+ __IO uint32_t gpiodrst : 1; /* [3] */
+ __IO uint32_t gpioerst : 1; /* [4] */
+ __IO uint32_t gpiofrst : 1; /* [5] */
+ __IO uint32_t gpiogrst : 1; /* [6] */
+ __IO uint32_t gpiohrst : 1; /* [7] */
+ __IO uint32_t reserved2 : 4; /* [11:8] */
+ __IO uint32_t crcrst : 1; /* [12] */
+ __IO uint32_t reserved3 : 9; /* [21:13] */
+ __IO uint32_t dma1rst : 1; /* [22] */
+ __IO uint32_t reserved4 : 1; /* [23] */
+ __IO uint32_t dma2rst : 1; /* [24] */
+ __IO uint32_t emacrst : 1; /* [25] */
+ __IO uint32_t reserved5 : 6; /* [31:26] */
+ } ahbrst1_bit;
+ };
+
+ /**
+ * @brief crm ahbrst2 register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t ahbrst2;
+ struct
+ {
+ __IO uint32_t reserved1 : 4; /* [3:0] */
+ __IO uint32_t aesrst : 1; /* [4] */
+ __IO uint32_t reserved2 : 1; /* [5] */
+ __IO uint32_t trngrst : 1; /* [6] */
+ __IO uint32_t otgfs1rst : 1; /* [7] */
+ __IO uint32_t reserved3 : 7; /* [14:8] */
+ __IO uint32_t sdio1rst : 1; /* [15] */
+ __IO uint32_t reserved4 : 16;/* [31:16] */
+ } ahbrst2_bit;
+ };
+
+ /**
+ * @brief crm ahbrst3 register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t ahbrst3;
+ struct
+ {
+ __IO uint32_t xmcrst : 1; /* [0] */
+ __IO uint32_t reserved1 : 31;/* [31:1] */
+ } ahbrst3_bit;
+ };
+
+ /**
+ * @brief crm reserved1 register, offset:0x14 ~ 0x1C
+ */
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief crm apb1rst register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t apb1rst;
+ struct
+ {
+ __IO uint32_t tmr2rst : 1; /* [0] */
+ __IO uint32_t tmr3rst : 1; /* [1] */
+ __IO uint32_t tmr4rst : 1; /* [2] */
+ __IO uint32_t tmr5rst : 1; /* [3] */
+ __IO uint32_t tmr6rst : 1; /* [4] */
+ __IO uint32_t tmr7rst : 1; /* [5] */
+ __IO uint32_t tmr12rst : 1; /* [6] */
+ __IO uint32_t tmr13rst : 1; /* [7] */
+ __IO uint32_t adc14rst : 1; /* [8] */
+ __IO uint32_t reserved3 : 2; /* [10:9] */
+ __IO uint32_t wwdtrst : 1; /* [11] */
+ __IO uint32_t reserved4 : 2; /* [13:12] */
+ __IO uint32_t spi2rst : 1; /* [14] */
+ __IO uint32_t spi3rst : 1; /* [15] */
+ __IO uint32_t reserved5 : 1; /* [16] */
+ __IO uint32_t usart2rst : 1; /* [17] */
+ __IO uint32_t usart3rst : 1; /* [18] */
+ __IO uint32_t usart4rst : 1; /* [19] */
+ __IO uint32_t usart5rst : 1; /* [20] */
+ __IO uint32_t i2c1rst : 1; /* [21] */
+ __IO uint32_t i2c2rst : 1; /* [22] */
+ __IO uint32_t i2c3rst : 1; /* [23] */
+ __IO uint32_t reserved6 : 1; /* [24] */
+ __IO uint32_t can1rst : 1; /* [25] */
+ __IO uint32_t can2rst : 1; /* [26] */
+ __IO uint32_t can3rst : 1; /* [27] */
+ __IO uint32_t pwcrst : 1; /* [28] */
+ __IO uint32_t dacrst : 1; /* [29] */
+ __IO uint32_t usart7rst : 1; /* [30] */
+ __IO uint32_t usart8rst : 1; /* [31] */
+ } apb1rst_bit;
+ };
+
+ /**
+ * @brief crm apb2rst register, offset:0x24
+ */
+ union
+ {
+ __IO uint32_t apb2rst;
+ struct
+ {
+ __IO uint32_t tmr1rst : 1; /* [0] */
+ __IO uint32_t tmr8rst : 1; /* [1] */
+ __IO uint32_t reserved1 : 2; /* [3:2] */
+ __IO uint32_t usart1rst : 1; /* [4] */
+ __IO uint32_t usart6rst : 1; /* [5] */
+ __IO uint32_t reserved2 : 2; /* [7:6] */
+ __IO uint32_t adcrst : 1; /* [8] */
+ __IO uint32_t reserved3 : 3; /* [11:9] */
+ __IO uint32_t spi1rst : 1; /* [12] */
+ __IO uint32_t spi4rst : 1; /* [13] */
+ __IO uint32_t scfgrst : 1; /* [14] */
+ __IO uint32_t reserved4 : 1; /* [15] */
+ __IO uint32_t tmr9rst : 1; /* [16] */
+ __IO uint32_t tmr10rst : 1; /* [17] */
+ __IO uint32_t tmr11rst : 1; /* [18] */
+ __IO uint32_t reserved5 : 1; /* [19] */
+ __IO uint32_t i2sf5rst : 1; /* [20] */
+ __IO uint32_t reserved6 : 8; /* [28:21] */
+ __IO uint32_t accrst : 1; /* [29] */
+ __IO uint32_t i2s2extrst : 1; /* [30] */
+ __IO uint32_t i2s3extrst : 1; /* [31] */
+ } apb2rst_bit;
+ };
+
+ /**
+ * @brief crm reserved2 register, offset:0x28~0x2C
+ */
+ __IO uint32_t reserved2[2];
+
+ /**
+ * @brief crm ahben1 register, offset:0x30
+ */
+ union
+ {
+ __IO uint32_t ahben1;
+ struct
+ {
+ __IO uint32_t gpioaen : 1; /* [0] */
+ __IO uint32_t gpioben : 1; /* [1] */
+ __IO uint32_t gpiocen : 1; /* [2] */
+ __IO uint32_t gpioden : 1; /* [3] */
+ __IO uint32_t gpioeen : 1; /* [4] */
+ __IO uint32_t gpiofen : 1; /* [5] */
+ __IO uint32_t gpiogen : 1; /* [6] */
+ __IO uint32_t gpiohen : 1; /* [7] */
+ __IO uint32_t reserved2 : 4; /* [11:8] */
+ __IO uint32_t crcen : 1; /* [12] */
+ __IO uint32_t reserved3 : 9; /* [21:13] */
+ __IO uint32_t dma1en : 1; /* [22] */
+ __IO uint32_t reserved4 : 1; /* [23] */
+ __IO uint32_t dma2en : 1; /* [24] */
+ __IO uint32_t emacen : 1; /* [25] */
+ __IO uint32_t emactxen : 1; /* [26] */
+ __IO uint32_t emacrxen : 1; /* [27] */
+ __IO uint32_t emacptpen : 1; /* [28] */
+ __IO uint32_t reserved6 : 3; /* [31:29] */
+ } ahben1_bit;
+ };
+
+ /**
+ * @brief crm ahben2 register, offset:0x34
+ */
+ union
+ {
+ __IO uint32_t ahben2;
+ struct
+ {
+ __IO uint32_t reserved1 : 4; /* [3:0] */
+ __IO uint32_t aesen : 1; /* [4] */
+ __IO uint32_t reserved2 : 1; /* [5] */
+ __IO uint32_t trngen : 1; /* [6] */
+ __IO uint32_t otgfs1en : 1; /* [7] */
+ __IO uint32_t reserved3 : 7; /* [14:8] */
+ __IO uint32_t sdio1en : 1; /* [15] */
+ __IO uint32_t reserved4 : 16;/* [31:16] */
+ } ahben2_bit;
+ };
+
+ /**
+ * @brief crm ahben3 register, offset:0x38
+ */
+ union
+ {
+ __IO uint32_t ahben3;
+ struct
+ {
+ __IO uint32_t xmcen : 1; /* [1] */
+ __IO uint32_t reserved2 : 31;/* [31:1] */
+ } ahben3_bit;
+ };
+
+ /**
+ * @brief crm reserved3 register, offset:0x3C
+ */
+ __IO uint32_t reserved3;
+
+ /**
+ * @brief crm apb1en register, offset:0x40
+ */
+ union
+ {
+ __IO uint32_t apb1en;
+ struct
+ {
+ __IO uint32_t tmr2en : 1; /* [0] */
+ __IO uint32_t tmr3en : 1; /* [1] */
+ __IO uint32_t tmr4en : 1; /* [2] */
+ __IO uint32_t tmr5en : 1; /* [3] */
+ __IO uint32_t tmr6en : 1; /* [4] */
+ __IO uint32_t tmr7en : 1; /* [5] */
+ __IO uint32_t tmr12en : 1; /* [6] */
+ __IO uint32_t tmr13en : 1; /* [7] */
+ __IO uint32_t tmr14en : 1; /* [8] */
+ __IO uint32_t reserved3 : 2; /* [10:9] */
+ __IO uint32_t wwdten : 1; /* [11] */
+ __IO uint32_t reserved4 : 2; /* [13:12] */
+ __IO uint32_t spi2en : 1; /* [14] */
+ __IO uint32_t spi3en : 1; /* [15] */
+ __IO uint32_t reserved5 : 1; /* [16] */
+ __IO uint32_t usart2en : 1; /* [17] */
+ __IO uint32_t usart3en : 1; /* [18] */
+ __IO uint32_t usart4en : 1; /* [19] */
+ __IO uint32_t usart5en : 1; /* [20] */
+ __IO uint32_t i2c1en : 1; /* [21] */
+ __IO uint32_t i2c2en : 1; /* [22] */
+ __IO uint32_t i2c3en : 1; /* [23] */
+ __IO uint32_t reserved6 : 1; /* [24] */
+ __IO uint32_t can1en : 1; /* [25] */
+ __IO uint32_t can2en : 1; /* [26] */
+ __IO uint32_t can3en : 1; /* [27] */
+ __IO uint32_t pwcen : 1; /* [28] */
+ __IO uint32_t dacen : 1; /* [29] */
+ __IO uint32_t usart7en : 1; /* [30] */
+ __IO uint32_t usart8en : 1; /* [31] */
+ } apb1en_bit;
+ };
+
+ /**
+ * @brief crm apb2en register, offset:0x44
+ */
+ union
+ {
+ __IO uint32_t apb2en;
+ struct
+ {
+ __IO uint32_t tmr1en : 1; /* [0] */
+ __IO uint32_t tmr8en : 1; /* [1] */
+ __IO uint32_t reserved1 : 2; /* [3:2] */
+ __IO uint32_t usart1en : 1; /* [4] */
+ __IO uint32_t usart6en : 1; /* [5] */
+ __IO uint32_t reserved2 : 2; /* [7:6] */
+ __IO uint32_t adc1en : 1; /* [8] */
+ __IO uint32_t reserved3 : 3; /* [11:9] */
+ __IO uint32_t spi1en : 1; /* [12] */
+ __IO uint32_t spi4en : 1; /* [13] */
+ __IO uint32_t scfgen : 1; /* [14] */
+ __IO uint32_t reserved5 : 1; /* [15] */
+ __IO uint32_t tmr9en : 1; /* [16] */
+ __IO uint32_t tmr10en : 1; /* [17] */
+ __IO uint32_t tmr11en : 1; /* [18] */
+ __IO uint32_t reserved6 : 1; /* [19] */
+ __IO uint32_t i2sf5en : 1; /* [20] */
+ __IO uint32_t reserved7 : 8; /* [28:21] */
+ __IO uint32_t accen : 1; /* [29] */
+ __IO uint32_t i2s2exten : 1; /* [30] */
+ __IO uint32_t i2s3exten : 1; /* [31] */
+ } apb2en_bit;
+ };
+
+ /**
+ * @brief crm reserved4 register, offset:0x48~0x4C
+ */
+ __IO uint32_t reserved4[2];
+
+ /**
+ * @brief crm ahblpen1 register, offset:0x50
+ */
+ union
+ {
+ __IO uint32_t ahblpen1;
+ struct
+ {
+ __IO uint32_t gpioalpen : 1; /* [0] */
+ __IO uint32_t gpioblpen : 1; /* [1] */
+ __IO uint32_t gpioclpen : 1; /* [2] */
+ __IO uint32_t gpiodlpen : 1; /* [3] */
+ __IO uint32_t gpioelpen : 1; /* [4] */
+ __IO uint32_t gpioflpen : 1; /* [5] */
+ __IO uint32_t gpioglpen : 1; /* [6] */
+ __IO uint32_t gpiohlpen : 1; /* [7] */
+ __IO uint32_t reserved2 : 4; /* [11:8] */
+ __IO uint32_t crclpen : 1; /* [12] */
+ __IO uint32_t reserved3 : 2; /* [14:13] */
+ __IO uint32_t flashlpen : 1; /* [15] */
+ __IO uint32_t sramlpen : 1; /* [16] */
+ __IO uint32_t reserved4 : 5; /* [21:17] */
+ __IO uint32_t dma1lpen : 1; /* [22] */
+ __IO uint32_t reserved5 : 1; /* [23] */
+ __IO uint32_t dma2lpen : 1; /* [24] */
+ __IO uint32_t emaclpen : 1; /* [25] */
+ __IO uint32_t emactxlpen : 1; /* [26] */
+ __IO uint32_t emacrtlpen : 1; /* [27] */
+ __IO uint32_t emacptplpen : 1; /* [28] */
+ __IO uint32_t reserved6 : 3; /* [31:29] */
+ } ahblpen1_bit;
+ };
+
+ /**
+ * @brief crm ahblpen2 register, offset:0x54
+ */
+ union
+ {
+ __IO uint32_t ahblpen2;
+ struct
+ {
+ __IO uint32_t reserved1 : 4; /* [3:0] */
+ __IO uint32_t aeslpen : 1; /* [4] */
+ __IO uint32_t reserved2 : 1; /* [5] */
+ __IO uint32_t trnglpen : 1; /* [6] */
+ __IO uint32_t otgfs1lpen : 1; /* [7] */
+ __IO uint32_t reserved3 : 7; /* [14:7] */
+ __IO uint32_t sdio1lpen : 1; /* [15] */
+ __IO uint32_t reserved4 : 16;/* [31:16] */
+ } ahblpen2_bit;
+ };
+
+ /**
+ * @brief crm ahblpen3 register, offset:0x58
+ */
+ union
+ {
+ __IO uint32_t ahblpen3;
+ struct
+ {
+ __IO uint32_t xmclpen : 1; /* [0] */
+ __IO uint32_t qspilpen : 1; /* [1] */
+ __IO uint32_t reserved1 : 30;/* [31:2] */
+ } ahblpen3_bit;
+ };
+
+ /**
+ * @brief crm reserved5 register, offset:0x5C
+ */
+ __IO uint32_t reserved5;
+
+ /**
+ * @brief crm apb1lpen register, offset:0x60
+ */
+ union
+ {
+ __IO uint32_t apb1lpen;
+ struct
+ {
+ __IO uint32_t tmr2lpen : 1; /* [0] */
+ __IO uint32_t tmr3lpen : 1; /* [1] */
+ __IO uint32_t tmr4lpen : 1; /* [2] */
+ __IO uint32_t tmr5lpen : 1; /* [3] */
+ __IO uint32_t tmr6lpen : 1; /* [4] */
+ __IO uint32_t tmr7lpen : 1; /* [5] */
+ __IO uint32_t tmr12lpen : 1; /* [6] */
+ __IO uint32_t tmr13lpen : 1; /* [7] */
+ __IO uint32_t adc14lpen : 1; /* [8] */
+ __IO uint32_t reserved3 : 2; /* [10:9] */
+ __IO uint32_t wwdtlpen : 1; /* [11] */
+ __IO uint32_t reserved4 : 2; /* [13:12] */
+ __IO uint32_t spi2lpen : 1; /* [14] */
+ __IO uint32_t spi3lpen : 1; /* [15] */
+ __IO uint32_t reserved5 : 1; /* [16] */
+ __IO uint32_t usart2lpen : 1; /* [17] */
+ __IO uint32_t usart3lpen : 1; /* [18] */
+ __IO uint32_t usart4lpen : 1; /* [19] */
+ __IO uint32_t usart5lpen : 1; /* [20] */
+ __IO uint32_t i2c1lpen : 1; /* [21] */
+ __IO uint32_t i2c2lpen : 1; /* [22] */
+ __IO uint32_t i2c3lpen : 1; /* [23] */
+ __IO uint32_t reserved6 : 1; /* [24] */
+ __IO uint32_t can1lpen : 1; /* [25] */
+ __IO uint32_t can2lpen : 1; /* [26] */
+ __IO uint32_t can3lpen : 1; /* [27] */
+ __IO uint32_t pwclpen : 1; /* [28] */
+ __IO uint32_t daclpen : 1; /* [29] */
+ __IO uint32_t usart7lpen : 1; /* [30] */
+ __IO uint32_t usart8lpen : 1; /* [31] */
+ } apb1lpen_bit;
+ };
+
+ /**
+ * @brief crm apb2lpen register, offset:0x64
+ */
+ union
+ {
+ __IO uint32_t apb2lpen;
+ struct
+ {
+ __IO uint32_t tmr1lpen : 1; /* [0] */
+ __IO uint32_t tmr8lpen : 1; /* [1] */
+ __IO uint32_t reserved1 : 2; /* [3:2] */
+ __IO uint32_t usart1lpen : 1; /* [4] */
+ __IO uint32_t usart6lpen : 1; /* [5] */
+ __IO uint32_t reserved2 : 2; /* [7:6] */
+ __IO uint32_t adclpen : 1; /* [8] */
+ __IO uint32_t reserved3 : 3; /* [11:9] */
+ __IO uint32_t spi1lpen : 1; /* [12] */
+ __IO uint32_t spi4lpen : 1; /* [13] */
+ __IO uint32_t scfglpen : 1; /* [14] */
+ __IO uint32_t reserved4 : 1; /* [15] */
+ __IO uint32_t tmr9lpen : 1; /* [16] */
+ __IO uint32_t tmr10lpen : 1; /* [17] */
+ __IO uint32_t tmr11lpen : 1; /* [18] */
+ __IO uint32_t reserved5 : 1; /* [19] */
+ __IO uint32_t i2sf5lpen : 1; /* [20] */
+ __IO uint32_t reserved6 : 8; /* [28:21] */
+ __IO uint32_t acclpen : 1; /* [29] */
+ __IO uint32_t i2s2extlpen : 1; /* [30] */
+ __IO uint32_t i2s3extlpen : 1; /* [31] */
+ } apb2lpen_bit;
+ };
+
+ /**
+ * @brief crm piclk register, offset:0x68
+ */
+ union
+ {
+ __IO uint32_t piclks;
+ struct
+ {
+ __IO uint32_t reserved1 : 24;/* [23:0] */
+ __IO uint32_t can1_clksel : 2; /* [25:24] */
+ __IO uint32_t can2_clksel : 2; /* [27:26] */
+ __IO uint32_t can3_clksel : 2; /* [29:28] */
+ __IO uint32_t reserved2 : 2; /* [31:30] */
+ } piclks_bit;
+ };
+
+ /**
+ * @brief crm reserved6 register, offset:0x6C
+ */
+ __IO uint32_t reserved6;
+
+ /**
+ * @brief crm bpdc register, offset:0x70
+ */
+ union
+ {
+ __IO uint32_t bpdc;
+ struct
+ {
+ __IO uint32_t lexten : 1; /* [0] */
+ __IO uint32_t lextstbl : 1; /* [1] */
+ __IO uint32_t lextbyps : 1; /* [2] */
+ __IO uint32_t lextdrv : 2; /* [4:3] */
+ __IO uint32_t reserved1 : 3; /* [7:5] */
+ __IO uint32_t ertcsel : 2; /* [9:8] */
+ __IO uint32_t reserved2 : 5; /* [14:10] */
+ __IO uint32_t ertcen : 1; /* [15] */
+ __IO uint32_t bpdrst : 1; /* [16] */
+ __IO uint32_t reserved3 : 15;/* [31:17] */
+ } bpdc_bit;
+ };
+
+ /**
+ * @brief crm ctrlsts register, offset:0x74
+ */
+ union
+ {
+ __IO uint32_t ctrlsts;
+ struct
+ {
+ __IO uint32_t licken : 1; /* [0] */
+ __IO uint32_t lickstbl : 1; /* [1] */
+ __IO uint32_t reserved1 : 22;/* [23:2] */
+ __IO uint32_t rstfc : 1; /* [24] */
+ __IO uint32_t reserved2 : 1; /* [25] */
+ __IO uint32_t nrstf : 1; /* [26] */
+ __IO uint32_t porrstf : 1; /* [27] */
+ __IO uint32_t swrstf : 1; /* [28] */
+ __IO uint32_t wdtrstf : 1; /* [29] */
+ __IO uint32_t wwdtrstf : 1; /* [30] */
+ __IO uint32_t lprstf : 1; /* [31] */
+ } ctrlsts_bit;
+ };
+
+ /**
+ * @brief crm reserved7 register, offset:0x78~0x9C
+ */
+ __IO uint32_t reserved7[10];
+
+ /**
+ * @brief crm misc1 register, offset:0xA0
+ */
+ union
+ {
+ __IO uint32_t misc1;
+ struct
+ {
+ __IO uint32_t hickcal_key : 8; /* [7:0] */
+ __IO uint32_t reserved1 : 6; /* [13:8] */
+ __IO uint32_t hick_to_sclk : 1; /* [14] */
+ __IO uint32_t reserved2 : 1; /* [15] */
+ __IO uint32_t clkout_sel2 : 4; /* [19:16] */
+ __IO uint32_t reserved3 : 8; /* [27:20] */
+ __IO uint32_t clkoutdiv2 : 4; /* [31:28] */
+ } misc1_bit;
+ };
+
+ /**
+ * @brief crm misc2 register, offset:0xA4
+ */
+ union
+ {
+ __IO uint32_t misc2;
+ struct
+ {
+ __IO uint32_t reserved1 : 4; /* [3:0] */
+ __IO uint32_t auto_step_en : 2; /* [5:4] */
+ __IO uint32_t reserved2 : 3; /* [8:6] */
+ __IO uint32_t emac_pps_sel : 1; /* [9] */
+ __IO uint32_t pllu_usb48_sel : 1; /* [10] */
+ __IO uint32_t reserved3 : 1; /* [11] */
+ __IO uint32_t apb3div : 3; /* [14:12] */
+ __IO uint32_t reserved4 : 1; /* [15] */
+ __IO uint32_t hick_to_sclk_div : 3; /* [18:16] */
+ __IO uint32_t hext_to_sclk_div : 3; /* [21:19] */
+ __IO uint32_t hextdrv : 2; /* [23:22] */
+ __IO uint32_t vbathdiv : 2; /* [25:24] */
+ __IO uint32_t reserved5 : 6; /* [31:26] */
+ } misc2_bit;
+ };
+
+} crm_type;
+
+/**
+ * @}
+ */
+
+#define CRM ((crm_type *) CRM_BASE)
+
+/** @defgroup CRM_exported_functions
+ * @{
+ */
+
+void crm_reset(void);
+void crm_lext_bypass(confirm_state new_state);
+void crm_hext_bypass(confirm_state new_state);
+flag_status crm_flag_get(uint32_t flag);
+error_status crm_hext_stable_wait(void);
+void crm_hick_clock_trimming_set(uint8_t trim_value);
+void crm_hick_clock_calibration_set(uint8_t cali_value);
+void crm_periph_clock_enable(crm_periph_clock_type value, confirm_state new_state);
+void crm_periph_reset(crm_periph_reset_type value, confirm_state new_state);
+void crm_periph_lowpower_mode_enable(crm_periph_clock_lowpower_type value, confirm_state new_state);
+void crm_clock_source_enable(crm_clock_source_type source, confirm_state new_state);
+void crm_flag_clear(uint32_t flag);
+void crm_ertc_clock_select(crm_ertc_clock_type value);
+void crm_ertc_clock_enable(confirm_state new_state);
+void crm_ahb_div_set(crm_ahb_div_type value);
+void crm_apb1_div_set(crm_apb1_div_type value);
+void crm_apb2_div_set(crm_apb2_div_type value);
+void crm_hext_sclk_div_set(crm_hext_sclk_div_type value);
+void crm_hick_sclk_div_set(crm_hick_sclk_div_type value);
+void crm_clock_failure_detection_enable(confirm_state new_state);
+void crm_battery_powered_domain_reset(confirm_state new_state);
+void crm_pll_config(crm_pll_clock_source_type clock_source, uint16_t pll_ns, \
+ uint16_t pll_ms, crm_pll_fp_type pll_fr);
+void crm_sysclk_switch(crm_sclk_type value);
+crm_sclk_type crm_sysclk_switch_status_get(void);
+void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct);
+void crm_clock_out_set(crm_clkout_select_type clkout);
+void crm_clkout_div_set(crm_clkout_div1_type div1, crm_clkout_div2_type div2);
+void crm_interrupt_enable(uint32_t crm_int, confirm_state new_state);
+void crm_auto_step_mode_enable(confirm_state new_state);
+void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value);
+void crm_usb_clock_source_select(crm_usb_clock_source_type value);
+void crm_emac_output_pulse_set(crm_emac_output_pulse_type width);
+error_status crm_pll_parameter_calculate(crm_pll_clock_source_type pll_rcs, uint32_t target_sclk_freq, \
+ uint16_t *ret_ms, uint16_t *ret_ns, uint16_t *ret_fr);
+void crm_apb3_div_set(crm_apb3_div_type value);
+void crm_i2sf5_clock_select(crm_i2sf5_clock_source_type value);
+void crm_can_clock_select(crm_can_type can_index, crm_can_clock_source_type value);
+crm_can_clock_source_type crm_can_clock_get(crm_can_type can_index);
+void crm_pllu_div_set(crm_pll_fu_type pll_fu);
+void crm_pllu_output_set(confirm_state new_state);
+void crm_vbath_div_set(crm_vbath_div_type value);
+void crm_lextdrv_set(crm_drv_strength_type value);
+void crm_hextdrv_set(crm_drv_strength_type value);
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_dac.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_dac.h
new file mode 100644
index 00000000000..cf615e1fd64
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_dac.h
@@ -0,0 +1,393 @@
+/**
+ **************************************************************************
+ * @file at32F45x_dac.h
+ * @brief at32F45x dac header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_DAC_H
+#define __AT32F45x_DAC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f45x.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+#define DAC1_D1DMAUDRF ((uint32_t)(0x00002000))
+#define DAC2_D2DMAUDRF ((uint32_t)(0x20000000))
+
+/** @defgroup DAC_exported_types
+ * @{
+ */
+
+/**
+ * @brief dac select type
+ */
+typedef enum
+{
+ DAC1_SELECT = 0x01, /*!< dac1 select */
+ DAC2_SELECT = 0x02 /*!< dac2 select */
+} dac_select_type;
+
+/**
+ * @brief dac trigger type
+ */
+typedef enum
+{
+ DAC_TMR6_TRGOUT_EVENT = 0x00, /*!< dac trigger selection:timer6 trgout event */
+ DAC_TMR8_TRGOUT_EVENT = 0x01, /*!< dac trigger selection:timer8 trgout event */
+ DAC_TMR7_TRGOUT_EVENT = 0x02, /*!< dac trigger selection:timer7 trgout event */
+ DAC_TMR5_TRGOUT_EVENT = 0x03, /*!< dac trigger selection:timer5 trgout event */
+ DAC_TMR2_TRGOUT_EVENT = 0x04, /*!< dac trigger selection:timer2 trgout event */
+ DAC_TMR4_TRGOUT_EVENT = 0x05, /*!< dac trigger selection:timer4 trgout event */
+ DAC_EXTERNAL_INTERRUPT_LINE_9 = 0x06, /*!< dac trigger selection:external line9 */
+ DAC_SOFTWARE_TRIGGER = 0x07 /*!< dac trigger selection:software trigger */
+} dac_trigger_type;
+
+/**
+ * @brief dac wave type
+ */
+typedef enum
+{
+ DAC_WAVE_GENERATE_NONE = 0x00, /*!< dac wave generation disabled */
+ DAC_WAVE_GENERATE_NOISE = 0x01, /*!< dac noise wave generation enabled */
+ DAC_WAVE_GENERATE_TRIANGLE = 0x02 /*!< dac triangle wave generation enabled */
+} dac_wave_type;
+
+/**
+ * @brief dac mask amplitude type
+ */
+typedef enum
+{
+ DAC_LSFR_BIT0_AMPLITUDE_1 = 0x00, /*!< unmask bit0/ triangle amplitude equal to 1 */
+ DAC_LSFR_BIT10_AMPLITUDE_3 = 0x01, /*!< unmask bit[1:0]/ triangle amplitude equal to 3 */
+ DAC_LSFR_BIT20_AMPLITUDE_7 = 0x02, /*!< unmask bit[2:0]/ triangle amplitude equal to 7 */
+ DAC_LSFR_BIT30_AMPLITUDE_15 = 0x03, /*!< unmask bit[3:0]/ triangle amplitude equal to 15 */
+ DAC_LSFR_BIT40_AMPLITUDE_31 = 0x04, /*!< unmask bit[4:0]/ triangle amplitude equal to 31 */
+ DAC_LSFR_BIT50_AMPLITUDE_63 = 0x05, /*!< unmask bit[5:0]/ triangle amplitude equal to 63 */
+ DAC_LSFR_BIT60_AMPLITUDE_127 = 0x06, /*!< unmask bit[6:0]/ triangle amplitude equal to 127 */
+ DAC_LSFR_BIT70_AMPLITUDE_255 = 0x07, /*!< unmask bit[7:0]/ triangle amplitude equal to 255 */
+ DAC_LSFR_BIT80_AMPLITUDE_511 = 0x08, /*!< unmask bit[8:0]/ triangle amplitude equal to 511 */
+ DAC_LSFR_BIT90_AMPLITUDE_1023 = 0x09, /*!< unmask bit[9:0]/ triangle amplitude equal to 1023 */
+ DAC_LSFR_BITA0_AMPLITUDE_2047 = 0x0A, /*!< unmask bit[10:0]/ triangle amplitude equal to 2047 */
+ DAC_LSFR_BITB0_AMPLITUDE_4095 = 0x0B /*!< unmask bit[11:0]/ triangle amplitude equal to 4095 */
+} dac_mask_amplitude_type;
+
+/**
+ * @brief dac1 aligned data type
+ */
+typedef enum
+{
+ DAC1_12BIT_RIGHT = 0x40007408, /*!< dac1 12-bit data right-aligned */
+ DAC1_12BIT_LEFT = 0x4000740C, /*!< dac1 12-bit data left-aligned */
+ DAC1_8BIT_RIGHT = 0x40007410 /*!< dac1 8-bit data right-aligned */
+} dac1_aligned_data_type;
+
+/**
+ * @brief dac2 aligned data type
+ */
+typedef enum
+{
+ DAC2_12BIT_RIGHT = 0x40007414, /*!< dac2 12-bit data right-aligned */
+ DAC2_12BIT_LEFT = 0x40007418, /*!< dac2 12-bit data left-aligned */
+ DAC2_8BIT_RIGHT = 0x4000741C /*!< dac2 8-bit data right-aligned */
+} dac2_aligned_data_type;
+
+/**
+ * @brief dac dual data type
+ */
+typedef enum
+{
+ DAC_DUAL_12BIT_RIGHT = 0x40007420, /*!psr = (uint32_t)(0x150 | wtcyc))
+
+/** @defgroup FLASH_exported_types
+ * @{
+ */
+
+/**
+ * @brief flash status type
+ */
+typedef enum
+{
+ FLASH_OPERATE_BUSY = 0x00, /*!< flash status is operate busy */
+ FLASH_PROGRAM_ERROR = 0x01, /*!< flash status is program error */
+ FLASH_EPP_ERROR = 0x02, /*!< flash status is epp error */
+ FLASH_OPERATE_DONE = 0x03, /*!< flash status is operate done */
+ FLASH_OPERATE_TIMEOUT = 0x04 /*!< flash status is operate timeout */
+} flash_status_type;
+
+/**
+ * @brief flash wait cycle type
+ */
+typedef enum
+{
+ FLASH_WAIT_CYCLE_0 = 0x00, /*!< sysclk 1~32mhz */
+ FLASH_WAIT_CYCLE_1 = 0x01, /*!< sysclk 33~64mhz */
+ FLASH_WAIT_CYCLE_2 = 0x02, /*!< sysclk 65~96mhz */
+ FLASH_WAIT_CYCLE_3 = 0x03, /*!< sysclk 97~128mhz */
+ FLASH_WAIT_CYCLE_4 = 0x04, /*!< sysclk 129~160mhz */
+ FLASH_WAIT_CYCLE_5 = 0x05, /*!< sysclk 161~180mhz */
+} flash_wait_cycle_type;
+
+/**
+ * @brief type define flash register all
+ */
+typedef struct
+{
+ /**
+ * @brief flash psr register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t psr;
+ struct
+ {
+ __IO uint32_t wtcyc : 3; /* [2:0] */
+ __IO uint32_t reserved1 : 1; /* [3] */
+ __IO uint32_t pft_en : 1; /* [4] */
+ __IO uint32_t pft_enf : 1; /* [5] */
+ __IO uint32_t pft_en2 : 1; /* [6] */
+ __IO uint32_t pft_enf2 : 1; /* [7] */
+ __IO uint32_t pft_lat_dis : 1; /* [8] */
+ __IO uint32_t reserved2 : 23;/* [31:9] */
+ } psr_bit;
+ };
+
+ /**
+ * @brief flash unlock register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t unlock;
+ struct
+ {
+ __IO uint32_t ukval : 32;/* [31:0] */
+ } unlock_bit;
+ };
+
+ /**
+ * @brief flash usd unlock register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t usd_unlock;
+ struct
+ {
+ __IO uint32_t usd_ukval : 32;/* [31:0] */
+ } usd_unlock_bit;
+ };
+
+ /**
+ * @brief flash sts register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t obf : 1; /* [0] */
+ __IO uint32_t reserved1 : 1; /* [1] */
+ __IO uint32_t prgmerr : 1; /* [2] */
+ __IO uint32_t reserved2 : 1; /* [3] */
+ __IO uint32_t epperr : 1; /* [4] */
+ __IO uint32_t odf : 1; /* [5] */
+ __IO uint32_t reserved3 : 26;/* [31:6] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief flash ctrl register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t ctrl;
+ struct
+ {
+ __IO uint32_t fprgm : 1; /* [0] */
+ __IO uint32_t secers : 1; /* [1] */
+ __IO uint32_t bankers : 1; /* [2] */
+ __IO uint32_t reserved1 : 1; /* [3] */
+ __IO uint32_t usdprgm : 1; /* [4] */
+ __IO uint32_t usders : 1; /* [5] */
+ __IO uint32_t erstr : 1; /* [6] */
+ __IO uint32_t oplk : 1; /* [7] */
+ __IO uint32_t reserved2 : 1; /* [8] */
+ __IO uint32_t usdulks : 1; /* [9] */
+ __IO uint32_t errie : 1; /* [10] */
+ __IO uint32_t reserved3 : 1; /* [11] */
+ __IO uint32_t odfie : 1; /* [12] */
+ __IO uint32_t reserved4 : 19;/* [31:13] */
+ } ctrl_bit;
+ };
+
+ /**
+ * @brief flash addr register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t addr;
+ struct
+ {
+ __IO uint32_t fa : 32;/* [31:0] */
+ } addr_bit;
+ };
+
+ /**
+ * @brief flash reserved1 register, offset:0x18
+ */
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief flash usd register, offset:0x1C
+ */
+ union
+ {
+ __IO uint32_t usd;
+ struct
+ {
+ __IO uint32_t usderr : 1; /* [0] */
+ __IO uint32_t fap : 1; /* [1] */
+ __IO uint32_t wdt_ato_en : 1; /* [2] */
+ __IO uint32_t depslp_rst : 1; /* [3] */
+ __IO uint32_t stdby_rst : 1; /* [4] */
+ __IO uint32_t reserved1 : 1; /* [5] */
+ __IO uint32_t boot1 : 1; /* [6] */
+ __IO uint32_t depslp_wdt : 1; /* [7] */
+ __IO uint32_t stdby_wdt : 1; /* [8] */
+ __IO uint32_t reserved2 : 1; /* [9] */
+ __IO uint32_t user_d0 : 8; /* [17:10] */
+ __IO uint32_t user_d1 : 8; /* [25:18] */
+ __IO uint32_t fap_hl : 1; /* [26] */
+ __IO uint32_t reserved3 : 5; /* [31:27] */
+ } usd_bit;
+ };
+
+ /**
+ * @brief flash epps register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t epps;
+ struct
+ {
+ __IO uint32_t epps : 32;/* [31:0] */
+ } epps_bit;
+ };
+
+ /**
+ * @brief flash reserved2 register, offset:0x70~0x24
+ */
+ __IO uint32_t reserved2[20];
+
+ /**
+ * @brief flash slib_sts0 register, offset:0x74
+ */
+ union
+ {
+ __IO uint32_t slib_sts0;
+ struct
+ {
+ __IO uint32_t btm_ap_enf : 1; /* [0] */
+ __IO uint32_t reserved1 : 1; /* [1] */
+ __IO uint32_t em_slib_enf : 1; /* [2] */
+ __IO uint32_t slib_enf : 1; /* [3] */
+ __IO uint32_t reserved2 : 12;/* [15:4] */
+ __IO uint32_t em_slib_inst_ss : 8; /* [23:16] */
+ __IO uint32_t reserved3 : 8; /* [31:24] */
+ } slib_sts0_bit;
+ };
+
+ /**
+ * @brief flash slib_sts1 register, offset:0x78
+ */
+ union
+ {
+ __IO uint32_t slib_sts1;
+ struct
+ {
+ __IO uint32_t slib_ss : 11;/* [10:0] */
+ __IO uint32_t slib_inst_ss : 11;/* [21:11] */
+ __IO uint32_t slib_es : 10;/* [31:22] */
+ } slib_sts1_bit;
+ };
+
+ /**
+ * @brief flash slib_pwd_clr register, offset:0x7C
+ */
+ union
+ {
+ __IO uint32_t slib_pwd_clr;
+ struct
+ {
+ __IO uint32_t slib_pclr_val : 32;/* [31:0] */
+ } slib_pwd_clr_bit;
+ };
+
+ /**
+ * @brief flash slib_misc_sts register, offset:0x80
+ */
+ union
+ {
+ __IO uint32_t slib_misc_sts;
+ struct
+ {
+ __IO uint32_t slib_pwd_err : 1; /* [0] */
+ __IO uint32_t slib_pwd_ok : 1; /* [1] */
+ __IO uint32_t slib_ulkf : 1; /* [2] */
+ __IO uint32_t reserved1 : 29;/* [31:3] */
+ } slib_misc_sts_bit;
+ };
+
+ /**
+ * @brief flash crc_addr register, offset:0x84
+ */
+ union
+ {
+ __IO uint32_t crc_addr;
+ struct
+ {
+ __IO uint32_t crc_addr : 32;/* [31:0] */
+ } crc_addr_bit;
+ };
+
+ /**
+ * @brief flash crc_ctrl register, offset:0x88
+ */
+ union
+ {
+ __IO uint32_t crc_ctrl;
+ struct
+ {
+ __IO uint32_t crc_sn : 16;/* [15:0] */
+ __IO uint32_t crc_strt : 1; /* [16] */
+ __IO uint32_t reserved1 : 15;/* [31:17] */
+ } crc_ctrl_bit;
+ };
+
+ /**
+ * @brief flash crc_chkr register, offset:0x8C
+ */
+ union
+ {
+ __IO uint32_t crc_chkr;
+ struct
+ {
+ __IO uint32_t crc_chkr : 32;/* [31:0] */
+ } crc_chkr_bit;
+ };
+
+ /**
+ * @brief flash reserved3 register, offset:0x15C~0x90
+ */
+ __IO uint32_t reserved3[52];
+
+ /**
+ * @brief flash slib_set_pwd register, offset:0x160
+ */
+ union
+ {
+ __IO uint32_t slib_set_pwd;
+ struct
+ {
+ __IO uint32_t slib_pset_val : 32;/* [31:0] */
+ } slib_set_pwd_bit;
+ };
+
+ /**
+ * @brief flash slib_set_range register, offset:0x164
+ */
+ union
+ {
+ __IO uint32_t slib_set_range;
+ struct
+ {
+ __IO uint32_t slib_ss_set : 11;/* [10:0] */
+ __IO uint32_t slib_iss_set : 11;/* [21:11] */
+ __IO uint32_t slib_es_set : 10;/* [31:22] */
+ } slib_set_range_bit;
+ };
+
+ /**
+ * @brief flash em_slib_set register, offset:0x168
+ */
+ union
+ {
+ __IO uint32_t em_slib_set;
+ struct
+ {
+ __IO uint32_t em_slib_set : 16;/* [15:0] */
+ __IO uint32_t em_slib_iss_set : 8; /* [23:16] */
+ __IO uint32_t reserved1 : 8; /* [31:24] */
+ } em_slib_set_bit;
+ };
+
+ /**
+ * @brief flash btm_mode_set register, offset:0x16C
+ */
+ union
+ {
+ __IO uint32_t btm_mode_set;
+ struct
+ {
+ __IO uint32_t btm_mode_set : 8; /* [7:0] */
+ __IO uint32_t reserved1 : 24;/* [31:8] */
+ } btm_mode_set_bit;
+ };
+
+ /**
+ * @brief flash slib_unlock register, offset:0x170
+ */
+ union
+ {
+ __IO uint32_t slib_unlock;
+ struct
+ {
+ __IO uint32_t slib_ukval : 32;/* [31:0] */
+ } slib_unlock_bit;
+ };
+
+} flash_type;
+
+/**
+ * @brief user system data
+ */
+typedef struct
+{
+ __IO uint16_t fap;
+ __IO uint16_t ssb;
+ __IO uint16_t data0;
+ __IO uint16_t data1;
+ __IO uint16_t epp0;
+ __IO uint16_t epp1;
+ __IO uint16_t epp2;
+ __IO uint16_t epp3;
+} usd_type;
+
+/**
+ * @}
+ */
+
+#define FLASH ((flash_type *) FLASH_REG_BASE)
+#define USD ((usd_type *) USD_BASE)
+
+/** @defgroup FLASH_exported_functions
+ * @{
+ */
+
+flag_status flash_flag_get(uint32_t flash_flag);
+void flash_flag_clear(uint32_t flash_flag);
+flash_status_type flash_operation_status_get(void);
+flash_status_type flash_operation_wait_for(uint32_t time_out);
+void flash_unlock(void);
+void flash_lock(void);
+flash_status_type flash_sector_erase(uint32_t sector_address);
+flash_status_type flash_internal_all_erase(void);
+flash_status_type flash_user_system_data_erase(void);
+flash_status_type flash_word_program(uint32_t address, uint32_t data);
+flash_status_type flash_halfword_program(uint32_t address, uint16_t data);
+flash_status_type flash_byte_program(uint32_t address, uint8_t data);
+flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data);
+flash_status_type flash_epp_set(uint32_t *sector_bits);
+void flash_epp_status_get(uint32_t *sector_bits);
+flash_status_type flash_fap_enable(confirm_state new_state);
+flag_status flash_fap_status_get(void);
+flash_status_type flash_fap_high_level_enable(void);
+flag_status flash_fap_high_level_status_get(void);
+flash_status_type flash_ssb_set(uint8_t usd_ssb);
+uint8_t flash_ssb_status_get(void);
+void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state);
+flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t inst_start_sector, uint16_t end_sector);
+error_status flash_slib_disable(uint32_t pwd);
+flag_status flash_slib_state_get(void);
+uint16_t flash_slib_start_sector_get(void);
+uint16_t flash_slib_inststart_sector_get(void);
+uint16_t flash_slib_end_sector_get(void);
+uint32_t flash_crc_calibrate(uint32_t start_addr, uint32_t sector_cnt);
+void flash_boot_memory_extension_mode_enable(void);
+flash_status_type flash_extension_memory_slib_enable(uint32_t pwd, uint16_t inst_start_sector);
+flag_status flash_extension_memory_slib_state_get(void);
+uint16_t flash_em_slib_inststart_sector_get(void);
+flash_status_type flash_otp_data_program(uint32_t address, uint8_t *data_buf, uint16_t length);
+flash_status_type flash_otp_lock_enable(uint8_t area_index);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_gpio.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_gpio.h
new file mode 100644
index 00000000000..e5f8a9e0d62
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_gpio.h
@@ -0,0 +1,591 @@
+/**
+ **************************************************************************
+ * @file at32f45x_gpio.h
+ * @brief at32f45x gpio header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_GPIO_H
+#define __AT32F45x_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f45x.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/** @defgroup GPIO_pins_number_definition
+ * @{
+ */
+
+#define GPIO_PINS_0 0x0001 /*!< gpio pins number 0 */
+#define GPIO_PINS_1 0x0002 /*!< gpio pins number 1 */
+#define GPIO_PINS_2 0x0004 /*!< gpio pins number 2 */
+#define GPIO_PINS_3 0x0008 /*!< gpio pins number 3 */
+#define GPIO_PINS_4 0x0010 /*!< gpio pins number 4 */
+#define GPIO_PINS_5 0x0020 /*!< gpio pins number 5 */
+#define GPIO_PINS_6 0x0040 /*!< gpio pins number 6 */
+#define GPIO_PINS_7 0x0080 /*!< gpio pins number 7 */
+#define GPIO_PINS_8 0x0100 /*!< gpio pins number 8 */
+#define GPIO_PINS_9 0x0200 /*!< gpio pins number 9 */
+#define GPIO_PINS_10 0x0400 /*!< gpio pins number 10 */
+#define GPIO_PINS_11 0x0800 /*!< gpio pins number 11 */
+#define GPIO_PINS_12 0x1000 /*!< gpio pins number 12 */
+#define GPIO_PINS_13 0x2000 /*!< gpio pins number 13 */
+#define GPIO_PINS_14 0x4000 /*!< gpio pins number 14 */
+#define GPIO_PINS_15 0x8000 /*!< gpio pins number 15 */
+#define GPIO_PINS_ALL 0xFFFF /*!< gpio all pins */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_exported_types
+ * @{
+ */
+
+/**
+ * @brief gpio mode select
+ */
+typedef enum
+{
+ GPIO_MODE_INPUT = 0x00, /*!< gpio input mode */
+ GPIO_MODE_OUTPUT = 0x01, /*!< gpio output mode */
+ GPIO_MODE_MUX = 0x02, /*!< gpio mux function mode */
+ GPIO_MODE_ANALOG = 0x03 /*!< gpio analog in/out mode */
+} gpio_mode_type;
+
+/**
+ * @brief gpio output drive strength select
+ */
+typedef enum
+{
+ GPIO_DRIVE_STRENGTH_STRONGER = 0x01, /*!< stronger sourcing/sinking strength */
+ GPIO_DRIVE_STRENGTH_MODERATE = 0x02 /*!< moderate sourcing/sinking strength */
+} gpio_drive_type;
+
+/**
+ * @brief gpio output type
+ */
+typedef enum
+{
+ GPIO_OUTPUT_PUSH_PULL = 0x00, /*!< output push-pull */
+ GPIO_OUTPUT_OPEN_DRAIN = 0x01 /*!< output open-drain */
+} gpio_output_type;
+
+/**
+ * @brief gpio pull type
+ */
+typedef enum
+{
+ GPIO_PULL_NONE = 0x00, /*!< floating for input, no pull for output */
+ GPIO_PULL_UP = 0x01, /*!< pull-up */
+ GPIO_PULL_DOWN = 0x02 /*!< pull-down */
+} gpio_pull_type;
+
+/**
+ * @brief gpio init type
+ */
+typedef struct
+{
+ uint32_t gpio_pins; /*!< pins number selection */
+ gpio_output_type gpio_out_type; /*!< output type selection */
+ gpio_pull_type gpio_pull; /*!< pull type selection */
+ gpio_mode_type gpio_mode; /*!< mode selection */
+ gpio_drive_type gpio_drive_strength; /*!< drive strength selection */
+} gpio_init_type;
+
+/**
+ * @brief gpio pins source type
+ */
+typedef enum
+{
+ GPIO_PINS_SOURCE0 = 0x00, /*!< gpio pins source number 0 */
+ GPIO_PINS_SOURCE1 = 0x01, /*!< gpio pins source number 1 */
+ GPIO_PINS_SOURCE2 = 0x02, /*!< gpio pins source number 2 */
+ GPIO_PINS_SOURCE3 = 0x03, /*!< gpio pins source number 3 */
+ GPIO_PINS_SOURCE4 = 0x04, /*!< gpio pins source number 4 */
+ GPIO_PINS_SOURCE5 = 0x05, /*!< gpio pins source number 5 */
+ GPIO_PINS_SOURCE6 = 0x06, /*!< gpio pins source number 6 */
+ GPIO_PINS_SOURCE7 = 0x07, /*!< gpio pins source number 7 */
+ GPIO_PINS_SOURCE8 = 0x08, /*!< gpio pins source number 8 */
+ GPIO_PINS_SOURCE9 = 0x09, /*!< gpio pins source number 9 */
+ GPIO_PINS_SOURCE10 = 0x0A, /*!< gpio pins source number 10 */
+ GPIO_PINS_SOURCE11 = 0x0B, /*!< gpio pins source number 11 */
+ GPIO_PINS_SOURCE12 = 0x0C, /*!< gpio pins source number 12 */
+ GPIO_PINS_SOURCE13 = 0x0D, /*!< gpio pins source number 13 */
+ GPIO_PINS_SOURCE14 = 0x0E, /*!< gpio pins source number 14 */
+ GPIO_PINS_SOURCE15 = 0x0F /*!< gpio pins source number 15 */
+} gpio_pins_source_type;
+
+/**
+ * @brief gpio muxing function selection type
+ */
+typedef enum
+{
+ GPIO_MUX_0 = 0x00, /*!< gpio muxing function selection 0 */
+ GPIO_MUX_1 = 0x01, /*!< gpio muxing function selection 1 */
+ GPIO_MUX_2 = 0x02, /*!< gpio muxing function selection 2 */
+ GPIO_MUX_3 = 0x03, /*!< gpio muxing function selection 3 */
+ GPIO_MUX_4 = 0x04, /*!< gpio muxing function selection 4 */
+ GPIO_MUX_5 = 0x05, /*!< gpio muxing function selection 5 */
+ GPIO_MUX_6 = 0x06, /*!< gpio muxing function selection 6 */
+ GPIO_MUX_7 = 0x07, /*!< gpio muxing function selection 7 */
+ GPIO_MUX_8 = 0x08, /*!< gpio muxing function selection 8 */
+ GPIO_MUX_9 = 0x09, /*!< gpio muxing function selection 9 */
+ GPIO_MUX_10 = 0x0A, /*!< gpio muxing function selection 10 */
+ GPIO_MUX_11 = 0x0B, /*!< gpio muxing function selection 11 */
+ GPIO_MUX_12 = 0x0C, /*!< gpio muxing function selection 12 */
+ GPIO_MUX_13 = 0x0D, /*!< gpio muxing function selection 13 */
+ GPIO_MUX_14 = 0x0E, /*!< gpio muxing function selection 14 */
+ GPIO_MUX_15 = 0x0F /*!< gpio muxing function selection 15 */
+} gpio_mux_sel_type;
+
+/**
+ * @brief type define gpio register all
+ */
+typedef struct
+{
+ /**
+ * @brief gpio mode register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t cfgr;
+ struct
+ {
+ __IO uint32_t iomc0 : 2; /* [1:0] */
+ __IO uint32_t iomc1 : 2; /* [3:2] */
+ __IO uint32_t iomc2 : 2; /* [5:4] */
+ __IO uint32_t iomc3 : 2; /* [7:6] */
+ __IO uint32_t iomc4 : 2; /* [9:8] */
+ __IO uint32_t iomc5 : 2; /* [11:10] */
+ __IO uint32_t iomc6 : 2; /* [13:12] */
+ __IO uint32_t iomc7 : 2; /* [15:14] */
+ __IO uint32_t iomc8 : 2; /* [17:16] */
+ __IO uint32_t iomc9 : 2; /* [19:18] */
+ __IO uint32_t iomc10 : 2; /* [21:20] */
+ __IO uint32_t iomc11 : 2; /* [23:22] */
+ __IO uint32_t iomc12 : 2; /* [25:24] */
+ __IO uint32_t iomc13 : 2; /* [27:26] */
+ __IO uint32_t iomc14 : 2; /* [29:28] */
+ __IO uint32_t iomc15 : 2; /* [31:30] */
+ } cfgr_bit;
+ };
+
+ /**
+ * @brief gpio output type register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t omode;
+ struct
+ {
+ __IO uint32_t om0 : 1; /* [0] */
+ __IO uint32_t om1 : 1; /* [1] */
+ __IO uint32_t om2 : 1; /* [2] */
+ __IO uint32_t om3 : 1; /* [3] */
+ __IO uint32_t om4 : 1; /* [4] */
+ __IO uint32_t om5 : 1; /* [5] */
+ __IO uint32_t om6 : 1; /* [6] */
+ __IO uint32_t om7 : 1; /* [7] */
+ __IO uint32_t om8 : 1; /* [8] */
+ __IO uint32_t om9 : 1; /* [9] */
+ __IO uint32_t om10 : 1; /* [10] */
+ __IO uint32_t om11 : 1; /* [11] */
+ __IO uint32_t om12 : 1; /* [12] */
+ __IO uint32_t om13 : 1; /* [13] */
+ __IO uint32_t om14 : 1; /* [14] */
+ __IO uint32_t om15 : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } omode_bit;
+ };
+
+ /**
+ * @brief gpio output driver register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t odrvr;
+ struct
+ {
+ __IO uint32_t odrv0 : 2; /* [1:0] */
+ __IO uint32_t odrv1 : 2; /* [3:2] */
+ __IO uint32_t odrv2 : 2; /* [5:4] */
+ __IO uint32_t odrv3 : 2; /* [7:6] */
+ __IO uint32_t odrv4 : 2; /* [9:8] */
+ __IO uint32_t odrv5 : 2; /* [11:10] */
+ __IO uint32_t odrv6 : 2; /* [13:12] */
+ __IO uint32_t odrv7 : 2; /* [15:14] */
+ __IO uint32_t odrv8 : 2; /* [17:16] */
+ __IO uint32_t odrv9 : 2; /* [19:18] */
+ __IO uint32_t odrv10 : 2; /* [21:20] */
+ __IO uint32_t odrv11 : 2; /* [23:22] */
+ __IO uint32_t odrv12 : 2; /* [25:24] */
+ __IO uint32_t odrv13 : 2; /* [27:26] */
+ __IO uint32_t odrv14 : 2; /* [29:28] */
+ __IO uint32_t odrv15 : 2; /* [31:30] */
+ } odrvr_bit;
+ };
+
+ /**
+ * @brief gpio pull up/down register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t pull;
+ struct
+ {
+ __IO uint32_t pull0 : 2; /* [1:0] */
+ __IO uint32_t pull1 : 2; /* [3:2] */
+ __IO uint32_t pull2 : 2; /* [5:4] */
+ __IO uint32_t pull3 : 2; /* [7:6] */
+ __IO uint32_t pull4 : 2; /* [9:8] */
+ __IO uint32_t pull5 : 2; /* [11:10] */
+ __IO uint32_t pull6 : 2; /* [13:12] */
+ __IO uint32_t pull7 : 2; /* [15:14] */
+ __IO uint32_t pull8 : 2; /* [17:16] */
+ __IO uint32_t pull9 : 2; /* [19:18] */
+ __IO uint32_t pull10 : 2; /* [21:20] */
+ __IO uint32_t pull11 : 2; /* [23:22] */
+ __IO uint32_t pull12 : 2; /* [25:24] */
+ __IO uint32_t pull13 : 2; /* [27:26] */
+ __IO uint32_t pull14 : 2; /* [29:28] */
+ __IO uint32_t pull15 : 2; /* [31:30] */
+ } pull_bit;
+ };
+
+ /**
+ * @brief gpio input data register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t idt;
+ struct
+ {
+ __IO uint32_t idt0 : 1; /* [0] */
+ __IO uint32_t idt1 : 1; /* [1] */
+ __IO uint32_t idt2 : 1; /* [2] */
+ __IO uint32_t idt3 : 1; /* [3] */
+ __IO uint32_t idt4 : 1; /* [4] */
+ __IO uint32_t idt5 : 1; /* [5] */
+ __IO uint32_t idt6 : 1; /* [6] */
+ __IO uint32_t idt7 : 1; /* [7] */
+ __IO uint32_t idt8 : 1; /* [8] */
+ __IO uint32_t idt9 : 1; /* [9] */
+ __IO uint32_t idt10 : 1; /* [10] */
+ __IO uint32_t idt11 : 1; /* [11] */
+ __IO uint32_t idt12 : 1; /* [12] */
+ __IO uint32_t idt13 : 1; /* [13] */
+ __IO uint32_t idt14 : 1; /* [14] */
+ __IO uint32_t idt15 : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } idt_bit;
+ };
+
+ /**
+ * @brief gpio output data register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t odt;
+ struct
+ {
+ __IO uint32_t odt0 : 1; /* [0] */
+ __IO uint32_t odt1 : 1; /* [1] */
+ __IO uint32_t odt2 : 1; /* [2] */
+ __IO uint32_t odt3 : 1; /* [3] */
+ __IO uint32_t odt4 : 1; /* [4] */
+ __IO uint32_t odt5 : 1; /* [5] */
+ __IO uint32_t odt6 : 1; /* [6] */
+ __IO uint32_t odt7 : 1; /* [7] */
+ __IO uint32_t odt8 : 1; /* [8] */
+ __IO uint32_t odt9 : 1; /* [9] */
+ __IO uint32_t odt10 : 1; /* [10] */
+ __IO uint32_t odt11 : 1; /* [11] */
+ __IO uint32_t odt12 : 1; /* [12] */
+ __IO uint32_t odt13 : 1; /* [13] */
+ __IO uint32_t odt14 : 1; /* [14] */
+ __IO uint32_t odt15 : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } odt_bit;
+ };
+
+ /**
+ * @brief gpio scr register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t scr;
+ struct
+ {
+ __IO uint32_t iosb0 : 1; /* [0] */
+ __IO uint32_t iosb1 : 1; /* [1] */
+ __IO uint32_t iosb2 : 1; /* [2] */
+ __IO uint32_t iosb3 : 1; /* [3] */
+ __IO uint32_t iosb4 : 1; /* [4] */
+ __IO uint32_t iosb5 : 1; /* [5] */
+ __IO uint32_t iosb6 : 1; /* [6] */
+ __IO uint32_t iosb7 : 1; /* [7] */
+ __IO uint32_t iosb8 : 1; /* [8] */
+ __IO uint32_t iosb9 : 1; /* [9] */
+ __IO uint32_t iosb10 : 1; /* [10] */
+ __IO uint32_t iosb11 : 1; /* [11] */
+ __IO uint32_t iosb12 : 1; /* [12] */
+ __IO uint32_t iosb13 : 1; /* [13] */
+ __IO uint32_t iosb14 : 1; /* [14] */
+ __IO uint32_t iosb15 : 1; /* [15] */
+ __IO uint32_t iocb0 : 1; /* [16] */
+ __IO uint32_t iocb1 : 1; /* [17] */
+ __IO uint32_t iocb2 : 1; /* [18] */
+ __IO uint32_t iocb3 : 1; /* [19] */
+ __IO uint32_t iocb4 : 1; /* [20] */
+ __IO uint32_t iocb5 : 1; /* [21] */
+ __IO uint32_t iocb6 : 1; /* [22] */
+ __IO uint32_t iocb7 : 1; /* [23] */
+ __IO uint32_t iocb8 : 1; /* [24] */
+ __IO uint32_t iocb9 : 1; /* [25] */
+ __IO uint32_t iocb10 : 1; /* [26] */
+ __IO uint32_t iocb11 : 1; /* [27] */
+ __IO uint32_t iocb12 : 1; /* [28] */
+ __IO uint32_t iocb13 : 1; /* [29] */
+ __IO uint32_t iocb14 : 1; /* [30] */
+ __IO uint32_t iocb15 : 1; /* [31] */
+ } scr_bit;
+ };
+
+ /**
+ * @brief gpio wpen register, offset:0x1C
+ */
+ union
+ {
+ __IO uint32_t wpr;
+ struct
+ {
+ __IO uint32_t wpen0 : 1; /* [0] */
+ __IO uint32_t wpen1 : 1; /* [1] */
+ __IO uint32_t wpen2 : 1; /* [2] */
+ __IO uint32_t wpen3 : 1; /* [3] */
+ __IO uint32_t wpen4 : 1; /* [4] */
+ __IO uint32_t wpen5 : 1; /* [5] */
+ __IO uint32_t wpen6 : 1; /* [6] */
+ __IO uint32_t wpen7 : 1; /* [7] */
+ __IO uint32_t wpen8 : 1; /* [8] */
+ __IO uint32_t wpen9 : 1; /* [9] */
+ __IO uint32_t wpen10 : 1; /* [10] */
+ __IO uint32_t wpen11 : 1; /* [11] */
+ __IO uint32_t wpen12 : 1; /* [12] */
+ __IO uint32_t wpen13 : 1; /* [13] */
+ __IO uint32_t wpen14 : 1; /* [14] */
+ __IO uint32_t wpen15 : 1; /* [15] */
+ __IO uint32_t wpseq : 1; /* [16] */
+ __IO uint32_t reserved1 : 15;/* [31:17] */
+ } wpr_bit;
+ };
+
+ /**
+ * @brief gpio muxl register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t muxl;
+ struct
+ {
+ __IO uint32_t muxl0 : 4; /* [3:0] */
+ __IO uint32_t muxl1 : 4; /* [7:4] */
+ __IO uint32_t muxl2 : 4; /* [11:8] */
+ __IO uint32_t muxl3 : 4; /* [15:12] */
+ __IO uint32_t muxl4 : 4; /* [19:16] */
+ __IO uint32_t muxl5 : 4; /* [23:20] */
+ __IO uint32_t muxl6 : 4; /* [27:24] */
+ __IO uint32_t muxl7 : 4; /* [31:28] */
+ } muxl_bit;
+ };
+
+ /**
+ * @brief gpio muxh register, offset:0x24
+ */
+ union
+ {
+ __IO uint32_t muxh;
+ struct
+ {
+ __IO uint32_t muxh8 : 4; /* [3:0] */
+ __IO uint32_t muxh9 : 4; /* [7:4] */
+ __IO uint32_t muxh10 : 4; /* [11:8] */
+ __IO uint32_t muxh11 : 4; /* [15:12] */
+ __IO uint32_t muxh12 : 4; /* [19:16] */
+ __IO uint32_t muxh13 : 4; /* [23:20] */
+ __IO uint32_t muxh14 : 4; /* [27:24] */
+ __IO uint32_t muxh15 : 4; /* [31:28] */
+ } muxh_bit;
+ };
+
+ /**
+ * @brief gpio clr register, offset:0x28
+ */
+ union
+ {
+ __IO uint32_t clr;
+ struct
+ {
+ __IO uint32_t iocb0 : 1; /* [0] */
+ __IO uint32_t iocb1 : 1; /* [1] */
+ __IO uint32_t iocb2 : 1; /* [2] */
+ __IO uint32_t iocb3 : 1; /* [3] */
+ __IO uint32_t iocb4 : 1; /* [4] */
+ __IO uint32_t iocb5 : 1; /* [5] */
+ __IO uint32_t iocb6 : 1; /* [6] */
+ __IO uint32_t iocb7 : 1; /* [7] */
+ __IO uint32_t iocb8 : 1; /* [8] */
+ __IO uint32_t iocb9 : 1; /* [9] */
+ __IO uint32_t iocb10 : 1; /* [10] */
+ __IO uint32_t iocb11 : 1; /* [11] */
+ __IO uint32_t iocb12 : 1; /* [12] */
+ __IO uint32_t iocb13 : 1; /* [13] */
+ __IO uint32_t iocb14 : 1; /* [14] */
+ __IO uint32_t iocb15 : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } clr_bit;
+ };
+
+ /**
+ * @brief gpio togr register, offset:0x2C
+ */
+ union
+ {
+ __IO uint32_t togr;
+ struct
+ {
+ __IO uint32_t iotb0 : 1; /* [0] */
+ __IO uint32_t iotb1 : 1; /* [1] */
+ __IO uint32_t iotb2 : 1; /* [2] */
+ __IO uint32_t iotb3 : 1; /* [3] */
+ __IO uint32_t iotb4 : 1; /* [4] */
+ __IO uint32_t iotb5 : 1; /* [5] */
+ __IO uint32_t iotb6 : 1; /* [6] */
+ __IO uint32_t iotb7 : 1; /* [7] */
+ __IO uint32_t iotb8 : 1; /* [8] */
+ __IO uint32_t iotb9 : 1; /* [9] */
+ __IO uint32_t iotb10 : 1; /* [10] */
+ __IO uint32_t iotb11 : 1; /* [11] */
+ __IO uint32_t iotb12 : 1; /* [12] */
+ __IO uint32_t iotb13 : 1; /* [13] */
+ __IO uint32_t iotb14 : 1; /* [14] */
+ __IO uint32_t iotb15 : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } togr_bit;
+ };
+
+ /**
+ * @brief gpio reserved1 register, offset:0x30~0x38
+ */
+ __IO uint32_t reserved1[3];
+
+ /**
+ * @brief gpio hdrv register, offset:0x3C
+ */
+ union
+ {
+ __IO uint32_t hdrv;
+ struct
+ {
+ __IO uint32_t hdrv0 : 1; /* [0] */
+ __IO uint32_t hdrv1 : 1; /* [1] */
+ __IO uint32_t hdrv2 : 1; /* [2] */
+ __IO uint32_t hdrv3 : 1; /* [3] */
+ __IO uint32_t hdrv4 : 1; /* [4] */
+ __IO uint32_t hdrv5 : 1; /* [5] */
+ __IO uint32_t hdrv6 : 1; /* [6] */
+ __IO uint32_t hdrv7 : 1; /* [7] */
+ __IO uint32_t hdrv8 : 1; /* [8] */
+ __IO uint32_t hdrv9 : 1; /* [9] */
+ __IO uint32_t hdrv10 : 1; /* [10] */
+ __IO uint32_t hdrv11 : 1; /* [11] */
+ __IO uint32_t hdrv12 : 1; /* [12] */
+ __IO uint32_t hdrv13 : 1; /* [13] */
+ __IO uint32_t hdrv14 : 1; /* [14] */
+ __IO uint32_t hdrv15 : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } hdrv_bit;
+ };
+} gpio_type;
+
+/**
+ * @}
+ */
+
+#define GPIOA ((gpio_type *) GPIOA_BASE)
+#define GPIOB ((gpio_type *) GPIOB_BASE)
+#define GPIOC ((gpio_type *) GPIOC_BASE)
+#define GPIOD ((gpio_type *) GPIOD_BASE)
+#define GPIOE ((gpio_type *) GPIOE_BASE)
+#define GPIOF ((gpio_type *) GPIOF_BASE)
+#define GPIOG ((gpio_type *) GPIOG_BASE)
+#define GPIOH ((gpio_type *) GPIOH_BASE)
+
+/** @defgroup GPIO_exported_functions
+ * @{
+ */
+
+void gpio_reset(gpio_type *gpio_x);
+void gpio_init(gpio_type *gpio_x, gpio_init_type *gpio_init_struct);
+void gpio_default_para_init(gpio_init_type *gpio_init_struct);
+flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins);
+uint16_t gpio_input_data_read(gpio_type *gpio_x);
+flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins);
+uint16_t gpio_output_data_read(gpio_type *gpio_x);
+void gpio_bits_set(gpio_type *gpio_x, uint16_t pins);
+void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins);
+void gpio_bits_toggle(gpio_type *gpio_x, uint16_t pins);
+void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state);
+void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value);
+void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins);
+void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state);
+void gpio_pin_mux_config(gpio_type *gpio_x, gpio_pins_source_type gpio_pin_source, gpio_mux_sel_type gpio_mux);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_i2c.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_i2c.h
new file mode 100644
index 00000000000..ccf59dd1b08
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_i2c.h
@@ -0,0 +1,478 @@
+/**
+ **************************************************************************
+ * @file at32f45x_i2c.h
+ * @brief at32f45x i2c header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_I2C_H
+#define __AT32F45x_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f45x.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/**
+ * @brief maximum number of single transfers
+ */
+#define MAX_TRANSFER_CNT 255 /*!< maximum number of single transfers */
+
+/** @defgroup I2C_interrupts_definition
+ * @brief i2c interrupt
+ * @{
+ */
+
+#define I2C_TD_INT ((uint32_t)0x00000002) /*!< i2c transmit data interrupt */
+#define I2C_RD_INT ((uint32_t)0x00000004) /*!< i2c receive data interrupt */
+#define I2C_ADDR_INT ((uint32_t)0x00000008) /*!< i2c address match interrupt */
+#define I2C_ACKFIAL_INT ((uint32_t)0x00000010) /*!< i2c ack fail interrupt */
+#define I2C_STOP_INT ((uint32_t)0x00000020) /*!< i2c stop detect interrupt */
+#define I2C_TDC_INT ((uint32_t)0x00000040) /*!< i2c transmit data complete interrupt */
+#define I2C_ERR_INT ((uint32_t)0x00000080) /*!< i2c bus error interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_flags_definition
+ * @brief i2c flag
+ * @{
+ */
+
+#define I2C_TDBE_FLAG ((uint32_t)0x00000001) /*!< i2c transmit data buffer empty flag */
+#define I2C_TDIS_FLAG ((uint32_t)0x00000002) /*!< i2c send interrupt status */
+#define I2C_RDBF_FLAG ((uint32_t)0x00000004) /*!< i2c receive data buffer full flag */
+#define I2C_ADDRF_FLAG ((uint32_t)0x00000008) /*!< i2c 0~7 bit address match flag */
+#define I2C_ACKFAIL_FLAG ((uint32_t)0x00000010) /*!< i2c acknowledge failure flag */
+#define I2C_STOPF_FLAG ((uint32_t)0x00000020) /*!< i2c stop condition generation complete flag */
+#define I2C_TDC_FLAG ((uint32_t)0x00000040) /*!< i2c transmit data complete flag */
+#define I2C_TCRLD_FLAG ((uint32_t)0x00000080) /*!< i2c transmission is complete, waiting to load data */
+#define I2C_BUSERR_FLAG ((uint32_t)0x00000100) /*!< i2c bus error flag */
+#define I2C_ARLOST_FLAG ((uint32_t)0x00000200) /*!< i2c arbitration lost flag */
+#define I2C_OUF_FLAG ((uint32_t)0x00000400) /*!< i2c overflow or underflow flag */
+#define I2C_PECERR_FLAG ((uint32_t)0x00000800) /*!< i2c pec receive error flag */
+#define I2C_TMOUT_FLAG ((uint32_t)0x00001000) /*!< i2c smbus timeout flag */
+#define I2C_ALERTF_FLAG ((uint32_t)0x00002000) /*!< i2c smbus alert flag */
+#define I2C_BUSYF_FLAG ((uint32_t)0x00008000) /*!< i2c bus busy flag transmission mode */
+#define I2C_SDIR_FLAG ((uint32_t)0x00010000) /*!< i2c slave data transmit direction */
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_exported_types
+ * @{
+ */
+
+/**
+ * @brief i2c smbus mode set
+ */
+typedef enum
+{
+ I2C_SMBUS_MODE_DEVICE = 0x00, /*!< smbus device mode */
+ I2C_SMBUS_MODE_HOST = 0x01 /*!< smbus host mode */
+} i2c_smbus_mode_type;
+
+/**
+ * @brief i2c address mode
+ */
+typedef enum
+{
+ I2C_ADDRESS_MODE_7BIT = 0x00, /*!< 7bit address mode */
+ I2C_ADDRESS_MODE_10BIT = 0x01 /*!< 10bit address mode */
+} i2c_address_mode_type;
+
+/**
+ * @brief i2c transfer direction
+ */
+typedef enum
+{
+ I2C_DIR_TRANSMIT = 0x00, /*!< master request a write transfer */
+ I2C_DIR_RECEIVE = 0x01 /*!< master request a read transfer */
+} i2c_transfer_dir_type;
+
+/**
+ * @brief i2c dma requests direction
+ */
+typedef enum
+{
+ I2C_DMA_REQUEST_TX = 0x00, /*!< dma transmit request */
+ I2C_DMA_REQUEST_RX = 0x01 /*!< dma receive request */
+} i2c_dma_request_type;
+
+/**
+ * @brief i2c smbus alert pin set
+ */
+typedef enum
+{
+ I2C_SMBUS_ALERT_HIGH = 0x00, /*!< smbus alert pin set high */
+ I2C_SMBUS_ALERT_LOW = 0x01 /*!< smbus alert pin set low */
+} i2c_smbus_alert_set_type;
+
+/**
+ * @brief i2c clock timeout detection mode
+ */
+typedef enum
+{
+ I2C_TIMEOUT_DETCET_LOW = 0x00, /*!< detect low level timeout */
+ I2C_TIMEOUT_DETCET_HIGH = 0x01 /*!< detect high level timeout */
+} i2c_timeout_detcet_type;
+
+/**
+ * @brief i2c own address2 mask
+ */
+typedef enum
+{
+ I2C_ADDR2_NOMASK = 0x00, /*!< compare bit [7:1] */
+ I2C_ADDR2_MASK01 = 0x01, /*!< only compare bit [7:2] */
+ I2C_ADDR2_MASK02 = 0x02, /*!< only compare bit [7:3] */
+ I2C_ADDR2_MASK03 = 0x03, /*!< only compare bit [7:4] */
+ I2C_ADDR2_MASK04 = 0x04, /*!< only compare bit [7:5] */
+ I2C_ADDR2_MASK05 = 0x05, /*!< only compare bit [7:6] */
+ I2C_ADDR2_MASK06 = 0x06, /*!< only compare bit [7] */
+ I2C_ADDR2_MASK07 = 0x07 /*!< response all addresses other than those reserved for i2c */
+} i2c_addr2_mask_type;
+
+/**
+ * @brief i2c reload end mode
+ */
+typedef enum
+{
+ I2C_AUTO_STOP_MODE = 0x02000000, /*!< auto generate stop mode */
+ I2C_SOFT_STOP_MODE = 0x00000000, /*!< soft generate stop mode */
+ I2C_RELOAD_MODE = 0x01000000 /*!< reload mode */
+} i2c_reload_stop_mode_type;
+
+/**
+ * @brief i2c start mode
+ */
+typedef enum
+{
+ I2C_WITHOUT_START = 0x00000000, /*!< transfer data without start condition */
+ I2C_GEN_START_READ = 0x00002400, /*!< read data and generate start */
+ I2C_GEN_START_WRITE = 0x00002000 /*!< send data and generate start */
+} i2c_start_mode_type;
+
+/**
+ * @brief type define i2c register all
+ */
+typedef struct
+{
+ /**
+ * @brief i2c ctrl1 register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t ctrl1;
+ struct
+ {
+ __IO uint32_t i2cen : 1; /* [0] */
+ __IO uint32_t tdien : 1; /* [1] */
+ __IO uint32_t rdien : 1; /* [2] */
+ __IO uint32_t addrien : 1; /* [3] */
+ __IO uint32_t ackfailien : 1; /* [4] */
+ __IO uint32_t stopien : 1; /* [5] */
+ __IO uint32_t tdcien : 1; /* [6] */
+ __IO uint32_t errien : 1; /* [7] */
+ __IO uint32_t dflt : 4; /* [11:8] */
+ __IO uint32_t reserved1 : 2; /* [13:12] */
+ __IO uint32_t dmaten : 1; /* [14] */
+ __IO uint32_t dmaren : 1; /* [15] */
+ __IO uint32_t sctrl : 1; /* [16] */
+ __IO uint32_t stretch : 1; /* [17] */
+ __IO uint32_t reserved2 : 1; /* [18] */
+ __IO uint32_t gcaen : 1; /* [19] */
+ __IO uint32_t haddren : 1; /* [20] */
+ __IO uint32_t devaddren : 1; /* [21] */
+ __IO uint32_t smbalert : 1; /* [22] */
+ __IO uint32_t pecen : 1; /* [23] */
+ __IO uint32_t reserved3 : 8; /* [31:24] */
+ } ctrl1_bit;
+ };
+
+ /**
+ * @brief i2c ctrl2 register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t ctrl2;
+ struct
+ {
+ __IO uint32_t saddr : 10;/* [9:0] */
+ __IO uint32_t dir : 1; /* [10] */
+ __IO uint32_t addr10 : 1; /* [11] */
+ __IO uint32_t readh10 : 1; /* [12] */
+ __IO uint32_t genstart : 1; /* [13] */
+ __IO uint32_t genstop : 1; /* [14] */
+ __IO uint32_t nacken : 1; /* [15] */
+ __IO uint32_t cnt : 8; /* [23:16] */
+ __IO uint32_t rlden : 1; /* [24] */
+ __IO uint32_t astopen : 1; /* [25] */
+ __IO uint32_t pecten : 1; /* [26] */
+ __IO uint32_t reserved1 : 5; /* [31:27] */
+ } ctrl2_bit;
+ };
+
+ /**
+ * @brief i2c oaddr1 register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t oaddr1;
+ struct
+ {
+ __IO uint32_t addr1 : 10;/* [9:0] */
+ __IO uint32_t addr1mode : 1; /* [10] */
+ __IO uint32_t reserved1 : 4; /* [14:11] */
+ __IO uint32_t addr1en : 1; /* [15] */
+ __IO uint32_t reserved2 : 16;/* [31:16] */
+ } oaddr1_bit;
+ };
+
+ /**
+ * @brief i2c oaddr2 register, offset:0x0c
+ */
+ union
+ {
+ __IO uint32_t oaddr2;
+ struct
+ {
+ __IO uint32_t reserved1 : 1; /* [0] */
+ __IO uint32_t addr2 : 7; /* [7:1] */
+ __IO uint32_t addr2mask : 3; /* [10:8] */
+ __IO uint32_t reserved2 : 4; /* [14:11] */
+ __IO uint32_t addr2en : 1; /* [15] */
+ __IO uint32_t reserved3 : 16;/* [31:16] */
+ } oaddr2_bit;
+ };
+
+ /**
+ * @brief i2c clkctrl register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t clkctrl;
+ struct
+ {
+ __IO uint32_t scll : 8; /* [7:0] */
+ __IO uint32_t sclh : 8; /* [15:8] */
+ __IO uint32_t sdad : 4; /* [19:16] */
+ __IO uint32_t scld : 4; /* [23:20] */
+ __IO uint32_t divh : 4; /* [27:24] */
+ __IO uint32_t divl : 4; /* [31:28] */
+ } clkctrl_bit;
+ };
+
+ /**
+ * @brief i2c timeout register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t timeout;
+ struct
+ {
+ __IO uint32_t totime : 12;/* [11:0] */
+ __IO uint32_t tomode : 1; /* [12] */
+ __IO uint32_t reserved1 : 2; /* [14:13] */
+ __IO uint32_t toen : 1; /* [15] */
+ __IO uint32_t exttime : 12;/* [27:16] */
+ __IO uint32_t reserved2 : 3; /* [30:28] */
+ __IO uint32_t exten : 1; /* [31] */
+ } timeout_bit;
+ };
+
+ /**
+ * @brief i2c sts register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t tdbe : 1; /* [0] */
+ __IO uint32_t tdis : 1; /* [1] */
+ __IO uint32_t rdbf : 1; /* [2] */
+ __IO uint32_t addrf : 1; /* [3] */
+ __IO uint32_t ackfail : 1; /* [4] */
+ __IO uint32_t stopf : 1; /* [5] */
+ __IO uint32_t tdc : 1; /* [6] */
+ __IO uint32_t tcrld : 1; /* [7] */
+ __IO uint32_t buserr : 1; /* [8] */
+ __IO uint32_t arlost : 1; /* [9] */
+ __IO uint32_t ouf : 1; /* [10] */
+ __IO uint32_t pecerr : 1; /* [11] */
+ __IO uint32_t tmout : 1; /* [12] */
+ __IO uint32_t alertf : 1; /* [13] */
+ __IO uint32_t reserved1 : 1; /* [14] */
+ __IO uint32_t busyf : 1; /* [15] */
+ __IO uint32_t sdir : 1; /* [16] */
+ __IO uint32_t addr : 7; /* [23:17] */
+ __IO uint32_t reserved2 : 8; /* [31:24] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief i2c clr register, offset:0x1c
+ */
+ union
+ {
+ __IO uint32_t clr;
+ struct
+ {
+ __IO uint32_t reserved1 : 3; /* [2:0] */
+ __IO uint32_t addrc : 1; /* [3] */
+ __IO uint32_t ackfailc : 1; /* [4] */
+ __IO uint32_t stopc : 1; /* [5] */
+ __IO uint32_t reserved2 : 2; /* [6:7] */
+ __IO uint32_t buserrc : 1; /* [8] */
+ __IO uint32_t arlostc : 1; /* [9] */
+ __IO uint32_t oufc : 1; /* [10] */
+ __IO uint32_t pecerrc : 1; /* [11] */
+ __IO uint32_t tmoutc : 1; /* [12] */
+ __IO uint32_t alertc : 1; /* [13] */
+ __IO uint32_t reserved3 : 18;/* [31:14] */
+ } clr_bit;
+ };
+
+ /**
+ * @brief i2c pec register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t pec;
+ struct
+ {
+ __IO uint32_t pecval : 8; /* [7:0] */
+ __IO uint32_t reserved1 : 24;/* [31:8] */
+ } pec_bit;
+ };
+
+ /**
+ * @brief i2c rxdt register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t rxdt;
+ struct
+ {
+ __IO uint32_t dt : 8; /* [7:0] */
+ __IO uint32_t reserved1 : 24;/* [31:8] */
+ } rxdt_bit;
+ };
+
+ /**
+ * @brief i2c txdt register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t txdt;
+ struct
+ {
+ __IO uint32_t dt : 8; /* [7:0] */
+ __IO uint32_t reserved1 : 24;/* [31:8] */
+ } txdt_bit;
+ };
+
+} i2c_type;
+
+/**
+ * @}
+ */
+
+#define I2C1 ((i2c_type *) I2C1_BASE)
+#define I2C2 ((i2c_type *) I2C2_BASE)
+#define I2C3 ((i2c_type *) I2C3_BASE)
+
+/** @defgroup I2C_exported_functions
+ * @{
+ */
+
+void i2c_reset(i2c_type *i2c_x);
+void i2c_init(i2c_type *i2c_x, uint8_t dfilters, uint32_t clk);
+void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t address);
+void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address, i2c_addr2_mask_type mask);
+void i2c_own_address2_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_smbus_enable(i2c_type *i2c_x, i2c_smbus_mode_type mode, confirm_state new_state);
+void i2c_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_clock_stretch_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_ack_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_addr10_mode_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_transfer_addr_set(i2c_type *i2c_x, uint16_t address);
+uint16_t i2c_transfer_addr_get(i2c_type *i2c_x);
+void i2c_transfer_dir_set(i2c_type *i2c_x, i2c_transfer_dir_type i2c_direction);
+i2c_transfer_dir_type i2c_transfer_dir_get(i2c_type *i2c_x);
+uint8_t i2c_matched_addr_get(i2c_type *i2c_x);
+void i2c_auto_stop_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_reload_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_cnt_set(i2c_type *i2c_x, uint8_t cnt);
+void i2c_addr10_header_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_general_call_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_smbus_alert_set(i2c_type *i2c_x, i2c_smbus_alert_set_type level);
+void i2c_slave_data_ctrl_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_pec_calculate_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_pec_transmit_enable(i2c_type *i2c_x, confirm_state new_state);
+uint8_t i2c_pec_value_get(i2c_type *i2c_x);
+void i2c_timeout_set(i2c_type *i2c_x, uint16_t timeout);
+void i2c_timeout_detcet_set(i2c_type *i2c_x, i2c_timeout_detcet_type mode);
+void i2c_timeout_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_ext_timeout_set(i2c_type *i2c_x, uint16_t timeout);
+void i2c_ext_timeout_enable(i2c_type *i2c_x, confirm_state new_state);
+void i2c_interrupt_enable(i2c_type *i2c_x, uint32_t source, confirm_state new_state);
+flag_status i2c_interrupt_get(i2c_type *i2c_x, uint16_t source);
+void i2c_dma_enable(i2c_type *i2c_x, i2c_dma_request_type dma_req, confirm_state new_state);
+void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_mode_type start);
+void i2c_start_generate(i2c_type *i2c_x);
+void i2c_stop_generate(i2c_type *i2c_x);
+void i2c_data_send(i2c_type *i2c_x, uint8_t data);
+uint8_t i2c_data_receive(i2c_type *i2c_x);
+flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag);
+flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag);
+void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_misc.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_misc.h
new file mode 100644
index 00000000000..98bfefb6cbd
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_misc.h
@@ -0,0 +1,123 @@
+/**
+ **************************************************************************
+ * @file at32f45x_misc.h
+ * @brief at32f45x misc header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_MISC_H
+#define __AT32F45x_MISC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f45x.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @addtogroup MISC
+ * @{
+ */
+
+/** @defgroup MISC_vector_table_base_address
+ * @{
+ */
+
+#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< nvic vector table based ram address */
+#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< nvic vector table based flash address */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_exported_types
+ * @{
+ */
+
+/**
+ * @brief nvic interrupt priority group
+ */
+typedef enum
+{
+ NVIC_PRIORITY_GROUP_0 = ((uint32_t)0x7), /*!< 0 bits for preemption priority, 4 bits for subpriority */
+ NVIC_PRIORITY_GROUP_1 = ((uint32_t)0x6), /*!< 1 bits for preemption priority, 3 bits for subpriority */
+ NVIC_PRIORITY_GROUP_2 = ((uint32_t)0x5), /*!< 2 bits for preemption priority, 2 bits for subpriority */
+ NVIC_PRIORITY_GROUP_3 = ((uint32_t)0x4), /*!< 3 bits for preemption priority, 1 bits for subpriority */
+ NVIC_PRIORITY_GROUP_4 = ((uint32_t)0x3) /*!< 4 bits for preemption priority, 0 bits for subpriority */
+} nvic_priority_group_type;
+
+/**
+ * @brief nvic low power mode
+ */
+typedef enum
+{
+ NVIC_LP_SLEEPONEXIT = 0x02, /*!< send event on pending */
+ NVIC_LP_SLEEPDEEP = 0x04, /*!< enable sleep-deep output signal when entering sleep mode */
+ NVIC_LP_SEVONPEND = 0x10 /*!< enable sleep-on-exit feature */
+} nvic_lowpower_mode_type;
+
+/**
+ * @brief systick clock source
+ */
+typedef enum
+{
+ SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8 = ((uint32_t)0x00000000), /*!< systick clock source from core clock div8 */
+ SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV = ((uint32_t)0x00000004) /*!< systick clock source from core clock */
+} systick_clock_source_type;
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_exported_functions
+ * @{
+ */
+
+void nvic_system_reset(void);
+void nvic_irq_enable(IRQn_Type irqn, uint32_t preempt_priority, uint32_t sub_priority);
+void nvic_irq_disable(IRQn_Type irqn);
+void nvic_priority_group_config(nvic_priority_group_type priority_group);
+void nvic_vector_table_set(uint32_t base, uint32_t offset);
+void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state new_state);
+void systick_clock_source_config(systick_clock_source_type source);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_pwc.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_pwc.h
new file mode 100644
index 00000000000..5788b9fca4d
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_pwc.h
@@ -0,0 +1,293 @@
+/**
+ **************************************************************************
+ * @file at32f45x_pwc.h
+ * @brief at32f45x pwr header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_PWC_H
+#define __AT32F45x_PWC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f45x.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @addtogroup PWC
+ * @{
+ */
+
+/** @defgroup PWC_flags_definition
+ * @brief pwc flag
+ * @{
+ */
+
+#define PWC_WAKEUP_PIN1_FLAG ((uint32_t)0x00000001) /*!< wakeup pin1 event flag */
+#define PWC_WAKEUP_PIN2_FLAG ((uint32_t)0x00000002) /*!< wakeup pin2 event flag */
+#define PWC_WAKEUP_PIN4_FLAG ((uint32_t)0x00000008) /*!< wakeup pin4 event flag */
+#define PWC_WAKEUP_PIN5_FLAG ((uint32_t)0x00000010) /*!< wakeup pin5 event flag */
+#define PWC_WAKEUP_PIN6_FLAG ((uint32_t)0x00000020) /*!< wakeup pin6 event flag */
+#define PWC_WAKEUP_PIN7_FLAG ((uint32_t)0x00000040) /*!< wakeup pin7 event flag */
+#define PWC_STANDBY_FLAG ((uint32_t)0x00000100) /*!< standby flag */
+#define PWC_PVM_OUTPUT_FLAG ((uint32_t)0x00000200) /*!< pvm output flag */
+#define PWC_WAKEUP_INTERNAL_FLAG ((uint32_t)0x00008000) /*!< internal wakeup event flag */
+
+/**
+ * @}
+ */
+
+/**
+ * @brief pwc wakeup pin num definition
+ */
+#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00010000) /*!< standby wake-up pin1 */
+#define PWC_WAKEUP_PIN_2 ((uint32_t)0x00020000) /*!< standby wake-up pin2 */
+#define PWC_WAKEUP_PIN_4 ((uint32_t)0x00080000) /*!< standby wake-up pin4 */
+#define PWC_WAKEUP_PIN_5 ((uint32_t)0x00100000) /*!< standby wake-up pin5 */
+#define PWC_WAKEUP_PIN_6 ((uint32_t)0x00200000) /*!< standby wake-up pin6 */
+#define PWC_WAKEUP_PIN_7 ((uint32_t)0x00400000) /*!< standby wake-up pin7 */
+
+/**
+ * @brief select ldo output voltage.
+ * @param val: set the ldo output voltage.
+ * this parameter can be one of the following values:
+ * - PWC_LDO_OUTPUT_1V1: system clock up to 108MHz.
+ * - PWC_LDO_OUTPUT_1V2: system clock up to 160MHz.
+ * - PWC_LDO_OUTPUT_1V3: system clock up to 192MHz.
+ * @note none.
+ */
+#define pwc_ldo_output_voltage_set(val) (PWC->ldoov_bit.ldoovsel = val)
+
+/** @defgroup PWC_exported_types
+ * @{
+ */
+
+/**
+ * @brief pwc pvm voltage type
+ */
+typedef enum
+{
+ PWC_PVM_VOLTAGE_2V3 = 0x01, /*!< power voltage monitoring boundary 2.3v */
+ PWC_PVM_VOLTAGE_2V4 = 0x02, /*!< power voltage monitoring boundary 2.4v */
+ PWC_PVM_VOLTAGE_2V5 = 0x03, /*!< power voltage monitoring boundary 2.5v */
+ PWC_PVM_VOLTAGE_2V6 = 0x04, /*!< power voltage monitoring boundary 2.6v */
+ PWC_PVM_VOLTAGE_2V7 = 0x05, /*!< power voltage monitoring boundary 2.7v */
+ PWC_PVM_VOLTAGE_2V8 = 0x06, /*!< power voltage monitoring boundary 2.8v */
+ PWC_PVM_VOLTAGE_2V9 = 0x07 /*!< power voltage monitoring boundary 2.9v */
+} pwc_pvm_voltage_type;
+
+/**
+ * @brief pwc ldo output voltage type
+ */
+typedef enum
+{
+ PWC_LDO_OUTPUT_1V1 = 0x01, /*!< ldo output voltage is 1.1v */
+ PWC_LDO_OUTPUT_1V2 = 0x02, /*!< ldo output voltage is 1.2v */
+ PWC_LDO_OUTPUT_1V3 = 0x03 /*!< ldo output voltage is 1.3v */
+} pwc_ldo_output_voltage_type;
+
+/**
+ * @brief pwc sleep enter type
+ */
+typedef enum
+{
+ PWC_SLEEP_ENTER_WFI = 0x00, /*!< use wfi enter sleep mode */
+ PWC_SLEEP_ENTER_WFE = 0x01 /*!< use wfe enter sleep mode */
+} pwc_sleep_enter_type ;
+
+/**
+ * @brief pwc deep sleep enter type
+ */
+typedef enum
+{
+ PWC_DEEP_SLEEP_ENTER_WFI = 0x00, /*!< use wfi enter deepsleep mode */
+ PWC_DEEP_SLEEP_ENTER_WFE = 0x01 /*!< use wfe enter deepsleep mode */
+} pwc_deep_sleep_enter_type ;
+
+/**
+ * @brief pwc regulator type
+ */
+typedef enum
+{
+ PWC_REGULATOR_ON = 0x00, /*!< voltage regulator state on when deepsleep mode */
+ PWC_REGULATOR_LOW_POWER = 0x01, /*!< voltage regulator state low power when deepsleep mode */
+ PWC_REGULATOR_EXTRA_LOW_POWER = 0x02 /*!< voltage regulator state extra low power when deepsleep mode */
+} pwc_regulator_type ;
+
+/**
+ * @brief pwc wakeup pin polarity type
+ */
+typedef enum
+{
+ PWC_RISING_EDGE_WAKEUP = 0x00, /*!< standby wakeup pin's polarity is rising edge */
+ PWC_FALLING_EDGE_WAKEUP = 0x01, /*!< standby wakeup pin's polarity is falling edge */
+} pwc_wakeup_pin_polarity_type ;
+
+/**
+ * @brief type define pwc register all
+ */
+typedef struct
+{
+ /**
+ * @brief pwc ctrl register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t ctrl;
+ struct
+ {
+ __IO uint32_t vrsel : 1; /* [0] */
+ __IO uint32_t lpsel : 1; /* [1] */
+ __IO uint32_t reserved1 : 2; /* [3:2] */
+ __IO uint32_t pvmen : 1; /* [4] */
+ __IO uint32_t pvmsel : 3; /* [7:5] */
+ __IO uint32_t bpwen : 1; /* [8] */
+ __IO uint32_t reserved2 : 7; /* [15:9] */
+ __IO uint32_t swpen1 : 1; /* [16] */
+ __IO uint32_t swpen2 : 1; /* [17] */
+ __IO uint32_t reserved3 : 1; /* [18] */
+ __IO uint32_t swpen4 : 1; /* [19] */
+ __IO uint32_t swpen5 : 1; /* [20] */
+ __IO uint32_t swpen6 : 1; /* [21] */
+ __IO uint32_t swpen7 : 1; /* [22] */
+ __IO uint32_t reserved4 : 1; /* [23] */
+ __IO uint32_t swp1pol : 1; /* [24] */
+ __IO uint32_t swp2pol : 1; /* [25] */
+ __IO uint32_t reserved5 : 1; /* [26] */
+ __IO uint32_t swp4pol : 1; /* [27] */
+ __IO uint32_t swp5pol : 1; /* [28] */
+ __IO uint32_t swp6pol : 1; /* [29] */
+ __IO uint32_t swp7pol : 1; /* [30] */
+ __IO uint32_t reserved6 : 1; /* [31] */
+ } ctrl_bit;
+ };
+
+ /**
+ * @brief pwc ctrlsts register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t ctrlsts;
+ struct
+ {
+ __IO uint32_t sw1ef : 1; /* [0] */
+ __IO uint32_t sw2ef : 1; /* [1] */
+ __IO uint32_t reserved1 : 1; /* [2] */
+ __IO uint32_t sw4ef : 1; /* [3] */
+ __IO uint32_t sw5ef : 1; /* [4] */
+ __IO uint32_t sw6ef : 1; /* [5] */
+ __IO uint32_t sw7ef : 1; /* [6] */
+ __IO uint32_t reserved2 : 1; /* [7] */
+ __IO uint32_t sef : 1; /* [8] */
+ __IO uint32_t pvmof : 1; /* [9] */
+ __IO uint32_t reserved3 : 5; /* [14:10] */
+ __IO uint32_t swef : 1; /* [15] */
+ __IO uint32_t reserved4 : 16;/* [31:16] */
+ } ctrlsts_bit;
+ };
+
+ /**
+ * @brief pwc clr register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t clr;
+ struct
+ {
+ __IO uint32_t clsw1ef : 1; /* [0] */
+ __IO uint32_t clsw2ef : 1; /* [1] */
+ __IO uint32_t reserved1 : 1; /* [2] */
+ __IO uint32_t clsw4ef : 1; /* [3] */
+ __IO uint32_t clsw5ef : 1; /* [4] */
+ __IO uint32_t clsw6ef : 1; /* [5] */
+ __IO uint32_t clsw7ef : 1; /* [6] */
+ __IO uint32_t reserved2 : 1; /* [7] */
+ __IO uint32_t clsef : 1; /* [8] */
+ __IO uint32_t reserved3 : 6; /* [14:9] */
+ __IO uint32_t clswef : 1; /* [15] */
+ __IO uint32_t reserved4 : 16;/* [31:16] */
+ } clr_bit;
+ };
+
+ __IO uint32_t reserved1[1];
+
+ /**
+ * @brief pwc ldoov register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t ldoov;
+ struct
+ {
+ __IO uint32_t ldoovsel : 2; /* [1:0] */
+ __IO uint32_t reserved1 : 2; /* [3:2] */
+ __IO uint32_t vrexlpen : 1; /* [4] */
+ __IO uint32_t reserved2 : 27;/* [31:5] */
+ } ldoov_bit;
+ };
+} pwc_type;
+
+/**
+ * @}
+ */
+
+#define PWC ((pwc_type *) PWC_BASE)
+
+/** @defgroup PWC_exported_functions
+ * @{
+ */
+
+void pwc_reset(void);
+void pwc_battery_powered_domain_access(confirm_state new_state);
+void pwc_pvm_level_select(pwc_pvm_voltage_type pvm_voltage);
+void pwc_power_voltage_monitor_enable(confirm_state new_state);
+void pwc_wakeup_pin_polarity_select(uint32_t pin_num, pwc_wakeup_pin_polarity_type wakeup_pin_polarity);
+void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state);
+void pwc_flag_clear(uint32_t pwc_flag);
+flag_status pwc_flag_get(uint32_t pwc_flag);
+void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter);
+void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter);
+void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator);
+void pwc_standby_mode_enter(void);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_qspi.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_qspi.h
new file mode 100644
index 00000000000..03fee1cefe1
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_qspi.h
@@ -0,0 +1,563 @@
+/**
+ **************************************************************************
+ * @file at32f45x_qspi.h
+ * @brief at32f45x qspi header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_QSPI_H
+#define __AT32F45x_QSPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f45x.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @addtogroup QSPI
+ * @{
+ */
+
+/** @defgroup QSPI_flags_definition
+ * @brief qspi flag
+ * @{
+ */
+
+#define QSPI_CMDSTS_FLAG ((uint32_t)0x00000001) /*!< qspi command complete status flag */
+#define QSPI_RXFIFORDY_FLAG ((uint32_t)0x00000002) /*!< qspi rxfifo ready status flag */
+#define QSPI_TXFIFORDY_FLAG ((uint32_t)0x00000004) /*!< qspi txfifo ready status flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup QSPI_exported_types
+ * @{
+ */
+
+/**
+ * @brief qspi xip read access mode type
+ */
+typedef enum
+{
+ QSPI_XIPR_SEL_MODED = 0x00, /*!< qspi xip read select mode d */
+ QSPI_XIPR_SEL_MODET = 0x01 /*!< qspi xip read select mode t */
+} qspi_xip_read_sel_type;
+
+/**
+ * @brief qspi xip write access mode type
+ */
+typedef enum
+{
+ QSPI_XIPW_SEL_MODED = 0x00, /*!< qspi xip write select mode d */
+ QSPI_XIPW_SEL_MODET = 0x01 /*!< qspi xip write select mode t */
+} qspi_xip_write_sel_type;
+
+/**
+ * @brief qspi busy bit offset position in status register type
+ */
+typedef enum
+{
+ QSPI_BUSY_OFFSET_0 = 0x00, /*!< qspi busy bit offset position 0 */
+ QSPI_BUSY_OFFSET_1 = 0x01, /*!< qspi busy bit offset position 1 */
+ QSPI_BUSY_OFFSET_2 = 0x02, /*!< qspi busy bit offset position 2 */
+ QSPI_BUSY_OFFSET_3 = 0x03, /*!< qspi busy bit offset position 3 */
+ QSPI_BUSY_OFFSET_4 = 0x04, /*!< qspi busy bit offset position 4 */
+ QSPI_BUSY_OFFSET_5 = 0x05, /*!< qspi busy bit offset position 5 */
+ QSPI_BUSY_OFFSET_6 = 0x06, /*!< qspi busy bit offset position 6 */
+ QSPI_BUSY_OFFSET_7 = 0x07 /*!< qspi busy bit offset position 7 */
+} qspi_busy_pos_type;
+
+/**
+ * @brief qspi read status configure type
+ */
+typedef enum
+{
+ QSPI_RSTSC_HW_AUTO = 0x00, /*!< qspi read status by hardware */
+ QSPI_RSTSC_SW_ONCE = 0x01 /*!< qspi read status by software */
+} qspi_read_status_conf_type;
+
+/**
+ * @brief qspi operate mode type
+ */
+typedef enum
+{
+ QSPI_OPERATE_MODE_111 = 0x00, /*!< qspi serial mode */
+ QSPI_OPERATE_MODE_112 = 0x01, /*!< qspi dual mode */
+ QSPI_OPERATE_MODE_114 = 0x02, /*!< qspi quad mode */
+ QSPI_OPERATE_MODE_122 = 0x03, /*!< qspi dual i/o mode */
+ QSPI_OPERATE_MODE_144 = 0x04, /*!< qspi quad i/o mode */
+ QSPI_OPERATE_MODE_222 = 0x05, /*!< qspi instruction 2-bit mode */
+ QSPI_OPERATE_MODE_444 = 0x06 /*!< qspi instruction 4-bit mode(qpi) */
+} qspi_operate_mode_type;
+
+/**
+ * @brief qspi clock division type
+ */
+typedef enum
+{
+ QSPI_CLK_DIV_1 = 0x08, /*!< qspi clk divide by 1 */
+ QSPI_CLK_DIV_2 = 0x00, /*!< qspi clk divide by 2 */
+ QSPI_CLK_DIV_3 = 0x04, /*!< qspi clk divide by 3 */
+ QSPI_CLK_DIV_4 = 0x01, /*!< qspi clk divide by 4 */
+ QSPI_CLK_DIV_5 = 0x05, /*!< qspi clk divide by 5 */
+ QSPI_CLK_DIV_6 = 0x02, /*!< qspi clk divide by 6 */
+ QSPI_CLK_DIV_8 = 0x03, /*!< qspi clk divide by 8 */
+ QSPI_CLK_DIV_10 = 0x06, /*!< qspi clk divide by 10 */
+ QSPI_CLK_DIV_12 = 0x07 /*!< qspi clk divide by 12 */
+} qspi_clk_div_type;
+
+/**
+ * @brief qspi command port address length type
+ */
+typedef enum
+{
+ QSPI_CMD_ADRLEN_0_BYTE = 0x00, /*!< qspi no address */
+ QSPI_CMD_ADRLEN_1_BYTE = 0x01, /*!< qspi address length 1 byte */
+ QSPI_CMD_ADRLEN_2_BYTE = 0x02, /*!< qspi address length 2 byte */
+ QSPI_CMD_ADRLEN_3_BYTE = 0x03, /*!< qspi address length 3 byte */
+ QSPI_CMD_ADRLEN_4_BYTE = 0x04 /*!< qspi address length 4 byte */
+} qspi_cmd_adrlen_type;
+
+/**
+ * @brief qspi command port instruction length type
+ */
+typedef enum
+{
+ QSPI_CMD_INSLEN_0_BYTE = 0x00, /*!< qspi no instruction code */
+ QSPI_CMD_INSLEN_1_BYTE = 0x01, /*!< qspi instruction code 1 byte */
+ QSPI_CMD_INSLEN_2_BYTE = 0x02 /*!< qspi instruction code 2 byte(repeat) */
+} qspi_cmd_inslen_type;
+
+/**
+ * @brief qspi xip r/w address length type
+ */
+typedef enum
+{
+ QSPI_XIP_ADDRLEN_3_BYTE = 0x00, /*!< qspi xip address length 3 byte */
+ QSPI_XIP_ADDRLEN_4_BYTE = 0x01 /*!< qspi xip address length 4 byte */
+} qspi_xip_addrlen_type;
+
+/**
+ * @brief qspi sckout mode type
+ */
+typedef enum
+{
+ QSPI_SCK_MODE_0 = 0x00, /*!< qspi sck mode 0 */
+ QSPI_SCK_MODE_3 = 0x01 /*!< qspi sck mode 3 */
+} qspi_clk_mode_type;
+
+/**
+ * @brief qspi dma tx/rx fifo threshold type
+ */
+typedef enum
+{
+ QSPI_DMA_FIFO_THOD_WORD08 = 0x00, /*!< qspi dma fifo threshold 8 words */
+ QSPI_DMA_FIFO_THOD_WORD16 = 0x01, /*!< qspi dma fifo threshold 16 words */
+ QSPI_DMA_FIFO_THOD_WORD24 = 0x02 /*!< qspi dma fifo threshold 24 words */
+} qspi_dma_fifo_thod_type;
+
+/**
+ * @brief qspi cmd type
+ */
+typedef struct
+{
+ confirm_state pe_mode_enable; /*!< performance enhance mode enable */
+ uint8_t pe_mode_operate_code; /*!< performance enhance mode operate code */
+ uint8_t instruction_code; /*!< instruction code */
+ qspi_cmd_inslen_type instruction_length; /*!< instruction code length */
+ uint32_t address_code; /*!< address code */
+ qspi_cmd_adrlen_type address_length; /*!< address legnth */
+ uint32_t data_counter; /*!< read/write data counter */
+ uint8_t second_dummy_cycle_num; /*!< number of second dummy state cycle 0~32 */
+ qspi_operate_mode_type operation_mode; /*!< operation mode */
+ qspi_read_status_conf_type read_status_config; /*!< config to read status */
+ confirm_state read_status_enable; /*!< enable to read status */
+ confirm_state write_data_enable; /*!< enable to write data */
+} qspi_cmd_type;
+
+/**
+ * @brief qspi xip type
+ */
+typedef struct
+{
+ uint8_t read_instruction_code; /*!< read instruction code */
+ qspi_xip_addrlen_type read_address_length; /*!< read address legnth */
+ qspi_operate_mode_type read_operation_mode; /*!< read operation mode */
+ uint8_t read_second_dummy_cycle_num; /*!< read number of second dummy state cycle 0~32 */
+ uint8_t write_instruction_code; /*!< write instruction code */
+ qspi_xip_addrlen_type write_address_length; /*!< write address legnth */
+ qspi_operate_mode_type write_operation_mode; /*!< write operation mode */
+ uint8_t write_second_dummy_cycle_num; /*!< write number of second dummy state cycle 0~32 */
+ qspi_xip_write_sel_type write_select_mode; /*!< write mode d or mode t selection */
+ uint8_t write_time_counter; /*!< write count for mode t */
+ uint8_t write_data_counter; /*!< write count for mode d */
+ qspi_xip_read_sel_type read_select_mode; /*!< read mode d or mode t selection */
+ uint8_t read_time_counter; /*!< read count for mode t */
+ uint8_t read_data_counter; /*!< read count for mode d */
+} qspi_xip_type;
+
+/**
+ * @brief type define qspi register all
+ */
+typedef struct
+{
+ /**
+ * @brief qspi cmd_w0 register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t cmd_w0;
+ struct
+ {
+
+ __IO uint32_t spiadr : 32;/* [31:0] */
+ } cmd_w0_bit;
+ };
+
+ /**
+ * @brief qspi cmd_w1 register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t cmd_w1;
+ struct
+ {
+ __IO uint32_t adrlen : 3; /* [2:0] */
+ __IO uint32_t reserved1 : 13;/* [15:3] */
+ __IO uint32_t dum2 : 8; /* [23:16] */
+ __IO uint32_t inslen : 2; /* [25:24] */
+ __IO uint32_t reserved2 : 2; /* [27:26] */
+ __IO uint32_t pemen : 1; /* [28] */
+ __IO uint32_t reserved3 : 3; /* [31:29] */
+ } cmd_w1_bit;
+ };
+
+ /**
+ * @brief qspi cmd_w2 register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t cmd_w2;
+ struct
+ {
+ __IO uint32_t dcnt : 32;/* [31:0] */
+ } cmd_w2_bit;
+ };
+
+ /**
+ * @brief qspi cmd_w3 register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t cmd_w3;
+ struct
+ {
+ __IO uint32_t reserved1 : 1; /* [0] */
+ __IO uint32_t wen : 1; /* [1] */
+ __IO uint32_t rstsen : 1; /* [2] */
+ __IO uint32_t rstsc : 1; /* [3] */
+ __IO uint32_t reserved2 : 1; /* [4] */
+ __IO uint32_t opmode : 3; /* [7:5] */
+ __IO uint32_t reserved3 : 8; /* [15:8] */
+ __IO uint32_t pemopc : 8; /* [23:16] */
+ __IO uint32_t insc : 8; /* [31:24] */
+ } cmd_w3_bit;
+ };
+
+ /**
+ * @brief qspi ctrl register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t ctrl;
+ struct
+ {
+ __IO uint32_t clkdiv : 3; /* [2:0] */
+ __IO uint32_t reserved1 : 1; /* [3] */
+ __IO uint32_t sckmode : 1; /* [4] */
+ __IO uint32_t reserved2 : 2; /* [6:5] */
+ __IO uint32_t xipidle : 1; /* [7] */
+ __IO uint32_t abort : 1; /* [8] */
+ __IO uint32_t reserved3 : 7; /* [15:9] */
+ __IO uint32_t busy : 3; /* [18:16] */
+ __IO uint32_t xiprcmdf : 1; /* [19] */
+ __IO uint32_t xipsel : 1; /* [20] */
+ __IO uint32_t keyen : 1; /* [21] */
+ __IO uint32_t reserved4 : 10;/* [31:22] */
+ } ctrl_bit;
+ };
+
+ /**
+ * @brief qspi register, offset:0x14
+ */
+ __IO uint32_t reserved0;
+
+ /**
+ * @brief qspi fifosts register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t fifosts;
+ struct
+ {
+ __IO uint32_t txfifordy : 1; /* [0] */
+ __IO uint32_t rxfifordy : 1; /* [1] */
+ __IO uint32_t reserved1 : 30;/* [31:2] */
+ } fifosts_bit;
+ };
+
+ /**
+ * @brief qspi reserved register, offset:0x1C
+ */
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief qspi ctrl2 register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t ctrl2;
+ struct
+ {
+ __IO uint32_t dmaen : 1; /* [0] */
+ __IO uint32_t cmdie : 1; /* [1] */
+ __IO uint32_t reserved1 : 6; /* [7:2] */
+ __IO uint32_t txfifo_thod : 2; /* [9:8] */
+ __IO uint32_t reserved2 : 2; /* [11:10] */
+ __IO uint32_t rxfifo_thod : 2; /* [13:12] */
+ __IO uint32_t reserved3 : 18;/* [31:14] */
+ } ctrl2_bit;
+ };
+
+ /**
+ * @brief qspi cmdsts register, offset:0x24
+ */
+ union
+ {
+ __IO uint32_t cmdsts;
+ struct
+ {
+ __IO uint32_t cmdsts : 1; /* [0] */
+ __IO uint32_t reserved1 : 31;/* [31:1] */
+ } cmdsts_bit;
+ };
+
+ /**
+ * @brief qspi rsts register, offset:0x28
+ */
+ union
+ {
+ __IO uint32_t rsts;
+ struct
+ {
+ __IO uint32_t spists : 8; /* [7:0] */
+ __IO uint32_t reserved1 : 24;/* [31:8] */
+ } rsts_bit;
+ };
+
+ /**
+ * @brief qspi fsize register, offset:0x2C
+ */
+ union
+ {
+ __IO uint32_t fsize;
+ struct
+ {
+ __IO uint32_t spifsize : 32;/* [31:0] */
+ } fsize_bit;
+ };
+
+ /**
+ * @brief qspi xip_cmd_w0 register, offset:0x30
+ */
+ union
+ {
+ __IO uint32_t xip_cmd_w0;
+ struct
+ {
+ __IO uint32_t xipr_dum2 : 8; /* [7:0] */
+ __IO uint32_t xipr_opmode : 3; /* [10:8] */
+ __IO uint32_t xipr_adrlen : 1; /* [11] */
+ __IO uint32_t xipr_insc : 8; /* [19:12] */
+ __IO uint32_t reserved1 : 12;/* [31:20] */
+ } xip_cmd_w0_bit;
+ };
+
+ /**
+ * @brief qspi xip_cmd_w1 register, offset:0x34
+ */
+ union
+ {
+ __IO uint32_t xip_cmd_w1;
+ struct
+ {
+ __IO uint32_t xipr_dum2 : 8; /* [7:0] */
+ __IO uint32_t xipr_opmode : 3; /* [10:8] */
+ __IO uint32_t xipr_adrlen : 1; /* [11] */
+ __IO uint32_t xipr_insc : 8; /* [19:12] */
+ __IO uint32_t reserved1 : 12;/* [31:20] */
+ } xip_cmd_w1_bit;
+ };
+
+ /**
+ * @brief qspi xip_cmd_w2 register, offset:0x38
+ */
+ union
+ {
+ __IO uint32_t xip_cmd_w2;
+ struct
+ {
+ __IO uint32_t xipr_dcnt : 5; /* [4:0] */
+ __IO uint32_t reserved1 : 3; /* [7:5] */
+ __IO uint32_t xipr_tcnt : 7; /* [14:8] */
+ __IO uint32_t xipr_sel : 1; /* [15] */
+ __IO uint32_t xipw_dcnt : 5; /* [20:16] */
+ __IO uint32_t reserved2 : 3; /* [23:21] */
+ __IO uint32_t xipw_tcnt : 7; /* [30:24] */
+ __IO uint32_t xipw_sel : 1; /* [31] */
+ } xip_cmd_w2_bit;
+ };
+
+ /**
+ * @brief qspi xip_cmd_w3 register, offset:0x3C
+ */
+ union
+ {
+ __IO uint32_t xip_cmd_w3;
+ struct
+ {
+ __IO uint32_t bypassc : 1; /* [0] */
+ __IO uint32_t reserved1 : 2; /* [2:1] */
+ __IO uint32_t csts : 1; /* [3] */
+ __IO uint32_t reserved2 : 28;/* [31:4] */
+ } xip_cmd_w3_bit;
+ };
+
+ /**
+ * @brief qspi ctrl3 register, offset:0x40
+ */
+ union
+ {
+ __IO uint32_t ctrl3;
+ struct
+ {
+ __IO uint32_t ispd : 6; /* [5:0] */
+ __IO uint32_t reserved1 : 2; /* [7:6] */
+ __IO uint32_t ispc : 1; /* [8] */
+ __IO uint32_t reserved2 : 23;/* [31:9] */
+ } ctrl3_bit;
+ };
+
+ /**
+ * @brief qspi reserved register, offset:0x44~4C
+ */
+ __IO uint32_t reserved2[3];
+
+ /**
+ * @brief qspi rev register, offset:0x50
+ */
+ union
+ {
+ __IO uint32_t rev;
+ struct
+ {
+ __IO uint32_t rev : 32;/* [31:0] */
+ } rev_bit;
+ };
+
+ /**
+ * @brief qspi reserved register, offset:0x54~FC
+ */
+ __IO uint32_t reserved3[43];
+
+ /**
+ * @brief qspi dt register, offset:0x100
+ */
+ union
+ {
+ __IO uint8_t dt_u8;
+ __IO uint16_t dt_u16;
+ __IO uint32_t dt;
+ struct
+ {
+ __IO uint32_t dt : 32;/* [31:0] */
+ } dt_bit;
+ };
+
+} qspi_type;
+
+/**
+ * @}
+ */
+
+#define QSPI1 ((qspi_type*)QSPI1_REG_BASE)
+
+/** @defgroup QSPI_exported_functions
+ * @{
+ */
+
+void qspi_reset(qspi_type* qspi_x);
+void qspi_encryption_enable(qspi_type* qspi_x, confirm_state new_state);
+void qspi_sck_mode_set(qspi_type* qspi_x, qspi_clk_mode_type new_mode);
+void qspi_clk_division_set(qspi_type* qspi_x, qspi_clk_div_type new_clkdiv);
+void qspi_xip_cache_bypass_set(qspi_type* qspi_x, confirm_state new_state);
+void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state);
+flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag);
+flag_status qspi_interrupt_flag_get(qspi_type* qspi_x, uint32_t flag);
+void qspi_flag_clear(qspi_type* qspi_x, uint32_t flag);
+void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold);
+void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold);
+void qspi_dma_enable(qspi_type* qspi_x, confirm_state new_state);
+void qspi_busy_config(qspi_type* qspi_x, qspi_busy_pos_type busy_pos);
+void qspi_xip_enable(qspi_type* qspi_x, confirm_state new_state);
+void qspi_cmd_operation_kick(qspi_type* qspi_x, qspi_cmd_type* qspi_cmd_struct);
+void qspi_xip_init(qspi_type* qspi_x, qspi_xip_type* xip_init_struct);
+uint8_t qspi_byte_read(qspi_type* qspi_x);
+uint16_t qspi_half_word_read(qspi_type* qspi_x);
+uint32_t qspi_word_read(qspi_type* qspi_x);
+void qspi_word_write(qspi_type* qspi_x, uint32_t value);
+void qspi_half_word_write(qspi_type* qspi_x, uint16_t value);
+void qspi_byte_write(qspi_type* qspi_x, uint8_t value);
+void qspi_auto_ispc_enable(qspi_type* qspi_x);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_scfg.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_scfg.h
new file mode 100644
index 00000000000..6618abdd882
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_scfg.h
@@ -0,0 +1,352 @@
+/**
+ **************************************************************************
+ * @file at32f45x_scfg.h
+ * @brief at32f45x system config header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_SCFG_H
+#define __AT32F45x_SCFG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f45x.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @addtogroup SCFG
+ * @{
+ */
+
+#define SCFG_REG(value) PERIPH_REG(SCFG_BASE, value)
+#define SCFG_REG_BIT(value) PERIPH_REG_BIT(value)
+
+/** @defgroup SCFG_exported_types
+ * @{
+ */
+
+/**
+ * @brief scfg xmc addres mapping swap type
+ */
+typedef enum
+{
+ SCFG_XMC_SWAP_NONE = 0x00, /* no swap */
+ SCFG_XMC_SWAP_MODE1 = 0x01 /* sdram 0x60000000 and 0x70000000, nor psram sram nand2 0xC00000000 and 0xD0000000 */
+} scfg_xmc_swap_type;
+
+/**
+ * @brief scfg qspi addres mapping swap type
+ */
+typedef enum
+{
+ SCFG_QSPI_SWAP_NONE = 0x00, /* no swap */
+ SCFG_QSPI_SWAP_MODE1 = 0x01 /* qspi 0x09000000 - 0x18FFFFFF */
+} scfg_qspi_swap_type;
+
+/**
+ * @brief scfg infrared modulation signal source selecting type
+ */
+typedef enum
+{
+ SCFG_IR_SOURCE_TMR10 = 0x00 /* infrared signal source select tmr10 */
+} scfg_ir_source_type;
+
+/**
+ * @brief scfg infrared output polarity selecting type
+ */
+typedef enum
+{
+ SCFG_IR_POLARITY_NO_AFFECTE = 0x00, /* infrared output polarity no affecte */
+ SCFG_IR_POLARITY_REVERSE = 0x01 /* infrared output polarity reverse */
+} scfg_ir_polarity_type;
+
+/**
+ * @brief scfg memory address mapping selecting type
+ */
+typedef enum
+{
+ SCFG_MEM_MAP_MAIN_MEMORY = 0x00, /* 0x00000000 address mapping from main memory */
+ SCFG_MEM_MAP_BOOT_MEMORY = 0x01, /* 0x00000000 address mapping from boot memory */
+ SCFG_MEM_MAP_INTERNAL_SRAM = 0x03 /* 0x00000000 address mapping from internal sram */
+} scfg_mem_map_type;
+
+/**
+ * @brief scfg can timestamp counting source type
+ */
+typedef enum
+{
+ SCFG_CAN_TIMESTAMP_TMR3 = 0x00, /* can timestamp counting source select tmr3 */
+ SCFG_CAN_TIMESTAMP_TMR5 = 0x01 /* can timestamp counting source select tmr5 */
+} scfg_can_timestamp_source_type;
+
+/**
+ * @brief scfg can index
+ */
+typedef enum
+{
+ SCFG_CAN1 = 0x00, /* can1 */
+ SCFG_CAN2 = 0x01, /* can2 */
+ SCFG_CAN3 = 0x02 /* can3 */
+} scfg_can_type;
+
+/**
+ * @brief scfg pin source type
+ */
+typedef enum
+{
+ SCFG_PINS_SOURCE0 = 0x00,
+ SCFG_PINS_SOURCE1 = 0x01,
+ SCFG_PINS_SOURCE2 = 0x02,
+ SCFG_PINS_SOURCE3 = 0x03,
+ SCFG_PINS_SOURCE4 = 0x04,
+ SCFG_PINS_SOURCE5 = 0x05,
+ SCFG_PINS_SOURCE6 = 0x06,
+ SCFG_PINS_SOURCE7 = 0x07,
+ SCFG_PINS_SOURCE8 = 0x08,
+ SCFG_PINS_SOURCE9 = 0x09,
+ SCFG_PINS_SOURCE10 = 0x0A,
+ SCFG_PINS_SOURCE11 = 0x0B,
+ SCFG_PINS_SOURCE12 = 0x0C,
+ SCFG_PINS_SOURCE13 = 0x0D,
+ SCFG_PINS_SOURCE14 = 0x0E,
+ SCFG_PINS_SOURCE15 = 0x0F
+} scfg_pins_source_type;
+
+/**
+ * @brief gpio port source type
+ */
+typedef enum
+{
+ SCFG_PORT_SOURCE_GPIOA = 0x00,
+ SCFG_PORT_SOURCE_GPIOB = 0x01,
+ SCFG_PORT_SOURCE_GPIOC = 0x02,
+ SCFG_PORT_SOURCE_GPIOD = 0x03,
+ SCFG_PORT_SOURCE_GPIOE = 0x04,
+ SCFG_PORT_SOURCE_GPIOF = 0x05,
+ SCFG_PORT_SOURCE_GPIOG = 0x06,
+ SCFG_PORT_SOURCE_GPIOH = 0x07
+} scfg_port_source_type;
+
+/**
+ * @brief scfg emac interface selecting type
+ */
+typedef enum
+{
+ SCFG_EMAC_SELECT_MII = 0x00, /* emac interface select mii mode */
+ SCFG_EMAC_SELECT_RMII = 0x01 /* emac interface select rmii mode */
+} scfg_emac_interface_type;
+
+/**
+ * @brief scfg ultra high sourcing/sinking strength pins type
+ */
+typedef enum
+{
+ SCFG_ULTRA_DRIVEN_PB9 = MAKE_VALUE(0x2C, 0),
+ SCFG_ULTRA_DRIVEN_PB8 = MAKE_VALUE(0x2C, 1),
+ SCFG_ULTRA_DRIVEN_PD12 = MAKE_VALUE(0x2C, 2),
+ SCFG_ULTRA_DRIVEN_PD13 = MAKE_VALUE(0x2C, 3),
+ SCFG_ULTRA_DRIVEN_PD14 = MAKE_VALUE(0x2C, 4),
+ SCFG_ULTRA_DRIVEN_PD15 = MAKE_VALUE(0x2C, 5)
+} scfg_ultra_driven_pins_type;
+
+/**
+ * @brief type define system config register all
+ */
+typedef struct
+{
+ /**
+ * @brief scfg cfg1 register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t cfg1;
+ struct
+ {
+ __IO uint32_t mem_map_sel : 2; /* [1:0] */
+ __IO uint32_t reserved1 : 3; /* [4:2] */
+ __IO uint32_t ir_pol : 1; /* [5] */
+ __IO uint32_t ir_src_sel : 2; /* [7:6] */
+ __IO uint32_t reserved2 : 2; /* [9:8] */
+ __IO uint32_t swap_xmc : 1; /* [10] */
+ __IO uint32_t reserved3 : 1; /* [11] */
+ __IO uint32_t swap_qspi : 1; /* [12] */
+ __IO uint32_t reserved4 : 19;/* [31:13] */
+ } cfg1_bit;
+ };
+
+ /**
+ * @brief scfg cfg2 register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t cfg2;
+ struct
+ {
+ __IO uint32_t lockup_lk : 1; /* [0] */
+ __IO uint32_t sram_operr_lk : 1; /* [1] */
+ __IO uint32_t pvm_lk : 1; /* [2] */
+ __IO uint32_t reserved1 : 5; /* [7:3] */
+ __IO uint32_t sram_operr_sts : 1; /* [8] */
+ __IO uint32_t reserved2 : 14;/* [22:9] */
+ __IO uint32_t mii_rmii_sel : 1; /* [23] */
+ __IO uint32_t can1_tst_sel : 1; /* [24] */
+ __IO uint32_t can2_tst_sel : 1; /* [25] */
+ __IO uint32_t can3_tst_sel : 1; /* [26] */
+ __IO uint32_t reserved3 : 5; /* [31:27] */
+ } cfg2_bit;
+ };
+
+ /**
+ * @brief scfg exintc1 register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t exintc1;
+ struct
+ {
+ __IO uint32_t exint0 : 4; /* [3:0] */
+ __IO uint32_t exint1 : 4; /* [7:4] */
+ __IO uint32_t exint2 : 4; /* [11:8] */
+ __IO uint32_t exint3 : 4; /* [15:12] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } exintc1_bit;
+ };
+
+ /**
+ * @brief scfg exintc2 register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t exintc2;
+ struct
+ {
+ __IO uint32_t exint4 : 4; /* [3:0] */
+ __IO uint32_t exint5 : 4; /* [7:4] */
+ __IO uint32_t exint6 : 4; /* [11:8] */
+ __IO uint32_t exint7 : 4; /* [15:12] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } exintc2_bit;
+ };
+
+ /**
+ * @brief scfg exintc3 register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t exintc3;
+ struct
+ {
+ __IO uint32_t exint8 : 4; /* [3:0] */
+ __IO uint32_t exint9 : 4; /* [7:4] */
+ __IO uint32_t exint10 : 4; /* [11:8] */
+ __IO uint32_t exint11 : 4; /* [15:12] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } exintc3_bit;
+ };
+
+ /**
+ * @brief scfg exintc4 register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t exintc4;
+ struct
+ {
+ __IO uint32_t exint12 : 4; /* [3:0] */
+ __IO uint32_t exint13 : 4; /* [7:4] */
+ __IO uint32_t exint14 : 4; /* [11:8] */
+ __IO uint32_t exint15 : 4; /* [15:12] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } exintc4_bit;
+ };
+
+ /**
+ * @brief crm reserved1 register, offset:0x18~0x28
+ */
+ __IO uint32_t reserved1[5];
+
+ /**
+ * @brief scfg uhdrv register, offset:0x2C
+ */
+ union
+ {
+ __IO uint32_t uhdrv;
+ struct
+ {
+ __IO uint32_t pb8_uh : 1; /* [0] */
+ __IO uint32_t pb9_uh : 1; /* [1] */
+ __IO uint32_t pd12_uh : 1; /* [2] */
+ __IO uint32_t pd13_uh : 1; /* [3] */
+ __IO uint32_t pd14_uh : 1; /* [4] */
+ __IO uint32_t pd15_uh : 1; /* [5] */
+ __IO uint32_t reserved1 : 26;/* [31:6] */
+ } uhdrv_bit;
+ };
+
+} scfg_type;
+
+/**
+ * @}
+ */
+
+#define SCFG ((scfg_type *) SCFG_BASE)
+
+/** @defgroup SCFG_exported_functions
+ * @{
+ */
+
+void scfg_reset(void);
+void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type polarity);
+scfg_mem_map_type scfg_mem_map_get(void);
+void scfg_xmc_mapping_swap_set(scfg_xmc_swap_type xmc_swap);
+void scfg_qspi_mapping_swap_set(scfg_qspi_swap_type qspi_swap);
+flag_status scfg_sram_operr_status_get(void);
+void scfg_sram_operr_lock_enable(confirm_state new_state);
+void scfg_lockup_enable(confirm_state new_state);
+void scfg_pvm_lock_enable(confirm_state new_state);
+void scfg_can_timestamp_source_set(scfg_can_type can_index, scfg_can_timestamp_source_type source);
+void scfg_emac_interface_set(scfg_emac_interface_type mode);
+void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source);
+void scfg_pins_ultra_driven_enable(scfg_ultra_driven_pins_type value, confirm_state new_state);
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_sdio.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_sdio.h
new file mode 100644
index 00000000000..79f2ec419a4
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_sdio.h
@@ -0,0 +1,623 @@
+/**
+ **************************************************************************
+ * @file at32f45x_sdio.h
+ * @brief at32f45x sdio header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_SDIO_H
+#define __AT32F45x_SDIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f45x.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @addtogroup SDIO
+ * @{
+ */
+
+/** @defgroup SDIO_interrupts_definition
+ * @brief sdio interrupt
+ * @{
+ */
+
+#define SDIO_CMDFAIL_INT ((uint32_t)0x00000001) /*!< command response received check failed interrupt */
+#define SDIO_DTFAIL_INT ((uint32_t)0x00000002) /*!< data block sent/received check failed interrupt */
+#define SDIO_CMDTIMEOUT_INT ((uint32_t)0x00000004) /*!< command response timerout interrupt */
+#define SDIO_DTTIMEOUT_INT ((uint32_t)0x00000008) /*!< data timeout interrupt */
+#define SDIO_TXERRU_INT ((uint32_t)0x00000010) /*!< transmit underrun error interrupt */
+#define SDIO_RXERRO_INT ((uint32_t)0x00000020) /*!< received overrun error interrupt */
+#define SDIO_CMDRSPCMPL_INT ((uint32_t)0x00000040) /*!< command response received interrupt */
+#define SDIO_CMDCMPL_INT ((uint32_t)0x00000080) /*!< command sent interrupt */
+#define SDIO_DTCMP_INT ((uint32_t)0x00000100) /*!< data sent interrupt */
+#define SDIO_SBITERR_INT ((uint32_t)0x00000200) /*!< start bit not detected on data bus interrupt */
+#define SDIO_DTBLKCMPL_INT ((uint32_t)0x00000400) /*!< data block sent/received interrupt */
+#define SDIO_DOCMD_INT ((uint32_t)0x00000800) /*!< command transfer in progress interrupt */
+#define SDIO_DOTX_INT ((uint32_t)0x00001000) /*!< data transmit in progress interrupt */
+#define SDIO_DORX_INT ((uint32_t)0x00002000) /*!< data receive in progress interrupt */
+#define SDIO_TXBUFH_INT ((uint32_t)0x00004000) /*!< transmit buf half empty interrupt */
+#define SDIO_RXBUFH_INT ((uint32_t)0x00008000) /*!< receive buf half full interrupt */
+#define SDIO_TXBUFF_INT ((uint32_t)0x00010000) /*!< transmit buf full interrupt */
+#define SDIO_RXBUFF_INT ((uint32_t)0x00020000) /*!< receive buf full interrupt */
+#define SDIO_TXBUFE_INT ((uint32_t)0x00040000) /*!< transmit buf empty interrupt */
+#define SDIO_RXBUFE_INT ((uint32_t)0x00080000) /*!< receive buf empty interrupt */
+#define SDIO_TXBUF_INT ((uint32_t)0x00100000) /*!< data available in transmit interrupt */
+#define SDIO_RXBUF_INT ((uint32_t)0x00200000) /*!< data available in receive interrupt */
+#define SDIO_SDIOIF_INT ((uint32_t)0x00400000) /*!< sdio interface received interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_flags_definition
+ * @brief sdio flag
+ * @{
+ */
+
+#define SDIO_CMDFAIL_FLAG ((uint32_t)0x00000001) /*!< command response received check failed flag */
+#define SDIO_DTFAIL_FLAG ((uint32_t)0x00000002) /*!< data block sent/received check failed flag */
+#define SDIO_CMDTIMEOUT_FLAG ((uint32_t)0x00000004) /*!< command response timerout flag */
+#define SDIO_DTTIMEOUT_FLAG ((uint32_t)0x00000008) /*!< data timeout flag */
+#define SDIO_TXERRU_FLAG ((uint32_t)0x00000010) /*!< transmit underrun error flag */
+#define SDIO_RXERRO_FLAG ((uint32_t)0x00000020) /*!< received overrun error flag */
+#define SDIO_CMDRSPCMPL_FLAG ((uint32_t)0x00000040) /*!< command response received flag */
+#define SDIO_CMDCMPL_FLAG ((uint32_t)0x00000080) /*!< command sent flag */
+#define SDIO_DTCMPL_FLAG ((uint32_t)0x00000100) /*!< data sent flag */
+#define SDIO_SBITERR_FLAG ((uint32_t)0x00000200) /*!< start bit not detected on data bus flag */
+#define SDIO_DTBLKCMPL_FLAG ((uint32_t)0x00000400) /*!< data block sent/received flag */
+#define SDIO_DOCMD_FLAG ((uint32_t)0x00000800) /*!< command transfer in progress flag */
+#define SDIO_DOTX_FLAG ((uint32_t)0x00001000) /*!< data transmit in progress flag */
+#define SDIO_DORX_FLAG ((uint32_t)0x00002000) /*!< data receive in progress flag */
+#define SDIO_TXBUFH_FLAG ((uint32_t)0x00004000) /*!< transmit buf half empty flag */
+#define SDIO_RXBUFH_FLAG ((uint32_t)0x00008000) /*!< receive buf half full flag */
+#define SDIO_TXBUFF_FLAG ((uint32_t)0x00010000) /*!< transmit buf full flag */
+#define SDIO_RXBUFF_FLAG ((uint32_t)0x00020000) /*!< receive buf full flag */
+#define SDIO_TXBUFE_FLAG ((uint32_t)0x00040000) /*!< transmit buf empty flag */
+#define SDIO_RXBUFE_FLAG ((uint32_t)0x00080000) /*!< receive buf empty flag */
+#define SDIO_TXBUF_FLAG ((uint32_t)0x00100000) /*!< data available in transmit flag */
+#define SDIO_RXBUF_FLAG ((uint32_t)0x00200000) /*!< data available in receive flag */
+#define SDIO_SDIOIF_FLAG ((uint32_t)0x00400000) /*!< sdio interface received flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup SDIO_exported_types
+ * @{
+ */
+
+/**
+ * @brief sdio power state
+ */
+typedef enum
+{
+ SDIO_POWER_OFF = 0x00, /*!< power-off, clock to card is stopped */
+ SDIO_POWER_ON = 0x03 /*!< power-on, the card is clocked */
+} sdio_power_state_type;
+
+/**
+ * @brief sdio edge phase
+ */
+typedef enum
+{
+ SDIO_CLOCK_EDGE_RISING = 0x00, /*!< sdio bus clock generated on the rising edge of the master clock */
+ SDIO_CLOCK_EDGE_FALLING = 0x01 /*!< sdio bus clock generated on the falling edge of the master clock */
+} sdio_edge_phase_type;
+
+/**
+ * @brief sdio bus width
+ */
+typedef enum
+{
+ SDIO_BUS_WIDTH_D1 = 0x00, /*!< sdio wide bus select 1-bit */
+ SDIO_BUS_WIDTH_D4 = 0x01, /*!< sdio wide bus select 4-bit */
+ SDIO_BUS_WIDTH_D8 = 0x02 /*!< sdio wide bus select 8-bit */
+} sdio_bus_width_type;
+
+/**
+ * @brief sdio response type
+ */
+typedef enum
+{
+ SDIO_RESPONSE_NO = 0x00, /*!< no response */
+ SDIO_RESPONSE_SHORT = 0x01, /*!< short response */
+ SDIO_RESPONSE_LONG = 0x03 /*!< long response */
+} sdio_reponse_type;
+
+/**
+ * @brief sdio wait type
+ */
+typedef enum
+{
+ SDIO_WAIT_FOR_NO = 0x00, /*!< no wait */
+ SDIO_WAIT_FOR_INT = 0x01, /*!< wait interrupt request */
+ SDIO_WAIT_FOR_PEND = 0x02 /*!< wait end of transfer */
+} sdio_wait_type;
+
+/**
+ * @brief sdio response register index
+ */
+typedef enum
+{
+ SDIO_RSP1_INDEX = 0x00, /*!< response index 1, corresponding to sdio_rsp register 1 */
+ SDIO_RSP2_INDEX = 0x01, /*!< response index 2, corresponding to sdio_rsp register 2 */
+ SDIO_RSP3_INDEX = 0x02, /*!< response index 3, corresponding to sdio_rsp register 3 */
+ SDIO_RSP4_INDEX = 0x03 /*!< response index 4, corresponding to sdio_rsp register 4 */
+} sdio_rsp_index_type;
+
+/**
+ * @brief sdio data block size
+ */
+typedef enum
+{
+ SDIO_DATA_BLOCK_SIZE_1B = 0x00, /*!< data block size 1 byte */
+ SDIO_DATA_BLOCK_SIZE_2B = 0x01, /*!< data block size 2 bytes */
+ SDIO_DATA_BLOCK_SIZE_4B = 0x02, /*!< data block size 4 bytes */
+ SDIO_DATA_BLOCK_SIZE_8B = 0x03, /*!< data block size 8 bytes */
+ SDIO_DATA_BLOCK_SIZE_16B = 0x04, /*!< data block size 16 bytes */
+ SDIO_DATA_BLOCK_SIZE_32B = 0x05, /*!< data block size 32 bytes */
+ SDIO_DATA_BLOCK_SIZE_64B = 0x06, /*!< data block size 64 bytes */
+ SDIO_DATA_BLOCK_SIZE_128B = 0x07, /*!< data block size 128 bytes */
+ SDIO_DATA_BLOCK_SIZE_256B = 0x08, /*!< data block size 256 bytes */
+ SDIO_DATA_BLOCK_SIZE_512B = 0x09, /*!< data block size 512 bytes */
+ SDIO_DATA_BLOCK_SIZE_1024B = 0x0A, /*!< data block size 1024 bytes */
+ SDIO_DATA_BLOCK_SIZE_2048B = 0x0B, /*!< data block size 2048 bytes */
+ SDIO_DATA_BLOCK_SIZE_4096B = 0x0C, /*!< data block size 4096 bytes */
+ SDIO_DATA_BLOCK_SIZE_8192B = 0x0D, /*!< data block size 8192 bytes */
+ SDIO_DATA_BLOCK_SIZE_16384B = 0x0E /*!< data block size 16384 bytes */
+} sdio_block_size_type;
+
+/**
+ * @brief sdio data transfer mode
+ */
+typedef enum
+{
+ SDIO_DATA_BLOCK_TRANSFER = 0x00, /*!< the sdio block transfer mode */
+ SDIO_DATA_STREAM_TRANSFER = 0x01 /*!< the sdio stream transfer mode */
+} sdio_transfer_mode_type;
+
+/**
+ * @brief sdio data transfer direction
+ */
+typedef enum
+{
+ SDIO_DATA_TRANSFER_TO_CARD = 0x00, /*!< the sdio controller write */
+ SDIO_DATA_TRANSFER_TO_CONTROLLER = 0x01 /*!< the sdio controller read */
+} sdio_transfer_direction_type;
+
+/**
+ * @brief sdio read wait mode
+ */
+typedef enum
+{
+ SDIO_READ_WAIT_CONTROLLED_BY_D2 = 0x00, /*!< the sdio read wait on data2 line */
+ SDIO_READ_WAIT_CONTROLLED_BY_CK = 0x01 /*!< the sdio read wait on clock line */
+} sdio_read_wait_mode_type;
+
+/**
+ * @brief sdio command structure
+ */
+typedef struct
+{
+ uint32_t argument; /*!< the sdio command argument is sent to a card as part of command message */
+ uint8_t cmd_index; /*!< the sdio command index */
+ sdio_reponse_type rsp_type; /*!< the sdio response type */
+ sdio_wait_type wait_type; /*!< the sdio wait for interrupt request is enabled or disable */
+} sdio_command_struct_type;
+
+/**
+ * @brief sdio data structure
+ */
+typedef struct
+{
+ uint32_t timeout; /*!< the sdio data timeout period in car bus clock periods */
+ uint32_t data_length; /*!< the sdio data length */
+ sdio_block_size_type block_size; /*!< the sdio data block size of block transfer mode */
+ sdio_transfer_mode_type transfer_mode; /*!< the sdio transfer mode, block or stream */
+ sdio_transfer_direction_type transfer_direction; /*!< the sdio data transfer direction */
+} sdio_data_struct_type;
+
+/**
+ * @brief type define sdio register all
+ */
+typedef struct
+{
+ /**
+ * @brief sdio pwrctrl register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t pwrctrl;
+ struct
+ {
+ __IO uint32_t ps : 2; /* [1:0] */
+ __IO uint32_t reserved1 : 30;/* [31:2] */
+ } pwrctrl_bit;
+ };
+
+ /**
+ * @brief sdio clkctrl register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t clkctrl;
+ struct
+ {
+ __IO uint32_t clkdiv_l : 8; /* [7:0] */
+ __IO uint32_t clkoen : 1; /* [8] */
+ __IO uint32_t pwrsven : 1; /* [9] */
+ __IO uint32_t bypsen : 1; /* [10] */
+ __IO uint32_t busws : 2; /* [12:11] */
+ __IO uint32_t clkegs : 1; /* [13] */
+ __IO uint32_t hfcen : 1; /* [14] */
+ __IO uint32_t clkdiv_h : 2; /* [16:15] */
+ __IO uint32_t reserved1 : 15;/* [31:17] */
+ } clkctrl_bit;
+ };
+
+ /**
+ * @brief sdio argu register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t argu;
+ struct
+ {
+ __IO uint32_t argu : 32;/* [31:0] */
+ } argu_bit;
+ };
+
+ /**
+ * @brief sdio cmdctrl register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t cmdctrl;
+ struct
+ {
+ __IO uint32_t cmdidx : 6; /* [5:0] */
+ __IO uint32_t rspwt : 2; /* [7:6] */
+ __IO uint32_t intwt : 1; /* [8] */
+ __IO uint32_t pndwt : 1; /* [9] */
+ __IO uint32_t ccsmen : 1; /* [10] */
+ __IO uint32_t iosusp : 1; /* [11] */
+ __IO uint32_t reserved1 : 20;/* [31:12] */
+ } cmdctrl_bit;
+ };
+
+ /**
+ * @brief sdio rspcmd register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t rspcmd;
+ struct
+ {
+ __IO uint32_t rspcmd : 6; /* [5:0] */
+ __IO uint32_t reserved1 : 26;/* [31:6] */
+ } rspcmd_bit;
+ };
+
+ /**
+ * @brief sdio rsp1 register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t rsp1;
+ struct
+ {
+ __IO uint32_t cardsts1 : 32;/* [31:0] */
+ } rsp1_bit;
+ };
+
+ /**
+ * @brief sdio rsp2 register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t rsp2;
+ struct
+ {
+ __IO uint32_t cardsts2 : 32;/* [31:0] */
+ } rsp2_bit;
+ };
+
+ /**
+ * @brief sdio rsp3 register, offset:0x1C
+ */
+ union
+ {
+ __IO uint32_t rsp3;
+ struct
+ {
+ __IO uint32_t cardsts3 : 32;/* [31:0] */
+ } rsp3_bit;
+ };
+
+ /**
+ * @brief sdio rsp4 register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t rsp4;
+ struct
+ {
+ __IO uint32_t cardsts4 : 32;/* [31:0] */
+ } rsp4_bit;
+ };
+
+ /**
+ * @brief sdio dttmr register, offset:0x24
+ */
+ union
+ {
+ __IO uint32_t dttmr;
+ struct
+ {
+ __IO uint32_t timeout : 32;/* [31:0] */
+ } dttmr_bit;
+ };
+
+ /**
+ * @brief sdio dtlen register, offset:0x28
+ */
+ union
+ {
+ __IO uint32_t dtlen;
+ struct
+ {
+ __IO uint32_t dtlen : 25;/* [24:0] */
+ __IO uint32_t reserved1 : 7; /* [31:25] */
+ } dtlen_bit;
+ };
+
+ /**
+ * @brief sdio dtctrl register, offset:0x2C
+ */
+ union
+ {
+ __IO uint32_t dtctrl;
+ struct
+ {
+ __IO uint32_t tfren : 1; /* [0] */
+ __IO uint32_t tfrdir : 1; /* [1] */
+ __IO uint32_t tfrmode : 1; /* [2] */
+ __IO uint32_t dmaen : 1; /* [3] */
+ __IO uint32_t blksize : 4; /* [7:4] */
+ __IO uint32_t rdwtstart : 1; /* [8] */
+ __IO uint32_t rdwtstop : 1; /* [9] */
+ __IO uint32_t rdwtmode : 1; /* [10] */
+ __IO uint32_t ioen : 1; /* [11] */
+ __IO uint32_t reserved1 : 20;/* [31:12] */
+ } dtctrl_bit;
+ };
+
+ /**
+ * @brief sdio dtcnt register, offset:0x30
+ */
+ union
+ {
+ __IO uint32_t dtcnt;
+ struct
+ {
+ __IO uint32_t cnt : 25;/* [24:0] */
+ __IO uint32_t reserved1 : 7; /* [31:25] */
+ } dtcnt_bit;
+ };
+
+ /**
+ * @brief sdio sts register, offset:0x34
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t cmdfail : 1; /* [0] */
+ __IO uint32_t dtfail : 1; /* [1] */
+ __IO uint32_t cmdtimeout : 1; /* [2] */
+ __IO uint32_t dttimeout : 1; /* [3] */
+ __IO uint32_t txerru : 1; /* [4] */
+ __IO uint32_t rxerro : 1; /* [5] */
+ __IO uint32_t cmdrspcmpl : 1; /* [6] */
+ __IO uint32_t cmdcmpl : 1; /* [7] */
+ __IO uint32_t dtcmpl : 1; /* [8] */
+ __IO uint32_t sbiterr : 1; /* [9] */
+ __IO uint32_t dtblkcmpl : 1; /* [10] */
+ __IO uint32_t docmd : 1; /* [11] */
+ __IO uint32_t dotx : 1; /* [12] */
+ __IO uint32_t dorx : 1; /* [13] */
+ __IO uint32_t txbufh : 1; /* [14] */
+ __IO uint32_t rxbufh : 1; /* [15] */
+ __IO uint32_t txbuff : 1; /* [16] */
+ __IO uint32_t rxbuff : 1; /* [17] */
+ __IO uint32_t txbufe : 1; /* [18] */
+ __IO uint32_t rxbufe : 1; /* [19] */
+ __IO uint32_t txbuf : 1; /* [20] */
+ __IO uint32_t rxbuf : 1; /* [21] */
+ __IO uint32_t ioif : 1; /* [22] */
+ __IO uint32_t reserved1 : 9; /* [31:23] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief sdio intclr register, offset:0x38
+ */
+ union
+ {
+ __IO uint32_t intclr;
+ struct
+ {
+ __IO uint32_t cmdfail : 1; /* [0] */
+ __IO uint32_t dtfail : 1; /* [1] */
+ __IO uint32_t cmdtimeout : 1; /* [2] */
+ __IO uint32_t dttimeout : 1; /* [3] */
+ __IO uint32_t txerru : 1; /* [4] */
+ __IO uint32_t rxerro : 1; /* [5] */
+ __IO uint32_t cmdrspcmpl : 1; /* [6] */
+ __IO uint32_t cmdcmpl : 1; /* [7] */
+ __IO uint32_t dtcmpl : 1; /* [8] */
+ __IO uint32_t sbiterr : 1; /* [9] */
+ __IO uint32_t dtblkcmpl : 1; /* [10] */
+ __IO uint32_t reserved1 : 11;/* [21:11] */
+ __IO uint32_t ioif : 1; /* [22] */
+ __IO uint32_t reserved2 : 9; /* [31:23] */
+ } intclr_bit;
+ };
+
+ /**
+ * @brief sdio inten register, offset:0x3C
+ */
+ union
+ {
+ __IO uint32_t inten;
+ struct
+ {
+ __IO uint32_t cmdfailien : 1; /* [0] */
+ __IO uint32_t dtfailien : 1; /* [1] */
+ __IO uint32_t cmdtimeoutien : 1; /* [2] */
+ __IO uint32_t dttimeoutien : 1; /* [3] */
+ __IO uint32_t txerruien : 1; /* [4] */
+ __IO uint32_t rxerroien : 1; /* [5] */
+ __IO uint32_t cmdrspcmplien : 1; /* [6] */
+ __IO uint32_t cmdcmplien : 1; /* [7] */
+ __IO uint32_t dtcmplien : 1; /* [8] */
+ __IO uint32_t sbiterrien : 1; /* [9] */
+ __IO uint32_t dtblkcmplien : 1; /* [10] */
+ __IO uint32_t docmdien : 1; /* [11] */
+ __IO uint32_t dotxien : 1; /* [12] */
+ __IO uint32_t dorxien : 1; /* [13] */
+ __IO uint32_t txbufhien : 1; /* [14] */
+ __IO uint32_t rxbufhien : 1; /* [15] */
+ __IO uint32_t txbuffien : 1; /* [16] */
+ __IO uint32_t rxbuffien : 1; /* [17] */
+ __IO uint32_t txbufeien : 1; /* [18] */
+ __IO uint32_t rxbufeien : 1; /* [19] */
+ __IO uint32_t txbufien : 1; /* [20] */
+ __IO uint32_t rxbufien : 1; /* [21] */
+ __IO uint32_t ioifien : 1; /* [22] */
+ __IO uint32_t reserved1 : 9; /* [31:23] */
+ } inten_bit;
+ };
+
+ /**
+ * @brief sdio reserved1 register, offset:0x40~0x44
+ */
+ __IO uint32_t reserved1[2];
+
+ /**
+ * @brief sdio bufcnt register, offset:0x48
+ */
+ union
+ {
+ __IO uint32_t bufcnt;
+ struct
+ {
+ __IO uint32_t cnt : 24;/* [23:0] */
+ __IO uint32_t reserved1 : 8; /* [31:24] */
+ } bufcnt_bit;
+ };
+
+ /**
+ * @brief sdio reserved2 register, offset:0x4C~0x7C
+ */
+ __IO uint32_t reserved2[13];
+
+ /**
+ * @brief sdio buf register, offset:0x80
+ */
+ union
+ {
+ __IO uint32_t buf;
+ struct
+ {
+ __IO uint32_t dt : 32;/* [31:0] */
+ } buf_bit;
+ };
+
+} sdio_type;
+
+/**
+ * @}
+ */
+
+#define SDIO1 ((sdio_type *) SDIO1_BASE)
+#define SDIO2 ((sdio_type *) SDIO2_BASE)
+
+/** @defgroup SDIO_exported_functions
+ * @{
+ */
+
+void sdio_reset(sdio_type *sdio_x);
+void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state);
+sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x);
+void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg);
+void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width);
+void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state);
+void sdio_power_saving_mode_enable(sdio_type *sdio_x, confirm_state new_state);
+void sdio_flow_control_enable(sdio_type *sdio_x, confirm_state new_state);
+void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state);
+void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state);
+void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state new_state);
+flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag);
+flag_status sdio_interrupt_flag_get(sdio_type *sdio_x, uint32_t flag);
+void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag);
+void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct);
+void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
+uint8_t sdio_command_response_get(sdio_type *sdio_x);
+uint32_t sdio_response_get(sdio_type *sdio_x, sdio_rsp_index_type reg_index);
+void sdio_data_config(sdio_type *sdio_x, sdio_data_struct_type *data_struct);
+void sdio_data_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
+uint32_t sdio_data_counter_get(sdio_type *sdio_x);
+uint32_t sdio_data_read(sdio_type *sdio_x);
+uint32_t sdio_buffer_counter_get(sdio_type *sdio_x);
+void sdio_data_write(sdio_type *sdio_x, uint32_t data);
+void sdio_read_wait_mode_set(sdio_type *sdio_x, sdio_read_wait_mode_type mode);
+void sdio_read_wait_start(sdio_type *sdio_x, confirm_state new_state);
+void sdio_read_wait_stop(sdio_type *sdio_x, confirm_state new_state);
+void sdio_io_function_enable(sdio_type *sdio_x, confirm_state new_state);
+void sdio_io_suspend_command_set(sdio_type *sdio_x, confirm_state new_state);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_spi.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_spi.h
new file mode 100644
index 00000000000..c3b2bb1f6ac
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_spi.h
@@ -0,0 +1,534 @@
+/**
+ **************************************************************************
+ * @file at32f45x_spi.h
+ * @brief at32f45x spi header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_SPI_H
+#define __AT32F45x_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f45x.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/**
+ * @defgroup SPI_I2S_flags_definition
+ * @brief spi i2s flag
+ * @{
+ */
+
+#define SPI_I2S_RDBF_FLAG ((uint32_t)0x00000001) /*!< spi or i2s receive data buffer full flag */
+#define SPI_I2S_TDBE_FLAG ((uint32_t)0x00000002) /*!< spi or i2s transmit data buffer empty flag */
+#define I2S_ACS_FLAG ((uint32_t)0x00000004) /*!< i2s audio channel state flag */
+#define I2S_TUERR_FLAG ((uint32_t)0x00000008) /*!< i2s transmitter underload error flag */
+#define SPI_CCERR_FLAG ((uint32_t)0x00000010) /*!< spi crc calculation error flag */
+#define SPI_MMERR_FLAG ((uint32_t)0x00000020) /*!< spi master mode error flag */
+#define SPI_I2S_ROERR_FLAG ((uint32_t)0x00000040) /*!< spi or i2s receiver overflow error flag */
+#define SPI_I2S_BF_FLAG ((uint32_t)0x00000080) /*!< spi or i2s busy flag */
+#define SPI_I2S_CSPAS_FLAG ((uint32_t)0x00000100) /*!< spi or i2s cs pulse abnormal setting fiag */
+
+/**
+ * @}
+ */
+
+/**
+ * @defgroup SPI_I2S_interrupts_definition
+ * @brief spi i2s interrupt
+ * @{
+ */
+
+#define SPI_I2S_ERROR_INT ((uint32_t)0x00000020) /*!< error interrupt */
+#define SPI_I2S_RDBF_INT ((uint32_t)0x00000040) /*!< receive data buffer full interrupt */
+#define SPI_I2S_TDBE_INT ((uint32_t)0x00000080) /*!< transmit data buffer empty interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_exported_types
+ * @{
+ */
+
+/**
+ * @brief spi frame bit num type
+ */
+typedef enum
+{
+ SPI_FRAME_8BIT = 0x00, /*!< 8-bit data frame format */
+ SPI_FRAME_16BIT = 0x01 /*!< 16-bit data frame format */
+} spi_frame_bit_num_type;
+
+/**
+ * @brief spi master/slave mode type
+ */
+typedef enum
+{
+ SPI_MODE_SLAVE = 0x00, /*!< select as slave mode */
+ SPI_MODE_MASTER = 0x01 /*!< select as master mode */
+} spi_master_slave_mode_type;
+
+/**
+ * @brief spi clock polarity (clkpol) type
+ */
+typedef enum
+{
+ SPI_CLOCK_POLARITY_LOW = 0x00, /*!< sck keeps low at idle state */
+ SPI_CLOCK_POLARITY_HIGH = 0x01 /*!< sck keeps high at idle state */
+} spi_clock_polarity_type;
+
+/**
+ * @brief spi clock phase (clkpha) type
+ */
+typedef enum
+{
+ SPI_CLOCK_PHASE_1EDGE = 0x00, /*!< data capture start from the first clock edge */
+ SPI_CLOCK_PHASE_2EDGE = 0x01 /*!< data capture start from the second clock edge */
+} spi_clock_phase_type;
+
+/**
+ * @brief spi cs mode type
+ */
+typedef enum
+{
+ SPI_CS_HARDWARE_MODE = 0x00, /*!< cs is hardware mode */
+ SPI_CS_SOFTWARE_MODE = 0x01 /*!< cs is software mode */
+} spi_cs_mode_type;
+
+/**
+ * @brief spi master clock frequency division type
+ */
+typedef enum
+{
+ SPI_MCLK_DIV_2 = 0x00, /*!< master clock frequency division 2 */
+ SPI_MCLK_DIV_3 = 0x0A, /*!< master clock frequency division 3 */
+ SPI_MCLK_DIV_4 = 0x01, /*!< master clock frequency division 4 */
+ SPI_MCLK_DIV_8 = 0x02, /*!< master clock frequency division 8 */
+ SPI_MCLK_DIV_16 = 0x03, /*!< master clock frequency division 16 */
+ SPI_MCLK_DIV_32 = 0x04, /*!< master clock frequency division 32 */
+ SPI_MCLK_DIV_64 = 0x05, /*!< master clock frequency division 64 */
+ SPI_MCLK_DIV_128 = 0x06, /*!< master clock frequency division 128 */
+ SPI_MCLK_DIV_256 = 0x07, /*!< master clock frequency division 256 */
+ SPI_MCLK_DIV_512 = 0x08, /*!< master clock frequency division 512 */
+ SPI_MCLK_DIV_1024 = 0x09 /*!< master clock frequency division 1024 */
+} spi_mclk_freq_div_type;
+
+/**
+ * @brief spi transmit first bit (lsb/msb) type
+ */
+typedef enum
+{
+ SPI_FIRST_BIT_MSB = 0x00, /*!< the frame format is msb first */
+ SPI_FIRST_BIT_LSB = 0x01 /*!< the frame format is lsb first */
+} spi_first_bit_type;
+
+/**
+ * @brief spi transmission mode type
+ */
+typedef enum
+{
+ SPI_TRANSMIT_FULL_DUPLEX = 0x00, /*!< dual line unidirectional full-duplex mode(slben = 0 and ora = 0) */
+ SPI_TRANSMIT_SIMPLEX_RX = 0x01, /*!< dual line unidirectional simplex receive-only mode(slben = 0 and ora = 1) */
+ SPI_TRANSMIT_HALF_DUPLEX_RX = 0x02, /*!< single line bidirectional half duplex mode-receiving(slben = 1 and slbtd = 0) */
+ SPI_TRANSMIT_HALF_DUPLEX_TX = 0x03 /*!< single line bidirectional half duplex mode-transmitting(slben = 1 and slbtd = 1) */
+} spi_transmission_mode_type;
+
+/**
+ * @brief spi crc direction type
+ */
+typedef enum
+{
+ SPI_CRC_RX = 0x0014, /*!< crc direction is rx */
+ SPI_CRC_TX = 0x0018 /*!< crc direction is tx */
+} spi_crc_direction_type;
+
+/**
+ * @brief spi single line bidirectional direction type
+ */
+typedef enum
+{
+ SPI_HALF_DUPLEX_DIRECTION_RX = 0x00, /*!< single line bidirectional half duplex mode direction: receive(slbtd = 0) */
+ SPI_HALF_DUPLEX_DIRECTION_TX = 0x01 /*!< single line bidirectional half duplex mode direction: transmit(slbtd = 1) */
+} spi_half_duplex_direction_type;
+
+/**
+ * @brief spi software cs internal level type
+ */
+typedef enum
+{
+ SPI_SWCS_INTERNAL_LEVEL_LOW = 0x00, /*!< internal level low */
+ SPI_SWCS_INTERNAL_LEVEL_HIGHT = 0x01 /*!< internal level high */
+} spi_software_cs_level_type;
+
+/**
+ * @brief i2s audio protocol type
+ */
+typedef enum
+{
+ I2S_AUDIO_PROTOCOL_PHILLIPS = 0x00, /*!< i2s philip standard */
+ I2S_AUDIO_PROTOCOL_MSB = 0x01, /*!< msb-justified standard */
+ I2S_AUDIO_PROTOCOL_LSB = 0x02, /*!< lsb-justified standard */
+ I2S_AUDIO_PROTOCOL_PCM_SHORT = 0x03, /*!< pcm standard-short frame */
+ I2S_AUDIO_PROTOCOL_PCM_LONG = 0x04 /*!< pcm standard-long frame */
+} i2s_audio_protocol_type;
+
+/**
+ * @brief i2s audio frequency type
+ */
+typedef enum
+{
+ I2S_AUDIO_FREQUENCY_DEFAULT = 2, /*!< i2s audio sampling frequency default */
+ I2S_AUDIO_FREQUENCY_8K = 8000, /*!< i2s audio sampling frequency 8k */
+ I2S_AUDIO_FREQUENCY_11_025K = 11025, /*!< i2s audio sampling frequency 11.025k */
+ I2S_AUDIO_FREQUENCY_16K = 16000, /*!< i2s audio sampling frequency 16k */
+ I2S_AUDIO_FREQUENCY_22_05K = 22050, /*!< i2s audio sampling frequency 22.05k */
+ I2S_AUDIO_FREQUENCY_32K = 32000, /*!< i2s audio sampling frequency 32k */
+ I2S_AUDIO_FREQUENCY_44_1K = 44100, /*!< i2s audio sampling frequency 44.1k */
+ I2S_AUDIO_FREQUENCY_48K = 48000, /*!< i2s audio sampling frequency 48k */
+ I2S_AUDIO_FREQUENCY_96K = 96000, /*!< i2s audio sampling frequency 96k */
+ I2S_AUDIO_FREQUENCY_192K = 192000 /*!< i2s audio sampling frequency 192k */
+} i2s_audio_sampling_freq_type;
+
+/**
+ * @brief i2s data bit num and channel bit num type
+ */
+typedef enum
+{
+ I2S_DATA_16BIT_CHANNEL_16BIT = 0x01, /*!< 16-bit data packed in 16-bit channel frame */
+ I2S_DATA_16BIT_CHANNEL_32BIT = 0x02, /*!< 16-bit data packed in 32-bit channel frame */
+ I2S_DATA_24BIT_CHANNEL_32BIT = 0x03, /*!< 24-bit data packed in 32-bit channel frame */
+ I2S_DATA_32BIT_CHANNEL_32BIT = 0x04 /*!< 32-bit data packed in 32-bit channel frame */
+} i2s_data_channel_format_type;
+
+/**
+ * @brief i2s operation mode type
+ */
+typedef enum
+{
+ I2S_MODE_SLAVE_TX = 0x00, /*!< slave transmission mode */
+ I2S_MODE_SLAVE_RX = 0x01, /*!< slave reception mode */
+ I2S_MODE_MASTER_TX = 0x02, /*!< master transmission mode */
+ I2S_MODE_MASTER_RX = 0x03 /*!< master reception mode */
+} i2s_operation_mode_type;
+
+/**
+ * @brief i2s clock polarity type
+ */
+typedef enum
+{
+ I2S_CLOCK_POLARITY_LOW = 0x00, /*!< i2s clock steady state is low level */
+ I2S_CLOCK_POLARITY_HIGH = 0x01 /*!< i2s clock steady state is high level */
+} i2s_clock_polarity_type;
+
+/**
+ * @brief i2s pcm mode sample clock selection type
+ */
+typedef enum
+{
+ I2S_PCM_SAMPLE_CLOCK_FALLING = 0x00, /*!< i2s pcm mode sample clock is falling edge */
+ I2S_PCM_SAMPLE_CLOCK_RISING = 0x01 /*!< i2s pcm mode sample clock is rising edge */
+} i2s_pcm_sample_clock_type;
+
+/**
+ * @brief spi init type
+ */
+typedef struct
+{
+ spi_transmission_mode_type transmission_mode; /*!< transmission mode selection */
+ spi_master_slave_mode_type master_slave_mode; /*!< master or slave mode selection */
+ spi_mclk_freq_div_type mclk_freq_division; /*!< master clock frequency division selection */
+ spi_first_bit_type first_bit_transmission;/*!< transmit lsb or msb selection */
+ spi_frame_bit_num_type frame_bit_num; /*!< frame bit num 8 or 16 bit selection */
+ spi_clock_polarity_type clock_polarity; /*!< clock polarity selection */
+ spi_clock_phase_type clock_phase; /*!< clock phase selection */
+ spi_cs_mode_type cs_mode_selection; /*!< hardware or software cs mode selection */
+} spi_init_type;
+
+/**
+ * @brief i2s init type
+ */
+typedef struct
+{
+ i2s_operation_mode_type operation_mode; /*!< operation mode selection */
+ i2s_audio_protocol_type audio_protocol; /*!< audio protocol selection */
+ i2s_audio_sampling_freq_type audio_sampling_freq; /*!< audio frequency selection */
+ i2s_data_channel_format_type data_channel_format; /*!< data bit num and channel bit num selection */
+ i2s_clock_polarity_type clock_polarity; /*!< clock polarity selection */
+ confirm_state mclk_output_enable; /*!< mclk_output selection */
+ uint32_t i2s_ckin_value; /*!< i2s clock input walue */
+ i2s_pcm_sample_clock_type pcm_sample_clock_selection; /*!< i2s pcm mode sample clock selection */
+} i2s_init_type;
+
+/**
+ * @brief type define spi register all
+ */
+typedef struct
+{
+
+ /**
+ * @brief spi ctrl1 register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t ctrl1;
+ struct
+ {
+ __IO uint32_t clkpha : 1; /* [0] */
+ __IO uint32_t clkpol : 1; /* [1] */
+ __IO uint32_t msten : 1; /* [2] */
+ __IO uint32_t mdiv_l : 3; /* [5:3] */
+ __IO uint32_t spien : 1; /* [6] */
+ __IO uint32_t ltf : 1; /* [7] */
+ __IO uint32_t swcsil : 1; /* [8] */
+ __IO uint32_t swcsen : 1; /* [9] */
+ __IO uint32_t ora : 1; /* [10] */
+ __IO uint32_t fbn : 1; /* [11] */
+ __IO uint32_t ntc : 1; /* [12] */
+ __IO uint32_t ccen : 1; /* [13] */
+ __IO uint32_t slbtd : 1; /* [14] */
+ __IO uint32_t slben : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } ctrl1_bit;
+ };
+
+ /**
+ * @brief spi ctrl2 register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t ctrl2;
+ struct
+ {
+ __IO uint32_t dmaren : 1; /* [0] */
+ __IO uint32_t dmaten : 1; /* [1] */
+ __IO uint32_t hwcsoe : 1; /* [2] */
+ __IO uint32_t reserved1 : 1; /* [3] */
+ __IO uint32_t tien : 1; /* [4] */
+ __IO uint32_t errie : 1; /* [5] */
+ __IO uint32_t rdbfie : 1; /* [6] */
+ __IO uint32_t tdbeie : 1; /* [7] */
+ __IO uint32_t mdiv_h : 1; /* [8] */
+ __IO uint32_t mdiv3en : 1; /* [9] */
+ __IO uint32_t reserved2 : 22;/* [31:10] */
+ } ctrl2_bit;
+ };
+
+ /**
+ * @brief spi sts register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t rdbf : 1; /* [0] */
+ __IO uint32_t tdbe : 1; /* [1] */
+ __IO uint32_t acs : 1; /* [2] */
+ __IO uint32_t tuerr : 1; /* [3] */
+ __IO uint32_t ccerr : 1; /* [4] */
+ __IO uint32_t mmerr : 1; /* [5] */
+ __IO uint32_t roerr : 1; /* [6] */
+ __IO uint32_t bf : 1; /* [7] */
+ __IO uint32_t cspas : 1; /* [8] */
+ __IO uint32_t reserved1 : 23;/* [31:9] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief spi dt register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t dt;
+ struct
+ {
+ __IO uint32_t dt : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } dt_bit;
+ };
+
+ /**
+ * @brief spi cpoly register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t cpoly;
+ struct
+ {
+ __IO uint32_t cpoly : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } cpoly_bit;
+ };
+
+ /**
+ * @brief spi rcrc register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t rcrc;
+ struct
+ {
+ __IO uint32_t rcrc : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } rcrc_bit;
+ };
+
+ /**
+ * @brief spi tcrc register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t tcrc;
+ struct
+ {
+ __IO uint32_t tcrc : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } tcrc_bit;
+ };
+
+ /**
+ * @brief spi i2sctrl register, offset:0x1C
+ */
+ union
+ {
+ __IO uint32_t i2sctrl;
+ struct
+ {
+ __IO uint32_t i2scbn : 1; /* [0] */
+ __IO uint32_t i2sdbn : 2; /* [2:1] */
+ __IO uint32_t i2sclkpol : 1; /* [3] */
+ __IO uint32_t stdsel : 2; /* [5:4] */
+ __IO uint32_t reserved1 : 1; /* [6] */
+ __IO uint32_t pcmfssel : 1; /* [7] */
+ __IO uint32_t opersel : 2; /* [9:8] */
+ __IO uint32_t i2sen : 1; /* [10] */
+ __IO uint32_t i2smsel : 1; /* [11] */
+ __IO uint32_t reserved2 : 1; /* [12] */
+ __IO uint32_t i2sfdupen : 1; /* [13] */
+ __IO uint32_t reserved3 : 18;/* [31:14] */
+ } i2sctrl_bit;
+ };
+
+ /**
+ * @brief spi i2sclk register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t i2sclk;
+ struct
+ {
+ __IO uint32_t i2sdiv_l : 8; /* [7:0] */
+ __IO uint32_t i2sodd : 1; /* [8] */
+ __IO uint32_t i2smclkoe : 1; /* [9] */
+ __IO uint32_t i2sdiv_h : 2; /* [11:10] */
+ __IO uint32_t reserved1 : 20;/* [31:12] */
+ } i2sclk_bit;
+ };
+
+ __IO uint32_t reserved1[3];
+
+ /**
+ * @brief spi misc1 register, offset:0x30
+ */
+ union
+ {
+ __IO uint32_t misc1;
+ struct
+ {
+ __IO uint32_t i2sfpcmcksel : 1; /* [0] */
+ __IO uint32_t reserved1 : 31; /* [31:1] */
+ } misc1_bit;
+ };
+} spi_type;
+
+/**
+ * @}
+ */
+
+#define SPI1 ((spi_type *) SPI1_BASE)
+#define SPI2 ((spi_type *) SPI2_BASE)
+#define SPI3 ((spi_type *) SPI3_BASE)
+#define SPI4 ((spi_type *) SPI4_BASE)
+#define I2SF5 ((spi_type *) I2SF5_BASE)
+#define I2S2EXT ((spi_type *) I2S2EXT_BASE)
+#define I2S3EXT ((spi_type *) I2S3EXT_BASE)
+
+/** @defgroup SPI_exported_functions
+ * @{
+ */
+
+void spi_i2s_reset(spi_type *spi_x);
+void spi_default_para_init(spi_init_type* spi_init_struct);
+void spi_init(spi_type* spi_x, spi_init_type* spi_init_struct);
+void spi_ti_mode_enable(spi_type* spi_x, confirm_state new_state);
+void spi_crc_next_transmit(spi_type* spi_x);
+void spi_crc_polynomial_set(spi_type* spi_x, uint16_t crc_poly);
+uint16_t spi_crc_polynomial_get(spi_type* spi_x);
+void spi_crc_enable(spi_type* spi_x, confirm_state new_state);
+uint16_t spi_crc_value_get(spi_type* spi_x, spi_crc_direction_type crc_direction);
+void spi_hardware_cs_output_enable(spi_type* spi_x, confirm_state new_state);
+void spi_software_cs_internal_level_set(spi_type* spi_x, spi_software_cs_level_type level);
+void spi_frame_bit_num_set(spi_type* spi_x, spi_frame_bit_num_type bit_num);
+void spi_half_duplex_direction_set(spi_type* spi_x, spi_half_duplex_direction_type direction);
+void spi_enable(spi_type* spi_x, confirm_state new_state);
+void i2s_default_para_init(i2s_init_type* i2s_init_struct);
+void i2s_init(spi_type* spi_x, i2s_init_type* i2s_init_struct);
+void i2s_enable(spi_type* spi_x, confirm_state new_state);
+void spi_i2s_interrupt_enable(spi_type* spi_x, uint32_t spi_i2s_int, confirm_state new_state);
+void spi_i2s_dma_transmitter_enable(spi_type* spi_x, confirm_state new_state);
+void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state);
+void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data);
+uint16_t spi_i2s_data_receive(spi_type* spi_x);
+flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag);
+flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag);
+void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag);
+void i2sf_full_duplex_mode_enable(spi_type* spi_x, confirm_state new_state);
+void i2sf_pcm_sample_clock_set(spi_type* spi_x, i2s_pcm_sample_clock_type pcm_sample_clock);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_tmr.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_tmr.h
new file mode 100644
index 00000000000..e41fc49014f
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_tmr.h
@@ -0,0 +1,1012 @@
+/**
+ **************************************************************************
+ * @file at32f45x_tmr.h
+ * @brief at32f45x tmr header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_TMR_H
+#define __AT32F45x_TMR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f45x.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @addtogroup TMR
+ * @{
+ */
+
+/** @defgroup TMR_flags_definition
+ * @brief tmr flag
+ * @{
+ */
+
+#define TMR_OVF_FLAG ((uint32_t)0x000001) /*!< tmr flag overflow */
+#define TMR_C1_FLAG ((uint32_t)0x000002) /*!< tmr flag channel 1 */
+#define TMR_C2_FLAG ((uint32_t)0x000004) /*!< tmr flag channel 2 */
+#define TMR_C3_FLAG ((uint32_t)0x000008) /*!< tmr flag channel 3 */
+#define TMR_C4_FLAG ((uint32_t)0x000010) /*!< tmr flag channel 4 */
+#define TMR_C5_FLAG ((uint32_t)0x010000) /*!< tmr flag channel 5 */
+#define TMR_HALL_FLAG ((uint32_t)0x000020) /*!< tmr flag hall */
+#define TMR_TRIGGER_FLAG ((uint32_t)0x000040) /*!< tmr flag trigger */
+#define TMR_BRK_FLAG ((uint32_t)0x000080) /*!< tmr flag brake */
+#define TMR_C1_RECAPTURE_FLAG ((uint32_t)0x000200) /*!< tmr flag channel 1 recapture */
+#define TMR_C2_RECAPTURE_FLAG ((uint32_t)0x000400) /*!< tmr flag channel 2 recapture */
+#define TMR_C3_RECAPTURE_FLAG ((uint32_t)0x000800) /*!< tmr flag channel 3 recapture */
+#define TMR_C4_RECAPTURE_FLAG ((uint32_t)0x001000) /*!< tmr flag channel 4 recapture */
+
+/**
+ * @}
+ */
+
+/** @defgroup TMR_interrupt_select_type_definition
+ * @brief tmr interrupt select type
+ * @{
+ */
+
+#define TMR_OVF_INT ((uint32_t)0x000001) /*!< tmr interrupt overflow */
+#define TMR_C1_INT ((uint32_t)0x000002) /*!< tmr interrupt channel 1 */
+#define TMR_C2_INT ((uint32_t)0x000004) /*!< tmr interrupt channel 2 */
+#define TMR_C3_INT ((uint32_t)0x000008) /*!< tmr interrupt channel 3 */
+#define TMR_C4_INT ((uint32_t)0x000010) /*!< tmr interrupt channel 4 */
+#define TMR_HALL_INT ((uint32_t)0x000020) /*!< tmr interrupt hall */
+#define TMR_TRIGGER_INT ((uint32_t)0x000040) /*!< tmr interrupt trigger */
+#define TMR_BRK_INT ((uint32_t)0x000080) /*!< tmr interrupt brake */
+
+/**
+ * @}
+ */
+
+/** @defgroup TMR_exported_types
+ * @{
+ */
+
+/**
+ * @brief tmr clock division type
+ */
+typedef enum
+{
+ TMR_CLOCK_DIV1 = 0x00, /*!< tmr clock division 1 */
+ TMR_CLOCK_DIV2 = 0x01, /*!< tmr clock division 2 */
+ TMR_CLOCK_DIV4 = 0x02 /*!< tmr clock division 4 */
+} tmr_clock_division_type;
+
+/**
+ * @brief tmr counter mode type
+ */
+typedef enum
+{
+ TMR_COUNT_UP = 0x00, /*!< tmr counter mode up */
+ TMR_COUNT_DOWN = 0x01, /*!< tmr counter mode down */
+ TMR_COUNT_TWO_WAY_1 = 0x02, /*!< tmr counter mode two way 1 */
+ TMR_COUNT_TWO_WAY_2 = 0x04, /*!< tmr counter mode two way 2 */
+ TMR_COUNT_TWO_WAY_3 = 0x06 /*!< tmr counter mode two way 3 */
+} tmr_count_mode_type;
+
+/**
+ * @brief tmr primary mode select type
+ */
+typedef enum
+{
+ TMR_PRIMARY_SEL_RESET = 0x00, /*!< tmr primary mode select reset */
+ TMR_PRIMARY_SEL_ENABLE = 0x01, /*!< tmr primary mode select enable */
+ TMR_PRIMARY_SEL_OVERFLOW = 0x02, /*!< tmr primary mode select overflow */
+ TMR_PRIMARY_SEL_COMPARE = 0x03, /*!< tmr primary mode select compare */
+ TMR_PRIMARY_SEL_C1ORAW = 0x04, /*!< tmr primary mode select c1oraw */
+ TMR_PRIMARY_SEL_C2ORAW = 0x05, /*!< tmr primary mode select c2oraw */
+ TMR_PRIMARY_SEL_C3ORAW = 0x06, /*!< tmr primary mode select c3oraw */
+ TMR_PRIMARY_SEL_C4ORAW = 0x07 /*!< tmr primary mode select c4oraw */
+} tmr_primary_select_type;
+
+/**
+ * @brief tmr subordinate mode input select type
+ */
+typedef enum
+{
+ TMR_SUB_INPUT_SEL_IS0 = 0x00, /*!< subordinate mode input select is0 */
+ TMR_SUB_INPUT_SEL_IS1 = 0x01, /*!< subordinate mode input select is1 */
+ TMR_SUB_INPUT_SEL_IS2 = 0x02, /*!< subordinate mode input select is2 */
+ TMR_SUB_INPUT_SEL_IS3 = 0x03, /*!< subordinate mode input select is3 */
+ TMR_SUB_INPUT_SEL_C1INC = 0x04, /*!< subordinate mode input select c1inc */
+ TMR_SUB_INPUT_SEL_C1DF1 = 0x05, /*!< subordinate mode input select c1df1 */
+ TMR_SUB_INPUT_SEL_C2DF2 = 0x06, /*!< subordinate mode input select c2df2 */
+ TMR_SUB_INPUT_SEL_EXTIN = 0x07 /*!< subordinate mode input select extin */
+} sub_tmr_input_sel_type;
+
+/**
+ * @brief tmr subordinate mode select type
+ */
+typedef enum
+{
+ TMR_SUB_MODE_DIABLE = 0x00, /*!< subordinate mode disable */
+ TMR_SUB_ENCODER_MODE_A = 0x01, /*!< subordinate mode select encoder mode a */
+ TMR_SUB_ENCODER_MODE_B = 0x02, /*!< subordinate mode select encoder mode b */
+ TMR_SUB_ENCODER_MODE_C = 0x03, /*!< subordinate mode select encoder mode c */
+ TMR_SUB_RESET_MODE = 0x04, /*!< subordinate mode select reset */
+ TMR_SUB_HANG_MODE = 0x05, /*!< subordinate mode select hang */
+ TMR_SUB_TRIGGER_MODE = 0x06, /*!< subordinate mode select trigger */
+ TMR_SUB_EXTERNAL_CLOCK_MODE_A = 0x07 /*!< subordinate mode external clock mode a */
+} tmr_sub_mode_select_type;
+
+/**
+ * @brief tmr encoder mode type
+ */
+typedef enum
+{
+ TMR_ENCODER_MODE_A = TMR_SUB_ENCODER_MODE_A, /*!< tmr encoder mode a */
+ TMR_ENCODER_MODE_B = TMR_SUB_ENCODER_MODE_B, /*!< tmr encoder mode b */
+ TMR_ENCODER_MODE_C = TMR_SUB_ENCODER_MODE_C /*!< tmr encoder mode c */
+} tmr_encoder_mode_type;
+
+/**
+ * @brief tmr output control mode type
+ */
+typedef enum
+{
+ TMR_OUTPUT_CONTROL_OFF = 0x00, /*!< tmr output control mode off */
+ TMR_OUTPUT_CONTROL_HIGH = 0x01, /*!< tmr output control mode high */
+ TMR_OUTPUT_CONTROL_LOW = 0x02, /*!< tmr output control mode low */
+ TMR_OUTPUT_CONTROL_SWITCH = 0x03, /*!< tmr output control mode switch */
+ TMR_OUTPUT_CONTROL_FORCE_LOW = 0x04, /*!< tmr output control mode force low */
+ TMR_OUTPUT_CONTROL_FORCE_HIGH = 0x05, /*!< tmr output control mode force high */
+ TMR_OUTPUT_CONTROL_PWM_MODE_A = 0x06, /*!< tmr output control mode pwm a */
+ TMR_OUTPUT_CONTROL_PWM_MODE_B = 0x07 /*!< tmr output control mode pwm b */
+} tmr_output_control_mode_type;
+
+/**
+ * @brief tmr force output type
+ */
+typedef enum
+{
+ TMR_FORCE_OUTPUT_HIGH = TMR_OUTPUT_CONTROL_FORCE_HIGH, /*!< tmr force output high */
+ TMR_FORCE_OUTPUT_LOW = TMR_OUTPUT_CONTROL_FORCE_LOW /*!< tmr force output low */
+} tmr_force_output_type;
+
+/**
+ * @brief tmr output channel polarity type
+ */
+typedef enum
+{
+ TMR_OUTPUT_ACTIVE_HIGH = 0x00, /*!< tmr output channel polarity high */
+ TMR_OUTPUT_ACTIVE_LOW = 0x01 /*!< tmr output channel polarity low */
+} tmr_output_polarity_type;
+
+/**
+ * @brief tmr input channel polarity type
+ */
+typedef enum
+{
+ TMR_INPUT_RISING_EDGE = 0x00, /*!< tmr input channel polarity rising */
+ TMR_INPUT_FALLING_EDGE = 0x01, /*!< tmr input channel polarity falling */
+ TMR_INPUT_BOTH_EDGE = 0x03 /*!< tmr input channel polarity both edge */
+} tmr_input_polarity_type;
+
+/**
+ * @brief tmr channel select type
+ */
+typedef enum
+{
+ TMR_SELECT_CHANNEL_1 = 0x00, /*!< tmr channel select channel 1 */
+ TMR_SELECT_CHANNEL_1C = 0x01, /*!< tmr channel select channel 1 complementary */
+ TMR_SELECT_CHANNEL_2 = 0x02, /*!< tmr channel select channel 2 */
+ TMR_SELECT_CHANNEL_2C = 0x03, /*!< tmr channel select channel 2 complementary */
+ TMR_SELECT_CHANNEL_3 = 0x04, /*!< tmr channel select channel 3 */
+ TMR_SELECT_CHANNEL_3C = 0x05, /*!< tmr channel select channel 3 complementary */
+ TMR_SELECT_CHANNEL_4 = 0x06, /*!< tmr channel select channel 4 */
+ TMR_SELECT_CHANNEL_4C = 0x07, /*!< tmr channel select channel 4 complementary */
+ TMR_SELECT_CHANNEL_5 = 0x08 /*!< tmr channel select channel 5 */
+} tmr_channel_select_type;
+
+/**
+ * @brief tmr channel1 input connected type
+ */
+typedef enum
+{
+ TMR_CHANEL1_CONNECTED_C1IRAW = 0x00, /*!< channel1 pins is only connected to C1IRAW input */
+ TMR_CHANEL1_2_3_CONNECTED_C1IRAW_XOR = 0x01 /*!< channel1/2/3 pins are connected to C1IRAW input after xored */
+} tmr_channel1_input_connected_type;
+
+/**
+ * @brief tmr input channel mapped type channel direction
+ */
+typedef enum
+{
+ TMR_CC_CHANNEL_MAPPED_DIRECT = 0x01, /*!< channel is configured as input, mapped direct */
+ TMR_CC_CHANNEL_MAPPED_INDIRECT = 0x02, /*!< channel is configured as input, mapped indirect */
+ TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped sti */
+} tmr_input_direction_mapped_type;
+
+/**
+ * @brief tmr input divider type
+ */
+typedef enum
+{
+ TMR_CHANNEL_INPUT_DIV_1 = 0x00, /*!< tmr channel input divider 1 */
+ TMR_CHANNEL_INPUT_DIV_2 = 0x01, /*!< tmr channel input divider 2 */
+ TMR_CHANNEL_INPUT_DIV_4 = 0x02, /*!< tmr channel input divider 4 */
+ TMR_CHANNEL_INPUT_DIV_8 = 0x03 /*!< tmr channel input divider 8 */
+} tmr_channel_input_divider_type;
+
+/**
+ * @brief tmr dma request source select type
+ */
+typedef enum
+{
+ TMR_DMA_REQUEST_BY_CHANNEL = 0x00, /*!< tmr dma request source select channel */
+ TMR_DMA_REQUEST_BY_OVERFLOW = 0x01 /*!< tmr dma request source select overflow */
+} tmr_dma_request_source_type;
+
+/**
+ * @brief tmr dma request type
+ */
+typedef enum
+{
+ TMR_OVERFLOW_DMA_REQUEST = 0x00000100, /*!< tmr dma request select overflow */
+ TMR_C1_DMA_REQUEST = 0x00000200, /*!< tmr dma request select channel 1 */
+ TMR_C2_DMA_REQUEST = 0x00000400, /*!< tmr dma request select channel 2 */
+ TMR_C3_DMA_REQUEST = 0x00000800, /*!< tmr dma request select channel 3 */
+ TMR_C4_DMA_REQUEST = 0x00001000, /*!< tmr dma request select channel 4 */
+ TMR_HALL_DMA_REQUEST = 0x00002000, /*!< tmr dma request select hall */
+ TMR_TRIGGER_DMA_REQUEST = 0x00004000 /*!< tmr dma request select trigger */
+} tmr_dma_request_type;
+
+/**
+ * @brief tmr event triggered by software type
+ */
+typedef enum
+{
+ TMR_OVERFLOW_SWTRIG = 0x00000001, /*!< tmr event triggered by software of overflow */
+ TMR_C1_SWTRIG = 0x00000002, /*!< tmr event triggered by software of channel 1 */
+ TMR_C2_SWTRIG = 0x00000004, /*!< tmr event triggered by software of channel 2 */
+ TMR_C3_SWTRIG = 0x00000008, /*!< tmr event triggered by software of channel 3 */
+ TMR_C4_SWTRIG = 0x00000010, /*!< tmr event triggered by software of channel 4 */
+ TMR_HALL_SWTRIG = 0x00000020, /*!< tmr event triggered by software of hall */
+ TMR_TRIGGER_SWTRIG = 0x00000040, /*!< tmr event triggered by software of trigger */
+ TMR_BRK_SWTRIG = 0x00000080 /*!< tmr event triggered by software of brake */
+}tmr_event_trigger_type;
+
+/**
+ * @brief tmr polarity active type
+ */
+typedef enum
+{
+ TMR_POLARITY_ACTIVE_HIGH = 0x00, /*!< tmr polarity active high */
+ TMR_POLARITY_ACTIVE_LOW = 0x01, /*!< tmr polarity active low */
+ TMR_POLARITY_ACTIVE_BOTH = 0x02 /*!< tmr polarity active both high ande low */
+}tmr_polarity_active_type;
+
+/**
+ * @brief tmr external signal divider type
+ */
+typedef enum
+{
+ TMR_ES_FREQUENCY_DIV_1 = 0x00, /*!< tmr external signal frequency divider 1 */
+ TMR_ES_FREQUENCY_DIV_2 = 0x01, /*!< tmr external signal frequency divider 2 */
+ TMR_ES_FREQUENCY_DIV_4 = 0x02, /*!< tmr external signal frequency divider 4 */
+ TMR_ES_FREQUENCY_DIV_8 = 0x03 /*!< tmr external signal frequency divider 8 */
+}tmr_external_signal_divider_type;
+
+/**
+ * @brief tmr external signal polarity type
+ */
+typedef enum
+{
+ TMR_ES_POLARITY_NON_INVERTED = 0x00, /*!< tmr external signal polarity non-inerted */
+ TMR_ES_POLARITY_INVERTED = 0x01 /*!< tmr external signal polarity inerted */
+}tmr_external_signal_polarity_type;
+
+/**
+ * @brief tmr dma transfer length type
+ */
+typedef enum
+{
+ TMR_DMA_TRANSFER_1BYTE = 0x00, /*!< tmr dma transfer length 1 byte */
+ TMR_DMA_TRANSFER_2BYTES = 0x01, /*!< tmr dma transfer length 2 bytes */
+ TMR_DMA_TRANSFER_3BYTES = 0x02, /*!< tmr dma transfer length 3 bytes */
+ TMR_DMA_TRANSFER_4BYTES = 0x03, /*!< tmr dma transfer length 4 bytes */
+ TMR_DMA_TRANSFER_5BYTES = 0x04, /*!< tmr dma transfer length 5 bytes */
+ TMR_DMA_TRANSFER_6BYTES = 0x05, /*!< tmr dma transfer length 6 bytes */
+ TMR_DMA_TRANSFER_7BYTES = 0x06, /*!< tmr dma transfer length 7 bytes */
+ TMR_DMA_TRANSFER_8BYTES = 0x07, /*!< tmr dma transfer length 8 bytes */
+ TMR_DMA_TRANSFER_9BYTES = 0x08, /*!< tmr dma transfer length 9 bytes */
+ TMR_DMA_TRANSFER_10BYTES = 0x09, /*!< tmr dma transfer length 10 bytes */
+ TMR_DMA_TRANSFER_11BYTES = 0x0A, /*!< tmr dma transfer length 11 bytes */
+ TMR_DMA_TRANSFER_12BYTES = 0x0B, /*!< tmr dma transfer length 12 bytes */
+ TMR_DMA_TRANSFER_13BYTES = 0x0C, /*!< tmr dma transfer length 13 bytes */
+ TMR_DMA_TRANSFER_14BYTES = 0x0D, /*!< tmr dma transfer length 14 bytes */
+ TMR_DMA_TRANSFER_15BYTES = 0x0E, /*!< tmr dma transfer length 15 bytes */
+ TMR_DMA_TRANSFER_16BYTES = 0x0F, /*!< tmr dma transfer length 16 bytes */
+ TMR_DMA_TRANSFER_17BYTES = 0x10, /*!< tmr dma transfer length 17 bytes */
+ TMR_DMA_TRANSFER_18BYTES = 0x11 /*!< tmr dma transfer length 18 bytes */
+}tmr_dma_transfer_length_type;
+
+/**
+ * @brief tmr dma base address type
+ */
+typedef enum
+{
+ TMR_CTRL1_ADDRESS = 0x0000, /*!< tmr dma base address ctrl1 */
+ TMR_CTRL2_ADDRESS = 0x0001, /*!< tmr dma base address ctrl2 */
+ TMR_STCTRL_ADDRESS = 0x0002, /*!< tmr dma base address stctrl */
+ TMR_IDEN_ADDRESS = 0x0003, /*!< tmr dma base address iden */
+ TMR_ISTS_ADDRESS = 0x0004, /*!< tmr dma base address ists */
+ TMR_SWEVT_ADDRESS = 0x0005, /*!< tmr dma base address swevt */
+ TMR_CM1_ADDRESS = 0x0006, /*!< tmr dma base address cm1 */
+ TMR_CM2_ADDRESS = 0x0007, /*!< tmr dma base address cm2 */
+ TMR_CCTRL_ADDRESS = 0x0008, /*!< tmr dma base address cctrl */
+ TMR_CVAL_ADDRESS = 0x0009, /*!< tmr dma base address cval */
+ TMR_DIV_ADDRESS = 0x000A, /*!< tmr dma base address div */
+ TMR_PR_ADDRESS = 0x000B, /*!< tmr dma base address pr */
+ TMR_RPR_ADDRESS = 0x000C, /*!< tmr dma base address rpr */
+ TMR_C1DT_ADDRESS = 0x000D, /*!< tmr dma base address c1dt */
+ TMR_C2DT_ADDRESS = 0x000E, /*!< tmr dma base address c2dt */
+ TMR_C3DT_ADDRESS = 0x000F, /*!< tmr dma base address c3dt */
+ TMR_C4DT_ADDRESS = 0x0010, /*!< tmr dma base address c4dt */
+ TMR_BRK_ADDRESS = 0x0011, /*!< tmr dma base address brake */
+ TMR_DMACTRL_ADDRESS = 0x0012 /*!< tmr dma base address dmactrl */
+}tmr_dma_address_type;
+
+/**
+ * @brief tmr brk polarity type
+ */
+typedef enum
+{
+ TMR_BRK_INPUT_ACTIVE_LOW = 0x00, /*!< tmr brk input channel active low */
+ TMR_BRK_INPUT_ACTIVE_HIGH = 0x01 /*!< tmr brk input channel active high */
+}tmr_brk_polarity_type;
+
+/**
+ * @brief tmr write protect level type
+ */
+typedef enum
+{
+ TMR_WP_OFF = 0x00, /*!< tmr write protect off */
+ TMR_WP_LEVEL_3 = 0x01, /*!< tmr write protect level 3 */
+ TMR_WP_LEVEL_2 = 0x02, /*!< tmr write protect level 2 */
+ TMR_WP_LEVEL_1 = 0x03 /*!< tmr write protect level 1 */
+}tmr_wp_level_type;
+
+/**
+ * @brief tmr input remap type
+ */
+typedef enum
+{
+ TMR2_TMR8TRGOUT_TMR5_GPIO_TMR14_GPIO = 0x00, /*!< tmr2 input remap to tmr8_trgout or tmr5 remap to gpio or tmr14 remap to gpio */
+ TMR2_EMAC_PTP_TMR5_LICK_TMR14_ERTC_CLK = 0x01, /*!< tmr2 input remap to emac ptp or tmr5 remap to lick or tmr14 remap to ertc clock */
+ TMR2_USB_SOF_TMR5_LEXT_TMR14_HEXT_DIV = 0x02, /*!< tmr2 input remap to usb sof or tmr5 remap to lext or tmr14 remap to hext divider */
+ TMR5_ERTC_WKUP_TMR14_CLKOUT = 0x03 /*!< tmr5 remap to ertc wkup or tmr14 remap to clock out */
+}tmr_input_remap_type ;
+/**
+
+ * @brief tmr output config type
+ */
+typedef struct
+{
+ tmr_output_control_mode_type oc_mode; /*!< output channel mode */
+ confirm_state oc_idle_state; /*!< output channel idle state */
+ confirm_state occ_idle_state; /*!< output channel complementary idle state */
+ tmr_output_polarity_type oc_polarity; /*!< output channel polarity */
+ tmr_output_polarity_type occ_polarity; /*!< output channel complementary polarity */
+ confirm_state oc_output_state; /*!< output channel enable */
+ confirm_state occ_output_state; /*!< output channel complementary enable */
+} tmr_output_config_type;
+
+/**
+ * @brief tmr input capture config type
+ */
+typedef struct
+{
+ tmr_channel_select_type input_channel_select; /*!< tmr input channel select */
+ tmr_input_polarity_type input_polarity_select; /*!< tmr input polarity select */
+ tmr_input_direction_mapped_type input_mapped_select; /*!< tmr channel mapped direct or indirect */
+ uint8_t input_filter_value; /*!< tmr channel filter value */
+} tmr_input_config_type;
+
+/**
+ * @brief tmr brkdt config type
+ */
+typedef struct
+{
+ uint8_t deadtime; /*!< dead-time generator setup */
+ tmr_brk_polarity_type brk_polarity; /*!< tmr brake polarity */
+ tmr_wp_level_type wp_level; /*!< write protect configuration */
+ confirm_state auto_output_enable; /*!< automatic output enable */
+ confirm_state fcsoen_state; /*!< frozen channel status when output enable */
+ confirm_state fcsodis_state; /*!< frozen channel status when output disable */
+ confirm_state brk_enable; /*!< tmr brk enale */
+} tmr_brkdt_config_type;
+
+/**
+ * @brief type define tmr register all
+ */
+typedef struct
+{
+ /**
+ * @brief tmr ctrl1 register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t ctrl1;
+ struct
+ {
+ __IO uint32_t tmren : 1; /* [0] */
+ __IO uint32_t ovfen : 1; /* [1] */
+ __IO uint32_t ovfs : 1; /* [2] */
+ __IO uint32_t ocmen : 1; /* [3] */
+ __IO uint32_t cnt_dir : 3; /* [6:4] */
+ __IO uint32_t prben : 1; /* [7] */
+ __IO uint32_t clkdiv : 2; /* [9:8] */
+ __IO uint32_t pmen : 1; /* [10] */
+ __IO uint32_t reserved1 : 21;/* [31:11] */
+ } ctrl1_bit;
+ };
+
+ /**
+ * @brief tmr ctrl2 register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t ctrl2;
+ struct
+ {
+ __IO uint32_t cbctrl : 1; /* [0] */
+ __IO uint32_t reserved1 : 1; /* [1] */
+ __IO uint32_t ccfs : 1; /* [2] */
+ __IO uint32_t drs : 1; /* [3] */
+ __IO uint32_t ptos : 3; /* [6:4] */
+ __IO uint32_t c1insel : 1; /* [7] */
+ __IO uint32_t c1ios : 1; /* [8] */
+ __IO uint32_t c1cios : 1; /* [9] */
+ __IO uint32_t c2ios : 1; /* [10] */
+ __IO uint32_t c2cios : 1; /* [11] */
+ __IO uint32_t c3ios : 1; /* [12] */
+ __IO uint32_t c3cios : 1; /* [13] */
+ __IO uint32_t c4ios : 1; /* [14] */
+ __IO uint32_t c4cios : 1; /* [15] */
+ __IO uint32_t reserved2 : 15;/* [30:16] */
+ __IO uint32_t trgout2en : 1; /* [31] */
+ } ctrl2_bit;
+ };
+
+ /**
+ * @brief tmr smc register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t stctrl;
+ struct
+ {
+ __IO uint32_t smsel : 3; /* [2:0] */
+ __IO uint32_t reserved1 : 1; /* [3] */
+ __IO uint32_t stis : 3; /* [6:4] */
+ __IO uint32_t sts : 1; /* [7] */
+ __IO uint32_t esf : 4; /* [11:8] */
+ __IO uint32_t esdiv : 2; /* [13:12] */
+ __IO uint32_t ecmben : 1; /* [14] */
+ __IO uint32_t esp : 1; /* [15] */
+ __IO uint32_t reserved2 : 16;/* [31:16] */
+ } stctrl_bit;
+ };
+
+ /**
+ * @brief tmr die register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t iden;
+ struct
+ {
+ __IO uint32_t ovfien : 1; /* [0] */
+ __IO uint32_t c1ien : 1; /* [1] */
+ __IO uint32_t c2ien : 1; /* [2] */
+ __IO uint32_t c3ien : 1; /* [3] */
+ __IO uint32_t c4ien : 1; /* [4] */
+ __IO uint32_t hallien : 1; /* [5] */
+ __IO uint32_t tien : 1; /* [6] */
+ __IO uint32_t brkie : 1; /* [7] */
+ __IO uint32_t ovfden : 1; /* [8] */
+ __IO uint32_t c1den : 1; /* [9] */
+ __IO uint32_t c2den : 1; /* [10] */
+ __IO uint32_t c3den : 1; /* [11] */
+ __IO uint32_t c4den : 1; /* [12] */
+ __IO uint32_t hallde : 1; /* [13] */
+ __IO uint32_t tden : 1; /* [14] */
+ __IO uint32_t reserved1 : 17;/* [31:15] */
+ } iden_bit;
+ };
+
+ /**
+ * @brief tmr ists register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t ists;
+ struct
+ {
+ __IO uint32_t ovfif : 1; /* [0] */
+ __IO uint32_t c1if : 1; /* [1] */
+ __IO uint32_t c2if : 1; /* [2] */
+ __IO uint32_t c3if : 1; /* [3] */
+ __IO uint32_t c4if : 1; /* [4] */
+ __IO uint32_t hallif : 1; /* [5] */
+ __IO uint32_t trgif : 1; /* [6] */
+ __IO uint32_t brkif : 1; /* [7] */
+ __IO uint32_t reserved1 : 1; /* [8] */
+ __IO uint32_t c1rf : 1; /* [9] */
+ __IO uint32_t c2rf : 1; /* [10] */
+ __IO uint32_t c3rf : 1; /* [11] */
+ __IO uint32_t c4rf : 1; /* [12] */
+ __IO uint32_t reserved2 : 19;/* [31:13] */
+ } ists_bit;
+ };
+
+ /**
+ * @brief tmr eveg register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t swevt;
+ struct
+ {
+ __IO uint32_t ovfswtr : 1; /* [0] */
+ __IO uint32_t c1swtr : 1; /* [1] */
+ __IO uint32_t c2swtr : 1; /* [2] */
+ __IO uint32_t c3swtr : 1; /* [3] */
+ __IO uint32_t c4swtr : 1; /* [4] */
+ __IO uint32_t hallswtr : 1; /* [5] */
+ __IO uint32_t trgswtr : 1; /* [6] */
+ __IO uint32_t brkswtr : 1; /* [7] */
+ __IO uint32_t reserved : 24;/* [31:8] */
+ } swevt_bit;
+ };
+
+ /**
+ * @brief tmr ccm1 register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t cm1;
+
+ /**
+ * @brief channel mode
+ */
+ struct
+ {
+ __IO uint32_t c1c : 2; /* [1:0] */
+ __IO uint32_t c1oien : 1; /* [2] */
+ __IO uint32_t c1oben : 1; /* [3] */
+ __IO uint32_t c1octrl : 3; /* [6:4] */
+ __IO uint32_t c1osen : 1; /* [7] */
+ __IO uint32_t c2c : 2; /* [9:8] */
+ __IO uint32_t c2oien : 1; /* [10] */
+ __IO uint32_t c2oben : 1; /* [11] */
+ __IO uint32_t c2octrl : 3; /* [14:12] */
+ __IO uint32_t c2osen : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } cm1_output_bit;
+
+ /**
+ * @brief input capture mode
+ */
+ struct
+ {
+ __IO uint32_t c1c : 2; /* [1:0] */
+ __IO uint32_t c1idiv : 2; /* [3:2] */
+ __IO uint32_t c1df : 4; /* [7:4] */
+ __IO uint32_t c2c : 2; /* [9:8] */
+ __IO uint32_t c2idiv : 2; /* [11:10] */
+ __IO uint32_t c2df : 4; /* [15:12] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } cm1_input_bit;
+ };
+
+ /**
+ * @brief tmr ccm2 register, offset:0x1C
+ */
+ union
+ {
+ __IO uint32_t cm2;
+
+ /**
+ * @brief channel mode
+ */
+ struct
+ {
+ __IO uint32_t c3c : 2; /* [1:0] */
+ __IO uint32_t c3oien : 1; /* [2] */
+ __IO uint32_t c3oben : 1; /* [3] */
+ __IO uint32_t c3octrl : 3; /* [6:4] */
+ __IO uint32_t c3osen : 1; /* [7] */
+ __IO uint32_t c4c : 2; /* [9:8] */
+ __IO uint32_t c4oien : 1; /* [10] */
+ __IO uint32_t c4oben : 1; /* [11] */
+ __IO uint32_t c4octrl : 3; /* [14:12] */
+ __IO uint32_t c4osen : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } cm2_output_bit;
+
+ /**
+ * @brief input capture mode
+ */
+ struct
+ {
+ __IO uint32_t c3c : 2; /* [1:0] */
+ __IO uint32_t c3idiv : 2; /* [3:2] */
+ __IO uint32_t c3df : 4; /* [7:4] */
+ __IO uint32_t c4c : 2; /* [9:8] */
+ __IO uint32_t c4idiv : 2; /* [11:10] */
+ __IO uint32_t c4df : 4; /* [15:12] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } cm2_input_bit;
+ };
+
+ /**
+ * @brief tmr cce register, offset:0x20
+ */
+ union
+ {
+ uint32_t cctrl;
+ struct
+ {
+ __IO uint32_t c1en : 1; /* [0] */
+ __IO uint32_t c1p : 1; /* [1] */
+ __IO uint32_t c1cen : 1; /* [2] */
+ __IO uint32_t c1cp : 1; /* [3] */
+ __IO uint32_t c2en : 1; /* [4] */
+ __IO uint32_t c2p : 1; /* [5] */
+ __IO uint32_t c2cen : 1; /* [6] */
+ __IO uint32_t c2cp : 1; /* [7] */
+ __IO uint32_t c3en : 1; /* [8] */
+ __IO uint32_t c3p : 1; /* [9] */
+ __IO uint32_t c3cen : 1; /* [10] */
+ __IO uint32_t c3cp : 1; /* [11] */
+ __IO uint32_t c4en : 1; /* [12] */
+ __IO uint32_t c4p : 1; /* [13] */
+ __IO uint32_t c4cen : 1; /* [14] */
+ __IO uint32_t c4cp : 1; /* [15] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } cctrl_bit;
+ };
+
+ /**
+ * @brief tmr cnt register, offset:0x24
+ */
+ union
+ {
+ __IO uint32_t cval;
+ struct
+ {
+ __IO uint32_t cval : 32;/* [31:0] */
+ } cval_bit;
+ };
+
+ /**
+ * @brief tmr div, offset:0x28
+ */
+ union
+ {
+ __IO uint32_t div;
+ struct
+ {
+ __IO uint32_t div : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } div_bit;
+ };
+
+ /**
+ * @brief tmr pr register, offset:0x2C
+ */
+ union
+ {
+ __IO uint32_t pr;
+ struct
+ {
+ __IO uint32_t pr : 32;/* [31:0] */
+ } pr_bit;
+ };
+
+ /**
+ * @brief tmr rpr register, offset:0x30
+ */
+ union
+ {
+ __IO uint32_t rpr;
+ struct
+ {
+ __IO uint32_t rpr : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } rpr_bit;
+ };
+
+ /**
+ * @brief tmr c1dt register, offset:0x34
+ */
+ union
+ {
+ uint32_t c1dt;
+ struct
+ {
+ __IO uint32_t c1dt : 32;/* [31:0] */
+ } c1dt_bit;
+ };
+
+ /**
+ * @brief tmr c2dt register, offset:0x38
+ */
+ union
+ {
+ uint32_t c2dt;
+ struct
+ {
+ __IO uint32_t c2dt : 32;/* [31:0] */
+ } c2dt_bit;
+ };
+
+ /**
+ * @brief tmr c3dt register, offset:0x3C
+ */
+ union
+ {
+ __IO uint32_t c3dt;
+ struct
+ {
+ __IO uint32_t c3dt : 32;/* [31:0] */
+ } c3dt_bit;
+ };
+
+ /**
+ * @brief tmr c4dt register, offset:0x40
+ */
+ union
+ {
+ __IO uint32_t c4dt;
+ struct
+ {
+ __IO uint32_t c4dt : 32;/* [31:0] */
+ } c4dt_bit;
+ };
+
+ /**
+ * @brief tmr brk register, offset:0x44
+ */
+ union
+ {
+ __IO uint32_t brk;
+ struct
+ {
+ __IO uint32_t dtc : 8; /* [7:0] */
+ __IO uint32_t wpc : 2; /* [9:8] */
+ __IO uint32_t fcsodis : 1; /* [10] */
+ __IO uint32_t fcsoen : 1; /* [11] */
+ __IO uint32_t brken : 1; /* [12] */
+ __IO uint32_t brkv : 1; /* [13] */
+ __IO uint32_t aoen : 1; /* [14] */
+ __IO uint32_t oen : 1; /* [15] */
+ __IO uint32_t brkf : 4; /* [19:16] */
+ __IO uint32_t reserved1 : 12;/* [31:20] */
+ } brk_bit;
+ };
+
+ /**
+ * @brief tmr dmactrl register, offset:0x48
+ */
+ union
+ {
+ __IO uint32_t dmactrl;
+ struct
+ {
+ __IO uint32_t addr : 5; /* [4:0] */
+ __IO uint32_t reserved1 : 3; /* [7:5] */
+ __IO uint32_t dtb : 5; /* [12:8] */
+ __IO uint32_t reserved2 : 19;/* [31:13] */
+ } dmactrl_bit;
+ };
+
+ /**
+ * @brief tmr dmadt register, offset:0x4C
+ */
+ union
+ {
+ __IO uint32_t dmadt;
+ struct
+ {
+ __IO uint32_t dmadt : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } dmadt_bit;
+ };
+
+ /**
+ * @brief tmr rmp register, offset:0x50
+ */
+ union
+ {
+ __IO uint32_t rmp;
+ struct
+ {
+ __IO uint32_t tmr14_ch1_irmp : 2; /* [1:0] */
+ __IO uint32_t reserved1 : 4; /* [5:2] */
+ __IO uint32_t tmr5_ch4_irmp : 2; /* [7:6] */
+ __IO uint32_t reserved2 : 2; /* [9:8] */
+ __IO uint32_t tmr2_ch1_irmp : 2; /* [11:10] */
+ __IO uint32_t reserved3 : 20;/* [31:16] */
+ } rmp_bit;
+ };
+
+ /**
+ * @brief tmr reserved0 register, offset:0x54-0x6C
+ */
+ __IO uint32_t reserved1[7];
+
+ /**
+ * @brief tmr cm3 register, offset:0x70
+ */
+ union
+ {
+ __IO uint32_t cm3;
+ struct
+ {
+ __IO uint32_t reserved1 : 2; /* [1:0] */
+ __IO uint32_t c5oien : 1; /* [2] */
+ __IO uint32_t c5oben : 1; /* [3] */
+ __IO uint32_t c5octrl : 3; /* [6:4] */
+ __IO uint32_t c5osen : 1; /* [7] */
+ __IO uint32_t reserved2 : 24;/* [31:8] */
+ } cm3_output_bit;
+ };
+
+ /**
+ * @brief tmr c5dt register, offset:0x74
+ */
+ union
+ {
+ __IO uint32_t c5dt;
+ struct
+ {
+ __IO uint32_t c5dt : 32;/* [31:0] */
+ } c5dt_bit;
+ };
+} tmr_type;
+
+/**
+ * @}
+ */
+
+#define TMR1 ((tmr_type *) TMR1_BASE)
+#define TMR2 ((tmr_type *) TMR2_BASE)
+#define TMR3 ((tmr_type *) TMR3_BASE)
+#define TMR4 ((tmr_type *) TMR4_BASE)
+#define TMR5 ((tmr_type *) TMR5_BASE)
+#define TMR6 ((tmr_type *) TMR6_BASE)
+#define TMR7 ((tmr_type *) TMR7_BASE)
+#define TMR8 ((tmr_type *) TMR8_BASE)
+#define TMR9 ((tmr_type *) TMR9_BASE)
+#define TMR10 ((tmr_type *) TMR10_BASE)
+#define TMR11 ((tmr_type *) TMR11_BASE)
+#define TMR12 ((tmr_type *) TMR12_BASE)
+#define TMR13 ((tmr_type *) TMR13_BASE)
+#define TMR14 ((tmr_type *) TMR14_BASE)
+
+/** @defgroup TMR_exported_functions
+ * @{
+ */
+
+void tmr_reset(tmr_type *tmr_x);
+void tmr_counter_enable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_output_default_para_init(tmr_output_config_type *tmr_output_struct);
+void tmr_input_default_para_init(tmr_input_config_type *tmr_input_struct);
+void tmr_brkdt_default_para_init(tmr_brkdt_config_type *tmr_brkdt_struct);
+void tmr_base_init(tmr_type* tmr_x, uint32_t tmr_pr, uint32_t tmr_div);
+void tmr_clock_source_div_set(tmr_type *tmr_x, tmr_clock_division_type tmr_clock_div);
+void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir);
+void tmr_repetition_counter_set(tmr_type *tmr_x, uint16_t tmr_rpr_value);
+void tmr_counter_value_set(tmr_type *tmr_x, uint32_t tmr_cnt_value);
+uint32_t tmr_counter_value_get(tmr_type *tmr_x);
+void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value);
+uint32_t tmr_div_value_get(tmr_type *tmr_x);
+void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_output_config_type *tmr_output_struct);
+void tmr_output_channel_mode_select(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_output_control_mode_type oc_mode);
+void tmr_period_value_set(tmr_type *tmr_x, uint32_t tmr_pr_value);
+uint32_t tmr_period_value_get(tmr_type *tmr_x);
+void tmr_channel_value_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ uint32_t tmr_channel_value);
+uint32_t tmr_channel_value_get(tmr_type *tmr_x, tmr_channel_select_type tmr_channel);
+void tmr_period_buffer_enable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_output_channel_buffer_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ confirm_state new_state);
+void tmr_output_channel_immediately_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ confirm_state new_state);
+void tmr_output_channel_switch_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ confirm_state new_state);
+void tmr_one_cycle_mode_enable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_32_bit_function_enable (tmr_type *tmr_x, confirm_state new_state);
+void tmr_overflow_request_source_set(tmr_type *tmr_x, confirm_state new_state);
+void tmr_overflow_event_disable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
+ tmr_channel_input_divider_type divider_factor);
+void tmr_channel_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, confirm_state new_state);
+void tmr_input_channel_filter_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ uint16_t filter_value);
+void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
+ tmr_channel_input_divider_type divider_factor);
+void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect);
+void tmr_input_channel_divider_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_channel_input_divider_type divider_factor);
+void tmr_primary_mode_select(tmr_type *tmr_x, tmr_primary_select_type primary_mode);
+void tmr_sub_mode_select(tmr_type *tmr_x, tmr_sub_mode_select_type sub_mode);
+void tmr_channel_dma_select(tmr_type *tmr_x, tmr_dma_request_source_type cc_dma_select);
+void tmr_hall_select(tmr_type *tmr_x, confirm_state new_state);
+void tmr_channel_buffer_enable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_trgout2_enable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_select);
+void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state);
+void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state);
+void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state);
+flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag);
+flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag);
+void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag);
+void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event);
+void tmr_output_enable(tmr_type *tmr_x, confirm_state new_state);
+void tmr_internal_clock_set(tmr_type *tmr_x);
+void tmr_output_channel_polarity_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_polarity_active_type oc_polarity);
+void tmr_external_clock_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
+ tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);
+void tmr_external_clock_mode1_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
+ tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);
+void tmr_external_clock_mode2_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
+ tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);
+void tmr_encoder_mode_config(tmr_type *tmr_x, tmr_encoder_mode_type encoder_mode, tmr_input_polarity_type \
+ ic1_polarity, tmr_input_polarity_type ic2_polarity);
+void tmr_force_output_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_force_output_type force_output);
+void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_length, \
+ tmr_dma_address_type dma_base_address);
+void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct);
+void tmr_brk_filter_value_set(tmr_type *tmr_x, uint8_t filter_value);
+void tmr_iremap_config(tmr_type *tmr_x, tmr_input_remap_type input_remap);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_trng.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_trng.h
new file mode 100644
index 00000000000..ac974ac410b
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_trng.h
@@ -0,0 +1,183 @@
+/**
+ **************************************************************************
+ * @file at32f45x_trng.h
+ * @brief at32f45x trng header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_TRNG_H
+#define __AT32F45x_TRNG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f45x.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @addtogroup TRNG
+ * @{
+ */
+
+/** @defgroup TRNG_flags_definition
+ * @brief trng flag
+ * @{
+ */
+#define TRNG_DTRDY_FLAG ((uint32_t)0x00000001) /*!< data ready flag */
+#define TRNG_CKFES_FLAG ((uint32_t)0x00000002) /*!< clock fail event flag */
+#define TRNG_ESFES_FLAG ((uint32_t)0x00000004) /*!< entropy fail event flag */
+#define TRNG_CEFIS_FLAG ((uint32_t)0x00000020) /*!< clock fail interrupt flag */
+#define TRNG_ESFIS_FLAG ((uint32_t)0x00000040) /*!< entropy fail interrupt flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup TRNG_interrupts_definition
+ * @brief trng interrupt
+ * @{
+ */
+
+#define TRNG_FIE_INT ((uint32_t)0x00000008) /*!< trng fail interrupt */
+#define TRNG_DTRIE_INT ((uint32_t)0x00000010) /*!< trng data port ready interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup TRNG_exported_types
+ * @{
+ */
+
+/**
+ * @brief type define trng register all
+ */
+typedef struct
+{
+ /**
+ * @brief trng ctrl register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t ctrl;
+ struct
+ {
+ __IO uint32_t reserved1 : 2; /* [1:0] */
+ __IO uint32_t nsen : 1; /* [2] */
+ __IO uint32_t fie : 1; /* [3] */
+ __IO uint32_t dtrie : 1; /* [4] */
+ __IO uint32_t reserved2 : 11;/* [15:5] */
+ __IO uint32_t clkdiv : 4; /* [19:16] */
+ __IO uint32_t ht0 : 2; /* [21:20] */
+ __IO uint32_t reserved3 : 7; /* [28:22] */
+ __IO uint32_t fesclr : 1; /* [29] */
+ __IO uint32_t cudis : 1; /* [30] */
+ __IO uint32_t prglk : 1; /* [31] */
+ } ctrl_bit;
+ };
+
+ /**
+ * @brief trng sts register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t dtrdy : 1; /* [0] */
+ __IO uint32_t ckfes : 1; /* [1] */
+ __IO uint32_t esfes : 1; /* [2] */
+ __IO uint32_t reserved1 : 2; /* [4:3] */
+ __IO uint32_t ckfis : 1; /* [5] */
+ __IO uint32_t esfis : 1; /* [6] */
+ __IO uint32_t reserved2 : 25;/* [31:7] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief trng dt register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t dt;
+ struct
+ {
+ __IO uint32_t dt : 32;/* [31:0] */
+ } dt_bit;
+ };
+
+ /**
+ * @brief trng htctrl register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t htctrl;
+ struct
+ {
+ __IO uint32_t ht1 : 20;/* [19:0] */
+ __IO uint32_t reserved : 12;/* [31:20] */
+ } htctrl_bit;
+ };
+} trng_type;
+
+/**
+ * @}
+ */
+
+#define TRNG ((trng_type *) TRNG_BASE)
+
+/** @defgroup TRNG_exported_functions
+ * @{
+ */
+
+void trng_reset(void);
+void trng_enable(confirm_state new_state);
+void trng_interrupt_enable(uint32_t trng_int, confirm_state new_state);
+void trng_clock_divider_set(uint8_t factor);
+void trng_conditioning_and_buffer_enable(confirm_state new_state);
+void trng_programing_register_lock(void);
+uint32_t trng_value_get(void);
+flag_status trng_flag_get(uint32_t flag);
+flag_status trng_interrupt_flag_get(uint32_t flag);
+void trng_flag_clear(uint32_t flag);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_usart.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_usart.h
new file mode 100644
index 00000000000..2ddd568329a
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_usart.h
@@ -0,0 +1,459 @@
+/**
+ **************************************************************************
+ * @file at32f45x_usart.h
+ * @brief at32f45x usart header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_USART_H
+#define __AT32F45x_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f45x.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @addtogroup USART
+ * @{
+ */
+
+/** @defgroup USART_flags_definition
+ * @brief usart flag
+ * @{
+ */
+
+#define USART_PERR_FLAG ((uint32_t)0x00000001) /*!< usart parity error flag */
+#define USART_FERR_FLAG ((uint32_t)0x00000002) /*!< usart framing error flag */
+#define USART_NERR_FLAG ((uint32_t)0x00000004) /*!< usart noise error flag */
+#define USART_ROERR_FLAG ((uint32_t)0x00000008) /*!< usart receiver overflow error flag */
+#define USART_IDLEF_FLAG ((uint32_t)0x00000010) /*!< usart idle flag */
+#define USART_RDBF_FLAG ((uint32_t)0x00000020) /*!< usart receive data buffer full flag */
+#define USART_TDC_FLAG ((uint32_t)0x00000040) /*!< usart transmit data complete flag */
+#define USART_TDBE_FLAG ((uint32_t)0x00000080) /*!< usart transmit data buffer empty flag */
+#define USART_BFF_FLAG ((uint32_t)0x00000100) /*!< usart break frame flag */
+#define USART_CTSCF_FLAG ((uint32_t)0x00000200) /*!< usart cts change flag */
+#define USART_RTODF_FLAG ((uint32_t)0x00000800) /*!< usart cts change flag */
+#define USART_CMDF_FLAG ((uint32_t)0x00020000) /*!< usart character match detection flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_interrupts_definition
+ * @brief usart interrupt
+ * @{
+ */
+
+#define USART_IDLE_INT MAKE_VALUE(0x0C,0x04) /*!< usart idle interrupt */
+#define USART_RDBF_INT MAKE_VALUE(0x0C,0x05) /*!< usart receive data buffer full interrupt */
+#define USART_TDC_INT MAKE_VALUE(0x0C,0x06) /*!< usart transmit data complete interrupt */
+#define USART_TDBE_INT MAKE_VALUE(0x0C,0x07) /*!< usart transmit data buffer empty interrupt */
+#define USART_PERR_INT MAKE_VALUE(0x0C,0x08) /*!< usart parity error interrupt */
+#define USART_CMD_INT MAKE_VALUE(0x0C,0x0E) /*!< usart character match detection flag interrupt */
+#define USART_RTOD_INT MAKE_VALUE(0x0C,0x1A) /*!< usart receiver time out detection flag interrupt */
+#define USART_BF_INT MAKE_VALUE(0x10,0x06) /*!< usart break frame interrupt */
+#define USART_ERR_INT MAKE_VALUE(0x14,0x00) /*!< usart error interrupt */
+#define USART_CTSCF_INT MAKE_VALUE(0x14,0x0A) /*!< usart cts change interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup USART_exported_types
+ * @{
+ */
+
+/**
+ * @brief usart parity selection type
+ */
+typedef enum
+{
+ USART_PARITY_NONE = 0x00, /*!< usart no parity */
+ USART_PARITY_EVEN = 0x01, /*!< usart even parity */
+ USART_PARITY_ODD = 0x02 /*!< usart odd parity */
+} usart_parity_selection_type;
+
+/**
+ * @brief usart wakeup mode type
+ */
+typedef enum
+{
+ USART_WAKEUP_BY_IDLE_FRAME = 0x00, /*!< usart wakeup by idle frame */
+ USART_WAKEUP_BY_MATCHING_ID = 0x01 /*!< usart wakeup by matching id */
+} usart_wakeup_mode_type;
+
+/**
+ * @brief usart data bit num type
+ */
+typedef enum
+{
+ USART_DATA_7BITS = 0x00, /*!< usart data size is 7 bits */
+ USART_DATA_8BITS = 0x01, /*!< usart data size is 8 bits */
+ USART_DATA_9BITS = 0x02 /*!< usart data size is 9 bits */
+} usart_data_bit_num_type;
+
+/**
+ * @brief usart break frame bit num type
+ */
+typedef enum
+{
+ USART_BREAK_10BITS = 0x00, /*!< usart lin mode berak frame detection 10 bits */
+ USART_BREAK_11BITS = 0x01 /*!< usart lin mode berak frame detection 11 bits */
+} usart_break_bit_num_type;
+
+/**
+ * @brief usart phase of the clock type
+ */
+typedef enum
+{
+ USART_CLOCK_PHASE_1EDGE = 0x00, /*!< usart data capture is done on the clock leading edge */
+ USART_CLOCK_PHASE_2EDGE = 0x01 /*!< usart data capture is done on the clock trailing edge */
+} usart_clock_phase_type;
+
+/**
+ * @brief usart polarity of the clock type
+ */
+typedef enum
+{
+ USART_CLOCK_POLARITY_LOW = 0x00, /*!< usart clock stay low level outside transmission window */
+ USART_CLOCK_POLARITY_HIGH = 0x01 /*!< usart clock stay high level outside transmission window */
+} usart_clock_polarity_type;
+
+/**
+ * @brief usart last bit clock pulse type
+ */
+typedef enum
+{
+ USART_CLOCK_LAST_BIT_NONE = 0x00, /*!< usart clock pulse of the last data bit is not outputted */
+ USART_CLOCK_LAST_BIT_OUTPUT = 0x01 /*!< usart clock pulse of the last data bit is outputted */
+} usart_lbcp_type;
+
+/**
+ * @brief usart stop bit num type
+ */
+typedef enum
+{
+ USART_STOP_1_BIT = 0x00, /*!< usart stop bits num is 1 */
+ USART_STOP_0_5_BIT = 0x01, /*!< usart stop bits num is 0.5 */
+ USART_STOP_2_BIT = 0x02, /*!< usart stop bits num is 2 */
+ USART_STOP_1_5_BIT = 0x03 /*!< usart stop bits num is 1.5 */
+} usart_stop_bit_num_type;
+
+/**
+ * @brief usart hardware flow control type
+ */
+typedef enum
+{
+ USART_HARDWARE_FLOW_NONE = 0x00, /*!< usart without hardware flow */
+ USART_HARDWARE_FLOW_RTS = 0x01, /*!< usart hardware flow only rts */
+ USART_HARDWARE_FLOW_CTS = 0x02, /*!< usart hardware flow only cts */
+ USART_HARDWARE_FLOW_RTS_CTS = 0x03 /*!< usart hardware flow both rts and cts */
+} usart_hardware_flow_control_type;
+
+/**
+ * @brief usart identification bit num type
+ */
+typedef enum
+{
+ USART_ID_FIXED_4_BIT = 0x00, /*!< usart id bit num fixed 4 bits */
+ USART_ID_RELATED_DATA_BIT = 0x01 /*!< usart id bit num related data bits */
+} usart_identification_bit_num_type;
+
+/**
+ * @brief usart de polarity type
+ */
+typedef enum
+{
+ USART_DE_POLARITY_HIGH = 0x00, /*!< usart de polarity high */
+ USART_DE_POLARITY_LOW = 0x01 /*!< usart de polarity low */
+} usart_de_polarity_type;
+
+/**
+ * @brief type define usart register all
+ */
+typedef struct
+{
+ /**
+ * @brief usart sts register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t perr : 1; /* [0] */
+ __IO uint32_t ferr : 1; /* [1] */
+ __IO uint32_t nerr : 1; /* [2] */
+ __IO uint32_t roerr : 1; /* [3] */
+ __IO uint32_t idlef : 1; /* [4] */
+ __IO uint32_t rdbf : 1; /* [5] */
+ __IO uint32_t tdc : 1; /* [6] */
+ __IO uint32_t tdbe : 1; /* [7] */
+ __IO uint32_t bff : 1; /* [8] */
+ __IO uint32_t ctscf : 1; /* [9] */
+ __IO uint32_t reserved1 : 1; /* [10] */
+ __IO uint32_t rtodf : 1; /* [11] */
+ __IO uint32_t reserved2 : 5; /* [16:12] */
+ __IO uint32_t cmdf : 1; /* [17] */
+ __IO uint32_t reserved3 : 14;/* [31:18] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief usart dt register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t dt;
+ struct
+ {
+ __IO uint32_t dt : 9; /* [8:0] */
+ __IO uint32_t reserved1 : 23;/* [31:9] */
+ } dt_bit;
+ };
+
+ /**
+ * @brief usart baudr register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t baudr;
+ struct
+ {
+ __IO uint32_t div : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } baudr_bit;
+ };
+
+ /**
+ * @brief usart ctrl1 register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t ctrl1;
+ struct
+ {
+ __IO uint32_t sbf : 1; /* [0] */
+ __IO uint32_t rm : 1; /* [1] */
+ __IO uint32_t ren : 1; /* [2] */
+ __IO uint32_t ten : 1; /* [3] */
+ __IO uint32_t idleien : 1; /* [4] */
+ __IO uint32_t rdbfien : 1; /* [5] */
+ __IO uint32_t tdcien : 1; /* [6] */
+ __IO uint32_t tdbeien : 1; /* [7] */
+ __IO uint32_t perrien : 1; /* [8] */
+ __IO uint32_t psel : 1; /* [9] */
+ __IO uint32_t pen : 1; /* [10] */
+ __IO uint32_t wum : 1; /* [11] */
+ __IO uint32_t dbn0 : 1; /* [12] */
+ __IO uint32_t uen : 1; /* [13] */
+ __IO uint32_t cmdie : 1; /* [14] */
+ __IO uint32_t reserved1 : 1; /* [15] */
+ __IO uint32_t tcdt : 5; /* [20:16] */
+ __IO uint32_t tsdt : 5; /* [25:21] */
+ __IO uint32_t retodie : 1; /* [26] */
+ __IO uint32_t rtoden : 1; /* [27] */
+ __IO uint32_t dbn1 : 1; /* [28] */
+ __IO uint32_t reserved2 : 3; /* [31:29] */
+ } ctrl1_bit;
+ };
+
+ /**
+ * @brief usart ctrl2 register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t ctrl2;
+ struct
+ {
+ __IO uint32_t idl : 4; /* [3:0] */
+ __IO uint32_t idbn : 1; /* [4] */
+ __IO uint32_t bfbn : 1; /* [5] */
+ __IO uint32_t bfien : 1; /* [6] */
+ __IO uint32_t reserved1 : 1; /* [7] */
+ __IO uint32_t lbcp : 1; /* [8] */
+ __IO uint32_t clkpha : 1; /* [9] */
+ __IO uint32_t clkpol : 1; /* [10] */
+ __IO uint32_t clken : 1; /* [11] */
+ __IO uint32_t stopbn : 2; /* [13:12] */
+ __IO uint32_t linen : 1; /* [14] */
+ __IO uint32_t trpswap : 1; /* [15] */
+ __IO uint32_t rxrev : 1; /* [16] */
+ __IO uint32_t txrev : 1; /* [17] */
+ __IO uint32_t dtrev : 1; /* [18] */
+ __IO uint32_t mtf : 1; /* [19] */
+ __IO uint32_t reserved2 : 8; /* [27:20] */
+ __IO uint32_t idh : 4; /* [31:28] */
+ } ctrl2_bit;
+ };
+
+ /**
+ * @brief usart ctrl3 register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t ctrl3;
+ struct
+ {
+ __IO uint32_t errien : 1; /* [0] */
+ __IO uint32_t irdaen : 1; /* [1] */
+ __IO uint32_t irdalp : 1; /* [2] */
+ __IO uint32_t slben : 1; /* [3] */
+ __IO uint32_t scnacken : 1; /* [4] */
+ __IO uint32_t scmen : 1; /* [5] */
+ __IO uint32_t dmaren : 1; /* [6] */
+ __IO uint32_t dmaten : 1; /* [7] */
+ __IO uint32_t rtsen : 1; /* [8] */
+ __IO uint32_t ctsen : 1; /* [9] */
+ __IO uint32_t ctscfien : 1; /* [10] */
+ __IO uint32_t reserved1 : 3; /* [13:11] */
+ __IO uint32_t rs485en : 1; /* [14] */
+ __IO uint32_t dep : 1; /* [15] */
+ __IO uint32_t reserved2 : 16;/* [31:16] */
+ } ctrl3_bit;
+ };
+
+ /**
+ * @brief usart gdiv register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t gdiv;
+ struct
+ {
+ __IO uint32_t isdiv : 8; /* [7:0] */
+ __IO uint32_t scgt : 8; /* [15:8] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } gdiv_bit;
+ };
+
+ /**
+ * @brief usart rtov register, offset:0x1c
+ */
+ union
+ {
+ __IO uint32_t rtov;
+ struct
+ {
+ __IO uint32_t rtov : 24;/* [23:0] */
+ __IO uint32_t reserved : 8; /* [31:24] */
+ } rtov_bit;
+ };
+
+ /**
+ * @brief usart ifc register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t ifc;
+ struct
+ {
+ __IO uint32_t reserved1 : 11;/* [10:0] */
+ __IO uint32_t rtodfc : 1; /* [11] */
+ __IO uint32_t reserved2 : 5; /* [16:12] */
+ __IO uint32_t cmdfc : 1; /* [17] */
+ __IO uint32_t reserved3 : 14;/* [31:18] */
+ } ifc_bit;
+ };
+} usart_type;
+
+/**
+ * @}
+ */
+
+#define USART1 ((usart_type *) USART1_BASE)
+#define USART2 ((usart_type *) USART2_BASE)
+#define USART3 ((usart_type *) USART3_BASE)
+#define USART4 ((usart_type *) USART4_BASE)
+#define USART5 ((usart_type *) USART5_BASE)
+#define USART6 ((usart_type *) USART6_BASE)
+#define USART7 ((usart_type *) USART7_BASE)
+#define USART8 ((usart_type *) USART8_BASE)
+
+/** @defgroup USART_exported_functions
+ * @{
+ */
+
+void usart_reset(usart_type* usart_x);
+void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type data_bit, usart_stop_bit_num_type stop_bit);
+void usart_parity_selection_config(usart_type* usart_x, usart_parity_selection_type parity);
+void usart_enable(usart_type* usart_x, confirm_state new_state);
+void usart_transmitter_enable(usart_type* usart_x, confirm_state new_state);
+void usart_receiver_enable(usart_type* usart_x, confirm_state new_state);
+void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, usart_clock_phase_type clk_pha, usart_lbcp_type clk_lb);
+void usart_clock_enable(usart_type* usart_x, confirm_state new_state);
+void usart_interrupt_enable(usart_type* usart_x, uint32_t usart_int, confirm_state new_state);
+void usart_dma_transmitter_enable(usart_type* usart_x, confirm_state new_state);
+void usart_dma_receiver_enable(usart_type* usart_x, confirm_state new_state);
+void usart_wakeup_id_set(usart_type* usart_x, uint8_t usart_id);
+void usart_wakeup_mode_set(usart_type* usart_x, usart_wakeup_mode_type wakeup_mode);
+void usart_receiver_mute_enable(usart_type* usart_x, confirm_state new_state);
+void usart_break_bit_num_set(usart_type* usart_x, usart_break_bit_num_type break_bit);
+void usart_lin_mode_enable(usart_type* usart_x, confirm_state new_state);
+void usart_data_transmit(usart_type* usart_x, uint16_t data);
+uint16_t usart_data_receive(usart_type* usart_x);
+void usart_break_send(usart_type* usart_x);
+void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val);
+void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val);
+void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state);
+void usart_smartcard_nack_set(usart_type* usart_x, confirm_state new_state);
+void usart_single_line_halfduplex_select(usart_type* usart_x, confirm_state new_state);
+void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state);
+void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state);
+void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state);
+flag_status usart_flag_get(usart_type* usart_x, uint32_t flag);
+flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag);
+void usart_flag_clear(usart_type* usart_x, uint32_t flag);
+void usart_rs485_delay_time_config(usart_type* usart_x, uint8_t start_delay_time, uint8_t complete_delay_time);
+void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state);
+void usart_id_bit_num_set(usart_type* usart_x, usart_identification_bit_num_type id_bit_num);
+void usart_de_polarity_set(usart_type* usart_x, usart_de_polarity_type de_polarity);
+void usart_rs485_mode_enable(usart_type* usart_x, confirm_state new_state);
+void usart_msb_transmit_first_enable(usart_type* usart_x, confirm_state new_state);
+void usart_dt_polarity_reverse(usart_type* usart_x, confirm_state new_state);
+void usart_transmit_pin_polarity_reverse(usart_type* usart_x, confirm_state new_state);
+void usart_receive_pin_polarity_reverse(usart_type* usart_x, confirm_state new_state);
+void usart_receiver_timeout_detection_enable(usart_type* usart_x, confirm_state new_state);
+void usart_receiver_timeout_value_set(usart_type* usart_x, uint32_t value);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_usb.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_usb.h
new file mode 100644
index 00000000000..77a05bac48d
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_usb.h
@@ -0,0 +1,1421 @@
+/**
+ **************************************************************************
+ * @file at32f45x_usb.h
+ * @brief at32f45x usb header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_USB_H
+#define __AT32F45x_USB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f45x.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @addtogroup USB
+ * @{
+ */
+
+/** @defgroup USB_global_interrupts_definition
+ * @brief usb global interrupt mask
+ * @{
+ */
+
+#define USB_OTG_MODEMIS_INT ((uint32_t)0x00000002) /*!< usb otg mode mismatch interrupt */
+#define USB_OTG_OTGINT_INT ((uint32_t)0x00000004) /*!< usb otg interrupt */
+#define USB_OTG_SOF_INT ((uint32_t)0x00000008) /*!< usb otg sof interrupt */
+#define USB_OTG_RXFLVL_INT ((uint32_t)0x00000010) /*!< usb otg receive fifo non-empty interrupt */
+#define USB_OTG_NPTXFEMP_INT ((uint32_t)0x00000020) /*!< usb otg non-periodic tx fifo empty interrupt */
+#define USB_OTG_GINNAKEFF_INT ((uint32_t)0x00000040) /*!< usb otg global non-periodic in nak effective interrupt */
+#define USB_OTG_GOUTNAKEFF_INT ((uint32_t)0x00000080) /*!< usb otg global out nak effective interrupt */
+#define USB_OTG_ERLYSUSP_INT ((uint32_t)0x00000400) /*!< usb otg early suspend interrupt */
+#define USB_OTG_USBSUSP_INT ((uint32_t)0x00000800) /*!< usb otg suspend interrupt */
+#define USB_OTG_USBRST_INT ((uint32_t)0x00001000) /*!< usb otg reset interrupt */
+#define USB_OTG_ENUMDONE_INT ((uint32_t)0x00002000) /*!< usb otg enumeration done interrupt */
+#define USB_OTG_ISOOUTDROP_INT ((uint32_t)0x00004000) /*!< usb otg isochronous out packet dropped interrut */
+#define USB_OTG_EOPF_INT ((uint32_t)0x00008000) /*!< usb otg eop interrupt */
+#define USB_OTG_IEPT_INT ((uint32_t)0x00040000) /*!< usb otg in endpoint interrupt */
+#define USB_OTG_OEPT_INT ((uint32_t)0x00080000) /*!< usb otg out endpoint interrupt */
+#define USB_OTG_INCOMISOIN_INT ((uint32_t)0x00100000) /*!< usb otg incomplete isochronous in transfer interrupt */
+#define USB_OTG_INCOMPIP_INCOMPISOOUT_INT ((uint32_t)0x00200000) /*!< usb otg incomplete periodic transfer/isochronous out interrupt */
+#define USB_OTG_PRT_INT ((uint32_t)0x01000000) /*!< usb otg host port interrupt */
+#define USB_OTG_HCH_INT ((uint32_t)0x02000000) /*!< usb otg host channel interrupt */
+#define USB_OTG_PTXFEMP_INT ((uint32_t)0x04000000) /*!< usb otg periodic txfifo empty interrupt */
+#define USB_OTG_CONIDSCHG_INT ((uint32_t)0x10000000) /*!< usb otg connector id status change interrupt */
+#define USB_OTG_DISCON_INT ((uint32_t)0x20000000) /*!< usb otg disconnect detected interrupt */
+#define USB_OTG_WKUP_INT ((uint32_t)0x80000000) /*!< usb otg wakeup interrupt */
+
+/**
+ * @}
+ */
+
+/** @defgroup USB_global_interrupt_flags_definition
+ * @brief usb global interrupt flag
+ * @{
+ */
+
+#define USB_OTG_CURMODE ((uint32_t)0x00000001) /*!< usb otg current mode */
+#define USB_OTG_MODEMIS_FLAG ((uint32_t)0x00000002) /*!< usb otg mode mismatch flag */
+#define USB_OTG_OTGINT_FLAG ((uint32_t)0x00000004) /*!< usb otg flag */
+#define USB_OTG_SOF_FLAG ((uint32_t)0x00000008) /*!< usb otg sof flag */
+#define USB_OTG_RXFLVL_FLAG ((uint32_t)0x00000010) /*!< usb otg receive fifo non-empty flag */
+#define USB_OTG_NPTXFEMP_FLAG ((uint32_t)0x00000020) /*!< usb otg non-periodic tx fifo empty flag */
+#define USB_OTG_GINNAKEFF_FLAG ((uint32_t)0x00000040) /*!< usb otg global non-periodic in nak effective flag */
+#define USB_OTG_GOUTNAKEFF_FLAG ((uint32_t)0x00000080) /*!< usb otg global out nak effective flag */
+#define USB_OTG_ERLYSUSP_FLAG ((uint32_t)0x00000400) /*!< usb otg early suspend flag */
+#define USB_OTG_USBSUSP_FLAG ((uint32_t)0x00000800) /*!< usb otg suspend flag */
+#define USB_OTG_USBRST_FLAG ((uint32_t)0x00001000) /*!< usb otg reset flag */
+#define USB_OTG_ENUMDONE_FLAG ((uint32_t)0x00002000) /*!< usb otg enumeration done flag */
+#define USB_OTG_ISOOUTDROP_FLAG ((uint32_t)0x00004000) /*!< usb otg isochronous out packet dropped flag */
+#define USB_OTG_EOPF_FLAG ((uint32_t)0x00008000) /*!< usb otg eop flag */
+#define USB_OTG_IEPT_FLAG ((uint32_t)0x00040000) /*!< usb otg in endpoint flag */
+#define USB_OTG_OEPT_FLAG ((uint32_t)0x00080000) /*!< usb otg out endpoint flag */
+#define USB_OTG_INCOMISOIN_FLAG ((uint32_t)0x00100000) /*!< usb otg incomplete isochronous in transfer flag */
+#define USB_OTG_INCOMPIP_INCOMPISOOUT_FLAG ((uint32_t)0x00200000) /*!< usb otg incomplete periodic transfer/isochronous out flag */
+#define USB_OTG_PRT_FLAG ((uint32_t)0x01000000) /*!< usb otg host port flag */
+#define USB_OTG_HCH_FLAG ((uint32_t)0x02000000) /*!< usb otg host channel flag */
+#define USB_OTG_PTXFEMP_FLAG ((uint32_t)0x04000000) /*!< usb otg periodic txfifo empty flag */
+#define USB_OTG_CONIDSCHG_FLAG ((uint32_t)0x10000000) /*!< usb otg connector id status change flag */
+#define USB_OTG_DISCON_FLAG ((uint32_t)0x20000000) /*!< usb otg disconnect detected flag */
+#define USB_OTG_WKUP_FLAG ((uint32_t)0x80000000) /*!< usb otg wakeup flag */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup USB_global_setting_definition
+ * @brief usb global setting
+ * @{
+ */
+
+/**
+ * @brief usb turnaround time
+ */
+#define USB_TRDTIM_8 0x9 /*!< usb turn around time 8 */
+#define USB_TRDTIM_16 0x5 /*!< usb turn around time 16 */
+
+/**
+ * @brief usb receive status
+ */
+#define USB_OTG_GRXSTSP_EPTNUM ((uint32_t)0x0000000F) /*!< usb device receive packet endpoint number*/
+#define USB_OTG_GRXSTSP_CHNUM ((uint32_t)0x0000000F) /*!< usb host receive packet channel number*/
+#define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< usb receive packet byte count */
+#define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< usb receive packet pid */
+#define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< usb receive packet status */
+
+/**
+ * @brief usb host packet status
+ */
+#define PKTSTS_IN_DATA_PACKET_RECV 0x2 /*!< usb host in data packet received */
+#define PKTSTS_IN_TRANSFER_COMPLETE 0x3 /*!< usb host in transfer completed */
+#define PKTSTS_DATA_BIT_ERROR 0x5 /*!< usb host data toggle error */
+#define PKTSTS_CHANNEL_STOP 0x7 /*!< usb host channel halted */
+
+/**
+ * @brief usb device packet status
+ */
+#define USB_OUT_STS_NAK 0x1 /*!< usb device global out nak */
+#define USB_OUT_STS_DATA 0x2 /*!< usb device out data packet received */
+#define USB_OUT_STS_COMP 0x3 /*!< usb device out transfer completed */
+#define USB_SETUP_STS_COMP 0x4 /*!< usb device setup transcation completed */
+#define USB_SETUP_STS_DATA 0x6 /*!< usb device setup data packet received */
+
+/**
+ * @}
+ */
+
+/** @defgroup USB_host_config_definition
+ * @{
+ */
+
+/**
+ * @brief usb host phy clock
+ */
+#define USB_HCFG_CLK_60M 0 /*!< usb host phy clock 60mhz */
+#define USB_HCFG_CLK_48M 1 /*!< usb host phy clock 48mhz */
+#define USB_HCFG_CLK_6M 2 /*!< usb host phy clock 6mhz */
+
+/**
+ * @brief usb host port status
+ */
+#define USB_OTG_HPRT_PRTCONSTS ((uint32_t)0x00000001) /*!< usb host port connect status */
+#define USB_OTG_HPRT_PRTCONDET ((uint32_t)0x00000002) /*!< usb host port connect detected */
+#define USB_OTG_HPRT_PRTENA ((uint32_t)0x00000004) /*!< usb host port enable */
+#define USB_OTG_HPRT_PRTENCHNG ((uint32_t)0x00000008) /*!< usb host port enable/disable change */
+#define USB_OTG_HPRT_PRTOVRCACT ((uint32_t)0x00000010) /*!< usb host port overcurrent active */
+#define USB_OTG_HPRT_PRTOVRCCHNG ((uint32_t)0x00000020) /*!< usb host port overcurrent change */
+#define USB_OTG_HPRT_PRTRES ((uint32_t)0x00000040) /*!< usb host port resume */
+#define USB_OTG_HPRT_PRTSUSP ((uint32_t)0x00000080) /*!< usb host port suspend */
+#define USB_OTG_HPRT_PRTRST ((uint32_t)0x00000100) /*!< usb host port reset */
+#define USB_OTG_HPRT_PRTLNSTS ((uint32_t)0x00000C00) /*!< usb host port line status */
+#define USB_OTG_HPRT_PRTPWR ((uint32_t)0x00001000) /*!< usb host port power */
+#define USB_OTG_HPRT_PRTSPD ((uint32_t)0x00060000) /*!< usb host port speed */
+
+/**
+ * @brief usb port speed
+ */
+#define USB_PRTSPD_HIGH_SPEED 0 /*!< usb host port high speed */
+#define USB_PRTSPD_FULL_SPEED 1 /*!< usb host port full speed */
+#define USB_PRTSPD_LOW_SPEED 2 /*!< usb host port low speed */
+
+/**
+ * @brief usb host register hcchar bit define
+ */
+#define USB_OTG_HCCHAR_MPS ((uint32_t)0x000007FF) /*!< channel maximum packet size */
+#define USB_OTG_HCCHAR_EPTNUM ((uint32_t)0x00007800) /*!< endpoint number */
+#define USB_OTG_HCCHAR_EPTDIR ((uint32_t)0x00008000) /*!< endpoint direction */
+#define USB_OTG_HCCHAR_LSPDDEV ((uint32_t)0x00020000) /*!< low speed device */
+#define USB_OTG_HCCHAR_EPTYPE ((uint32_t)0x000C0000) /*!< endpoint type */
+#define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< multi count */
+#define USB_OTG_HCCHAR_DEVADDR ((uint32_t)0x1FC00000) /*!< device address */
+#define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< odd frame */
+#define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< channel disable */
+#define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< channel enable */
+
+/**
+ * @brief usb host register hctsiz bit define
+ */
+#define USB_OTG_HCTSIZ_XFERSIZE ((uint32_t)0x0007FFFF) /*!< channel transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< channel packet count */
+#define USB_OTG_HCTSIZ_PID ((uint32_t)0x60000000) /*!< channel pid */
+
+/**
+ * @brief usb host channel interrupt mask
+ */
+#define USB_OTG_HC_XFERCM_INT ((uint32_t)0x00000001) /*!< channel transfer complete interrupt */
+#define USB_OTG_HC_CHHLTDM_INT ((uint32_t)0x00000002) /*!< channel halted interrupt */
+#define USB_OTG_HC_STALLM_INT ((uint32_t)0x00000008) /*!< channel stall interrupt */
+#define USB_OTG_HC_NAKM_INT ((uint32_t)0x00000010) /*!< channel nak interrupt */
+#define USB_OTG_HC_ACKM_INT ((uint32_t)0x00000020) /*!< channel ack interrupt */
+#define USB_OTG_HC_NYETM_INT ((uint32_t)0x00000040) /*!< channel nyet interrupt */
+#define USB_OTG_HC_XACTERRM_INT ((uint32_t)0x00000080) /*!< channel transaction error interrupt */
+#define USB_OTG_HC_BBLERRM_INT ((uint32_t)0x00000100) /*!< channel babble error interrupt */
+#define USB_OTG_HC_FRMOVRRUN_INT ((uint32_t)0x00000200) /*!< channel frame overrun interrupt */
+#define USB_OTG_HC_DTGLERRM_INT ((uint32_t)0x00000400) /*!< channel data toggle interrupt */
+
+/**
+ * @brief usb host channel interrupt flag
+ */
+#define USB_OTG_HC_XFERC_FLAG ((uint32_t)0x00000001) /*!< channel transfer complete flag */
+#define USB_OTG_HC_CHHLTD_FLAG ((uint32_t)0x00000002) /*!< channel halted flag */
+#define USB_OTG_HC_STALL_FLAG ((uint32_t)0x00000008) /*!< channel stall flag */
+#define USB_OTG_HC_NAK_FLAG ((uint32_t)0x00000010) /*!< channel nak flag */
+#define USB_OTG_HC_ACK_FLAG ((uint32_t)0x00000020) /*!< channel ack flag */
+#define USB_OTG_HC_NYET_FLAG ((uint32_t)0x00000040) /*!< channel nyet flag */
+#define USB_OTG_HC_XACTERR_FLAG ((uint32_t)0x00000080) /*!< channel transaction error flag */
+#define USB_OTG_HC_BBLERR_FLAG ((uint32_t)0x00000100) /*!< channel babble error flag */
+#define USB_OTG_HC_FRMOVRRUN_FLAG ((uint32_t)0x00000200) /*!< channel frame overrun flag */
+#define USB_OTG_HC_DTGLERR_FLAG ((uint32_t)0x00000400) /*!< channel data toggle flag */
+
+/**
+ * @}
+ */
+
+
+/** @defgroup USB_device_config_definition
+ * @{
+ */
+/**
+ * @brief usb device periodic frame interval
+ */
+typedef enum
+{
+ DCFG_PERFRINT_80 = 0x00, /*!< periodic frame interval 80% */
+ DCFG_PERFRINT_85 = 0x01, /*!< periodic frame interval 85% */
+ DCFG_PERFRINT_90 = 0x02, /*!< periodic frame interval 90% */
+ DCFG_PERFRINT_95 = 0x03 /*!< periodic frame interval 95% */
+} dcfg_perfrint_type;
+
+
+/**
+ * @brief usb device full speed
+ */
+#define USB_DCFG_FULL_SPEED 3 /*!< device full speed */
+
+/**
+ * @brief usb device ctrl define
+ */
+#define USB_OTG_DCTL_RWKUPSIG ((uint32_t)0x00000001) /*!< usb device remote wakeup signaling */
+#define USB_OTG_DCTL_SFTDISCON ((uint32_t)0x00000002) /*!< usb device soft disconnect */
+#define USB_OTG_DCTL_GNPINNAKSTS ((uint32_t)0x00000004) /*!< usb device global non-periodic in nak status */
+#define USB_OTG_DCTL_GOUTNAKSTS ((uint32_t)0x00000008) /*!< usb device global out nak status */
+#define USB_OTG_DCTL_SGNPINNAK ((uint32_t)0x00000080) /*!< usb device set global non-periodic in nak */
+#define USB_OTG_DCTL_CGNPINNAK ((uint32_t)0x00000100) /*!< usb device clear global non-periodic in nak */
+#define USB_OTG_DCTL_SGOUTNAK ((uint32_t)0x00000200) /*!< usb device set global out nak status */
+#define USB_OTG_DCTL_CGOUTNAK ((uint32_t)0x00000400) /*!< usb device clear global out nak status */
+#define USB_OTG_DCTL_PWROPRGDNE ((uint32_t)0x00000800) /*!< usb device power on programming done */
+
+/**
+ * @brief usb device in endpoint flag
+ */
+#define USB_OTG_DIEPINT_XFERC_FLAG ((uint32_t)0x00000001) /*!< usb device in transfer completed flag */
+#define USB_OTG_DIEPINT_EPTDISD_FLAG ((uint32_t)0x00000002) /*!< usb device endpoint disable flag */
+#define USB_OTG_DIEPINT_TIMEOUT_FLAG ((uint32_t)0x00000008) /*!< usb device in timeout */
+#define USB_OTG_DIEPINT_INTKNTXFEMP_FLAG ((uint32_t)0x00000010) /*!< usb device in token received when tx fifo is empty flag */
+#define USB_OTG_DIEPINT_INEPTNAK_FLAG ((uint32_t)0x00000040) /*!< usb device in endpoint nak effective flag */
+#define USB_OTG_DIEPINT_TXFEMP_FLAG ((uint32_t)0x00000080) /*!< usb device transmit fifo empty flag */
+
+/**
+ * @brief usb device out endpoint flag
+ */
+#define USB_OTG_DOEPINT_XFERC_FLAG ((uint32_t)0x00000001) /*!< usb device out transfer completed flag */
+#define USB_OTG_DOEPINT_EPTDISD_FLAG ((uint32_t)0x00000002) /*!< usb device endpoint disable flag */
+#define USB_OTG_DOEPINT_SETUP_FLAG ((uint32_t)0x00000008) /*!< usb device setup flag */
+#define USB_OTG_DOEPINT_OUTTEPD_FLAG ((uint32_t)0x00000010) /*!< usb device out token recevied when endpoint disable flag */
+#define USB_OTG_DOEPINT_B2BSTUP_FLAG ((uint32_t)0x00000040) /*!< back-to-back setup packets received */
+
+/**
+ * @brief usb device in endpoint fifo space mask
+ */
+#define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< usb device in endpoint tx fifo space avail */
+
+/**
+ * @brief endpoint0 maximum packet size
+ */
+#define USB_EPT0_MPS_64 0 /*!< usb device endpoint 0 maximum packet size 64byte */
+#define USB_EPT0_MPS_32 1 /*!< usb device endpoint 0 maximum packet size 32byte */
+#define USB_EPT0_MPS_16 2 /*!< usb device endpoint 0 maximum packet size 16byte */
+#define USB_EPT0_MPS_8 3 /*!< usb device endpoint 0 maximum packet size 8byte */
+
+/**
+ * @}
+ */
+
+/**
+ * @brief otg fifo size (word)
+ */
+#define OTG_FIFO_SIZE 320 /*!< otg usb total fifo size */
+
+/**
+ * @brief otg host max buffer length (byte)
+ */
+#define USB_MAX_DATA_LENGTH 0x200 /*!< usb host maximum buffer size */
+
+#define OTGFS_USB_GLOBAL
+#define OTGFS_USB_DEVICE
+#define OTGFS_USB_HOST
+
+/** @defgroup USB_exported_enum_types
+ * @{
+ */
+
+/**
+ * @brief usb mode define(device, host, drd)
+ */
+typedef enum
+{
+ OTG_DEVICE_MODE, /*!< usb device mode */
+ OTG_HOST_MODE, /*!< usb host mode */
+ OTG_DRD_MODE /*!< usb drd mode */
+} otg_mode_type;
+
+/**
+ * @brief endpoint type define
+ */
+typedef enum
+{
+ EPT_CONTROL_TYPE = 0x00, /*!< usb endpoint type control */
+ EPT_ISO_TYPE = 0x01, /*!< usb endpoint type iso */
+ EPT_BULK_TYPE = 0x02, /*!< usb endpoint type bulk */
+ EPT_INT_TYPE = 0x03 /*!< usb endpoint type interrupt */
+} endpoint_trans_type;
+
+/**
+ * @brief usb endpoint number define type
+ */
+typedef enum
+{
+ USB_EPT0 = 0x00, /*!< usb endpoint 0 */
+ USB_EPT1 = 0x01, /*!< usb endpoint 1 */
+ USB_EPT2 = 0x02, /*!< usb endpoint 2 */
+ USB_EPT3 = 0x03, /*!< usb endpoint 3 */
+ USB_EPT4 = 0x04, /*!< usb endpoint 4 */
+ USB_EPT5 = 0x05, /*!< usb endpoint 5 */
+ USB_EPT6 = 0x06, /*!< usb endpoint 6 */
+ USB_EPT7 = 0x07 /*!< usb endpoint 7 */
+} usb_endpoint_number_type;
+
+/**
+ * @brief usb endpoint max num define
+ */
+#ifndef USB_EPT_MAX_NUM
+#define USB_EPT_MAX_NUM 8 /*!< usb device support endpoint number */
+#endif
+/**
+ * @brief usb channel max num define
+ */
+#ifndef USB_HOST_CHANNEL_NUM
+#define USB_HOST_CHANNEL_NUM 16 /*!< usb host support channel number */
+#endif
+
+/**
+ * @brief endpoint trans dir type
+ */
+typedef enum
+{
+ EPT_DIR_IN = 0x00, /*!< usb transfer direction in */
+ EPT_DIR_OUT = 0x01 /*!< usb transfer direction out */
+} endpoint_dir_type;
+
+/**
+ * @brief otgfs1 and otgfs2 select type
+ */
+typedef enum
+{
+ USB_OTG1_ID, /*!< usb otg 1 id */
+ USB_OTG2_ID /*!< usb otg 2 id */
+} otg_id_type;
+
+/**
+ * @brief usb clock select
+ */
+typedef enum
+{
+ USB_CLK_HICK, /*!< usb clock use hick */
+ USB_CLK_HEXT /*!< usb clock use hext */
+}usb_clk48_s;
+
+/**
+ * @}
+ */
+
+
+
+/** @defgroup USB_exported_types
+ * @{
+ */
+
+/**
+ * @brief usb endpoint infomation structure definition
+ */
+typedef struct
+{
+ uint8_t eptn; /*!< endpoint register number (0~7) */
+ uint8_t ept_address; /*!< endpoint address */
+ uint8_t inout; /*!< endpoint dir EPT_DIR_IN or EPT_DIR_OUT */
+ uint8_t trans_type; /*!< endpoint type:
+ EPT_CONTROL_TYPE, EPT_BULK_TYPE, EPT_INT_TYPE, EPT_ISO_TYPE*/
+ uint16_t tx_addr; /*!< endpoint tx buffer offset address */
+ uint16_t rx_addr; /*!< endpoint rx buffer offset address */
+ uint32_t maxpacket; /*!< endpoint max packet*/
+ uint8_t is_double_buffer; /*!< endpoint double buffer flag */
+ uint8_t stall; /*!< endpoint is stall state */
+ uint32_t status;
+
+ /* transmission buffer and count */
+ uint8_t *trans_buf; /*!< endpoint transmission buffer */
+ uint32_t total_len; /*!< endpoint transmission lengtg */
+ uint32_t trans_len; /*!< endpoint transmission length*/
+
+ uint32_t last_len; /*!< last transfer length */
+ uint32_t rem0_len; /*!< rem transfer length */
+ uint32_t ept0_slen; /*!< endpoint 0 transfer sum length */
+} usb_ept_info;
+
+
+/**
+ * @brief usb host channel infomation structure definition
+ */
+typedef struct
+{
+ uint8_t ch_num; /*!< host channel number */
+ uint8_t address; /*!< device address */
+ uint8_t dir; /*!< transmission direction */
+ uint8_t ept_num; /*!< device endpoint number */
+ uint8_t ept_type; /*!< channel transmission type */
+ uint32_t maxpacket; /*!< support max packet size */
+ uint8_t data_pid; /*!< data pid */
+ uint8_t speed; /*!< usb speed */
+ uint8_t stall; /*!< channel stall flag */
+ uint32_t status; /*!< channel status */
+ uint32_t state; /*!< channel state */
+ uint32_t urb_sts; /*!< usb channel request block state */
+
+ uint8_t toggle_in; /*!< channel in transfer toggle */
+ uint8_t toggle_out; /*!< channel out transfer toggle */
+
+ /* transmission buffer and count */
+ uint8_t *trans_buf; /* host channel buffer */
+ uint32_t trans_len; /* host channel transmission len */
+ uint32_t trans_count; /* host channel transmission count*/
+} usb_hch_type;
+
+
+typedef struct
+{
+ /**
+ * @brief otgfs control and status register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t gotgctrl;
+ struct
+ {
+ __IO uint32_t reserved1 : 16; /* [15:0] */
+ __IO uint32_t cidsts : 1; /* [16] */
+ __IO uint32_t reserved2 : 4; /* [20:17] */
+ __IO uint32_t curmod : 1; /* [21] */
+ __IO uint32_t reserved3 : 10; /* [31:22] */
+ } gotgctrl_bit;
+ };
+
+ /**
+ * @brief otgfs interrupt register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t gotgint;
+ struct
+ {
+ __IO uint32_t reserved1 : 2; /* [1:0] */
+ __IO uint32_t sesenddet : 1; /* [2] */
+ __IO uint32_t reserved2 : 29; /* [31:3] */
+
+ } gotgint_bit;
+ };
+
+ /**
+ * @brief otgfs gahbcfg configuration register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t gahbcfg;
+ struct
+ {
+ __IO uint32_t glbintmsk : 1; /* [0] */
+ __IO uint32_t reserved1 : 6; /* [6:1] */
+ __IO uint32_t nptxfemplvl : 1; /* [7] */
+ __IO uint32_t ptxfemplvl : 1; /* [8] */
+ __IO uint32_t reserved2 : 23; /* [31:9] */
+ } gahbcfg_bit;
+ };
+
+ /**
+ * @brief otgfs usb configuration register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t gusbcfg;
+ struct
+ {
+ __IO uint32_t toutcal : 3; /* [2:0] */
+ __IO uint32_t reserved1 : 7; /* [9:3] */
+ __IO uint32_t usbtrdtim : 4; /* [13:10] */
+ __IO uint32_t reserved2 : 15; /* [28:14] */
+ __IO uint32_t fhstmode : 1; /* [29] */
+ __IO uint32_t fdevmode : 1; /* [30] */
+ __IO uint32_t cotxpkt : 1; /* [31] */
+ } gusbcfg_bit;
+ };
+
+ /**
+ * @brief otgfs reset register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t grstctl;
+ struct
+ {
+ __IO uint32_t csftrst : 1; /* [0] */
+ __IO uint32_t piusftrst : 1; /* [1] */
+ __IO uint32_t frmcntrst : 1; /* [2] */
+ __IO uint32_t reserved1 : 1; /* [3] */
+ __IO uint32_t rxfflsh : 1; /* [4] */
+ __IO uint32_t txfflsh : 1; /* [5] */
+ __IO uint32_t txfnum : 5; /* [10:6] */
+ __IO uint32_t reserved2 : 20; /* [30:11] */
+ __IO uint32_t ahbidle : 1; /* [31] */
+ } grstctl_bit;
+ };
+
+ /**
+ * @brief otgfs core interrupt register, offset:0x14
+ */
+ union
+ {
+ __IO uint32_t gintsts;
+ struct
+ {
+ __IO uint32_t curmode : 1; /* [0] */
+ __IO uint32_t modemis : 1; /* [1] */
+ __IO uint32_t otgint : 1; /* [2] */
+ __IO uint32_t sof : 1; /* [3] */
+ __IO uint32_t rxflvl : 1; /* [4] */
+ __IO uint32_t nptxfemp : 1; /* [5] */
+ __IO uint32_t ginnakeff : 1; /* [6] */
+ __IO uint32_t goutnakeff : 1; /* [7] */
+ __IO uint32_t reserved1 : 2; /* [9:8]] */
+ __IO uint32_t erlysusp : 1; /* [10] */
+ __IO uint32_t usbsusp : 1; /* [11] */
+ __IO uint32_t usbrst : 1; /* [12] */
+ __IO uint32_t enumdone : 1; /* [13] */
+ __IO uint32_t isooutdrop : 1; /* [14] */
+ __IO uint32_t eopf : 1; /* [15] */
+ __IO uint32_t reserved2 : 2; /* [17:16]] */
+ __IO uint32_t ieptint : 1; /* [18] */
+ __IO uint32_t oeptint : 1; /* [19] */
+ __IO uint32_t incompisoin : 1; /* [20] */
+ __IO uint32_t incompip_incompisoout : 1; /* [21] */
+ __IO uint32_t reserved3 : 2; /* [23:22] */
+ __IO uint32_t prtint : 1; /* [24] */
+ __IO uint32_t hchint : 1; /* [25] */
+ __IO uint32_t ptxfemp : 1; /* [26] */
+ __IO uint32_t reserved4 : 1; /* [27] */
+ __IO uint32_t conidschg : 1; /* [28] */
+ __IO uint32_t disconint : 1; /* [29] */
+ __IO uint32_t reserved5 : 1; /* [30] */
+ __IO uint32_t wkupint : 1; /* [31] */
+ } gintsts_bit;
+ };
+
+ /**
+ * @brief otgfs interrupt mask register, offset:0x18
+ */
+ union
+ {
+ __IO uint32_t gintmsk;
+ struct
+ {
+ __IO uint32_t reserved1 : 1; /* [0] */
+ __IO uint32_t modemismsk : 1; /* [1] */
+ __IO uint32_t otgintmsk : 1; /* [2] */
+ __IO uint32_t sofmsk : 1; /* [3] */
+ __IO uint32_t rxflvlmsk : 1; /* [4] */
+ __IO uint32_t nptxfempmsk : 1; /* [5] */
+ __IO uint32_t ginnakeffmsk : 1; /* [6] */
+ __IO uint32_t goutnakeffmsk : 1; /* [7] */
+ __IO uint32_t reserved2 : 2; /* [9:8]] */
+ __IO uint32_t erlysuspmsk : 1; /* [10] */
+ __IO uint32_t usbsuspmsk : 1; /* [11] */
+ __IO uint32_t usbrstmsk : 1; /* [12] */
+ __IO uint32_t enumdonemsk : 1; /* [13] */
+ __IO uint32_t isooutdropmsk : 1; /* [14] */
+ __IO uint32_t eopfmsk : 1; /* [15] */
+ __IO uint32_t reserved3 : 2; /* [17:16]] */
+ __IO uint32_t ieptintmsk : 1; /* [18] */
+ __IO uint32_t oeptintmsk : 1; /* [19] */
+ __IO uint32_t incompisoinmsk : 1; /* [20] */
+ __IO uint32_t incompip_incompisooutmsk : 1; /* [21] */
+ __IO uint32_t reserved4 : 2; /* [23:22] */
+ __IO uint32_t prtintmsk : 1; /* [24] */
+ __IO uint32_t hchintmsk : 1; /* [25] */
+ __IO uint32_t ptxfempmsk : 1; /* [26] */
+ __IO uint32_t reserved5 : 1; /* [27] */
+ __IO uint32_t conidschgmsk : 1; /* [28] */
+ __IO uint32_t disconintmsk : 1; /* [29] */
+ __IO uint32_t reserved6 : 1; /* [30] */
+ __IO uint32_t wkupintmsk : 1; /* [31] */
+ } gintmsk_bit;
+ };
+
+ /**
+ * @brief otgfs rx status debug read register, offset:0x1C
+ */
+ union
+ {
+ __IO uint32_t grxstsr;
+ struct
+ {
+ __IO uint32_t eptnum : 4; /* [3:0] */
+ __IO uint32_t bcnt : 11; /* [14:4] */
+ __IO uint32_t dpid : 2; /* [16:15] */
+ __IO uint32_t pktsts : 4; /* [20:17] */
+ __IO uint32_t fn : 4; /* [24:21] */
+ __IO uint32_t reserved1 : 7; /* [31:25] */
+ } grxstsr_bit;
+ };
+
+ /**
+ * @brief otgfs rx status read and pop register, offset:0x20
+ */
+ union
+ {
+ __IO uint32_t grxstsp;
+ struct
+ {
+ __IO uint32_t chnum : 4; /* [3:0] */
+ __IO uint32_t bcnt : 11; /* [14:4] */
+ __IO uint32_t dpid : 2; /* [16:15] */
+ __IO uint32_t pktsts : 4; /* [20:17] */
+ __IO uint32_t reserved1 : 11; /* [31:21] */
+ } grxstsp_bit;
+ };
+
+ /**
+ * @brief otgfs rx fifo size register, offset:0x24
+ */
+ union
+ {
+ __IO uint32_t grxfsiz;
+ struct
+ {
+ __IO uint32_t rxfdep : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } grxfsiz_bit;
+ };
+
+ /**
+ * @brief otgfs non-periodic and ept0 tx fifo size register, offset:0x28
+ */
+ union
+ {
+ __IO uint32_t gnptxfsiz_ept0tx;
+ struct
+ {
+ __IO uint32_t nptxfstaddr : 16; /* [15:0] */
+ __IO uint32_t nptxfdep : 16; /* [31:16] */
+ } gnptxfsiz_ept0tx_bit;
+ };
+
+ /**
+ * @brief otgfs non-periodic tx fifo request queue status register, offset:0x2C
+ */
+ union
+ {
+ __IO uint32_t gnptxsts;
+ struct
+ {
+ __IO uint32_t nptxfspcavail : 16; /* [15:0] */
+ __IO uint32_t nptxqspcavail : 8; /* [23:16] */
+ __IO uint32_t nptxqtop : 7; /* [30:24] */
+ __IO uint32_t reserved1 : 1; /* [31] */
+ } gnptxsts_bit;
+ };
+
+ __IO uint32_t reserved2[2];
+
+ /**
+ * @brief otgfs general core configuration register, offset:0x38
+ */
+ union
+ {
+ __IO uint32_t gccfg;
+ struct
+ {
+ __IO uint32_t reserved1 : 16; /* [15:0] */
+ __IO uint32_t pwrdown : 1; /* [16] */
+ __IO uint32_t lp_mode : 1; /* [17] */
+ __IO uint32_t reserved2 : 2; /* [19:18] */
+ __IO uint32_t sofouten : 1; /* [20] */
+ __IO uint32_t vbusig : 1; /* [21] */
+ __IO uint32_t reserved3 : 10; /* [31:22] */
+ } gccfg_bit;
+ };
+
+ /**
+ * @brief otgfs core id register, offset:0x3C
+ */
+ union
+ {
+ __IO uint32_t guid;
+ struct
+ {
+ __IO uint32_t userid : 32; /* [31:0] */
+ } guid_bit;
+ };
+
+ __IO uint32_t reserved3[48];
+
+ /**
+ * @brief otgfs host periodic tx fifo size register, offset:0x100
+ */
+ union
+ {
+ __IO uint32_t hptxfsiz;
+ struct
+ {
+ __IO uint32_t ptxfstaddr : 16; /* [15:0] */
+ __IO uint32_t ptxfsize : 16; /* [31:16] */
+ } hptxfsiz_bit;
+ };
+
+ /**
+ * @brief otgfs host periodic tx fifo size register, offset:0x100
+ */
+ union
+ {
+ __IO uint32_t dieptxfn[7];
+ struct
+ {
+ __IO uint32_t ineptxfstaddr : 16; /* [15:0] */
+ __IO uint32_t ineptxfdep : 16; /* [31:16] */
+ } dieptxfn_bit[7];
+ };
+} otg_global_type;
+
+
+typedef struct
+{
+ /**
+ * @brief otgfs host mode configuration register, offset:0x400
+ */
+ union
+ {
+ __IO uint32_t hcfg;
+ struct
+ {
+ __IO uint32_t fslspclksel : 2; /* [1:0] */
+ __IO uint32_t fslssupp : 1; /* [2] */
+ __IO uint32_t reserved1 : 29; /* [31:3] */
+ } hcfg_bit;
+ };
+
+ /**
+ * @brief otgfs host frame interval register, offset:0x404
+ */
+ union
+ {
+ __IO uint32_t hfir;
+ struct
+ {
+ __IO uint32_t frint : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:15] */
+ } hfir_bit;
+ };
+
+ /**
+ * @brief otgfs host frame number and time remaining register, offset:0x408
+ */
+ union
+ {
+ __IO uint32_t hfnum;
+ struct
+ {
+ __IO uint32_t frnum : 16; /* [15:0] */
+ __IO uint32_t ftrem : 16; /* [31:15] */
+ } hfnum_bit;
+ };
+
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief otgfs host periodic tx fifo request queue register, offset:0x410
+ */
+ union
+ {
+ __IO uint32_t hptxsts;
+ struct
+ {
+ __IO uint32_t ptxfspcavil : 16; /* [15:0] */
+ __IO uint32_t ptxqspcavil : 8; /* [23:16] */
+ __IO uint32_t ptxqtop : 8; /* [31:24] */
+ } hptxsts_bit;
+ };
+
+ /**
+ * @brief otgfs host all channel interrupt register, offset:0x414
+ */
+ union
+ {
+ __IO uint32_t haint;
+ struct
+ {
+ __IO uint32_t haint : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [32:16] */
+ } haint_bit;
+ };
+
+ /**
+ * @brief otgfs host all channel interrupt mask register, offset:0x418
+ */
+ union
+ {
+ __IO uint32_t haintmsk;
+ struct
+ {
+ __IO uint32_t haintmsk : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [32:16] */
+ } haintmsk_bit;
+ };
+
+ __IO uint32_t reserved2[9];
+
+ /**
+ * @brief otgfs host port control and status register, offset:0x440
+ */
+ union
+ {
+ __IO uint32_t hprt;
+ struct
+ {
+ __IO uint32_t prtconsts : 1; /* [0] */
+ __IO uint32_t prtcondet : 1; /* [1] */
+ __IO uint32_t prtena : 1; /* [2] */
+ __IO uint32_t prtenchng : 1; /* [3] */
+ __IO uint32_t prtovrcact : 1; /* [4] */
+ __IO uint32_t prtovrcchng : 1; /* [5] */
+ __IO uint32_t prtres : 1; /* [6] */
+ __IO uint32_t prtsusp : 1; /* [7] */
+ __IO uint32_t prtrst : 1; /* [8] */
+ __IO uint32_t reserved1 : 1; /* [9] */
+ __IO uint32_t prtlnsts : 2; /* [11:10] */
+ __IO uint32_t prtpwr : 1; /* [12] */
+ __IO uint32_t prttsctl : 4; /* [16:13] */
+ __IO uint32_t prtspd : 2; /* [18:17] */
+ __IO uint32_t reserved2 : 13; /* [31:19] */
+
+ } hprt_bit;
+ };
+} otg_host_type;
+
+typedef struct
+{
+ /**
+ * @brief otgfs host channel x characterisic register, offset:0x500
+ */
+ union
+ {
+ __IO uint32_t hcchar;
+ struct
+ {
+ __IO uint32_t mps : 11; /* [10:0] */
+ __IO uint32_t eptnum : 4; /* [14:11] */
+ __IO uint32_t eptdir : 1; /* [15] */
+ __IO uint32_t reserved1 : 1; /* [16] */
+ __IO uint32_t lspddev : 1; /* [17] */
+ __IO uint32_t eptype : 2; /* [19:18] */
+ __IO uint32_t mc : 2; /* [21:20] */
+ __IO uint32_t devaddr : 7; /* [28:22] */
+ __IO uint32_t oddfrm : 1; /* [29] */
+ __IO uint32_t chdis : 1; /* [30] */
+ __IO uint32_t chena : 1; /* [31] */
+ } hcchar_bit;
+ };
+
+ /**
+ * @brief otgfs host channel split control register, offset:0x504
+ */
+ union
+ {
+ __IO uint32_t hcsplt;
+ struct
+ {
+ __IO uint32_t prtaddr : 7; /* [6:0] */
+ __IO uint32_t hubaddr : 7; /* [13:7] */
+ __IO uint32_t xactpos : 2; /* [15:14] */
+ __IO uint32_t compsplt : 1; /* [16] */
+ __IO uint32_t reserved1 : 14; /* [30:17] */
+ __IO uint32_t spltena : 1; /* [31] */
+ } hcsplt_bit;
+ };
+
+ /**
+ * @brief otgfs host channel interrupt register, offset:0x508
+ */
+ union
+ {
+ __IO uint32_t hcint;
+ struct
+ {
+ __IO uint32_t xferc : 1; /* [0] */
+ __IO uint32_t chhltd : 1; /* [1] */
+ __IO uint32_t reserved1 : 1; /* [2] */
+ __IO uint32_t stall : 1; /* [3] */
+ __IO uint32_t nak : 1; /* [4] */
+ __IO uint32_t ack : 1; /* [5] */
+ __IO uint32_t reserved2 : 1; /* [6] */
+ __IO uint32_t xacterr : 1; /* [7] */
+ __IO uint32_t bblerr : 1; /* [8] */
+ __IO uint32_t frmovrun : 1; /* [9] */
+ __IO uint32_t dtglerr : 1; /* [10] */
+ __IO uint32_t reserved3 : 21; /* [31:11] */
+ } hcint_bit;
+ };
+
+ /**
+ * @brief otgfs host channel interrupt mask register, offset:0x50C
+ */
+ union
+ {
+ __IO uint32_t hcintmsk;
+ struct
+ {
+ __IO uint32_t xfercmsk : 1; /* [0] */
+ __IO uint32_t chhltdmsk : 1; /* [1] */
+ __IO uint32_t reserved1 : 1; /* [2] */
+ __IO uint32_t stallmsk : 1; /* [3] */
+ __IO uint32_t nakmsk : 1; /* [4] */
+ __IO uint32_t ackmsk : 1; /* [5] */
+ __IO uint32_t reserved2 : 1; /* [6] */
+ __IO uint32_t xacterrmsk : 1; /* [7] */
+ __IO uint32_t bblerrmsk : 1; /* [8] */
+ __IO uint32_t frmovrunmsk : 1; /* [9] */
+ __IO uint32_t dtglerrmsk : 1; /* [10] */
+ __IO uint32_t reserved3 : 21; /* [31:11] */
+ } hcintmsk_bit;
+ };
+
+ /**
+ * @brief otgfs host channel transfer size register, offset:0x510
+ */
+ union
+ {
+ __IO uint32_t hctsiz;
+ struct
+ {
+ __IO uint32_t xfersize : 19; /* [18:0] */
+ __IO uint32_t pktcnt : 10; /* [28:19] */
+ __IO uint32_t pid : 2; /* [30:29] */
+ __IO uint32_t reserved1 : 1; /* [31] */
+ } hctsiz_bit;
+ };
+ __IO uint32_t reserved3[3];
+
+}otg_hchannel_type;
+
+
+typedef struct
+{
+ /**
+ * @brief otgfs device configuration register, offset:0x800
+ */
+ union
+ {
+ __IO uint32_t dcfg;
+ struct
+ {
+ __IO uint32_t devspd : 2; /* [1:0] */
+ __IO uint32_t nzstsouthshk : 1; /* [2] */
+ __IO uint32_t reserved1 : 1; /* [3] */
+ __IO uint32_t devaddr : 7; /* [10:4] */
+ __IO uint32_t perfrint : 2; /* [12:11] */
+ __IO uint32_t reserved2 : 19; /* [31:13] */
+ } dcfg_bit;
+ };
+
+ /**
+ * @brief otgfs device controls register, offset:0x804
+ */
+ union
+ {
+ __IO uint32_t dctl;
+ struct
+ {
+ __IO uint32_t rwkupsig : 1; /* [0] */
+ __IO uint32_t sftdiscon : 1; /* [1] */
+ __IO uint32_t gnpinnaksts : 1; /* [2] */
+ __IO uint32_t goutnaksts : 1; /* [3] */
+ __IO uint32_t tstctl : 3; /* [6:4] */
+ __IO uint32_t sgnpinak : 1; /* [7] */
+ __IO uint32_t cgnpinak : 1; /* [8] */
+ __IO uint32_t sgoutnak : 1; /* [9] */
+ __IO uint32_t cgoutnak : 1; /* [10] */
+ __IO uint32_t pwroprgdne : 1; /* [11] */
+ __IO uint32_t reserved1 : 20; /* [31:12] */
+ } dctl_bit;
+ };
+
+ /**
+ * @brief otgfs device status register, offset:0x80C
+ */
+ union
+ {
+ __IO uint32_t dsts;
+ struct
+ {
+ __IO uint32_t suspsts : 1; /* [0] */
+ __IO uint32_t enumspd : 2; /* [2:1] */
+ __IO uint32_t eticerr : 1; /* [3] */
+ __IO uint32_t reserved1 : 4; /* [7:4] */
+ __IO uint32_t soffn : 14; /* [21:8] */
+ __IO uint32_t reserved2 : 10; /* [31:22] */
+ } dsts_bit;
+ };
+
+ __IO uint32_t reserved1;
+ /**
+ * @brief otgfs device in endpoint general interrupt mask register, offset:0x810
+ */
+ union
+ {
+ __IO uint32_t diepmsk;
+ struct
+ {
+ __IO uint32_t xfercmsk : 1; /* [0] */
+ __IO uint32_t eptdismsk : 1; /* [1] */
+ __IO uint32_t reserved1 : 1; /* [2] */
+ __IO uint32_t timeoutmsk : 1; /* [3] */
+ __IO uint32_t intkntxfempmsk : 1; /* [4] */
+ __IO uint32_t intkneptmismsk : 1; /* [5] */
+ __IO uint32_t ineptnakmsk : 1; /* [6] */
+ __IO uint32_t reserved2 : 1; /* [7] */
+ __IO uint32_t txfifoudrmsk : 1; /* [8] */
+ __IO uint32_t bnainmsk : 1; /* [9] */
+ __IO uint32_t reserved3 : 22; /* [31:10] */
+ } diepmsk_bit;
+ };
+
+ /**
+ * @brief otgfs device out endpoint general interrupt mask register, offset:0x814
+ */
+ union
+ {
+ __IO uint32_t doepmsk;
+ struct
+ {
+ __IO uint32_t xfercmsk : 1; /* [0] */
+ __IO uint32_t eptdismsk : 1; /* [1] */
+ __IO uint32_t reserved1 : 1; /* [2] */
+ __IO uint32_t setupmsk : 1; /* [3] */
+ __IO uint32_t outtepdmsk : 1; /* [4] */
+ __IO uint32_t reserved2 : 1; /* [5] */
+ __IO uint32_t b2bsetupmsk : 1; /* [6] */
+ __IO uint32_t reserved3 : 1; /* [7] */
+ __IO uint32_t outperrmsk : 1; /* [8] */
+ __IO uint32_t bnaoutmsk : 1; /* [9] */
+ __IO uint32_t reserved4 : 22; /* [31:10] */
+ } doepmsk_bit;
+ };
+
+ /**
+ * @brief otgfs device all endpoint interrupt register, offset:0x818
+ */
+ union
+ {
+ __IO uint32_t daint;
+ struct
+ {
+ __IO uint32_t ineptint : 16; /* [15:0] */
+ __IO uint32_t outeptint : 16; /* [31:16] */
+ } daint_bit;
+ };
+
+ /**
+ * @brief otgfs device all endpoint interrupt mask register, offset:0x81C
+ */
+ union
+ {
+ __IO uint32_t daintmsk;
+ struct
+ {
+ __IO uint32_t ineptmsk : 16; /* [15:0] */
+ __IO uint32_t outeptmsk : 16; /* [31:16] */
+ } daintmsk_bit;
+ };
+
+ __IO uint32_t reserved2[5];
+
+ /**
+ * @brief otgfs device in endpoint fifo empty interrupt mask register, offset:0x834
+ */
+ union
+ {
+ __IO uint32_t diepempmsk;
+ struct
+ {
+ __IO uint32_t ineptxfemsk : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } diepempmsk_bit;
+ };
+
+} otg_device_type;
+
+typedef struct
+{
+ /**
+ * @brief otgfs device out endpoint control register, offset:0x900
+ */
+ union
+ {
+ __IO uint32_t diepctl;
+ struct
+ {
+ __IO uint32_t mps : 11; /* [10:0] */
+ __IO uint32_t reserved1 : 4; /* [14:11] */
+ __IO uint32_t usbacept : 1; /* [15] */
+ __IO uint32_t dpid : 1; /* [16] */
+ __IO uint32_t naksts : 1; /* [17] */
+ __IO uint32_t eptype : 2; /* [19:18] */
+ __IO uint32_t reserved2 : 1; /* [20] */
+ __IO uint32_t stall : 1; /* [21] */
+ __IO uint32_t txfnum : 4; /* [25:22] */
+ __IO uint32_t cnak : 1; /* [26] */
+ __IO uint32_t snak : 1; /* [27] */
+ __IO uint32_t setd0pid : 1; /* [28] */
+ __IO uint32_t setd1pid : 1; /* [29] */
+ __IO uint32_t eptdis : 1; /* [30] */
+ __IO uint32_t eptena : 1; /* [31] */
+ } diepctl_bit;
+ };
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief otgfs device in endpoint interrupt register, offset:0x908
+ */
+ union
+ {
+ __IO uint32_t diepint;
+ struct
+ {
+ __IO uint32_t xferc : 1; /* [0] */
+ __IO uint32_t epdisd : 1; /* [1] */
+ __IO uint32_t reserved1 : 1; /* [2] */
+ __IO uint32_t timeout : 1; /* [3] */
+ __IO uint32_t intkntxfemp : 1; /* [4] */
+ __IO uint32_t reserved2 : 1; /* [5] */
+ __IO uint32_t ineptnak : 1; /* [6] */
+ __IO uint32_t txfemp : 1; /* [7] */
+ __IO uint32_t reserved3 : 24; /* [31:8] */
+ } diepint_bit;
+ };
+ __IO uint32_t reserved2;
+
+ /**
+ * @brief otgfs device in endpoint transfer size register, offset:0x910 + endpoint number * 0x20
+ */
+ union
+ {
+ __IO uint32_t dieptsiz;
+ struct
+ {
+ __IO uint32_t xfersize : 19; /* [18:0] */
+ __IO uint32_t pktcnt : 10; /* [28:19] */
+ __IO uint32_t mc : 2; /* [30:29] */
+ __IO uint32_t reserved1 : 1; /* [31] */
+ } dieptsiz_bit;
+ };
+
+ __IO uint32_t reserved3;
+
+ /**
+ * @brief otgfs device in endpoint tx fifo status register, offset:0x918 + endpoint number * 0x20
+ */
+ union
+ {
+ __IO uint32_t dtxfsts;
+ struct
+ {
+ __IO uint32_t ineptxfsav : 16; /* [15:0] */
+ __IO uint32_t reserved1 : 16; /* [31:16] */
+ } dtxfsts_bit;
+ };
+
+} otg_eptin_type;
+
+typedef struct
+{
+ /**
+ * @brief otgfs device out endpoint control register, offset:0xb00 + endpoint number * 0x20
+ */
+ union
+ {
+ __IO uint32_t doepctl;
+ struct
+ {
+ __IO uint32_t mps : 11; /* [10:0] */
+ __IO uint32_t reserved1 : 4; /* [14:11] */
+ __IO uint32_t usbacept : 1; /* [15] */
+ __IO uint32_t dpid : 1; /* [16] */
+ __IO uint32_t naksts : 1; /* [17] */
+ __IO uint32_t eptype : 2; /* [19:18] */
+ __IO uint32_t snpm : 1; /* [20] */
+ __IO uint32_t stall : 1; /* [21] */
+ __IO uint32_t reserved2 : 4; /* [25:22] */
+ __IO uint32_t cnak : 1; /* [26] */
+ __IO uint32_t snak : 1; /* [27] */
+ __IO uint32_t setd0pid : 1; /* [28] */
+ __IO uint32_t setd1pid : 1; /* [29] */
+ __IO uint32_t eptdis : 1; /* [30] */
+ __IO uint32_t eptena : 1; /* [31] */
+ } doepctl_bit;
+ };
+ __IO uint32_t reserved1;
+
+ /**
+ * @brief otgfs device out endpoint interrupt register, offset:0xb08 + endpoint number * 0x20
+ */
+ union
+ {
+ __IO uint32_t doepint;
+ struct
+ {
+ __IO uint32_t xferc : 1; /* [0] */
+ __IO uint32_t epdisd : 1; /* [1] */
+ __IO uint32_t reserved1 : 1; /* [2] */
+ __IO uint32_t setup : 1; /* [3] */
+ __IO uint32_t outtepd : 1; /* [4] */
+ __IO uint32_t reserved2 : 1; /* [5] */
+ __IO uint32_t b2pstup : 1; /* [6] */
+ __IO uint32_t reserved3 : 25; /* [31:7] */
+ } doepint_bit;
+ };
+ __IO uint32_t reserved2;
+
+ /**
+ * @brief otgfs device out endpoint transfer size register, offset:0xb10 + endpoint number * 0x20
+ */
+ union
+ {
+ __IO uint32_t doeptsiz;
+ struct
+ {
+ __IO uint32_t xfersize : 19; /* [18:0] */
+ __IO uint32_t pktcnt : 10; /* [28:19] */
+ __IO uint32_t rxdpid_setupcnt : 2; /* [30:29] */
+ __IO uint32_t reserved1 : 1; /* [31] */
+ } doeptsiz_bit;
+ };
+} otg_eptout_type;
+
+typedef struct
+{
+ /**
+ * @brief otgfs power and clock gating control registers, offset:0xe00
+ */
+ union
+ {
+ __IO uint32_t pcgcctl;
+ struct
+ {
+ __IO uint32_t stoppclk : 1; /* [0] */
+ __IO uint32_t reserved1 : 3; /* [3:1] */
+ __IO uint32_t suspendm : 1; /* [4] */
+ __IO uint32_t reserved2 : 27; /* [31:5] */
+ } pcgcctl_bit;
+ };
+} otg_pcgcctl_type;
+
+/**
+ * @}
+ */
+
+/** @defgroup USB_exported_functions
+ * @{
+ */
+
+/**
+ * @brief usb host and device offset address
+ */
+#define OTG_HOST_ADDR_OFFSET 0x400 /*!< usb host register offset address */
+#define OTG_HOST_CHANNEL_ADDR_OFFSET 0x500 /*!< usb host channel register offset address */
+#define OTG_DEVICE_ADDR_OFFSET 0x800 /*!< usb device register offset address */
+#define OTG_DEVICE_EPTIN_ADDR_OFFSET 0x900 /*!< usb device endpoint in register offset address */
+#define OTG_DEVICE_EPTOUT_ADDR_OFFSET 0xB00 /*!< usb device endpoint out register offset address */
+#define OTG_PCGCCTL_ADDR_OFFSET 0xE00 /*!< usb power and clock control register offset address */
+#define OTG_FIFO_ADDR_OFFSET 0x1000 /*!< usb fifo offset address */
+
+/**
+ * @brief usb host and device register define
+ */
+#define OTG1_GLOBAL ((otg_global_type *)(OTGFS1_BASE)) /*!< usb otg1 global register */
+#define OTG_PCGCCTL(usbx) ((otg_pcgcctl_type *)((uint32_t)usbx + OTG_PCGCCTL_ADDR_OFFSET)) /*!< usb power and clock control register */
+#define OTG_DEVICE(usbx) ((otg_device_type *)((uint32_t)usbx + OTG_DEVICE_ADDR_OFFSET)) /*!< usb device register */
+#define OTG_HOST(usbx) ((otg_host_type *)((uint32_t)usbx + OTG_HOST_ADDR_OFFSET)) /*!< usb host register */
+#define USB_CHL(usbx, n) ((otg_hchannel_type *)((uint32_t)usbx + OTG_HOST_CHANNEL_ADDR_OFFSET + n * 0x20)) /*!< usb channel n register */
+#define USB_INEPT(usbx, eptn) ((otg_eptin_type *)((uint32_t)usbx + OTG_DEVICE_EPTIN_ADDR_OFFSET + eptn * 0x20)) /*!< usb device endpoint in register */
+#define USB_OUTEPT(usbx, eptn) ((otg_eptout_type *)((uint32_t)usbx + OTG_DEVICE_EPTOUT_ADDR_OFFSET + eptn * 0x20)) /*!< usb device endpoint out register */
+#define USB_FIFO(usbx, eptn) *(__IO uint32_t *)((uint32_t)usbx + OTG_FIFO_ADDR_OFFSET + eptn * 0x1000) /*!< usb fifo address */
+
+
+
+typedef otg_global_type usb_reg_type;
+
+/** @defgroup USB_exported_functions
+ * @{
+ */
+
+#ifdef OTGFS_USB_GLOBAL
+error_status usb_global_reset(otg_global_type *usbx);
+void usb_global_init(otg_global_type *usbx);
+otg_global_type *usb_global_select_core(uint8_t usb_id);
+void usb_flush_tx_fifo(otg_global_type *usbx, uint32_t fifo_num);
+void usb_flush_rx_fifo(otg_global_type *usbx);
+void usb_global_interrupt_enable(otg_global_type *usbx, uint16_t interrupt, confirm_state new_state);
+uint32_t usb_global_get_all_interrupt(otg_global_type *usbx);
+void usb_global_clear_interrupt(otg_global_type *usbx, uint32_t flag);
+void usb_interrupt_enable(otg_global_type *usbx);
+void usb_interrupt_disable(otg_global_type *usbx);
+void usb_set_rx_fifo(otg_global_type *usbx, uint16_t size);
+void usb_set_tx_fifo(otg_global_type *usbx, uint8_t txfifo, uint16_t size);
+void usb_global_set_mode(otg_global_type *usbx, uint32_t mode);
+void usb_global_power_on(otg_global_type *usbx);
+void usb_write_packet(otg_global_type *usbx, uint8_t *pusr_buf, uint16_t num, uint16_t nbytes);
+void usb_read_packet(otg_global_type *usbx, uint8_t *pusr_buf, uint16_t num, uint16_t nbytes);
+void usb_stop_phy_clk(otg_global_type *usbx);
+void usb_open_phy_clk(otg_global_type *usbx);
+#endif
+
+#ifdef OTGFS_USB_DEVICE
+void usb_ept_open(otg_global_type *usbx, usb_ept_info *ept_info);
+void usb_ept_close(otg_global_type *usbx, usb_ept_info *ept_info);
+void usb_ept_stall(otg_global_type *usbx, usb_ept_info *ept_info);
+void usb_ept_clear_stall(otg_global_type *usbx, usb_ept_info *ept_info);
+uint32_t usb_get_all_out_interrupt(otg_global_type *usbx);
+uint32_t usb_get_all_in_interrupt(otg_global_type *usbx);
+uint32_t usb_ept_out_interrupt(otg_global_type *usbx, uint32_t eptn);
+uint32_t usb_ept_in_interrupt(otg_global_type *usbx, uint32_t eptn);
+void usb_ept_out_clear(otg_global_type *usbx, uint32_t eptn, uint32_t flag);
+void usb_ept_in_clear(otg_global_type *usbx, uint32_t eptn, uint32_t flag);
+void usb_set_address(otg_global_type *usbx, uint8_t address);
+void usb_ept0_start(otg_global_type *usbx);
+void usb_ept0_setup(otg_global_type *usbx);
+void usb_connect(otg_global_type *usbx);
+void usb_disconnect(otg_global_type *usbx);
+void usb_remote_wkup_set(otg_global_type *usbx);
+void usb_remote_wkup_clear(otg_global_type *usbx);
+uint8_t usb_suspend_status_get(otg_global_type *usbx);
+#endif
+
+#ifdef OTGFS_USB_HOST
+void usb_port_power_on(otg_global_type *usbx, confirm_state state);
+uint32_t usbh_get_frame(otg_global_type *usbx);
+void usb_hc_enable(otg_global_type *usbx,
+ uint8_t chn,
+ uint8_t ept_num,
+ uint8_t dev_address,
+ uint8_t type,
+ uint16_t maxpacket,
+ uint8_t speed);
+uint32_t usb_hch_read_interrupt(otg_global_type *usbx);
+void usb_host_disable(otg_global_type *usbx);
+void usb_hch_halt(otg_global_type *usbx, uint8_t chn);
+void usbh_fsls_clksel(otg_global_type *usbx, uint8_t clk);
+#endif
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_wdt.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_wdt.h
new file mode 100644
index 00000000000..b703ecd971f
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_wdt.h
@@ -0,0 +1,195 @@
+/**
+ **************************************************************************
+ * @file at32f45x_wdt.h
+ * @brief at32f45x wdt header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_WDT_H
+#define __AT32F45x_WDT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f45x.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @addtogroup WDT
+ * @{
+ */
+
+
+/** @defgroup WDT_flags_definition
+ * @brief wdt flag
+ * @{
+ */
+
+#define WDT_DIVF_UPDATE_FLAG ((uint16_t)0x0001) /*!< wdt division value update complete flag */
+#define WDT_RLDF_UPDATE_FLAG ((uint16_t)0x0002) /*!< wdt reload value update complete flag */
+#define WDT_WINF_UPDATE_FLAG ((uint16_t)0x0004) /*!< wdt window value update complete flag */
+
+/**
+ * @}
+ */
+
+/** @defgroup WDT_exported_types
+ * @{
+ */
+
+/**
+ * @brief wdt division value type
+ */
+typedef enum
+{
+ WDT_CLK_DIV_4 = 0x00, /*!< wdt clock divider value is 4 */
+ WDT_CLK_DIV_8 = 0x01, /*!< wdt clock divider value is 8 */
+ WDT_CLK_DIV_16 = 0x02, /*!< wdt clock divider value is 16 */
+ WDT_CLK_DIV_32 = 0x03, /*!< wdt clock divider value is 32 */
+ WDT_CLK_DIV_64 = 0x04, /*!< wdt clock divider value is 64 */
+ WDT_CLK_DIV_128 = 0x05, /*!< wdt clock divider value is 128 */
+ WDT_CLK_DIV_256 = 0x06 /*!< wdt clock divider value is 256 */
+} wdt_division_type;
+
+/**
+ * @brief wdt cmd value type
+ */
+typedef enum
+{
+ WDT_CMD_LOCK = 0x0000, /*!< disable write protection command */
+ WDT_CMD_UNLOCK = 0x5555, /*!< enable write protection command */
+ WDT_CMD_ENABLE = 0xCCCC, /*!< enable wdt command */
+ WDT_CMD_RELOAD = 0xAAAA /*!< reload command */
+} wdt_cmd_value_type;
+
+/**
+ * @brief type define wdt register all
+ */
+typedef struct
+{
+
+ /**
+ * @brief wdt cmd register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t cmd;
+ struct
+ {
+ __IO uint32_t cmd : 16;/* [15:0] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } cmd_bit;
+ };
+
+ /**
+ * @brief wdt div register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t div;
+ struct
+ {
+ __IO uint32_t div : 3; /* [2:0] */
+ __IO uint32_t reserved1 : 29;/* [31:3] */
+ } div_bit;
+ };
+
+ /**
+ * @brief wdt rld register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t rld;
+ struct
+ {
+ __IO uint32_t rld : 12;/* [11:0] */
+ __IO uint32_t reserved1 : 20;/* [31:12] */
+ } rld_bit;
+ };
+
+ /**
+ * @brief wdt sts register, offset:0x0C
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t divf : 1; /* [0] */
+ __IO uint32_t rldf : 1; /* [1] */
+ __IO uint32_t reserved1 : 30;/* [31:2] */
+ } sts_bit;
+ };
+
+ /**
+ * @brief wdt win register, offset:0x10
+ */
+ union
+ {
+ __IO uint32_t win;
+ struct
+ {
+ __IO uint32_t win : 12;/* [11:0] */
+ __IO uint32_t reserved1 : 20;/* [31:12] */
+ } win_bit;
+ };
+} wdt_type;
+
+/**
+ * @}
+ */
+
+#define WDT ((wdt_type *) WDT_BASE)
+
+/** @defgroup WDT_exported_functions
+ * @{
+ */
+
+void wdt_enable(void);
+void wdt_counter_reload(void);
+void wdt_reload_value_set(uint16_t reload_value);
+void wdt_divider_set(wdt_division_type division);
+void wdt_register_write_enable( confirm_state new_state);
+flag_status wdt_flag_get(uint16_t wdt_flag);
+void wdt_window_counter_set(uint16_t window_cnt);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_wwdt.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_wwdt.h
new file mode 100644
index 00000000000..cbd1bccbbc6
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_wwdt.h
@@ -0,0 +1,157 @@
+/**
+ **************************************************************************
+ * @file at32f45x_wwdt.h
+ * @brief at32f45x wwdt header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_WWDT_H
+#define __AT32F45x_WWDT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f45x.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @addtogroup WWDT
+ * @{
+ */
+
+/** @defgroup WWDT_enable_bit_definition
+ * @brief wwdt enable bit
+ * @{
+ */
+
+#define WWDT_EN_BIT ((uint32_t)0x00000080) /*!< wwdt enable bit */
+
+/**
+ * @}
+ */
+
+/** @defgroup WWDT_exported_types
+ * @{
+ */
+
+/**
+ * @brief wwdt division type
+ */
+typedef enum
+{
+ WWDT_PCLK1_DIV_4096 = 0x00, /*!< wwdt counter clock = (pclk1/4096)/1) */
+ WWDT_PCLK1_DIV_8192 = 0x01, /*!< wwdt counter clock = (pclk1/4096)/2) */
+ WWDT_PCLK1_DIV_16384 = 0x02, /*!< wwdt counter clock = (pclk1/4096)/4) */
+ WWDT_PCLK1_DIV_32768 = 0x03 /*!< wwdt counter clock = (pclk1/4096)/8) */
+} wwdt_division_type;
+
+/**
+ * @brief type define wwdt register all
+ */
+typedef struct
+{
+
+ /**
+ * @brief wwdt ctrl register, offset:0x00
+ */
+ union
+ {
+ __IO uint32_t ctrl;
+ struct
+ {
+ __IO uint32_t cnt : 7; /* [6:0] */
+ __IO uint32_t wwdten : 1; /* [7] */
+ __IO uint32_t reserved1 : 24;/* [31:8] */
+ } ctrl_bit;
+ };
+
+ /**
+ * @brief wwdt cfg register, offset:0x04
+ */
+ union
+ {
+ __IO uint32_t cfg;
+ struct
+ {
+ __IO uint32_t win : 7; /* [6:0] */
+ __IO uint32_t div : 2; /* [8:7] */
+ __IO uint32_t rldien : 1; /* [9] */
+ __IO uint32_t reserved1 : 22;/* [31:10] */
+ } cfg_bit;
+ };
+
+ /**
+ * @brief wwdt cfg register, offset:0x08
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t rldf : 1; /* [0] */
+ __IO uint32_t reserved1 : 31;/* [31:1] */
+ } sts_bit;
+ };
+
+} wwdt_type;
+
+/**
+ * @}
+ */
+
+#define WWDT ((wwdt_type *) WWDT_BASE)
+
+/** @defgroup WWDT_exported_functions
+ * @{
+ */
+
+void wwdt_reset(void);
+void wwdt_divider_set(wwdt_division_type division);
+void wwdt_flag_clear(void);
+void wwdt_enable(uint8_t wwdt_cnt);
+void wwdt_interrupt_enable(void);
+flag_status wwdt_flag_get(void);
+flag_status wwdt_interrupt_flag_get(void);
+void wwdt_counter_set(uint8_t wwdt_cnt);
+void wwdt_window_counter_set(uint8_t window_cnt);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_xmc.h b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_xmc.h
new file mode 100644
index 00000000000..0f6bb436968
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/inc/at32f45x_xmc.h
@@ -0,0 +1,729 @@
+/**
+ **************************************************************************
+ * @file at32f45x_xmc.h
+ * @brief at32f45x xmc header file
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __AT32F45x_XMC_H
+#define __AT32F45x_XMC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "at32f45x.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @addtogroup XMC
+ * @{
+ */
+
+/** @defgroup XMC_exported_types
+ * @{
+ */
+
+/**
+ * @brief xmc data address bus multiplexing type
+ */
+typedef enum
+{
+ XMC_DATA_ADDR_MUX_DISABLE = 0x00000000, /*!< xmc address/data multiplexing disable */
+ XMC_DATA_ADDR_MUX_ENABLE = 0x00000002 /*!< xmc address/data multiplexing enable */
+} xmc_data_addr_mux_type;
+
+/**
+ * @brief xmc burst access mode type
+ */
+typedef enum
+{
+ XMC_BURST_MODE_DISABLE = 0x00000000, /*!< xmc burst mode disable */
+ XMC_BURST_MODE_ENABLE = 0x00000100 /*!< xmc burst mode enable */
+} xmc_burst_access_mode_type;
+
+/**
+ * @brief xmc asynchronous wait type
+ */
+typedef enum
+{
+ XMC_ASYN_WAIT_DISABLE = 0x00000000, /*!< xmc wait signal during asynchronous transfers disbale */
+ XMC_ASYN_WAIT_ENABLE = 0x00008000 /*!< xmc wait signal during asynchronous transfers enable */
+} xmc_asyn_wait_type;
+
+/**
+ * @brief xmc wrapped mode type
+ */
+typedef enum
+{
+ XMC_WRAPPED_MODE_DISABLE = 0x00000000, /*!< xmc direct wrapped burst is disbale */
+ XMC_WRAPPED_MODE_ENABLE = 0x00000400 /*!< xmc direct wrapped burst is enable */
+} xmc_wrap_mode_type;
+
+/**
+ * @brief xmc write operation type
+ */
+typedef enum
+{
+ XMC_WRITE_OPERATION_DISABLE = 0x00000000, /*!< xmc write operations is disable */
+ XMC_WRITE_OPERATION_ENABLE = 0x00001000 /*!< xmc write operations is enable */
+} xmc_write_operation_type;
+
+/**
+ * @brief xmc wait signal type
+ */
+typedef enum
+{
+ XMC_WAIT_SIGNAL_DISABLE = 0x00000000, /*!< xmc nwait signal is disable */
+ XMC_WAIT_SIGNAL_ENABLE = 0x00002000 /*!< xmc nwait signal is enable */
+} xmc_wait_signal_type;
+
+/**
+ * @brief xmc write burst type
+ */
+typedef enum
+{
+ XMC_WRITE_BURST_SYN_DISABLE = 0x00000000, /*!< xmc write operations are always performed in asynchronous mode */
+ XMC_WRITE_BURST_SYN_ENABLE = 0x00080000 /*!< xmc write operations are performed in synchronous mode */
+} xmc_write_burst_type;
+
+/**
+ * @brief xmc extended mode type
+ */
+typedef enum
+{
+ XMC_WRITE_TIMING_DISABLE = 0x00000000, /*!< xmc write timing disable */
+ XMC_WRITE_TIMING_ENABLE = 0x00004000 /*!< xmc write timing enable */
+} xmc_extended_mode_type;
+
+/**
+ * @brief xmc pccard wait type
+ */
+typedef enum
+{
+ XMC_WAIT_OPERATION_DISABLE = 0x00000000, /*!< xmc wait operation for the pc card/nand flash memory bank disable */
+ XMC_WAIT_OPERATION_ENABLE = 0x00000002 /*!< xmc wait operation for the pc card/nand flash memory bank enable */
+} xmc_nand_pccard_wait_type;
+
+/**
+ * @brief xmc nor/sram subbank type
+ */
+typedef enum
+{
+ XMC_BANK1_NOR_SRAM1 = 0x00000000, /*!< xmc nor/sram subbank1 */
+ XMC_BANK1_NOR_SRAM2 = 0x00000001, /*!< xmc nor/sram subbank2 */
+ XMC_BANK1_NOR_SRAM3 = 0x00000002, /*!< xmc nor/sram subbank3 */
+ XMC_BANK1_NOR_SRAM4 = 0x00000003 /*!< xmc nor/sram subbank4 */
+} xmc_nor_sram_subbank_type;
+
+/**
+ * @brief xmc class bank type
+ */
+typedef enum
+{
+ XMC_BANK5_6_SDRAM = 0x00000003 /*!< xmc sdram bank5/6 */
+} xmc_class_bank_type;
+
+/**
+ * @brief xmc memory type
+ */
+typedef enum
+{
+ XMC_DEVICE_SRAM = 0x00000000, /*!< xmc device choice sram */
+ XMC_DEVICE_PSRAM = 0x00000004, /*!< xmc device choice psram */
+ XMC_DEVICE_NOR = 0x00000008 /*!< xmc device choice nor flash */
+} xmc_memory_type;
+
+/**
+ * @brief xmc data width type
+ */
+typedef enum
+{
+ XMC_BUSTYPE_8_BITS = 0x00000000, /*!< xmc databuss width 8bits */
+ XMC_BUSTYPE_16_BITS = 0x00000010 /*!< xmc databuss width 16bits */
+} xmc_data_width_type;
+
+/**
+ * @brief xmc wait signal polarity type
+ */
+typedef enum
+{
+ XMC_WAIT_SIGNAL_LEVEL_LOW = 0x00000000, /*!< xmc nwait active low */
+ XMC_WAIT_SIGNAL_LEVEL_HIGH = 0x00000200 /*!< xmc nwait active high */
+} xmc_wait_signal_polarity_type;
+
+/**
+ * @brief xmc wait timing type
+ */
+typedef enum
+{
+ XMC_WAIT_SIGNAL_SYN_BEFORE = 0x00000000, /*!< xmc nwait signal is active one data cycle before wait state */
+ XMC_WAIT_SIGNAL_SYN_DURING = 0x00000800 /*!< xmc nwait signal is active during wait state */
+} xmc_wait_timing_type;
+
+/**
+ * @brief xmc access mode type
+ */
+typedef enum
+{
+ XMC_ACCESS_MODE_A = 0x00000000, /*!< xmc access mode A */
+ XMC_ACCESS_MODE_B = 0x10000000, /*!< xmc access mode B */
+ XMC_ACCESS_MODE_C = 0x20000000, /*!< xmc access mode C */
+ XMC_ACCESS_MODE_D = 0x30000000 /*!< xmc access mode D */
+} xmc_access_mode_type;
+
+/**
+ * @brief xmc interrupt sources type
+ */
+typedef enum
+{
+ XMC_INT_RISING_EDGE = 0x00000008, /*!< xmc rising edge detection interrupt enable */
+ XMC_INT_LEVEL = 0x00000010, /*!< xmc high-level edge detection interrupt enable */
+ XMC_INT_FALLING_EDGE = 0x00000020, /*!< xmc falling edge detection interrupt enable */
+ XMC_INT_ERR = 0x00004000 /*!< xmc sdram error interrupt enable */
+} xmc_interrupt_sources_type;
+
+/**
+ * @brief xmc interrupt flag type
+ */
+typedef enum
+{
+ XMC_ERR_FLAG = 0x00000001, /*!< xmc sdram error flag */
+ XMC_BUSY_FLAG = 0x00000020 /*!< xmc sdram busy flag */
+} xmc_interrupt_flag_type;
+
+/**
+ * @brief xmc sdram number of column address type
+ */
+typedef enum
+{
+ XMC_COLUMN_8 = 0x00000000, /*!< xmc sdram column address 8bit */
+ XMC_COLUMN_9 = 0x00000001, /*!< xmc sdram column address 9bit */
+ XMC_COLUMN_10 = 0x00000002, /*!< xmc sdram column address 10bit */
+ XMC_COLUMN_11 = 0x00000003 /*!< xmc sdram column address 11bit */
+}xmc_sdram_column_type;
+
+/**
+ * @brief xmc sdram number of row address type
+ */
+typedef enum
+{
+ XMC_ROW_11 = 0x00000000, /*!< xmc sdram row address 11bit */
+ XMC_ROW_12 = 0x00000001, /*!< xmc sdram row address 12bit */
+ XMC_ROW_13 = 0x00000002 /*!< xmc sdram row address 13bit */
+}xmc_sdram_row_type;
+
+/**
+ * @brief xmc sdram memory data bus width type
+ */
+typedef enum
+{
+ XMC_MEM_WIDTH_8 = 0x00000000, /*!< xmc sdram data bus width 8 */
+ XMC_MEM_WIDTH_16 = 0x00000001 /*!< xmc sdram data bus width 16 */
+}xmc_sdram_width_type;
+
+/**
+ * @brief xmc sdram number of internal banks type
+ */
+typedef enum
+{
+ XMC_INBK_2 = 0x00000000, /*!< xmc sdram 2 internal banks */
+ XMC_INBK_4 = 0x00000001 /*!< xmc sdram 4 internal banks */
+}xmc_sdram_inbk_type;
+
+/**
+ * @brief xmc sdram cas latency type
+ */
+typedef enum
+{
+ XMC_CAS_1 = 0x00000001, /*!< xmc sdram cas 1 */
+ XMC_CAS_2 = 0x00000002, /*!< xmc sdram cas 2 */
+ XMC_CAS_3 = 0x00000003 /*!< xmc sdram cas 3 */
+}xmc_sdram_cas_type;
+
+/**
+ * @brief xmc sdram clock div type
+ */
+typedef enum
+{
+ XMC_NO_CLK = 0x00000000, /*!< xmc sdram disable clock */
+ XMC_CLKDIV_1 = 0x00000010, /*!< xmc sdram clock div 1 */
+ XMC_CLKDIV_2 = 0x00000002, /*!< xmc sdram clock div 2 */
+ XMC_CLKDIV_3 = 0x00000003, /*!< xmc sdram clock div 3 */
+ XMC_CLKDIV_4 = 0x00000001 /*!< xmc sdram clock div 4 */
+}xmc_sdram_clkdiv_type;
+
+/**
+ * @brief xmc sdram read delay
+ */
+typedef enum
+{
+ XMC_READ_DELAY_0 = 0x00000000, /*!< xmc sdram no delay */
+ XMC_READ_DELAY_1 = 0x00000001, /*!< xmc sdram delay 1 clock*/
+ XMC_READ_DELAY_2 = 0x00000002, /*!< xmc sdram delay 2 clock */
+}xmc_sdram_rd_delay_type;
+
+/**
+ * @brief xmc sdram bank type
+ */
+typedef enum
+{
+ XMC_SDRAM_BANK1 = 0x00000000, /*!< xmc sdram bank 1 */
+ XMC_SDRAM_BANK2 = 0x00000001 /*!< xmc sdram bank 2 */
+}xmc_sdram_bank_type;
+
+
+/**
+ * @brief xmc sdram timing delay cycle type
+ */
+typedef enum
+{
+ XMC_DELAY_CYCLE_1 = 0x00000000, /*!< xmc sdram timming delay 1 cycle */
+ XMC_DELAY_CYCLE_2 = 0x00000001, /*!< xmc sdram timming delay 2 cycle */
+ XMC_DELAY_CYCLE_3 = 0x00000002, /*!< xmc sdram timming delay 3 cycle */
+ XMC_DELAY_CYCLE_4 = 0x00000003, /*!< xmc sdram timming delay 4 cycle */
+ XMC_DELAY_CYCLE_5 = 0x00000004, /*!< xmc sdram timming delay 5 cycle */
+ XMC_DELAY_CYCLE_6 = 0x00000005, /*!< xmc sdram timming delay 6 cycle */
+ XMC_DELAY_CYCLE_7 = 0x00000006, /*!< xmc sdram timming delay 7 cycle */
+ XMC_DELAY_CYCLE_8 = 0x00000007, /*!< xmc sdram timming delay 8 cycle */
+ XMC_DELAY_CYCLE_9 = 0x00000008, /*!< xmc sdram timming delay 9 cycle */
+ XMC_DELAY_CYCLE_10 = 0x00000009, /*!< xmc sdram timming delay 10 cycle */
+ XMC_DELAY_CYCLE_11 = 0x0000000A, /*!< xmc sdram timming delay 11 cycle */
+ XMC_DELAY_CYCLE_12 = 0x0000000B, /*!< xmc sdram timming delay 12 cycle */
+ XMC_DELAY_CYCLE_13 = 0x0000000C, /*!< xmc sdram timming delay 13 cycle */
+ XMC_DELAY_CYCLE_14 = 0x0000000D, /*!< xmc sdram timming delay 14 cycle */
+ XMC_DELAY_CYCLE_15 = 0x0000000E, /*!< xmc sdram timming delay 15 cycle */
+ XMC_DELAY_CYCLE_16 = 0x0000000F /*!< xmc sdram timming delay 16 cycle */
+}xmc_sdram_delay_type;
+
+
+/**
+ * @brief xmc sdram command type
+ */
+typedef enum
+{
+ XMC_CMD_NORMAL = 0x00000000, /*!< xmc sdram command normal */
+ XMC_CMD_CLK = 0x00000001, /*!< xmc sdram command clock enable */
+ XMC_CMD_PRECHARG_ALL = 0x00000002, /*!< xmc sdram command precharg all bank */
+ XMC_CMD_AUTO_REFRESH = 0x00000003, /*!< xmc sdram command auto refresh */
+ XMC_CMD_LOAD_MODE = 0x00000004, /*!< xmc sdram command load mode register */
+ XMC_CMD_SELF_REFRESH = 0x00000005, /*!< xmc sdram command self refresh */
+ XMC_CMD_POWER_DOWN = 0x00000006 /*!< xmc sdram command power down */
+}xmc_command_type;
+
+/**
+ * @brief xmc sdram command bank select type
+ */
+typedef enum
+{
+ XMC_CMD_BANK1 = 0x00000010, /*!< send xmc sdram command to bank1 */
+ XMC_CMD_BANK2 = 0x00000008, /*!< send xmc sdram command to bank2 */
+ XMC_CMD_BANK1_2 = 0x00000018 /*!< send xmc sdram command to bank1 and bank2 */
+}xmc_cmd_bank1_2_type;
+
+
+/**
+ * @brief xmc sdram bank status type
+ */
+typedef enum
+{
+ XMC_STATUS_NORMAL = 0x00000000, /*!< xmc sdram status normal */
+ XMC_STATUS_SELF_REFRESH = 0x00000001, /*!< xmc sdram status self refresh */
+ XMC_STATUS_POWER_DOWN = 0x00000002, /*!< xmc sdram power down */
+ XMC_STATUS_MASK = 0x00000003 /*!< xmc sdram mask */
+}xmc_bank_status_type;
+
+
+/**
+ * @brief nor/sram banks timing parameters
+ */
+typedef struct
+{
+ xmc_nor_sram_subbank_type subbank; /*!< xmc nor/sram subbank */
+ xmc_extended_mode_type write_timing_enable; /*!< xmc nor/sram write timing enable */
+ uint32_t addr_setup_time; /*!< xmc nor/sram address setup time */
+ uint32_t addr_hold_time; /*!< xmc nor/sram address hold time */
+ uint32_t data_setup_time; /*!< xmc nor/sram data setup time */
+ uint32_t bus_latency_time; /*!< xmc nor/sram bus latency time */
+ uint32_t clk_psc; /*!< xmc nor/sram clock prescale */
+ uint32_t data_latency_time; /*!< xmc nor/sram data latency time */
+ xmc_access_mode_type mode; /*!< xmc nor/sram access mode */
+} xmc_norsram_timing_init_type;
+
+/**
+ * @brief xmc nor/sram init structure definition
+ */
+typedef struct
+{
+ xmc_nor_sram_subbank_type subbank; /*!< xmc nor/sram subbank */
+ xmc_data_addr_mux_type data_addr_multiplex; /*!< xmc nor/sram address/data multiplexing enable */
+ xmc_memory_type device; /*!< xmc nor/sram memory device */
+ xmc_data_width_type bus_type; /*!< xmc nor/sram data bus width */
+ xmc_burst_access_mode_type burst_mode_enable; /*!< xmc nor/sram burst mode enable */
+ xmc_asyn_wait_type asynwait_enable; /*!< xmc nor/sram nwait in asynchronous transfer enable */
+ xmc_wait_signal_polarity_type wait_signal_lv; /*!< xmc nor/sram nwait polarity */
+ xmc_wrap_mode_type wrapped_mode_enable; /*!< xmc nor/sram wrapped enable */
+ xmc_wait_timing_type wait_signal_config; /*!< xmc nor/sram nwait timing configuration */
+ xmc_write_operation_type write_enable; /*!< xmc nor/sram write enable */
+ xmc_wait_signal_type wait_signal_enable; /*!< xmc nor/sram nwait in synchronous transfer enable */
+ xmc_extended_mode_type write_timing_enable; /*!< xmc nor/sram read-write timing different */
+ xmc_write_burst_type write_burst_syn; /*!< xmc nor/sram memory write mode control */
+} xmc_norsram_init_type;
+
+/**
+ * @brief nand and pccard timing parameters xmc
+ */
+
+typedef struct
+{
+ xmc_class_bank_type class_bank; /*!< xmc nand/pccard bank */
+ uint32_t mem_setup_time; /*!< xmc nand/pccard memory setup time */
+ uint32_t mem_waite_time; /*!< xmc nand/pccard memory wait time */
+ uint32_t mem_hold_time; /*!< xmc nand/pccard memory hold time */
+ uint32_t mem_hiz_time; /*!< xmc nand/pccard memory databus high resistance time */
+} xmc_nand_pccard_timinginit_type;
+
+/**
+ * @brief xmc sdram init structure definition
+ */
+
+typedef struct
+{
+ xmc_sdram_bank_type sdram_bank; /*!< xmc sdram bank bype */
+ xmc_sdram_inbk_type internel_banks; /*!< xmc sdram internal banks */
+ xmc_sdram_clkdiv_type clkdiv; /*!< xmc sdram clock div */
+ uint8_t write_protection; /*!< xmc sdram write protection */
+ uint8_t burst_read; /*!< xmc sdram burst read */
+ uint8_t read_delay; /*!< xmc sdram read delay */
+ xmc_sdram_column_type column_address; /*!< xmc sdram column address */
+ xmc_sdram_row_type row_address; /*!< xmc sdram row address */
+ xmc_sdram_cas_type cas; /*!< xmc sdram cas */
+ xmc_sdram_width_type width; /*!< xmc sdram data width */
+} xmc_sdram_init_type;
+
+/**
+ * @brief xmc sdram timing structure definition
+ */
+
+typedef struct
+{
+ xmc_sdram_delay_type tmrd; /*!< mode register program to active delay */
+ xmc_sdram_delay_type txsr; /*!< exit self-refresh to active delay */
+ xmc_sdram_delay_type tras; /*!< self refresh */
+ xmc_sdram_delay_type trc; /*!< refresh to active delay */
+ xmc_sdram_delay_type twr; /*!< write recovery delay */
+ xmc_sdram_delay_type trp; /*!< precharge to active delay */
+ xmc_sdram_delay_type trcd; /*!< row active to read/write delay */
+} xmc_sdram_timing_type;
+
+/**
+ * @brief xmc sdram command structure definition
+ */
+
+typedef struct
+{
+ xmc_command_type cmd; /*!< sdram command */
+ xmc_cmd_bank1_2_type cmd_banks; /*!< which bank send command */
+ uint32_t auto_refresh; /*!< auto refresh times */
+ uint32_t data; /*!< mode register data */
+} xmc_sdram_cmd_type;
+
+typedef struct
+{
+ /**
+ * @brief xmc bank1 bk1ctrl register, offset:0x00+0x08*(x-1) x= 1...4
+ */
+ union
+ {
+ __IO uint32_t bk1ctrl;
+ struct
+ {
+ __IO uint32_t en : 1; /* [0] */
+ __IO uint32_t admuxen : 1; /* [1] */
+ __IO uint32_t dev : 2; /* [3:2] */
+ __IO uint32_t extmdbw : 2; /* [5:4] */
+ __IO uint32_t noren : 1; /* [6] */
+ __IO uint32_t reserved1 : 1; /* [7] */
+ __IO uint32_t syncben : 1; /* [8] */
+ __IO uint32_t nwpol : 1; /* [9] */
+ __IO uint32_t wrapen : 1; /* [10] */
+ __IO uint32_t nwtcfg : 1; /* [11] */
+ __IO uint32_t wen : 1; /* [12] */
+ __IO uint32_t nwsen : 1; /* [13] */
+ __IO uint32_t rwtd : 1; /* [14] */
+ __IO uint32_t nwasen : 1; /* [15] */
+ __IO uint32_t crpgs : 3; /* [18:16] */
+ __IO uint32_t mwmc : 1; /* [19] */
+ __IO uint32_t reserved2 : 12;/* [31:20] */
+ } bk1ctrl_bit;
+ };
+
+ /**
+ * @brief xmc bank1 bk1tmg register, offset:0x04+0x08*(x-1) x= 1...4
+ */
+ union
+ {
+ __IO uint32_t bk1tmg;
+ struct
+ {
+ __IO uint32_t addrst : 4; /* [3:0] */
+ __IO uint32_t addrht : 4; /* [7:4] */
+ __IO uint32_t dtst : 8; /* [15:8] */
+ __IO uint32_t buslat : 4; /* [19:16] */
+ __IO uint32_t clkpsc : 4; /* [23:20] */
+ __IO uint32_t dtlat : 4; /* [27:24] */
+ __IO uint32_t asyncm : 2; /* [29:28] */
+ __IO uint32_t reserved1 : 2; /* [31:30] */
+ } bk1tmg_bit;
+ };
+
+} xmc_bank1_ctrl_tmg_reg_type;
+
+typedef struct
+{
+ /**
+ * @brief xmc bank1 bk1tmgwr register, offset:0x104+0x08*(x-1) x= 1...4
+ */
+ union
+ {
+ __IO uint32_t bk1tmgwr;
+ struct
+ {
+ __IO uint32_t addrst : 4; /* [3:0] */
+ __IO uint32_t addrht : 4; /* [7:4] */
+ __IO uint32_t dtst : 8; /* [15:8] */
+ __IO uint32_t buslat : 4; /* [19:16] */
+ __IO uint32_t reserved1 : 8; /* [27:20] */
+ __IO uint32_t asyncm : 2; /* [29:28] */
+ __IO uint32_t reserved2 : 2; /* [31:30] */
+ } bk1tmgwr_bit;
+ };
+
+ /**
+ * @brief xmc bank1 reserved register
+ */
+ __IO uint32_t reserved1;
+
+} xmc_bank1_tmgwr_reg_type;
+
+/**
+ * @brief xmc bank1 registers
+ */
+typedef struct
+{
+ /**
+ * @brief xmc bank1 ctrl and tmg register, offset:0x00~0x1C
+ */
+ xmc_bank1_ctrl_tmg_reg_type ctrl_tmg_group[4];
+
+ /**
+ * @brief xmc bank1 reserved register, offset:0x20~0x100
+ */
+ __IO uint32_t reserved1[57];
+
+ /**
+ * @brief xmc bank1 tmgwr register, offset:0x104~0x11C
+ */
+ xmc_bank1_tmgwr_reg_type tmgwr_group[4];
+
+ /**
+ * @brief xmc bank1 reserved register, offset:0x120~0x220
+ */
+ __IO uint32_t reserved2[63];
+
+ /**
+ * @brief xmc bank1 ext register, offset:0x220~0x22C
+ */
+ union
+ {
+ __IO uint32_t ext[4];
+ struct
+ {
+ __IO uint32_t buslatw2w : 8; /* [7:0] */
+ __IO uint32_t buslatr2r : 8; /* [15:8] */
+ __IO uint32_t reserved1 : 16;/* [31:16] */
+ } ext_bit[4];
+ };
+
+} xmc_bank1_type;
+
+/**
+ * @brief xmc sdram type
+ */
+typedef struct
+{
+ /**
+ * @brief xmc sdram ctrl register, offset:0x140~0x144
+ */
+ union
+ {
+ __IO uint32_t ctrl[2];
+ struct
+ {
+ __IO uint32_t ca : 2; /* [1:0] */
+ __IO uint32_t ra : 2; /* [3:2] */
+ __IO uint32_t db : 2; /* [5:4] */
+ __IO uint32_t inbk : 1; /* [6] */
+ __IO uint32_t cas : 2; /* [8:7] */
+ __IO uint32_t wrp : 1; /* [9] */
+ __IO uint32_t clkdiv : 2; /* [11:10] */
+ __IO uint32_t bstr : 1; /* [12] */
+ __IO uint32_t rd : 2; /* [14:13] */
+ __IO uint32_t reserved1 : 17;/* [31:15] */
+ } ctrl_bit[2];
+ };
+
+ /**
+ * @brief xmc sdram tm register, offset:0x148~0x14C
+ */
+ union
+ {
+ __IO uint32_t tm[2];
+ struct
+ {
+ __IO uint32_t tmrd : 4; /* [3:0] */
+ __IO uint32_t txsr : 4; /* [7:4] */
+ __IO uint32_t tras : 4; /* [11:8] */
+ __IO uint32_t trc : 4; /* [15:12] */
+ __IO uint32_t twr : 4; /* [19:16] */
+ __IO uint32_t trp : 4; /* [23:20] */
+ __IO uint32_t trcd : 4; /* [27:24] */
+ __IO uint32_t reserved1 : 4; /* [31:28] */
+ } tm_bit[2];
+
+ };
+
+/**
+ * @brief xmc sdram cmd register, offset:0x150
+ */
+ union
+ {
+ __IO uint32_t cmd;
+ struct
+ {
+ __IO uint32_t cmd : 3; /* [2:0] */
+ __IO uint32_t bk2 : 1; /* [3] */
+ __IO uint32_t bk1 : 1; /* [4] */
+ __IO uint32_t art : 4; /* [8:5] */
+ __IO uint32_t mrd : 13;/* [21:9] */
+ __IO uint32_t reserved1 : 10;/* [31:22] */
+ } cmd_bit;
+ };
+
+ /**
+ * @brief xmc sdram rcnt register, offset:0x154
+ */
+ union
+ {
+ __IO uint32_t rcnt;
+ struct
+ {
+ __IO uint32_t errc : 1; /* [0] */
+ __IO uint32_t rc : 13;/* [13:1] */
+ __IO uint32_t erien : 1; /* [14] */
+ __IO uint32_t reserved1 : 17;/* [31:15] */
+ } rcnt_bit;
+ };
+
+ /**
+ * @brief xmc sdram sts register, offset:0x158
+ */
+ union
+ {
+ __IO uint32_t sts;
+ struct
+ {
+ __IO uint32_t err : 1; /* [0] */
+ __IO uint32_t bk1sts : 2; /* [2:1] */
+ __IO uint32_t bk2sts : 2; /* [4:3] */
+ __IO uint32_t busy : 1; /* [5] */
+ __IO uint32_t reserved1 : 26;/* [31:6] */
+ } sts_bit;
+ };
+ __IO uint32_t reserved1[9];
+
+ /**
+ * @brief xmc sdram clkdiv1, offset:0x180
+ */
+ union
+ {
+ __IO uint32_t clkdiv1;
+ struct
+ {
+ __IO uint32_t reserved1 : 4; /* [3:0] */
+ __IO uint32_t clkdiv1 : 1; /* [4] */
+ __IO uint32_t reserved2 : 27;/* [31:5] */
+ } clkdiv1_bit;
+ };
+}xmc_sdram_type;
+
+/**
+ * @}
+ */
+
+#define XMC_BANK1 ((xmc_bank1_type *) XMC_BANK1_REG_BASE)
+#define XMC_SDRAM ((xmc_sdram_type *) XMC_SDRAM_REG_BASE)
+
+/** @defgroup XMC_exported_functions
+ * @{
+ */
+
+void xmc_nor_sram_reset(xmc_nor_sram_subbank_type xmc_subbank);
+void xmc_nor_sram_init(xmc_norsram_init_type* xmc_norsram_init_struct);
+void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
+ xmc_norsram_timing_init_type* xmc_w_timing_struct);
+void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_struct);
+void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
+ xmc_norsram_timing_init_type* xmc_w_timing_struct);
+void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state);
+void xmc_ext_timing_config(volatile xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing);
+void xmc_interrupt_enable(xmc_class_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state);
+flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
+void xmc_flag_clear(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
+void xmc_sdram_reset(xmc_sdram_bank_type xmc_bank);
+void xmc_sdram_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing_type *xmc_sdram_timing_struct);
+void xmc_sdram_default_para_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing_type *xmc_sdram_timing_struct);
+void xmc_sdram_cmd(xmc_sdram_cmd_type *xmc_sdram_cmd_struct);
+uint32_t xmc_sdram_status_get(xmc_sdram_bank_type xmc_bank);
+void xmc_sdram_refresh_counter_set(uint32_t counter);
+void xmc_sdram_auto_refresh_set(uint32_t number);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_acc.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_acc.c
new file mode 100644
index 00000000000..7604ee45ade
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_acc.c
@@ -0,0 +1,233 @@
+/**
+ **************************************************************************
+ * @file at32f45x_acc.c
+ * @brief contains all the functions for the acc firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup ACC
+ * @brief ACC driver modules
+ * @{
+ */
+
+#ifdef ACC_MODULE_ENABLED
+
+/** @defgroup ACC_private_functions
+ * @{
+ */
+
+/**
+ * @brief enable or disable the acc calibration mode.
+ * @param acc_trim: specifies the acc calibration type.
+ * this parameter can be one of the following values:
+ * - ACC_CAL_HICKCAL
+ * - ACC_CAL_HICKTRIM
+ * @param new_state: specifies the acc calibration to be enabled or disabled.(TRUE or FALSE)
+ * @retval none
+ */
+void acc_calibration_mode_enable(uint16_t acc_trim, confirm_state new_state)
+{
+ if(acc_trim == ACC_CAL_HICKCAL)
+ {
+ ACC->ctrl1_bit.entrim = FALSE;
+ }
+ else
+ {
+ ACC->ctrl1_bit.entrim = TRUE;
+ }
+ ACC->ctrl1_bit.calon = new_state;
+}
+
+/**
+ * @brief store calibration step data in acc's ctrl1 register.
+ * @param step_value: value to be stored in the acc's ctrl1 register
+ * @retval none
+ */
+void acc_step_set(uint8_t step_value)
+{
+ ACC->ctrl1_bit.step = step_value;
+}
+
+
+/**
+ * @brief enable or disable the specified acc interrupts.
+ * @param acc_int: specifies the acc interrupt sources to be enabled or disabled.
+ * this parameter can be one of the following values:
+ * - ACC_CALRDYIEN_INT
+ * - ACC_EIEN_INT
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void acc_interrupt_enable(uint16_t acc_int, confirm_state new_state)
+{
+ if(acc_int == ACC_CALRDYIEN_INT)
+ {
+ ACC->ctrl1_bit.calrdyien = new_state;
+ }
+ else
+ {
+ ACC->ctrl1_bit.eien = new_state;
+ }
+}
+
+/**
+ * @brief return the current acc hicktrim value.
+ * @param none
+ * @retval 8-bit hicktrim value.
+ */
+uint8_t acc_hicktrim_get(void)
+{
+ return ((uint8_t)(ACC->ctrl2_bit.hicktrim));
+}
+
+/**
+ * @brief return the current acc hickcal value.
+ * @param none
+ * @retval 8-bit hicktrim value.
+ */
+uint8_t acc_hickcal_get(void)
+{
+ return ((uint8_t)(ACC->ctrl2_bit.hickcal));
+}
+
+/**
+ * @brief wtire the value to acc c1 register.
+ * @param acc_c1_value
+ * @retval none.
+ */
+void acc_write_c1(uint16_t acc_c1_value)
+{
+ ACC->c1 = acc_c1_value;
+}
+
+/**
+ * @brief wtire the value to acc c2 register.
+ * @param acc_c2_value
+ * @retval none.
+ */
+void acc_write_c2(uint16_t acc_c2_value)
+{
+ ACC->c2 = acc_c2_value;
+}
+
+/**
+ * @brief wtire the value to acc c3 register.
+ * @param acc_c3_value
+ * @retval none.
+ */
+void acc_write_c3(uint16_t acc_c3_value)
+{
+ ACC->c3 = acc_c3_value;
+}
+
+/**
+ * @brief return the current acc c1 value.
+ * @param none
+ * @retval 16-bit c1 value.
+ */
+uint16_t acc_read_c1(void)
+{
+ return ((uint16_t)(ACC->c1));
+}
+
+/**
+ * @brief return the current acc c2 value.
+ * @param none
+ * @retval 16-bit c2 value.
+ */
+uint16_t acc_read_c2(void)
+{
+ return ((uint16_t)(ACC->c2));
+}
+
+/**
+ * @brief return the current acc c3 value.
+ * @param none
+ * @retval 16-bit c3 value.
+ */
+uint16_t acc_read_c3(void)
+{
+ return ((uint16_t)(ACC->c3));
+}
+
+/**
+ * @brief check whether the specified acc flag is set or not.
+ * @param acc_flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - ACC_RSLOST_FLAG
+ * - ACC_CALRDY_FLAG
+ * @retval flag_status (SET or RESET)
+ */
+flag_status acc_flag_get(uint16_t acc_flag)
+{
+ if(acc_flag == ACC_CALRDY_FLAG)
+ return (flag_status)(ACC->sts_bit.calrdy);
+ else
+ return (flag_status)(ACC->sts_bit.rslost);
+}
+
+/**
+ * @brief check whether the specified acc interrupt flag is set or not.
+ * @param acc_flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - ACC_RSLOST_FLAG
+ * - ACC_CALRDY_FLAG
+ * @retval flag_status (SET or RESET)
+ */
+flag_status acc_interrupt_flag_get(uint16_t acc_flag)
+{
+ if(acc_flag == ACC_CALRDY_FLAG)
+ return (flag_status)(ACC->sts_bit.calrdy && ACC->ctrl1_bit.calrdyien);
+ else
+ return (flag_status)(ACC->sts_bit.rslost && ACC->ctrl1_bit.eien);
+}
+
+/**
+ * @brief clear the specified acc flag is set or not.
+ * @param acc_flag: specifies the flag to check.
+ * this parameter can be any combination of the following values:
+ * - ACC_RSLOST_FLAG
+ * - ACC_CALRDY_FLAG
+ * @retval none
+ */
+void acc_flag_clear(uint16_t acc_flag)
+{
+ ACC->sts = ~acc_flag;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_adc.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_adc.c
new file mode 100644
index 00000000000..dce18fc08b0
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_adc.c
@@ -0,0 +1,1163 @@
+/**
+ **************************************************************************
+ * @file at32f45x_adc.c
+ * @brief contains all the functions for the adc firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup ADC
+ * @brief ADC driver modules
+ * @{
+ */
+
+#ifdef ADC_MODULE_ENABLED
+
+/** @defgroup ADC_private_functions
+ * @{
+ */
+
+/**
+ * @brief deinitialize the adc peripheral registers to their default reset values.
+ * @param none
+ * @retval none
+ */
+void adc_reset(void)
+{
+ crm_periph_reset(CRM_ADC_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_ADC_PERIPH_RESET, FALSE);
+}
+
+/**
+ * @brief enable or disable the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param new_state: new state of a/d converter.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ctrl2_bit.adcen = new_state;
+}
+
+/**
+ * @brief adc base default para init.
+ * @param sequence_mode: set the state of adc sequence mode.
+ * this parameter can be:TRUE or FALSE
+ * @param repeat_mode: set the state of adc repeat conversion mode.
+ * this parameter can be:TRUE or FALSE
+ * @param data_align: set the state of adc data alignment.
+ * this parameter can be one of the following values:
+ * - ADC_RIGHT_ALIGNMENT
+ * - ADC_LEFT_ALIGNMENT
+ * @param ordinary_channel_length: configure the adc ordinary channel sequence length.
+ * this parameter can be:
+ * - (0x1~0xf)
+ * @retval none
+ */
+void adc_base_default_para_init(adc_base_config_type *adc_base_struct)
+{
+ adc_base_struct->sequence_mode = FALSE;
+ adc_base_struct->repeat_mode = FALSE;
+ adc_base_struct->data_align = ADC_RIGHT_ALIGNMENT;
+ adc_base_struct->ordinary_channel_length = 1;
+}
+
+/**
+ * @brief initialize the adc peripheral according to the specified parameters.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param sequence_mode: set the state of adc sequence mode.
+ * this parameter can be:TRUE or FALSE
+ * @param repeat_mode: set the state of adc repeat conversion mode.
+ * this parameter can be:TRUE or FALSE
+ * @param data_align: set the state of adc data alignment.
+ * this parameter can be one of the following values:
+ * - ADC_RIGHT_ALIGNMENT
+ * - ADC_LEFT_ALIGNMENT
+ * @param ordinary_channel_length: configure the adc ordinary channel sequence length.
+ * this parameter can be:
+ * - (0x1~0xf)
+ * @retval none
+ */
+void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct)
+{
+ adc_x->ctrl1_bit.sqen = adc_base_struct->sequence_mode;
+ adc_x->ctrl2_bit.rpen = adc_base_struct->repeat_mode;
+ adc_x->ctrl2_bit.dtalign = adc_base_struct->data_align;
+ adc_x->osq1_bit.oclen = adc_base_struct->ordinary_channel_length - 1;
+}
+
+/**
+ * @brief adc common default para init.
+ * @param combine_mode: configure the adc combine_mode mode.
+ * this parameter can be one of the following values:
+ * - ADC_INDEPENDENT_MODE - ADC_ORDINARY_SMLT_PREEMPT_SMLT_ONESLAVE_MODE - ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_ONESLAVE_MODE
+ * - ADC_PREEMPT_SMLT_ONLY_ONESLAVE_MODE - ADC_ORDINARY_SMLT_ONLY_ONESLAVE_MODE - ADC_ORDINARY_SHIFT_ONLY_ONESLAVE_MODE
+ * - ADC_PREEMPT_INTERLTRIG_ONLY_ONESLAVE_MODE
+ * @param div: configure the adc division.
+ * this parameter can be one of the following values:
+ * - ADC_HCLK_DIV_2 - ADC_HCLK_DIV_3 - ADC_HCLK_DIV_4 - ADC_HCLK_DIV_5
+ * - ADC_HCLK_DIV_6 - ADC_HCLK_DIV_7 - ADC_HCLK_DIV_8 - ADC_HCLK_DIV_9
+ * - ADC_HCLK_DIV_10 - ADC_HCLK_DIV_11 - ADC_HCLK_DIV_12 - ADC_HCLK_DIV_13
+ * - ADC_HCLK_DIV_14 - ADC_HCLK_DIV_15 - ADC_HCLK_DIV_16 - ADC_HCLK_DIV_17
+ * @param common_dma_mode: configure the adc common dma mode.
+ * this parameter can be one of the following values:
+ * - ADC_COMMON_DMAMODE_DISABLE
+ * - ADC_COMMON_DMAMODE_1
+ * - ADC_COMMON_DMAMODE_2
+ * - ADC_COMMON_DMAMODE_3
+ * @param common_dma_request_repeat_state: set the adc common dma request repeat state.
+ * this parameter can be:TRUE or FALSE
+ * @param sampling_interval: configure the ordinary shifting mode adjacent adc sampling interval.
+ * this parameter can be one of the following values:
+ * - ADC_SAMPLING_INTERVAL_5CYCLES - ADC_SAMPLING_INTERVAL_6CYCLES - ADC_SAMPLING_INTERVAL_7CYCLES - ADC_SAMPLING_INTERVAL_8CYCLES
+ * - ADC_SAMPLING_INTERVAL_9CYCLES - ADC_SAMPLING_INTERVAL_10CYCLES - ADC_SAMPLING_INTERVAL_11CYCLES - ADC_SAMPLING_INTERVAL_12CYCLES
+ * - ADC_SAMPLING_INTERVAL_13CYCLES - ADC_SAMPLING_INTERVAL_14CYCLES - ADC_SAMPLING_INTERVAL_15CYCLES - ADC_SAMPLING_INTERVAL_16CYCLES
+ * - ADC_SAMPLING_INTERVAL_17CYCLES - ADC_SAMPLING_INTERVAL_18CYCLES - ADC_SAMPLING_INTERVAL_19CYCLES - ADC_SAMPLING_INTERVAL_20CYCLES
+ * @param tempervintrv_state: set the adc temperature sensor and vintrv state.
+ * this parameter can be:TRUE or FALSE
+ * @param vbat_state: set the adc voltage battery state.
+ * this parameter can be:TRUE or FALSE
+ * @retval none
+ */
+void adc_common_default_para_init(adc_common_config_type *adc_common_struct)
+{
+ adc_common_struct->combine_mode = ADC_INDEPENDENT_MODE;
+ adc_common_struct->div = ADC_HCLK_DIV_2;
+ adc_common_struct->common_dma_mode = ADC_COMMON_DMAMODE_DISABLE;
+ adc_common_struct->common_dma_request_repeat_state = FALSE;
+ adc_common_struct->sampling_interval = ADC_SAMPLING_INTERVAL_5CYCLES;
+ adc_common_struct->tempervintrv_state = FALSE;
+ adc_common_struct->vbat_state = FALSE;
+}
+
+/**
+ * @brief adc common default para init.
+ * @param combine_mode: configure the adc combine_mode.
+ * this parameter can be one of the following values:
+ * - ADC_INDEPENDENT_MODE - ADC_ORDINARY_SMLT_PREEMPT_SMLT_ONESLAVE_MODE - ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_ONESLAVE_MODE
+ * - ADC_PREEMPT_SMLT_ONLY_ONESLAVE_MODE - ADC_ORDINARY_SMLT_ONLY_ONESLAVE_MODE - ADC_ORDINARY_SHIFT_ONLY_ONESLAVE_MODE
+ * - ADC_PREEMPT_INTERLTRIG_ONLY_ONESLAVE_MODE - ADC_ORDINARY_SMLT_PREEMPT_SMLT_TWOSLAVE_MODE - ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_TWOSLAVE_MODE
+ * - ADC_PREEMPT_SMLT_ONLY_TWOSLAVE_MODE - ADC_ORDINARY_SMLT_ONLY_TWOSLAVE_MODE - ADC_ORDINARY_SHIFT_ONLY_TWOSLAVE_MODE
+ * - ADC_PREEMPT_INTERLTRIG_ONLY_TWOSLAVE_MODE
+ * @param div: configure the adc division.
+ * this parameter can be one of the following values:
+ * - ADC_HCLK_DIV_2 - ADC_HCLK_DIV_3 - ADC_HCLK_DIV_4 - ADC_HCLK_DIV_5
+ * - ADC_HCLK_DIV_6 - ADC_HCLK_DIV_7 - ADC_HCLK_DIV_8 - ADC_HCLK_DIV_9
+ * - ADC_HCLK_DIV_10 - ADC_HCLK_DIV_11 - ADC_HCLK_DIV_12 - ADC_HCLK_DIV_13
+ * - ADC_HCLK_DIV_14 - ADC_HCLK_DIV_15 - ADC_HCLK_DIV_16 - ADC_HCLK_DIV_17
+ * @param common_dma_mode: configure the adc common dma mode.
+ * this parameter can be one of the following values:
+ * - ADC_COMMON_DMAMODE_DISABLE
+ * - ADC_COMMON_DMAMODE_1
+ * - ADC_COMMON_DMAMODE_2
+ * - ADC_COMMON_DMAMODE_3
+ * @param common_dma_request_repeat_state: set the adc common dma request repeat state.
+ * this parameter can be:TRUE or FALSE
+ * @param sampling_interval: configure the ordinary shifting mode adjacent adc sampling interval.
+ * this parameter can be one of the following values:
+ * - ADC_SAMPLING_INTERVAL_5CYCLES - ADC_SAMPLING_INTERVAL_6CYCLES - ADC_SAMPLING_INTERVAL_7CYCLES - ADC_SAMPLING_INTERVAL_8CYCLES
+ * - ADC_SAMPLING_INTERVAL_9CYCLES - ADC_SAMPLING_INTERVAL_10CYCLES - ADC_SAMPLING_INTERVAL_11CYCLES - ADC_SAMPLING_INTERVAL_12CYCLES
+ * - ADC_SAMPLING_INTERVAL_13CYCLES - ADC_SAMPLING_INTERVAL_14CYCLES - ADC_SAMPLING_INTERVAL_15CYCLES - ADC_SAMPLING_INTERVAL_16CYCLES
+ * - ADC_SAMPLING_INTERVAL_17CYCLES - ADC_SAMPLING_INTERVAL_18CYCLES - ADC_SAMPLING_INTERVAL_19CYCLES - ADC_SAMPLING_INTERVAL_20CYCLES
+ * @param tempervintrv_state: set the adc temperature sensor and vintrv state.
+ * this parameter can be:TRUE or FALSE
+ * @param vbat_state: set the adc voltage battery state.
+ * this parameter can be:TRUE or FALSE
+ * @retval none
+ */
+void adc_common_config(adc_common_config_type *adc_common_struct)
+{
+ ADCCOM->cctrl_bit.mssel = adc_common_struct->combine_mode;
+ ADCCOM->cctrl_bit.adcdiv = adc_common_struct->div;
+ if(adc_common_struct->common_dma_mode & 0x04)
+ {
+ ADCCOM->cctrl_bit.msdmasel_h = TRUE;
+ }
+ else
+ {
+ ADCCOM->cctrl_bit.msdmasel_h = FALSE;
+ }
+ ADCCOM->cctrl_bit.msdmasel_l = adc_common_struct->common_dma_mode &0x03;
+ ADCCOM->cctrl_bit.msdrcen = adc_common_struct->common_dma_request_repeat_state;
+ ADCCOM->cctrl_bit.asisel = adc_common_struct->sampling_interval;
+ ADCCOM->cctrl_bit.itsrven = adc_common_struct->tempervintrv_state;
+ ADCCOM->cctrl_bit.vbaten = adc_common_struct->vbat_state;
+}
+
+/**
+ * @brief adc combine mode set.
+ * @param combine_mode: configure the adc combine mode.
+ * this parameter can be one of the following values:
+ * - ADC_INDEPENDENT_MODE - ADC_ORDINARY_SMLT_PREEMPT_SMLT_ONESLAVE_MODE - ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_ONESLAVE_MODE
+ * - ADC_PREEMPT_SMLT_ONLY_ONESLAVE_MODE - ADC_ORDINARY_SMLT_ONLY_ONESLAVE_MODE - ADC_ORDINARY_SHIFT_ONLY_ONESLAVE_MODE
+ * - ADC_PREEMPT_INTERLTRIG_ONLY_ONESLAVE_MODE
+ * @retval none
+ */
+void adc_combine_mode_set(adc_combine_mode_type combine_mode)
+{
+ ADCCOM->cctrl_bit.mssel = combine_mode;
+}
+
+/**
+ * @brief get adc combine mode.
+ * @retval the new state of combine mode.
+ */
+uint32_t adc_combine_mode_get(void)
+{
+ return ADCCOM->cctrl_bit.mssel;
+}
+
+/**
+ * @brief enable or disable the adc voltage battery.
+ * @param new_state: new state of the adc voltage battery.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_voltage_battery_enable(confirm_state new_state)
+{
+ ADCCOM->cctrl_bit.vbaten = new_state;
+}
+
+/**
+ * @brief set resolution of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param resolution: set the conversion resolution.
+ * this parameter can be one of the following values:
+ * - ADC_RESOLUTION_12B
+ * - ADC_RESOLUTION_10B
+ * - ADC_RESOLUTION_8B
+ * - ADC_RESOLUTION_6B
+ * @retval none
+ */
+void adc_resolution_set(adc_type *adc_x, adc_resolution_type resolution)
+{
+ adc_x->ctrl1_bit.crsel = resolution;
+}
+
+/**
+ * @brief enable or disable the adc dma transfer.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param new_state: new state of the adc dma transfer.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_dma_mode_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ctrl2_bit.ocdmaen = new_state;
+}
+
+/**
+ * @brief enable or disable the adc dma request repeat.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param new_state: the adc dma request repeat state.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_dma_request_repeat_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ctrl2_bit.ocdrcen = new_state;
+}
+
+/**
+ * @brief enable or disable the specified adc interrupts.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param adc_int: specifies the adc interrupt sources to be enabled or disabled.
+ * this parameter can be one of the following values:
+ * - ADC_OCCE_INT
+ * - ADC_VMOR_INT
+ * - ADC_PCCE_INT
+ * - ADC_OCCO_INT
+ * - ADC_TCF_INT
+ * @param new_state: new state of the specified adc interrupts.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_interrupt_enable(adc_type *adc_x, uint32_t adc_int, confirm_state new_state)
+{
+ if(new_state == TRUE)
+ {
+ adc_x->ctrl1 |= adc_int;
+ }
+ else if(new_state == FALSE)
+ {
+ adc_x->ctrl1 &= ~adc_int;
+ }
+}
+
+/**
+ * @brief initialize calibration register of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @retval none
+ */
+void adc_calibration_init(adc_type *adc_x)
+{
+ adc_x->ctrl2_bit.adcalinit = TRUE;
+}
+
+/**
+ * @brief get calibration register's initialize status of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @retval the new state of reset calibration register status(SET or RESET).
+ */
+flag_status adc_calibration_init_status_get(adc_type *adc_x)
+{
+ if(adc_x->ctrl2_bit.adcalinit)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief start calibration process of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @retval none
+ */
+void adc_calibration_start(adc_type *adc_x)
+{
+ adc_x->ctrl2_bit.adcal = TRUE;
+}
+
+/**
+ * @brief get calibration status of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @retval the new state of calibration status(SET or RESET).
+ */
+flag_status adc_calibration_status_get(adc_type *adc_x)
+{
+ if(adc_x->ctrl2_bit.adcal)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief enable or disable the voltage monitoring on single/all ordinary or preempt channels of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param adc_voltage_monitoring: choose the adc_voltage_monitoring config.
+ * this parameter can be one of the following values:
+ * - ADC_VMONITOR_SINGLE_ORDINARY
+ * - ADC_VMONITOR_SINGLE_PREEMPT
+ * - ADC_VMONITOR_SINGLE_ORDINARY_PREEMPT
+ * - ADC_VMONITOR_ALL_ORDINARY
+ * - ADC_VMONITOR_ALL_PREEMPT
+ * - ADC_VMONITOR_ALL_ORDINARY_PREEMPT
+ * - ADC_VMONITOR_NONE
+ * @retval none
+ */
+void adc_voltage_monitor_enable(adc_type *adc_x, adc_voltage_monitoring_type adc_voltage_monitoring)
+{
+ adc_x->ctrl1_bit.ocvmen = FALSE;
+ adc_x->ctrl1_bit.pcvmen = FALSE;
+ adc_x->ctrl1_bit.vmsgen = FALSE;
+ adc_x->ctrl1 |= adc_voltage_monitoring;
+}
+
+/**
+ * @brief set voltage monitoring's high and low thresholds value of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param adc_high_threshold: voltage monitoring's high thresholds value.
+ * this parameter can be:
+ * - (0x0000~0xFFFF)
+ * @param adc_low_threshold: voltage monitoring's low thresholds value.
+ * this parameter can be:
+ * - (0x0000~0xFFFF)
+ * @retval none
+ */
+void adc_voltage_monitor_threshold_value_set(adc_type *adc_x, uint16_t adc_high_threshold, uint16_t adc_low_threshold)
+{
+ adc_x->vmhb_bit.vmhb = adc_high_threshold;
+ adc_x->vmlb_bit.vmlb = adc_low_threshold;
+}
+
+/**
+ * @brief select the voltage monitoring's channel of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param adc_channel: select the channel.
+ * this parameter can be one of the following values:
+ * - ADC_CHANNEL_0 - ADC_CHANNEL_1 - ADC_CHANNEL_2 - ADC_CHANNEL_3
+ * - ADC_CHANNEL_4 - ADC_CHANNEL_5 - ADC_CHANNEL_6 - ADC_CHANNEL_7
+ * - ADC_CHANNEL_8 - ADC_CHANNEL_9 - ADC_CHANNEL_10 - ADC_CHANNEL_11
+ * - ADC_CHANNEL_12 - ADC_CHANNEL_13 - ADC_CHANNEL_14 - ADC_CHANNEL_15
+ * - ADC_CHANNEL_16 - ADC_CHANNEL_17 - ADC_CHANNEL_18
+ * @retval none
+ */
+void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_select_type adc_channel)
+{
+ adc_x->ctrl1_bit.vmcsel = adc_channel;
+}
+
+/**
+ * @brief set ordinary channel's corresponding rank in the sequencer and sample time of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param adc_channel: select the channel.
+ * this parameter can be one of the following values:
+ * - ADC_CHANNEL_0 - ADC_CHANNEL_1 - ADC_CHANNEL_2 - ADC_CHANNEL_3
+ * - ADC_CHANNEL_4 - ADC_CHANNEL_5 - ADC_CHANNEL_6 - ADC_CHANNEL_7
+ * - ADC_CHANNEL_8 - ADC_CHANNEL_9 - ADC_CHANNEL_10 - ADC_CHANNEL_11
+ * - ADC_CHANNEL_12 - ADC_CHANNEL_13 - ADC_CHANNEL_14 - ADC_CHANNEL_15
+ * - ADC_CHANNEL_16 - ADC_CHANNEL_17 - ADC_CHANNEL_18
+ * @param adc_sequence: set rank in the ordinary group sequencer.
+ * this parameter must be:
+ * - between 1 to 16
+ * @param adc_sampletime: set the sampletime of adc channel.
+ * this parameter can be one of the following values:
+ * - ADC_SAMPLETIME_2_5
+ * - ADC_SAMPLETIME_6_5
+ * - ADC_SAMPLETIME_12_5
+ * - ADC_SAMPLETIME_24_5
+ * - ADC_SAMPLETIME_47_5
+ * - ADC_SAMPLETIME_92_5
+ * - ADC_SAMPLETIME_247_5
+ * - ADC_SAMPLETIME_640_5
+ * @retval none
+ */
+void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime)
+{
+ uint32_t tmp_reg;
+ if(adc_channel < ADC_CHANNEL_10)
+ {
+ tmp_reg = adc_x->spt2;
+ tmp_reg &= ~(0x07 << 3 * adc_channel);
+ tmp_reg |= adc_sampletime << 3 * adc_channel;
+ adc_x->spt2 = tmp_reg;
+ }
+ else
+ {
+ tmp_reg = adc_x->spt1;
+ tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10));
+ tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10);
+ adc_x->spt1 = tmp_reg;
+ }
+
+ if(adc_sequence >= 13)
+ {
+ tmp_reg = adc_x->osq1;
+ tmp_reg &= ~(0x01F << 5 * (adc_sequence - 13));
+ tmp_reg |= adc_channel << 5 * (adc_sequence - 13);
+ adc_x->osq1 = tmp_reg;
+ }
+ else if(adc_sequence >= 7)
+ {
+ tmp_reg = adc_x->osq2;
+ tmp_reg &= ~(0x01F << 5 * (adc_sequence - 7));
+ tmp_reg |= adc_channel << 5 * (adc_sequence - 7);
+ adc_x->osq2 = tmp_reg;
+ }
+ else
+ {
+ tmp_reg = adc_x->osq3;
+ tmp_reg &= ~(0x01F << 5 * (adc_sequence - 1));
+ tmp_reg |= adc_channel << 5 * (adc_sequence - 1);
+ adc_x->osq3 = tmp_reg;
+ }
+}
+
+/**
+ * @brief set preempt channel lenghth of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param adc_channel_lenght: set the adc preempt channel lenghth.
+ * this parameter can be:
+ * - (0x1~0x4)
+ * @retval none
+ */
+void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght)
+{
+ adc_x->psq_bit.pclen = adc_channel_lenght - 1;
+}
+
+/**
+ * @brief configure preempt channel's corresponding rank in the sequencer and sample time of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param adc_channel: select the channel.
+ * this parameter can be one of the following values:
+ * - ADC_CHANNEL_0 - ADC_CHANNEL_1 - ADC_CHANNEL_2 - ADC_CHANNEL_3
+ * - ADC_CHANNEL_4 - ADC_CHANNEL_5 - ADC_CHANNEL_6 - ADC_CHANNEL_7
+ * - ADC_CHANNEL_8 - ADC_CHANNEL_9 - ADC_CHANNEL_10 - ADC_CHANNEL_11
+ * - ADC_CHANNEL_12 - ADC_CHANNEL_13 - ADC_CHANNEL_14 - ADC_CHANNEL_15
+ * - ADC_CHANNEL_16 - ADC_CHANNEL_17 - ADC_CHANNEL_18
+ * @param adc_sequence: set rank in the preempt group sequencer.
+ * this parameter must be:
+ * - between 1 to 4
+ * @param adc_sampletime: config the sampletime of adc channel.
+ * this parameter can be one of the following values:
+ * - ADC_SAMPLETIME_2_5
+ * - ADC_SAMPLETIME_6_5
+ * - ADC_SAMPLETIME_12_5
+ * - ADC_SAMPLETIME_24_5
+ * - ADC_SAMPLETIME_47_5
+ * - ADC_SAMPLETIME_92_5
+ * - ADC_SAMPLETIME_247_5
+ * - ADC_SAMPLETIME_640_5
+ * @retval none
+ */
+void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime)
+{
+ uint32_t tmp_reg;
+ uint8_t sequence_index;
+ if(adc_channel < ADC_CHANNEL_10)
+ {
+ tmp_reg = adc_x->spt2;
+ tmp_reg &= ~(0x07 << 3 * adc_channel);
+ tmp_reg |= adc_sampletime << 3 * adc_channel;
+ adc_x->spt2 = tmp_reg;
+ }
+ else
+ {
+ tmp_reg = adc_x->spt1;
+ tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10));
+ tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10);
+ adc_x->spt1 = tmp_reg;
+ }
+
+ sequence_index = adc_sequence + 3 - adc_x->psq_bit.pclen;
+ switch(sequence_index)
+ {
+ case 1:
+ adc_x->psq_bit.psn1 = adc_channel;
+ break;
+ case 2:
+ adc_x->psq_bit.psn2 = adc_channel;
+ break;
+ case 3:
+ adc_x->psq_bit.psn3 = adc_channel;
+ break;
+ case 4:
+ adc_x->psq_bit.psn4 = adc_channel;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief set the ordinary channel's external trigger edge and
+ * set external trigger event of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param adc_ordinary_trig: select the external trigger event.
+ * this parameter can be one of the following values:
+ * - ADC_ORDINARY_TRIG_TMR1CH1 - ADC_ORDINARY_TRIG_TMR1CH2 - ADC_ORDINARY_TRIG_TMR1CH3 - ADC_ORDINARY_TRIG_TMR2CH2
+ * - ADC_ORDINARY_TRIG_TMR2CH3 - ADC_ORDINARY_TRIG_TMR2CH4 - ADC_ORDINARY_TRIG_TMR2TRGOUT - ADC_ORDINARY_TRIG_TMR3CH1
+ * - ADC_ORDINARY_TRIG_TMR3TRGOUT - ADC_ORDINARY_TRIG_TMR4CH4 - ADC_ORDINARY_TRIG_TMR5CH1 - ADC_ORDINARY_TRIG_TMR5CH2
+ * - ADC_ORDINARY_TRIG_TMR5CH3 - ADC_ORDINARY_TRIG_TMR8CH1 - ADC_ORDINARY_TRIG_TMR8TRGOUT - ADC_ORDINARY_TRIG_EXINT11
+ * - ADC_ORDINARY_TRIG_TMR8TRGOUT2 - ADC_ORDINARY_TRIG_TMR1TRGOUT2 - ADC_ORDINARY_TRIG_TMR4TRGOUT - ADC_ORDINARY_TRIG_TMR6TRGOUT
+ * - ADC_ORDINARY_TRIG_TMR3CH4 - ADC_ORDINARY_TRIG_TMR4CH1 - ADC_ORDINARY_TRIG_TMR1TRGOUT - ADC_ORDINARY_TRIG_TMR2CH1
+ * - ADC_ORDINARY_TRIG_TMR7TRGOUT
+ * @param adc_ordinary_trig_edge: ordinary channel conversion's external_trigger_edge.
+ * this parameter can be one of the following values:
+ * - ADC_ORDINARY_TRIG_EDGE_NONE
+ * - ADC_ORDINARY_TRIG_EDGE_RISING
+ * - ADC_ORDINARY_TRIG_EDGE_FALLING
+ * - ADC_ORDINARY_TRIG_EDGE_RISING_FALLING
+ * @retval none
+ */
+void adc_ordinary_conversion_trigger_set(adc_type *adc_x, adc_ordinary_trig_select_type adc_ordinary_trig, adc_ordinary_trig_edge_type adc_ordinary_trig_edge)
+{
+ if(adc_ordinary_trig > ADC_ORDINARY_TRIG_EXINT11)
+ {
+ adc_x->ctrl2_bit.octesel_h = 1;
+ adc_x->ctrl2_bit.octesel_l = adc_ordinary_trig & 0x0F;
+ }
+ else
+ {
+ adc_x->ctrl2_bit.octesel_h = 0;
+ adc_x->ctrl2_bit.octesel_l = adc_ordinary_trig & 0x0F;
+ }
+ adc_x->ctrl2_bit.ocete = adc_ordinary_trig_edge;
+}
+
+/**
+ * @brief enable or disable the preempt channel's external trigger and
+ * set external trigger event of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param adc_preempt_trig: select the external trigger event.
+ * this parameter can be one of the following values:
+ * - ADC_PREEMPT_TRIG_TMR1CH4 - ADC_PREEMPT_TRIG_TMR1TRGOUT - ADC_PREEMPT_TRIG_TMR2CH1 - ADC_PREEMPT_TRIG_TMR2TRGOUT
+ * - ADC_PREEMPT_TRIG_TMR3CH2 - ADC_PREEMPT_TRIG_TMR3CH4 - ADC_PREEMPT_TRIG_TMR4CH1 - ADC_PREEMPT_TRIG_TMR4CH2
+ * - ADC_PREEMPT_TRIG_TMR4CH3 - ADC_PREEMPT_TRIG_TMR4TRGOUT - ADC_PREEMPT_TRIG_TMR5CH4 - ADC_PREEMPT_TRIG_TMR5TRGOUT
+ * - ADC_PREEMPT_TRIG_TMR8CH2 - ADC_PREEMPT_TRIG_TMR8CH3 - ADC_PREEMPT_TRIG_TMR8CH4 - ADC_PREEMPT_TRIG_EXINT15
+ * - ADC_PREEMPT_TRIG_TMR1TRGOUT2 - ADC_PREEMPT_TRIG_TMR8TRGOUT - ADC_PREEMPT_TRIG_TMR8TRGOUT2 - ADC_PREEMPT_TRIG_TMR3CH3
+ * - ADC_PREEMPT_TRIG_TMR3TRGOUT - ADC_PREEMPT_TRIG_TMR3CH1 - ADC_PREEMPT_TRIG_TMR6TRGOUT - ADC_PREEMPT_TRIG_TMR4CH4
+ * - ADC_PREEMPT_TRIG_TMR1CH3 - ADC_PREEMPT_TRIG_TMR7TRGOUT
+ * @param adc_preempt_trig_edge: preempt channel conversion's external_trigger_edge.
+ * this parameter can be one of the following values:
+ * - ADC_PREEMPT_TRIG_EDGE_NONE
+ * - ADC_PREEMPT_TRIG_EDGE_RISING
+ * - ADC_PREEMPT_TRIG_EDGE_FALLING
+ * - ADC_PREEMPT_TRIG_EDGE_RISING_FALLING
+ * @retval none
+ */
+void adc_preempt_conversion_trigger_set(adc_type *adc_x, adc_preempt_trig_select_type adc_preempt_trig, adc_preempt_trig_edge_type adc_preempt_trig_edge)
+{
+ if(adc_preempt_trig > ADC_PREEMPT_TRIG_EXINT15)
+ {
+ adc_x->ctrl2_bit.pctesel_h = 1;
+ adc_x->ctrl2_bit.pctesel_l = adc_preempt_trig & 0x0F;
+ }
+ else
+ {
+ adc_x->ctrl2_bit.pctesel_h = 0;
+ adc_x->ctrl2_bit.pctesel_l = adc_preempt_trig & 0x0F;
+ }
+ adc_x->ctrl2_bit.pcete = adc_preempt_trig_edge;
+}
+
+/**
+ * @brief set preempt channel's conversion value offset of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param adc_preempt_channel: select the preempt channel.
+ * this parameter can be one of the following values:
+ * - ADC_PREEMPT_CHANNEL_1
+ * - ADC_PREEMPT_CHANNEL_2
+ * - ADC_PREEMPT_CHANNEL_3
+ * - ADC_PREEMPT_CHANNEL_4
+ * @param adc_offset_value: set the adc preempt channel's conversion value offset.
+ * this parameter can be:
+ * - (0x000~0xFFF)
+ * @retval none
+ */
+void adc_preempt_offset_value_set(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel, uint16_t adc_offset_value)
+{
+ switch(adc_preempt_channel)
+ {
+ case ADC_PREEMPT_CHANNEL_1:
+ adc_x->pcdto1_bit.pcdto1 = adc_offset_value;
+ break;
+ case ADC_PREEMPT_CHANNEL_2:
+ adc_x->pcdto2_bit.pcdto2 = adc_offset_value;
+ break;
+ case ADC_PREEMPT_CHANNEL_3:
+ adc_x->pcdto3_bit.pcdto3 = adc_offset_value;
+ break;
+ case ADC_PREEMPT_CHANNEL_4:
+ adc_x->pcdto4_bit.pcdto4 = adc_offset_value;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief set partitioned mode channel count of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param adc_channel_count: configure the adc partitioned mode channel count.
+ * this parameter can be:
+ * - (0x1~0x8)
+ * @retval none
+ */
+void adc_ordinary_part_count_set(adc_type *adc_x, uint8_t adc_channel_count)
+{
+ adc_x->ctrl1_bit.ocpcnt = adc_channel_count - 1;
+}
+
+/**
+ * @brief enable or disable the partitioned mode on ordinary channel of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param new_state: new state of ordinary channel's partitioned mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_ordinary_part_mode_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ctrl1_bit.ocpen = new_state;
+}
+
+/**
+ * @brief enable or disable the partitioned mode on preempt channel of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param new_state: new state of preempt channel's partitioned mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_preempt_part_mode_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ctrl1_bit.pcpen = new_state;
+}
+
+/**
+ * @brief enable or disable automatic preempt group conversion of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param new_state: new state of automatic preempt group conversion.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_preempt_auto_mode_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ctrl1_bit.pcautoen = new_state;
+}
+
+/**
+ * @brief stop the ongoing conversion of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @retval none
+ */
+void adc_conversion_stop(adc_type *adc_x)
+{
+ adc_x->ctrl2_bit.adabrt = TRUE;
+}
+
+/**
+ * @brief get stop conversion's status of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @retval the new state of stop conversion's status(SET or RESET).
+ */
+flag_status adc_conversion_stop_status_get(adc_type *adc_x)
+{
+ if(adc_x->ctrl2_bit.adabrt)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief enable or disable each ordinary channel conversion set occe flag of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param new_state: new state of each ordinary channel conversion set occe flag.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_occe_each_conversion_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ctrl2_bit.eocsfen = new_state;
+}
+
+/**
+ * @brief enable or disable ordinary software start conversion of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param new_state: new state of ordinary software start conversion.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_ordinary_software_trigger_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ctrl2_bit.ocswtrg = new_state;
+}
+
+/**
+ * @brief get ordinary software start conversion status of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @retval the new state of ordinary software start conversion status(SET or RESET).
+ */
+flag_status adc_ordinary_software_trigger_status_get(adc_type *adc_x)
+{
+ if(adc_x->ctrl2_bit.ocswtrg)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief enable or disable preempt software start conversion of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param new_state: new state of preempt software start conversion.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_preempt_software_trigger_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ctrl2_bit.pcswtrg = new_state;
+ adc_x->ctrl2_bit.pcswtrg = FALSE;
+}
+
+/**
+ * @brief get preempt software start conversion status of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @retval the new state of preempt software start conversion status(SET or RESET).
+ */
+flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x)
+{
+ if(adc_x->ctrl2_bit.pcswtrg)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief return the last conversion data for ordinary channel of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @retval the last conversion data for ordinary channel.
+ */
+uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x)
+{
+ return (uint16_t)(adc_x->odt_bit.odt);
+}
+
+/**
+ * @brief return the last ordinary conversion data of combine adc.
+ * @retval the last conversion data for ordinary channel.
+ */
+uint32_t adc_combine_ordinary_conversion_data_get(void)
+{
+ return (uint32_t)(ADCCOM->codt);
+}
+
+/**
+ * @brief return the conversion data for selection preempt channel of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param adc_preempt_channel: select the preempt channel.
+ * this parameter can be one of the following values:
+ * - ADC_PREEMPT_CHANNEL_1
+ * - ADC_PREEMPT_CHANNEL_2
+ * - ADC_PREEMPT_CHANNEL_3
+ * - ADC_PREEMPT_CHANNEL_4
+ * @retval the conversion data for selection preempt channel.
+ */
+uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel)
+{
+ uint16_t preempt_conv_data_index = 0;
+ switch(adc_preempt_channel)
+ {
+ case ADC_PREEMPT_CHANNEL_1:
+ preempt_conv_data_index = (uint16_t)(adc_x->pdt1_bit.pdt1);
+ break;
+ case ADC_PREEMPT_CHANNEL_2:
+ preempt_conv_data_index = (uint16_t)(adc_x->pdt2_bit.pdt2);
+ break;
+ case ADC_PREEMPT_CHANNEL_3:
+ preempt_conv_data_index = (uint16_t)(adc_x->pdt3_bit.pdt3);
+ break;
+ case ADC_PREEMPT_CHANNEL_4:
+ preempt_conv_data_index = (uint16_t)(adc_x->pdt4_bit.pdt4);
+ break;
+ default:
+ break;
+ }
+ return preempt_conv_data_index;
+}
+
+/**
+ * @brief get flag of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param adc_flag: select the adc flag.
+ * this parameter can be one of the following values:
+ * - ADC_VMOR_FLAG
+ * - ADC_OCCE_FLAG
+ * - ADC_PCCE_FLAG
+ * - ADC_PCCS_FLAG(no interrupt associated)
+ * - ADC_OCCS_FLAG(no interrupt associated)
+ * - ADC_OCCO_FLAG
+ * - ADC_RDY_FLAG(no interrupt associated)
+ * - ADC_TCF_FLAG
+ * @retval the new state of adc flag status(SET or RESET).
+ */
+flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag)
+{
+ flag_status status = RESET;
+
+ if((adc_x->sts & adc_flag) == RESET)
+ {
+ status = RESET;
+ }
+ else
+ {
+ status = SET;
+ }
+ return status;
+}
+
+/**
+ * @brief get interrupt flag of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param adc_flag: select the adc flag.
+ * this parameter can be one of the following values:
+ * - ADC_VMOR_FLAG
+ * - ADC_OCCE_FLAG
+ * - ADC_PCCE_FLAG
+ * - ADC_OCCO_FLAG
+ * - ADC_TCF_FLAG
+ * @retval the new state of adc flag status(SET or RESET).
+ */
+flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag)
+{
+ flag_status status = RESET;
+ switch(adc_flag)
+ {
+ case ADC_VMOR_FLAG:
+ if(adc_x->sts_bit.vmor && adc_x->ctrl1_bit.vmorien)
+ {
+ status = SET;
+ }
+ break;
+ case ADC_OCCE_FLAG:
+ if(adc_x->sts_bit.occe && adc_x->ctrl1_bit.occeien)
+ {
+ status = SET;
+ }
+ break;
+ case ADC_PCCE_FLAG:
+ if(adc_x->sts_bit.pcce && adc_x->ctrl1_bit.pcceien)
+ {
+ status = SET;
+ }
+ break;
+ case ADC_OCCO_FLAG:
+ if(adc_x->sts_bit.occo && adc_x->ctrl1_bit.occoien)
+ {
+ status = SET;
+ }
+ break;
+ case ADC_TCF_FLAG:
+ if(adc_x->sts_bit.tcf && adc_x->ctrl1_bit.tcfien)
+ {
+ status = SET;
+ }
+ break;
+ default:
+ break;
+ }
+ return status;
+}
+
+/**
+ * @brief clear flag of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * ADC1, ADC2.
+ * @param adc_flag: select the adc flag.
+ * this parameter can be any combination of the following values:
+ * - ADC_VMOR_FLAG
+ * - ADC_OCCE_FLAG(also can clear by reading the adc_x->odt)
+ * - ADC_PCCE_FLAG
+ * - ADC_PCCS_FLAG
+ * - ADC_OCCS_FLAG
+ * - ADC_OCCO_FLAG
+ * - ADC_TCF_FLAG
+ * - note:"ADC_RDY_FLAG" cannot be choose!rdy bit is readonly bit,it means the adc is ready to accept conversion request
+ * @retval none
+ */
+void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag)
+{
+ adc_x->sts = ~adc_flag;
+}
+
+/**
+ * @brief enable or disable the ordinary oversampling of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param new_state: new state of ordinary oversampling.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_ordinary_oversample_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ovsp_bit.oosen = new_state;
+}
+
+/**
+ * @brief enable or disable the preempt oversampling of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param new_state: new state of preempt oversampling.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_preempt_oversample_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ovsp_bit.posen = new_state;
+}
+
+/**
+ * @brief config the oversampling ratio and shift of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param adc_oversample_ratio: set the oversample ratio.
+ * this parameter can be one of the following values:
+ * - ADC_OVERSAMPLE_RATIO_2
+ * - ADC_OVERSAMPLE_RATIO_4
+ * - ADC_OVERSAMPLE_RATIO_8
+ * - ADC_OVERSAMPLE_RATIO_16
+ * - ADC_OVERSAMPLE_RATIO_32
+ * - ADC_OVERSAMPLE_RATIO_64
+ * - ADC_OVERSAMPLE_RATIO_128
+ * - ADC_OVERSAMPLE_RATIO_256
+ * @param adc_oversample_shift: set the oversample shift.
+ * this parameter can be one of the following values:
+ * - ADC_OVERSAMPLE_SHIFT_0
+ * - ADC_OVERSAMPLE_SHIFT_1
+ * - ADC_OVERSAMPLE_SHIFT_2
+ * - ADC_OVERSAMPLE_SHIFT_3
+ * - ADC_OVERSAMPLE_SHIFT_4
+ * - ADC_OVERSAMPLE_SHIFT_5
+ * - ADC_OVERSAMPLE_SHIFT_6
+ * - ADC_OVERSAMPLE_SHIFT_7
+ * - ADC_OVERSAMPLE_SHIFT_8
+ * @retval none
+ */
+void adc_oversample_ratio_shift_set(adc_type *adc_x, adc_oversample_ratio_type adc_oversample_ratio, adc_oversample_shift_type adc_oversample_shift)
+{
+ adc_x->ovsp_bit.osrsel = adc_oversample_ratio;
+ adc_x->ovsp_bit.osssel = adc_oversample_shift;
+}
+
+/**
+ * @brief enable or disable the ordinary oversampling trigger mode of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param new_state: new state of ordinary oversampling trigger mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void adc_ordinary_oversample_trig_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ovsp_bit.oostren = new_state;
+}
+
+/**
+ * @brief set ordinary oversample restart mode of the specified adc peripheral.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param adc_or_oversample_restart: ordinary oversample restart mode.
+ * this parameter can be one of the following values:
+ * - ADC_OVERSAMPLE_CONTINUE
+ * - ADC_OVERSAMPLE_RESTART
+ * @retval none
+ */
+void adc_ordinary_oversample_restart_set(adc_type *adc_x, adc_ordinary_oversample_restart_type adc_ordinary_oversample_restart)
+{
+ adc_x->ovsp_bit.oosrsel = adc_ordinary_oversample_restart;
+}
+
+/**
+ * @brief enable or disable adc trigger conversion fail auto conversion abort.
+ * @param adc_x: select the adc peripheral.
+ * this parameter can be one of the following values:
+ * - ADC1, ADC2.
+ * @param new_state: new state of ordinary oversampling trigger mode.
+ * this parameter can be: TRUE or FALSE.
+ * - note: if you want to use "conversion fail auto conversion abort" function(tcfaca=1), you must enable enable tcf interrupt first(tcfien=1).
+ * @retval none
+ */
+void adc_convert_fail_auto_abort_enable(adc_type *adc_x, confirm_state new_state)
+{
+ adc_x->ctrl1_bit.tcfien = new_state;
+ adc_x->ctrl1_bit.tcfaca = new_state;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_aes.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_aes.c
new file mode 100644
index 00000000000..8c3df28cdd3
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_aes.c
@@ -0,0 +1,388 @@
+/**
+ **************************************************************************
+ * @file at32f45x_aes.c
+ * @brief contains all the functions for the aes firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup AES
+ * @brief AES driver modules
+ * @{
+ */
+
+#ifdef AES_MODULE_ENABLED
+
+/** @defgroup AES_private_functions
+ * @{
+ */
+
+/**
+ * @brief reset the aes register
+ * @param none
+ * @retval none
+ */
+void aes_reset(void)
+{
+ crm_periph_reset(CRM_AES_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_AES_PERIPH_RESET, FALSE);
+}
+
+/**
+ * @brief set aes key value
+ * @param aes_kl
+ * this parameter can be one of the following values:
+ * - AES_KEY_LENGTH_128
+ * - AES_KEY_LENGTH_192
+ * - AES_KEY_LENGTH_256
+ * @param aes_key
+ * - pointer to the aes key value
+ * @retval none
+ */
+void aes_key_set(aes_key_length_type aes_kl, uint32_t* aes_key)
+{
+ AES->key0 = aes_key[0];
+ AES->key1 = aes_key[1];
+ AES->key2 = aes_key[2];
+ AES->key3 = aes_key[3];
+ if(aes_kl == AES_KEY_LENGTH_192)
+ {
+ AES->key4 = aes_key[4];
+ AES->key5 = aes_key[5];
+ }
+ else if(aes_kl == AES_KEY_LENGTH_256)
+ {
+ AES->key4 = aes_key[4];
+ AES->key5 = aes_key[5];
+ AES->key6 = aes_key[6];
+ AES->key7 = aes_key[7];
+ }
+}
+
+/**
+ * @brief set aes initial vector
+ * @param aes_iv
+ * - pointer to the aes initial vector
+ * @retval none
+ */
+void aes_iv_set(uint32_t* aes_iv)
+{
+ AES->iv0 = aes_iv[0];
+ AES->iv1 = aes_iv[1];
+ AES->iv2 = aes_iv[2];
+ AES->iv3 = aes_iv[3];
+}
+
+/**
+ * @brief set aes number of dummy data
+ * @param num: number of dummy data (0~15)
+ * @retval none
+ */
+void aes_dummy_data_num_set(uint8_t num)
+{
+ AES->ctrl_bit.ndd = (num & 0x0F);
+}
+
+/**
+ * @brief set processing stage field in ctrl regsiter, valid for ccm/gcm mode
+ * @param prc_type
+ * this parameter can be one of the following values:
+ * - AES_PRC_INIT
+ * - AES_PRC_ASSOC
+ * - AES_PRC_DATA
+ * - AES_PRC_TAG
+ * @retval none
+ */
+void aes_processing_stage_set(aes_processing_stage_type prc_type)
+{
+ AES->ctrl_bit.prc = prc_type;
+}
+
+/**
+ * @brief aes init config with its default value
+ * @param aes_init_struct
+ * - pointer to a aes_init_type structure which will be initialized
+ * @retval none
+ */
+void aes_default_para_init(aes_init_type* aes_init_struct)
+{
+ aes_init_struct->operate_mode = AES_OPMODE_DECRYPT;
+ aes_init_struct->chaining_mode = AES_CHMODE_ECB;
+ aes_init_struct->key_len = AES_KEY_LENGTH_128;
+ aes_init_struct->key_buf = 0;
+ aes_init_struct->data_swap_mode = AES_SWAP_TYPE_NONE;
+}
+
+/**
+ * @brief init aes
+ * @param aes_init_struct
+ * - pointer to a aes_init_type structure
+ * @retval none
+ */
+void aes_init(aes_init_type* aes_init_struct)
+{
+ /* setup ctrl */
+ AES->ctrl_bit.opr = aes_init_struct->operate_mode;
+ AES->ctrl_bit.chn = aes_init_struct->chaining_mode;
+ AES->ctrl_bit.swp = aes_init_struct->data_swap_mode;
+ AES->ctrl_bit.kl = aes_init_struct->key_len;
+
+ aes_key_set(aes_init_struct->key_len, aes_init_struct->key_buf);
+}
+
+/**
+ * @brief init aes suspend information
+ * @param none
+ * @retval none
+ */
+void aes_suspend_info_init(void)
+{
+ AES->si0 = 0;
+ AES->si1 = 0;
+ AES->si2 = 0;
+ AES->si3 = 0;
+ AES->si4 = 0;
+ AES->si5 = 0;
+ AES->si6 = 0;
+ AES->si7 = 0;
+}
+
+/**
+ * @brief set aes suspend information
+ * @param si_buf
+ * - pointer to the aes suspend information
+ * @retval none
+ */
+void aes_suspend_info_set(uint32_t* si_buf)
+{
+ AES->si0 = si_buf[0];
+ AES->si1 = si_buf[1];
+ AES->si2 = si_buf[2];
+ AES->si3 = si_buf[3];
+ AES->si4 = si_buf[4];
+ AES->si5 = si_buf[5];
+ AES->si6 = si_buf[6];
+ AES->si7 = si_buf[7];
+}
+
+/**
+ * @brief set aes operation mode
+ * @param op_mode
+ * this parameter can be one of the following values:
+ * - AES_OPMODE_ENCRYPT
+ * - AES_OPMODE_KEY_SCHEDULING
+ * - AES_OPMODE_DECRYPT
+ * - AES_OPMODE_KEY_SCHEDULING_DECRYPT
+ * @retval none
+ */
+void aes_operate_mode_set(aes_operate_mode_type op_mode)
+{
+ AES->ctrl_bit.opr = op_mode;
+}
+
+/**
+ * @brief enable or disable the aes
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void aes_enable(confirm_state new_state)
+{
+ AES->ctrl_bit.aesen = new_state;
+}
+
+/**
+ * @brief enable or disable using dma when data in
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void aes_dma_in_enable(confirm_state new_state)
+{
+ AES->ctrl_bit.dmawe = new_state;
+}
+
+/**
+ * @brief enable or disable using dma when data out
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void aes_dma_out_enable(confirm_state new_state)
+{
+ AES->ctrl_bit.dmare = new_state;
+}
+
+/**
+ * @brief enable or disable the last block data
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void aes_last_block_enable(confirm_state new_state)
+{
+ AES->ctrl_bit.lst = new_state;
+}
+
+/**
+ * @brief enable or disable the specified aes interrupts
+ * @param aes_int
+ * this parameter can be any combination of the following values:
+ * - AES_RWEIE_INT
+ * - AES_PDIE_INT
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void aes_interrupt_enable(uint32_t aes_int, confirm_state new_state)
+{
+ if(new_state == TRUE)
+ {
+ AES->ctrl |= aes_int;
+ }
+ else if(new_state == FALSE)
+ {
+ AES->ctrl |= aes_int;
+ }
+}
+
+/**
+ * @brief check whether the specified aes interrupt flag is set or not.
+ * @param flag
+ * this parameter can be one of the following values:
+ * - AES_PDFS_FLAG
+ * - AES_REFS_FLAG
+ * - AES_WEFS_FLAG
+ * @retval flag_status (SET or RESET)
+ */
+flag_status aes_interrupt_flag_get(uint32_t flag)
+{
+ flag_status status = RESET;
+ switch(flag)
+ {
+ case AES_PDFS_FLAG:
+ if((AES->sts & flag) && (AES->ctrl_bit.pdie))
+ status = SET;
+ break;
+ case AES_REFS_FLAG:
+ case AES_WEFS_FLAG:
+ if((AES->sts & flag) && (AES->ctrl_bit.rweie))
+ status = SET;
+ break;
+ default:
+ break;
+ }
+ return status;
+}
+
+/**
+ * @brief check whether the specified aes flag is set or not.
+ * @param flag
+ * this parameter can be one of the following values:
+ * - AES_PDFS_FLAG
+ * - AES_REFS_FLAG
+ * - AES_WEFS_FLAG
+ * - AES_PBS_FLAG
+ * - AES_NZDFS_FLAG
+ * @retval flag_status (SET or RESET)
+ */
+flag_status aes_flag_get(uint32_t flag)
+{
+ if(AES->sts & flag)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief clear aes flag
+ * @param flag
+ * this parameter can be one of the following values:
+ * - AES_PDFS_FLAG
+ * - AES_REFS_FLAG
+ * - AES_WEFS_FLAG
+ * - AES_NZDFS_FLAG
+ * @retval none
+ */
+void aes_flag_clear(uint32_t flag)
+{
+ switch(flag)
+ {
+ case AES_PDFS_FLAG:
+ AES->fclr_bit.pdfc = 1;
+ break;
+ case AES_REFS_FLAG:
+ AES->fclr_bit.refc = 1;
+ break;
+ case AES_WEFS_FLAG:
+ AES->fclr_bit.wefc = 1;
+ break;
+ case AES_NZDFS_FLAG:
+ AES->fclr_bit.nzdfc = 1;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief aes process input data and return remaining data pointer
+ * @param input_ptr:
+ * - pointer to aes process input data(word alignment)
+ * @retval pointer to remaining data
+ */
+void aes_data_input(uint32_t* input_ptr)
+{
+ AES->idt = input_ptr[0];
+ AES->idt = input_ptr[1];
+ AES->idt = input_ptr[2];
+ AES->idt = input_ptr[3];
+}
+
+/**
+ * @brief aes store output data and return remaining data pointer
+ * @param output_ptr
+ * - pointer to aes store output data(word alignment)
+ * @retval pointer to remaining data
+ */
+void aes_data_output(uint32_t* output_ptr)
+{
+ output_ptr[0] = AES->odt;
+ output_ptr[1] = AES->odt;
+ output_ptr[2] = AES->odt;
+ output_ptr[3] = AES->odt;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_can.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_can.c
new file mode 100644
index 00000000000..50993e25af5
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_can.c
@@ -0,0 +1,1446 @@
+/**
+ **************************************************************************
+ * @file at32f45x_can.c
+ * @brief contains all the functions for the can firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup CAN
+ * @brief CAN driver modules
+ * @{
+ */
+
+#ifdef CAN_MODULE_ENABLED
+
+#ifdef SUPPORT_CAN_FD
+static const uint8_t dlc_to_bytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
+#endif
+
+/** @defgroup CAN_private_functions
+ * @{
+ */
+
+/**
+ * @brief deinitialize the can peripheral registers to their default reset values.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @retval none
+ */
+void can_reset(can_type* can_x)
+{
+ if(can_x == CAN1)
+ {
+ crm_periph_reset(CRM_CAN1_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_CAN1_PERIPH_RESET, FALSE);
+ }
+}
+
+/**
+ * @brief enable can software reset, it is forces several components to a reset state.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param new_state: new state of software reset request.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none.
+ */
+void can_software_reset(can_type* can_x, confirm_state new_state)
+{
+ can_x->ctrlstat_bit.reset = new_state;
+}
+
+#ifdef SUPPORT_CAN_FD
+/**
+ * @brief enable the iso 11898-1:2015 protocol mode of the can peripheral.
+ * can-fd frame format is according to iso 11898-1:2015 or bosch(non-iso) standard.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param new_state: new state of the can iso 11898-1 protocol mode.
+ * this parameter can be: TRUE or FALSE.
+ * @note this bit is only writeable if reset=1.
+ * @retval none
+ */
+void can_fd_iso_mode_enable(can_type* can_x, confirm_state new_state)
+{
+ can_x->ctrlstat_bit.fd_iso = new_state;
+}
+#endif
+
+/**
+ * @brief set the mode of the can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param mode_selection: select can mode type.
+ * this parameter can be one of the following values:
+ * - CAN_MODE_COMMUNICATE
+ * - CAN_MODE_EXT_LOOPBACK
+ * - CAN_MODE_EXT_LOOPBACK_ACK
+ * - CAN_MODE_INT_LOOPBACK
+ * - CAN_MODE_LISTENONLY
+ * - CAN_MODE_LISTENONLY_EXT
+ * - CAN_MODE_LISTENONLY_EXT_ACK
+ * @retval none
+ */
+void can_mode_set(can_type* can_x, can_mode_type mode_selection)
+{
+ switch(mode_selection)
+ {
+ case CAN_MODE_COMMUNICATE:
+ can_x->ctrlstat_bit.lbme = FALSE;
+ can_x->ctrlstat_bit.sack = FALSE;
+ can_x->ctrlstat_bit.lbmi = FALSE;
+ can_x->ctrlstat_bit.lom = FALSE;
+ break;
+ case CAN_MODE_EXT_LOOPBACK:
+ can_x->ctrlstat_bit.lbme = TRUE;
+ can_x->ctrlstat_bit.sack = FALSE;
+ can_x->ctrlstat_bit.lbmi = FALSE;
+ can_x->ctrlstat_bit.lom = FALSE;
+ break;
+ case CAN_MODE_EXT_LOOPBACK_ACK:
+ can_x->ctrlstat_bit.lbme = TRUE;
+ can_x->ctrlstat_bit.sack = TRUE;
+ can_x->ctrlstat_bit.lbmi = FALSE;
+ can_x->ctrlstat_bit.lom = FALSE;
+ break;
+ case CAN_MODE_INT_LOOPBACK:
+ can_x->ctrlstat_bit.lbme = FALSE;
+ can_x->ctrlstat_bit.sack = FALSE;
+ can_x->ctrlstat_bit.lbmi = TRUE;
+ can_x->ctrlstat_bit.lom = FALSE;
+ break;
+ case CAN_MODE_LISTENONLY:
+ can_x->ctrlstat_bit.lbme = FALSE;
+ can_x->ctrlstat_bit.sack = FALSE;
+ can_x->ctrlstat_bit.lbmi = FALSE;
+ can_x->ctrlstat_bit.lom = TRUE;
+ break;
+ case CAN_MODE_LISTENONLY_EXT:
+ can_x->ctrlstat_bit.lbme = TRUE;
+ can_x->ctrlstat_bit.sack = FALSE;
+ can_x->ctrlstat_bit.lbmi = FALSE;
+ can_x->ctrlstat_bit.lom = TRUE;
+ break;
+ case CAN_MODE_LISTENONLY_EXT_ACK:
+ can_x->ctrlstat_bit.lbme = TRUE;
+ can_x->ctrlstat_bit.sack = TRUE;
+ can_x->ctrlstat_bit.lbmi = FALSE;
+ can_x->ctrlstat_bit.lom = TRUE;
+ break;
+ default:
+ return;
+ }
+}
+
+/**
+ * @brief enable the transceiver standby mode of the can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param new_state: new state of the can transceiver standby mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval SUCCESS or ERROR
+ */
+error_status can_standby_mode_enable(can_type* can_x, confirm_state new_state)
+{
+ if (new_state != FALSE)
+ {
+ /* can-ctrl does not allow stby to be set if a transmission is already active (tpe, tsone or tsall is set). */
+ if(can_x->ctrlstat_bit.tsall || can_x->ctrlstat_bit.tsone || can_x->ctrlstat_bit.tpe)
+ return ERROR;
+ can_x->ctrlstat_bit.stby = TRUE;
+ }
+ else
+ {
+ can_x->ctrlstat_bit.stby = FALSE;
+ }
+
+ return SUCCESS;
+}
+
+/**
+ * @brief enable restricted operation of the can peripheral.
+ * a can node which is in restricted operation mode shall not transmit data frames
+ * unless it is a potential time master for ttcan.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param new_state: new state of the can restricted operation.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void can_restricted_operation_enable(can_type* can_x, confirm_state new_state)
+{
+ can_x->tncfg_bit.rop = new_state;
+}
+
+/**
+ * @brief fill each can_bittime_struct member with its default value.
+ * @param can_bittime_struct: pointer to a can_bittime_type structure which will be initialized.
+ * @retval none.
+ */
+void can_bittime_default_para_init(can_bittime_type* can_bittime_struct)
+{
+ /* reset can bittime structure parameters values */
+
+ can_bittime_struct->bittime_div = 1;
+
+ can_bittime_struct->ac_bts1_size = 12;
+ can_bittime_struct->ac_bts2_size = 4;
+ can_bittime_struct->ac_rsaw_size = 4;
+
+#ifdef SUPPORT_CAN_FD
+ can_bittime_struct->fd_bts1_size = 6;
+ can_bittime_struct->fd_bts2_size = 2;
+ can_bittime_struct->fd_rsaw_size = 2;
+ can_bittime_struct->fd_ssp_offset = 7;
+#endif
+}
+
+/**
+ * @brief set the bittime of the can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param can_bittime_struct: pointer to a can_bittime_type structure which will be set.
+ * @note baudrate calculate method is:
+ * baudrate = can_clk/(baudrate_div *(bts1_size + bts2_size))
+ * @retval none
+ */
+void can_bittime_set(can_type* can_x, can_bittime_type* can_bittime_struct)
+{
+ can_x->lbtcfg_bit.presc = can_bittime_struct->bittime_div - 1;
+
+ can_x->actime_bit.ac_seg_1 = can_bittime_struct->ac_bts1_size-2;
+ can_x->actime_bit.ac_seg_2 = can_bittime_struct->ac_bts2_size-1;
+ can_x->actime_bit.ac_sjw = can_bittime_struct->ac_rsaw_size-1;
+
+#ifdef SUPPORT_CAN_FD
+ can_x->fdtime_bit.fd_seg_1 = can_bittime_struct->fd_bts1_size-2;
+ can_x->fdtime_bit.fd_seg_2 = can_bittime_struct->fd_bts2_size-1;
+ can_x->fdtime_bit.fd_sjw = can_bittime_struct->fd_rsaw_size-1;
+ can_x->lbtcfg_bit.fd_sspoff = can_bittime_struct->fd_ssp_offset;
+#endif
+}
+
+/**
+ * @brief set the retransmission limit value of the can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param re_trans_times: can re-transmission times type.
+ * this parameter can be one of the following values:
+ * - CAN_RE_TRANS_TIMES_0
+ * - CAN_RE_TRANS_TIMES_1
+ * - CAN_RE_TRANS_TIMES_2
+ * - CAN_RE_TRANS_TIMES_3
+ * - CAN_RE_TRANS_TIMES_4
+ * - CAN_RE_TRANS_TIMES_5
+ * - CAN_RE_TRANS_TIMES_6
+ * - CAN_RE_TRANS_TIMES_UNLIMIT
+ * @retval none
+ */
+void can_retransmission_limit_set(can_type* can_x, can_retransmission_times_type re_trans_times)
+{
+ can_x->lbtcfg_bit.retlim = re_trans_times;
+}
+
+/**
+ * @brief set the re-arbitration limit value of the can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param re_arbi_times: can re-arbitration times type.
+ * this parameter can be one of the following values:
+ * - CAN_RE_ARBI_TIMES_0
+ * - CAN_RE_ARBI_TIMES_1
+ * - CAN_RE_ARBI_TIMES_2
+ * - CAN_RE_ARBI_TIMES_3
+ * - CAN_RE_ARBI_TIMES_4
+ * - CAN_RE_ARBI_TIMES_5
+ * - CAN_RE_ARBI_TIMES_6
+ * - CAN_RE_ARBI_TIMES_UNLIMIT
+ * @retval none
+ */
+void can_rearbitration_limit_set(can_type* can_x, can_rearbitration_times_type re_arbi_times)
+{
+ can_x->lbtcfg_bit.realim = re_arbi_times;
+}
+
+/**
+ * @brief enable time-stamping of the can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param new_state: new state of the can time-stamping.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void can_timestamp_enable(can_type* can_x, confirm_state new_state)
+{
+ can_x->tncfg_bit.tsen = new_state;
+}
+
+/**
+ * @brief set time-stamping position of the can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param timestamp_position: can timestamp position type.
+ * this parameter can be one of the following values:
+ * - CAN_TIMESTAMP_AT_SOF
+ * - CAN_TIMESTAMP_AT_EOF
+ * @retval none
+ */
+void can_timestamp_position_set(can_type* can_x, can_timestamp_position_type timestamp_position)
+{
+ can_x->tncfg_bit.tspos = timestamp_position;
+}
+
+/**
+ * @brief return the transmission timestamp of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @retval the value of transmission timestamp.
+ */
+uint32_t can_transmit_timestamp_get(can_type* can_x)
+{
+ return (uint32_t)can_x->tts;
+}
+
+/**
+ * @brief write the transmission buffer of the can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param txbuf_type: txbuf select type
+ * this parameter can be one of the following values:
+ * - CAN_TXBUF_PTB
+ * - CAN_TXBUF_STB
+ * @param can_txbuf_struct: pointer to a structure which contains the buffer to be trans.
+ * @retval SUCCESS or ERROR
+ */
+error_status can_txbuf_write(can_type* can_x, can_txbuf_select_type txbuf_type, can_txbuf_type* can_txbuf_struct)
+{
+#ifdef SUPPORT_CAN_FD
+ uint8_t len = dlc_to_bytes[can_txbuf_struct->data_length];
+#else
+ uint8_t len = can_txbuf_struct->data_length;
+#endif
+ uint32_t* wp = (uint32_t*)can_x->tbdat;
+ uint8_t* rp = can_txbuf_struct->data;
+ uint8_t byte_cnt;
+
+ uint8_t* reg;
+ uint8_t tmp;
+
+ switch(txbuf_type)
+ {
+ case CAN_TXBUF_PTB:
+ if(can_x->ctrlstat_bit.tpe == TRUE)
+ {
+ /* if tpe=1 then the primary transmit buffer is write-locked. */
+ return ERROR;
+ }
+ break;
+ case CAN_TXBUF_STB:
+ if(can_x->ctrlstat_bit.tsnext == TRUE)
+ {
+ /* while tsnext=1, then writing to the secondary transmit buffer is blocked. */
+ return ERROR;
+ }
+ break;
+ default:
+ return ERROR;
+ }
+
+ /* write tbsel, avoid duplicate setting these bits(tsa, tsall, tsone, tpa, tpe and tbsel). */
+ reg = (uint8_t*)&can_x->ctrlstat + 1;
+ tmp = *reg & 0x60;
+ *reg = tmp | (txbuf_type<<7);
+
+ switch(can_txbuf_struct->id_type)
+ {
+ case CAN_ID_STANDARD:
+ can_x->tbid = (0x7FF & can_txbuf_struct->id)<<18;
+ break;
+ case CAN_ID_EXTENDED:
+ can_x->tbid = (0x1FFFFFFF & can_txbuf_struct->id);
+ break;
+ default:
+ return ERROR;
+ }
+ can_x->tbid |= (can_txbuf_struct->tx_timestamp << 31);
+
+ can_x->tbfmt = 0;
+ can_x->tbfmt_bit.ide = can_txbuf_struct->id_type;
+ can_x->tbfmt_bit.rmf = can_txbuf_struct->frame_type;
+ can_x->tbfmt_bit.dlc = can_txbuf_struct->data_length;
+#ifdef SUPPORT_CAN_FD
+ can_x->tbfmt_bit.brs = can_txbuf_struct->fd_rate_switch;
+ can_x->tbfmt_bit.fdf = can_txbuf_struct->fd_format;
+#endif
+
+ /* write tx payload to the buffer ram. */
+ for (byte_cnt = 0; byte_cnt < len; byte_cnt += 4U)
+ {
+ *wp++ = (((uint32_t)rp[byte_cnt + 3U] << 24U) |
+ ((uint32_t)rp[byte_cnt + 2U] << 16U) |
+ ((uint32_t)rp[byte_cnt + 1U] << 8U) |
+ (uint32_t)rp[byte_cnt]);
+ }
+
+ can_x->tbtyp = 0;
+ can_x->tbtyp_bit.handle = can_txbuf_struct->handle;
+ can_x->reserved8 = 0;
+
+ if(txbuf_type == CAN_TXBUF_STB)
+ {
+ /* write tsnext, mark a slot filled and point to the next frame slot. */
+ reg = (uint8_t*)&can_x->ctrlstat + 2;
+ tmp = *reg;
+ *reg = tmp | 0x40;
+ }
+
+ return SUCCESS;
+}
+
+/**
+ * @brief read the receive buffer of the can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param can_rxbuf_struct: pointer to a structure which contains the buffer to be receive.
+ * @retval SUCCESS or ERROR
+ */
+error_status can_rxbuf_read(can_type* can_x, can_rxbuf_type* can_rxbuf_struct)
+{
+#ifdef SUPPORT_CAN_FD
+ uint8_t len = dlc_to_bytes[can_x->rbfmt_bit.dlc];
+#else
+ uint8_t len = can_x->rbfmt_bit.dlc;
+#endif
+ uint32_t* rp = (uint32_t*)can_x->rbdat;
+ uint8_t* wp = can_rxbuf_struct->data;
+ uint8_t byte_cnt;
+ uint16_t pos;
+
+ uint8_t* reg;
+ uint8_t tmp;
+
+ if(can_x->ctrlstat_bit.rstat == CAN_RXBUF_STATUS_EMPTY)
+ {
+ /* receive buffer is empty. */
+ return ERROR;
+ }
+
+ can_rxbuf_struct->id_type = (can_identifier_type)can_x->rbfmt_bit.ide;
+ switch(can_rxbuf_struct->id_type)
+ {
+ case CAN_ID_STANDARD:
+ can_rxbuf_struct->id = 0x7FF & (can_x->rbid >> 18);
+ break;
+ case CAN_ID_EXTENDED:
+ can_rxbuf_struct->id = (0x1FFFFFFF & can_x->rbid);
+ break;
+ default:
+ return ERROR;
+ }
+
+ can_rxbuf_struct->frame_type = (can_frame_type)can_x->rbfmt_bit.rmf;
+#ifdef SUPPORT_CAN_FD
+ can_rxbuf_struct->fd_format = (can_format_type)can_x->rbfmt_bit.fdf;
+ can_rxbuf_struct->fd_rate_switch = (can_rate_switch_type)can_x->rbfmt_bit.brs;
+ can_rxbuf_struct->fd_error_state = (can_error_state_type)can_x->rbfmt_bit.esi;
+#endif
+ can_rxbuf_struct->kind_error = (can_error_type)can_x->rbfmt_bit.koer;
+ can_rxbuf_struct->recv_frame = (can_recv_frame_type)can_x->rbfmt_bit.lbf;
+ can_rxbuf_struct->data_length = (can_data_length_type)can_x->rbfmt_bit.dlc;
+
+ /* read the buffer ram to rx payload */
+ for (byte_cnt = 0; byte_cnt < len; byte_cnt += 4U)
+ {
+ wp[byte_cnt] = *rp & 0xFF;
+ wp[byte_cnt+1U] = (*rp >> 8U) & 0xFF;
+ wp[byte_cnt+2U] = (*rp >> 16U) & 0xFF;
+ wp[byte_cnt+3U] = (*rp >> 24U) & 0xFF;
+ rp++;
+ }
+
+ can_x->llcformat = can_x->rbfmt;
+ pos = (can_x->llcsize_bit.llcaot / 4) - 4;
+ can_rxbuf_struct->rx_timestamp = (uint32_t)can_x->rbdat[pos];
+ can_rxbuf_struct->cycle_time = (uint16_t)can_x->rbdat[pos + 2];
+
+ /* set rrel, receive buffer release. */
+ reg = (uint8_t*)&can_x->ctrlstat + 3;
+ tmp = *reg;
+ *reg = tmp | 0x10;
+
+ return SUCCESS;
+}
+
+/**
+ * @brief enable acceptance filters of the can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param filter_number: point to a specific acceptance filter.
+ * this parameter can be one of the following values:
+ * - CAN_FILTER_NUM_0
+ * - CAN_FILTER_NUM_1
+ * - CAN_FILTER_NUM_2
+ * - CAN_FILTER_NUM_3
+ * - CAN_FILTER_NUM_4
+ * - CAN_FILTER_NUM_5
+ * - CAN_FILTER_NUM_6
+ * - CAN_FILTER_NUM_7
+ * - CAN_FILTER_NUM_8
+ * - CAN_FILTER_NUM_9
+ * - CAN_FILTER_NUM_10
+ * - CAN_FILTER_NUM_11
+ * - CAN_FILTER_NUM_12
+ * - CAN_FILTER_NUM_13
+ * - CAN_FILTER_NUM_14
+ * - CAN_FILTER_NUM_15
+ * @param new_state: new state of the specific acceptance filter.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void can_filter_enable(can_type* can_x, can_filter_type filter_number, confirm_state new_state)
+{
+ if (new_state != FALSE)
+ {
+ can_x->acfctrl_bit.ae_x |= (uint16_t)(1<acfctrl_bit.ae_x &= (uint16_t)~(1<code_para.id = 0;
+ filter_config_struct->code_para.id_type = CAN_ID_STANDARD;
+ filter_config_struct->code_para.frame_type = CAN_FRAME_DATA;
+ filter_config_struct->code_para.data_length = 0;
+ filter_config_struct->code_para.recv_frame = CAN_RECV_NORMAL;
+#ifdef SUPPORT_CAN_FD
+ filter_config_struct->code_para.fd_format = CAN_FORMAT_CLASSIC;
+ filter_config_struct->code_para.fd_rate_switch = CAN_BRS_OFF;
+ filter_config_struct->code_para.fd_error_state = CAN_ESI_ACTIVE;
+#endif
+
+ filter_config_struct->mask_para.id = 0xFFFFFFFF;
+ filter_config_struct->mask_para.id_type = TRUE;
+ filter_config_struct->mask_para.frame_type = TRUE;
+ filter_config_struct->mask_para.data_length = 0xF;
+ filter_config_struct->mask_para.recv_frame = TRUE;
+#ifdef SUPPORT_CAN_FD
+ filter_config_struct->mask_para.fd_format = TRUE;
+ filter_config_struct->mask_para.fd_rate_switch = TRUE;
+ filter_config_struct->mask_para.fd_error_state = TRUE;
+#endif
+}
+
+/**
+ * @brief set acceptance filters of the can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param filter_number: point to a specific acceptance filter number.
+ * this parameter can be one of the following values:
+ * - CAN_FILTER_NUM_0
+ * - CAN_FILTER_NUM_1
+ * - CAN_FILTER_NUM_2
+ * - CAN_FILTER_NUM_3
+ * - CAN_FILTER_NUM_4
+ * - CAN_FILTER_NUM_5
+ * - CAN_FILTER_NUM_6
+ * - CAN_FILTER_NUM_7
+ * - CAN_FILTER_NUM_8
+ * - CAN_FILTER_NUM_9
+ * - CAN_FILTER_NUM_10
+ * - CAN_FILTER_NUM_11
+ * - CAN_FILTER_NUM_12
+ * - CAN_FILTER_NUM_13
+ * - CAN_FILTER_NUM_14
+ * - CAN_FILTER_NUM_15
+ * @param filter_config_struct: pointer to a structure which contains acceptance filter config.
+ * @retval none
+ */
+void can_filter_set(can_type* can_x, can_filter_type filter_number, can_filter_config_type* filter_config_struct)
+{
+ can_x->acfctrl_bit.acfadr = filter_number;
+
+ switch(filter_config_struct->code_para.id_type)
+ {
+ case CAN_ID_STANDARD:
+ can_x->fcid = (0x7FF & filter_config_struct->code_para.id)<<18;
+ break;
+ case CAN_ID_EXTENDED:
+ can_x->fcid = (0x1FFFFFFF & filter_config_struct->code_para.id);
+ break;
+ default:
+ break;
+ }
+ can_x->fcfmt_bit.ide = filter_config_struct->code_para.id_type;
+ can_x->fcfmt_bit.rmf = filter_config_struct->code_para.frame_type;
+ can_x->fcfmt_bit.dlc = filter_config_struct->code_para.data_length;
+ can_x->fcfmt_bit.lbf = filter_config_struct->code_para.recv_frame;
+#ifdef SUPPORT_CAN_FD
+ can_x->fcfmt_bit.brs = filter_config_struct->code_para.fd_rate_switch;
+ can_x->fcfmt_bit.fdf = filter_config_struct->code_para.fd_format;
+ can_x->fcfmt_bit.esi = filter_config_struct->code_para.fd_error_state;
+#endif
+
+ can_x->fmid = 0xFFFFFFFF;
+ /* write mask_id by id_type of filter_code_struct. */
+ switch(filter_config_struct->code_para.id_type)
+ {
+ case CAN_ID_STANDARD:
+ can_x->fmid &= ~((0x7FF & ~filter_config_struct->mask_para.id)<<18);
+ break;
+ case CAN_ID_EXTENDED:
+ can_x->fmid &= ~(0x1FFFFFFF & ~filter_config_struct->mask_para.id);
+ break;
+ default:
+ break;
+ }
+ can_x->fmfmt = 0xFFFFFFFF;
+ can_x->fmfmt_bit.ide = filter_config_struct->mask_para.id_type;
+ can_x->fmfmt_bit.rmf = filter_config_struct->mask_para.frame_type;
+ can_x->fmfmt_bit.dlc = filter_config_struct->mask_para.data_length;
+ can_x->fmfmt_bit.lbf = filter_config_struct->mask_para.recv_frame;
+#ifdef SUPPORT_CAN_FD
+ can_x->fmfmt_bit.brs = filter_config_struct->mask_para.fd_rate_switch;
+ can_x->fmfmt_bit.fdf = filter_config_struct->mask_para.fd_format;
+ can_x->fmfmt_bit.esi = filter_config_struct->mask_para.fd_error_state;
+#endif
+ can_x->fmtyp = 0xFFFFFFFF;
+ can_x->reserved6[0] = 0xFFFFFFFF;
+}
+
+/**
+ * @brief release the receive buffer of the can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @retval SUCCESS or ERROR
+ */
+error_status can_rxbuf_release(can_type* can_x)
+{
+ uint8_t* reg;
+ uint8_t tmp;
+
+ if(can_x->ctrlstat_bit.rstat == CAN_RXBUF_STATUS_EMPTY)
+ {
+ /* receive buffer is empty. */
+ return ERROR;
+ }
+
+ /* set rrel, receive buffer release. */
+ reg = (uint8_t*)&can_x->ctrlstat + 3;
+ tmp = *reg;
+ *reg = tmp | 0x10;
+
+ return SUCCESS;
+}
+
+/**
+ * @brief return the bit position in the frame where the arbitration has been lost.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @retval the value of the bit position in the frame.
+ */
+uint8_t can_arbitration_lost_position_get(can_type* can_x)
+{
+ return (uint8_t)can_x->err_bit.alc;
+}
+
+/**
+ * @brief set the value of receive buffer almost full warning limit.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param warning_value: defines the internal warning limit of receive buffer almost full.
+ * this parameter can be 1~6.
+ * @retval none
+ */
+void can_rxbuf_warning_set(can_type* can_x, uint8_t warning_value)
+{
+ can_x->err_bit.afwl = warning_value;
+}
+
+/**
+ * @brief set the value of error warning limit controls eif.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param warning_value: programmable error warning limit = (warning_value + 1)*8. possible limit values: 8, 16, ... 128.
+ * this parameter can be 0~15.
+ * @retval none
+ */
+void can_error_warning_set(can_type* can_x, uint8_t warning_value)
+{
+ can_x->err_bit.ewl = warning_value;
+}
+
+/**
+ * @brief return the receive error counter of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @retval the value of receive error counter.
+ */
+uint8_t can_receive_error_counter_get(can_type* can_x)
+{
+ uint8_t counter = 0;
+ counter = can_x->err_bit.recnt;
+ return counter;
+}
+
+/**
+ * @brief return the transmit error counter of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @retval the value of transmit error counter.
+ */
+uint8_t can_transmit_error_counter_get(can_type* can_x)
+{
+ uint8_t counter = 0;
+ counter = can_x->err_bit.tecnt;
+ return counter;
+}
+
+/**
+ * @brief return error type of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @retval can kind of error type.
+ * the returned value can be one of the following values:
+ * - CAN_KOER_NOERR
+ * - CAN_KOER_BIT
+ * - CAN_KOER_FORM
+ * - CAN_KOER_STUFF
+ * - CAN_KOER_ACK
+ * - CAN_KOER_CRC
+ * - CAN_KOER_OTHER
+ * - CAN_KOER_PCRC
+ */
+can_error_type can_kind_error_get(can_type* can_x)
+{
+ can_error_type error_code = CAN_KOER_NOERR;
+
+ error_code = (can_error_type)can_x->err_bit.koer;
+
+ return error_code;
+}
+
+/**
+ * @brief get bus off flag of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @retval status of can bus off flag, the returned value can be: SET or RESET.
+ */
+flag_status can_busoff_get(can_type* can_x)
+{
+ flag_status bit_status = RESET;
+ if(can_x->ctrlstat_bit.busoff)
+ {
+ bit_status = SET;
+ }
+ return bit_status;
+}
+
+/**
+ * @brief resets the error counters and therefore forces the node to leave the bus off state.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @retval none.
+ */
+void can_busoff_reset(can_type* can_x)
+{
+ can_x->ctrlstat_bit.busoff = SET;
+}
+
+/**
+ * @brief set the secondary transmit buffer operation mode.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param stb_transmit_mode: secondary transmit buffer operation mode.
+ * this parameter can be one of the following values:
+ * - CAN_STB_TRANSMIT_BY_FIFO
+ * - CAN_STB_TRANSMIT_BY_ID
+ * @note the secondary transmit buffer operation mode shall be switched only if reset=1.
+ * @retval none
+ */
+void can_stb_transmit_mode_set(can_type* can_x, can_stb_transmit_mode_type stb_transmit_mode)
+{
+ can_x->ctrlstat_bit.tsmode = stb_transmit_mode;
+}
+
+/**
+ * @brief get the status of can secondary transmit buffer.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @retval the status of the secondary transmit buffer.
+ * the returned value can be one of the following values:
+ * - CAN_STB_STATUS_EMPTY
+ * - CAN_STB_STATUS_LESS
+ * - CAN_STB_STATUS_MORE
+ * - CAN_STB_STATUS_FULL
+ */
+can_stb_status_type can_stb_status_get(can_type* can_x)
+{
+ uint8_t status = can_x->ctrlstat_bit.tsstat;
+ return (can_stb_status_type)status;
+}
+
+/**
+ * @brief get the status of can frame transmissions.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param transmit_status_struct: pointer to a structure which contains the status of the frame transmissions.
+ * @retval none
+ */
+void can_transmit_status_get(can_type* can_x, can_transmit_status_type* transmit_status_struct)
+{
+ transmit_status_struct->current_handle = can_x->tstat_bit.handle_1;
+ transmit_status_struct->current_tstat = (can_tstat_encoding_type)can_x->tstat_bit.tstat_1;
+ transmit_status_struct->final_handle = can_x->tstat_bit.handle_2;
+ transmit_status_struct->final_tstat = (can_tstat_encoding_type)can_x->tstat_bit.tstat_2;
+}
+
+/**
+ * @brief get the status of can receive buffer.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @retval the status of can receive buffer.
+ * the returned value can be:
+ * - CAN_RXBUF_STATUS_EMPTY
+ * - CAN_RXBUF_STATUS_LESS
+ * - CAN_RXBUF_STATUS_ALMOST
+ * - CAN_RXBUF_STATUS_FULL
+ * - CAN_RXBUF_STATUS_OVERFLOW
+ */
+can_rxbuf_status_type can_rxbuf_status_get(can_type* can_x)
+{
+ uint8_t status = can_x->ctrlstat_bit.rstat;
+
+ if(can_x->ctrlstat_bit.rov == SET)
+ {
+ status = CAN_RXBUF_STATUS_OVERFLOW;
+ }
+
+ return (can_rxbuf_status_type)status;
+}
+
+/**
+ * @brief set the mode of receive buffer overflow.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param rxbuf_overflow_mode: the mode of receive buffer overflow.
+ * this parameter can be one of the following values:
+ * - CAN_RXBUF_OVERFLOW_BE_OVWR
+ * - CAN_RXBUF_OVERFLOW_BE_LOSE
+ * @retval none
+ */
+void can_rxbuf_overflow_mode_set(can_type* can_x, can_rxbuf_overflow_mode_type rxbuf_overflow_mode)
+{
+ can_x->ctrlstat_bit.rom = rxbuf_overflow_mode;
+}
+
+/**
+ * @brief enable receive buffer stores all frames include frames with error.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param new_state: new state of receive buffer stores frames.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void can_receive_all_enable(can_type* can_x, confirm_state new_state)
+{
+ can_x->ctrlstat_bit.rball = new_state;
+}
+
+/**
+ * @brief abort a transmission from the primary transmit buffer or the secondary transmit buffer of the can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param abort_type: abort transmit type.
+ * this parameter can be one of the following values:
+ * - CAN_ABORT_TRANSMIT_PTB
+ * - CAN_ABORT_TRANSMIT_STB
+ * @retval none
+ */
+void can_transmit_abort(can_type* can_x, can_abort_transmit_type abort_type)
+{
+ uint8_t* reg = (uint8_t*)&can_x->ctrlstat + 1;
+ uint8_t tmp;
+
+ /* avoid duplicate setting these bits(tsa, tsall, tsone, tpa, tpe). */
+ tmp = *reg & 0xE0;
+ *reg = tmp | abort_type;
+}
+
+/**
+ * @brief clear the secondary transmit buffer of the can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param abort_type: abort transmit type.
+ * this parameter can be one of the following values:
+ * - CAN_CLEAR_STB_ONE
+ * - CAN_CLEAR_STB_ALL
+ * @retval SUCCESS or ERROR
+ */
+error_status can_stb_clear(can_type* can_x, can_clear_stb_type clear_type)
+{
+ uint8_t* reg = (uint8_t*)&can_x->ctrlstat + 1;
+ uint8_t tmp;
+
+ if(can_x->ctrlstat_bit.tsstat == CAN_STB_STATUS_EMPTY)
+ {
+ /* the secondary transmit buffer is empty. */
+ return ERROR;
+ }
+
+ /* avoid duplicate setting these bits(tsa, tsall, tsone, tpa, tpe). */
+ tmp = *reg & 0xE0;
+ *reg = tmp | clear_type;
+
+ return SUCCESS;
+}
+
+/**
+ * @brief transmit the frame from txbuf of the can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param transmit_type: select transmit txbuf type.
+ * this parameter can be one of the following values:
+ * - CAN_TRANSMIT_PTB
+ * - CAN_TRANSMIT_STB_ONE
+ * - CAN_TRANSMIT_STB_ALL
+ * @retval SUCCESS or ERROR
+ */
+error_status can_txbuf_transmit(can_type* can_x, can_txbuf_transmit_type transmit_type)
+{
+ uint8_t* reg = (uint8_t*)&can_x->ctrlstat + 1;
+ uint8_t tmp;
+
+ /* once standby is activated no transmission is possible. */
+ if(can_x->ctrlstat_bit.stby == SET)
+ return ERROR;
+
+ switch(transmit_type)
+ {
+ case CAN_TRANSMIT_PTB:
+ if(can_x->ctrlstat_bit.tpe || can_x->ctrlstat_bit.tpa)
+ return ERROR;
+ break;
+ case CAN_TRANSMIT_STB_ONE:
+ case CAN_TRANSMIT_STB_ALL:
+ if(can_x->ctrlstat_bit.tsstat == CAN_STB_STATUS_EMPTY)
+ return ERROR;
+ if(can_x->ctrlstat_bit.tsall || can_x->ctrlstat_bit.tsone || can_x->ctrlstat_bit.tsa)
+ return ERROR;
+ break;
+ default:
+ return ERROR;
+ }
+
+ /* avoid duplicate setting these bits(tsa, tsall, tsone, tpa, tpe). */
+ tmp = *reg & 0xE0;
+ *reg = tmp | transmit_type;
+
+ return SUCCESS;
+}
+
+/**
+ * @brief set the reference message identifier for ttcan.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param id_type: the identifier type of reference message for ttcan.
+ * this parameter can be one of the following values:
+ * - CAN_ID_STANDARD
+ * - CAN_ID_EXTENDED
+ * @param id: the identifier of reference message for ttcan.
+ * @retval none
+ */
+void can_ttcan_ref_message_set(can_type* can_x, can_identifier_type id_type, uint32_t id)
+{
+ can_x->refmsg_bit.ref_ide = id_type;
+ switch(id_type)
+ {
+ case CAN_ID_STANDARD:
+ can_x->refmsg_bit.ref_id = (0x7FF & id);
+ break;
+ case CAN_ID_EXTENDED:
+ can_x->refmsg_bit.ref_id = (0x1FFFFFFF & id);
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief set the timer prescaler for ttcan.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param div_value: can ttcan time trigger div type.
+ * this parameter can be one of the following values:
+ * - CAN_TTCAN_TIMER_DIV_1
+ * - CAN_TTCAN_TIMER_DIV_2
+ * - CAN_TTCAN_TIMER_DIV_4
+ * - CAN_TTCAN_TIMER_DIV_8
+ * @retval none
+ */
+void can_ttcan_timer_div_set(can_type* can_x, can_ttcan_timer_div_type div_value)
+{
+ can_x->ttcfg_bit.t_presc = div_value;
+}
+
+/**
+ * @brief enable time trigger for ttcan.
+ * if ttcan enabled, the timer for ttcan is running.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param new_state: new state of ttcan enable.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void can_ttcan_enable(can_type* can_x, confirm_state new_state)
+{
+ can_x->ttcfg_bit.tten = new_state;
+}
+
+/**
+ * @brief enable transmit buffer support for ttcan mode.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param new_state: new state of transmit buffer support for ttcan.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void can_ttcan_txbuf_enable(can_type* can_x, confirm_state new_state)
+{
+ can_x->ctrlstat_bit.tttbm = new_state;
+}
+
+/**
+ * @brief set the trigger type for ttcan.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param trigger_type: can ttcan trigger type.
+ * this parameter can be one of the following values:
+ * - CAN_TTCAN_TRIGGER_IMMEDIATE
+ * - CAN_TTCAN_TRIGGER_TIME
+ * - CAN_TTCAN_TRIGGER_SINGLE_TRANSMIT
+ * - CAN_TTCAN_TRIGGER_TRANSMIT_START
+ * - CAN_TTCAN_TRIGGER_TRANSMIT_STOP
+ * @retval none
+ */
+void can_ttcan_trigger_type_set(can_type* can_x, can_ttcan_trigger_type trigger_type)
+{
+ can_x->ttcfg_bit.ttype = trigger_type;
+}
+
+/**
+ * @brief set the cycle time for a time trigger for ttcan.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param trigger_time: defines the cycle time for a time trigger.
+ * @retval none
+ */
+void can_ttcan_trigger_set(can_type* can_x, uint16_t trigger_time)
+{
+ uint16_t* reg = (uint16_t*)&(can_x->tttrig);
+ *reg = trigger_time;
+}
+
+/**
+ * @brief set the cycle time for a watch time trigger for ttcan.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param watch_trigger_time: defines the cycle time for a watch time trigger.
+ * @retval none
+ */
+void can_ttcan_watch_trigger_set(can_type* can_x, uint16_t watch_trigger_time)
+{
+ uint16_t* reg = (uint16_t*)&(can_x->tttrig);
+ *(reg + 1) = watch_trigger_time;
+}
+
+/**
+ * @brief set the txbuf slot status for ttcan.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param txbuf_number: pointer to a txbuf frame slot.
+ * this parameter can be one of the following values:
+ * - CAN_TTCAN_TXBUF_NUM_0
+ * - CAN_TTCAN_TXBUF_NUM_1
+ * - CAN_TTCAN_TXBUF_NUM_2
+ * - CAN_TTCAN_TXBUF_NUM_3
+ * @param ttcan_buffer_type: ttcan txbuf slot status.
+ * this parameter can be one of the following values:
+ * - CAN_TTCAN_TXBUF_EMPTY
+ * - CAN_TTCAN_TXBUF_FILLED
+ * @retval none
+ */
+void can_ttcan_txbuf_status_set(can_type* can_x, can_ttcan_txbuf_type txbuf_number, can_ttcan_txbuf_status_type status_type)
+{
+ can_x->ttcfg_bit.tbptr = txbuf_number;
+ switch(status_type)
+ {
+ case CAN_TTCAN_TXBUF_EMPTY:
+ can_x->ttcfg_bit.tbe = TRUE;
+ break;
+ case CAN_TTCAN_TXBUF_FILLED:
+ can_x->ttcfg_bit.tbf = TRUE;
+ break;
+ default:
+ return;
+ }
+}
+
+/**
+ * @brief get the txbuf slot status for ttcan.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param txbuf_number: pointer to a txbuf frame slot.
+ * this parameter can be one of the following values:
+ * - CAN_TTCAN_TXBUF_NUM_0
+ * - CAN_TTCAN_TXBUF_NUM_1
+ * - CAN_TTCAN_TXBUF_NUM_2
+ * - CAN_TTCAN_TXBUF_NUM_3
+ * @retval ttcan_buffer_type: ttcan txbuf slot status.
+ * this parameter can be one of the following values:
+ * - CAN_TTCAN_TXBUF_EMPTY
+ * - CAN_TTCAN_TXBUF_FILLED
+ */
+can_ttcan_txbuf_status_type can_ttcan_txbuf_status_get(can_type* can_x, can_ttcan_txbuf_type txbuf_number)
+{
+ can_x->ttcfg_bit.tbptr = txbuf_number;
+ if(can_x->ctrlstat_bit.tsff != SET)
+ {
+ return CAN_TTCAN_TXBUF_EMPTY;
+ }
+ else{
+ return CAN_TTCAN_TXBUF_FILLED;
+ }
+}
+
+/**
+ * @brief write the transmission buffer of the can peripheral for ttcan.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param txbuf_number: pointer to a txbuf frame slot.
+ * this parameter can be one of the following values:
+ * - CAN_TTCAN_TXBUF_NUM_0
+ * - CAN_TTCAN_TXBUF_NUM_1
+ * - CAN_TTCAN_TXBUF_NUM_2
+ * - CAN_TTCAN_TXBUF_NUM_3
+ * @param can_txbuf_struct: pointer to a structure which contains the buffer to be trans.
+ * @retval SUCCESS or ERROR.
+ */
+error_status can_ttcan_txbuf_write(can_type* can_x, can_ttcan_txbuf_type txbuf_number, can_txbuf_type* can_txbuf_struct)
+{
+#ifdef SUPPORT_CAN_FD
+ uint8_t len = dlc_to_bytes[can_txbuf_struct->data_length];
+#else
+ uint8_t len = can_txbuf_struct->data_length;
+#endif
+ uint32_t *wp = (uint32_t*)can_x->tbdat;
+ uint8_t *rp = can_txbuf_struct->data;
+ uint8_t byte_cnt;
+
+ can_x->ttcfg_bit.tbptr = txbuf_number;
+ if(can_x->ctrlstat_bit.tsff == SET)
+ {
+ /* the buffer slot selected by tbptr be filled are write-locked. */
+ return ERROR;
+ }
+
+ switch(can_txbuf_struct->id_type)
+ {
+ case CAN_ID_STANDARD:
+ can_x->tbid = (0x7FF & can_txbuf_struct->id)<<18;
+ break;
+ case CAN_ID_EXTENDED:
+ can_x->tbid = (0x1FFFFFFF & can_txbuf_struct->id);
+ break;
+ default:
+ return ERROR;
+ }
+ can_x->tbid |= (can_txbuf_struct->tx_timestamp << 31);
+
+ can_x->tbfmt = 0;
+ can_x->tbfmt_bit.ide = can_txbuf_struct->id_type;
+ can_x->tbfmt_bit.rmf = can_txbuf_struct->frame_type;
+ can_x->tbfmt_bit.dlc = can_txbuf_struct->data_length;
+#ifdef SUPPORT_CAN_FD
+ can_x->tbfmt_bit.brs = can_txbuf_struct->fd_rate_switch;
+ can_x->tbfmt_bit.fdf = can_txbuf_struct->fd_format;
+#endif
+
+ /* write tx payload to the message ram */
+ for (byte_cnt = 0; byte_cnt < len; byte_cnt += 4U)
+ {
+ *wp++ = (((uint32_t)rp[byte_cnt + 3U] << 24U) |
+ ((uint32_t)rp[byte_cnt + 2U] << 16U) |
+ ((uint32_t)rp[byte_cnt + 1U] << 8U) |
+ (uint32_t)rp[byte_cnt]);
+ }
+
+ can_x->tbtyp = 0;
+ can_x->tbtyp_bit.handle = can_txbuf_struct->handle;
+ can_x->reserved8 = 0;
+
+ /* the buffer slot selected by tbptr shall be marked as filled. */
+ can_x->ttcfg_bit.tbf = TRUE;
+
+ return SUCCESS;
+}
+
+/**
+ * @brief set transmit trigger txbuf slot pointer for ttcan.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param txbuf_number: pointer to a txbuf frame slot.
+ * this parameter can be one of the following values:
+ * - CAN_TTCAN_TXBUF_NUM_0
+ * - CAN_TTCAN_TXBUF_NUM_1
+ * - CAN_TTCAN_TXBUF_NUM_2
+ * - CAN_TTCAN_TXBUF_NUM_3
+ * @retval none
+ */
+void can_ttcan_txbuf_transmit_set(can_type* can_x, can_ttcan_txbuf_type txbuf_number)
+{
+ can_x->ttcfg_bit.ttptr = txbuf_number;
+}
+
+/**
+ * @brief set transmit enable window for ttcan.
+ * for a single shot transmit trigger there is a time of up to 16 ticks of the cycle time where the frame is allowed to start.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param window_ticks: transmit enable window. window_ticks+1 defines the number of ticks.
+ * this parameter can be 0~15.
+ * @retval none
+ */
+void can_ttcan_transmit_window_set(can_type* can_x, uint8_t window_ticks)
+{
+ can_x->ttcfg_bit.tew = window_ticks;
+}
+
+/**
+ * @brief enable or disable the interrupt of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param can_int: specifies the can interrupt sources to be enabled or disabled.
+ * this parameter can be one of the following values:
+ * - CAN_AIE_INT
+ * - CAN_EIE_INT
+ * - CAN_TSIE_INT
+ * - CAN_TPIE_INT
+ * - CAN_RAFIE_INT
+ * - CAN_RFIE_INT
+ * - CAN_ROIE_INT
+ * - CAN_RIE_INT
+ * - CAN_BEIE_INT
+ * - CAN_ALIE_INT
+ * - CAN_EPIE_INT
+ * - CAN_TTIE_INT
+ * - CAN_TEIF_FLAG
+ * - CAN_WTIE_INT
+ * - CAN_ALL_INT
+ * @param new_state: new state of the can interrupts.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none.
+ */
+void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state)
+{
+ if (new_state != FALSE)
+ {
+ can_x->inten |= can_int;
+ }
+ else
+ {
+ can_x->inten &= ~can_int;
+ }
+}
+
+/**
+ * @brief get flag of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param can_flag: select the flag.
+ * this parameter can be one of the following flags:
+ * - CAN_AIF_FLAG
+ * - CAN_EIF_FLAG
+ * - CAN_TSIF_FLAG
+ * - CAN_TPIF_FLAG
+ * - CAN_RAFIF_FLAG
+ * - CAN_RFIF_FLAG
+ * - CAN_ROIF_FLAG
+ * - CAN_RIF_FLAG
+ * - CAN_BEIF_FLAG
+ * - CAN_ALIF_FLAG
+ * - CAN_EPIF_FLAG
+ * - CAN_TTIF_FLAG
+ * - CAN_TEIF_FLAG
+ * - CAN_WTIE_FLAG
+ * - CAN_EPASS_FLAG
+ * - CAN_EWARN_FLAG
+ * @retval status of can flag, the returned value can be: SET or RESET.
+ */
+flag_status can_flag_get(can_type* can_x, uint32_t can_flag)
+{
+ flag_status bit_status = RESET;
+ if(can_x->sts & can_flag)
+ {
+ bit_status = SET;
+ }
+ return bit_status;
+}
+
+/**
+ * @brief get interrupt flag of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param can_flag: select the flag.
+ * this parameter can be one of the following flags:
+ * - CAN_AIF_FLAG
+ * - CAN_EIF_FLAG
+ * - CAN_TSIF_FLAG
+ * - CAN_TPIF_FLAG
+ * - CAN_RAFIF_FLAG
+ * - CAN_RFIF_FLAG
+ * - CAN_ROIF_FLAG
+ * - CAN_RIF_FLAG
+ * - CAN_BEIF_FLAG
+ * - CAN_ALIF_FLAG
+ * - CAN_EPIF_FLAG
+ * - CAN_TTIF_FLAG
+ * - CAN_TEIF_FLAG
+ * - CAN_WTIE_FLAG
+ * @retval flag_status (SET or RESET)
+ */
+flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag)
+{
+ flag_status status = RESET;
+ if((can_x->inten & can_flag) && (can_x->sts & can_flag))
+ {
+ status = SET;
+ }
+ return status;
+}
+
+/**
+ * @brief clear flag of the specified can peripheral.
+ * @param can_x: select the can peripheral.
+ * this parameter can be one of the following values:
+ * CAN1, CAN2, CAN3.
+ * @param can_flag: select the flag.
+ * this parameter can be one of the following flags:
+ * - CAN_AIF_FLAG
+ * - CAN_EIF_FLAG
+ * - CAN_TSIF_FLAG
+ * - CAN_TPIF_FLAG
+ * - CAN_RAFIF_FLAG
+ * - CAN_RFIF_FLAG
+ * - CAN_ROIF_FLAG
+ * - CAN_RIF_FLAG
+ * - CAN_BEIF_FLAG
+ * - CAN_ALIF_FLAG
+ * - CAN_EPIF_FLAG
+ * - CAN_TTIF_FLAG
+ * - CAN_TEIF_FLAG
+ * - CAN_WTIE_FLAG
+ * - CAN_EPASS_FLAG
+ * - CAN_EWARN_FLAG
+ * - CAN_ALL_FLAG
+ * @retval none.
+ */
+void can_flag_clear(can_type* can_x, uint32_t can_flag)
+{
+ can_x->sts = can_flag;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_crc.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_crc.c
new file mode 100644
index 00000000000..5f471491248
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_crc.c
@@ -0,0 +1,208 @@
+/**
+ **************************************************************************
+ * @file at32f45x_crc.c
+ * @brief contains all the functions for the crc firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup CRC
+ * @brief CRC driver modules
+ * @{
+ */
+
+#ifdef CRC_MODULE_ENABLED
+
+/** @defgroup CRC_private_functions
+ * @{
+ */
+
+/**
+ * @brief reset the crc data register.
+ * @param none
+ * @retval none
+ */
+void crc_data_reset(void)
+{
+ /* reset crc generator */
+ CRC->ctrl_bit.rst = 0x1;
+}
+
+/**
+ * @brief compute the 32-bit crc of a given data word(32-bit).
+ * @param data: data word(32-bit) to compute its crc
+ * @retval 32-bit crc
+ */
+uint32_t crc_one_word_calculate(uint32_t data)
+{
+ CRC->dt = data;
+ return (CRC->dt);
+}
+
+/**
+ * @brief compute the 32-bit crc of a given buffer of data word(32-bit).
+ * @param pbuffer: pointer to the buffer containing the data to be computed
+ * @param length: length of the buffer to be computed
+ * @retval 32-bit crc
+ */
+uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length)
+{
+ uint32_t index = 0;
+
+ for(index = 0; index < length; index++)
+ {
+ CRC->dt = pbuffer[index];
+ }
+
+ return (CRC->dt);
+}
+
+/**
+ * @brief return the current crc value.
+ * @param none
+ * @retval 32-bit crc
+ */
+uint32_t crc_data_get(void)
+{
+ return (CRC->dt);
+}
+
+/**
+ * @brief store a 8-bit data in the common data register.
+ * @param cdt_value: 8-bit value to be stored in the common data register
+ * @retval none
+ */
+void crc_common_data_set(uint8_t cdt_value)
+{
+ CRC->cdt_bit.cdt = cdt_value;
+}
+
+/**
+ * @brief return the 8-bit data stored in the common data register
+ * @param none
+ * @retval 8-bit value of the common data register
+ */
+uint8_t crc_common_data_get(void)
+{
+ return (CRC->cdt_bit.cdt);
+}
+
+/**
+ * @brief set the 32-bit initial data of crc
+ * @param value: initial data
+ * @retval none
+ */
+void crc_init_data_set(uint32_t value)
+{
+ CRC->idt = value;
+}
+
+/**
+ * @brief control the reversal of the bit order in the input data
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRC_REVERSE_INPUT_NO_AFFECTE
+ * - CRC_REVERSE_INPUT_BY_BYTE
+ * - CRC_REVERSE_INPUT_BY_HALFWORD
+ * - CRC_REVERSE_INPUT_BY_WORD
+ * @retval none.
+ */
+void crc_reverse_input_data_set(crc_reverse_input_type value)
+{
+ CRC->ctrl_bit.revid = value;
+}
+
+/**
+ * @brief control the reversal of the bit order in the output data
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRC_REVERSE_OUTPUT_NO_AFFECTE
+ * - CRC_REVERSE_OUTPUT_DATA
+ * @retval none.
+ */
+void crc_reverse_output_data_set(crc_reverse_output_type value)
+{
+ CRC->ctrl_bit.revod = value;
+}
+
+/**
+ * @brief config crc polynomial value
+ * @param value
+ * 32-bit new data of crc poly value
+ * @retval none.
+ */
+void crc_poly_value_set(uint32_t value)
+{
+ CRC->poly = value;
+}
+
+/**
+ * @brief return crc polynomial value
+ * @param none
+ * @retval 32-bit value of the polynomial value.
+ */
+uint32_t crc_poly_value_get(void)
+{
+ return (CRC->poly);
+}
+
+/**
+ * @brief config crc polynomial data size
+ * @param size
+ * this parameter can be one of the following values:
+ * - CRC_POLY_SIZE_32B
+ * - CRC_POLY_SIZE_16B
+ * - CRC_POLY_SIZE_8B
+ * - CRC_POLY_SIZE_7B
+ * @retval none.
+ */
+void crc_poly_size_set(crc_poly_size_type size)
+{
+ CRC->ctrl_bit.poly_size = size;
+}
+
+/**
+ * @brief return crc polynomial data size
+ * @param none
+ * @retval polynomial data size.
+ */
+crc_poly_size_type crc_poly_size_get(void)
+{
+ return (crc_poly_size_type)(CRC->ctrl_bit.poly_size);
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_crm.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_crm.c
new file mode 100644
index 00000000000..2518c670969
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_crm.c
@@ -0,0 +1,1148 @@
+/**
+ **************************************************************************
+ * @file at32f45x_crm.c
+ * @brief contains all the functions for the crm firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup CRM
+ * @brief CRM driver modules
+ * @{
+ */
+
+#ifdef CRM_MODULE_ENABLED
+
+/** @defgroup CRM_private_functions
+ * @{
+ */
+
+/**
+ * @brief reset the crm register
+ * @param none
+ * @retval none
+ */
+void crm_reset(void)
+{
+ /* reset the crm clock configuration to the default reset state(for debug purpose) */
+ /* enable auto step mode */
+ crm_auto_step_mode_enable(TRUE);
+
+ /* set hicken bit */
+ CRM->ctrl_bit.hicken = TRUE;
+
+ /* wait hick stable */
+ while(CRM->ctrl_bit.hickstbl != SET);
+
+ /* hick used as system clock */
+ CRM->cfg_bit.sclksel = CRM_SCLK_HICK;
+
+ /* wait sclk switch status */
+ while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK);
+
+ /* reset hexten, hextbyps, cfden and pllen bits */
+ CRM->ctrl &= ~(0x010D0000U);
+
+ /* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv, clkout bits */
+ CRM->cfg = 0x40000000U;
+
+ /* reset pllms pllns pllfp pllrcs bits */
+ CRM->pllcfg = 0x000007C1U;
+
+ /* reset clkout_sel, clkoutdiv */
+ CRM->misc1 = 0x000F1000;
+
+ /* disable all interrupts enable and clear pending bits */
+ CRM->clkint = 0x009F0000U;
+
+ /* disable auto step mode */
+ crm_auto_step_mode_enable(FALSE);
+}
+
+/**
+ * @brief enable or disable crm low speed external crystal bypass
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void crm_lext_bypass(confirm_state new_state)
+{
+ CRM->bpdc_bit.lextbyps = new_state;
+}
+
+/**
+ * @brief enable or disable crm high speed external crystal bypass
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void crm_hext_bypass(confirm_state new_state)
+{
+ CRM->ctrl_bit.hextbyps = new_state;
+}
+
+/**
+ * @brief get crm flag status
+ * @param flag
+ * this parameter can be one of the following values:
+ * - CRM_HICK_STABLE_FLAG
+ * - CRM_HEXT_STABLE_FLAG
+ * - CRM_PLL_STABLE_FLAG
+ * - CRM_PLLU_STABLE_FLAG
+ * - CRM_LEXT_STABLE_FLAG
+ * - CRM_LICK_STABLE_FLAG
+ * - CRM_PIN_RESET_FLAG
+ * - CRM_POR_RESET_FLAG
+ * - CRM_SW_RESET_FLAG
+ * - CRM_WDT_RESET_FLAG
+ * - CRM_WWDT_RESET_FLAG
+ * - CRM_LOWPOWER_RESET_FLAG
+ * interrupt flag:
+ * - CRM_LICK_READY_INT_FLAG
+ * - CRM_LEXT_READY_INT_FLAG
+ * - CRM_HICK_READY_INT_FLAG
+ * - CRM_HEXT_READY_INT_FLAG
+ * - CRM_PLL_READY_INT_FLAG
+ * - CRM_CLOCK_FAILURE_INT_FLAG
+ * @retval flag_status (SET or RESET)
+ */
+flag_status crm_flag_get(uint32_t flag)
+{
+ flag_status status = RESET;
+ if((CRM_REG(flag) & CRM_REG_BIT(flag)) != CRM_REG_BIT(flag))
+ {
+ status = RESET;
+ }
+ else
+ {
+ status = SET;
+ }
+ return status;
+}
+
+/**
+ * @brief wait for hext stable
+ * @param none
+ * @retval error_status (ERROR or SUCCESS)
+ */
+error_status crm_hext_stable_wait(void)
+{
+ uint32_t stable_cnt = 0;
+ error_status status = ERROR;
+
+ while((crm_flag_get(CRM_HEXT_STABLE_FLAG) != SET) && (stable_cnt < HEXT_STARTUP_TIMEOUT))
+ {
+ stable_cnt ++;
+ }
+
+ if(crm_flag_get(CRM_HEXT_STABLE_FLAG) != SET)
+ {
+ status = ERROR;
+ }
+ else
+ {
+ status = SUCCESS;
+ }
+
+ return status;
+}
+
+/**
+ * @brief set the hick trimming value
+ * @param trim_value (0x00~0x3F)
+ * @retval none
+ */
+void crm_hick_clock_trimming_set(uint8_t trim_value)
+{
+ CRM->ctrl_bit.hicktrim = trim_value;
+}
+
+/**
+ * @brief set the crm calibration value
+ * @param cali_value (0x00~0xFF)
+ * @retval none
+ */
+void crm_hick_clock_calibration_set(uint8_t cali_value)
+{
+ /* enable write hick calibration */
+ CRM->misc1_bit.hickcal_key = 0x5A;
+
+ /* write hick calibration value */
+ CRM->ctrl_bit.hickcal = cali_value;
+
+ /* disable write hick calibration */
+ CRM->misc1_bit.hickcal_key = 0x0;
+}
+
+/**
+ * @brief enable or disable the peripheral clock
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_GPIOA_PERIPH_CLOCK - CRM_GPIOB_PERIPH_CLOCK - CRM_GPIOC_PERIPH_CLOCK - CRM_GPIOD_PERIPH_CLOCK
+ * - CRM_GPIOE_PERIPH_CLOCK - CRM_GPIOF_PERIPH_CLOCK - CRM_GPIOG_PERIPH_CLOCK - CRM_GPIOH_PERIPH_CLOCK
+ * - CRM_CRC_PERIPH_CLOCK - CRM_DMA1_PERIPH_CLOCK - CRM_DMA2_PERIPH_CLOCK - CRM_EMAC_PERIPH_CLOCK
+ * - CRM_EMACTX_PERIPH_CLOCK - CRM_EMACRX_PERIPH_CLOCK - CRM_EMACPTP_PERIPH_CLOCK - CRM_AES_PERIPH_CLOCK
+ * - CRM_TRNG_PERIPH_CLOCK - CRM_OTGFS1_PERIPH_CLOCK - CRM_SDIO1_PERIPH_CLOCK - CRM_XMC_PERIPH_CLOCK
+ * - CRM_QSPI1_PERIPH_CLOCK - CRM_TMR2_PERIPH_CLOCK - CRM_TMR3_PERIPH_CLOCK - CRM_TMR4_PERIPH_CLOCK
+ * - CRM_TMR5_PERIPH_CLOCK - CRM_TMR6_PERIPH_CLOCK - CRM_TMR7_PERIPH_CLOCK - CRM_TMR12_PERIPH_CLOCK
+ * - CRM_TMR13_PERIPH_CLOCK - CRM_TMR14_PERIPH_CLOCK - CRM_WWDT_PERIPH_CLOCK - CRM_SPI2_PERIPH_CLOCK
+ * - CRM_SPI3_PERIPH_CLOCK - CRM_USART2_PERIPH_CLOCK - CRM_USART3_PERIPH_CLOCK - CRM_USART4_PERIPH_CLOCK
+ * - CRM_USART5_PERIPH_CLOCK - CRM_I2C1_PERIPH_CLOCK - CRM_I2C2_PERIPH_CLOCK - CRM_I2C3_PERIPH_CLOCK
+ * - CRM_CAN1_PERIPH_CLOCK - CRM_CAN2_PERIPH_CLOCK - CRM_CAN3_PERIPH_CLOCK - CRM_PWC_PERIPH_CLOCK
+ * - CRM_DAC_PERIPH_CLOCK - CRM_USART7_PERIPH_CLOCK - CRM_USART8_PERIPH_CLOCK - CRM_TMR1_PERIPH_CLOCK
+ * - CRM_TMR8_PERIPH_CLOCK - CRM_USART1_PERIPH_CLOCK - CRM_USART6_PERIPH_CLOCK - CRM_ADC2_PERIPH_CLOCK
+ * - CRM_ADC1_PERIPH_CLOCK - CRM_SPI1_PERIPH_CLOCK - CRM_SPI4_PERIPH_CLOCK - CRM_SCFG_PERIPH_CLOCK
+ * - CRM_TMR9_PERIPH_CLOCK - CRM_TMR10_PERIPH_CLOCK - CRM_TMR11_PERIPH_CLOCK - CRM_I2SF5_PERIPH_CLOCK
+ * - CRM_ACC_PERIPH_CLOCK - CRM_I2S2EXT_PERIPH_CLOCK - CRM_I2S3EXT_PERIPH_CLOCK
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void crm_periph_clock_enable(crm_periph_clock_type value, confirm_state new_state)
+{
+ /* enable periph clock */
+ if(TRUE == new_state)
+ {
+ CRM_REG(value) |= CRM_REG_BIT(value);
+ }
+ /* disable periph clock */
+ else
+ {
+ CRM_REG(value) &= ~(CRM_REG_BIT(value));
+ }
+}
+
+/**
+ * @brief enable or disable the peripheral reset
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_GPIOA_PERIPH_RESET - CRM_GPIOB_PERIPH_RESET - CRM_GPIOC_PERIPH_RESET - CRM_GPIOD_PERIPH_RESET
+ * - CRM_GPIOE_PERIPH_RESET - CRM_GPIOF_PERIPH_RESET - CRM_GPIOG_PERIPH_RESET - CRM_GPIOH_PERIPH_RESET
+ * - CRM_CRC_PERIPH_RESET - CRM_DMA1_PERIPH_RESET - CRM_DMA2_PERIPH_RESET - CRM_EMAC_PERIPH_RESET
+ * - CRM_AES_PERIPH_RESET - CRM_TRNG_PERIPH_RESET - CRM_OTGFS1_PERIPH_RESET - CRM_SDIO1_PERIPH_RESET
+ * - CRM_XMC_PERIPH_RESET - CRM_QSPI1_PERIPH_RESET - CRM_TMR2_PERIPH_RESET - CRM_TMR3_PERIPH_RESET
+ * - CRM_TMR4_PERIPH_RESET - CRM_TMR5_PERIPH_RESET - CRM_TMR6_PERIPH_RESET - CRM_TMR7_PERIPH_RESET
+ * - CRM_TMR12_PERIPH_RESET - CRM_TMR13_PERIPH_RESET - CRM_TMR14_PERIPH_RESET - CRM_WWDT_PERIPH_RESET
+ * - CRM_SPI2_PERIPH_RESET - CRM_SPI3_PERIPH_RESET - CRM_USART2_PERIPH_RESET - CRM_USART3_PERIPH_RESET
+ * - CRM_USART4_PERIPH_RESET - CRM_USART5_PERIPH_RESET - CRM_I2C1_PERIPH_RESET - CRM_I2C2_PERIPH_RESET
+ * - CRM_I2C3_PERIPH_RESET - CRM_CAN1_PERIPH_RESET - CRM_CAN2_PERIPH_RESET - CRM_CAN3_PERIPH_RESET
+ * - CRM_PWC_PERIPH_RESET - CRM_DAC_PERIPH_RESET - CRM_USART7_PERIPH_RESET - CRM_USART8_PERIPH_RESET
+ * - CRM_TMR1_PERIPH_RESET - CRM_TMR8_PERIPH_RESET - CRM_USART1_PERIPH_RESET - CRM_USART6_PERIPH_RESET
+ * - CRM_ADC2_PERIPH_RESET - CRM_ADC1_PERIPH_RESET - CRM_SPI1_PERIPH_RESET - CRM_SPI4_PERIPH_RESET
+ * - CRM_SCFG_PERIPH_RESET - CRM_TMR9_PERIPH_RESET - CRM_TMR10_PERIPH_RESET - CRM_TMR11_PERIPH_RESET
+ * - CRM_I2SF5_PERIPH_RESET - CRM_ACC_PERIPH_RESET - CRM_I2S2EXT_PERIPH_RESET - CRM_I2S3EXT_PERIPH_RESET
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void crm_periph_reset(crm_periph_reset_type value, confirm_state new_state)
+{
+ /* enable periph reset */
+ if(new_state == TRUE)
+ {
+ CRM_REG(value) |= (CRM_REG_BIT(value));
+ }
+ /* disable periph reset */
+ else
+ {
+ CRM_REG(value) &= ~(CRM_REG_BIT(value));
+ }
+}
+
+/**
+ * @brief enable or disable the peripheral clock in lowpower mode
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_GPIOA_PERIPH_LOWPOWER - CRM_GPIOB_PERIPH_LOWPOWER - CRM_GPIOC_PERIPH_LOWPOWER - CRM_GPIOD_PERIPH_LOWPOWER
+ * - CRM_GPIOE_PERIPH_LOWPOWER - CRM_GPIOF_PERIPH_LOWPOWER - CRM_GPIOG_PERIPH_LOWPOWER - CRM_GPIOH_PERIPH_LOWPOWER
+ * - CRM_CRC_PERIPH_LOWPOWER - CRM_DMA1_PERIPH_LOWPOWER - CRM_DMA2_PERIPH_LOWPOWER - CRM_EMAC_PERIPH_LOWPOWER
+ * - CRM_EMACTX_PERIPH_LOWPOWER - CRM_EMACRX_PERIPH_LOWPOWER - CRM_EMACPTP_PERIPH_LOWPOWER - CRM_AES_PERIPH_LOWPOWER
+ * - CRM_TRNG_PERIPH_LOWPOWER - CRM_OTGFS1_PERIPH_LOWPOWER - CRM_SDIO1_PERIPH_LOWPOWER - CRM_XMC_PERIPH_LOWPOWER
+ * - CRM_QSPI1_PERIPH_LOWPOWER - CRM_TMR2_PERIPH_LOWPOWER - CRM_TMR3_PERIPH_LOWPOWER - CRM_TMR4_PERIPH_LOWPOWER
+ * - CRM_TMR5_PERIPH_LOWPOWER - CRM_TMR6_PERIPH_LOWPOWER - CRM_TMR7_PERIPH_LOWPOWER - CRM_TMR12_PERIPH_LOWPOWER
+ * - CRM_TMR13_PERIPH_LOWPOWER - CRM_TMR14_PERIPH_LOWPOWER - CRM_WWDT_PERIPH_LOWPOWER - CRM_SPI2_PERIPH_LOWPOWER
+ * - CRM_SPI3_PERIPH_LOWPOWER - CRM_USART2_PERIPH_LOWPOWER - CRM_USART3_PERIPH_LOWPOWER - CRM_USART4_PERIPH_LOWPOWER
+ * - CRM_USART5_PERIPH_LOWPOWER - CRM_I2C1_PERIPH_LOWPOWER - CRM_I2C2_PERIPH_LOWPOWER - CRM_I2C3_PERIPH_LOWPOWER
+ * - CRM_CAN1_PERIPH_LOWPOWER - CRM_CAN2_PERIPH_LOWPOWER - CRM_CAN3_PERIPH_LOWPOWER - CRM_PWC_PERIPH_LOWPOWER
+ * - CRM_DAC_PERIPH_LOWPOWER - CRM_USART7_PERIPH_LOWPOWER - CRM_USART8_PERIPH_LOWPOWER - CRM_TMR1_PERIPH_LOWPOWER
+ * - CRM_TMR8_PERIPH_LOWPOWER - CRM_USART1_PERIPH_LOWPOWER - CRM_USART6_PERIPH_LOWPOWER - CRM_ADC2_PERIPH_LOWPOWER
+ * - CRM_ADC1_PERIPH_LOWPOWER - CRM_SPI1_PERIPH_LOWPOWER - CRM_SPI4_PERIPH_LOWPOWER - CRM_SCFG_PERIPH_LOWPOWER
+ * - CRM_TMR9_PERIPH_LOWPOWER - CRM_TMR10_PERIPH_LOWPOWER - CRM_TMR11_PERIPH_LOWPOWER - CRM_I2SF5_PERIPH_LOWPOWER
+ * - CRM_ACC_PERIPH_LOWPOWER - CRM_I2S2EXT_PERIPH_LOWPOWER - CRM_I2S3EXT_PERIPH_LOWPOWER
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void crm_periph_lowpower_mode_enable(crm_periph_clock_lowpower_type value, confirm_state new_state)
+{
+ /* enable periph clock in lowpower mode */
+ if(new_state == TRUE)
+ {
+ CRM_REG(value) |= (CRM_REG_BIT(value));
+ }
+ /* disable periph clock in lowpower mode */
+ else
+ {
+ CRM_REG(value) &= ~(CRM_REG_BIT(value));
+ }
+}
+
+/**
+ * @brief enable or disable the crm clock source
+ * @param source
+ * this parameter can be one of the following values:
+ * - CRM_CLOCK_SOURCE_HICK
+ * - CRM_CLOCK_SOURCE_HEXT
+ * - CRM_CLOCK_SOURCE_PLL
+ * - CRM_CLOCK_SOURCE_LEXT
+ * - CRM_CLOCK_SOURCE_LICK
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void crm_clock_source_enable(crm_clock_source_type source, confirm_state new_state)
+{
+ switch(source)
+ {
+ case CRM_CLOCK_SOURCE_HICK:
+ CRM->ctrl_bit.hicken = new_state;
+ break;
+ case CRM_CLOCK_SOURCE_HEXT:
+ CRM->ctrl_bit.hexten = new_state;
+ break;
+ case CRM_CLOCK_SOURCE_PLL:
+ CRM->ctrl_bit.pllen = new_state;
+ break;
+ case CRM_CLOCK_SOURCE_LEXT:
+ CRM->bpdc_bit.lexten = new_state;
+ break;
+ case CRM_CLOCK_SOURCE_LICK:
+ CRM->ctrlsts_bit.licken = new_state;
+ break;
+ default: break;
+ }
+}
+
+/**
+ * @brief clear the crm reset flags
+ * @param flag
+ * this parameter can be one of the following values:
+ * reset flag:
+ * - CRM_PIN_RESET_FLAG
+ * - CRM_POR_RESET_FLAG
+ * - CRM_SW_RESET_FLAG
+ * - CRM_WDT_RESET_FLAG
+ * - CRM_WWDT_RESET_FLAG
+ * - CRM_LOWPOWER_RESET_FLAG
+ * - CRM_ALL_RESET_FLAG
+ * interrupt flag:
+ * - CRM_LICK_READY_INT_FLAG
+ * - CRM_LEXT_READY_INT_FLAG
+ * - CRM_HICK_READY_INT_FLAG
+ * - CRM_HEXT_READY_INT_FLAG
+ * - CRM_PLL_READY_INT_FLAG
+ * - CRM_CLOCK_FAILURE_INT_FLAG
+ * @retval none
+ */
+void crm_flag_clear(uint32_t flag)
+{
+ switch(flag)
+ {
+ case CRM_NRST_RESET_FLAG:
+ case CRM_POR_RESET_FLAG:
+ case CRM_SW_RESET_FLAG:
+ case CRM_WDT_RESET_FLAG:
+ case CRM_WWDT_RESET_FLAG:
+ case CRM_LOWPOWER_RESET_FLAG:
+ case CRM_ALL_RESET_FLAG:
+ CRM->ctrlsts_bit.rstfc = TRUE;
+ while(CRM->ctrlsts_bit.rstfc == TRUE);
+ break;
+ case CRM_LICK_READY_INT_FLAG:
+ CRM->clkint_bit.lickstblfc = TRUE;
+ break;
+ case CRM_LEXT_READY_INT_FLAG:
+ CRM->clkint_bit.lextstblfc = TRUE;
+ break;
+ case CRM_HICK_READY_INT_FLAG:
+ CRM->clkint_bit.hickstblfc = TRUE;
+ break;
+ case CRM_HEXT_READY_INT_FLAG:
+ CRM->clkint_bit.hextstblfc = TRUE;
+ break;
+ case CRM_PLL_READY_INT_FLAG:
+ CRM->clkint_bit.pllstblfc = TRUE;
+ break;
+ case CRM_CLOCK_FAILURE_INT_FLAG:
+ CRM->clkint_bit.cfdfc = TRUE;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief select ertc clock
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_ERTC_CLOCK_NOCLK
+ * - CRM_ERTC_CLOCK_LEXT
+ * - CRM_ERTC_CLOCK_LICK
+ * - CRM_ERTC_CLOCK_HEXT_DIV_2
+ * - CRM_ERTC_CLOCK_HEXT_DIV_3
+ * - CRM_ERTC_CLOCK_HEXT_DIV_4
+ * - CRM_ERTC_CLOCK_HEXT_DIV_5
+ * - CRM_ERTC_CLOCK_HEXT_DIV_6
+ * - CRM_ERTC_CLOCK_HEXT_DIV_7
+ * - CRM_ERTC_CLOCK_HEXT_DIV_8
+ * - CRM_ERTC_CLOCK_HEXT_DIV_9
+ * - CRM_ERTC_CLOCK_HEXT_DIV_10
+ * - CRM_ERTC_CLOCK_HEXT_DIV_11
+ * - CRM_ERTC_CLOCK_HEXT_DIV_12
+ * - CRM_ERTC_CLOCK_HEXT_DIV_13
+ * - CRM_ERTC_CLOCK_HEXT_DIV_14
+ * - CRM_ERTC_CLOCK_HEXT_DIV_15
+ * - CRM_ERTC_CLOCK_HEXT_DIV_16
+ * - CRM_ERTC_CLOCK_HEXT_DIV_17
+ * - CRM_ERTC_CLOCK_HEXT_DIV_18
+ * - CRM_ERTC_CLOCK_HEXT_DIV_19
+ * - CRM_ERTC_CLOCK_HEXT_DIV_20
+ * - CRM_ERTC_CLOCK_HEXT_DIV_21
+ * - CRM_ERTC_CLOCK_HEXT_DIV_22
+ * - CRM_ERTC_CLOCK_HEXT_DIV_23
+ * - CRM_ERTC_CLOCK_HEXT_DIV_24
+ * - CRM_ERTC_CLOCK_HEXT_DIV_25
+ * - CRM_ERTC_CLOCK_HEXT_DIV_26
+ * - CRM_ERTC_CLOCK_HEXT_DIV_27
+ * - CRM_ERTC_CLOCK_HEXT_DIV_28
+ * - CRM_ERTC_CLOCK_HEXT_DIV_29
+ * - CRM_ERTC_CLOCK_HEXT_DIV_30
+ * - CRM_ERTC_CLOCK_HEXT_DIV_31
+ * @retval none
+ */
+void crm_ertc_clock_select(crm_ertc_clock_type value)
+{
+ CRM->cfg_bit.ertcdiv = ((value & 0x1F0) >> 4);
+ CRM->bpdc_bit.ertcsel = (value & 0xF);
+}
+
+/**
+ * @brief enable or disable ertc
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void crm_ertc_clock_enable(confirm_state new_state)
+{
+ CRM->bpdc_bit.ertcen = new_state;
+}
+
+/**
+ * @brief set crm ahb division
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_AHB_DIV_1
+ * - CRM_AHB_DIV_2
+ * - CRM_AHB_DIV_4
+ * - CRM_AHB_DIV_8
+ * - CRM_AHB_DIV_16
+ * - CRM_AHB_DIV_64
+ * - CRM_AHB_DIV_128
+ * - CRM_AHB_DIV_256
+ * - CRM_AHB_DIV_512
+ * @retval none
+ */
+void crm_ahb_div_set(crm_ahb_div_type value)
+{
+ /* enable auto step mode */
+ crm_auto_step_mode_enable(TRUE);
+
+ CRM->cfg_bit.ahbdiv = value;
+
+ /* disable auto step mode */
+ crm_auto_step_mode_enable(FALSE);
+}
+
+/**
+ * @brief set crm apb1 division
+ * @note the maximum frequency of APB1 clock is 180 MHz
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_APB1_DIV_1
+ * - CRM_APB1_DIV_2
+ * - CRM_APB1_DIV_4
+ * - CRM_APB1_DIV_8
+ * - CRM_APB1_DIV_16
+ * @retval none
+ */
+void crm_apb1_div_set(crm_apb1_div_type value)
+{
+ CRM->cfg_bit.apb1div = value;
+}
+
+/**
+ * @brief set crm apb2 division
+ * @note the maximum frequency of APB2 clock is 180 MHz
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_APB2_DIV_1
+ * - CRM_APB2_DIV_2
+ * - CRM_APB2_DIV_4
+ * - CRM_APB2_DIV_8
+ * - CRM_APB2_DIV_16
+ * @retval none
+ */
+void crm_apb2_div_set(crm_apb2_div_type value)
+{
+ CRM->cfg_bit.apb2div = value;
+}
+
+/**
+ * @brief set crm apb3 division
+ * @note the maximum frequency of APB3 clock is 90 MHz
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_APB3_DIV_1
+ * - CRM_APB3_DIV_2
+ * - CRM_APB3_DIV_4
+ * - CRM_APB3_DIV_8
+ * - CRM_APB3_DIV_16
+ * @retval none
+ */
+void crm_apb3_div_set(crm_apb3_div_type value)
+{
+ CRM->misc2_bit.apb3div = value;
+}
+
+/**
+ * @brief set crm vbat ahb division
+ * @note the maximum frequency of vbat accessing clock is 120 MHz
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_VBATH_DIV_1
+ * - CRM_VBATH_DIV_2
+ * - CRM_VBATH_DIV_4
+ * @retval none
+ */
+void crm_vbath_div_set(crm_vbath_div_type value)
+{
+ CRM->misc2_bit.vbathdiv = value;
+}
+
+/**
+ * @brief set crm lext driving strength
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_DRV_STRENGTH_LOW
+ * - CRM_DRV_STRENGTH_MEDIUM_LOW
+ * - CRM_DRV_STRENGTH_MEDIUM_HIGH
+ * - CRM_DRV_STRENGTH_HIGH
+ * @retval none
+ */
+void crm_lextdrv_set(crm_drv_strength_type value)
+{
+ CRM->bpdc_bit.lextdrv = value;
+}
+
+/**
+ * @brief set crm hext driving strength
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_DRV_STRENGTH_LOW
+ * - CRM_DRV_STRENGTH_MEDIUM_LOW
+ * - CRM_DRV_STRENGTH_MEDIUM_HIGH
+ * - CRM_DRV_STRENGTH_HIGH
+ * @retval none
+ */
+void crm_hextdrv_set(crm_drv_strength_type value)
+{
+ CRM->misc2_bit.hextdrv = value;
+}
+
+/**
+ * @brief set crm hext to sysclk division
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_HEXT_SCLK_DIV_1
+ * - CRM_HEXT_SCLK_DIV_2
+ * - CRM_HEXT_SCLK_DIV_4
+ * - CRM_HEXT_SCLK_DIV_8
+ * - CRM_HEXT_SCLK_DIV_16
+ * - CRM_HEXT_SCLK_DIV_32
+ * @retval none
+ */
+void crm_hext_sclk_div_set(crm_hext_sclk_div_type value)
+{
+ CRM->misc2_bit.hext_to_sclk_div = value;
+}
+
+/**
+ * @brief set crm hick to sysclk division
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_HICK_SCLK_DIV_1
+ * - CRM_HICK_SCLK_DIV_2
+ * - CRM_HICK_SCLK_DIV_4
+ * - CRM_HICK_SCLK_DIV_8
+ * - CRM_HICK_SCLK_DIV_16
+ * @retval none
+ */
+void crm_hick_sclk_div_set(crm_hick_sclk_div_type value)
+{
+ CRM->misc2_bit.hick_to_sclk_div = value;
+}
+
+/**
+ * @brief enable or disable clock failure detection
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void crm_clock_failure_detection_enable(confirm_state new_state)
+{
+ CRM->ctrl_bit.cfden = new_state;
+}
+
+/**
+ * @brief battery powered domain software reset
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void crm_battery_powered_domain_reset(confirm_state new_state)
+{
+ CRM->bpdc_bit.bpdrst = new_state;
+}
+
+/**
+ * @brief auto step clock switch enable
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void crm_auto_step_mode_enable(confirm_state new_state)
+{
+ if(new_state == TRUE)
+ CRM->misc2_bit.auto_step_en = CRM_AUTO_STEP_MODE_ENABLE;
+ else
+ CRM->misc2_bit.auto_step_en = CRM_AUTO_STEP_MODE_DISABLE;
+}
+
+/**
+ * @brief i2sf5 clock source select
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_I2SF5_CLOCK_SOURCE_PLLP
+ * - CRM_I2SF5_CLOCK_SOURCE_HICK
+ * - CRM_I2SF5_CLOCK_SOURCE_SCLK
+ * - CRM_I2SF5_CLOCK_SOURCE_EXTERNAL
+ * @retval none
+ */
+void crm_i2sf5_clock_select(crm_i2sf5_clock_source_type value)
+{
+ CRM->cfg_bit.i2sf5clksel = value;
+}
+
+/**
+ * @brief hick as system clock frequency select
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_HICK_SCLK_8MHZ
+ * - CRM_HICK_SCLK_48MHZ
+ * @retval none
+ */
+void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value)
+{
+ CRM->misc1_bit.hick_to_sclk = value;
+}
+
+/**
+ * @brief usb 48 mhz clock source select
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_USB_CLOCK_SOURCE_PLLU
+ * - CRM_USB_CLOCK_SOURCE_HICK
+ * @retval none
+ */
+void crm_usb_clock_source_select(crm_usb_clock_source_type value)
+{
+ CRM->misc2_bit.pllu_usb48_sel = value;
+}
+
+/**
+ * @brief can multi clock source select
+ * @param can_index
+ * this parameter can be one of the following values:
+ * - CRM_CAN1
+ * - CRM_CAN2
+ * - CRM_CAN3
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_CAN_CLOCK_SOURCE_HEXT
+ * - CRM_CAN_CLOCK_SOURCE_PLLU
+ * - CRM_CAN_CLOCK_SOURCE_PCLK
+ * @retval none
+ */
+void crm_can_clock_select(crm_can_type can_index, crm_can_clock_source_type value)
+{
+ switch(can_index)
+ {
+ case CRM_CAN1:
+ CRM->piclks_bit.can1_clksel = value;
+ break;
+ case CRM_CAN2:
+ CRM->piclks_bit.can2_clksel = value;
+ break;
+ case CRM_CAN3:
+ CRM->piclks_bit.can3_clksel = value;
+ break;
+ }
+}
+
+/**
+ * @brief can multi clock source select
+ * @param can_index
+ * this parameter can be one of the following values:
+ * - CRM_CAN1
+ * - CRM_CAN2
+ * - CRM_CAN3
+ * @retval crm_can_clock_source_type : the clock source of can index.
+ */
+crm_can_clock_source_type crm_can_clock_get(crm_can_type can_index)
+{
+ crm_can_clock_source_type value = CRM_CAN_CLOCK_SOURCE_PCLK;
+
+ switch(can_index)
+ {
+ case CRM_CAN1:
+ value = (crm_can_clock_source_type)CRM->piclks_bit.can1_clksel;
+ break;
+ case CRM_CAN2:
+ value = (crm_can_clock_source_type)CRM->piclks_bit.can2_clksel;
+ break;
+ case CRM_CAN3:
+ value = (crm_can_clock_source_type)CRM->piclks_bit.can3_clksel;
+ break;
+ }
+
+ return value;
+}
+
+/**
+ * @brief config crm pll
+ * pll_rcs_freq * pll_ns
+ * pll clock = --------------------------------
+ * pll_ms * pll_fp_n
+ * attemtion:
+ * 31 <= pll_ns <= 500
+ * 1 <= pll_ms <= 15
+ *
+ * pll_rcs_freq
+ * 2mhz <= ---------------------- <= 16mhz
+ * pll_ms
+ *
+ * pll_rcs_freq * pll_ns
+ * 500mhz <= -------------------------------- <= 1200mhz
+ * pll_ms
+ * @param clock_source
+ * this parameter can be one of the following values:
+ * - CRM_PLL_SOURCE_HICK
+ * - CRM_PLL_SOURCE_HEXT
+ * @param pll_ns (31~500)
+ * @param pll_ms (1~15)
+ * @param pll_fp
+ * this parameter can be one of the following values:
+ * - CRM_PLL_FP_1
+ * - CRM_PLL_FP_2
+ * - CRM_PLL_FP_4
+ * - CRM_PLL_FP_6
+ * - CRM_PLL_FP_8
+ * - CRM_PLL_FP_10
+ * - CRM_PLL_FP_12
+ * - CRM_PLL_FP_14
+ * - CRM_PLL_FP_16
+ * - CRM_PLL_FP_18
+ * - CRM_PLL_FP_20
+ * - CRM_PLL_FP_22
+ * - CRM_PLL_FP_24
+ * - CRM_PLL_FP_26
+ * - CRM_PLL_FP_28
+ * - CRM_PLL_FP_30
+ * @retval none
+ */
+void crm_pll_config(crm_pll_clock_source_type clock_source, uint16_t pll_ns, \
+ uint16_t pll_ms, crm_pll_fp_type pll_fp)
+{
+ /* config pll clock source */
+ CRM->pllcfg_bit.pllrcs = clock_source;
+
+ /* config pll multiplication factor */
+ CRM->pllcfg_bit.pllns = pll_ns;
+ CRM->pllcfg_bit.pllms = pll_ms;
+ CRM->pllcfg_bit.pllfp = pll_fp;
+}
+
+/**
+ * @brief set pllu division when pllu selected as usb clock.
+ * @param pll_fu
+ * this parameter can be one of the following values:
+ * - CRM_PLL_FU_11
+ * - CRM_PLL_FU_12
+ * - CRM_PLL_FU_13
+ * - CRM_PLL_FU_14
+ * - CRM_PLL_FU_16
+ * - CRM_PLL_FU_18
+ * - CRM_PLL_FU_20
+ * @retval none
+ */
+void crm_pllu_div_set(crm_pll_fu_type pll_fu)
+{
+ CRM->pllcfg_bit.pllfu = pll_fu;
+}
+
+/**
+ * @brief config crm pllu output
+ * @param confirm_state
+ * TRUE or FALSE
+ * @retval none
+ */
+void crm_pllu_output_set(confirm_state new_state)
+{
+ /* config pll clock source type output */
+ CRM->pllcfg_bit.plluen = new_state;
+}
+
+/**
+ * @brief select system clock source
+ * @param value
+ * this parameter can be one of the following values:
+ * - CRM_SCLK_HICK
+ * - CRM_SCLK_HEXT
+ * - CRM_SCLK_PLL
+ * @retval none
+ */
+void crm_sysclk_switch(crm_sclk_type value)
+{
+ /* enable auto step mode */
+ crm_auto_step_mode_enable(TRUE);
+
+ CRM->cfg_bit.sclksel = value;
+
+ /* disable auto step mode */
+ crm_auto_step_mode_enable(FALSE);
+}
+
+/**
+ * @brief indicate which clock source is used as system clock
+ * @param none
+ * @retval crm_sclk
+ * this return can be one of the following values:
+ * - CRM_SCLK_HICK
+ * - CRM_SCLK_HEXT
+ * - CRM_SCLK_PLL
+ */
+crm_sclk_type crm_sysclk_switch_status_get(void)
+{
+ return (crm_sclk_type)CRM->cfg_bit.sclksts;
+}
+
+/**
+ * @brief get crm clocks freqency
+ * @param clocks_struct
+ * - pointer to the crm_clocks_freq_type structure
+ * @retval none
+ */
+void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct)
+{
+ uint32_t pll_ns = 0, pll_ms = 0, pll_fp = 0, pll_clock_source = 0, pllrcsfreq = 0;
+ uint32_t temp = 0, div_value = 0, psc = 0;
+ crm_sclk_type sclk_source;
+
+ static const uint8_t sclk_ahb_div_table[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+ static const uint8_t ahb_apb1_div_table[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+ static const uint8_t ahb_apb2_div_table[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+ static const uint8_t pll_fp_table[16] = {1, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30};
+
+ /* get sclk source */
+ sclk_source = crm_sysclk_switch_status_get();
+
+ switch(sclk_source)
+ {
+ case CRM_SCLK_HICK:
+ if((CRM->misc1_bit.hick_to_sclk) != RESET)
+ clocks_struct->sclk_freq = HICK_VALUE * 6;
+ else
+ clocks_struct->sclk_freq = HICK_VALUE;
+
+ psc = CRM->misc2_bit.hick_to_sclk_div;
+ clocks_struct->sclk_freq = clocks_struct->sclk_freq >> psc;
+ break;
+ case CRM_SCLK_HEXT:
+ clocks_struct->sclk_freq = HEXT_VALUE;
+ psc = CRM->misc2_bit.hext_to_sclk_div;
+ clocks_struct->sclk_freq = clocks_struct->sclk_freq >> psc;
+ break;
+ case CRM_SCLK_PLL:
+ /* get pll clock source */
+ pll_clock_source = CRM->pllcfg_bit.pllrcs;
+
+ /* get multiplication factor */
+ pll_ns = CRM->pllcfg_bit.pllns;
+ pll_ms = CRM->pllcfg_bit.pllms;
+ pll_fp = pll_fp_table[CRM->pllcfg_bit.pllfp];
+
+ if (pll_clock_source == CRM_PLL_SOURCE_HICK)
+ {
+ /* hick selected as pll clock entry */
+ pllrcsfreq = HICK_VALUE;
+ }
+ else
+ {
+ /* hext selected as pll clock entry */
+ pllrcsfreq = HEXT_VALUE;
+ }
+
+ clocks_struct->sclk_freq = (uint32_t)(((uint64_t)pllrcsfreq * pll_ns) / (pll_ms * pll_fp));
+ break;
+ default:
+ clocks_struct->sclk_freq = HICK_VALUE;
+ break;
+ }
+
+ /* compute sclk, ahbclk, abp1clk and apb2clk frequencies */
+ /* get ahb division */
+ temp = CRM->cfg_bit.ahbdiv;
+ div_value = sclk_ahb_div_table[temp];
+ /* ahbclk frequency */
+ clocks_struct->ahb_freq = clocks_struct->sclk_freq >> div_value;
+
+ /* get apb1 division */
+ temp = CRM->cfg_bit.apb1div;
+ div_value = ahb_apb1_div_table[temp];
+ /* apb1clk frequency */
+ clocks_struct->apb1_freq = clocks_struct->ahb_freq >> div_value;
+
+ /* get apb2 division */
+ temp = CRM->cfg_bit.apb2div;
+ div_value = ahb_apb2_div_table[temp];
+ /* apb2clk frequency */
+ clocks_struct->apb2_freq = clocks_struct->ahb_freq >> div_value;
+}
+
+/**
+ * @brief set crm clkout
+ * @param clkout
+ * this parameter can be one of the following values:
+ * - CRM_CLKOUT_SCLK
+ * - CRM_CLKOUT_HEXT
+ * - CRM_CLKOUT_PLL
+ * - CRM_CLKOUT_USB
+ * - CRM_CLKOUT_ADC
+ * - CRM_CLKOUT_HICK
+ * - CRM_CLKOUT_LICK
+ * - CRM_CLKOUT_LEXT
+ * @retval none
+ */
+void crm_clock_out_set(crm_clkout_select_type clkout)
+{
+ if(clkout < 0x10)
+ {
+ CRM->cfg_bit.clkout_sel1 = (clkout & 0x3);
+ }
+ else
+ {
+ CRM->cfg_bit.clkout_sel1 = 0x1;
+ CRM->misc1_bit.clkout_sel2 = (clkout & 0xF);
+ }
+}
+
+/**
+ * @brief set crm clkout1 division1
+ * @param div1
+ * this parameter can be one of the following values:
+ * - CRM_CLKOUT_DIV1_1
+ * - CRM_CLKOUT_DIV1_2
+ * - CRM_CLKOUT_DIV1_3
+ * - CRM_CLKOUT_DIV1_4
+ * - CRM_CLKOUT_DIV1_5
+ * @param div2
+ * this parameter can be one of the following values:
+ * - CRM_CLKOUT_DIV2_1
+ * - CRM_CLKOUT_DIV2_2
+ * - CRM_CLKOUT_DIV2_4
+ * - CRM_CLKOUT_DIV2_8
+ * - CRM_CLKOUT_DIV2_16
+ * - CRM_CLKOUT_DIV2_64
+ * - CRM_CLKOUT_DIV2_128
+ * - CRM_CLKOUT_DIV2_256
+ * - CRM_CLKOUT_DIV2_512
+ * @retval none
+ */
+void crm_clkout_div_set(crm_clkout_div1_type div1, crm_clkout_div2_type div2)
+{
+ CRM->cfg_bit.clkoutdiv1 = div1;
+ CRM->misc1_bit.clkoutdiv2 = div2;
+}
+
+/**
+ * @brief set emac output pulse width
+ * @param width
+ * this parameter can be one of the following values:
+ * - CRM_EMAC_PULSE_125MS
+ * - CRM_EMAC_PULSE_1SCLK
+ * @retval none
+ */
+void crm_emac_output_pulse_set(crm_emac_output_pulse_type width)
+{
+ CRM->misc2_bit.emac_pps_sel = width;
+}
+
+/**
+ * @brief config crm interrupt
+ * @param int
+ * this parameter can be any combination of the following values:
+ * - CRM_LICK_STABLE_INT
+ * - CRM_LEXT_STABLE_INT
+ * - CRM_HICK_STABLE_INT
+ * - CRM_HEXT_STABLE_INT
+ * - CRM_PLL_STABLE_INT
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void crm_interrupt_enable(uint32_t crm_int, confirm_state new_state)
+{
+ if(TRUE == new_state)
+ CRM->clkint |= crm_int;
+ else
+ CRM->clkint &= ~crm_int;
+}
+
+/**
+ * @brief calculate the pll parameters with pll reference clock and target pll output frequency.
+ * pll_rcs_freq * pll_ns
+ * pll clock = --------------------------------
+ * pll_ms * pll_fp_n
+ * attemtion:
+ * 31 <= pll_ns <= 500
+ * 1 <= pll_ms <= 15
+ *
+ * pll_rcs_freq
+ * 2mhz <= ---------------------- <= 16mhz
+ * pll_ms
+ *
+ * pll_rcs_freq * pll_ns
+ * 500mhz <= -------------------------------- <= 1200mhz
+ * pll_ms
+ * @param pll_rcs
+ * this parameter can be one of the following values:
+ * - CRM_PLL_SOURCE_HICK
+ * - CRM_PLL_SOURCE_HEXT
+ * @param target_sclk_freq: target pll output frequency, such as 200 mhz (target_sclk_freq: 200000000)
+ * @param ret_ms: pointer to ms value, return the pll_ms of pll parameters
+ * @param ret_ns: pointer to ns value, return the pll_ns of pll parameters
+ * @param ret_fp: pointer to fr value, return the pll_fp of pll parameters
+ * @retval error_status (SUCCESS or ERROR)
+ */
+error_status crm_pll_parameter_calculate(crm_pll_clock_source_type pll_rcs, uint32_t target_sclk_freq, \
+ uint16_t *ret_ms, uint16_t *ret_ns, uint16_t *ret_fp)
+{
+ uint32_t pll_rcs_freq = 0, ns = 0, ms = 0, fp = 0, fp_div = 0;
+ uint32_t ms_min = 0, ms_max = 0, error_min = 0xFFFFFFFF;
+ uint32_t result = 0, absolute_value = 0;
+
+ /* reduce calculate accuracy, target_sclk_freq accuracy with khz */
+ target_sclk_freq = target_sclk_freq / 1000;
+
+ /* get pll reference clock frequency, accuracy with khz */
+ if(pll_rcs == CRM_PLL_SOURCE_HICK)
+ pll_rcs_freq = HICK_VALUE / 1000;
+ else
+ pll_rcs_freq = HEXT_VALUE / 1000;
+
+ /* polling ms range, accuracy with khz */
+ for(ms = 1; ms <= 15; ms ++)
+ {
+ result = pll_rcs_freq / ms;
+ if((result >= 2000U) && (result <= 16000U))
+ {
+ if(ms_min == 0)
+ ms_min = ms;
+
+ ms_max = ms;
+ }
+ }
+
+ /* polling pll parameters */
+ for(ms = ms_min; ms <= ms_max; ms ++)
+ {
+ for(fp = 0; fp <= 15; fp ++)
+ {
+ for(ns = 31; ns <= 500; ns ++)
+ {
+ result = (pll_rcs_freq * ns) / (ms);
+ /* check vco frequency range, accuracy with khz */
+ if((result < 500000U) || (result > 1200000U))
+ {
+ continue;
+ }
+ if(fp == 0)
+ {
+ fp_div = 1;
+ }
+ else
+ {
+ fp_div = 2 * fp;
+ }
+
+ /* calculate pll output frequency */
+ result = result / fp_div;
+ /* check frequency */
+ if(target_sclk_freq == result)
+ {
+ *ret_ms = ms;
+ *ret_ns = ns;
+ *ret_fp = fp;
+ /* the pll parameters that is equal to target_sclk_freq */
+ return SUCCESS;
+ }
+ /* calculate error range, accuracy with khz */
+ absolute_value = (result > target_sclk_freq) ? (result - target_sclk_freq) : (target_sclk_freq - result);
+ if(absolute_value < error_min)
+ {
+ error_min = absolute_value;
+ *ret_ms = ms;
+ *ret_ns = ns;
+ *ret_fp = fp;
+ }
+ }
+ }
+ }
+ /* the pll parameters that is the closest approach to target_sclk_freq */
+ return ERROR;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_dac.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_dac.c
new file mode 100644
index 00000000000..147cc6cce44
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_dac.c
@@ -0,0 +1,480 @@
+/**
+ **************************************************************************
+ * @file at32f45x_dac.c
+ * @brief contains all the functions for the dac firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup DAC
+ * @brief DAC driver modules
+ * @{
+ */
+
+#ifdef DAC_MODULE_ENABLED
+
+/** @defgroup DAC_private_functions
+ * @{
+ */
+
+/**
+ * @brief dac reset
+ * @param none
+ * @retval none
+ */
+void dac_reset(void)
+{
+ crm_periph_reset(CRM_DAC_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_DAC_PERIPH_RESET, FALSE);
+}
+
+/**
+ * @brief enable or disable dac
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void dac_enable(dac_select_type dac_select, confirm_state new_state)
+{
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ DAC->ctrl_bit.d1en = new_state;
+ break;
+ case DAC2_SELECT:
+ DAC->ctrl_bit.d2en = new_state;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief enable or disable dac output buffer
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void dac_output_buffer_enable(dac_select_type dac_select, confirm_state new_state)
+{
+ new_state = (confirm_state)!new_state;
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ DAC->ctrl_bit.d1obdis = new_state;
+ break;
+ case DAC2_SELECT:
+ DAC->ctrl_bit.d2obdis = new_state;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief enable or disable dac trigger
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void dac_trigger_enable(dac_select_type dac_select, confirm_state new_state)
+{
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ DAC->ctrl_bit.d1trgen = new_state;
+ break;
+ case DAC2_SELECT:
+ DAC->ctrl_bit.d2trgen = new_state;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief select dac trigger
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @param dac_trigger_source
+ * this parameter can be one of the following values:
+ * - DAC_TMR6_TRGOUT_EVENT
+ * - DAC_TMR8_TRGOUT_EVENT
+ * - DAC_TMR7_TRGOUT_EVENT
+ * - DAC_TMR5_TRGOUT_EVENT
+ * - DAC_TMR2_TRGOUT_EVENT
+ * - DAC_TMR4_TRGOUT_EVENT
+ * - DAC_EXTERNAL_INTERRUPT_LINE_9
+ * - DAC_SOFTWARE_TRIGGER
+ * @retval none
+ */
+void dac_trigger_select(dac_select_type dac_select, dac_trigger_type dac_trigger_source)
+{
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ DAC->ctrl_bit.d1trgsel = dac_trigger_source;
+ break;
+ case DAC2_SELECT:
+ DAC->ctrl_bit.d2trgsel = dac_trigger_source;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief generate dac software trigger
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @retval none
+ */
+void dac_software_trigger_generate(dac_select_type dac_select)
+{
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ DAC->swtrg_bit.d1swtrg = TRUE;
+ break;
+ case DAC2_SELECT:
+ DAC->swtrg_bit.d2swtrg = TRUE;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief generate dac dual software trigger synchronously
+ * @param none
+ * @retval none
+ */
+void dac_dual_software_trigger_generate(void)
+{
+ DAC->swtrg |= 0x03;
+}
+
+/**
+ * @brief generate dac wave
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @param dac_wave
+ * this parameter can be one of the following values:
+ * - DAC_WAVE_GENERATE_NONE
+ * - DAC_WAVE_GENERATE_NOISE
+ * - DAC_WAVE_GENERATE_TRIANGLE
+ * @retval none
+ */
+void dac_wave_generate(dac_select_type dac_select, dac_wave_type dac_wave)
+{
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ DAC->ctrl_bit.d1nm = dac_wave;
+ break;
+ case DAC2_SELECT:
+ DAC->ctrl_bit.d2nm = dac_wave;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief select dac mask amplitude
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @param dac_mask_amplitude
+ * this parameter can be one of the following values:
+ * - DAC_LSFR_BIT0_AMPLITUDE_1
+ * - DAC_LSFR_BIT10_AMPLITUDE_3
+ * - DAC_LSFR_BIT20_AMPLITUDE_7
+ * - DAC_LSFR_BIT30_AMPLITUDE_15
+ * - DAC_LSFR_BIT40_AMPLITUDE_31
+ * - DAC_LSFR_BIT50_AMPLITUDE_63
+ * - DAC_LSFR_BIT60_AMPLITUDE_127
+ * - DAC_LSFR_BIT70_AMPLITUDE_255
+ * - DAC_LSFR_BIT80_AMPLITUDE_511
+ * - DAC_LSFR_BIT90_AMPLITUDE_1023
+ * - DAC_LSFR_BITA0_AMPLITUDE_2047
+ * - DAC_LSFR_BITB0_AMPLITUDE_4095
+ * @retval none
+ */
+void dac_mask_amplitude_select(dac_select_type dac_select, dac_mask_amplitude_type dac_mask_amplitude)
+{
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ DAC->ctrl_bit.d1nbsel = dac_mask_amplitude;
+ break;
+ case DAC2_SELECT:
+ DAC->ctrl_bit.d2nbsel = dac_mask_amplitude;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief enable or disable dac dma
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void dac_dma_enable(dac_select_type dac_select, confirm_state new_state)
+{
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ DAC->ctrl_bit.d1dmaen = new_state;
+ break;
+ case DAC2_SELECT:
+ DAC->ctrl_bit.d2dmaen = new_state;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief get dac data output
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @retval dac channel data output
+ */
+uint16_t dac_data_output_get(dac_select_type dac_select)
+{
+ uint16_t data_output =0;
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ data_output = DAC->d1odt_bit.d1odt;
+ break;
+ case DAC2_SELECT:
+ data_output = DAC->d2odt_bit.d2odt;
+ break;
+ default:
+ break;
+ }
+ return data_output;
+}
+
+/**
+ * @brief set dac1 data
+ * @param dac1_aligned
+ * this parameter can be one of the following values:
+ * DAC1_12BIT_RIGHT
+ * DAC1_12BIT_LEFT
+ * DAC1_8BIT_RIGHT
+ * @param dac1_data :indecate from selected data holding register
+ * @retval none
+ */
+void dac_1_data_set(dac1_aligned_data_type dac1_aligned, uint16_t dac1_data)
+{
+ *(__IO uint32_t *) dac1_aligned = dac1_data;
+}
+
+/**
+ * @brief set dac2 data
+ * @param dac2_aligned
+ * this parameter can be one of the following values:
+ * DAC2_12BIT_RIGHT
+ * DAC2_12BIT_LEFT
+ * DAC2_8BIT_RIGHT
+ * @param dac2_data :indecate from selected data holding register
+ * @retval none
+ */
+void dac_2_data_set(dac2_aligned_data_type dac2_aligned, uint16_t dac2_data)
+{
+ *(__IO uint32_t *) dac2_aligned = dac2_data;
+}
+
+/**
+ * @brief set dac dual data
+ * @param dac_dual
+ * this parameter can be one of the following values:
+ * DAC_DUAL_12BIT_RIGHT
+ * DAC_DUAL_12BIT_LEFT
+ * DAC_DUAL_8BIT_RIGHT
+ * @param data1 :dac1 channel indecate from selected data holding register
+ * @param data2 :dac1 channel indecate from selected data holding register
+ * @retval none
+ */
+void dac_dual_data_set(dac_dual_data_type dac_dual, uint16_t data1, uint16_t data2)
+{
+ switch(dac_dual)
+ {
+ case DAC_DUAL_12BIT_RIGHT:
+ *(__IO uint32_t *) dac_dual = (uint32_t)(data1 | (data2 << 16));
+ break;
+ case DAC_DUAL_12BIT_LEFT:
+ *(__IO uint32_t *) dac_dual = (uint32_t)(data1 | (data2 << 16));
+ break;
+ case DAC_DUAL_8BIT_RIGHT:
+ *(__IO uint32_t *) dac_dual = (uint32_t)(data1 | (data2 << 8));
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief enable/disable dac dma udr interrupt
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void dac_udr_enable(dac_select_type dac_select, confirm_state new_state)
+{
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ DAC->ctrl_bit.d1dmaudrien = new_state;
+ break;
+ case DAC2_SELECT:
+ DAC->ctrl_bit.d2dmaudrien = new_state;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief get flag of the dac udr flag.
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @retval the new state of dac udr flag status(SET or RESET).
+ */
+flag_status dac_udr_flag_get(dac_select_type dac_select)
+{
+ flag_status status = RESET;
+
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ if(DAC->sts_bit.d1dmaudrf != 0)
+ status = SET;
+ break;
+ case DAC2_SELECT:
+ if(DAC->sts_bit.d2dmaudrf != 0)
+ status = SET;
+ break;
+ default:
+ break;
+ }
+ return status;
+}
+
+/**
+ * @brief get flag of the dac udr interrupt flag.
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @retval the new state of dac udr flag status(SET or RESET).
+ */
+flag_status dac_udr_interrupt_flag_get(dac_select_type dac_select)
+{
+ flag_status status = RESET;
+
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ if((DAC->sts_bit.d1dmaudrf && DAC->ctrl_bit.d1dmaudrien) != 0)
+ status = SET;
+ break;
+ case DAC2_SELECT:
+ if((DAC->sts_bit.d2dmaudrf && DAC->ctrl_bit.d2dmaudrien) != 0)
+ status = SET;
+ break;
+ default:
+ break;
+ }
+ return status;
+}
+
+/**
+ * @brief clear the dac udr flag.
+ * @param dac_select
+ * this parameter can be one of the following values:
+ * - DAC1_SELECT
+ * - DAC2_SELECT
+ * @retval none
+ */
+void dac_udr_flag_clear(dac_select_type dac_select)
+{
+ switch(dac_select)
+ {
+ case DAC1_SELECT:
+ DAC->sts = DAC1_D1DMAUDRF;
+ break;
+ case DAC2_SELECT:
+ DAC->sts = DAC2_D2DMAUDRF;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_debug.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_debug.c
new file mode 100644
index 00000000000..86285b74920
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_debug.c
@@ -0,0 +1,150 @@
+/**
+ **************************************************************************
+ * @file at32f45x_mcudbg.c
+ * @brief contains all the functions for the mcudbg firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup DEBUG
+ * @brief DEBUG driver modules
+ * @{
+ */
+
+#ifdef DEBUG_MODULE_ENABLED
+
+/** @defgroup DEBUG_private_functions
+ * @{
+ */
+
+/**
+ * @brief get debug device id
+ * @param none
+ * @retval the debug device id
+ */
+uint32_t debug_device_id_get(void)
+{
+ return DEBUGMCU->pid;
+}
+/**
+ * @brief set periph debug mode
+ * @param periph_debug_mode
+ * this parameter can be one of the following values:
+ * - DEBUG_SLEEP
+ * - DEBUG_DEEPSLEEP
+ * - DEBUG_STANDBY
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void debug_low_power_mode_set(uint32_t low_power_mode, confirm_state new_state)
+{
+ if(new_state != FALSE)
+ {
+ DEBUGMCU->ctrl |= low_power_mode;
+ }
+ else
+ {
+ DEBUGMCU->ctrl &= ~low_power_mode;
+ }
+}
+/**
+ * @brief set apb1 periph debug mode
+ * @param periph_debug_mode
+ * this parameter can be any combination of the following values:
+ * - DEBUG_TMR3_PAUSE - DEBUG_TMR4_PAUSE
+ * - DEBUG_TMR2_PAUSE - DEBUG_TMR5_PAUSE
+ * - DEBUG_TMR6_PAUSE - DEBUG_TMR7_PAUSE
+ * - DEBUG_TMR12_PAUSE - DEBUG_TMR13_PAUSE
+ * - DEBUG_TMR14_PAUSE - DEBUG_WDT_PAUSE
+ * - DEBUG_I2C1_SMBUS_TIMEOUT - DEBUG_I2C2_SMBUS_TIMEOUT
+ * - DEBUG_I2C3_SMBUS_TIMEOUT
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void debug_apb1_periph_mode_set(uint32_t apb1_periph, confirm_state new_state)
+{
+ if(new_state != FALSE)
+ {
+ DEBUGMCU->apb1_frz |= apb1_periph;
+ }
+ else
+ {
+ DEBUGMCU->apb1_frz &= ~apb1_periph;
+ }
+}
+/**
+ * @brief set apb2 periph debug mode
+ * @param periph_debug_mode
+ * this parameter can be any combination of the following values:
+ * - DEBUG_TMR1_PAUSE - DEBUG_TMR9_PAUSE
+ * - DEBUG_TMR10_PAUSE - DEBUG_TMR11_PAUSE
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void debug_apb2_periph_mode_set(uint32_t apb2_periph, confirm_state new_state)
+{
+ if(new_state != FALSE)
+ {
+ DEBUGMCU->apb2_frz |= apb2_periph;
+ }
+ else
+ {
+ DEBUGMCU->apb2_frz &= ~apb2_periph;
+ }
+}
+
+/**
+ * @brief set apb3 periph debug mode
+ * @param periph_debug_mode
+ * this parameter can be any combination of the following values:
+ * - DEBUG_ERTC_PAUSE
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void debug_apb3_periph_mode_set(uint32_t apb3_periph, confirm_state new_state)
+{
+ if(new_state != FALSE)
+ {
+ DEBUGMCU->apb3_frz |= apb3_periph;
+ }
+ else
+ {
+ DEBUGMCU->apb3_frz &= ~apb3_periph;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_dma.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_dma.c
new file mode 100644
index 00000000000..ea760a05d36
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_dma.c
@@ -0,0 +1,865 @@
+/**
+ **************************************************************************
+ * @file at32f45x_dma.c
+ * @brief contains all the functions for the dma firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup DMA
+ * @brief DMA driver modules
+ * @{
+ */
+
+#ifdef DMA_MODULE_ENABLED
+
+/** @defgroup DMA_private_functions
+ * @{
+ */
+
+/**
+ * @brief reset dmax channely register.
+ * @param dmax_channely:
+ * this parameter can be one of the following values:
+ * - DMA1_CHANNEL1
+ * - DMA1_CHANNEL2
+ * - DMA1_CHANNEL3
+ * - DMA1_CHANNEL4
+ * - DMA1_CHANNEL5
+ * - DMA1_CHANNEL6
+ * - DMA1_CHANNEL7
+ * - DMA2_CHANNEL1
+ * - DMA2_CHANNEL2
+ * - DMA2_CHANNEL3
+ * - DMA2_CHANNEL4
+ * - DMA2_CHANNEL5
+ * - DMA2_CHANNEL6
+ * - DMA2_CHANNEL7
+ * @retval none.
+ */
+void dma_reset(dma_channel_type *dmax_channely)
+{
+ uint32_t temp = 0;
+ dmax_channely->ctrl_bit.chen = FALSE;
+ dmax_channely->ctrl = 0;
+ dmax_channely->dtcnt = 0;
+ dmax_channely->paddr = 0;
+ dmax_channely->maddr = 0;
+
+ temp = (uint32_t)dmax_channely;
+
+ if((temp & 0x6FF) < 0x608)
+ {
+ /* dma1 channel */
+ DMA1->clr |= (uint32_t)(0x0F << ((((temp & 0xFF) - 0x08) / 0x14) * 4));
+ }
+ else if((temp & 0x6FF) < 0x688)
+ {
+ /* dma2 channel */
+ DMA2->clr |= (uint32_t)(0x0F << ((((temp & 0xFF) - 0x08) / 0x14) * 4));
+ }
+}
+
+/**
+ * @brief set the number of data to be transferred.
+ * @param dmax_channely:
+ * this parameter can be one of the following values:
+ * - DMA1_CHANNEL1
+ * - DMA1_CHANNEL2
+ * - DMA1_CHANNEL3
+ * - DMA1_CHANNEL4
+ * - DMA1_CHANNEL5
+ * - DMA1_CHANNEL6
+ * - DMA1_CHANNEL7
+ * - DMA2_CHANNEL1
+ * - DMA2_CHANNEL2
+ * - DMA2_CHANNEL3
+ * - DMA2_CHANNEL4
+ * - DMA2_CHANNEL5
+ * - DMA2_CHANNEL6
+ * - DMA2_CHANNEL7
+ * @param data_number: the number of data to be transferred (0x0000~0xFFFF).
+ * @retval none.
+ */
+void dma_data_number_set(dma_channel_type *dmax_channely, uint16_t data_number)
+{
+ dmax_channely->dtcnt = data_number;
+}
+
+/**
+ * @brief get the number of data to be transferred.
+ * @param dmax_channely:
+ * this parameter can be one of the following values:
+ * - DMA1_CHANNEL1
+ * - DMA1_CHANNEL2
+ * - DMA1_CHANNEL3
+ * - DMA1_CHANNEL4
+ * - DMA1_CHANNEL5
+ * - DMA1_CHANNEL6
+ * - DMA1_CHANNEL7
+ * - DMA2_CHANNEL1
+ * - DMA2_CHANNEL2
+ * - DMA2_CHANNEL3
+ * - DMA2_CHANNEL4
+ * - DMA2_CHANNEL5
+ * - DMA2_CHANNEL6
+ * - DMA2_CHANNEL7
+ * @retval the number value.
+ */
+uint16_t dma_data_number_get(dma_channel_type *dmax_channely)
+{
+ return (uint16_t)dmax_channely->dtcnt;
+}
+
+/**
+ * @brief enable or disable dma interrupt.
+ * @param dmax_channely:
+ * this parameter can be one of the following values:
+ * - DMA1_CHANNEL1
+ * - DMA1_CHANNEL2
+ * - DMA1_CHANNEL3
+ * - DMA1_CHANNEL4
+ * - DMA1_CHANNEL5
+ * - DMA1_CHANNEL6
+ * - DMA1_CHANNEL7
+ * - DMA2_CHANNEL1
+ * - DMA2_CHANNEL2
+ * - DMA2_CHANNEL3
+ * - DMA2_CHANNEL4
+ * - DMA2_CHANNEL5
+ * - DMA2_CHANNEL6
+ * - DMA2_CHANNEL7
+ * @param dma_int:
+ * this parameter can be any combination of the following values:
+ * - DMA_FDT_INT
+ * - DMA_HDT_INT
+ * - DMA_DTERR_INT
+ * @param new_state (TRUE or FALSE)
+ * @retval none.
+ */
+void dma_interrupt_enable(dma_channel_type *dmax_channely, uint32_t dma_int, confirm_state new_state)
+{
+ if(new_state != FALSE)
+ {
+ dmax_channely->ctrl |= dma_int;
+ }
+ else
+ {
+ dmax_channely->ctrl &= ~dma_int;
+ }
+}
+
+/**
+ * @brief enable or disable dma channel.
+ * @param dmax_channely:
+ * this parameter can be one of the following values:
+ * - DMA1_CHANNEL1
+ * - DMA1_CHANNEL2
+ * - DMA1_CHANNEL3
+ * - DMA1_CHANNEL4
+ * - DMA1_CHANNEL5
+ * - DMA1_CHANNEL6
+ * - DMA1_CHANNEL7
+ * - DMA2_CHANNEL1
+ * - DMA2_CHANNEL2
+ * - DMA2_CHANNEL3
+ * - DMA2_CHANNEL4
+ * - DMA2_CHANNEL5
+ * - DMA2_CHANNEL6
+ * - DMA2_CHANNEL7
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void dma_channel_enable(dma_channel_type *dmax_channely, confirm_state new_state)
+{
+ dmax_channely->ctrl_bit.chen = new_state;
+}
+
+/**
+ * @brief dma flag get.
+ * @param dma_flag
+ * - DMA1_GL1_FLAG - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
+ * - DMA1_GL2_FLAG - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
+ * - DMA1_GL3_FLAG - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
+ * - DMA1_GL4_FLAG - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
+ * - DMA1_GL5_FLAG - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
+ * - DMA1_GL6_FLAG - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG
+ * - DMA1_GL7_FLAG - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG
+ * - DMA2_GL1_FLAG - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG
+ * - DMA2_GL2_FLAG - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG
+ * - DMA2_GL3_FLAG - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG
+ * - DMA2_GL4_FLAG - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG
+ * - DMA2_GL5_FLAG - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG
+ * - DMA2_GL6_FLAG - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG
+ * - DMA2_GL7_FLAG - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG
+ * @retval state of dma flag.
+ */
+flag_status dma_flag_get(uint32_t dmax_flag)
+{
+ uint32_t temp = 0;
+
+ if(dmax_flag > 0x10000000)
+ {
+ temp = DMA2->sts;
+ }
+ else
+ {
+ temp = DMA1->sts;
+ }
+
+ if((temp & dmax_flag) != RESET)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief dma interrupt flag get.
+ * @param dma_flag
+ * - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
+ * - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
+ * - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
+ * - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
+ * - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
+ * - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG
+ * - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG
+ * - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG
+ * - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG
+ * - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG
+ * - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG
+ * - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG
+ * - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG
+ * - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG
+ * @retval state of dma flag.
+ */
+flag_status dma_interrupt_flag_get(uint32_t dmax_flag)
+{
+ uint32_t temp = 0;
+
+ if(dmax_flag > 0x10000000)
+ {
+ temp = DMA2->sts;
+ }
+ else
+ {
+ temp = DMA1->sts;
+ }
+
+ if((temp & dmax_flag) != RESET)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief dma flag clear.
+ * @param dma_flag
+ * this parameter can be one of the following values:
+ * - DMA1_GL1_FLAG - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
+ * - DMA1_GL2_FLAG - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
+ * - DMA1_GL3_FLAG - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
+ * - DMA1_GL4_FLAG - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
+ * - DMA1_GL5_FLAG - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
+ * - DMA1_GL6_FLAG - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG
+ * - DMA1_GL7_FLAG - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG
+ * - DMA2_GL1_FLAG - DMA2_FDT1_FLAG - DMA2_HDT1_FLAG - DMA2_DTERR1_FLAG
+ * - DMA2_GL2_FLAG - DMA2_FDT2_FLAG - DMA2_HDT2_FLAG - DMA2_DTERR2_FLAG
+ * - DMA2_GL3_FLAG - DMA2_FDT3_FLAG - DMA2_HDT3_FLAG - DMA2_DTERR3_FLAG
+ * - DMA2_GL4_FLAG - DMA2_FDT4_FLAG - DMA2_HDT4_FLAG - DMA2_DTERR4_FLAG
+ * - DMA2_GL5_FLAG - DMA2_FDT5_FLAG - DMA2_HDT5_FLAG - DMA2_DTERR5_FLAG
+ * - DMA2_GL6_FLAG - DMA2_FDT6_FLAG - DMA2_HDT6_FLAG - DMA2_DTERR6_FLAG
+ * - DMA2_GL7_FLAG - DMA2_FDT7_FLAG - DMA2_HDT7_FLAG - DMA2_DTERR7_FLAG
+ * @retval none.
+ */
+void dma_flag_clear(uint32_t dmax_flag)
+{
+ if(dmax_flag > ((uint32_t)0x10000000))
+ {
+ DMA2->clr = (uint32_t)(dmax_flag & 0x0FFFFFFF);
+ }
+ else
+ {
+ DMA1->clr = dmax_flag;
+ }
+}
+
+/**
+ * @brief dma init config with its default value.
+ * @param dma_init_struct: pointer to a dma_init_type structure which will be initialized.
+ * @retval none.
+ */
+void dma_default_para_init(dma_init_type *dma_init_struct)
+{
+ dma_init_struct->peripheral_base_addr = 0;
+ dma_init_struct->memory_base_addr = 0;
+ dma_init_struct->direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
+ dma_init_struct->buffer_size = 0;
+ dma_init_struct->peripheral_inc_enable = FALSE;
+ dma_init_struct->memory_inc_enable = FALSE;
+ dma_init_struct->peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
+ dma_init_struct->memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
+ dma_init_struct->loop_mode_enable = FALSE;
+ dma_init_struct->priority = DMA_PRIORITY_LOW;
+}
+
+/**
+ * @brief dma init.
+ * @param dmax_channely:
+ * this parameter can be one of the following values:
+ * - DMA1_CHANNEL1
+ * - DMA1_CHANNEL2
+ * - DMA1_CHANNEL3
+ * - DMA1_CHANNEL4
+ * - DMA1_CHANNEL5
+ * - DMA1_CHANNEL6
+ * - DMA1_CHANNEL7
+ * - DMA2_CHANNEL1
+ * - DMA2_CHANNEL2
+ * - DMA2_CHANNEL3
+ * - DMA2_CHANNEL4
+ * - DMA2_CHANNEL5
+ * - DMA2_CHANNEL6
+ * - DMA2_CHANNEL7
+ * @param dma_init_struct: pointer to a dma_init_type structure.
+ * @retval none.
+ */
+void dma_init(dma_channel_type *dmax_channely, dma_init_type *dma_init_struct)
+{
+ /* clear ctrl register dtd bit and m2m bit */
+ dmax_channely->ctrl &= 0xbfef;
+ dmax_channely->ctrl |= dma_init_struct->direction;
+
+ dmax_channely->ctrl_bit.chpl = dma_init_struct->priority;
+ dmax_channely->ctrl_bit.mwidth = dma_init_struct->memory_data_width;
+ dmax_channely->ctrl_bit.pwidth = dma_init_struct->peripheral_data_width;
+ dmax_channely->ctrl_bit.mincm = dma_init_struct->memory_inc_enable;
+ dmax_channely->ctrl_bit.pincm = dma_init_struct->peripheral_inc_enable;
+ dmax_channely->ctrl_bit.lm = dma_init_struct->loop_mode_enable;
+ dmax_channely->dtcnt_bit.cnt = dma_init_struct->buffer_size;
+ dmax_channely->paddr = dma_init_struct->peripheral_base_addr;
+ dmax_channely->maddr = dma_init_struct->memory_base_addr;
+}
+/**
+ * @brief dmamux init.
+ * @param dma_x: pointer to a dma_type structure, can be DMA1 or DMA2.
+ * @param dmamux_channelx:
+ * this parameter can be one of the following values:
+ * - DMA1MUX_CHANNEL1
+ * - DMA1MUX_CHANNEL2
+ * - DMA1MUX_CHANNEL3
+ * - DMA1MUX_CHANNEL4
+ * - DMA1MUX_CHANNEL5
+ * - DMA1MUX_CHANNEL6
+ * - DMA1MUX_CHANNEL7
+ * - DMA2MUX_CHANNEL1
+ * - DMA2MUX_CHANNEL2
+ * - DMA2MUX_CHANNEL3
+ * - DMA2MUX_CHANNEL4
+ * - DMA2MUX_CHANNEL5
+ * - DMA2MUX_CHANNEL6
+ * - DMA2MUX_CHANNEL7
+ * @param dmamux_req_sel:
+ * this parameter can be one of the following values:
+ * - DMAMUX_DMAREQ_ID_REQ_G1 - DMAMUX_DMAREQ_ID_REQ_G2 - DMAMUX_DMAREQ_ID_REQ_G3 - DMAMUX_DMAREQ_ID_REQ_G4
+ * - DMAMUX_DMAREQ_ID_ADC1 - DMAMUX_DMAREQ_ID_ADC2 - DMAMUX_DMAREQ_ID_DAC1 - DMAMUX_DMAREQ_ID_DAC2
+ * - DMAMUX_DMAREQ_ID_TMR6_OVERFLOW - DMAMUX_DMAREQ_ID_TMR7_OVERFLOW - DMAMUX_DMAREQ_ID_SPI1_RX - DMAMUX_DMAREQ_ID_SPI1_TX
+ * - DMAMUX_DMAREQ_ID_SPI2_RX - DMAMUX_DMAREQ_ID_SPI2_TX - DMAMUX_DMAREQ_ID_SPI3_RX - DMAMUX_DMAREQ_ID_SPI3_TX
+ * - DMAMUX_DMAREQ_ID_SPI4_RX - DMAMUX_DMAREQ_ID_SPI4_TX - DMAMUX_DMAREQ_ID_I2S2_EXT_RX - DMAMUX_DMAREQ_ID_I2S2_EXT_TX
+ * - DMAMUX_DMAREQ_ID_I2S3_EXT_RX - DMAMUX_DMAREQ_ID_I2S3_EXT_TX - DMAMUX_DMAREQ_ID_I2S5_RX - DMAMUX_DMAREQ_ID_I2S5_TX
+ * - DMAMUX_DMAREQ_ID_I2C1_RX - DMAMUX_DMAREQ_ID_I2C1_TX - DMAMUX_DMAREQ_ID_I2C2_RX - DMAMUX_DMAREQ_ID_I2C2_TX
+ * - DMAMUX_DMAREQ_ID_I2C3_RX - DMAMUX_DMAREQ_ID_I2C3_TX - DMAMUX_DMAREQ_ID_USART1_RX - DMAMUX_DMAREQ_ID_USART1_TX
+ * - DMAMUX_DMAREQ_ID_USART2_RX - DMAMUX_DMAREQ_ID_USART2_TX - DMAMUX_DMAREQ_ID_USART3_RX - DMAMUX_DMAREQ_ID_USART3_TX
+ * - DMAMUX_DMAREQ_ID_USART4_RX - DMAMUX_DMAREQ_ID_USART4_TX - DMAMUX_DMAREQ_ID_USART5_RX - DMAMUX_DMAREQ_ID_USART5_TX
+ * - DMAMUX_DMAREQ_ID_USART6_RX - DMAMUX_DMAREQ_ID_USART6_TX - DMAMUX_DMAREQ_ID_USART7_RX - DMAMUX_DMAREQ_ID_USART7_TX
+ * - DMAMUX_DMAREQ_ID_USART8_RX - DMAMUX_DMAREQ_ID_USART8_TX - DMAMUX_DMAREQ_ID_SDIO1 - DMAMUX_DMAREQ_ID_QSPI1
+ * - DMAMUX_DMAREQ_ID_TMR1_CH1 - DMAMUX_DMAREQ_ID_TMR1_CH2 - DMAMUX_DMAREQ_ID_TMR1_CH3 - DMAMUX_DMAREQ_ID_TMR1_CH4
+ * - DMAMUX_DMAREQ_ID_TMR1_OVERFLOW - DMAMUX_DMAREQ_ID_TMR1_TRIG - DMAMUX_DMAREQ_ID_TMR1_HALL - DMAMUX_DMAREQ_ID_TMR8_CH1
+ * - DMAMUX_DMAREQ_ID_TMR8_CH2 - DMAMUX_DMAREQ_ID_TMR8_CH3 - DMAMUX_DMAREQ_ID_TMR8_CH4 - DMAMUX_DMAREQ_ID_TMR8_OVERFLOW
+ * - DMAMUX_DMAREQ_ID_TMR8_TRIG - DMAMUX_DMAREQ_ID_TMR8_HALL - DMAMUX_DMAREQ_ID_TMR2_CH1 - DMAMUX_DMAREQ_ID_TMR2_CH2
+ * - DMAMUX_DMAREQ_ID_TMR2_CH3 - DMAMUX_DMAREQ_ID_TMR2_CH4 - DMAMUX_DMAREQ_ID_TMR2_OVERFLOW - DMAMUX_DMAREQ_ID_TMR2_TRIG
+ * - DMAMUX_DMAREQ_ID_TMR3_CH1 - DMAMUX_DMAREQ_ID_TMR3_CH2 - DMAMUX_DMAREQ_ID_TMR3_CH3 - DMAMUX_DMAREQ_ID_TMR3_CH4
+ * - DMAMUX_DMAREQ_ID_TMR3_OVERFLOW - DMAMUX_DMAREQ_ID_TMR3_TRIG - DMAMUX_DMAREQ_ID_TMR4_CH1 - DMAMUX_DMAREQ_ID_TMR4_CH2
+ * - DMAMUX_DMAREQ_ID_TMR4_CH3 - DMAMUX_DMAREQ_ID_TMR4_CH4 - DMAMUX_DMAREQ_ID_TMR4_OVERFLOW - DMAMUX_DMAREQ_ID_TMR4_TRIG
+ * - DMAMUX_DMAREQ_ID_TMR5_CH1 - DMAMUX_DMAREQ_ID_TMR5_CH2 - DMAMUX_DMAREQ_ID_TMR5_CH3 - DMAMUX_DMAREQ_ID_TMR5_CH4
+ * - DMAMUX_DMAREQ_ID_TMR5_OVERFLOW - DMAMUX_DMAREQ_ID_TMR5_TRIG - DMAMUX_DMAREQ_ID_TMR9_CH1 - DMAMUX_DMAREQ_ID_TMR9_CH2
+ * - DMAMUX_DMAREQ_ID_TMR9_OVERFLOW - DMAMUX_DMAREQ_ID_TMR9_TRIG - DMAMUX_DMAREQ_ID_TMR9_HALL - DMAMUX_DMAREQ_ID_TMR10_CH1
+ * - DMAMUX_DMAREQ_ID_TMR10_OVERFLOW- DMAMUX_DMAREQ_ID_TMR11_CH1 - DMAMUX_DMAREQ_ID_TMR11_OVERFLOW- DMAMUX_DMAREQ_ID_TMR12_CH1
+ * - DMAMUX_DMAREQ_ID_TMR12_CH2 - DMAMUX_DMAREQ_ID_TMR12_OVERFLOW- DMAMUX_DMAREQ_ID_TMR12_TRIG - DMAMUX_DMAREQ_ID_TMR12_HALL
+ * - DMAMUX_DMAREQ_ID_TMR13_CH1 - DMAMUX_DMAREQ_ID_TMR13_OVERFLOW- DMAMUX_DMAREQ_ID_TMR14_CH1 - DMAMUX_DMAREQ_ID_TMR14_OVERFLOW
+ * - DMAMUX_DMAREQ_ID_AES_IN - DMAMUX_DMAREQ_ID_AES_OUT
+ * @retval none.
+ */
+void dma_flexible_config(dma_type* dma_x, dmamux_channel_type *dmamux_channelx, dmamux_requst_id_sel_type dmamux_req_sel)
+{
+ dma_x->muxsel_bit.tblsel = TRUE;
+ dmamux_channelx->muxctrl_bit.reqsel = dmamux_req_sel;
+}
+
+/**
+ * @brief enable or disable the dmamux.
+ * @param dma_x: pointer to a dma_type structure, can be DMA1 or DMA2.
+ * @param new_state (TRUE or FALSE) .
+ * @retval none.
+ */
+void dmamux_enable(dma_type *dma_x, confirm_state new_state)
+{
+ dma_x->muxsel_bit.tblsel = new_state;
+}
+
+/**
+ * @brief dmamux init.
+ * @param dmamux_channelx:
+ * this parameter can be one of the following values:
+ * - DMA1MUX_CHANNEL1
+ * - DMA1MUX_CHANNEL2
+ * - DMA1MUX_CHANNEL3
+ * - DMA1MUX_CHANNEL4
+ * - DMA1MUX_CHANNEL5
+ * - DMA1MUX_CHANNEL6
+ * - DMA1MUX_CHANNEL7
+ * - DMA2MUX_CHANNEL1
+ * - DMA2MUX_CHANNEL2
+ * - DMA2MUX_CHANNEL3
+ * - DMA2MUX_CHANNEL4
+ * - DMA2MUX_CHANNEL5
+ * - DMA2MUX_CHANNEL6
+ * - DMA2MUX_CHANNEL7
+ * @param dmamux_req_sel:
+ * this parameter can be one of the following values:
+ * - DMAMUX_DMAREQ_ID_REQ_G1 - DMAMUX_DMAREQ_ID_REQ_G2 - DMAMUX_DMAREQ_ID_REQ_G3 - DMAMUX_DMAREQ_ID_REQ_G4
+ * - DMAMUX_DMAREQ_ID_ADC1 - DMAMUX_DMAREQ_ID_ADC2 - DMAMUX_DMAREQ_ID_DAC1 - DMAMUX_DMAREQ_ID_DAC2
+ * - DMAMUX_DMAREQ_ID_TMR6_OVERFLOW - DMAMUX_DMAREQ_ID_TMR7_OVERFLOW - DMAMUX_DMAREQ_ID_SPI1_RX - DMAMUX_DMAREQ_ID_SPI1_TX
+ * - DMAMUX_DMAREQ_ID_SPI2_RX - DMAMUX_DMAREQ_ID_SPI2_TX - DMAMUX_DMAREQ_ID_SPI3_RX - DMAMUX_DMAREQ_ID_SPI3_TX
+ * - DMAMUX_DMAREQ_ID_SPI4_RX - DMAMUX_DMAREQ_ID_SPI4_TX - DMAMUX_DMAREQ_ID_I2S2_EXT_RX - DMAMUX_DMAREQ_ID_I2S2_EXT_TX
+ * - DMAMUX_DMAREQ_ID_I2S3_EXT_RX - DMAMUX_DMAREQ_ID_I2S3_EXT_TX - DMAMUX_DMAREQ_ID_I2S5_RX - DMAMUX_DMAREQ_ID_I2S5_TX
+ * - DMAMUX_DMAREQ_ID_I2C1_RX - DMAMUX_DMAREQ_ID_I2C1_TX - DMAMUX_DMAREQ_ID_I2C2_RX - DMAMUX_DMAREQ_ID_I2C2_TX
+ * - DMAMUX_DMAREQ_ID_I2C3_RX - DMAMUX_DMAREQ_ID_I2C3_TX - DMAMUX_DMAREQ_ID_USART1_RX - DMAMUX_DMAREQ_ID_USART1_TX
+ * - DMAMUX_DMAREQ_ID_USART2_RX - DMAMUX_DMAREQ_ID_USART2_TX - DMAMUX_DMAREQ_ID_USART3_RX - DMAMUX_DMAREQ_ID_USART3_TX
+ * - DMAMUX_DMAREQ_ID_USART4_RX - DMAMUX_DMAREQ_ID_USART4_TX - DMAMUX_DMAREQ_ID_USART5_RX - DMAMUX_DMAREQ_ID_USART5_TX
+ * - DMAMUX_DMAREQ_ID_USART6_RX - DMAMUX_DMAREQ_ID_USART6_TX - DMAMUX_DMAREQ_ID_USART7_RX - DMAMUX_DMAREQ_ID_USART7_TX
+ * - DMAMUX_DMAREQ_ID_USART8_RX - DMAMUX_DMAREQ_ID_USART8_TX - DMAMUX_DMAREQ_ID_SDIO1 - DMAMUX_DMAREQ_ID_QSPI1
+ * - DMAMUX_DMAREQ_ID_TMR1_CH1 - DMAMUX_DMAREQ_ID_TMR1_CH2 - DMAMUX_DMAREQ_ID_TMR1_CH3 - DMAMUX_DMAREQ_ID_TMR1_CH4
+ * - DMAMUX_DMAREQ_ID_TMR1_OVERFLOW - DMAMUX_DMAREQ_ID_TMR1_TRIG - DMAMUX_DMAREQ_ID_TMR1_HALL - DMAMUX_DMAREQ_ID_TMR8_CH1
+ * - DMAMUX_DMAREQ_ID_TMR8_CH2 - DMAMUX_DMAREQ_ID_TMR8_CH3 - DMAMUX_DMAREQ_ID_TMR8_CH4 - DMAMUX_DMAREQ_ID_TMR8_OVERFLOW
+ * - DMAMUX_DMAREQ_ID_TMR8_TRIG - DMAMUX_DMAREQ_ID_TMR8_HALL - DMAMUX_DMAREQ_ID_TMR2_CH1 - DMAMUX_DMAREQ_ID_TMR2_CH2
+ * - DMAMUX_DMAREQ_ID_TMR2_CH3 - DMAMUX_DMAREQ_ID_TMR2_CH4 - DMAMUX_DMAREQ_ID_TMR2_OVERFLOW - DMAMUX_DMAREQ_ID_TMR2_TRIG
+ * - DMAMUX_DMAREQ_ID_TMR3_CH1 - DMAMUX_DMAREQ_ID_TMR3_CH2 - DMAMUX_DMAREQ_ID_TMR3_CH3 - DMAMUX_DMAREQ_ID_TMR3_CH4
+ * - DMAMUX_DMAREQ_ID_TMR3_OVERFLOW - DMAMUX_DMAREQ_ID_TMR3_TRIG - DMAMUX_DMAREQ_ID_TMR4_CH1 - DMAMUX_DMAREQ_ID_TMR4_CH2
+ * - DMAMUX_DMAREQ_ID_TMR4_CH3 - DMAMUX_DMAREQ_ID_TMR4_CH4 - DMAMUX_DMAREQ_ID_TMR4_OVERFLOW - DMAMUX_DMAREQ_ID_TMR4_TRIG
+ * - DMAMUX_DMAREQ_ID_TMR5_CH1 - DMAMUX_DMAREQ_ID_TMR5_CH2 - DMAMUX_DMAREQ_ID_TMR5_CH3 - DMAMUX_DMAREQ_ID_TMR5_CH4
+ * - DMAMUX_DMAREQ_ID_TMR5_OVERFLOW - DMAMUX_DMAREQ_ID_TMR5_TRIG - DMAMUX_DMAREQ_ID_TMR9_CH1 - DMAMUX_DMAREQ_ID_TMR9_CH2
+ * - DMAMUX_DMAREQ_ID_TMR9_OVERFLOW - DMAMUX_DMAREQ_ID_TMR9_TRIG - DMAMUX_DMAREQ_ID_TMR9_HALL - DMAMUX_DMAREQ_ID_TMR10_CH1
+ * - DMAMUX_DMAREQ_ID_TMR10_OVERFLOW- DMAMUX_DMAREQ_ID_TMR11_CH1 - DMAMUX_DMAREQ_ID_TMR11_OVERFLOW- DMAMUX_DMAREQ_ID_TMR12_CH1
+ * - DMAMUX_DMAREQ_ID_TMR12_CH2 - DMAMUX_DMAREQ_ID_TMR12_OVERFLOW- DMAMUX_DMAREQ_ID_TMR12_TRIG - DMAMUX_DMAREQ_ID_TMR12_HALL
+ * - DMAMUX_DMAREQ_ID_TMR13_CH1 - DMAMUX_DMAREQ_ID_TMR13_OVERFLOW- DMAMUX_DMAREQ_ID_TMR14_CH1 - DMAMUX_DMAREQ_ID_TMR14_OVERFLOW
+ * - DMAMUX_DMAREQ_ID_AES_IN - DMAMUX_DMAREQ_ID_AES_OUT
+ * @retval none.
+ */
+void dmamux_init(dmamux_channel_type *dmamux_channelx, dmamux_requst_id_sel_type dmamux_req_sel)
+{
+ dmamux_channelx->muxctrl_bit.reqsel = dmamux_req_sel;
+}
+
+/**
+ * @brief dmamux sync init struct config with its default value.
+ * @param dmamux_sync_init_struct: pointer to a dmamux_sync_init_type structure which will be initialized.
+ * @retval none.
+ */
+void dmamux_sync_default_para_init(dmamux_sync_init_type *dmamux_sync_init_struct)
+{
+ dmamux_sync_init_struct->sync_enable = FALSE;
+ dmamux_sync_init_struct->sync_event_enable = FALSE;
+ dmamux_sync_init_struct->sync_polarity = DMAMUX_SYNC_POLARITY_DISABLE;
+ dmamux_sync_init_struct->sync_request_number = 0x0;
+ dmamux_sync_init_struct->sync_signal_sel = (dmamux_sync_id_sel_type)0;
+}
+
+/**
+ * @brief dmamux synchronization config.
+ * @param dmamux_channelx:
+ * this parameter can be one of the following values:
+ * - DMA1MUX_CHANNEL1
+ * - DMA1MUX_CHANNEL2
+ * - DMA1MUX_CHANNEL3
+ * - DMA1MUX_CHANNEL4
+ * - DMA1MUX_CHANNEL5
+ * - DMA1MUX_CHANNEL6
+ * - DMA1MUX_CHANNEL7
+ * - DMA2MUX_CHANNEL1
+ * - DMA2MUX_CHANNEL2
+ * - DMA2MUX_CHANNEL3
+ * - DMA2MUX_CHANNEL4
+ * - DMA2MUX_CHANNEL5
+ * - DMA2MUX_CHANNEL6
+ * - DMA2MUX_CHANNEL7
+ * @param dmamux_sync_init_struct: ointer to a dmamux_sync_init_type structure.
+ * @retval none.
+ */
+void dmamux_sync_config(dmamux_channel_type *dmamux_channelx, dmamux_sync_init_type *dmamux_sync_init_struct)
+{
+ dmamux_channelx->muxctrl_bit.syncsel = dmamux_sync_init_struct->sync_signal_sel;
+ dmamux_channelx->muxctrl_bit.syncpol = dmamux_sync_init_struct->sync_polarity;
+ dmamux_channelx->muxctrl_bit.reqcnt = dmamux_sync_init_struct->sync_request_number - 1;
+ dmamux_channelx->muxctrl_bit.evtgen = dmamux_sync_init_struct->sync_event_enable;
+ dmamux_channelx->muxctrl_bit.syncen = dmamux_sync_init_struct->sync_enable;
+}
+
+/**
+ * @brief dmamux request generator init struct config with its default value.
+ * @param dmamux_gen_init_struct: pointer to a dmamux_gen_init_type structure which will be initialized.
+ * @retval none.
+ */
+void dmamux_generator_default_para_init(dmamux_gen_init_type *dmamux_gen_init_struct)
+{
+ dmamux_gen_init_struct->gen_enable = FALSE;
+ dmamux_gen_init_struct->gen_polarity = DMAMUX_GEN_POLARITY_DISABLE;
+ dmamux_gen_init_struct->gen_request_number = 0x0;
+ dmamux_gen_init_struct->gen_signal_sel = (dmamux_gen_id_sel_type)0x0;
+}
+
+/**
+ * @brief dmamux request generator init.
+ * @param dmamux_gen_x :
+ * this parameter can be one of the following values:
+ * - DMA1MUX_GENERATOR1
+ * - DMA1MUX_GENERATOR2
+ * - DMA1MUX_GENERATOR3
+ * - DMA1MUX_GENERATOR4
+ * - DMA2MUX_GENERATOR1
+ * - DMA2MUX_GENERATOR2
+ * - DMA2MUX_GENERATOR3
+ * - DMA2MUX_GENERATOR4
+ * @param dmamux_gen_init_struct: pointer to a dmamux_gen_init_type structure which will be initialized.
+ * @retval none.
+ */
+void dmamux_generator_config(dmamux_generator_type *dmamux_gen_x, dmamux_gen_init_type *dmamux_gen_init_struct)
+{
+ dmamux_gen_x->gctrl_bit.sigsel = dmamux_gen_init_struct->gen_signal_sel;
+ dmamux_gen_x->gctrl_bit.gpol = dmamux_gen_init_struct->gen_polarity;
+ dmamux_gen_x->gctrl_bit.greqcnt = dmamux_gen_init_struct->gen_request_number - 1;
+ dmamux_gen_x->gctrl_bit.gen = dmamux_gen_init_struct->gen_enable;
+}
+
+/**
+ * @brief enable or disable the dmamux sync interrupts.
+ * @param dmamux_channelx:
+ * this parameter can be one of the following values:
+ * - DMA1MUX_CHANNEL1
+ * - DMA1MUX_CHANNEL2
+ * - DMA1MUX_CHANNEL3
+ * - DMA1MUX_CHANNEL4
+ * - DMA1MUX_CHANNEL5
+ * - DMA1MUX_CHANNEL6
+ * - DMA1MUX_CHANNEL7
+ * - DMA2MUX_CHANNEL1
+ * - DMA2MUX_CHANNEL2
+ * - DMA2MUX_CHANNEL3
+ * - DMA2MUX_CHANNEL4
+ * - DMA2MUX_CHANNEL5
+ * - DMA2MUX_CHANNEL6
+ * - DMA2MUX_CHANNEL7
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void dmamux_sync_interrupt_enable(dmamux_channel_type *dmamux_channelx, confirm_state new_state)
+{
+ if(new_state != FALSE)
+ {
+ dmamux_channelx->muxctrl_bit.syncovien = TRUE;
+ }
+ else
+ {
+ dmamux_channelx->muxctrl_bit.syncovien = FALSE;
+ }
+}
+
+/**
+ * @brief enable or disable the dmamux request generator interrupts.
+ * @param dmamux_gen_x : pointer to a dmamux_generator_type structure.
+ * this parameter can be one of the following values:
+ * - DMA1MUX_GENERATOR1
+ * - DMA1MUX_GENERATOR2
+ * - DMA1MUX_GENERATOR3
+ * - DMA1MUX_GENERATOR4
+ * - DMA2MUX_GENERATOR1
+ * - DMA2MUX_GENERATOR2
+ * - DMA2MUX_GENERATOR3
+ * - DMA2MUX_GENERATOR4
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void dmamux_generator_interrupt_enable(dmamux_generator_type *dmamux_gen_x, confirm_state new_state)
+{
+ if(new_state != FALSE)
+ {
+ dmamux_gen_x->gctrl_bit.trgovien = TRUE;
+ }
+ else
+ {
+ dmamux_gen_x->gctrl_bit.trgovien = FALSE;
+ }
+}
+
+/**
+ * @brief dmamux sync flag get.
+ * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
+ * @param flag
+ * this parameter can be any combination of the following values:
+ * - DMAMUX_SYNC_OV1_FLAG
+ * - DMAMUX_SYNC_OV2_FLAG
+ * - DMAMUX_SYNC_OV3_FLAG
+ * - DMAMUX_SYNC_OV4_FLAG
+ * - DMAMUX_SYNC_OV5_FLAG
+ * - DMAMUX_SYNC_OV6_FLAG
+ * - DMAMUX_SYNC_OV7_FLAG
+ * @retval state of dmamux sync flag.
+ */
+flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag)
+{
+ if((dma_x->muxsyncsts & flag) != RESET)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief dmamux sync interrupt flag get.
+ * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
+ * @param flag
+ * this parameter can be any combination of the following values:
+ * - DMAMUX_SYNC_OV1_FLAG
+ * - DMAMUX_SYNC_OV2_FLAG
+ * - DMAMUX_SYNC_OV3_FLAG
+ * - DMAMUX_SYNC_OV4_FLAG
+ * - DMAMUX_SYNC_OV5_FLAG
+ * - DMAMUX_SYNC_OV6_FLAG
+ * - DMAMUX_SYNC_OV7_FLAG
+ * @retval state of dmamux sync flag.
+ */
+flag_status dmamux_sync_interrupt_flag_get(dma_type *dma_x, uint32_t flag)
+{
+
+ flag_status bitstatus = RESET;
+ uint32_t sync_int_temp = flag;
+ uint32_t index = 0;
+ uint32_t tmpreg = 0, enablestatus = 0;
+ uint32_t regoffset = 0x4;
+
+ while((sync_int_temp & 0x00000001) == RESET)
+ {
+ sync_int_temp = sync_int_temp >> 1;
+ index++;
+ }
+
+ if(dma_x == DMA1)
+ {
+ tmpreg = *(uint32_t*)(DMA1MUX_BASE + (index * regoffset));
+ }
+ else
+ {
+ tmpreg = *(uint32_t*)(DMA2MUX_BASE + (index * regoffset));
+ }
+
+ if((tmpreg & (uint32_t)0x00000100) != (uint32_t)RESET)
+ {
+ enablestatus = SET;
+ }
+ else
+ {
+ enablestatus = RESET;
+ }
+
+ if(dma_x == DMA1)
+ {
+ if(((DMA1->muxsyncsts & flag) != (uint32_t)RESET) && (enablestatus != RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ else
+ {
+ if(((DMA2->muxsyncsts & flag) != (uint32_t)RESET) && (enablestatus != RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief dmamux sync flag clear.
+ * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
+ * @param flag
+ * this parameter can be any combination of the following values:
+ * - DMAMUX_SYNC_OV1_FLAG
+ * - DMAMUX_SYNC_OV2_FLAG
+ * - DMAMUX_SYNC_OV3_FLAG
+ * - DMAMUX_SYNC_OV4_FLAG
+ * - DMAMUX_SYNC_OV5_FLAG
+ * - DMAMUX_SYNC_OV6_FLAG
+ * - DMAMUX_SYNC_OV7_FLAG
+ * @retval none.
+ */
+void dmamux_sync_flag_clear(dma_type *dma_x, uint32_t flag)
+{
+ dma_x->muxsyncclr = flag;
+}
+
+/**
+ * @brief dmamux request generator flag get.
+ * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
+ * @param flag
+ * this parameter can be any combination of the following values:
+ * - DMAMUX_GEN_TRIG_OV1_FLAG
+ * - DMAMUX_GEN_TRIG_OV2_FLAG
+ * - DMAMUX_GEN_TRIG_OV3_FLAG
+ * - DMAMUX_GEN_TRIG_OV4_FLAG
+ * @retval state of dmamux sync flag.
+ */
+flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag)
+{
+ if((dma_x->muxgsts & flag) != RESET)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief dmamux request generator interrupt flag get.
+ * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
+ * @param flag
+ * this parameter can be any combination of the following values:
+ * - DMAMUX_GEN_TRIG_OV1_FLAG
+ * - DMAMUX_GEN_TRIG_OV2_FLAG
+ * - DMAMUX_GEN_TRIG_OV3_FLAG
+ * - DMAMUX_GEN_TRIG_OV4_FLAG
+ * @retval state of dmamux sync flag.
+ */
+flag_status dmamux_generator_interrupt_flag_get(dma_type *dma_x, uint32_t flag)
+{
+ flag_status bitstatus = RESET;
+ uint32_t sync_int_temp = flag;
+ uint32_t index = 0;
+ uint32_t tmpreg = 0, enablestatus = 0;
+ uint32_t regoffset = 0x4;
+
+ while((sync_int_temp & 0x00000001) == RESET)
+ {
+ sync_int_temp = sync_int_temp >> 1;
+ index++;
+ }
+
+ if(dma_x == DMA1)
+ tmpreg = *(uint32_t*)(DMA1MUX_GENERATOR1_BASE + (index * regoffset));
+ else
+ tmpreg = *(uint32_t*)(DMA2MUX_GENERATOR1_BASE + (index * regoffset));
+
+ if((tmpreg & (uint32_t)0x00000100) != (uint32_t)RESET)
+ {
+ enablestatus = SET;
+ }
+ else
+ {
+ enablestatus = RESET;
+ }
+ if(dma_x == DMA1)
+ {
+ if(((DMA1->muxgsts & flag) != (uint32_t)RESET) && (enablestatus != RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ else
+ {
+ if(((DMA2->muxgsts & flag) != (uint32_t)RESET) && (enablestatus != RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+
+ return bitstatus;
+}
+
+/**
+ * @brief dmamux request generator flag clear.
+ * @param dma_x : pointer to a dma_type structure, can be DMA1 or DMA2.
+ * @param flag
+ * this parameter can be any combination of the following values:
+ * - DMAMUX_GEN_TRIG_OV1_FLAG
+ * - DMAMUX_GEN_TRIG_OV2_FLAG
+ * - DMAMUX_GEN_TRIG_OV3_FLAG
+ * - DMAMUX_GEN_TRIG_OV4_FLAG
+ * @retval none.
+ */
+void dmamux_generator_flag_clear(dma_type *dma_x, uint32_t flag)
+{
+ dma_x->muxgclr = flag;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_emac.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_emac.c
new file mode 100644
index 00000000000..ce1ed56438a
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_emac.c
@@ -0,0 +1,2457 @@
+/**
+ **************************************************************************
+ * @file at32f45x_emac.c
+ * @brief contains all the functions for the emac firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup EMAC
+ * @brief EMAC driver modules
+ * @{
+ */
+
+#ifdef EMAC_MODULE_ENABLED
+
+/** @defgroup EMAC_private_functions
+ * @{
+ */
+
+#if defined (EMAC_BASE)
+/**
+ * @brief global pointers on tx and rx descriptor used to track transmit and receive descriptors
+ */
+__IO emac_dma_desc_type *dma_tx_desc_to_set;
+__IO emac_dma_desc_type *dma_rx_desc_to_get;
+__IO emac_dma_desc_type *ptp_dma_tx_desc_to_set;
+__IO emac_dma_desc_type *ptp_dma_rx_desc_to_get;
+
+/* emac private function */
+static void emac_delay(uint32_t delay);
+
+/**
+ * @brief deinitialize the emac peripheral registers to their default reset values.
+ * @param none
+ * @retval none
+ */
+void emac_reset(void)
+{
+ crm_periph_reset(CRM_EMAC_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_EMAC_PERIPH_RESET, FALSE);
+}
+
+/**
+ * @brief initialize emac control structure
+ * @param emac_control_config_type
+ * @retval none
+ */
+void emac_control_para_init(emac_control_config_type *control_para)
+{
+ control_para->auto_nego = EMAC_AUTO_NEGOTIATION_OFF;
+ control_para->auto_pad_crc_strip = FALSE;
+ control_para->back_off_limit = EMAC_BACKOFF_LIMIT_0;
+ control_para->carrier_sense_disable = FALSE;
+ control_para->deferral_check = FALSE;
+ control_para->duplex_mode = EMAC_HALF_DUPLEX;
+ control_para->fast_ethernet_speed = EMAC_SPEED_10MBPS;
+ control_para->interframe_gap = EMAC_INTERFRAME_GAP_96BIT;
+ control_para->ipv4_checksum_offload = FALSE;
+ control_para->jabber_disable = FALSE;
+ control_para->loopback_mode = FALSE;
+ control_para->receive_own_disable = FALSE;
+ control_para->retry_disable = FALSE;
+ control_para->watchdog_disable = FALSE;
+}
+
+/**
+ * @brief according to hclk to set mdc clock frequency.
+ * @param none
+ * @retval none
+ */
+void emac_clock_range_set(void)
+{
+ uint8_t bits_value = 0;
+ crm_clocks_freq_type clocks_freq = {0};
+
+ /* clear clock range bits */
+ EMAC->miiaddr_bit.cr = bits_value;
+
+ crm_clocks_freq_get(&clocks_freq);
+
+ if((clocks_freq.ahb_freq >= EMAC_HCLK_BORDER_20MHZ) && (clocks_freq.ahb_freq < EMAC_HCLK_BORDER_35MHZ))
+ {
+ bits_value = EMAC_CLOCK_RANGE_20_TO_35;
+ }
+ else if((clocks_freq.ahb_freq >= EMAC_HCLK_BORDER_35MHZ) && (clocks_freq.ahb_freq < EMAC_HCLK_BORDER_60MHZ))
+ {
+ bits_value = EMAC_CLOCK_RANGE_35_TO_60;
+ }
+ else if((clocks_freq.ahb_freq >= EMAC_HCLK_BORDER_60MHZ) && (clocks_freq.ahb_freq < EMAC_HCLK_BORDER_100MHZ))
+ {
+ bits_value = EMAC_CLOCK_RANGE_60_TO_100;
+ }
+ else if((clocks_freq.ahb_freq >= EMAC_HCLK_BORDER_100MHZ) && (clocks_freq.ahb_freq < EMAC_HCLK_BORDER_150MHZ))
+ {
+ bits_value = EMAC_CLOCK_RANGE_100_TO_150;
+ }
+ else if((clocks_freq.ahb_freq >= EMAC_HCLK_BORDER_150MHZ) && (clocks_freq.ahb_freq < EMAC_HCLK_BORDER_250MHZ))
+ {
+ bits_value = EMAC_CLOCK_RANGE_150_TO_250;
+ }
+ else if((clocks_freq.ahb_freq >= EMAC_HCLK_BORDER_250MHZ) && (clocks_freq.ahb_freq <= EMAC_HCLK_BORDER_288MHZ))
+ {
+ bits_value = EMAC_CLOCK_RANGE_250_TO_288;
+ }
+
+ EMAC->miiaddr_bit.cr = bits_value;
+}
+
+/**
+ * @brief configure emac control setting.
+ * @param control_struct: control setting of mac control register.
+ * @retval none
+ */
+void emac_control_config(emac_control_config_type *control_struct)
+{
+ emac_deferral_check_set(control_struct->deferral_check);
+ emac_backoff_limit_set(control_struct->back_off_limit);
+ emac_auto_pad_crc_stripping_set(control_struct->auto_pad_crc_strip);
+ emac_retry_disable(control_struct->retry_disable);
+ emac_ipv4_checksum_offload_set(control_struct->ipv4_checksum_offload);
+ emac_loopback_mode_enable(control_struct->loopback_mode);
+ emac_receive_own_disable(control_struct->receive_own_disable);
+ emac_carrier_sense_disable(control_struct->carrier_sense_disable);
+ emac_interframe_gap_set(control_struct->interframe_gap);
+ emac_jabber_disable(control_struct->jabber_disable);
+ emac_watchdog_disable(control_struct->watchdog_disable);
+}
+
+/**
+ * @brief reset emac dma
+ * @param none
+ * @retval none
+ */
+void emac_dma_software_reset_set(void)
+{
+ EMAC_DMA->bm_bit.swr = 1;
+}
+
+/**
+ * @brief get emac dma reset status
+ * @param none
+ * @retval TRUE of FALSE
+ */
+flag_status emac_dma_software_reset_get(void)
+{
+ if(EMAC_DMA->bm_bit.swr)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief enable emac and dma reception/transmission
+ * @param none
+ * @retval none
+ */
+void emac_start(void)
+{
+ /* enable transmit state machine of the mac for transmission on the mii */
+ emac_trasmitter_enable(TRUE);
+
+ /* flush transmit fifo */
+ emac_dma_operations_set(EMAC_DMA_OPS_FLUSH_TRANSMIT_FIFO, TRUE);
+
+ /* enable receive state machine of the mac for reception from the mii */
+ emac_receiver_enable(TRUE);
+
+ /* start dma transmission */
+ emac_dma_operations_set(EMAC_DMA_OPS_START_STOP_TRANSMIT, TRUE);
+
+ /* start dma reception */
+ emac_dma_operations_set(EMAC_DMA_OPS_START_STOP_RECEIVE, TRUE);
+}
+
+/**
+ * @brief stop emac and dma reception/transmission
+ * @param none
+ * @retval none
+ */
+void emac_stop(void)
+{
+ /* stop dma transmission */
+ emac_dma_operations_set(EMAC_DMA_OPS_START_STOP_TRANSMIT, FALSE);
+
+ /* stop dma reception */
+ emac_dma_operations_set(EMAC_DMA_OPS_START_STOP_RECEIVE, FALSE);
+
+ /* stop receive state machine of the mac for reception from the mii */
+ emac_receiver_enable(FALSE);
+
+ /* flush transmit fifo */
+ emac_dma_operations_set(EMAC_DMA_OPS_FLUSH_TRANSMIT_FIFO, TRUE);
+
+ /* stop transmit state machine of the mac for transmission on the mii */
+ emac_trasmitter_enable(FALSE);
+}
+
+/**
+ * @brief write phy data.
+ * @param address: phy address.
+ * @param reg: register of phy.
+ * @param data: value that wants to write to phy.
+ * @retval SUCCESS or ERROR
+ */
+error_status emac_phy_register_write(uint8_t address, uint8_t reg, uint16_t data)
+{
+ uint32_t timeout = 0;
+
+ EMAC->miidt_bit.md = data;
+
+ EMAC->miiaddr_bit.pa = address;
+ EMAC->miiaddr_bit.mii = reg;
+ EMAC->miiaddr_bit.mw = 1;
+ EMAC->miiaddr_bit.mb = 1;
+
+ do
+ {
+ timeout++;
+ } while((EMAC->miiaddr_bit.mb) && (timeout < PHY_TIMEOUT));
+
+ if(timeout == PHY_TIMEOUT)
+ {
+ return ERROR;
+ }
+ return SUCCESS;
+}
+
+/**
+ * @brief read phy data
+ * @param address: phy address.
+ * @param reg: register of phy.
+ * @param data: value that is read from phy.
+ * @retval SUCCESS or ERROR
+ */
+error_status emac_phy_register_read(uint8_t address, uint8_t reg, uint16_t *data)
+{
+ uint32_t timeout = 0;
+
+ EMAC->miiaddr_bit.pa = address;
+ EMAC->miiaddr_bit.mii = reg;
+ EMAC->miiaddr_bit.mw = 0;
+ EMAC->miiaddr_bit.mb = 1;
+
+ do
+ {
+ timeout++;
+ *data = EMAC->miidt_bit.md;
+ } while((EMAC->miiaddr_bit.mb) && (timeout < PHY_TIMEOUT));
+
+ if(timeout == PHY_TIMEOUT)
+ {
+ return ERROR;
+ }
+
+ *data = EMAC->miidt_bit.md;
+ return SUCCESS;
+}
+
+/**
+ * @brief emac receiver enable.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_receiver_enable(confirm_state new_state)
+{
+ __IO uint32_t temp = 0;
+
+ EMAC->ctrl_bit.re = new_state;
+
+ temp = EMAC->ctrl;
+ emac_delay(1);
+ EMAC->ctrl = temp;
+}
+
+/**
+ * @brief emac transmitter enable.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_trasmitter_enable(confirm_state new_state)
+{
+ __IO uint32_t temp = 0;
+
+ EMAC->ctrl_bit.te = new_state;
+
+ temp = EMAC->ctrl;
+ emac_delay(1);
+ EMAC->ctrl = temp;
+}
+
+/**
+ * @brief emac defferal check enable, only avalible in half-duplex mode.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_deferral_check_set(confirm_state new_state)
+{
+ EMAC->ctrl_bit.dc = new_state;
+}
+
+/**
+ * @brief emac back-off limit, only avalible in half-duplex mode.
+ * @param slot_time: waiting time of retransmission after collision
+ * this parameter can be one of the following values:
+ * - EMAC_BACKOFF_LIMIT_0
+ * - EMAC_BACKOFF_LIMIT_1
+ * - EMAC_BACKOFF_LIMIT_2
+ * - EMAC_BACKOFF_LIMIT_3
+ * @retval none
+ */
+void emac_backoff_limit_set(emac_bol_type slot_time)
+{
+ EMAC->ctrl_bit.bl = slot_time;
+}
+
+/**
+ * @brief set mac automatic pad/CRC stripping.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_auto_pad_crc_stripping_set(confirm_state new_state)
+{
+ EMAC->ctrl_bit.acs = new_state;
+}
+
+/**
+ * @brief transmittion retry disable.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_retry_disable(confirm_state new_state)
+{
+ EMAC->ctrl_bit.dr = new_state;
+}
+
+/**
+ * @brief set ipv4 checksum offload.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ipv4_checksum_offload_set(confirm_state new_state)
+{
+ EMAC->ctrl_bit.ipc = new_state;
+}
+
+/**
+ * @brief enable loopback mode.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_loopback_mode_enable(confirm_state new_state)
+{
+ EMAC->ctrl_bit.lm = new_state;
+}
+
+/**
+ * @brief receive own disable.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_receive_own_disable(confirm_state new_state)
+{
+ EMAC->ctrl_bit.dro = new_state;
+}
+
+/**
+ * @brief carrier sense disbale.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_carrier_sense_disable(confirm_state new_state)
+{
+ EMAC->ctrl_bit.dcs = new_state;
+}
+
+/**
+ * @brief set minimum interframe gap between frames during transmission.
+ * @param number: interframe gap number.
+ * this parameter can be one of the following values:
+ * - EMAC_FRAME_GAP_96BIT
+ * - EMAC_FRAME_GAP_88BIT
+ * - EMAC_FRAME_GAP_80BIT
+ * - EMAC_FRAME_GAP_72BIT
+ * - EMAC_FRAME_GAP_64BIT
+ * - EMAC_FRAME_GAP_56BIT
+ * - EMAC_FRAME_GAP_48BIT
+ * - EMAC_FRAME_GAP_40BIT
+ * @retval none
+ */
+void emac_interframe_gap_set(emac_intergrame_gap_type number)
+{
+ EMAC->ctrl_bit.ifg = number;
+}
+
+/**
+ * @brief jabber disable.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_jabber_disable(confirm_state new_state)
+{
+ EMAC->ctrl_bit.jd = new_state;
+}
+
+/**
+ * @brief watchdog disable.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_watchdog_disable(confirm_state new_state)
+{
+ EMAC->ctrl_bit.wd = new_state;
+}
+
+/**
+ * @brief set mac fast emac speed.
+ * @param speed: mac bandwidth
+ * this parameter can be one of the following values:
+ * - EMAC_SPEED_10MBPS
+ * - EMAC_SPEED_100MBPS
+ * @retval none
+ */
+void emac_fast_speed_set(emac_speed_type speed)
+{
+ EMAC->ctrl_bit.fes = speed;
+}
+
+/**
+ * @brief set duplex mode.
+ * @param duplex_mode: communication mode
+ * this parameter can be one of the following values:
+ * - EMAC_HALF_DUPLEX
+ * - EMAC_FULL_DUPLEX
+ * @retval none
+ */
+void emac_duplex_mode_set(emac_duplex_type duplex_mode)
+{
+ EMAC->ctrl_bit.dm = duplex_mode;
+}
+
+/**
+ * @brief set mac promiscuous mode.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_promiscuous_mode_set(confirm_state new_state)
+{
+ EMAC->frmf_bit.pr = new_state;
+}
+
+/**
+ * @brief hash unicast.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_hash_unicast_set(confirm_state new_state)
+{
+ EMAC->frmf_bit.huc = new_state;
+}
+
+/**
+ * @brief hash multicast.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_hash_multicast_set(confirm_state new_state)
+{
+ EMAC->frmf_bit.hmc = new_state;
+}
+
+/**
+ * @brief destination address inverse filtering.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_dstaddr_inverse_filter_set(confirm_state new_state)
+{
+ EMAC->frmf_bit.daif = new_state;
+}
+
+/**
+ * @brief pass all multicasting frames.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_pass_all_multicasting_set(confirm_state new_state)
+{
+ EMAC->frmf_bit.pmc = new_state;
+}
+
+/**
+ * @brief broadcast frames disable.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_broadcast_frames_disable(confirm_state new_state)
+{
+ EMAC->frmf_bit.dbf = new_state;
+}
+
+/**
+ * @brief set mac how to pass control frames.
+ * @param condition: set what control frame can pass filter.
+ * this parameter can be one of the following values:
+ * - EMAC_CONTROL_FRAME_PASSING_NO
+ * - EMAC_CONTROL_FRAME_PASSING_ALL_EXCEPT_PAUSE
+ * - EMAC_CONTROL_FRAME_PASSING_ALL
+ * - EMAC_CONTROL_FRAME_PASSING_MATCH
+ * @retval none
+ */
+void emac_pass_control_frames_set(emac_control_frames_filter_type condition)
+{
+ EMAC->frmf_bit.pcf = condition;
+}
+
+/**
+ * @brief source address inverse filtering.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_srcaddr_inverse_filter_set(confirm_state new_state)
+{
+ EMAC->frmf_bit.saif = new_state;
+}
+
+/**
+ * @brief source address filtering.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_srcaddr_filter_set(confirm_state new_state)
+{
+ EMAC->frmf_bit.saf = new_state;
+}
+
+/**
+ * @brief mac uses hash or perfect filter.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_hash_perfect_filter_set(confirm_state new_state)
+{
+ EMAC->frmf_bit.hpf = new_state;
+}
+
+/**
+ * @brief mac receives all frames.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_receive_all_set(confirm_state new_state)
+{
+ EMAC->frmf_bit.ra = new_state;
+}
+
+/**
+ * @brief hash table high 32-bit.
+ * @param high32bits: the highest 32-bit of hash table.
+ * @retval none
+ */
+void emac_hash_table_high32bits_set(uint32_t high32bits)
+{
+ EMAC->hth_bit.hth = high32bits;
+}
+
+/**
+ * @brief hash table low 32-bit.
+ * @param low32bits: the lowest 32-bit of hash table.
+ * @retval none
+ */
+void emac_hash_table_low32bits_set(uint32_t low32bits)
+{
+ EMAC->htl_bit.htl = low32bits;
+}
+
+/**
+ * @brief mii busy status.
+ * @param none
+ * @retval SET or RESET
+ */
+flag_status emac_mii_busy_get(void)
+{
+ if(EMAC->miiaddr_bit.mb) {
+ return SET;
+ }
+ else {
+ return RESET;
+ }
+}
+
+/**
+ * @brief tell phy that will be written.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_mii_write(confirm_state new_state)
+{
+ EMAC->miiaddr_bit.mw = new_state;
+}
+
+/**
+ * @brief set flow control busy in full-duplex mode, back pressure activate in half-duplex mode.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_fcb_bpa_set(confirm_state new_state)
+{
+ EMAC->fctrl_bit.fcbbpa = new_state;
+}
+
+/**
+ * @brief set transmit flow control.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_transmit_flow_control_enable(confirm_state new_state)
+{
+ EMAC->fctrl_bit.etf = new_state;
+}
+
+/**
+ * @brief set receive flow control.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_receive_flow_control_enable(confirm_state new_state)
+{
+ EMAC->fctrl_bit.erf = new_state;
+}
+
+/**
+ * @brief set unicast pause frame detect.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_unicast_pause_frame_detect(confirm_state new_state)
+{
+ EMAC->fctrl_bit.dup = new_state;
+}
+
+/**
+ * @brief set pause low threshold.
+ * @param pasue_threshold: pause slot time.
+ * this parameter can be one of the following values:
+ * - EMAC_PAUSE_4_SLOT_TIME
+ * - EMAC_PAUSE_28_SLOT_TIME
+ * - EMAC_PAUSE_144_SLOT_TIME
+ * - EMAC_PAUSE_256_SLOT_TIME
+ * @retval none
+ */
+void emac_pause_low_threshold_set(emac_pause_slot_threshold_type pasue_threshold)
+{
+ EMAC->fctrl_bit.plt = pasue_threshold;
+}
+
+/**
+ * @brief set zero-quanta pause disable.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_zero_quanta_pause_disable(confirm_state new_state)
+{
+ EMAC->fctrl_bit.dzqp = new_state;
+}
+
+/**
+ * @brief set pause time.
+ * @param pause_time: time slots to pause transmit frame.
+ * @retval none
+ */
+void emac_pause_time_set(uint16_t pause_time)
+{
+ EMAC->fctrl_bit.pt = pause_time;
+}
+
+/**
+ * @brief identify coming vlan frame field with setting value.
+ * @param identifier: it will be compared with coming frame.
+ * @retval none
+ */
+void emac_vlan_tag_identifier_set(uint16_t identifier)
+{
+ EMAC->vlt_bit.vti = identifier;
+}
+
+/**
+ * @brief set 12-bit vlan identifier.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_vlan_tag_comparison_set(confirm_state new_state)
+{
+ EMAC->vlt_bit.etv = new_state;
+}
+
+/**
+ * @brief set wakeup frame.
+ * @param value: it will be written to eight non transparent registers.
+ * @retval none
+ */
+void emac_wakeup_frame_set(uint32_t value)
+{
+ EMAC->rwff = value;
+}
+
+/**
+ * @brief get wakeup frame.
+ * @param none
+ * @retval get value from eight non transparent registers.
+ */
+uint32_t emac_wakeup_frame_get(void)
+{
+ return (EMAC->rwff);
+}
+
+/**
+ * @brief all frame will be droppped except wakeup frame or magic packet.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_power_down_set(confirm_state new_state)
+{
+ EMAC->pmtctrlsts_bit.pd = new_state;
+}
+
+/**
+ * @brief magic packet enable
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_magic_packet_enable(confirm_state new_state)
+{
+ EMAC->pmtctrlsts_bit.emp = new_state;
+}
+
+/**
+ * @brief wakeup frame enable
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_wakeup_frame_enable(confirm_state new_state)
+{
+ EMAC->pmtctrlsts_bit.erwf = new_state;
+}
+
+/**
+ * @brief received magic packet
+ * @param none
+ * @retval the new state of usart_flag (SET or RESET).
+ */
+flag_status emac_received_magic_packet_get(void)
+{
+ if(EMAC->pmtctrlsts_bit.rmp)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief received wakeup frame.
+ * @param none
+ * @retval the new state of usart_flag (SET or RESET).
+ */
+flag_status emac_received_wakeup_frame_get(void)
+{
+ if(EMAC->pmtctrlsts_bit.rrwf)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief set unicast frame that passes DAF as wakeup frame.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_global_unicast_set(confirm_state new_state)
+{
+ EMAC->pmtctrlsts_bit.guc = new_state;
+}
+
+/**
+ * @brief reset wakeup frame filter resgister
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_wakeup_frame_filter_reset(confirm_state new_state)
+{
+ EMAC->pmtctrlsts_bit.rwffpr = new_state;
+}
+
+/**
+ * @brief read interrupt status
+ * @param flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - EMAC_PMT_FLAG
+ * - EMAC_MMC_FLAG
+ * - EMAC_MMCR_FLAG
+ * - EMAC_MMCT_FLAG
+ * - EMAC_TST_FLAG
+ * @retval the new state of usart_flag (SET or RESET).
+ */
+flag_status emac_interrupt_status_read(uint32_t flag)
+{
+ if(EMAC->ists & flag)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief set interrupt mask
+ * @param mask_type: mask the interrupt signal
+ * this parameter can be one of the following values:
+ * - EMAC_INTERRUPT_PMT_MASK
+ * - EMAC_INTERRUPT_TST_MASK
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_interrupt_mask_set(emac_interrupt_mask_type mask_type, confirm_state new_state)
+{
+ switch(mask_type)
+ {
+ case EMAC_INTERRUPT_PMT_MASK:
+ {
+ EMAC->imr_bit.pim = new_state;
+ break;
+ }
+ case EMAC_INTERRUPT_TST_MASK:
+ {
+ EMAC->imr_bit.tim = new_state;
+ break;
+ }
+ }
+}
+
+/**
+ * @brief set local mac address
+ * @param address: local address for mac0
+ * @retval none
+ */
+void emac_local_address_set(uint8_t *address)
+{
+ EMAC->a0h_bit.ma0h = (uint32_t)(address[5] << 8 | address[4]);
+ EMAC->a0l_bit.ma0l = (uint32_t)(address[3] << 24 | address[2] << 16 | address[1] << 8 | address[0]);
+}
+
+/**
+ * @brief set mac filter address
+ * @param mac: select which mac you want to set
+ * this parameter can be one of the following values:
+ * - EMAC_ADDRESS_FILTER_1
+ * - EMAC_ADDRESS_FILTER_2
+ * - EMAC_ADDRESS_FILTER_3
+ * @retval none
+ */
+void emac_address_filter_set(emac_address_type mac, emac_address_filter_type filter, emac_address_mask_type mask_bit, confirm_state new_state)
+{
+ switch(mac)
+ {
+ case EMAC_ADDRESS_FILTER_1:
+ {
+ EMAC->a1h_bit.sa = filter;
+ EMAC->a1h_bit.mbc = mask_bit;
+ EMAC->a1h_bit.ae = new_state;
+ break;
+ }
+ case EMAC_ADDRESS_FILTER_2:
+ {
+ EMAC->a2h_bit.sa = filter;
+ EMAC->a2h_bit.mbc = mask_bit;
+ EMAC->a2h_bit.ae = new_state;
+ break;
+ }
+ case EMAC_ADDRESS_FILTER_3:
+ {
+ EMAC->a3h_bit.sa = filter;
+ EMAC->a3h_bit.mbc = mask_bit;
+ EMAC->a3h_bit.ae = new_state;
+ break;
+ }
+ }
+}
+
+/**
+ * @brief set transmit/receive descriptor list address
+ * @param transfer_type: it will be transmit or receive
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_TRANSMIT
+ * - EMAC_DMA_RECEIVE
+ * @param dma_desc_tab: pointer on the first tx desc list
+ * @param buff: pointer on the first tx/rx buffer list
+ * @param buffer_count: number of the used Tx desc in the list
+ * @retval none
+ */
+void emac_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, uint8_t *buff, uint32_t buffer_count)
+{
+ uint32_t i = 0;
+ emac_dma_desc_type *dma_descriptor;
+
+ switch(transfer_type)
+ {
+ case EMAC_DMA_TRANSMIT:
+ {
+ dma_tx_desc_to_set = dma_desc_tab;
+ for(i = 0; i < buffer_count; i++)
+ {
+ dma_descriptor = dma_desc_tab + i;
+
+ dma_descriptor->status = EMAC_DMATXDESC_TCH;
+
+ dma_descriptor->buf1addr = (uint32_t)(&buff[i * EMAC_MAX_PACKET_LENGTH]);
+
+ if(i < (buffer_count - 1))
+ {
+ dma_descriptor->buf2nextdescaddr = (uint32_t)(dma_desc_tab + i + 1);
+ }
+ else
+ {
+ dma_descriptor->buf2nextdescaddr = (uint32_t) dma_desc_tab;
+ }
+ }
+ EMAC_DMA->tdladdr_bit.stl = (uint32_t) dma_desc_tab;
+ break;
+ }
+ case EMAC_DMA_RECEIVE:
+ {
+ dma_rx_desc_to_get = dma_desc_tab;
+ for(i = 0; i < buffer_count; i++)
+ {
+ dma_descriptor = dma_desc_tab + i;
+
+ dma_descriptor->status = EMAC_DMARXDESC_OWN;
+
+ dma_descriptor->controlsize = EMAC_DMARXDESC_RCH | (uint32_t)EMAC_MAX_PACKET_LENGTH;
+
+ dma_descriptor->buf1addr = (uint32_t)(&buff[i * EMAC_MAX_PACKET_LENGTH]);
+
+ if(i < (buffer_count - 1))
+ {
+ dma_descriptor->buf2nextdescaddr = (uint32_t)(dma_desc_tab + i + 1);
+ }
+ else
+ {
+ dma_descriptor->buf2nextdescaddr = (uint32_t) dma_desc_tab;
+ }
+ }
+ EMAC_DMA->rdladdr_bit.srl = (uint32_t) dma_desc_tab;
+ break;
+ }
+ }
+}
+
+/**
+ * @brief set transmit/receive descriptor list address
+ * @param transfer_type: it will be transmit or receive
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_TRANSMIT
+ * - EMAC_DMA_RECEIVE
+ * @param dma_desc_tab: pointer on the first tx desc list
+ * @param buff: pointer on the first tx/rx buffer list
+ * @param buffer_count: number of the used Tx desc in the list
+ * @retval none
+ */
+void emac_ptp_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, emac_dma_desc_type *ptp_dma_desc_tab, uint8_t *buff, uint32_t buffer_count)
+{
+ uint32_t i = 0;
+ emac_dma_desc_type *dma_descriptor;
+
+ switch(transfer_type)
+ {
+ case EMAC_DMA_TRANSMIT:
+ {
+ dma_tx_desc_to_set = dma_desc_tab;
+ ptp_dma_tx_desc_to_set = ptp_dma_desc_tab;
+
+ for(i = 0; i < buffer_count; i++)
+ {
+ dma_descriptor = dma_desc_tab + i;
+
+ dma_descriptor->status = EMAC_DMATXDESC_TCH | EMAC_DMATXDESC_TTSE;
+
+ dma_descriptor->buf1addr = (uint32_t)(&buff[i * EMAC_MAX_PACKET_LENGTH]);
+
+ if(i < (buffer_count - 1))
+ {
+ dma_descriptor->buf2nextdescaddr = (uint32_t)(dma_desc_tab + i + 1);
+ }
+ else
+ {
+ dma_descriptor->buf2nextdescaddr = (uint32_t) dma_desc_tab;
+ }
+
+ (&ptp_dma_desc_tab[i])->buf1addr = dma_descriptor->buf1addr;
+ (&ptp_dma_desc_tab[i])->buf2nextdescaddr = dma_descriptor->buf2nextdescaddr;
+ }
+
+ (&ptp_dma_desc_tab[i-1])->status = (uint32_t) ptp_dma_desc_tab;
+
+ EMAC_DMA->tdladdr_bit.stl = (uint32_t) dma_desc_tab;
+ break;
+ }
+ case EMAC_DMA_RECEIVE:
+ {
+ dma_rx_desc_to_get = dma_desc_tab;
+ ptp_dma_rx_desc_to_get = ptp_dma_desc_tab;
+
+ for(i = 0; i < buffer_count; i++)
+ {
+ dma_descriptor = dma_desc_tab + i;
+
+ dma_descriptor->status = EMAC_DMARXDESC_OWN;
+
+ dma_descriptor->controlsize = EMAC_DMARXDESC_RCH | (uint32_t)EMAC_MAX_PACKET_LENGTH;
+
+ dma_descriptor->buf1addr = (uint32_t)(&buff[i * EMAC_MAX_PACKET_LENGTH]);
+
+ if(i < (buffer_count - 1))
+ {
+ dma_descriptor->buf2nextdescaddr = (uint32_t)(dma_desc_tab + i + 1);
+ }
+ else
+ {
+ dma_descriptor->buf2nextdescaddr = (uint32_t) dma_desc_tab;
+ }
+
+ (&ptp_dma_desc_tab[i])->buf1addr = dma_descriptor->buf1addr;
+ (&ptp_dma_desc_tab[i])->buf2nextdescaddr = dma_descriptor->buf2nextdescaddr;
+ }
+
+ (&ptp_dma_desc_tab[i-1])->status = (uint32_t) ptp_dma_desc_tab;
+
+ EMAC_DMA->rdladdr_bit.srl = (uint32_t) dma_desc_tab;
+ break;
+ }
+ }
+}
+/**
+ * @brief enable or disable the specified dma rx descriptor receive interrupt
+ * @param dma_rx_desc: pointer on a rx desc.
+ * @param new_state: new state of the specified dma rx descriptor interrupt.
+ * this parameter can be one of the following values:
+ * - TRUE
+ * - FALSE.
+ * @retval none
+ */
+void emac_dma_rx_desc_interrupt_config(emac_dma_desc_type *dma_rx_desc, confirm_state new_state)
+{
+ if (new_state != FALSE)
+ {
+ /* enable the dma rx desc receive interrupt */
+ dma_rx_desc->controlsize &= (~(uint32_t)EMAC_DMARXDESC_DIC);
+ }
+ else
+ {
+ /* disable the dma rx desc receive interrupt */
+ dma_rx_desc->controlsize |= EMAC_DMARXDESC_DIC;
+ }
+}
+
+/**
+ * @brief get transmit/receive descriptor list address
+ * @param transfer_type: it will be transmit or receive
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_TRANSMIT
+ * - EMAC_DMA_RECEIVE
+ * @retval transmit/receive descriptor list address
+ */
+uint32_t emac_dma_descriptor_list_address_get(emac_dma_tx_rx_type transfer_type)
+{
+ switch(transfer_type)
+ {
+ case EMAC_DMA_TRANSMIT:
+ {
+ return (EMAC_DMA->tdladdr_bit.stl);
+ }
+ case EMAC_DMA_RECEIVE:
+ {
+ return (EMAC_DMA->rdladdr_bit.srl);
+ }
+ }
+ return 0;
+}
+
+/**
+ * @brief get the size of received the received packet.
+ * @param none
+ * @retval received packet size
+ */
+uint32_t emac_received_packet_size_get(void)
+{
+ uint32_t frame_length = 0;
+ if(((dma_rx_desc_to_get->status & EMAC_DMARXDESC_OWN) == (uint32_t)RESET) &&
+ ((dma_rx_desc_to_get->status & EMAC_DMATXDESC_ES) == (uint32_t)RESET) &&
+ ((dma_rx_desc_to_get->status & EMAC_DMARXDESC_LS) != (uint32_t)RESET) &&
+ ((dma_rx_desc_to_get->status & EMAC_DMARXDESC_FS) != (uint32_t)RESET))
+ {
+ frame_length = emac_dmarxdesc_frame_length_get((emac_dma_desc_type*) dma_rx_desc_to_get);
+ }
+
+ return frame_length;
+}
+
+/**
+ * @brief get the specified dma rx descsriptor frame length.
+ * @param dma_rx_desc: pointer on a dma rx descriptor
+ * @retval the rx descriptor received frame length.
+ */
+uint32_t emac_dmarxdesc_frame_length_get(emac_dma_desc_type *dma_rx_desc)
+{
+ return ((dma_rx_desc->status & EMAC_DMARXDESC_FL) >> EMAC_DMARXDESC_FRAME_LENGTHSHIFT);
+}
+
+/**
+ * @brief init emac dma parameters
+ * @param emac_dma_config_type
+ * @retval none
+ */
+void emac_dma_para_init(emac_dma_config_type *control_para)
+{
+ control_para->aab_enable = FALSE;
+ control_para->da_enable = FALSE;
+ control_para->desc_skip_length = 0;
+ control_para->dt_disable = FALSE;
+ control_para->fb_enable = FALSE;
+ control_para->fef_enable = FALSE;
+ control_para->flush_rx_disable = FALSE;
+ control_para->fugf_enable = FALSE;
+ control_para->osf_enable = FALSE;
+ control_para->priority_ratio = EMAC_DMA_1_RX_1_TX;
+ control_para->rsf_enable = FALSE;
+ control_para->rx_dma_pal = EMAC_DMA_PBL_1;
+ control_para->rx_threshold = EMAC_DMA_RX_THRESHOLD_64_BYTES;
+ control_para->tsf_enable = FALSE;
+ control_para->tx_dma_pal = EMAC_DMA_PBL_1;
+ control_para->tx_threshold = EMAC_DMA_TX_THRESHOLD_64_BYTES;
+ control_para->usp_enable = FALSE;
+}
+
+/**
+ * @brief configure emac dma
+ * @param emac_dma_config_type
+ * @retval none
+ */
+void emac_dma_config(emac_dma_config_type *control_para)
+{
+ EMAC_DMA->bm_bit.aab = control_para->aab_enable;
+ EMAC_DMA->bm_bit.dsl = control_para->desc_skip_length;
+ EMAC_DMA->bm_bit.rdp = control_para->rx_dma_pal;
+ EMAC_DMA->bm_bit.pbl = control_para->tx_dma_pal;
+ EMAC_DMA->bm_bit.fb = control_para->fb_enable;
+ EMAC_DMA->bm_bit.usp = control_para->usp_enable;
+ EMAC_DMA->bm_bit.da = control_para->da_enable;
+ EMAC_DMA->bm_bit.pr = control_para->priority_ratio;
+
+ EMAC_DMA->opm_bit.dt = control_para->dt_disable;
+ EMAC_DMA->opm_bit.rsf = control_para->rsf_enable;
+ EMAC_DMA->opm_bit.dfrf = control_para->flush_rx_disable;
+ EMAC_DMA->opm_bit.tsf = control_para->tsf_enable;
+ EMAC_DMA->opm_bit.ttc = control_para->tx_threshold;
+ EMAC_DMA->opm_bit.fef = control_para->fef_enable;
+ EMAC_DMA->opm_bit.fugf = control_para->fugf_enable;
+ EMAC_DMA->opm_bit.rtc = control_para->rx_threshold;
+ EMAC_DMA->opm_bit.osf = control_para->osf_enable;
+}
+
+/**
+ * @brief set rx tx priority
+ * @param ratio: rx tx priority ratio
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_1_RX_1_TX
+ * - EMAC_DMA_2_RX_1_TX
+ * - EMAC_DMA_3_RX_1_TX
+ * - EMAC_DMA_4_RX_1_TX
+ * @param new_state: TRUE or FALSE
+ * @retval none
+ */
+void emac_dma_arbitation_set(emac_dma_rx_tx_ratio_type ratio, confirm_state new_state)
+{
+ EMAC_DMA->bm_bit.da = new_state;
+
+ if(new_state)
+ {
+ EMAC_DMA->bm_bit.pr = ratio;
+ }
+}
+
+/**
+ * @brief set descriptor skip mength
+ * @param length: descriptor skip length
+ * @retval none
+ */
+void emac_dma_descriptor_skip_length_set(uint8_t length)
+{
+ EMAC_DMA->bm_bit.dsl = length;
+}
+
+/**
+ * @brief set programmable burst length
+ * @param tx_length: tx programmable burst length
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_PBL_1
+ * - EMAC_DMA_PBL_2
+ * - EMAC_DMA_PBL_4
+ * - EMAC_DMA_PBL_8
+ * - EMAC_DMA_PBL_16
+ * - EMAC_DMA_PBL_32
+ * @param rx_length: rx programmable burst length
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_PBL_1
+ * - EMAC_DMA_PBL_2
+ * - EMAC_DMA_PBL_4
+ * - EMAC_DMA_PBL_8
+ * - EMAC_DMA_PBL_16
+ * - EMAC_DMA_PBL_32
+ * @param new_state: TRUE or FALSE
+ * @retval none
+ */
+void emac_dma_separate_pbl_set(emac_dma_pbl_type tx_length, emac_dma_pbl_type rx_length, confirm_state new_state)
+{
+ EMAC_DMA->bm_bit.usp = new_state;
+ EMAC_DMA->bm_bit.pbl = tx_length;
+
+ if(new_state)
+ {
+ EMAC_DMA->bm_bit.pbl = rx_length;
+ }
+}
+
+/**
+ * @brief set 8 times programmable burst length
+ * @param new_state: TRUE or FALSE
+ * @retval none
+ */
+void emac_dma_eight_pbl_mode_set(confirm_state new_state)
+{
+ EMAC_DMA->bm_bit.pblx8 = new_state;
+}
+
+/**
+ * @brief set address-aligned beats
+ * @param new_state: TRUE or FALSE
+ * @retval none
+ */
+void emac_dma_address_aligned_beats_set(confirm_state new_state)
+{
+ EMAC_DMA->bm_bit.aab = new_state;
+}
+
+/**
+ * @brief set transmit/receive poll demand
+ * @param transfer_type: it will be transmit or receive
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_TRANSMIT
+ * - EMAC_DMA_RECEIVE
+ * @param value: it can be any number
+ * @retval none
+ */
+void emac_dma_poll_demand_set(emac_dma_tx_rx_type transfer_type, uint32_t value)
+{
+ switch(transfer_type)
+ {
+ case EMAC_DMA_TRANSMIT:
+ {
+ EMAC_DMA->tpd_bit.tpd = value;
+ break;
+ }
+ case EMAC_DMA_RECEIVE:
+ {
+ EMAC_DMA->rpd_bit.rpd = value;
+ break;
+ }
+ }
+}
+
+/**
+ * @brief get transmit poll demand
+ * @param transfer_type: it will be transmit or receive
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_TRANSMIT
+ * - EMAC_DMA_RECEIVE
+ * @retval current transmit descriptor
+ */
+uint32_t emac_dma_poll_demand_get(emac_dma_tx_rx_type transfer_type)
+{
+ switch(transfer_type)
+ {
+ case EMAC_DMA_TRANSMIT:
+ {
+ return (EMAC_DMA->tpd_bit.tpd);
+ }
+ case EMAC_DMA_RECEIVE:
+ {
+ return (EMAC_DMA->rpd_bit.rpd);
+ }
+ }
+ return 0;
+}
+
+/**
+ * @brief get receive dma process status
+ * @param none
+ * @retval every situation it describe in RM
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_RX_RESET_STOP_COMMAND
+ * - EMAC_DMA_RX_FETCH_DESCRIPTOR
+ * - EMAC_DMA_RX_WAITING_PACKET
+ * - EMAC_DMA_RX_DESCRIPTOR_UNAVAILABLE
+ * - EMAC_DMA_RX_CLOSE_DESCRIPTOR
+ * - EMAC_DMA_RX_FIFO_TO_HOST
+ */
+emac_dma_receive_process_status_type emac_dma_receive_status_get(void)
+{
+ switch(EMAC_DMA->sts_bit.rs)
+ {
+ case EMAC_DMA_RX_RESET_STOP_COMMAND:
+ {
+ return EMAC_DMA_RX_RESET_STOP_COMMAND;
+ }
+
+ case EMAC_DMA_RX_FETCH_DESCRIPTOR:
+ {
+ return EMAC_DMA_RX_FETCH_DESCRIPTOR;
+ }
+
+ case EMAC_DMA_RX_WAITING_PACKET:
+ {
+ return EMAC_DMA_RX_WAITING_PACKET;
+ }
+
+ case EMAC_DMA_RX_DESCRIPTOR_UNAVAILABLE:
+ {
+ return EMAC_DMA_RX_DESCRIPTOR_UNAVAILABLE;
+ }
+
+ case EMAC_DMA_RX_CLOSE_DESCRIPTOR:
+ {
+ return EMAC_DMA_RX_CLOSE_DESCRIPTOR;
+ }
+
+ case EMAC_DMA_RX_FIFO_TO_HOST:
+ {
+ return EMAC_DMA_RX_FIFO_TO_HOST;
+ }
+ }
+
+ return EMAC_DMA_RX_RESET_STOP_COMMAND;
+}
+
+/**
+ * @brief get transmit dma process status
+ * @param none
+ * @retval every situation it describe in RM
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_TX_RESET_STOP_COMMAND
+ * - EMAC_DMA_TX_FETCH_DESCRIPTOR
+ * - EMAC_DMA_TX_WAITING_FOR_STATUS
+ * - EMAC_DMA_TX_HOST_TO_FIFO
+ * - EMAC_DMA_TX_DESCRIPTOR_UNAVAILABLE
+ * - EMAC_DMA_TX_CLOSE_DESCRIPTOR
+ */
+emac_dma_transmit_process_status_type emac_dma_transmit_status_get(void)
+{
+ switch(EMAC_DMA->sts_bit.ts)
+ {
+ case EMAC_DMA_TX_RESET_STOP_COMMAND:
+ {
+ return EMAC_DMA_TX_RESET_STOP_COMMAND;
+ }
+
+ case EMAC_DMA_TX_FETCH_DESCRIPTOR:
+ {
+ return EMAC_DMA_TX_FETCH_DESCRIPTOR;
+ }
+
+ case EMAC_DMA_TX_WAITING_FOR_STATUS:
+ {
+ return EMAC_DMA_TX_WAITING_FOR_STATUS;
+ }
+
+ case EMAC_DMA_TX_HOST_TO_FIFO:
+ {
+ return EMAC_DMA_TX_HOST_TO_FIFO;
+ }
+
+ case EMAC_DMA_TX_DESCRIPTOR_UNAVAILABLE:
+ {
+ return EMAC_DMA_TX_DESCRIPTOR_UNAVAILABLE;
+ }
+
+ case EMAC_DMA_TX_CLOSE_DESCRIPTOR:
+ {
+ return EMAC_DMA_TX_CLOSE_DESCRIPTOR;
+ }
+ }
+
+ return EMAC_DMA_TX_RESET_STOP_COMMAND;
+}
+
+/**
+ * @brief set dma operations
+ * @param ops: operations of dma
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_OPS_START_STOP_RECEIVE
+ * - EMAC_DMA_OPS_SECOND_FRAME
+ * - EMAC_DMA_OPS_FORWARD_UNDERSIZED
+ * - EMAC_DMA_OPS_FORWARD_ERROR
+ * - EMAC_DMA_OPS_START_STOP_TRANSMIT
+ * - EMAC_DMA_OPS_FLUSH_TRANSMIT_FIFO
+ * - EMAC_DMA_OPS_TRANSMIT_STORE_FORWARD
+ * - EMAC_DMA_OPS_RECEIVE_FLUSH_DISABLE
+ * - EMAC_DMA_OPS_RECEIVE_STORE_FORWARD
+ * - EMAC_DMA_OPS_DROP_ERROR_DISABLE
+ * @param new_state: TRUE or FALSE
+ * @retval none
+ */
+void emac_dma_operations_set(emac_dma_operations_type ops, confirm_state new_state)
+{
+ __IO uint32_t temp = 0;
+ switch(ops)
+ {
+ case EMAC_DMA_OPS_START_STOP_RECEIVE:
+ {
+ EMAC_DMA->opm_bit.ssr = new_state;
+ break;
+ }
+
+ case EMAC_DMA_OPS_SECOND_FRAME:
+ {
+ EMAC_DMA->opm_bit.osf = new_state;
+ break;
+ }
+
+ case EMAC_DMA_OPS_FORWARD_UNDERSIZED:
+ {
+ EMAC_DMA->opm_bit.fugf = new_state;
+ break;
+ }
+
+ case EMAC_DMA_OPS_FORWARD_ERROR:
+ {
+ EMAC_DMA->opm_bit.fef = new_state;
+ break;
+ }
+
+ case EMAC_DMA_OPS_START_STOP_TRANSMIT:
+ {
+ EMAC_DMA->opm_bit.sstc = new_state;
+ break;
+ }
+
+ case EMAC_DMA_OPS_FLUSH_TRANSMIT_FIFO:
+ {
+ EMAC_DMA->opm_bit.ftf = new_state;
+ temp = EMAC_DMA->opm;
+ emac_delay(1);
+ EMAC_DMA->opm = temp;
+ break;
+ }
+
+ case EMAC_DMA_OPS_TRANSMIT_STORE_FORWARD:
+ {
+ EMAC_DMA->opm_bit.tsf = new_state;
+ break;
+ }
+
+ case EMAC_DMA_OPS_RECEIVE_FLUSH_DISABLE:
+ {
+ EMAC_DMA->opm_bit.dfrf = new_state;
+ break;
+ }
+
+ case EMAC_DMA_OPS_RECEIVE_STORE_FORWARD:
+ {
+ EMAC_DMA->opm_bit.rsf = new_state;
+ break;
+ }
+
+ case EMAC_DMA_OPS_DROP_ERROR_DISABLE:
+ {
+ EMAC_DMA->opm_bit.dt = new_state;
+ break;
+ }
+ }
+}
+
+/**
+ * @brief set receive dma threshold
+ * @param value: receive threshold
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_RX_THRESHOLD_64_BYTES
+ * - EMAC_DMA_RX_THRESHOLD_32_BYTES
+ * - EMAC_DMA_RX_THRESHOLD_96_BYTES
+ * - EMAC_DMA_RX_THRESHOLD_128_BYTES
+ * @retval none
+ */
+void emac_dma_receive_threshold_set(emac_dma_receive_threshold_type value)
+{
+ EMAC_DMA->opm_bit.rtc = value;
+}
+
+/**
+ * @brief set transmit dma threshold
+ * @param value: transmit threshold
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_TX_THRESHOLD_64_BYTES
+ * - EMAC_DMA_TX_THRESHOLD_128_BYTES
+ * - EMAC_DMA_TX_THRESHOLD_192_BYTES
+ * - EMAC_DMA_TX_THRESHOLD_256_BYTES
+ * - EMAC_DMA_TX_THRESHOLD_40_BYTES
+ * - EMAC_DMA_TX_THRESHOLD_32_BYTES
+ * - EMAC_DMA_TX_THRESHOLD_24_BYTES
+ * - EMAC_DMA_TX_THRESHOLD_16_BYTES
+ * @retval none
+ */
+void emac_dma_transmit_threshold_set(emac_dma_transmit_threshold_type value)
+{
+ EMAC_DMA->opm_bit.ttc = value;
+}
+
+/**
+ * @brief enable dma interrupt
+ * @param it: interrupt type
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_INTERRUPT_TX
+ * - EMAC_DMA_INTERRUPT_TX_STOP
+ * - EMAC_DMA_INTERRUPT_TX_UNAVAILABLE
+ * - EMAC_DMA_INTERRUPT_TX_JABBER
+ * - EMAC_DMA_INTERRUPT_RX_OVERFLOW
+ * - EMAC_DMA_INTERRUPT_TX_UNDERFLOW
+ * - EMAC_DMA_INTERRUPT_RX
+ * - EMAC_DMA_INTERRUPT_RX_UNAVAILABLE
+ * - EMAC_DMA_INTERRUPT_RX_STOP
+ * - EMAC_DMA_INTERRUPT_RX_TIMEOUT
+ * - EMAC_DMA_INTERRUPT_TX_EARLY
+ * - EMAC_DMA_INTERRUPT_FATAL_BUS_ERROR
+ * - EMAC_DMA_INTERRUPT_RX_EARLY
+ * - EMAC_DMA_INTERRUPT_ABNORMAL_SUMMARY
+ * - EMAC_DMA_INTERRUPT_NORMAL_SUMMARY
+ * @param new_state: TRUE or FALSE
+ * @retval none
+ */
+void emac_dma_interrupt_enable(emac_dma_interrupt_type it, confirm_state new_state)
+{
+ switch(it)
+ {
+ case EMAC_DMA_INTERRUPT_TX:
+ {
+ EMAC_DMA->ie_bit.tie = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_TX_STOP:
+ {
+ EMAC_DMA->ie_bit.tse = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_TX_UNAVAILABLE:
+ {
+ EMAC_DMA->ie_bit.tue = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_TX_JABBER:
+ {
+ EMAC_DMA->ie_bit.tje = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_RX_OVERFLOW:
+ {
+ EMAC_DMA->ie_bit.ove = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_TX_UNDERFLOW:
+ {
+ EMAC_DMA->ie_bit.une = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_RX:
+ {
+ EMAC_DMA->ie_bit.rie = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_RX_UNAVAILABLE:
+ {
+ EMAC_DMA->ie_bit.rbue = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_RX_STOP:
+ {
+ EMAC_DMA->ie_bit.rse = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_RX_TIMEOUT:
+ {
+ EMAC_DMA->ie_bit.rwte = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_TX_EARLY:
+ {
+ EMAC_DMA->ie_bit.eie = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_FATAL_BUS_ERROR:
+ {
+ EMAC_DMA->ie_bit.fbee = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_RX_EARLY:
+ {
+ EMAC_DMA->ie_bit.ere = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_ABNORMAL_SUMMARY:
+ {
+ EMAC_DMA->ie_bit.aie = new_state;
+ break;
+ }
+ case EMAC_DMA_INTERRUPT_NORMAL_SUMMARY:
+ {
+ EMAC_DMA->ie_bit.nie = new_state;
+ break;
+ }
+ }
+}
+
+/**
+ * @brief get missed frames by the controller
+ * @param none
+ * @retval missed frames by the controller
+ */
+uint16_t emac_dma_controller_missing_frame_get(void)
+{
+ uint16_t number = EMAC_DMA->mfbocnt_bit.mfc;
+ return number;
+}
+
+/**
+ * @brief get overflow bit for missed frame counter
+ * @param none
+ * @retval overflow bit for missed frame counter
+ */
+uint8_t emac_dma_missing_overflow_bit_get(void)
+{
+ uint8_t number = EMAC_DMA->mfbocnt_bit.obmfc;
+ return number;
+}
+
+/**
+ * @brief get missed frames by the application
+ * @param none
+ * @retval missed frames by the application
+ */
+uint16_t emac_dma_application_missing_frame_get(void)
+{
+ uint16_t number = EMAC_DMA->mfbocnt_bit.ofc;
+ return number;
+}
+
+/**
+ * @brief get overflow bit for FIFO overflow counter
+ * @param none
+ * @retval overflow bit for FIFO overflow counter
+ */
+uint8_t emac_dma_fifo_overflow_bit_get(void)
+{
+ uint8_t number = EMAC_DMA->mfbocnt_bit.obfoc;
+ return number;
+}
+
+/**
+ * @brief get overflow bit for FIFO overflow counter
+ * @param transfer type: receive/transmit type
+ * this parameter can be one of the following values:
+ * - EMAC_DMA_TX_DESCRIPTOR
+ * - EMAC_DMA_RX_DESCRIPTOR
+ * - EMAC_DMA_TX_BUFFER
+ * - EMAC_DMA_RX_BUFFER
+ * @retval memory address
+ */
+uint32_t emac_dma_tansfer_address_get(emac_dma_transfer_address_type transfer_type)
+{
+ uint32_t address = 0;
+
+ switch(transfer_type)
+ {
+ case EMAC_DMA_TX_DESCRIPTOR:
+ {
+ address = EMAC_DMA->ctd_bit.htdap;
+ break;
+ }
+ case EMAC_DMA_RX_DESCRIPTOR:
+ {
+ address = EMAC_DMA->crd_bit.hrdap;
+ break;
+ }
+ case EMAC_DMA_TX_BUFFER:
+ {
+ address = EMAC_DMA->ctbaddr_bit.htbap;
+ break;
+ }
+ case EMAC_DMA_RX_BUFFER:
+ {
+ address = EMAC_DMA->crbaddr_bit.hrbap;
+ break;
+ }
+ }
+ return address;
+}
+
+/**
+ * @brief alternate dma descriptor size
+ * @param new_state: TRUE or FALSE
+ * @retval none
+ */
+void emac_dma_alternate_desc_size(confirm_state new_state)
+{
+ EMAC_DMA->bm_bit.atds = new_state;
+}
+
+/**
+ * @brief reset all counter
+ * @param none
+ * @retval none
+ */
+void emac_mmc_counter_reset(void)
+{
+ EMAC_MMC->ctrl_bit.rc = TRUE;
+}
+
+/**
+ * @brief counter stop counting from zero when it reaches maximum
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_mmc_rollover_stop(confirm_state new_state)
+{
+ EMAC_MMC->ctrl_bit.scr = new_state;
+}
+
+/**
+ * @brief enable reset on read
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_mmc_reset_on_read_enable(confirm_state new_state)
+{
+ EMAC_MMC->ctrl_bit.rr = new_state;
+}
+
+/**
+ * @brief freeze mmc counter
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_mmc_counter_freeze(confirm_state new_state)
+{
+ EMAC_MMC->ctrl_bit.fmc = new_state;
+}
+
+/**
+ * @brief interupt status of received frames
+ * @param flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - MMC_RX_CRC_ERROR
+ * - MMC_RX_ALIGN_ERROR
+ * - MMC_RX_GOOD_UNICAST
+ * @retval the new state of usart_flag (SET or RESET).
+ */
+flag_status emac_mmc_received_status_get(uint32_t flag)
+{
+ if(EMAC_MMC->ri & flag)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief interupt status of transmit frames
+ * @param transmit_type: transmit type.
+ * this parameter can be one of the following values:
+ * - MMC_TX_SINGLE_COL
+ * - MMC_TX_MULTIPLE_COL
+ * - MMC_TX_GOOD_FRAMES
+ * @retval the new state of usart_flag (SET or RESET).
+ */
+flag_status emac_mmc_transmit_status_get(uint32_t flag)
+{
+ if(EMAC_MMC->ti & flag)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief mask received mmc interrupt
+ * @param flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - MMC_RX_CRC_ERROR
+ * - MMC_RX_ALIGN_ERROR
+ * - MMC_RX_GOOD_UNICAST
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_mmc_received_interrupt_mask_set(uint32_t flag, confirm_state new_state)
+{
+ switch(flag)
+ {
+ case MMC_RX_CRC_ERROR:
+ {
+ EMAC_MMC->rim_bit.rcefcim = new_state;
+ break;
+ }
+ case MMC_RX_ALIGN_ERROR:
+ {
+ EMAC_MMC->rim_bit.raefacim = new_state;
+ break;
+ }
+ case MMC_RX_GOOD_UNICAST:
+ {
+ EMAC_MMC->rim_bit.rugfcim = new_state;
+ break;
+ }
+ }
+}
+
+/**
+ * @brief mask transmit mmc interrupt
+ * @param transmit_type: transmit type.
+ * this parameter can be one of the following values:
+ * - MMC_TX_SINGLE_COL
+ * - MMC_TX_MULTIPLE_COL
+ * - MMC_TX_GOOD_FRAMES
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_mmc_transmit_interrupt_mask_set(uint32_t flag, confirm_state new_state)
+{
+ switch(flag)
+ {
+ case MMC_TX_SINGLE_COL:
+ {
+ EMAC_MMC->tim_bit.tscgfcim = new_state;
+ break;
+ }
+ case MMC_TX_MULTIPLE_COL:
+ {
+ EMAC_MMC->tim_bit.tmcgfcim = new_state;
+ break;
+ }
+ case MMC_TX_GOOD_FRAMES:
+ {
+ EMAC_MMC->tim_bit.tgfcim = new_state;
+ break;
+ }
+ }
+}
+
+/**
+ * @brief get good frame numbers as single collision occurs.
+ * @param flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - MMC_TX_SINGLE_COL
+ * - MMC_TX_MULTIPLE_COL
+ * - MMC_TX_GOOD_FRAMES
+ * @retval good frames
+ */
+uint32_t emac_mmc_transmit_good_frames_get(uint32_t flag)
+{
+ uint32_t good_frames = MMC_TX_GOOD_FRAMES;
+
+ switch(flag)
+ {
+ case MMC_TX_SINGLE_COL:
+ {
+ good_frames = EMAC_MMC->tfscc_bit.tgfscc;
+ break;
+ }
+ case MMC_TX_MULTIPLE_COL:
+ {
+ good_frames = EMAC_MMC->tfmscc_bit.tgfmscc;
+ break;
+ }
+ case MMC_TX_GOOD_FRAMES:
+ {
+ good_frames = EMAC_MMC->tfcnt_bit.tgfc;
+ break;
+ }
+ }
+ return good_frames;
+}
+
+/**
+ * @brief get good frame numbers as single collision occurs.
+ * @param flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - MMC_RX_CRC_ERROR
+ * - MMC_RX_ALIGN_ERROR
+ * - MMC_RX_GOOD_UNICAST
+ * @retval good frames
+ */
+uint32_t emac_mmc_received_error_frames_get(uint32_t flag)
+{
+ uint32_t error_frames = MMC_RX_GOOD_UNICAST;
+
+ switch(flag)
+ {
+ case MMC_RX_CRC_ERROR:
+ {
+ error_frames = EMAC_MMC->rfcecnt_bit.rfcec;
+ break;
+ }
+ case MMC_RX_ALIGN_ERROR:
+ {
+ error_frames = EMAC_MMC->rfaecnt_bit.rfaec;
+ break;
+ }
+ case MMC_RX_GOOD_UNICAST:
+ {
+ error_frames = EMAC_MMC->rgufcnt_bit.rgufc;
+ break;
+ }
+ }
+ return error_frames;
+}
+
+/**
+ * @brief enable timestamp.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_timestamp_enable(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.te = new_state;
+}
+
+/**
+ * @brief enable timestamp fine update.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_timestamp_fine_update_enable(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.tfcu = new_state;
+}
+
+/**
+ * @brief initialize timestamp time system.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_timestamp_system_time_init(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.ti = new_state;
+}
+
+/**
+ * @brief update timestamp time system.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_timestamp_system_time_update(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.tu = new_state;
+}
+
+/**
+ * @brief enable timestamp interrupt trigger.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_interrupt_trigger_enable(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.tite = new_state;
+}
+
+/**
+ * @brief update timestamp addend register.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_addend_register_update(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.aru = new_state;
+}
+
+/**
+ * @brief enable timestamp snapshot for all received frames.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_snapshot_received_frames_enable(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.etaf = new_state;
+}
+
+/**
+ * @brief enable digital rollover.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_subsecond_rollover_enable(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.tdbrc = new_state;
+}
+
+/**
+ * @brief enable packet snooping for version 2.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_psv2_enable(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.eppv2f = new_state;
+}
+
+/**
+ * @brief enable snapshot over emac.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_snapshot_emac_frames_enable(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.eppef = new_state;
+}
+
+/**
+ * @brief enable snapshot for ipv6 frames.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_snapshot_ipv6_frames_enable(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.eppfsip6u = new_state;
+}
+
+/**
+ * @brief enable snapshot for ipv4 frames.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_snapshot_ipv4_frames_enable(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.eppfsip4u = new_state;
+}
+
+/**
+ * @brief enable snapshot for event message.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_snapshot_event_message_enable(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.etsfem = new_state;
+}
+
+/**
+ * @brief enable snapshot for message relevant to master
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_snapshot_master_event_enable(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.esfmrtm = new_state;
+}
+
+/**
+ * @brief set clock node type
+ * @param node: select ptp packets for taking snapshot
+ * this parameter can be one of the following values:
+ * - EMAC_PTP_NORMAL_CLOCK
+ * - EMAC_PTP_BOUNDARY_CLOCK
+ * - EMAC_PTP_END_TO_END_CLOCK
+ * - EMAC_PTP_PEER_TO_PEER_CLOCK
+ * @retval none
+ */
+void emac_ptp_clock_node_set(emac_ptp_clock_node_type node)
+{
+ EMAC_PTP->tsctrl_bit.sppfts = node;
+}
+
+/**
+ * @brief enable ptp frame filtering mac address
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void emac_ptp_mac_address_filter_enable(confirm_state new_state)
+{
+ EMAC_PTP->tsctrl_bit.emafpff = new_state;
+}
+
+/**
+ * @brief check whether the specified emac ptp flag is set or not.
+ * @param flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - EMAC_PTP_TI_FLAG: time stamp initialized flag
+ * - EMAC_PTP_TU_FLAG: time stamp updtated flag
+ * - EMAC_PTP_ARU_FLAG: transmit data buffer empty flag
+ * @retval the new state of usart_flag (SET or RESET).
+ */
+flag_status emac_ptp_flag_get(uint32_t flag)
+{
+ if(EMAC_PTP->tsctrl & flag)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief set subsecond increment value
+ * @param value: add to subsecond value for every update
+ * @retval none
+ */
+void emac_ptp_subsecond_increment_set(uint8_t value)
+{
+ EMAC_PTP->ssinc_bit.ssiv = value;
+}
+
+/**
+ * @brief get system time second
+ * @param none
+ * @retval system time second
+ */
+uint32_t emac_ptp_system_second_get(void)
+{
+ uint32_t second = EMAC_PTP->tsh_bit.ts;
+ return second;
+}
+
+/**
+ * @brief get system time subsecond
+ * @param none
+ * @retval system time subsecond
+ */
+uint32_t emac_ptp_system_subsecond_get(void)
+{
+ uint32_t subsecond = EMAC_PTP->tsl_bit.tss;
+ return subsecond;
+}
+
+/**
+ * @brief get system time sign
+ * @param none
+ * @retval TRUE or FALSE
+ */
+confirm_state emac_ptp_system_time_sign_get(void)
+{
+ if(EMAC_PTP->tsl_bit.ast)
+ {
+ return TRUE;
+ }
+ else
+ {
+ return FALSE;
+ }
+}
+
+/**
+ * @brief set system time
+ * @param sign: plus or minus
+ * @param second: system time second
+ * @param subsecond: system time subsecond
+ * @retval none
+ */
+void emac_ptp_system_time_set(uint32_t sign, uint32_t second, uint32_t subsecond)
+{
+ EMAC_PTP->tslud_bit.ast = sign ? 1 : 0;
+ EMAC_PTP->tshud_bit.ts = second;
+ EMAC_PTP->tslud_bit.tss = subsecond;
+}
+
+/**
+ * @brief set time stamp addend
+ * @param value: to achieve time synchronization
+ * @retval none
+ */
+void emac_ptp_timestamp_addend_set(uint32_t value)
+{
+ EMAC_PTP->tsad_bit.tar = value;
+}
+
+/**
+ * @brief set target time stamp high
+ * @param value: to set target time second
+ * @retval none
+ */
+void emac_ptp_target_second_set(uint32_t value)
+{
+ EMAC_PTP->tth_bit.ttsr = value;
+}
+
+/**
+ * @brief set target time stamp low
+ * @param value: to set target time nanosecond
+ * @retval none
+ */
+void emac_ptp_target_nanosecond_set(uint32_t value)
+{
+ EMAC_PTP->ttl_bit.ttlr = value;
+}
+
+/**
+ * @brief set target time stamp low
+ * @param status: type of status
+ * this parameter can be one of the following values:
+ * - EMAC_PTP_SECOND_OVERFLOW
+ * - EMAC_PTP_TARGET_TIME_REACH
+ * @retval TRUE or FALSE
+ */
+confirm_state emac_ptp_timestamp_status_get(emac_ptp_timestamp_status_type status)
+{
+ switch(status)
+ {
+ case EMAC_PTP_SECOND_OVERFLOW:
+ {
+ if(EMAC_PTP->tssr_bit.tso)
+ {
+ return TRUE;
+ }
+ else
+ {
+ return FALSE;
+ }
+ }
+ case EMAC_PTP_TARGET_TIME_REACH:
+ {
+ if(EMAC_PTP->tssr_bit.tttr)
+ {
+ return TRUE;
+ }
+ else
+ {
+ return FALSE;
+ }
+ }
+ }
+ return FALSE;
+}
+
+/**
+ * @brief set pps frequency
+ * @param freq: pps frequency
+ * this parameter can be one of the following values:
+ * - EMAC_PTP_PPS_1HZ
+ * - EMAC_PTP_PPS_2HZ
+ * - EMAC_PTP_PPS_4HZ
+ * - EMAC_PTP_PPS_8HZ
+ * - EMAC_PTP_PPS_16HZ
+ * - EMAC_PTP_PPS_32HZ
+ * - EMAC_PTP_PPS_64HZ
+ * - EMAC_PTP_PPS_128HZ
+ * - EMAC_PTP_PPS_256HZ
+ * - EMAC_PTP_PPS_512HZ
+ * - EMAC_PTP_PPS_1024HZ
+ * - EMAC_PTP_PPS_2048HZ
+ * - EMAC_PTP_PPS_4096HZ
+ * - EMAC_PTP_PPS_8192HZ
+ * - EMAC_PTP_PPS_16384HZ
+ * - EMAC_PTP_PPS_32768HZ
+ * @retval none
+ */
+void emac_ptp_pps_frequency_set(emac_ptp_pps_control_type freq)
+{
+ EMAC_PTP->ppscr_bit.pofc = freq;
+}
+
+/**
+ * @brief this is delay function base on system clock.
+ * @param delay: delay time
+ * @retval none
+ */
+static void emac_delay(uint32_t delay)
+{
+ __IO uint32_t delay_time = delay * (system_core_clock / 8 / 1000);
+ do
+ {
+ __NOP();
+ }
+ while(delay_time --);
+}
+
+/**
+ * @brief check whether the specified emac dma flag is set or not.
+ * @param dma_flag: specifies the emac dma flag to check.
+ * this parameter can be one of emac dma flag status:
+ * - EMAC_DMA_TI_FLAG
+ * - EMAC_DMA_TPS_FLAG
+ * - EMAC_DMA_TBU_FLAG
+ * - EMAC_DMA_TJT_FLAG
+ * - EMAC_DMA_OVF_FLAG
+ * - EMAC_DMA_UNF_FLAG
+ * - EMAC_DMA_RI_FLAG
+ * - EMAC_DMA_RBU_FLAG
+ * - EMAC_DMA_RPS_FLAG
+ * - EMAC_DMA_RWT_FLAG
+ * - EMAC_DMA_ETI_FLAG
+ * - EMAC_DMA_FBEI_FLAG
+ * - EMAC_DMA_ERI_FLAG
+ * - EMAC_DMA_AIS_FLAG
+ * - EMAC_DMA_NIS_FLAG
+ * @retval the new state of dma_flag (SET or RESET).
+ */
+flag_status emac_dma_flag_get(uint32_t dma_flag)
+{
+ flag_status status = RESET;
+
+ if(EMAC_DMA->sts & dma_flag)
+ status = SET;
+ /* return the new state (SET or RESET) */
+ return status;
+}
+
+/**
+ * @brief check whether the specified emac dma interrupt flag is set or not.
+ * @param dma_flag: specifies the emac dma flag to check.
+ * this parameter can be one of emac dma flag status:
+ * - EMAC_DMA_TI_FLAG
+ * - EMAC_DMA_TPS_FLAG
+ * - EMAC_DMA_TBU_FLAG
+ * - EMAC_DMA_TJT_FLAG
+ * - EMAC_DMA_OVF_FLAG
+ * - EMAC_DMA_UNF_FLAG
+ * - EMAC_DMA_RI_FLAG
+ * - EMAC_DMA_RBU_FLAG
+ * - EMAC_DMA_RPS_FLAG
+ * - EMAC_DMA_RWT_FLAG
+ * - EMAC_DMA_ETI_FLAG
+ * - EMAC_DMA_FBEI_FLAG
+ * - EMAC_DMA_ERI_FLAG
+ * - EMAC_DMA_AIS_FLAG
+ * - EMAC_DMA_NIS_FLAG
+ * @retval the new state of dma_flag (SET or RESET).
+ */
+flag_status emac_dma_interrupt_flag_get(uint32_t dma_flag)
+{
+ flag_status status = RESET;
+ switch(dma_flag)
+ {
+ case EMAC_DMA_TI_FLAG:
+ case EMAC_DMA_TBU_FLAG:
+ case EMAC_DMA_RI_FLAG:
+ case EMAC_DMA_ERI_FLAG:
+ if((EMAC_DMA->sts & dma_flag) &&
+ (EMAC_DMA->ie & dma_flag) &&
+ (EMAC_DMA->sts & EMAC_DMA_NIS_FLAG))
+ status = SET;
+ break;
+ case EMAC_DMA_TPS_FLAG:
+ case EMAC_DMA_TJT_FLAG:
+ case EMAC_DMA_OVF_FLAG:
+ case EMAC_DMA_UNF_FLAG:
+ case EMAC_DMA_RBU_FLAG:
+ case EMAC_DMA_RPS_FLAG:
+ case EMAC_DMA_RWT_FLAG:
+ case EMAC_DMA_ETI_FLAG:
+ case EMAC_DMA_FBEI_FLAG:
+ if((EMAC_DMA->sts & dma_flag) &&
+ (EMAC_DMA->ie & dma_flag) &&
+ (EMAC_DMA->sts & EMAC_DMA_AIS_FLAG))
+ status = SET;
+ break;
+ default:
+ break;
+ }
+ /* return the new state (SET or RESET) */
+ return status;
+}
+
+/**
+ * @brief clear the emac dma flag.
+ * @param dma_flag: specifies the emac dma flags to clear.
+ * this parameter can be any combination of the following values:
+ * - EMAC_DMA_TI_FLAG
+ * - EMAC_DMA_TPS_FLAG
+ * - EMAC_DMA_TBU_FLAG
+ * - EMAC_DMA_TJT_FLAG
+ * - EMAC_DMA_OVF_FLAG
+ * - EMAC_DMA_UNF_FLAG
+ * - EMAC_DMA_RI_FLAG
+ * - EMAC_DMA_RBU_FLAG
+ * - EMAC_DMA_RPS_FLAG
+ * - EMAC_DMA_RWT_FLAG
+ * - EMAC_DMA_ETI_FLAG
+ * - EMAC_DMA_FBEI_FLAG
+ * - EMAC_DMA_ERI_FLAG
+ * - EMAC_DMA_AIS_FLAG
+ * - EMAC_DMA_NIS_FLAG
+ * @retval none
+ */
+void emac_dma_flag_clear(uint32_t dma_flag)
+{
+ EMAC_DMA->sts = dma_flag;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_ertc.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_ertc.c
new file mode 100644
index 00000000000..398dcf18641
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_ertc.c
@@ -0,0 +1,1601 @@
+/**
+ **************************************************************************
+ * @file at32f45x_ertc.c
+ * @brief contains all the functions for the ertc firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup ERTC
+ * @brief ERTC driver modules
+ * @{
+ */
+
+#ifdef ERTC_MODULE_ENABLED
+
+/** @defgroup ERTC_private_functions
+ * @{
+ */
+
+#define ERTC_TIMEOUT ((uint32_t) 0x00360000)
+
+/**
+ * @brief number conversion to bcd code.
+ * @param num: number(0~99)
+ * @retval bcd code.
+ */
+uint8_t ertc_num_to_bcd(uint8_t num)
+{
+ uint8_t bcd_h = 0, bcd_l = 0;
+
+ bcd_h = num / 10;
+ bcd_l = num % 10;
+
+ return ((uint8_t)(bcd_h << 4) | bcd_l);
+}
+
+/**
+ * @brief bcd code conversion to number.
+ * @param bcd: bcd code(0~99).
+ * @retval number.
+ */
+uint8_t ertc_bcd_to_num(uint8_t bcd)
+{
+ return ((((uint8_t)(bcd & (uint8_t)0xF0) >> 4) * 10) + (bcd & (uint8_t)0x0F));
+}
+
+/**
+ * @brief enable write protection.
+ * @param none.
+ * @retval none
+ */
+void ertc_write_protect_enable(void)
+{
+ ERTC->wp = 0xFF;
+}
+
+/**
+ * @brief disable write protection.
+ * @param none.
+ * @retval none
+ */
+void ertc_write_protect_disable(void)
+{
+ ERTC->wp = 0xCA;
+ ERTC->wp = 0x53;
+}
+
+/**
+ * @brief ertc wait register update finish.
+ * @param none.
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_wait_update(void)
+{
+ uint32_t timeout = ERTC_TIMEOUT * 2;
+
+ /* clear updf flag */
+ ERTC->sts = ~(ERTC_UPDF_FLAG | 0x00000080) | (ERTC->sts_bit.imen << 7);
+
+ while(ERTC->sts_bit.updf == 0)
+ {
+ if(timeout == 0)
+ {
+ return ERROR;
+ }
+
+ timeout--;
+ }
+
+ return SUCCESS;
+}
+
+/**
+ * @brief ertc wait flag status.
+ * @param flag: flag to wait.
+ * this parameter can be one of the following values:
+ * - ERTC_ALAWF_FLAG: alarm a register allows write flag.
+ * - ERTC_ALBWF_FLAG: alarm b register allows write flag.
+ * - ERTC_WATWF_FLAG: wakeup timer register allows write flag.
+ * - ERTC_TADJF_FLAG: time adjustment flag.
+ * - ERTC_CALUPDF_FLAG: calibration value update completed flag.
+ * @param status: status to wait.
+ * this parameter can be one of the following values:
+ * - SET.
+ * - RESET.
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_wait_flag(uint32_t flag, flag_status status)
+{
+ uint32_t timeout = ERTC_TIMEOUT;
+
+ while(ertc_flag_get(flag) == status)
+ {
+ if(timeout == 0)
+ {
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return ERROR;
+ }
+
+ timeout--;
+ }
+
+ return SUCCESS;
+}
+
+/**
+ * @brief ertc enter init mode.
+ * @param none.
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_init_mode_enter(void)
+{
+ uint32_t timeout = ERTC_TIMEOUT * 2;
+
+ if(ERTC->sts_bit.imf == 0)
+ {
+ /* enter init mode */
+ ERTC->sts = 0xFFFFFFFF;
+
+ while(ERTC->sts_bit.imf == 0)
+ {
+ if(timeout == 0)
+ {
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return ERROR;
+ }
+
+ timeout--;
+ }
+ }
+
+ return SUCCESS;
+}
+
+/**
+ * @brief ertc exit init mode.
+ * @param none.
+ * @retval none.
+ */
+void ertc_init_mode_exit(void)
+{
+ ERTC->sts = 0xFFFFFF7F;
+}
+
+/**
+ * @brief ertc reset all register.
+ * @param none.
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_reset(void)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->ctrl = (uint32_t)0x00000000;
+
+ /* enter init mode */
+ if(ertc_init_mode_enter() != SUCCESS)
+ {
+ return ERROR;
+ }
+
+ /* reset register */
+ ERTC->time = (uint32_t)0x00000000;
+ ERTC->date = (uint32_t)0x00002101;
+ ERTC->ctrl = (uint32_t)0x00000000;
+ ERTC->div = (uint32_t)0x007F00FF;
+ ERTC->wat = (uint32_t)0x0000FFFF;
+ ERTC->ccal = (uint32_t)0x00000000;
+ ERTC->ala = (uint32_t)0x00000000;
+ ERTC->alb = (uint32_t)0x00000000;
+ ERTC->tadj = (uint32_t)0x00000000;
+ ERTC->scal = (uint32_t)0x00000000;
+ ERTC->tamp = (uint32_t)0x00000000;
+ ERTC->alasbs = (uint32_t)0x00000000;
+ ERTC->albsbs = (uint32_t)0x00000000;
+ ERTC->sts = (uint32_t)0x00000000;
+
+ /* wait calendar update */
+ ertc_wait_update();
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return SUCCESS;
+}
+
+/**
+ * @brief ertc division set.
+ * @param div_a: division a (0~0x7F).
+ * @param div_b: division b (0~0x7FFF).
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_divider_set(uint16_t div_a, uint16_t div_b)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ /* enter init mode */
+ if(ertc_init_mode_enter() != SUCCESS)
+ {
+ return ERROR;
+ }
+
+ /* config the ertc divider */
+ ERTC->div_bit.diva = div_a;
+ ERTC->div_bit.divb = div_b;
+
+ /* exit init mode */
+ ertc_init_mode_exit();
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return SUCCESS;
+}
+
+/**
+ * @brief ertc hour mode set.
+ * @param mode: hour mode.
+ * this parameter can be one of the following values:
+ * - ERTC_HOUR_MODE_24: 24-hour format.
+ * - ERTC_HOUR_MODE_12: 12-hour format.
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_hour_mode_set(ertc_hour_mode_set_type mode)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ /* enter init mode */
+ if(ertc_init_mode_enter() != SUCCESS)
+ {
+ return ERROR;
+ }
+
+ /* write register */
+ ERTC->ctrl_bit.hm = mode;
+
+ /* exit init mode */
+ ertc_init_mode_exit();
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return SUCCESS;
+}
+
+/**
+ * @brief set date.
+ * @param year: year (0~99).
+ * @param month: month (1~12).
+ * @param date: date (1~31).
+ * @param week: week (1~7).
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_date_set(uint8_t year, uint8_t month, uint8_t date, uint8_t week)
+{
+ ertc_reg_date_type reg;
+
+ reg.date = 0;
+
+ reg.date_bit.y = ertc_num_to_bcd(year);
+ reg.date_bit.m = ertc_num_to_bcd(month);
+ reg.date_bit.d = ertc_num_to_bcd(date);
+ reg.date_bit.wk = week;
+
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ /* enter init mode */
+ if(ertc_init_mode_enter() != SUCCESS)
+ {
+ return ERROR;
+ }
+
+ /* set the ertc_date register */
+ ERTC->date = reg.date;
+
+ /* exit init mode */
+ ertc_init_mode_exit();
+
+ if(ERTC->ctrl_bit.dren == 0)
+ {
+ ertc_wait_update();
+ }
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return SUCCESS;
+}
+
+/**
+ * @brief set time.
+ * @param hour: hour (0~23).
+ * @param min: minute (0~59).
+ * @param sec: second (0~59).
+ * @param ampm: hour mode.
+ * this parameter can be one of the following values:
+ * - ERTC_24H: 24-hour format.
+ * - ERTC_AM: 12-hour format, ante meridiem.
+ * - ERTC_PM: 12-hour format, post meridiem.
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_time_set(uint8_t hour, uint8_t min, uint8_t sec, ertc_am_pm_type ampm)
+{
+ ertc_reg_time_type reg;
+
+ reg.time = 0;
+
+ reg.time_bit.h = ertc_num_to_bcd(hour);
+ reg.time_bit.m = ertc_num_to_bcd(min);
+ reg.time_bit.s = ertc_num_to_bcd(sec);
+ reg.time_bit.ampm = ampm;
+
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ /* enter init mode */
+ if(ertc_init_mode_enter() != SUCCESS)
+ {
+ return ERROR;
+ }
+
+ ERTC->time = reg.time;
+
+ /* exit init mode */
+ ertc_init_mode_exit();
+
+ if(ERTC->ctrl_bit.dren == 0)
+ {
+ ertc_wait_update();
+ }
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return SUCCESS;
+}
+
+/**
+ * @brief get calendar
+ * @param time: ertc time.
+ * @retval none.
+ */
+void ertc_calendar_get(ertc_time_type* time)
+{
+ ertc_reg_time_type reg_tm;
+ ertc_reg_date_type reg_dt;
+
+ reg_tm.time = ERTC->time;
+ reg_dt.date = ERTC->date;
+
+ time->hour = ertc_bcd_to_num(reg_tm.time_bit.h);
+ time->min = ertc_bcd_to_num(reg_tm.time_bit.m);
+ time->sec = ertc_bcd_to_num(reg_tm.time_bit.s);
+ time->ampm = (ertc_am_pm_type)reg_tm.time_bit.ampm;
+
+ time->year = ertc_bcd_to_num(reg_dt.date_bit.y);
+ time->month = ertc_bcd_to_num(reg_dt.date_bit.m);
+ time->day = ertc_bcd_to_num(reg_dt.date_bit.d);
+ time->week = reg_dt.date_bit.wk;
+}
+
+/**
+ * @brief get current sub second.
+ * @param none.
+ * @retval sub second.
+ */
+uint32_t ertc_sub_second_get(void)
+{
+ uint32_t reg = 0;
+
+ reg = ERTC->sbs;
+
+ (void) (ERTC->date);
+
+ return (reg);
+}
+
+/**
+ * @brief set which bits are irrelevant to the alarm match.
+ * @param alarm_x: select the alarm.
+ * this parameter can be one of the following values:
+ * - ERTC_ALA: alarm a.
+ * - ERTC_ALB: alarm b.
+ * @param mask: select which bits are irrelevant to the alarm match.
+ * this parameter can be one of the following values:
+ * - ERTC_ALARM_MASK_NONE: match all.
+ * - ERTC_ALARM_MASK_SEC: don't match seconds.
+ * - ERTC_ALARM_MASK_MIN: don't match minute.
+ * - ERTC_ALARM_MASK_HOUR: don't match hour.
+ * - ERTC_ALARM_MASK_DATE_WEEK: don't match date or week.
+ * - ERTC_ALARM_MASK_ALL: don't match all.
+ * @param alarm: alarm para.
+ * @retval none.
+ */
+void ertc_alarm_mask_set(ertc_alarm_type alarm_x, uint32_t mask)
+{
+ uint32_t reg;
+
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ if(alarm_x == ERTC_ALA)
+ {
+ reg = ERTC->ala;
+
+ reg &= ~ERTC_ALARM_MASK_ALL;
+ reg |= mask;
+
+ ERTC->ala= reg;
+ }
+ else
+ {
+ reg = ERTC->alb;
+
+ reg &= ~ERTC_ALARM_MASK_ALL;
+ reg |= mask;
+
+ ERTC->alb= reg;
+ }
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief alarm week or date mode select.
+ * @param alarm_x: select the alarm.
+ * this parameter can be one of the following values:
+ * - ERTC_ALA: alarm a.
+ * - ERTC_ALB: alarm b.
+ * @param wk: week or date mode select.
+ * this parameter can be one of the following values:
+ * - ERTC_SLECT_DATE: slect date mode.
+ * - ERTC_SLECT_WEEK: slect week mode.
+ * @retval none.
+ */
+void ertc_alarm_week_date_select(ertc_alarm_type alarm_x, ertc_week_date_select_type wk)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ if(alarm_x == ERTC_ALA)
+ {
+ ERTC->ala_bit.wksel = wk;
+ }
+ else
+ {
+ ERTC->alb_bit.wksel = wk;
+ }
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief set alarm.
+ * @param alarm_x: select the alarm.
+ * this parameter can be one of the following values:
+ * - ERTC_ALA: alarm a.
+ * - ERTC_ALB: alarm b.
+ * @param week_day: week or date.
+ * - week: 1~7.
+ * - date: 1~31.
+ * @param hour: hour (0~23).
+ * @param min: minute (0~59).
+ * @param sec: second (0~59).
+ * @param ampm: hour mode.
+ * this parameter can be one of the following values:
+ * - ERTC_24H: 24-hour format.
+ * - ERTC_AM: 12-hour format, ante meridiem.
+ * - ERTC_PM: 12-hour format, post meridiem.
+ * @param alarm: alarm para.
+ * @retval none.
+ */
+void ertc_alarm_set(ertc_alarm_type alarm_x, uint8_t week_date, uint8_t hour, uint8_t min, uint8_t sec, ertc_am_pm_type ampm)
+{
+ ertc_reg_alarm_type reg;
+
+ if(alarm_x == ERTC_ALA)
+ {
+ reg.ala = ERTC->ala;
+ }
+ else
+ {
+ reg.ala = ERTC->alb;
+ }
+
+ reg.ala_bit.d = ertc_num_to_bcd(week_date);
+ reg.ala_bit.h = ertc_num_to_bcd(hour);
+ reg.ala_bit.m = ertc_num_to_bcd(min);
+ reg.ala_bit.s = ertc_num_to_bcd(sec);
+ reg.ala_bit.ampm = ampm;
+
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ if(alarm_x == ERTC_ALA)
+ {
+ ERTC->ala= reg.ala;
+ }
+ else
+ {
+ ERTC->alb = reg.ala;
+ }
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief set alarm sub second.
+ * @param alarm_x: select the alarm.
+ * this parameter can be one of the following values:
+ * - ERTC_ALA: alarm a.
+ * - ERTC_ALB: alarm b.
+ * @param value: sub second value.
+ * @param mask: sub second mask.
+ * this parameter can be one of the following values:
+ * - ERTC_ALARM_SBS_MASK_ALL: do not match the sub-second.
+ * - ERTC_ALARM_SBS_MASK_14_1: only compare bit [0].
+ * - ERTC_ALARM_SBS_MASK_14_2: only compare bit [1:0].
+ * - ERTC_ALARM_SBS_MASK_14_3: only compare bit [2:0].
+ * - ERTC_ALARM_SBS_MASK_14_4: only compare bit [3:0].
+ * - ERTC_ALARM_SBS_MASK_14_5: only compare bit [4:0].
+ * - ERTC_ALARM_SBS_MASK_14_6: only compare bit [5:0].
+ * - ERTC_ALARM_SBS_MASK_14_7: only compare bit [6:0].
+ * - ERTC_ALARM_SBS_MASK_14_8: only compare bit [7:0].
+ * - ERTC_ALARM_SBS_MASK_14_9: only compare bit [8:0].
+ * - ERTC_ALARM_SBS_MASK_14_10: only compare bit [9:0].
+ * - ERTC_ALARM_SBS_MASK_14_11: only compare bit [10:0].
+ * - ERTC_ALARM_SBS_MASK_14_12: only compare bit [11:0].
+ * - ERTC_ALARM_SBS_MASK_14_13: only compare bit [12:0].
+ * - ERTC_ALARM_SBS_MASK_14: only compare bit [13:0].
+ * - ERTC_ALARM_SBS_MASK_NONE: compare bit [14:0].
+ * @retval none.
+ */
+void ertc_alarm_sub_second_set(ertc_alarm_type alarm_x, uint32_t value, ertc_alarm_sbs_mask_type mask)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ if(alarm_x == ERTC_ALA)
+ {
+ ERTC->alasbs_bit.sbsmsk = mask;
+ ERTC->alasbs_bit.sbs = value;
+ }
+ else
+ {
+ ERTC->albsbs_bit.sbsmsk = mask;
+ ERTC->albsbs_bit.sbs = value;
+ }
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief enable or disable alarm clock.
+ * @param alarm_x: select the alarm.
+ * this parameter can be one of the following values:
+ * - ERTC_ALA: alarm a.
+ * - ERTC_ALB: alarm b.
+ * @param new_state (TRUE or FALSE).
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_alarm_enable(ertc_alarm_type alarm_x, confirm_state new_state)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ if(alarm_x == ERTC_ALA)
+ {
+ ERTC->ctrl_bit.alaen = new_state;
+
+ if(new_state == FALSE)
+ {
+ if(ertc_wait_flag(ERTC_ALAWF_FLAG, RESET) != SUCCESS)
+ {
+ return ERROR;
+ }
+ }
+ }
+ else
+ {
+ ERTC->ctrl_bit.alben = new_state;
+
+ if(new_state == FALSE)
+ {
+ if(ertc_wait_flag(ERTC_ALBWF_FLAG, RESET) != SUCCESS)
+ {
+ return ERROR;
+ }
+ }
+ }
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return SUCCESS;
+}
+
+/**
+ * @brief get alarm value.
+ * @param alarm_x: select the alarm.
+ * this parameter can be one of the following values:
+ * - ERTC_ALA: alarm a.
+ * - ERTC_ALB: alarm b.
+ * @param alarm: alarm para.
+ * @retval none.
+ */
+void ertc_alarm_get(ertc_alarm_type alarm_x, ertc_alarm_value_type* alarm)
+{
+ ertc_reg_alarm_type reg;
+
+ reg.ala = 0;
+
+ if(alarm_x == ERTC_ALA)
+ {
+ reg.ala = ERTC->ala;
+ }
+ else
+ {
+ reg.ala = ERTC->alb;
+ }
+
+ alarm->day = ertc_bcd_to_num(reg.ala_bit.d);
+ alarm->week = ertc_bcd_to_num(reg.ala_bit.d);
+ alarm->hour = ertc_bcd_to_num(reg.ala_bit.h);
+ alarm->min = ertc_bcd_to_num(reg.ala_bit.m);
+ alarm->sec = ertc_bcd_to_num(reg.ala_bit.s);
+ alarm->ampm = (ertc_am_pm_type)reg.ala_bit.ampm;
+ alarm->week_date_sel = reg.ala_bit.wksel;
+ alarm->mask = reg.ala & ERTC_ALARM_MASK_ALL;
+}
+
+/**
+ * @brief get alarm sub second.
+ * @param alarm_x: select the alarm.
+ * this parameter can be one of the following values:
+ * - ERTC_ALA: alarm a.
+ * - ERTC_ALB: alarm b.
+ * @retval sub second.
+ */
+uint32_t ertc_alarm_sub_second_get(ertc_alarm_type alarm_x)
+{
+ if(alarm_x == ERTC_ALA)
+ {
+ return (ERTC->alasbs_bit.sbs);
+ }
+ else
+ {
+ return (ERTC->albsbs_bit.sbs);
+ }
+}
+
+/**
+ * @brief set wakeup timer clock.
+ * @param clock: wakeup timer clock source.
+ * this parameter can be one of the following values:
+ * - ERTC_WAT_CLK_ERTCCLK_DIV16: ERTC_CLK / 16.
+ * - ERTC_WAT_CLK_ERTCCLK_DIV8: ERTC_CLK / 8.
+ * - ERTC_WAT_CLK_ERTCCLK_DIV4: ERTC_CLK / 4.
+ * - ERTC_WAT_CLK_ERTCCLK_DIV2: ERTC_CLK / 2.
+ * - ERTC_WAT_CLK_CK_B_16BITS: CK_B, wakeup counter = ERTC_WAT
+ * - ERTC_WAT_CLK_CK_B_17BITS: CK_B, wakeup counter = ERTC_WAT + 65535.
+ * @retval none.
+ */
+void ertc_wakeup_clock_set(ertc_wakeup_clock_type clock)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->ctrl_bit.watclk = clock;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief set wakeup counter.
+ * @param counter: wakeup counter(0~65535).
+ * @retval none.
+ */
+void ertc_wakeup_counter_set(uint32_t counter)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->wat_bit.val = counter;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief get wakeup counter.
+ * @param none.
+ * @retval wakeup counter.
+ */
+uint16_t ertc_wakeup_counter_get(void)
+{
+ return ERTC->wat_bit.val;
+}
+
+/**
+ * @brief enable or disable wakeup timer.
+ * @param new_state (TRUE or FALSE).
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_wakeup_enable(confirm_state new_state)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->ctrl_bit.waten = new_state;
+
+ if(new_state == FALSE)
+ {
+ if(ertc_wait_flag(ERTC_WATWF_FLAG, RESET) != SUCCESS)
+ {
+ return ERROR;
+ }
+ }
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return SUCCESS;
+}
+
+/**
+ * @brief config the smooth calibration.
+ * @param period: calibration period.
+ * this parameter can be one of the following values:
+ * - ERTC_SMOOTH_CAL_PERIOD_32: 32 second calibration period.
+ * - ERTC_SMOOTH_CAL_PERIOD_16: 16 second calibration period.
+ * - ERTC_SMOOTH_CAL_PERIOD_8: 8 second calibration period.
+ * @param clk_add: add clock.
+ * this parameter can be one of the following values:
+ * - ERTC_SMOOTH_CAL_CLK_ADD_0: do not increase clock.
+ * - ERTC_SMOOTH_CAL_CLK_ADD_512: add 512 clocks.
+ * @param clk_dec: decrease clock(0~511).
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_smooth_calibration_config(ertc_smooth_cal_period_type period, ertc_smooth_cal_clk_add_type clk_add, uint32_t clk_dec)
+{
+ ertc_reg_scal_type reg;
+
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ if(ertc_wait_flag(ERTC_CALUPDF_FLAG, SET) != SUCCESS)
+ {
+ return ERROR;
+ }
+
+ reg.scal = 0;
+
+ switch (period)
+ {
+ case ERTC_SMOOTH_CAL_PERIOD_32:
+ break;
+ case ERTC_SMOOTH_CAL_PERIOD_16:
+ reg.scal_bit.cal16 = 1;
+ break;
+ case ERTC_SMOOTH_CAL_PERIOD_8:
+ reg.scal_bit.cal8 = 1;
+ break;
+ default:
+ break;
+ }
+
+ reg.scal_bit.add = clk_add;
+ reg.scal_bit.dec = clk_dec;
+
+ ERTC->scal = reg.scal;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return SUCCESS;
+}
+
+/**
+ * @brief set the coarse digital calibration.
+ * @param dir: calibration direction.
+ * this parameter can be one of the following values:
+ * - ERTC_CAL_DIR_POSITIVE: positive calibration.
+ * - ERTC_CAL_DIR_NEGATIVE: negative calibration.
+ * @param value: calibration value(0~31).
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_coarse_calibration_set(ertc_cal_direction_type dir, uint32_t value)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ /* enter init mode */
+ if(ertc_init_mode_enter() == ERROR)
+ {
+ return ERROR;
+ }
+
+ ERTC->ccal_bit.caldir = dir;
+
+ ERTC->ccal_bit.calval = value;
+
+ /* exit init mode */
+ ertc_init_mode_exit();
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return SUCCESS;
+}
+
+/**
+ * @brief enable or disable coarse calibration.
+ * @param new_state (TRUE or FALSE).
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_coarse_calibration_enable(confirm_state new_state)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ /* enter init mode */
+ if(ertc_init_mode_enter() == ERROR)
+ {
+ return ERROR;
+ }
+
+ ERTC->ctrl_bit.ccalen = new_state;
+
+ /* exit init mode */
+ ertc_init_mode_exit();
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return SUCCESS;
+}
+
+/**
+ * @brief calibration output source select.
+ * @param output: output source.
+ * this parameter can be one of the following values:
+ * - ERTC_CAL_OUTPUT_512HZ: output 512 hz.
+ * - ERTC_CAL_OUTPUT_1HZ: output 1 hz.
+ * @retval none.
+ */
+void ertc_cal_output_select(ertc_cal_output_select_type output)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->ctrl_bit.calosel = output;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief enable or disable calibration output.
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void ertc_cal_output_enable(confirm_state new_state)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->ctrl_bit.caloen = new_state;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief adjust the time.
+ * @param add1s: second operation.
+ * this parameter can be one of the following values:
+ * - ERTC_TIME_ADD_NONE: none operation.
+ * - ERTC_TIME_ADD_1S: add 1 second.
+ * @param decsbs: decrease sub second(0~0x7FFF).
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_time_adjust(ertc_time_adjust_type add1s, uint32_t decsbs)
+{
+ ertc_reg_tadj_type reg;
+
+ reg.tadj = 0;
+
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ if(ertc_wait_flag(ERTC_TADJF_FLAG, SET) != SUCCESS)
+ {
+ return ERROR;
+ }
+
+ /* check if the reference clock detection is disabled */
+ if(ERTC->ctrl_bit.rcden == 0)
+ {
+ reg.tadj_bit.add1s = add1s;
+ reg.tadj_bit.decsbs = decsbs;
+
+ ERTC->tadj = reg.tadj;
+
+ if(ertc_wait_update() == ERROR)
+ {
+ return ERROR;
+ }
+ }
+ else
+ {
+ return ERROR;
+ }
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return SUCCESS;
+}
+
+/**
+ * @brief config the daylight saving time.
+ * @param operation: time adjust.
+ * this parameter can be one of the following values:
+ * - ERTC_DST_ADD_1H: add 1 hour.
+ * - ERTC_DST_DEC_1H: dec 1 hour.
+ * @param save: operation save.
+ * this parameter can be one of the following values:
+ * - ERTC_DST_SAVE_0: set the bpr register value to 0.
+ * - ERTC_DST_SAVE_1: set the bpr register value to 1.
+ * @retval none.
+ */
+void ertc_daylight_set(ertc_dst_operation_type operation, ertc_dst_save_type save)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ if(operation == ERTC_DST_ADD_1H)
+ {
+ ERTC->ctrl_bit.add1h = 1;
+ }
+ else
+ {
+ ERTC->ctrl_bit.dec1h = 1;
+ }
+
+ ERTC->ctrl_bit.bpr = save;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief get the bpr value.
+ * @param none.
+ * @retval bpr value.
+ */
+uint8_t ertc_daylight_bpr_get(void)
+{
+ return ERTC->ctrl_bit.bpr;
+}
+
+/**
+ * @brief enable or disable refer clock detect.
+ * @param new_state (TRUE or FALSE).
+ * @retval error_status (ERROR or SUCCESS).
+ */
+error_status ertc_refer_clock_detect_enable(confirm_state new_state)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ /* enter init mode */
+ if(ertc_init_mode_enter() != SUCCESS)
+ {
+ return ERROR;
+ }
+
+ /* write register */
+ ERTC->ctrl_bit.rcden = new_state;
+
+ /* exit init mode */
+ ertc_init_mode_exit();
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+
+ return SUCCESS;
+}
+
+/**
+ * @brief enable or disable direct read mode.
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void ertc_direct_read_enable(confirm_state new_state)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->ctrl_bit.dren = new_state;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief set the output mode.
+ * @param source: output source.
+ * this parameter can be one of the following values:
+ * - ERTC_OUTPUT_DISABLE: diable output.
+ * - ERTC_OUTPUT_ALARM_A: output alarm a event.
+ * - ERTC_OUTPUT_ALARM_B: output alarm b event.
+ * - ERTC_OUTPUT_WAKEUP: output wakeup event.
+ * @param polarity: output polarity.
+ * this parameter can be one of the following values:
+ * - ERTC_OUTPUT_POLARITY_HIGH: when the event occurs, the output is high.
+ * - ERTC_OUTPUT_POLARITY_LOW: when the event occurs, the output is low.
+ * @param type: output type.
+ * this parameter can be one of the following values:
+ * - ERTC_OUTPUT_TYPE_OPEN_DRAIN: open drain output.
+ * - ERTC_OUTPUT_TYPE_PUSH_PULL: push pull output.
+ * @retval none.
+ */
+void ertc_output_set(ertc_output_source_type source, ertc_output_polarity_type polarity, ertc_output_type type)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->ctrl_bit.outp = polarity;
+
+ ERTC->tamp_bit.outtype = type;
+
+ ERTC->ctrl_bit.outsel = source;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief timestamp detection pin selection.
+ * @param pin: data register
+ * this parameter can be one of the following values:
+ * - ERTC_PIN_PC13: pc13 is used as timestamp detection pin.
+ * - ERTC_PIN_PA0: pa0 is used as timestamp detection pin.
+ * @retval data value.
+ */
+void ertc_timestamp_pin_select(ertc_pin_select_type pin)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->tamp_bit.tspin = pin;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief set the timestamp valid edge.
+ * @param edge: calibration period.
+ * this parameter can be one of the following values:
+ * - ERTC_TIMESTAMP_EDGE_RISING : rising edge trigger.
+ * - ERTC_TIMESTAMP_EDGE_FALLING: falling edge trigger.
+ * @retval none.
+ */
+void ertc_timestamp_valid_edge_set(ertc_timestamp_valid_edge_type edge)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->ctrl_bit.tsedg = edge;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief enable or disable timestamp.
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void ertc_timestamp_enable(confirm_state new_state)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->ctrl_bit.tsen = new_state;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief get the timestamp.
+ * @param time: time.
+ * @param date: date.
+ * @retval none.
+ */
+void ertc_timestamp_get(ertc_time_type* time)
+{
+ ertc_reg_tstm_type tmtime;
+ ertc_reg_tsdt_type tmdate;
+
+ tmtime.tstm = ERTC->tstm;
+ tmdate.tsdt = ERTC->tsdt;
+
+ time->year = 0;
+ time->month = ertc_bcd_to_num(tmdate.tsdt_bit.m);
+ time->day = ertc_bcd_to_num(tmdate.tsdt_bit.d);
+ time->week = ertc_bcd_to_num(tmdate.tsdt_bit.wk);
+ time->hour = ertc_bcd_to_num(tmtime.tstm_bit.h);
+ time->min = ertc_bcd_to_num(tmtime.tstm_bit.m);
+ time->sec = ertc_bcd_to_num(tmtime.tstm_bit.s);
+ time->ampm = (ertc_am_pm_type)tmtime.tstm_bit.ampm;
+}
+
+/**
+ * @brief get the timestamp sub second.
+ * @param none.
+ * @retval timestamp sub second.
+ */
+uint32_t ertc_timestamp_sub_second_get(void)
+{
+ return ERTC->tssbs_bit.sbs;
+}
+
+/**
+ * @brief tamper 1 detection pin selection.
+ * @param pin: data register
+ * this parameter can be one of the following values:
+ * - ERTC_PIN_PC13: pc13 is used as tamper 1 detection pin.
+ * - ERTC_PIN_PA0: pa0 is used as tamper 1 detection pin.
+ * @retval data value.
+ */
+void ertc_tamper_1_pin_select(ertc_pin_select_type pin)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->tamp_bit.tp1pin = pin;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief enable or disable tamper pin pull up.
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void ertc_tamper_pull_up_enable(confirm_state new_state)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->tamp_bit.tppu = !new_state;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief set the tamper pin pre-charge time.
+ * @param precharge: tamper detection pre-charge time
+ * this parameter can be one of the following values:
+ * - ERTC_TAMPER_PR_1_ERTCCLK: pre-charge time is 1 ERTC_CLK.
+ * - ERTC_TAMPER_PR_2_ERTCCLK: pre-charge time is 2 ERTC_CLK.
+ * - ERTC_TAMPER_PR_4_ERTCCLK: pre-charge time is 4 ERTC_CLK.
+ * - ERTC_TAMPER_PR_8_ERTCCLK: pre-charge time is 8 ERTC_CLK.
+ * @retval none.
+ */
+void ertc_tamper_precharge_set(ertc_tamper_precharge_type precharge)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->tamp_bit.tppr = precharge;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief set the tamper filter time.
+ * @param filter: tamper filter.
+ * this parameter can be one of the following values:
+ * - ERTC_TAMPER_FILTER_DISABLE: disable filter function.
+ * - ERTC_TAMPER_FILTER_2: 2 consecutive samples arw valid, effective tamper event.
+ * - ERTC_TAMPER_FILTER_4: 4 consecutive samples arw valid, effective tamper event.
+ * - ERTC_TAMPER_FILTER_8: 8 consecutive samples arw valid, effective tamper event.
+ * @retval none.
+ */
+void ertc_tamper_filter_set(ertc_tamper_filter_type filter)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->tamp_bit.tpflt = filter;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief set the tamper detection frequency.
+ * @param freq: tamper detection frequency.
+ * this parameter can be one of the following values:
+ * - ERTC_TAMPER_FREQ_DIV_32768: ERTC_CLK / 32768.
+ * - ERTC_TAMPER_FREQ_DIV_16384: ERTC_CLK / 16384.
+ * - ERTC_TAMPER_FREQ_DIV_8192: ERTC_CLK / 8192.
+ * - ERTC_TAMPER_FREQ_DIV_4096: ERTC_CLK / 4096.
+ * - ERTC_TAMPER_FREQ_DIV_2048: ERTC_CLK / 2048.
+ * - ERTC_TAMPER_FREQ_DIV_1024: ERTC_CLK / 1024.
+ * - ERTC_TAMPER_FREQ_DIV_512: ERTC_CLK / 512.
+ * - ERTC_TAMPER_FREQ_DIV_256: ERTC_CLK / 256.
+ * @retval none.
+ */
+void ertc_tamper_detect_freq_set(ertc_tamper_detect_freq_type freq)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->tamp_bit.tpfreq = freq;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief set the tamper trigger.
+ * @param tamper_x: select the tamper.
+ * this parameter can be one of the following values:
+ * - ERTC_TAMPER_1: tamper 1.
+ * - ERTC_TAMPER_2: tamper 2.
+ * @param trigger: tamper valid edge.
+ * this parameter can be one of the following values:
+ * - ERTC_TAMPER_EDGE_RISING: rising gedge.
+ * - ERTC_TAMPER_EDGE_FALLING: falling gedge.
+ * - ERTC_TAMPER_EDGE_LOW: low level.
+ * - ERTC_TAMPER_EDGE_HIGH: high level.
+ * @param alarm: alarm para.
+ * @retval none.
+ */
+void ertc_tamper_valid_edge_set(ertc_tamper_select_type tamper_x, ertc_tamper_valid_edge_type trigger)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ if(tamper_x == ERTC_TAMPER_1)
+ {
+ ERTC->tamp_bit.tp1edg = trigger;
+ }
+ else
+ {
+ ERTC->tamp_bit.tp2edg = trigger;
+ }
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief enable or disable trigger timestamp when tamper event occurs.
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void ertc_tamper_timestamp_enable(confirm_state new_state)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ ERTC->tamp_bit.tptsen = new_state;
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief enable or disable tamper.
+ * @param tamper_x: select the tamper.
+ * this parameter can be one of the following values:
+ * - ERTC_TAMPER_1: tamper 1.
+ * - ERTC_TAMPER_2: tamper 2.
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void ertc_tamper_enable(ertc_tamper_select_type tamper_x, confirm_state new_state)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ if(tamper_x == ERTC_TAMPER_1)
+ {
+ ERTC->tamp_bit.tp1en = new_state;
+ }
+ else
+ {
+ ERTC->tamp_bit.tp2en = new_state;
+ }
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief enable or disable interrupt.
+ * @param source: interrupts sources
+ * this parameter can be any combination of the following values:
+ * - ERTC_TP_INT: tamper interrupt.
+ * - ERTC_ALA_INT: alarm a interrupt.
+ * - ERTC_ALB_INT: alarm b interrupt.
+ * - ERTC_WAT_INT: wakeup timer interrupt.
+ * - ERTC_TS_INT: timestamp interrupt.
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void ertc_interrupt_enable(uint32_t source, confirm_state new_state)
+{
+ /* disable write protection */
+ ertc_write_protect_disable();
+
+ if(source & ERTC_TP_INT)
+ {
+ if(new_state != FALSE)
+ {
+ ERTC->tamp |= ERTC_TP_INT;
+ }
+ else
+ {
+ ERTC->tamp &= ~ERTC_TP_INT;
+ }
+
+ source &= ~ERTC_TP_INT;
+ }
+
+ if(new_state != FALSE)
+ {
+ ERTC->ctrl |= source;
+ }
+ else
+ {
+ ERTC->ctrl &= ~source;
+ }
+
+ /* enable write protection */
+ ertc_write_protect_enable();
+}
+
+/**
+ * @brief get interrupt status
+ * @param source
+ * this parameter can be one of the following values:
+ * - ERTC_TP_INT: tamper interrupt.
+ * - ERTC_ALA_INT: alarm a interrupt.
+ * - ERTC_ALB_INT: alarm b interrupt.
+ * - ERTC_WAT_INT: wakeup timer interrupt.
+ * - ERTC_TS_INT: timestamp interrupt.
+ * @retval flag_status (SET or RESET)
+ */
+flag_status ertc_interrupt_get(uint32_t source)
+{
+ if(source & ERTC_TP_INT)
+ {
+ if((ERTC->tamp & ERTC_TP_INT) != RESET)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+ }
+
+ if((ERTC->ctrl & source) != RESET)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief get flag status.
+ * @param flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - ERTC_ALAWF_FLAG: alarm a register allows write flag.
+ * - ERTC_ALBWF_FLAG: alarm b register allows write flag.
+ * - ERTC_WATWF_FLAG: wakeup timer register allows write flag.
+ * - ERTC_TADJF_FLAG: time adjustment flag.
+ * - ERTC_INITF_FLAG: calendar initialization flag.
+ * - ERTC_UPDF_FLAG: calendar update flag.
+ * - ERTC_IMF_FLAG: enter initialization mode flag.
+ * - ERTC_ALAF_FLAG: alarm clock a flag.
+ * - ERTC_ALBF_FLAG: alarm clock b flag.
+ * - ERTC_WATF_FLAG: wakeup timer flag.
+ * - ERTC_TSF_FLAG: timestamp flag.
+ * - ERTC_TSOF_FLAG: timestamp overflow flag.
+ * - ERTC_TP1F_FLAG: tamper detection 1 flag.
+ * - ERTC_TP2F_FLAG: tamper detection 2 flag.
+ * - ERTC_CALUPDF_FLAG: calibration value update completed flag.
+ * @retval the new state of flag (SET or RESET).
+ */
+flag_status ertc_flag_get(uint32_t flag)
+{
+ if((ERTC->sts & flag) != (uint32_t)RESET)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief get interrupt flag status.
+ * @param flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - ERTC_ALAF_FLAG: alarm clock a flag.
+ * - ERTC_ALBF_FLAG: alarm clock b flag.
+ * - ERTC_WATF_FLAG: wakeup timer flag.
+ * - ERTC_TSF_FLAG: timestamp flag.
+ * - ERTC_TP1F_FLAG: tamper detection 1 flag.
+ * - ERTC_TP2F_FLAG: tamper detection 2 flag.
+ * @retval the new state of flag (SET or RESET).
+ */
+flag_status ertc_interrupt_flag_get(uint32_t flag)
+{
+ __IO uint32_t iten = 0;
+
+ switch(flag)
+ {
+ case ERTC_ALAF_FLAG:
+ iten = ERTC->ctrl_bit.alaien;
+ break;
+ case ERTC_ALBF_FLAG:
+ iten = ERTC->ctrl_bit.albien;
+ break;
+ case ERTC_WATF_FLAG:
+ iten = ERTC->ctrl_bit.watien;
+ break;
+ case ERTC_TSF_FLAG:
+ iten = ERTC->ctrl_bit.tsien;
+ break;
+ case ERTC_TP1F_FLAG:
+ case ERTC_TP2F_FLAG:
+ iten = ERTC->tamp_bit.tpien;
+ break;
+
+ default:
+ break;
+ }
+
+ if(((ERTC->sts & flag) != (uint32_t)RESET) && (iten))
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief clear flag status
+ * @param flag: specifies the flag to clear.
+ * this parameter can be any combination of the following values:
+ * - ERTC_ALAWF_FLAG: alarm a register allows write flag.
+ * - ERTC_ALBWF_FLAG: alarm b register allows write flag.
+ * - ERTC_WATWF_FLAG: wakeup timer register allows write flag.
+ * - ERTC_TADJF_FLAG: time adjustment flag.
+ * - ERTC_INITF_FLAG: calendar initialization flag.
+ * - ERTC_UPDF_FLAG: calendar update flag.
+ * - ERTC_IMF_FLAG: enter initialization mode flag.
+ * - ERTC_ALAF_FLAG: alarm clock a flag.
+ * - ERTC_ALBF_FLAG: alarm clock b flag.
+ * - ERTC_WATF_FLAG: wakeup timer flag.
+ * - ERTC_TSF_FLAG: timestamp flag.
+ * - ERTC_TSOF_FLAG: timestamp overflow flag.
+ * - ERTC_TP1F_FLAG: tamper detection 1 flag.
+ * - ERTC_TP2F_FLAG: tamper detection 2 flag.
+ * - ERTC_CALUPDF_FLAG: calibration value update completed flag.
+ * @retval none
+ */
+void ertc_flag_clear(uint32_t flag)
+{
+ ERTC->sts = ~(flag | 0x00000080) | (ERTC->sts_bit.imen << 7);
+}
+
+/**
+ * @brief write data to the bpr register.
+ * @param dt: data register
+ * this parameter can be one of the following values:
+ * - ERTC_DT1
+ * - ERTC_DT2
+ * - ...
+ * - ERTC_DT19
+ * - ERTC_DT20
+ * @param data: data to be write.
+ * @retval none.
+ */
+void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data)
+{
+ __IO uint32_t reg = 0;
+
+ reg = ERTC_BASE + 0x50 + (dt * 4);
+
+ *(__IO uint32_t *)reg = data;
+}
+
+/**
+ * @brief read data from bpr register.
+ * @param dt: data register
+ * this parameter can be one of the following values:
+ * - ERTC_DT1
+ * - ERTC_DT2
+ * - ...
+ * - ERTC_DT19
+ * - ERTC_DT20
+ * @retval data value.
+ */
+uint32_t ertc_bpr_data_read(ertc_dt_type dt)
+{
+ __IO uint32_t reg = 0;
+
+ reg = ERTC_BASE + 0x50 + (dt * 4);
+
+ return (*(__IO uint32_t *)reg);
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_exint.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_exint.c
new file mode 100644
index 00000000000..a479ac209bf
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_exint.c
@@ -0,0 +1,264 @@
+/**
+ **************************************************************************
+ * @file at32f45x_exint.c
+ * @brief contains all the functions for the exint firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup EXINT
+ * @brief EXINT driver modules
+ * @{
+ */
+
+#ifdef EXINT_MODULE_ENABLED
+
+/** @defgroup EXINT_private_functions
+ * @{
+ */
+
+/**
+ * @brief exint reset
+ * @param none
+ * @retval none
+ */
+void exint_reset(void)
+{
+ EXINT->inten = 0x00000000;
+ EXINT->polcfg1 = 0x00000000;
+ EXINT->polcfg2 = 0x00000000;
+ EXINT->evten = 0x00000000;
+ EXINT->intsts = 0xFFFFFFFF;
+}
+
+/**
+ * @brief exint default para init
+ * @param exint_struct
+ * - to the structure of exint_init_type
+ * @retval none
+ */
+void exint_default_para_init(exint_init_type *exint_struct)
+{
+ exint_struct->line_enable = FALSE;
+ exint_struct->line_select = EXINT_LINE_NONE;
+ exint_struct->line_polarity = EXINT_TRIGGER_FALLING_EDGE;
+ exint_struct->line_mode = EXINT_LINE_EVENT;
+}
+
+/**
+ * @brief exint init
+ * @param exint_struct
+ * - to the structure of exint_init_type
+ * @retval none
+ */
+void exint_init(exint_init_type *exint_struct)
+{
+ uint32_t line_index = 0;
+ line_index = exint_struct->line_select;
+
+ EXINT->inten &= ~line_index;
+ EXINT->evten &= ~line_index;
+
+ if(exint_struct->line_enable != FALSE)
+ {
+ if(exint_struct->line_mode == EXINT_LINE_INTERRUPT)
+ {
+ EXINT->inten |= line_index;
+ }
+ else
+ {
+ EXINT->evten |= line_index;
+ }
+
+ EXINT->polcfg1 &= ~line_index;
+ EXINT->polcfg2 &= ~line_index;
+ if(exint_struct->line_polarity == EXINT_TRIGGER_RISING_EDGE)
+ {
+ EXINT->polcfg1 |= line_index;
+ }
+ else if(exint_struct->line_polarity == EXINT_TRIGGER_FALLING_EDGE)
+ {
+ EXINT->polcfg2 |= line_index;
+ }
+ else
+ {
+ EXINT->polcfg1 |= line_index;
+ EXINT->polcfg2 |= line_index;
+ }
+ }
+}
+
+/**
+ * @brief clear exint flag
+ * @param exint_line
+ * this parameter can be any combination of the following values:
+ * - EXINT_LINE_0
+ * - EXINT_LINE_1
+ * ...
+ * - EXINT_LINE_21
+ * - EXINT_LINE_22
+ * @retval none
+ */
+void exint_flag_clear(uint32_t exint_line)
+{
+ EXINT->intsts = exint_line;
+}
+
+/**
+ * @brief get exint flag
+ * @param exint_line
+ * this parameter can be one of the following values:
+ * - EXINT_LINE_0
+ * - EXINT_LINE_1
+ * ...
+ * - EXINT_LINE_21
+ * - EXINT_LINE_22
+ * @retval the new state of exint flag(SET or RESET).
+ */
+flag_status exint_flag_get(uint32_t exint_line)
+{
+ flag_status status = RESET;
+ uint32_t exint_flag =0;
+ exint_flag = EXINT->intsts & exint_line;
+ if((exint_flag != (uint16_t)RESET))
+ {
+ status = SET;
+ }
+ else
+ {
+ status = RESET;
+ }
+ return status;
+}
+
+/**
+ * @brief get exint interrupt flag
+ * @param exint_line
+ * this parameter can be one of the following values:
+ * - EXINT_LINE_0
+ * - EXINT_LINE_1
+ * ...
+ * - EXINT_LINE_21
+ * - EXINT_LINE_22
+ * @retval the new state of exint flag(SET or RESET).
+ */
+flag_status exint_interrupt_flag_get(uint32_t exint_line)
+{
+ flag_status status = RESET;
+ uint32_t exint_flag = 0;
+ exint_flag = EXINT->intsts & exint_line;
+ exint_flag = exint_flag & EXINT->inten;
+
+ if((exint_flag != (uint16_t)RESET))
+ {
+ status = SET;
+ }
+ else
+ {
+ status = RESET;
+ }
+ return status;
+}
+
+
+/**
+ * @brief generate exint software interrupt event
+ * @param exint_line
+ * this parameter can be one of the following values:
+ * - EXINT_LINE_0
+ * - EXINT_LINE_1
+ * ...
+ * - EXINT_LINE_21
+ * - EXINT_LINE_22
+ * @retval none
+ */
+void exint_software_interrupt_event_generate(uint32_t exint_line)
+{
+ EXINT->swtrg |= exint_line;
+}
+
+/**
+ * @brief enable or disable exint interrupt
+ * @param exint_line
+ * this parameter can be any combination of the following values:
+ * - EXINT_LINE_0
+ * - EXINT_LINE_1
+ * ...
+ * - EXINT_LINE_21
+ * - EXINT_LINE_22
+ * @param new_state: new state of exint interrupt.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state)
+{
+ if(new_state == TRUE)
+ {
+ EXINT->inten |= exint_line;
+ }
+ else
+ {
+ EXINT->inten &= ~exint_line;
+ }
+}
+
+/**
+ * @brief enable or disable exint event
+ * @param exint_line
+ * this parameter can be any combination of the following values:
+ * - EXINT_LINE_0
+ * - EXINT_LINE_1
+ * ...
+ * - EXINT_LINE_21
+ * - EXINT_LINE_22
+ * @param new_state: new state of exint event.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void exint_event_enable(uint32_t exint_line, confirm_state new_state)
+{
+ if(new_state == TRUE)
+ {
+ EXINT->evten |= exint_line;
+ }
+ else
+ {
+ EXINT->evten &= ~exint_line;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_flash.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_flash.c
new file mode 100644
index 00000000000..7cccaca910d
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_flash.c
@@ -0,0 +1,869 @@
+/**
+ **************************************************************************
+ * @file at32f45x_flash.c
+ * @brief contains all the functions for the flash firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup FLASH
+ * @brief FLASH driver modules
+ * @{
+ */
+
+#ifdef FLASH_MODULE_ENABLED
+
+/** @defgroup FLASH_private_functions
+ * @{
+ */
+
+/**
+ * @brief check whether the specified flash flag is set or not.
+ * @param flash_flag: specifies the flash flag to check.
+ * this parameter can be one of flash flag status:
+ * - FLASH_OBF_FLAG
+ * - FLASH_ODF_FLAG
+ * - FLASH_PRGMERR_FLAG
+ * - FLASH_EPPERR_FLAG
+ * - FLASH_USDERR_FLAG
+ * @retval the new state of flash_flag (SET or RESET).
+ */
+flag_status flash_flag_get(uint32_t flash_flag)
+{
+ flag_status status = RESET;
+ uint32_t flag_position;
+ flag_position = flash_flag & 0x70000000;
+ flash_flag &= 0x8FFFFFFF;
+ switch(flag_position)
+ {
+ case 0x00000000:
+ if(FLASH->sts & flash_flag)
+ status = SET;
+ break;
+ case 0x40000000:
+ if(FLASH->usd & flash_flag)
+ status = SET;
+ break;
+ default:
+ break;
+ }
+ /* return the new state of flash_flag (SET or RESET) */
+ return status;
+}
+
+/**
+ * @brief clear the flash flag.
+ * @param flash_flag: specifies the flash flags to clear.
+ * this parameter can be any combination of the following values:
+ * - FLASH_ODF_FLAG
+ * - FLASH_PRGMERR_FLAG
+ * - FLASH_EPPERR_FLAG
+ * @retval none
+ */
+void flash_flag_clear(uint32_t flash_flag)
+{
+ FLASH->sts = flash_flag;
+}
+
+/**
+ * @brief return the flash operation status.
+ * @param none
+ * @retval status: the returned value can be: FLASH_OPERATE_BUSY,
+ * FLASH_PROGRAM_ERROR, FLASH_EPP_ERROR or FLASH_OPERATE_DONE.
+ */
+flash_status_type flash_operation_status_get(void)
+{
+ flash_status_type flash_status = FLASH_OPERATE_DONE;
+ if(FLASH->sts_bit.obf != RESET)
+ {
+ flash_status = FLASH_OPERATE_BUSY;
+ }
+ else if(FLASH->sts_bit.prgmerr != RESET)
+ {
+ flash_status = FLASH_PROGRAM_ERROR;
+ }
+ else if(FLASH->sts_bit.epperr != RESET)
+ {
+ flash_status = FLASH_EPP_ERROR;
+ }
+ else
+ {
+ flash_status = FLASH_OPERATE_DONE;
+ }
+ /* return the flash status */
+ return flash_status;
+}
+
+/**
+ * @brief wait for flash operation complete or timeout.
+ * @param time_out: flash operation timeout
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_operation_wait_for(uint32_t time_out)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+ /* check for the flash status */
+ status = flash_operation_status_get();
+
+ while((status == FLASH_OPERATE_BUSY) && (time_out != 0x00))
+ {
+ status = flash_operation_status_get();
+ time_out--;
+ }
+ if(time_out == 0x00)
+ {
+ status = FLASH_OPERATE_TIMEOUT;
+ }
+ /* return the status */
+ return status;
+}
+
+/**
+ * @brief unlock the flash controller.
+ * @param none
+ * @retval none
+ */
+void flash_unlock(void)
+{
+ FLASH->unlock = FLASH_UNLOCK_KEY1;
+ FLASH->unlock = FLASH_UNLOCK_KEY2;
+}
+
+/**
+ * @brief lock the flash controller.
+ * @param none
+ * @retval none
+ */
+void flash_lock(void)
+{
+ FLASH->ctrl_bit.oplk = TRUE;
+}
+
+/**
+ * @brief erase a specified flash sector.
+ * @param sector_address: the sector address to be erased.
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_sector_erase(uint32_t sector_address)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+
+ FLASH->ctrl_bit.secers = TRUE;
+ FLASH->addr = sector_address;
+ FLASH->ctrl_bit.erstr = TRUE;
+
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(ERASE_TIMEOUT);
+
+ /* disable the secers bit */
+ FLASH->ctrl_bit.secers = FALSE;
+
+ /* return the erase status */
+ return status;
+}
+
+/**
+ * @brief erase flash all internal sectors.
+ * @param none
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_internal_all_erase(void)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+
+ FLASH->ctrl_bit.bankers = TRUE;
+ FLASH->ctrl_bit.erstr = TRUE;
+
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(ERASE_TIMEOUT);
+
+ /* disable the bankers bit */
+ FLASH->ctrl_bit.bankers = FALSE;
+
+ /* return the erase status */
+ return status;
+}
+
+/**
+ * @brief erase the flash user system data.
+ * @note this functions erases all user system data except the fap byte.
+ * when fap high level enabled, can't use this function.
+ * @param none
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_user_system_data_erase(void)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+ uint16_t fap_val = FAP_RELIEVE_KEY;
+ /* get the flash access protection status */
+ if(flash_fap_status_get() != RESET)
+ {
+ fap_val = 0x0000;
+ }
+
+ /* unlock the user system data */
+ FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
+ FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
+ while(FLASH->ctrl_bit.usdulks==RESET);
+
+ /* erase the user system data */
+ FLASH->ctrl_bit.usders = TRUE;
+ FLASH->ctrl_bit.erstr = TRUE;
+
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(ERASE_TIMEOUT);
+
+ /* disable the usders bit */
+ FLASH->ctrl_bit.usders = FALSE;
+
+ if((status == FLASH_OPERATE_DONE) && (fap_val == FAP_RELIEVE_KEY))
+ {
+ /* enable the user system data programming operation */
+ FLASH->ctrl_bit.usdprgm = TRUE;
+
+ /* restore the last flash access protection value */
+ USD->fap = (uint16_t)fap_val;
+
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ /*disable the usdprgm bit */
+ FLASH->ctrl_bit.usdprgm = FALSE;
+ }
+
+ /* return the erase status */
+ return status;
+}
+
+/**
+ * @brief program a word at a specified address.
+ * @param address: specifies the address to be programmed, word alignment is recommended.
+ * @param data: specifies the data to be programmed.
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_word_program(uint32_t address, uint32_t data)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+
+ FLASH->ctrl_bit.fprgm = TRUE;
+ *(__IO uint32_t*)address = data;
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ /* disable the fprgm bit */
+ FLASH->ctrl_bit.fprgm = FALSE;
+
+ /* return the program status */
+ return status;
+}
+
+/**
+ * @brief program a halfword at a specified address.
+ * @param address: specifies the address to be programmed, halfword alignment is recommended.
+ * @param data: specifies the data to be programmed.
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_halfword_program(uint32_t address, uint16_t data)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+
+ FLASH->ctrl_bit.fprgm = TRUE;
+ *(__IO uint16_t*)address = data;
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ /* disable the fprgm bit */
+ FLASH->ctrl_bit.fprgm = FALSE;
+
+ /* return the program status */
+ return status;
+}
+
+/**
+ * @brief program a byte at a specified address.
+ * @param address: specifies the address to be programmed.
+ * @param data: specifies the data to be programmed.
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_byte_program(uint32_t address, uint8_t data)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+
+ FLASH->ctrl_bit.fprgm = TRUE;
+ *(__IO uint8_t*)address = data;
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ /* disable the fprgm bit */
+ FLASH->ctrl_bit.fprgm = FALSE;
+
+ /* return the program status */
+ return status;
+}
+
+/**
+ * @brief program a halfword at a specified user system data address.
+ * @param address: specifies the address to be programmed.
+ * @param data: specifies the data to be programmed.
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+
+ /* unlock the user system data */
+ FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
+ FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
+ while(FLASH->ctrl_bit.usdulks==RESET);
+
+ /* enable the user system data programming operation */
+ FLASH->ctrl_bit.usdprgm = TRUE;
+ *(__IO uint16_t*)address = data;
+
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ /* disable the usdprgm bit */
+ FLASH->ctrl_bit.usdprgm = FALSE;
+
+ /* return the user system data program status */
+ return status;
+}
+
+/**
+ * @brief config erase/program protection for the desired sectors.
+ * @param sector_bits:
+ * the pointer of the address of the sectors to be erase/program protected.
+ * the first 16bits general every bit is used to protect the 4KB bytes. the
+ * bit 31 is used to protect the extension memory.
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_epp_set(uint32_t *sector_bits)
+{
+ uint16_t epp_data[4] = {0xFFFF,0xFFFF,0xFFFF,0xFFFF};
+ flash_status_type status = FLASH_OPERATE_DONE;
+ sector_bits[0] = (uint32_t)(~sector_bits[0]);
+ epp_data[0] = (uint16_t)((sector_bits[0] >> 0) & 0xFF);
+ epp_data[1] = (uint16_t)((sector_bits[0] >> 8) & 0xFF);
+ epp_data[2] = (uint16_t)((sector_bits[0] >> 16) & 0xFF);
+ epp_data[3] = (uint16_t)((sector_bits[0] >> 24) & 0xFF);
+
+ /* unlock the user system data */
+ FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
+ FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
+ while(FLASH->ctrl_bit.usdulks==RESET);
+
+ FLASH->ctrl_bit.usdprgm = TRUE;
+ USD->epp0 = epp_data[0];
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ if(status == FLASH_OPERATE_DONE)
+ {
+ USD->epp1 = epp_data[1];
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+ }
+ if(status == FLASH_OPERATE_DONE)
+ {
+ USD->epp2 = epp_data[2];
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+ }
+ if(status == FLASH_OPERATE_DONE)
+ {
+ USD->epp3 = epp_data[3];
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+ }
+ /* disable the usdprgm bit */
+ FLASH->ctrl_bit.usdprgm = FALSE;
+
+ /* return the erase/program protection operation status */
+ return status;
+}
+
+/**
+ * @brief return the flash erase/program protection status.
+ * @param sector_bits: pointer to get the epps register.
+ * @retval none
+ */
+void flash_epp_status_get(uint32_t *sector_bits)
+{
+ /* return the flash erase/program protection register value */
+ sector_bits[0] = (uint32_t)(FLASH->epps);
+}
+
+/**
+ * @brief enable or disable the flash access protection.
+ * @note if the user has already programmed the other user system data before calling
+ * this function, must re-program them since this function erase all user system data.
+ * @param new_state: new state of the flash access protection.
+ * this parameter can be: TRUE or FALSE.
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_fap_enable(confirm_state new_state)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+
+ /* unlock the user system data */
+ FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
+ FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
+ while(FLASH->ctrl_bit.usdulks==RESET);
+
+ FLASH->ctrl_bit.usders = TRUE;
+ FLASH->ctrl_bit.erstr = TRUE;
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(ERASE_TIMEOUT);
+
+ /* disable the usders bit */
+ FLASH->ctrl_bit.usders = FALSE;
+
+ if(status == FLASH_OPERATE_DONE)
+ {
+ if(new_state == FALSE)
+ {
+ /* enable the user system data programming operation */
+ FLASH->ctrl_bit.usdprgm = TRUE;
+ USD->fap = FAP_RELIEVE_KEY;
+
+ /* Wait for operation to be completed */
+ status = flash_operation_wait_for(ERASE_TIMEOUT);
+
+ /* disable the usdprgm bit */
+ FLASH->ctrl_bit.usdprgm = FALSE;
+ }
+ }
+
+ /* return the flash access protection operation status */
+ return status;
+}
+
+/**
+ * @brief check the flash access protection status.
+ * @param none
+ * @retval flash access protection status(SET or RESET)
+ */
+flag_status flash_fap_status_get(void)
+{
+ return (flag_status)FLASH->usd_bit.fap;
+}
+
+/**
+ * @brief enable or disable the flash access protection high level.
+ * @note if the user has already programmed the other user system data before calling
+ * this function, must re-program them since this function erase all user system data.
+ * @note once the fap high level enabled, the swd debugger port will be permanently disable!!!
+ * @param new_state: new state of the flash access protection high level.
+ * this parameter can be: TRUE or FALSE.
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_fap_high_level_enable(void)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+
+ /* unlock the user system data */
+ FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
+ FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
+ while(FLASH->ctrl_bit.usdulks==RESET);
+
+ FLASH->ctrl_bit.usders = TRUE;
+ FLASH->ctrl_bit.erstr = TRUE;
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(ERASE_TIMEOUT);
+
+ /* disable the usders bit */
+ FLASH->ctrl_bit.usders = FALSE;
+
+ if(status == FLASH_OPERATE_DONE)
+ {
+ /* enable the user system data programming operation */
+ FLASH->ctrl_bit.usdprgm = TRUE;
+ USD->fap = FAP_HIGH_LEVEL_KEY;
+
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ /* disable the usdprgm bit */
+ FLASH->ctrl_bit.usdprgm = FALSE;
+ }
+
+ /* return the flash access protection operation status */
+ return status;
+}
+
+/**
+ * @brief check the flash access protection high level status.
+ * @param none
+ * @retval flash access protection high level status(SET or RESET)
+ */
+flag_status flash_fap_high_level_status_get(void)
+{
+ return (flag_status)FLASH->usd_bit.fap_hl;
+}
+
+/**
+ * @brief program the flash system setting byte in usd: wdt_ato_en / depslp_rst / stdby_rst / boot1 / depslp_wdt / stdby_wdt / ram_prt_chk.
+ * @param usd_ssb: the system setting byte
+ * @note this parameter usd_ssb must contain a combination of all the following 6 types of data
+ * type 1: wdt_ato_en, select the wdt auto start
+ * this data can be one of the following values:
+ * - USD_WDT_ATO_DISABLE: disable wdt auto start
+ * - USD_WDT_ATO_ENABLE: enable wdt auto start
+ * type 2: depslp_rst, reset event when entering deepsleep mode.
+ * this data can be one of the following values:
+ * - USD_DEPSLP_NO_RST: no reset generated when entering in deepsleep
+ * - USD_DEPSLP_RST: reset generated when entering in deepsleep
+ * type 3: stdby_rst, reset event when entering standby mode.
+ * this data can be one of the following values:
+ * - USD_STDBY_NO_RST: no reset generated when entering in standby
+ * - USD_STDBY_RST: reset generated when entering in standby
+ * type 4: depslp_wdt, wdt stop count when entering deepsleep mode.
+ * this data can be one of the following values:
+ * - USD_DEPSLP_WDT_CONTINUE: wdt continue count when entering in deepsleep
+ * - USD_DEPSLP_WDT_STOP: wdt stop count when entering in deepsleep
+ * type 5: stdby_wdt, wdt stop count when entering standby mode.
+ * this data can be one of the following values:
+ * - USD_STDBY_WDT_CONTINUE: wdt continue count when entering in standby
+ * - USD_STDBY_WDT_STOP: wdt stop count when entering in standby
+ * type 6: ram_prt_chk, wdt stop count when entering standby mode.
+ * - USD_RAM_PRT_CHK_ENABLE: ram parity check enabled
+ * - USD_RAM_PRT_CHK_DISABLE: ram parity check disabled
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_ssb_set(uint8_t usd_ssb)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+
+ /* unlock the user system data */
+ FLASH->usd_unlock = FLASH_UNLOCK_KEY1;
+ FLASH->usd_unlock = FLASH_UNLOCK_KEY2;
+ while(FLASH->ctrl_bit.usdulks==RESET);
+
+ /* enable the user system data programming operation */
+ FLASH->ctrl_bit.usdprgm = TRUE;
+
+ USD->ssb = usd_ssb;
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ /* disable the usdprgm bit */
+ FLASH->ctrl_bit.usdprgm = FALSE;
+
+ /* return the user system data program status */
+ return status;
+}
+
+/**
+ * @brief return the flash system setting byte status.
+ * @param none
+ * @retval values from flash_usd register: wdt_ato_en(bit0), depslp_rst(bit1),
+ * stdby_rst(bit2), boot1(bit4), depslp_wdt(bit5), stdby_wdt(bit6) and ram_prt_chk(bit7).
+ */
+uint8_t flash_ssb_status_get(void)
+{
+ /* return the system setting byte status */
+ return (uint8_t)(FLASH->usd >> 2);
+}
+
+/**
+ * @brief enable or disable the specified flash interrupts.
+ * @param flash_int: specifies the flash interrupt sources to be enabled or disabled.
+ * this parameter can be any combination of the following values:
+ * - FLASH_ERR_INT
+ * - FLASH_ODF_INT
+ * @param new_state: new state of the specified flash interrupts.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state)
+{
+ if(flash_int & FLASH_ERR_INT)
+ FLASH->ctrl_bit.errie = new_state;
+ if(flash_int & FLASH_ODF_INT)
+ FLASH->ctrl_bit.odfie = new_state;
+}
+
+/**
+ * @brief enable main block security library function.
+ * @param pwd: slib password
+ * start_sector: security library start sector
+ * inst_start_sector: security library i-bus area start sector
+ * end_sector: security library end sector
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t inst_start_sector, uint16_t end_sector)
+{
+ uint32_t slib_range;
+ flash_status_type status = FLASH_OPERATE_DONE;
+
+ /*check range param limits*/
+ if((start_sector>inst_start_sector) || ((inst_start_sector > end_sector) && \
+ (inst_start_sector != 0x7FF)) || (start_sector > end_sector))
+ return FLASH_PROGRAM_ERROR;
+
+ /* unlock slib cfg register */
+ FLASH->slib_unlock = SLIB_UNLOCK_KEY;
+ while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET);
+
+ slib_range = ((uint32_t)(inst_start_sector << 11) & FLASH_SLIB_INST_START_SECTOR) | \
+ ((uint32_t)(end_sector << 22) & FLASH_SLIB_END_SECTOR) | \
+ (start_sector & FLASH_SLIB_START_SECTOR);
+ /* configure slib, set pwd and range */
+ FLASH->slib_set_pwd = pwd;
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+ if(status == FLASH_OPERATE_DONE)
+ {
+ FLASH->slib_set_range = slib_range;
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+ }
+
+ return status;
+}
+
+/**
+ * @brief disable main block slib when slib enabled.
+ * @param pwd: slib password
+ * @retval success or error
+ */
+error_status flash_slib_disable(uint32_t pwd)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+ /* write password to disable slib */
+ FLASH->slib_pwd_clr = pwd;
+
+ status = flash_operation_wait_for(ERASE_TIMEOUT);
+ if(status == FLASH_OPERATE_DONE)
+ {
+ if(FLASH->slib_misc_sts_bit.slib_pwd_ok)
+ return SUCCESS;
+ else
+ return ERROR;
+ }
+ return ERROR;
+}
+
+/**
+ * @brief get the main block slib state.
+ * @param none
+ * @retval SET or RESET
+ */
+flag_status flash_slib_state_get(void)
+{
+ if(FLASH->slib_sts0_bit.slib_enf)
+ return SET;
+ else
+ return RESET;
+}
+
+/**
+ * @brief get the main block start sector of slib.
+ * @param none
+ * @retval uint16_t
+ */
+uint16_t flash_slib_start_sector_get(void)
+{
+ return (uint16_t)FLASH->slib_sts1_bit.slib_ss;
+}
+
+/**
+ * @brief get the main block inst start sector of slib.
+ * @param none
+ * @retval uint16_t
+ */
+uint16_t flash_slib_inststart_sector_get(void)
+{
+ return (uint16_t)FLASH->slib_sts1_bit.slib_inst_ss;
+}
+
+/**
+ * @brief get the main block end sector of slib.
+ * @param none
+ * @retval uint16_t
+ */
+uint16_t flash_slib_end_sector_get(void)
+{
+ return (uint16_t)FLASH->slib_sts1_bit.slib_es;
+}
+
+/**
+ * @brief flash crc calibration.
+ * @param start_addr: crc calibration start sector address
+ * sector_cnt: crc calibration sector count
+ * @retval uint32: crc calibration result
+ */
+uint32_t flash_crc_calibrate(uint32_t start_addr, uint32_t sector_cnt)
+{
+ FLASH->crc_addr = start_addr;
+ FLASH->crc_ctrl = sector_cnt | 0x10000;
+ flash_operation_wait_for(OPERATION_TIMEOUT);
+ return FLASH->crc_chkr;
+}
+
+/**
+ * @brief enable boot memory as extension mode.
+ * @note this function is irreversible, can not disable!!!
+ * @param none
+ * @retval none.
+ */
+void flash_boot_memory_extension_mode_enable(void)
+{
+ if(FLASH->slib_sts0_bit.btm_ap_enf == RESET)
+ {
+ FLASH->slib_unlock = SLIB_UNLOCK_KEY;
+ while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET);
+ FLASH->btm_mode_set = 0;
+ flash_operation_wait_for(OPERATION_TIMEOUT);
+ }
+}
+
+/**
+ * @brief enable extension memory security library function.
+ * @param pwd: slib password
+ * inst_start_sector: extension memory security library i-bus area start sector, range 0~3 or 0xFF
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_extension_memory_slib_enable(uint32_t pwd, uint16_t inst_start_sector)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+
+ /* unlock slib cfg register */
+ FLASH->slib_unlock = SLIB_UNLOCK_KEY;
+ while(FLASH->slib_misc_sts_bit.slib_ulkf==RESET);
+
+ /* configure slib, set pwd and range */
+ FLASH->slib_set_pwd = pwd;
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+ if(status == FLASH_OPERATE_DONE)
+ {
+ FLASH->em_slib_set = (uint32_t)(inst_start_sector << 16) + (uint32_t)0x5AA5;
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+ }
+
+ return status;
+}
+
+/**
+ * @brief get the extension memory slib state.
+ * @param none
+ * @retval SET or RESET
+ */
+flag_status flash_extension_memory_slib_state_get(void)
+{
+ if(FLASH->slib_sts0_bit.em_slib_enf)
+ return SET;
+ else
+ return RESET;
+}
+
+/**
+ * @brief get the extension memory inst start sector of slib.
+ * @param none
+ * @retval uint16_t
+ */
+uint16_t flash_em_slib_inststart_sector_get(void)
+{
+ return (uint16_t)FLASH->slib_sts0_bit.em_slib_inst_ss;
+}
+
+/**
+ * @brief start programing otp data from the specified address.
+ * @note the otp data can't erase!
+ * @param address: specifies the address to be programmed. the starting address is OTP_DATA_BASE.
+ * @param data_buf: specifies the otp data pointer to be programmed.
+ * @param length: specifies the length to be programmed.
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_otp_data_program(uint32_t address, uint8_t *data_buf, uint16_t length)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+
+ FLASH->ctrl_bit.fprgm = TRUE;
+ while(length--)
+ {
+ *(__IO uint8_t*)(address++) = *(data_buf++);
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+ if(status != FLASH_OPERATE_DONE)
+ break;
+ }
+ /* disable the fprgm bit */
+ FLASH->ctrl_bit.fprgm = FALSE;
+
+ return status;
+}
+
+/**
+ * @brief lock the specified otp data area.
+ * @note when the specified otp data area locked, it can't unlock!
+ * @param area_index: lock otp area index(0~31).
+ * each index corresponds to 32 bytes of otp data, locked otp data area starting address is OTP_DATA_BASE + 32 * area_index.
+ * @retval status: the returned value can be: FLASH_PROGRAM_ERROR,
+ * FLASH_EPP_ERROR, FLASH_OPERATE_DONE or FLASH_OPERATE_TIMEOUT.
+ */
+flash_status_type flash_otp_lock_enable(uint8_t area_index)
+{
+ flash_status_type status = FLASH_OPERATE_DONE;
+
+ FLASH->ctrl_bit.fprgm = TRUE;
+
+ *(__IO uint8_t*)(OTP_LOCK_BASE + area_index) = 0x00;
+ /* wait for operation to be completed */
+ status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
+
+ /* disable the fprgm bit */
+ FLASH->ctrl_bit.fprgm = FALSE;
+
+ return status;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_gpio.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_gpio.c
new file mode 100644
index 00000000000..d50532d366e
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_gpio.c
@@ -0,0 +1,552 @@
+/**
+ **************************************************************************
+ * @file at32f45x_gpio.c
+ * @brief contains all the functions for the gpio firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup GPIO
+ * @brief GPIO driver modules
+ * @{
+ */
+
+#ifdef GPIO_MODULE_ENABLED
+
+/** @defgroup GPIO_private_functions
+ * @{
+ */
+
+/**
+ * @brief reset the gpio register
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @retval none
+ */
+void gpio_reset(gpio_type *gpio_x)
+{
+ if(gpio_x == GPIOA)
+ {
+ crm_periph_reset(CRM_GPIOA_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_GPIOA_PERIPH_RESET, FALSE);
+ }
+ else if(gpio_x == GPIOB)
+ {
+ crm_periph_reset(CRM_GPIOB_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_GPIOB_PERIPH_RESET, FALSE);
+ }
+ else if(gpio_x == GPIOC)
+ {
+ crm_periph_reset(CRM_GPIOC_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_GPIOC_PERIPH_RESET, FALSE);
+ }
+ else if(gpio_x == GPIOD)
+ {
+ crm_periph_reset(CRM_GPIOD_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_GPIOD_PERIPH_RESET, FALSE);
+ }
+ else if(gpio_x == GPIOE)
+ {
+ crm_periph_reset(CRM_GPIOE_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_GPIOE_PERIPH_RESET, FALSE);
+ }
+ else if(gpio_x == GPIOF)
+ {
+ crm_periph_reset(CRM_GPIOF_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_GPIOF_PERIPH_RESET, FALSE);
+ }
+ else if(gpio_x == GPIOG)
+ {
+ crm_periph_reset(CRM_GPIOG_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_GPIOG_PERIPH_RESET, FALSE);
+ }
+ else if(gpio_x == GPIOH)
+ {
+ crm_periph_reset(CRM_GPIOH_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_GPIOH_PERIPH_RESET, FALSE);
+ }
+}
+
+/**
+ * @brief initialize the gpio peripheral.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @param gpio_init_struct: pointer to gpio init structure.
+ * @retval none
+ */
+void gpio_init(gpio_type *gpio_x, gpio_init_type *gpio_init_struct)
+{
+ uint16_t pinx_value, pin_index = 0;
+
+ pinx_value = (uint16_t)gpio_init_struct->gpio_pins;
+
+ while(pinx_value > 0)
+ {
+ if(pinx_value & 0x01)
+ {
+ gpio_x->cfgr &= (uint32_t)~(0x03 << (pin_index * 2));
+ gpio_x->cfgr |= (uint32_t)(gpio_init_struct->gpio_mode << (pin_index * 2));
+
+ gpio_x->omode &= (uint32_t)~(0x01 << (pin_index));
+ gpio_x->omode |= (uint32_t)(gpio_init_struct->gpio_out_type << (pin_index));
+
+ gpio_x->odrvr &= (uint32_t)~(0x03 << (pin_index * 2));
+ gpio_x->odrvr |= (uint32_t)(gpio_init_struct->gpio_drive_strength << (pin_index * 2));
+
+ gpio_x->pull &= (uint32_t)~(0x03 << (pin_index * 2));
+ gpio_x->pull |= (uint32_t)(gpio_init_struct->gpio_pull << (pin_index * 2));
+ }
+ pinx_value >>= 1;
+ pin_index++;
+ }
+}
+
+/**
+ * @brief fill each gpio_init_type member with its default value.
+ * @param gpio_init_struct : pointer to a gpio_init_type structure which will be initialized.
+ * @retval none
+ */
+void gpio_default_para_init(gpio_init_type *gpio_init_struct)
+{
+ /* reset gpio init structure parameters values */
+ gpio_init_struct->gpio_pins = GPIO_PINS_ALL;
+ gpio_init_struct->gpio_mode = GPIO_MODE_INPUT;
+ gpio_init_struct->gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
+ gpio_init_struct->gpio_pull = GPIO_PULL_NONE;
+ gpio_init_struct->gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
+}
+
+/**
+ * @brief read the specified input port pin.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @param pins: gpio pin number
+ * this parameter can be one of the following values:
+ * - GPIO_PINS_0
+ * - GPIO_PINS_1
+ * - GPIO_PINS_2
+ * - GPIO_PINS_3
+ * - GPIO_PINS_4
+ * - GPIO_PINS_5
+ * - GPIO_PINS_6
+ * - GPIO_PINS_7
+ * - GPIO_PINS_8
+ * - GPIO_PINS_9
+ * - GPIO_PINS_10
+ * - GPIO_PINS_11
+ * - GPIO_PINS_12
+ * - GPIO_PINS_13
+ * - GPIO_PINS_14
+ * - GPIO_PINS_15
+ * @retval flag_status (SET or RESET)
+ */
+flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins)
+{
+ flag_status status = RESET;
+
+ if(pins != (pins & gpio_x->idt))
+ {
+ status = RESET;
+ }
+ else
+ {
+ status = SET;
+ }
+
+ return status;
+}
+
+/**
+ * @brief read the specified gpio input data port.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @retval gpio input data port value.
+ */
+uint16_t gpio_input_data_read(gpio_type *gpio_x)
+{
+ return ((uint16_t)(gpio_x->idt));
+}
+
+/**
+ * @brief read the specified output port pin.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @param pins: gpio pin number
+ * this parameter can be one of the following values:
+ * - GPIO_PINS_0
+ * - GPIO_PINS_1
+ * - GPIO_PINS_2
+ * - GPIO_PINS_3
+ * - GPIO_PINS_4
+ * - GPIO_PINS_5
+ * - GPIO_PINS_6
+ * - GPIO_PINS_7
+ * - GPIO_PINS_8
+ * - GPIO_PINS_9
+ * - GPIO_PINS_10
+ * - GPIO_PINS_11
+ * - GPIO_PINS_12
+ * - GPIO_PINS_13
+ * - GPIO_PINS_14
+ * - GPIO_PINS_15
+ * @retval flag_status (SET or RESET)
+ */
+flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins)
+{
+ flag_status status = RESET;
+
+ if((gpio_x->odt & pins) != RESET)
+ {
+ status = SET;
+ }
+ else
+ {
+ status = RESET;
+ }
+
+ return status;
+}
+
+/**
+ * @brief read the specified gpio ouput data port.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @retval gpio input data port value.
+ */
+uint16_t gpio_output_data_read(gpio_type *gpio_x)
+{
+ return ((uint16_t)(gpio_x->odt));
+}
+
+/**
+ * @brief set the selected data port bits.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @param pins: gpio pin number
+ * parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
+ * - GPIO_PINS_0
+ * - GPIO_PINS_1
+ * - GPIO_PINS_2
+ * - GPIO_PINS_3
+ * - GPIO_PINS_4
+ * - GPIO_PINS_5
+ * - GPIO_PINS_6
+ * - GPIO_PINS_7
+ * - GPIO_PINS_8
+ * - GPIO_PINS_9
+ * - GPIO_PINS_10
+ * - GPIO_PINS_11
+ * - GPIO_PINS_12
+ * - GPIO_PINS_13
+ * - GPIO_PINS_14
+ * - GPIO_PINS_15
+ * - GPIO_PINS_ALL
+ * @retval none
+ */
+void gpio_bits_set(gpio_type *gpio_x, uint16_t pins)
+{
+ gpio_x->scr = pins;
+}
+
+/**
+ * @brief clear the selected data port bits.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @param pins: gpio pin number
+ * parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
+ * - GPIO_PINS_0
+ * - GPIO_PINS_1
+ * - GPIO_PINS_2
+ * - GPIO_PINS_3
+ * - GPIO_PINS_4
+ * - GPIO_PINS_5
+ * - GPIO_PINS_6
+ * - GPIO_PINS_7
+ * - GPIO_PINS_8
+ * - GPIO_PINS_9
+ * - GPIO_PINS_10
+ * - GPIO_PINS_11
+ * - GPIO_PINS_12
+ * - GPIO_PINS_13
+ * - GPIO_PINS_14
+ * - GPIO_PINS_15
+ * - GPIO_PINS_ALL
+ * @retval none
+ */
+void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins)
+{
+ gpio_x->clr = pins;
+}
+
+/**
+ * @brief toggle the selected data port bits.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @param pins: gpio pin number
+ * parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
+ * - GPIO_PINS_0
+ * - GPIO_PINS_1
+ * - GPIO_PINS_2
+ * - GPIO_PINS_3
+ * - GPIO_PINS_4
+ * - GPIO_PINS_5
+ * - GPIO_PINS_6
+ * - GPIO_PINS_7
+ * - GPIO_PINS_8
+ * - GPIO_PINS_9
+ * - GPIO_PINS_10
+ * - GPIO_PINS_11
+ * - GPIO_PINS_12
+ * - GPIO_PINS_13
+ * - GPIO_PINS_14
+ * - GPIO_PINS_15
+ * - GPIO_PINS_ALL
+ * @retval none
+ */
+void gpio_bits_toggle(gpio_type *gpio_x, uint16_t pins)
+{
+ gpio_x->togr = pins;
+}
+
+/**
+ * @brief set or clear the selected data port bit.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @param pins: gpio pin number
+ * parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
+ * - GPIO_PINS_0
+ * - GPIO_PINS_1
+ * - GPIO_PINS_2
+ * - GPIO_PINS_3
+ * - GPIO_PINS_4
+ * - GPIO_PINS_5
+ * - GPIO_PINS_6
+ * - GPIO_PINS_7
+ * - GPIO_PINS_8
+ * - GPIO_PINS_9
+ * - GPIO_PINS_10
+ * - GPIO_PINS_11
+ * - GPIO_PINS_12
+ * - GPIO_PINS_13
+ * - GPIO_PINS_14
+ * - GPIO_PINS_15
+ * - GPIO_PINS_ALL
+ * @param bit_state: specifies the value to be written to the selected bit (TRUE or FALSE).
+ * @retval none
+ */
+void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state)
+{
+ if(bit_state != FALSE)
+ {
+ gpio_x->scr = pins;
+ }
+ else
+ {
+ gpio_x->clr = pins;
+ }
+}
+
+/**
+ * @brief write data to the specified gpio data port.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @param port_value: specifies the value to be written to the port output data register.
+ * @retval none
+ */
+void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value)
+{
+ gpio_x->odt = port_value;
+}
+
+/**
+ * @brief write protect gpio pins configuration registers.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @param pins: gpio pin number
+ * this parameter can be any combination of the following:
+ * - GPIO_PINS_0
+ * - GPIO_PINS_1
+ * - GPIO_PINS_2
+ * - GPIO_PINS_3
+ * - GPIO_PINS_4
+ * - GPIO_PINS_5
+ * - GPIO_PINS_6
+ * - GPIO_PINS_7
+ * - GPIO_PINS_8
+ * - GPIO_PINS_9
+ * - GPIO_PINS_10
+ * - GPIO_PINS_11
+ * - GPIO_PINS_12
+ * - GPIO_PINS_13
+ * - GPIO_PINS_14
+ * - GPIO_PINS_15
+ * - GPIO_PINS_ALL
+ * @retval none
+ */
+void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins)
+{
+ uint32_t temp = 0x00010000;
+
+ temp |= pins;
+ /* set wpen bit */
+ gpio_x->wpr = temp;
+ /* reset wpen bit */
+ gpio_x->wpr = pins;
+ /* set wpen bit */
+ gpio_x->wpr = temp;
+ /* read wpen bit*/
+ temp = gpio_x->wpr;
+ /* read wpen bit*/
+ temp = gpio_x->wpr;
+}
+
+/**
+ * @brief enable or disable gpio pins huge driven.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @param pins: gpio pin number
+ * parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
+ * - GPIO_PINS_0
+ * - GPIO_PINS_1
+ * - GPIO_PINS_2
+ * - GPIO_PINS_3
+ * - GPIO_PINS_4
+ * - GPIO_PINS_5
+ * - GPIO_PINS_6
+ * - GPIO_PINS_7
+ * - GPIO_PINS_8
+ * - GPIO_PINS_9
+ * - GPIO_PINS_10
+ * - GPIO_PINS_11
+ * - GPIO_PINS_12
+ * - GPIO_PINS_13
+ * - GPIO_PINS_14
+ * - GPIO_PINS_15
+ * - GPIO_PINS_ALL
+ * @param new_state: new state of the slew rate.
+ * this parameter can be: true or false.
+ * @retval none
+ */
+void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state)
+{
+ if(new_state != FALSE)
+ {
+ gpio_x->hdrv |= pins;
+ }
+ else
+ {
+ gpio_x->hdrv &= ~pins;
+ }
+}
+
+/**
+ * @brief configure the pin's muxing function.
+ * @param gpio_x: to select the gpio peripheral.
+ * this parameter can be one of the following values:
+ * GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH.
+ * @param gpio_pin_source: specifies the pin for the muxing function.
+ * this parameter can be one of the following values:
+ * - GPIO_PINS_SOURCE0
+ * - GPIO_PINS_SOURCE1
+ * - GPIO_PINS_SOURCE2
+ * - GPIO_PINS_SOURCE3
+ * - GPIO_PINS_SOURCE4
+ * - GPIO_PINS_SOURCE5
+ * - GPIO_PINS_SOURCE6
+ * - GPIO_PINS_SOURCE7
+ * - GPIO_PINS_SOURCE8
+ * - GPIO_PINS_SOURCE9
+ * - GPIO_PINS_SOURCE10
+ * - GPIO_PINS_SOURCE11
+ * - GPIO_PINS_SOURCE12
+ * - GPIO_PINS_SOURCE13
+ * - GPIO_PINS_SOURCE14
+ * - GPIO_PINS_SOURCE15
+ * @param gpio_mux: select the pin to used as muxing function.
+ * this parameter can be one of the following values:
+ * - GPIO_MUX_0
+ * - GPIO_MUX_1
+ * - GPIO_MUX_2
+ * - GPIO_MUX_3
+ * - GPIO_MUX_4
+ * - GPIO_MUX_5
+ * - GPIO_MUX_6
+ * - GPIO_MUX_7
+ * - GPIO_MUX_8
+ * - GPIO_MUX_9
+ * - GPIO_MUX_10
+ * - GPIO_MUX_11
+ * - GPIO_MUX_12
+ * - GPIO_MUX_13
+ * - GPIO_MUX_14
+ * - GPIO_MUX_15
+ * @retval none
+ */
+void gpio_pin_mux_config(gpio_type *gpio_x, gpio_pins_source_type gpio_pin_source, gpio_mux_sel_type gpio_mux)
+{
+ uint32_t temp = 0x00;
+ uint32_t temp_2 = 0x00;
+
+ temp = ((uint32_t)(gpio_mux) << ((uint32_t)((uint32_t)gpio_pin_source & (uint32_t)0x07) * 4));
+ if(gpio_pin_source >> 0x03)
+ {
+ temp_2 = gpio_x->muxh;
+ temp_2 &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)gpio_pin_source & (uint32_t)0x07) * 4));
+ gpio_x->muxh = temp_2 | temp;
+ }
+ else
+ {
+ temp_2 = gpio_x->muxl;
+ temp_2 &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)gpio_pin_source & (uint32_t)0x07) * 4));
+ gpio_x->muxl = temp_2 | temp;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_i2c.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_i2c.c
new file mode 100644
index 00000000000..b8b6502e25f
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_i2c.c
@@ -0,0 +1,817 @@
+/**
+ **************************************************************************
+ * @file at32f45x_i2c.c
+ * @brief contains all the functions for the i2c firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup I2C
+ * @brief I2C driver modules
+ * @{
+ */
+
+#ifdef I2C_MODULE_ENABLED
+
+/** @defgroup I2C_private_functions
+ * @{
+ */
+
+/**
+ * @brief reset the i2c register
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @retval none
+ */
+void i2c_reset(i2c_type *i2c_x)
+{
+ if(i2c_x == I2C1)
+ {
+ crm_periph_reset(CRM_I2C1_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_I2C1_PERIPH_RESET, FALSE);
+ }
+ else if(i2c_x == I2C2)
+ {
+ crm_periph_reset(CRM_I2C2_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_I2C2_PERIPH_RESET, FALSE);
+ }
+ else if(i2c_x == I2C3)
+ {
+ crm_periph_reset(CRM_I2C3_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_I2C3_PERIPH_RESET, FALSE);
+ }
+}
+
+/**
+ * @brief init i2c digit filters and clock control register.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param dfilters: number of digit filters (0x00~0x0F).
+ * @param clk: i2c clock control register (0x00000000~0xFFFFFFFF).
+ * @retval none
+ */
+void i2c_init(i2c_type *i2c_x, uint8_t dfilters, uint32_t clk)
+{
+ /* disable i2c peripheral */
+ i2c_x->ctrl1_bit.i2cen = FALSE;
+
+ /* write clkctrl register*/
+ i2c_x->clkctrl = clk;
+
+ /* write digital filter register*/
+ i2c_x->ctrl1_bit.dflt = dfilters;
+}
+
+/**
+ * @brief config i2c own address 1.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param mode: i2c address mode.
+ * this parameter can be one of the following values:
+ * - I2C_ADDRESS_MODE_7BIT: 7bit address.
+ * - I2C_ADDRESS_MODE_10BIT: 10bit address.
+ * @param address: own address 1, such as 0xB0.
+ * @retval none
+ */
+void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t address)
+{
+ /* config address mode */
+ i2c_x->oaddr1_bit.addr1mode = mode;
+
+ /* config address */
+ i2c_x->oaddr1_bit.addr1 = address & 0x03FF;
+
+ /* enable address */
+ i2c_x->oaddr1_bit.addr1en = TRUE;
+}
+
+/**
+ * @brief config i2c own address 2 and mask.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param address: own address 1, such as 0xC0.
+ * @param mask: own address 2 mask.
+ * this parameter can be one of the following values:
+ * - I2C_ADDR2_NOMASK: compare bit [7:1].
+ * - I2C_ADDR2_MASK01: only compare bit [7:2].
+ * - I2C_ADDR2_MASK02: only compare bit [7:3].
+ * - I2C_ADDR2_MASK03: only compare bit [7:4].
+ * - I2C_ADDR2_MASK04: only compare bit [7:5].
+ * - I2C_ADDR2_MASK05: only compare bit [7:6].
+ * - I2C_ADDR2_MASK06: only compare bit [7].
+ * - I2C_ADDR2_MASK07: response all addresses other than those reserved for i2c.
+ * @retval none
+ */
+void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address, i2c_addr2_mask_type mask)
+{
+ i2c_x->oaddr2_bit.addr2mask = mask;
+
+ i2c_x->oaddr2_bit.addr2 = (address >> 1) & 0x7F;
+}
+
+/**
+ * @brief enable or disable own address 2.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_own_address2_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->oaddr2_bit.addr2en = new_state;
+}
+
+/**
+ * @brief enable or disable smbus mode.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param mode: smbus device mode.
+ * this parameter can be one of the following values:
+ * - I2C_SMBUS_MODE_DEVICE: smbus device.
+ * - I2C_SMBUS_MODE_HOST: smbus host.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_smbus_enable(i2c_type *i2c_x, i2c_smbus_mode_type mode, confirm_state new_state)
+{
+ switch (mode)
+ {
+ case I2C_SMBUS_MODE_DEVICE:
+ i2c_x->ctrl1_bit.devaddren = new_state;
+ break;
+ case I2C_SMBUS_MODE_HOST:
+ i2c_x->ctrl1_bit.haddren = new_state;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief enable or disable peripheral.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->ctrl1_bit.i2cen = new_state;
+}
+
+/**
+ * @brief enable or disable clock stretch.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_clock_stretch_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->ctrl1_bit.stretch = (!new_state);
+}
+
+/**
+ * @brief enable or disable ack.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none.
+ */
+void i2c_ack_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->ctrl2_bit.nacken = (!new_state);
+}
+
+/**
+ * @brief enable or disable 10-bit address mode (master transfer).
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_addr10_mode_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->ctrl2_bit.addr10 = new_state;
+}
+
+/**
+ * @brief config the slave address to be transmitted.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param address: slave address.
+ * @retval none
+ */
+void i2c_transfer_addr_set(i2c_type *i2c_x, uint16_t address)
+{
+ i2c_x->ctrl2_bit.saddr = address & 0x03FF;
+}
+
+/**
+ * @brief get the slave address to be transmitted.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @retval slave address
+ */
+uint16_t i2c_transfer_addr_get(i2c_type *i2c_x)
+{
+ return i2c_x->ctrl2_bit.saddr;
+}
+
+/**
+ * @brief config the master transfer direction.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param i2c_direction: transfer request direction.
+ * this parameter can be one of the following values:
+ * - I2C_DIR_TRANSMIT: master request a write transfer.
+ * - I2C_DIR_RECEIVE: master request a read transfer.
+ * @retval none
+ */
+void i2c_transfer_dir_set(i2c_type *i2c_x, i2c_transfer_dir_type i2c_direction)
+{
+ i2c_x->ctrl2_bit.dir = i2c_direction;
+}
+
+/**
+ * @brief slave get the i2c transfer direction.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @retval the value of the slave direction
+ * - I2C_DIR_TRANSMIT: master request a write transfer, slave enters receiver mode.
+ * - I2C_DIR_RECEIVE: master request a read transfer, slave enters transmitter mode.
+ */
+i2c_transfer_dir_type i2c_transfer_dir_get(i2c_type *i2c_x)
+{
+ if (i2c_x->sts_bit.sdir == 0)
+ {
+ return I2C_DIR_TRANSMIT;
+ }
+ else
+ {
+ return I2C_DIR_RECEIVE;
+ }
+}
+
+/**
+ * @brief get the i2c slave matched address.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @retval slave matched address.
+ */
+uint8_t i2c_matched_addr_get(i2c_type *i2c_x)
+{
+ return (i2c_x->sts_bit.addr << 1);
+}
+
+/**
+ * @brief enable or disable auto send stop mode.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_auto_stop_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->ctrl2_bit.astopen = new_state;
+}
+
+/**
+ * @brief enable or disable cnt reload mode.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_reload_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->ctrl2_bit.rlden = new_state;
+}
+
+/**
+ * @brief config the transfer cnt .
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param cnt: transfer cnt.
+ * @retval none
+ */
+void i2c_cnt_set(i2c_type *i2c_x, uint8_t cnt)
+{
+ i2c_x->ctrl2_bit.cnt = cnt;
+}
+
+/**
+ * @brief enable or disable read 10-bit header, this mode
+ * only used in 10-bit address mode read.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_addr10_header_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->ctrl2_bit.readh10 = new_state;
+}
+
+/**
+ * @brief enable or disable general call mode.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_general_call_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->ctrl1_bit.gcaen = new_state;
+}
+
+/**
+ * @brief drives the smbus alert pin high or low.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param level
+ * this parameter can be one of the following values:
+ * - I2C_SMBUS_ALERT_LOW: smbus alert set low.
+ * - I2C_SMBUS_ALERT_HIGH: smbus alert set high.
+ * @retval none
+ */
+void i2c_smbus_alert_set(i2c_type *i2c_x, i2c_smbus_alert_set_type level)
+{
+ i2c_x->ctrl1_bit.smbalert = level;
+}
+
+/**
+ * @brief enable or disable slave data control.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_slave_data_ctrl_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->ctrl1_bit.sctrl = new_state;
+}
+
+/**
+ * @brief enable or disable pec calculate.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_pec_calculate_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->ctrl1_bit.pecen = new_state;
+}
+
+/**
+ * @brief enable or disable pec transfer.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_pec_transmit_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->ctrl2_bit.pecten = new_state;
+}
+
+/**
+ * @brief get the i2c pec value.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @retval the value of the pec.
+ */
+uint8_t i2c_pec_value_get(i2c_type *i2c_x)
+{
+ return (uint8_t)(i2c_x->pec_bit.pecval);
+}
+
+/**
+ * @brief config the i2c bus timeout.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param timeout: timeout (0x0000~0x0FFF).
+ * @retval none
+ */
+void i2c_timeout_set(i2c_type *i2c_x, uint16_t timeout)
+{
+ i2c_x->timeout_bit.totime = timeout;
+}
+
+/**
+ * @brief config the bus timeout detcet level.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param level
+ * this parameter can be one of the following values:
+ * - I2C_TIMEOUT_DETCET_HIGH: detect high level timeout.
+ * - I2C_TIMEOUT_DETCET_LOW: detect low level timeout.
+ * @retval none
+ */
+void i2c_timeout_detcet_set(i2c_type *i2c_x, i2c_timeout_detcet_type mode)
+{
+ i2c_x->timeout_bit.tomode = mode;
+}
+
+/**
+ * @brief enable or disable bus timeout.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_timeout_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->timeout_bit.toen = new_state;
+}
+
+/**
+ * @brief config the i2c extend bus timeout.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param timeout: extend timeout (0x0000~0x0FFF).
+ * @retval none
+ */
+void i2c_ext_timeout_set(i2c_type *i2c_x, uint16_t timeout)
+{
+ i2c_x->timeout_bit.exttime = timeout;
+}
+
+/**
+ * @brief enable or disable extend bus timeout.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_ext_timeout_enable(i2c_type *i2c_x, confirm_state new_state)
+{
+ i2c_x->timeout_bit.exten = new_state;
+}
+
+/**
+ * @brief enable or disable interrupts.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param i2c_int: interrupts sources.
+ * this parameter can be one of the following values:
+ * - I2C_TD_INT: transmit data interrupt.
+ * - I2C_RD_INT: receive data interrupt.
+ * - I2C_ADDR_INT: address match interrupt.
+ * - I2C_ACKFIAL_INT: ack fail interrupt.
+ * - I2C_STOP_INT: stop detect interrupt.
+ * - I2C_TDC_INT: transmit data complete interrupt.
+ * - I2C_ERR_INT: bus error interrupt.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_interrupt_enable(i2c_type *i2c_x, uint32_t source, confirm_state new_state)
+{
+ if (new_state != FALSE)
+ {
+ i2c_x->ctrl1 |= source;
+ }
+ else
+ {
+ i2c_x->ctrl1 &= (uint32_t)~source;
+ }
+}
+
+/**
+ * @brief get interrupt status
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param source
+ * this parameter can be one of the following values:
+ * - I2C_TD_INT: transmit data interrupt.
+ * - I2C_RD_INT: receive data interrupt.
+ * - I2C_ADDR_INT: address match interrupt.
+ * - I2C_ACKFIAL_INT: ack fail interrupt.
+ * - I2C_STOP_INT: stop detect interrupt.
+ * - I2C_TDC_INT: transmit data complete interrupt.
+ * - I2C_ERR_INT: bus error interrupt.
+ * @retval flag_status (SET or RESET)
+ */
+flag_status i2c_interrupt_get(i2c_type *i2c_x, uint16_t source)
+{
+ if((i2c_x->ctrl1 & source) != RESET)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief enable or disable dma requests.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param dma_req: dma transfer request.
+ * this parameter can be one of the following values:
+ * - I2C_DMA_REQUEST_TX: dma transmit request.
+ * - I2C_DMA_REQUEST_RX: dma receive request.
+ * @param new_state (TRUE or FALSE).
+ * @retval none
+ */
+void i2c_dma_enable(i2c_type *i2c_x, i2c_dma_request_type dma_req, confirm_state new_state)
+{
+ if(dma_req == I2C_DMA_REQUEST_TX)
+ {
+ i2c_x->ctrl1_bit.dmaten = new_state;
+ }
+ else
+ {
+ i2c_x->ctrl1_bit.dmaren = new_state;
+ }
+}
+
+/**
+ * @brief config data transfer.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param address: slave address.
+ * @param cnt: transfer conuter(0~255)
+ * @param rld_stop: config reload and gen stop condition mode.
+ * this parameter can be one of the following values:
+ * - I2C_AUTO_STOP_MODE: auto generate stop mode.
+ * - I2C_SOFT_STOP_MODE: soft generate stop mode.
+ * - I2C_RELOAD_MODE: reload mode.
+ * @param start: config gen start condition mode.
+ * this parameter can be one of the following values:
+ * - I2C_WITHOUT_START: transfer data without start condition.
+ * - I2C_GEN_START_READ: read data and generate start.
+ * - I2C_GEN_START_WRITE: send data and generate start.
+ * @retval none
+ */
+void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_mode_type start)
+{
+ uint32_t temp;
+
+ /* copy ctrl2 value to temp */
+ temp = i2c_x->ctrl2;
+
+ /* clear ctrl2_bit specific bits */
+ temp &= ~0x03FF67FF;
+
+ /* transfer mode and address set */
+ temp |= address | rld_stop | start;
+
+ /* transfer counter set */
+ temp |= (uint32_t)cnt << 16;
+
+ /* update ctrl2 value */
+ i2c_x->ctrl2 = temp;
+}
+
+/**
+ * @brief generate start condition.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @retval none
+ */
+void i2c_start_generate(i2c_type *i2c_x)
+{
+ i2c_x->ctrl2_bit.genstart = TRUE;
+}
+
+/**
+ * @brief generate stop condition.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @retval none
+ */
+void i2c_stop_generate(i2c_type *i2c_x)
+{
+ i2c_x->ctrl2_bit.genstop = TRUE;
+}
+
+/**
+ * @brief send a byte through the i2c periph.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param data: byte to be transmitted.
+ * @retval none
+ */
+void i2c_data_send(i2c_type *i2c_x, uint8_t data)
+{
+ i2c_x->txdt = data;
+}
+
+/**
+ * @brief receive a byte through the i2c periph.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @retval the value of the received data.
+ */
+uint8_t i2c_data_receive(i2c_type *i2c_x)
+{
+ return (uint8_t)i2c_x->rxdt;
+}
+
+/**
+ * @brief get flag status.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - I2C_TDBE_FLAG: transmit data buffer empty flag.
+ * - I2C_TDIS_FLAG: send interrupt status.
+ * - I2C_RDBF_FLAG: receive data buffer full flag.
+ * - I2C_ADDRF_FLAG: 0~7 bit address match flag.
+ * - I2C_ACKFAIL_FLAG: acknowledge failure flag.
+ * - I2C_STOPF_FLAG: stop condition generation complete flag.
+ * - I2C_TDC_FLAG: transmit data complete flag.
+ * - I2C_TCRLD_FLAG: transmission is complete, waiting to load data.
+ * - I2C_BUSERR_FLAG: bus error flag.
+ * - I2C_ARLOST_FLAG: arbitration lost flag.
+ * - I2C_OUF_FLAG: overflow or underflow flag.
+ * - I2C_PECERR_FLAG: pec receive error flag.
+ * - I2C_TMOUT_FLAG: smbus timeout flag.
+ * - I2C_ALERTF_FLAG: smbus alert flag.
+ * - I2C_BUSYF_FLAG: bus busy flag transmission mode.
+ * - I2C_SDIR_FLAG: slave data transmit direction.
+ * @retval the new state of flag (SET or RESET).
+ */
+flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag)
+{
+ if((i2c_x->sts & flag) != RESET)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief get interrupt flag status.
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - I2C_TDBE_FLAG: transmit data buffer empty flag.
+ * - I2C_TDIS_FLAG: send interrupt status.
+ * - I2C_RDBF_FLAG: receive data buffer full flag.
+ * - I2C_ADDRF_FLAG: 0~7 bit address match flag.
+ * - I2C_ACKFAIL_FLAG: acknowledge failure flag.
+ * - I2C_STOPF_FLAG: stop condition generation complete flag.
+ * - I2C_TDC_FLAG: transmit data complete flag.
+ * - I2C_TCRLD_FLAG: transmission is complete, waiting to load data.
+ * - I2C_BUSERR_FLAG: bus error flag.
+ * - I2C_ARLOST_FLAG: arbitration lost flag.
+ * - I2C_OUF_FLAG: overflow or underflow flag.
+ * - I2C_PECERR_FLAG: pec receive error flag.
+ * - I2C_TMOUT_FLAG: smbus timeout flag.
+ * - I2C_ALERTF_FLAG: smbus alert flag.
+ * @retval the new state of flag (SET or RESET).
+ */
+flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag)
+{
+ __IO uint32_t iten = 0;
+
+ switch(flag)
+ {
+ case I2C_TDIS_FLAG:
+ iten = i2c_x->ctrl1_bit.tdien;
+ break;
+ case I2C_RDBF_FLAG:
+ iten = i2c_x->ctrl1_bit.rdien;
+ break;
+ case I2C_ADDRF_FLAG:
+ iten = i2c_x->ctrl1_bit.addrien;
+ break;
+ case I2C_ACKFAIL_FLAG:
+ iten = i2c_x->ctrl1_bit.ackfailien;
+ break;
+ case I2C_STOPF_FLAG:
+ iten = i2c_x->ctrl1_bit.stopien;
+ break;
+ case I2C_TDC_FLAG:
+ case I2C_TCRLD_FLAG:
+ iten = i2c_x->ctrl1_bit.tdcien;
+ break;
+ case I2C_BUSERR_FLAG:
+ case I2C_ARLOST_FLAG:
+ case I2C_OUF_FLAG:
+ case I2C_PECERR_FLAG:
+ case I2C_TMOUT_FLAG:
+ case I2C_ALERTF_FLAG:
+ iten = i2c_x->ctrl1_bit.errien;
+ break;
+
+ default:
+ break;
+ }
+
+ if(((i2c_x->sts & flag) != RESET) && (iten))
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief clear flag status
+ * @param i2c_x: to select the i2c peripheral.
+ * this parameter can be one of the following values:
+ * I2C1, I2C2, I2C3.
+ * @param flag: specifies the flag to clear.
+ * this parameter can be any combination of the following values:
+ * - I2C_ADDRF_FLAG: 0~7 bit address match flag.
+ * - I2C_ACKFAIL_FLAG: acknowledge failure flag.
+ * - I2C_STOPF_FLAG: stop condition generation complete flag.
+ * - I2C_BUSERR_FLAG: bus error flag.
+ * - I2C_ARLOST_FLAG: arbitration lost flag.
+ * - I2C_OUF_FLAG: overflow or underflow flag.
+ * - I2C_PECERR_FLAG: pec receive error flag.
+ * - I2C_TMOUT_FLAG: smbus timeout flag.
+ * - I2C_ALERTF_FLAG: smbus alert flag.
+ * @retval none
+ */
+void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag)
+{
+ i2c_x->clr = flag;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_misc.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_misc.c
new file mode 100644
index 00000000000..c63b6072deb
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_misc.c
@@ -0,0 +1,170 @@
+/**
+ **************************************************************************
+ * @file at32f45x_misc.c
+ * @brief contains all the functions for the misc firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup MISC
+ * @brief MISC driver modules
+ * @{
+ */
+
+#ifdef MISC_MODULE_ENABLED
+
+/** @defgroup MISC_private_functions
+ * @{
+ */
+
+#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
+
+/**
+ * @brief system reset
+ * @param none
+ * @retval none
+ */
+void nvic_system_reset(void)
+{
+ NVIC_SystemReset();
+}
+
+/**
+ * @brief enable nvic irq
+ * @param irqn (IRQn_Type number)
+ * @param preempt_priority: preemptive priority value (starting from 0)
+ * @param sub_priority: subpriority value (starting from 0)
+ * @retval none
+ */
+void nvic_irq_enable(IRQn_Type irqn, uint32_t preempt_priority, uint32_t sub_priority)
+{
+ uint32_t temp_priority = 0;
+
+ /* encode priority */
+ temp_priority = NVIC_EncodePriority(NVIC_GetPriorityGrouping(), preempt_priority, sub_priority);
+ /* set priority */
+ NVIC_SetPriority(irqn, temp_priority);
+ /* enable irqn */
+ NVIC_EnableIRQ(irqn);
+}
+
+/**
+ * @brief disable nvic irq number
+ * @param irqn (IRQn_Type number)
+ * @retval none
+ */
+void nvic_irq_disable(IRQn_Type irqn)
+{
+ NVIC_DisableIRQ(irqn);
+}
+
+/**
+ * @brief config nvic priority group
+ * @param priority_group
+ * this parameter can be one of the following values:
+ * - NVIC_PRIORITY_GROUP_0
+ * - NVIC_PRIORITY_GROUP_1
+ * - NVIC_PRIORITY_GROUP_2
+ * - NVIC_PRIORITY_GROUP_3
+ * - NVIC_PRIORITY_GROUP_4
+ * @retval none
+ */
+void nvic_priority_group_config(nvic_priority_group_type priority_group)
+{
+ /* set the prigroup[10:8] bits according to nvic_prioritygroup value */
+ NVIC_SetPriorityGrouping(priority_group);
+}
+
+/**
+ * @brief set the vector table location and offset.
+ * @param base
+ * this parameter can be one of the following values:
+ * - NVIC_VECTTAB_RAM
+ * - NVIC_VECTTAB_FLASH
+ * @param offset (vector table base offset field. this value must be a multiple of 0x200)
+ * @retval none
+ */
+void nvic_vector_table_set(uint32_t base, uint32_t offset)
+{
+ SCB->VTOR = base | (offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+ * @brief config nvic lowpower mode
+ * @param lp_mode
+ * this parameter can be one of the following values:
+ * - NVIC_LP_SEVONPEND
+ * - NVIC_LP_SLEEPDEEP
+ * - NVIC_LP_SLEEPONEXIT
+ * @param new_state (new state of lp condition. ENABLE or DISABLE)
+ * @retval none
+ */
+void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state new_state)
+{
+ if(new_state != FALSE)
+ {
+ SCB->SCR |= lp_mode;
+ }
+ else
+ {
+ SCB->SCR &= (uint32_t)(~(uint32_t)lp_mode);
+ }
+}
+
+/**
+ * @brief config systick clock source
+ * @param source
+ * this parameter can be one of the following values:
+ * - SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8
+ * - SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV
+ * @retval none
+ */
+void systick_clock_source_config(systick_clock_source_type source)
+{
+ if(source == SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV)
+ {
+ SysTick->CTRL |= SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV;
+ }
+ else
+ {
+ SysTick->CTRL &= ~(uint32_t)SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_pwc.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_pwc.c
new file mode 100644
index 00000000000..7a67674f520
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_pwc.c
@@ -0,0 +1,307 @@
+/**
+ **************************************************************************
+ * @file at32f45x_pwc.c
+ * @brief contains all the functions for the pwc firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup PWC
+ * @brief PWC driver modules
+ * @{
+ */
+
+#ifdef PWC_MODULE_ENABLED
+
+/** @defgroup PWC_private_functions
+ * @{
+ */
+
+/**
+ * @brief deinitialize the pwc peripheral registers to their default reset values.
+ * @param none
+ * @retval none
+ */
+void pwc_reset(void)
+{
+ crm_periph_reset(CRM_PWC_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_PWC_PERIPH_RESET, FALSE);
+}
+
+/**
+ * @brief enable or disable access to the battery powered domain.
+ * @param new_state: new state of battery powered domain access.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void pwc_battery_powered_domain_access(confirm_state new_state)
+{
+ PWC->ctrl_bit.bpwen= new_state;
+}
+
+/**
+ * @brief select the voltage threshold detected by the power voltage detector.
+ * @param pvm_voltage: select pwc pvm voltage
+ * this parameter can be one of the following values:
+ * - PWC_PVM_VOLTAGE_2V3
+ * - PWC_PVM_VOLTAGE_2V4
+ * - PWC_PVM_VOLTAGE_2V5
+ * - PWC_PVM_VOLTAGE_2V6
+ * - PWC_PVM_VOLTAGE_2V7
+ * - PWC_PVM_VOLTAGE_2V8
+ * - PWC_PVM_VOLTAGE_2V9
+ * @retval none
+ */
+void pwc_pvm_level_select(pwc_pvm_voltage_type pvm_voltage)
+{
+ PWC->ctrl_bit.pvmsel= pvm_voltage;
+}
+
+/**
+ * @brief enable or disable pwc power voltage monitor (pvm)
+ * @param new_state: new state of pvm.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void pwc_power_voltage_monitor_enable(confirm_state new_state)
+{
+ PWC->ctrl_bit.pvmen= new_state;
+}
+
+/**
+ * @brief set wakeup pin's polarity
+ * @param pin_num: choose the wakeup pin.
+ * this parameter can be be any combination of the following values:
+ * - PWC_WAKEUP_PIN_1
+ * - PWC_WAKEUP_PIN_2
+ * - PWC_WAKEUP_PIN_4
+ * - PWC_WAKEUP_PIN_5
+ * - PWC_WAKEUP_PIN_6
+ * - PWC_WAKEUP_PIN_7
+ * @param wakeup_pin_polarity: polarity of the standby wakeup pin.
+ * this parameter can be one of the following values:
+ * - PWC_RISING_EDGE_WAKEUP
+ * - PWC_FALLING_EDGE_WAKEUP
+ * @retval none
+ */
+void pwc_wakeup_pin_polarity_select(uint32_t pin_num, pwc_wakeup_pin_polarity_type wakeup_pin_polarity)
+{
+ if(wakeup_pin_polarity == PWC_FALLING_EDGE_WAKEUP)
+ {
+ PWC->ctrl |= pin_num << 8;
+ }
+ else
+ {
+ PWC->ctrl &= (uint32_t)~(pin_num << 8);
+ }
+}
+
+/**
+ * @brief enable or disable pwc standby wakeup pin
+ * @param pin_num: choose the wakeup pin.
+ * this parameter can be be any combination of the following values:
+ * - PWC_WAKEUP_PIN_1
+ * - PWC_WAKEUP_PIN_2
+ * - PWC_WAKEUP_PIN_4
+ * - PWC_WAKEUP_PIN_5
+ * - PWC_WAKEUP_PIN_6
+ * - PWC_WAKEUP_PIN_7
+ * @param new_state: new state of the standby wakeup pin.
+ * this parameter can be one of the following values:
+ * - TRUE
+ * - FALSE
+ * @retval none
+ */
+void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state)
+{
+ if(new_state == TRUE)
+ {
+ PWC->ctrl |= pin_num;
+ }
+ else
+ {
+ PWC->ctrl &= ~pin_num;
+ }
+}
+
+/**
+ * @brief clear flag of pwc
+ * @param pwc_flag: select the pwc flag.
+ * this parameter can be any combination of the following values:
+ * - PWC_WAKEUP_PIN1_FLAG
+ * - PWC_WAKEUP_PIN2_FLAG
+ * - PWC_WAKEUP_PIN4_FLAG
+ * - PWC_WAKEUP_PIN5_FLAG
+ * - PWC_WAKEUP_PIN6_FLAG
+ * - PWC_WAKEUP_PIN7_FLAG
+ * - PWC_STANDBY_FLAG
+ * - PWC_WAKEUP_INTERNAL_FLAG
+ * - note:"PWC_PVM_OUTPUT_FLAG" cannot be choose!this bit is readonly bit,it means the voltage monitoring output state
+ * @retval none
+ */
+void pwc_flag_clear(uint32_t pwc_flag)
+{
+ PWC->clr |= pwc_flag;
+}
+
+/**
+ * @brief get flag of pwc
+ * @param pwc_flag: select the pwc flag.
+ * this parameter can be one of the following values:
+ * - PWC_WAKEUP_PIN1_FLAG
+ * - PWC_WAKEUP_PIN2_FLAG
+ * - PWC_WAKEUP_PIN4_FLAG
+ * - PWC_WAKEUP_PIN5_FLAG
+ * - PWC_WAKEUP_PIN6_FLAG
+ * - PWC_WAKEUP_PIN7_FLAG
+ * - PWC_STANDBY_FLAG
+ * - PWC_PVM_OUTPUT_FLAG
+ * - PWC_WAKEUP_INTERNAL_FLAG
+ * @retval state of select flag(SET or RESET).
+ */
+flag_status pwc_flag_get(uint32_t pwc_flag)
+{
+ flag_status status = RESET;
+ if ((PWC->ctrlsts & pwc_flag) == RESET)
+ {
+ status = RESET;
+ }
+ else
+ {
+ status = SET;
+ }
+ return status;
+}
+
+/**
+ * @brief enter pwc sleep mode
+ * @param sleep_mode_enter: choose the instruction to enter sleep mode.
+ * this parameter can be one of the following values:
+ * - PWC_SLEEP_ENTER_WFI
+ * - PWC_SLEEP_ENTER_WFE
+ * @retval none
+ */
+void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter)
+{
+ SCB->SCR &= (uint32_t)~0x4;
+ if(pwc_sleep_enter == PWC_SLEEP_ENTER_WFE)
+ {
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+ else if(pwc_sleep_enter == PWC_SLEEP_ENTER_WFI)
+ {
+ __WFI();
+ }
+}
+
+/**
+ * @brief enter pwc deep-sleep mode
+ * @param pwc_deep_sleep_enter: choose the instruction to enter deep sleep mode.
+ * this parameter can be one of the following values:
+ * - PWC_DEEP_SLEEP_ENTER_WFI
+ * - PWC_DEEP_SLEEP_ENTER_WFE
+ * @retval none
+ */
+void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter)
+{
+ SCB->SCR |= 0x04;
+ if(pwc_deep_sleep_enter == PWC_DEEP_SLEEP_ENTER_WFE)
+ {
+ __SEV();
+ __WFE();
+ __WFE();
+ }
+ else if(pwc_deep_sleep_enter == PWC_DEEP_SLEEP_ENTER_WFI)
+ {
+ __WFI();
+ }
+ SCB->SCR &= (uint32_t)~0x4;
+}
+
+/**
+ * @brief regulate low power consumption in the deep sleep mode
+ * @param pwc_regulator: set the regulator state.
+ * this parameter can be one of the following values:
+ * - PWC_REGULATOR_ON
+ * - PWC_REGULATOR_LOW_POWER
+ * - PWC_REGULATOR_EXTRA_LOW_POWER
+ * @note: when using extra low power mode, it is prohibited to enable deepsleep_debug for debugging!
+ * @retval none
+ */
+void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator)
+{
+ switch(pwc_regulator)
+ {
+ case PWC_REGULATOR_ON:
+ PWC->ldoov_bit.vrexlpen = FALSE;
+ PWC->ctrl_bit.vrsel = FALSE;
+ break;
+ case PWC_REGULATOR_LOW_POWER:
+ PWC->ldoov_bit.vrexlpen = FALSE;
+ PWC->ctrl_bit.vrsel = TRUE;
+ break;
+ case PWC_REGULATOR_EXTRA_LOW_POWER:
+ PWC->ldoov_bit.vrexlpen = TRUE;
+ PWC->ctrl_bit.vrsel = TRUE;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief enter pwc standby mode
+ * @param none
+ * @retval none
+ */
+void pwc_standby_mode_enter(void)
+{
+ PWC->clr_bit.clswef = TRUE;
+ PWC->ctrl_bit.lpsel = TRUE;
+ SCB->SCR |= 0x04;
+#if defined (__CC_ARM)
+ __force_stores();
+#endif
+ while(1)
+ {
+ __WFI();
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_qspi.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_qspi.c
new file mode 100644
index 00000000000..c9cc49fc2a4
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_qspi.c
@@ -0,0 +1,488 @@
+/**
+ **************************************************************************
+ * @file at32f45x_qspi.c
+ * @brief contain all the functions for qspi firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup QSPI
+ * @brief QSPI driver modules
+ * @{
+ */
+
+#ifdef QSPI_MODULE_ENABLED
+
+/** @defgroup QSPI_private_functions
+ * @{
+ */
+
+/**
+ * @brief deinitialize the qspi peripheral registers to their default reset values.
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1.
+ * @retval none
+ */
+void qspi_reset(qspi_type* qspi_x)
+{
+ if(qspi_x == QSPI1)
+ {
+ crm_periph_reset(CRM_QSPI1_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_QSPI1_PERIPH_RESET, FALSE);
+ }
+}
+
+/**
+ * @brief enable/disable encryption for qspi.
+ * @note the function must be configured only when qspi in command-port mode!!!
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void qspi_encryption_enable(qspi_type* qspi_x, confirm_state new_state)
+{
+ qspi_x->ctrl_bit.keyen = new_state;
+}
+
+/**
+ * @brief set qspi sck mode.
+ * @note the function must be configured only when qspi in command-port mode!!!
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1.
+ * @param new_mode: new state to be set
+ * this parameter can be one of the following values:
+ * - QSPI_SCK_MODE_0
+ * - QSPI_SCK_MODE_3
+ * @retval none
+ */
+void qspi_sck_mode_set(qspi_type* qspi_x, qspi_clk_mode_type new_mode)
+{
+ qspi_x->ctrl_bit.sckmode = new_mode;
+}
+
+/**
+ * @brief set qspi clock division
+ * @note the function must be configured only when qspi in command-port mode!!!
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1.
+ * @param new_clkdiv: new division value
+ * this parameter can be one of the following values:
+ * - QSPI_CLK_DIV_2
+ * - QSPI_CLK_DIV_4
+ * - QSPI_CLK_DIV_6
+ * - QSPI_CLK_DIV_8
+ * - QSPI_CLK_DIV_3
+ * - QSPI_CLK_DIV_5
+ * - QSPI_CLK_DIV_10
+ * - QSPI_CLK_DIV_12
+ * @retval none
+ */
+void qspi_clk_division_set(qspi_type* qspi_x, qspi_clk_div_type new_clkdiv)
+{
+ qspi_x->ctrl_bit.clkdiv = new_clkdiv;
+}
+
+/**
+ * @brief enable/disable cache in xip mode
+ * @note the function must be configured only when qspi in command-port mode!!!
+ * the function only for applications in xip read-only(e.g. qspi flash)!!!
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1.
+ * @param new_state (TRUE or FALSE)
+ * TRUE: disable cache
+ * FALSE: enable cache
+ * @retval none
+ */
+void qspi_xip_cache_bypass_set(qspi_type* qspi_x, confirm_state new_state)
+{
+ qspi_x->xip_cmd_w3_bit.bypassc = new_state;
+}
+
+/**
+ * @brief enable/disable interrupt when command is completed
+ * @note the function must be configured only when qspi in command-port mode!!!
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state)
+{
+ qspi_x->ctrl2_bit.cmdie = new_state;
+}
+
+/**
+ * @brief get status flags.
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1.
+ * @param flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - QSPI_RXFIFORDY_FLAG
+ * - QSPI_TXFIFORDY_FLAG
+ * - QSPI_CMDSTS_FLAG
+ * @retval the new state of the flag (SET or RESET).
+ */
+flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag)
+{
+ flag_status bit_status = RESET;
+ switch(flag)
+ {
+ case QSPI_RXFIFORDY_FLAG:
+ bit_status = (flag_status)qspi_x->fifosts_bit.rxfifordy;
+ break;
+ case QSPI_TXFIFORDY_FLAG:
+ bit_status = (flag_status)qspi_x->fifosts_bit.txfifordy;
+ break;
+ case QSPI_CMDSTS_FLAG:
+ bit_status = (flag_status)qspi_x->cmdsts_bit.cmdsts;
+ break;
+ default:
+ break;
+ }
+ return bit_status;
+}
+
+/**
+ * @brief get interrupt flags.
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1.
+ * @param flag: only QSPI_CMDSTS_FLAG valid.
+ * @retval the new state of the flag (SET or RESET).
+ */
+flag_status qspi_interrupt_flag_get(qspi_type* qspi_x, uint32_t flag)
+{
+ if(QSPI_CMDSTS_FLAG != flag)
+ return RESET;
+ if(qspi_x->cmdsts_bit.cmdsts && qspi_x->ctrl2_bit.cmdie)
+ return SET;
+ else
+ return RESET;
+}
+
+/**
+ * @brief clear flags
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1.
+ * @param flag: flags to be clear
+ * this parameter can be one of the following values:
+ * - QSPI_CMDSTS_FLAG
+ * @retval none
+ */
+void qspi_flag_clear(qspi_type* qspi_x, uint32_t flag)
+{
+ qspi_x->cmdsts = flag;
+}
+
+/**
+ * @brief set dma threshold for dma rx
+ * @note the function must be configured only when qspi in command-port mode!!!
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1.
+ * @param new_threshold: value to set
+ * this parameter can be one of the following values:
+ * - QSPI_DMA_FIFO_THOD_WORD08
+ * - QSPI_DMA_FIFO_THOD_WORD16
+ * - QSPI_DMA_FIFO_THOD_WORD24
+ * @retval none
+ */
+void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold)
+{
+ qspi_x->ctrl2_bit.rxfifo_thod = new_threshold;
+}
+
+/**
+ * @brief set dma threshold for dma tx
+ * @note the function must be configured only when qspi in command-port mode!!!
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1.
+ * @param new_threshold: value to set
+ * this parameter can be one of the following values:
+ * - QSPI_DMA_FIFO_THOD_WORD08
+ * - QSPI_DMA_FIFO_THOD_WORD16
+ * - QSPI_DMA_FIFO_THOD_WORD24
+ * @retval none
+ */
+void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold)
+{
+ qspi_x->ctrl2_bit.txfifo_thod = new_threshold;
+}
+
+/**
+ * @brief enable/disable dma transfer
+ * @note the function must be configured only when qspi in command-port mode!!!
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void qspi_dma_enable(qspi_type* qspi_x, confirm_state new_state)
+{
+ qspi_x->ctrl2_bit.dmaen = new_state;
+}
+
+/**
+ * @brief set wip position in status register of flash
+ * @note the function must be configured only when qspi in command-port mode!!!
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1.
+ * @param busy_pos: value to set
+ * this parameter can be one of the following values:
+ * - QSPI_BUSY_OFFSET_0
+ * - QSPI_BUSY_OFFSET_1
+ * - QSPI_BUSY_OFFSET_2
+ * - QSPI_BUSY_OFFSET_3
+ * - QSPI_BUSY_OFFSET_4
+ * - QSPI_BUSY_OFFSET_5
+ * - QSPI_BUSY_OFFSET_6
+ * - QSPI_BUSY_OFFSET_7
+ * @retval none
+ */
+void qspi_busy_config(qspi_type* qspi_x, qspi_busy_pos_type busy_pos)
+{
+ qspi_x->ctrl_bit.busy = busy_pos;
+}
+
+/**
+ * @brief enable xip mode or command-port mode.
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void qspi_xip_enable(qspi_type* qspi_x, confirm_state new_state)
+{
+ register uint16_t dly=0;
+ /* skip if state is no change */
+ if(new_state == (confirm_state)(qspi_x->ctrl_bit.xipsel))
+ {
+ return;
+ }
+
+ /* wait until tx fifo is empty*/
+ while(qspi_x->fifosts_bit.txfifordy == 0);
+
+ /* make sure IO is transmitted */
+ dly = 64;
+ while(dly--)
+ {
+ __NOP();
+ }
+
+ /* flush and reset qspi state */
+ qspi_x->ctrl_bit.xiprcmdf = 1;
+
+ /* wait until action is finished */
+ while(qspi_x->ctrl_bit.abort);
+
+ /* make sure IO is transmitted */
+ dly = 64;
+ while(dly--)
+ {
+ __NOP();
+ }
+ /* set xip mode to new state */
+ qspi_x->ctrl_bit.xipsel = new_state;
+
+ /* wait until abort is not set */
+ while(qspi_x->ctrl_bit.abort);
+
+ /* wait until cache status valid*/
+ if(new_state == TRUE)
+ {
+ while( qspi_x->xip_cmd_w3_bit.csts );
+ }
+}
+
+/**
+ * @brief set command-port and qspi_x will start to work
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1.
+ * @param qspi_cmd_struct: pointer to qspi cmd structure
+ * @retval none
+ */
+void qspi_cmd_operation_kick(qspi_type* qspi_x, qspi_cmd_type* qspi_cmd_struct)
+{
+ uint32_t w1_val = 0, w3_val = 0;
+
+ /* config analyse cmd_w0 register */
+ qspi_x->cmd_w0 = (uint32_t)qspi_cmd_struct->address_code;
+
+ /* config analyse cmd_w1 register */
+ w1_val = (uint32_t)qspi_cmd_struct->address_length;
+ w1_val |= (uint32_t)(qspi_cmd_struct->second_dummy_cycle_num << 16);
+ w1_val |= (uint32_t)(qspi_cmd_struct->instruction_length << 24);
+ w1_val |= (uint32_t)(qspi_cmd_struct->pe_mode_enable << 28);
+ qspi_x->cmd_w1 = w1_val;
+
+ /* config analyse cmd_w2 register */
+ qspi_x->cmd_w2 = (uint32_t)qspi_cmd_struct->data_counter;
+
+ /* config analyse cmd_w3 register */
+ w3_val = (uint32_t)(qspi_cmd_struct->write_data_enable << 1);
+ w3_val |= (uint32_t)(qspi_cmd_struct->read_status_enable << 2);
+ w3_val |= (uint32_t)(qspi_cmd_struct->read_status_config << 3);
+ w3_val |= (uint32_t)(qspi_cmd_struct->operation_mode << 5);
+ w3_val |= (uint32_t)(qspi_cmd_struct->pe_mode_operate_code << 16);
+ w3_val |= (uint32_t)(qspi_cmd_struct->instruction_code << 24);
+ qspi_x->cmd_w3 = w3_val;
+}
+
+/**
+ * @brief initial xip mode for qspi_x
+ * @param qspi_x: select the qspi peripheral.
+ * this parameter can be one of the following values:
+ * QSPI1.
+ * @param xip_init_struct: pointer to xip init structure.
+ * @retval none.
+ */
+void qspi_xip_init(qspi_type* qspi_x, qspi_xip_type* xip_init_struct)
+{
+ uint32_t xc0_val = 0, xc1_val = 0, xc2_val = 0;
+ /* config analyse xip_cmd_w0 register */
+ xc0_val = (uint32_t)xip_init_struct->read_second_dummy_cycle_num;
+ xc0_val |= (uint32_t)(xip_init_struct->read_operation_mode << 8);
+ xc0_val |= (uint32_t)(xip_init_struct->read_address_length << 11);
+ xc0_val |= (uint32_t)(xip_init_struct->read_instruction_code << 12);
+ qspi_x->xip_cmd_w0 = xc0_val;
+
+ /* config analyse xip_cmd_w1 register */
+ xc1_val = (uint32_t)xip_init_struct->write_second_dummy_cycle_num;
+ xc1_val |= (uint32_t)(xip_init_struct->write_operation_mode << 8);
+ xc1_val |= (uint32_t)(xip_init_struct->write_address_length << 11);
+ xc1_val |= (uint32_t)(xip_init_struct->write_instruction_code << 12);
+ qspi_x->xip_cmd_w1 = xc1_val;
+
+ /* config analyse xip_cmd_w2 register */
+ xc2_val = (uint32_t)xip_init_struct->read_data_counter;
+ xc2_val |= (uint32_t)(xip_init_struct->read_time_counter << 8);
+ xc2_val |= (uint32_t)(xip_init_struct->read_select_mode << 15);
+ xc2_val |= (uint32_t)(xip_init_struct->write_data_counter << 16);
+ xc2_val |= (uint32_t)(xip_init_struct->write_time_counter << 24);
+ xc2_val |= (uint32_t)(xip_init_struct->write_select_mode << 31);
+ qspi_x->xip_cmd_w2 = xc2_val;
+}
+
+/**
+ * @brief read one byte from qspi device in command mode
+ * @param qspi_x: select the qspi peripheral.
+ * @retval 8-bit data.
+ */
+uint8_t qspi_byte_read(qspi_type* qspi_x)
+{
+ return qspi_x->dt_u8;
+}
+
+/**
+ * @brief read one half-word from qspi device in command mode
+ * @param qspi_x: select the qspi peripheral.
+ * @retval 16-bit data.
+ */
+uint16_t qspi_half_word_read(qspi_type* qspi_x)
+{
+ return qspi_x->dt_u16;
+}
+
+/**
+ * @brief read one word from qspi device in command mode
+ * @param qspi_x: select the qspi peripheral.
+ * @retval 32-bit data.
+ */
+uint32_t qspi_word_read(qspi_type* qspi_x)
+{
+ return qspi_x->dt;
+}
+
+/**
+ * @brief write one byte to qspi device in command mode
+ * @param qspi_x: select the qspi peripheral.
+ * @param value: 8-bit data.
+ * @retval none.
+ */
+void qspi_byte_write(qspi_type* qspi_x, uint8_t value)
+{
+ qspi_x->dt_u8 = value;
+}
+
+/**
+ * @brief write one half-word to qspi device in command mode
+ * @param qspi_x: select the qspi peripheral.
+ * @param value: 16-bit data.
+ * @retval none.
+ */
+void qspi_half_word_write(qspi_type* qspi_x, uint16_t value)
+{
+ qspi_x->dt_u16 = value;
+}
+
+/**
+ * @brief write one word to qspi device in command mode
+ * @param qspi_x: select the qspi peripheral.
+ * @param value: 32-bit data.
+ * @retval none.
+ */
+void qspi_word_write(qspi_type* qspi_x, uint32_t value)
+{
+ qspi_x->dt = value;
+}
+
+/**
+ * @brief enable auto input sampling phase correction
+ * @param qspi_x: select the qspi peripheral.
+ * @retval none.
+ */
+void qspi_auto_ispc_enable(qspi_type* qspi_x)
+{
+ qspi_x->ctrl3_bit.ispc = TRUE;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_scfg.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_scfg.c
new file mode 100644
index 00000000000..d161377b40d
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_scfg.c
@@ -0,0 +1,295 @@
+/**
+ **************************************************************************
+ * @file at32f45x_scfg.c
+ * @brief contains all the functions for the system config firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup SCFG
+ * @brief SCFG driver modules
+ * @{
+ */
+
+#ifdef SCFG_MODULE_ENABLED
+
+/** @defgroup SCFG_private_functions
+ * @{
+ */
+
+/**
+ * @brief scfg reset
+ * @param none
+ * @retval none
+ */
+void scfg_reset(void)
+{
+ crm_periph_reset(CRM_SCFG_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_SCFG_PERIPH_RESET, FALSE);
+}
+
+/**
+ * @brief scfg xmc address mapping swap set
+ * @param xmc_swap
+ * this parameter can be one of the following values:
+ * - SCFG_XMC_SWAP_NONE
+ * - SCFG_XMC_SWAP_MODE1
+ * @retval none
+ */
+void scfg_xmc_mapping_swap_set(scfg_xmc_swap_type xmc_swap)
+{
+ SCFG->cfg1_bit.swap_xmc = xmc_swap;
+}
+
+/**
+ * @brief scfg qspi address mapping swap set
+ * @param qspi_swap
+ * this parameter can be one of the following values:
+ * - SCFG_QSPI_SWAP_NONE
+ * - SCFG_QSPI_SWAP_MODE1
+ * @retval none
+ */
+void scfg_qspi_mapping_swap_set(scfg_qspi_swap_type qspi_swap)
+{
+ SCFG->cfg1_bit.swap_qspi = qspi_swap;
+}
+
+/**
+ * @brief scfg infrared config
+ * @param source
+ * this parameter can be one of the following values:
+ * - SCFG_IR_SOURCE_TMR10
+ * @param polarity
+ * this parameter can be one of the following values:
+ * - SCFG_IR_POLARITY_NO_AFFECTE
+ * - SCFG_IR_POLARITY_REVERSE
+ * @retval none
+ */
+void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type polarity)
+{
+ SCFG->cfg1_bit.ir_src_sel = source;
+ SCFG->cfg1_bit.ir_pol = polarity;
+}
+
+/**
+ * @brief scfg memory address mapping get
+ * @param none
+ * @retval return parameter can be one of the following values:
+ * - SCFG_MEM_MAP_MAIN_MEMORY
+ * - SCFG_MEM_MAP_BOOT_MEMORY
+ * - SCFG_MEM_MAP_INTERNAL_SRAM
+ */
+scfg_mem_map_type scfg_mem_map_get(void)
+{
+ if(SCFG->cfg1_bit.mem_map_sel & 0x1)
+ {
+ return (scfg_mem_map_type)SCFG->cfg1_bit.mem_map_sel;
+ }
+ return SCFG_MEM_MAP_MAIN_MEMORY;
+}
+
+/**
+ * @brief cm4f lockup enable
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void scfg_lockup_enable(confirm_state new_state)
+{
+ SCFG->cfg2_bit.lockup_lk = new_state;
+}
+
+/**
+ * @brief power voltage monitoring lock enable
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void scfg_pvm_lock_enable(confirm_state new_state)
+{
+ SCFG->cfg2_bit.pvm_lk = new_state;
+}
+
+/**
+ * @brief scfg sram odd parity error status get
+ * @param none
+ * @retval return sram odd parity error status(SET or RESET)
+ */
+flag_status scfg_sram_operr_status_get(void)
+{
+ return (flag_status)SCFG->cfg2_bit.sram_operr_sts;
+}
+
+/**
+ * @brief scfg sram odd parity error lock enable
+ * @param new_state: new state of the flash access protection.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void scfg_sram_operr_lock_enable(confirm_state new_state)
+{
+ SCFG->cfg2_bit.sram_operr_lk = new_state;
+}
+
+/**
+ * @brief can timestamp counting source set
+ * @param usart_index
+ * this parameter can be one of the following values:
+ * - SCFG_CAN1
+ * - SCFG_CAN2
+ * - SCFG_CAN3
+ * @param count_source
+ * this parameter can be one of the following values:
+ * - SCFG_CAN_TIMESTAMP_TMR3
+ * - SCFG_CAN_TIMESTAMP_TMR5
+ * @retval none
+ */
+void scfg_can_timestamp_source_set(scfg_can_type can_index, scfg_can_timestamp_source_type source)
+{
+ switch (can_index)
+ {
+ case SCFG_CAN1:
+ SCFG->cfg2_bit.can1_tst_sel = source;
+ break;
+ case SCFG_CAN2:
+ SCFG->cfg2_bit.can2_tst_sel = source;
+ break;
+ case SCFG_CAN3:
+ SCFG->cfg2_bit.can3_tst_sel = source;
+ break;
+ }
+}
+
+/**
+ * @brief scfg emac interface set
+ * @param mode
+ * this parameter can be one of the following values:
+ * - SCFG_EMAC_SELECT_MII
+ * - SCFG_EMAC_SELECT_RMII
+ * @retval none
+ */
+void scfg_emac_interface_set(scfg_emac_interface_type mode)
+{
+ SCFG->cfg2_bit.mii_rmii_sel = mode;
+}
+
+/**
+ * @brief select the gpio pin used as exint line.
+ * @param port_source:
+ * select the gpio port to be used as source for exint lines.
+ * this parameter can be one of the following values:
+ * - SCFG_PORT_SOURCE_GPIOA
+ * - SCFG_PORT_SOURCE_GPIOB
+ * - SCFG_PORT_SOURCE_GPIOC
+ * - SCFG_PORT_SOURCE_GPIOD
+ * - SCFG_PORT_SOURCE_GPIOE
+ * - SCFG_PORT_SOURCE_GPIOF
+ * - SCFG_PORT_SOURCE_GPIOG
+ * - SCFG_PORT_SOURCE_GPIOH
+ * @param pin_source:
+ * specifies the exint line to be configured.
+ * this parameter can be one of the following values:
+ * - SCFG_PINS_SOURCE0
+ * - SCFG_PINS_SOURCE1
+ * - SCFG_PINS_SOURCE2
+ * - SCFG_PINS_SOURCE3
+ * - SCFG_PINS_SOURCE4
+ * - SCFG_PINS_SOURCE5
+ * - SCFG_PINS_SOURCE6
+ * - SCFG_PINS_SOURCE7
+ * - SCFG_PINS_SOURCE8
+ * - SCFG_PINS_SOURCE9
+ * - SCFG_PINS_SOURCE10
+ * - SCFG_PINS_SOURCE11
+ * - SCFG_PINS_SOURCE12
+ * - SCFG_PINS_SOURCE13
+ * - SCFG_PINS_SOURCE14
+ * - SCFG_PINS_SOURCE15
+ * @retval none
+ */
+void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source)
+{
+ uint32_t tmp = 0x00;
+ tmp = ((uint32_t)0x0F) << (0x04 * (pin_source & (uint8_t)0x03));
+
+ switch (pin_source >> 0x02)
+ {
+ case 0:
+ SCFG->exintc1 &= ~tmp;
+ SCFG->exintc1 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
+ break;
+ case 1:
+ SCFG->exintc2 &= ~tmp;
+ SCFG->exintc2 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
+ break;
+ case 2:
+ SCFG->exintc3 &= ~tmp;
+ SCFG->exintc3 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
+ break;
+ case 3:
+ SCFG->exintc4 &= ~tmp;
+ SCFG->exintc4 |= (((uint32_t)port_source) << (0x04 * (pin_source & (uint8_t)0x03)));
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief enable or disable gpio pins ultra driven.
+ * @param value:
+ * this parameter can be one of the following values:
+ * - SCFG_ULTRA_DRIVEN_PB9
+ * - SCFG_ULTRA_DRIVEN_PB8
+ * - SCFG_ULTRA_DRIVEN_PD12
+ * - SCFG_ULTRA_DRIVEN_PD13
+ * - SCFG_ULTRA_DRIVEN_PD14
+ * - SCFG_ULTRA_DRIVEN_PD15
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void scfg_pins_ultra_driven_enable(scfg_ultra_driven_pins_type value, confirm_state new_state)
+{
+ if(TRUE == new_state)
+ {
+ SCFG_REG(value) |= SCFG_REG_BIT(value);
+ }
+ else
+ {
+ SCFG_REG(value) &= ~(SCFG_REG_BIT(value));
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_sdio.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_sdio.c
new file mode 100644
index 00000000000..82e16baebf2
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_sdio.c
@@ -0,0 +1,617 @@
+/**
+ **************************************************************************
+ * @file at32f45x_sdio.c
+ * @brief contains all the functions for the sdio firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup SDIO
+ * @brief SDIO driver modules
+ * @{
+ */
+
+#ifdef SDIO_MODULE_ENABLED
+
+/** @defgroup SDIO_private_functions
+ * @{
+ */
+
+/**
+ * @brief reset the sdio register
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @retval none
+ */
+void sdio_reset(sdio_type *sdio_x)
+{
+ sdio_x->pwrctrl = 0x0;
+ sdio_x->clkctrl = 0x0;
+ sdio_x->argu = 0x0;
+ sdio_x->cmdctrl = 0x0;
+ sdio_x->dttmr = 0x0;
+ sdio_x->dtlen = 0x0;
+ sdio_x->dtctrl = 0x0;
+ sdio_x->inten = 0x0;
+ sdio_x->intclr = 0x004007FF;
+}
+
+/**
+ * @brief set the power status of the controller
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @param power_state
+ * this parameter can be one of the following values:
+ * - SDIO_POWER_OFF
+ * - SDIO_POWER_ON
+ * @retval none
+ */
+void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state)
+{
+ sdio_x->pwrctrl_bit.ps = power_state;
+}
+
+/**
+ * @brief get power status.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @retval sdio_power_state_type (SDIO_POWER_ON or SDIO_POWER_OFF)
+ */
+sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x)
+{
+ return (sdio_power_state_type)(sdio_x->pwrctrl_bit.ps);
+}
+
+/**
+ * @brief config sdio clock
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @param clk_div: sdio clock divide factor(frequency = sdio_clk / [clk_psc + 2]).
+ * @param clk_edg
+ * this parameter can be one of the following values:
+ * - SDIO_CLOCK_EDGE_RISING
+ * - SDIO_CLOCK_EDGE_FALLING
+ * @retval none
+ */
+void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg)
+{
+ /* config clock edge */
+ sdio_x->clkctrl_bit.clkegs = clk_edg;
+
+ /* config clock divide [7:0] */
+ sdio_x->clkctrl_bit.clkdiv_l = (clk_div & 0xFF);
+
+ /* config clock divide [9:8] */
+ sdio_x->clkctrl_bit.clkdiv_h = ((clk_div & 0x300) >> 8);
+}
+
+/**
+ * @brief config sdio bus width
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @param width
+ * this parameter can be one of the following values:
+ * - SDIO_BUS_WIDTH_D1
+ * - SDIO_BUS_WIDTH_D4
+ * - SDIO_BUS_WIDTH_D8
+ * @retval none
+ */
+void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width)
+{
+ sdio_x->clkctrl_bit.busws = width;
+}
+
+/**
+ * @brief enable or disable clock divider bypss
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state)
+{
+ sdio_x->clkctrl_bit.bypsen = new_state;
+}
+
+/**
+ * @brief enable or disable power saving mode, config sdio_ck clock output
+ * when the bus is idle.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void sdio_power_saving_mode_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+ sdio_x->clkctrl_bit.pwrsven = new_state;
+}
+
+/**
+ * @brief enable or disable hardware flow control.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void sdio_flow_control_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+ sdio_x->clkctrl_bit.hfcen = new_state;
+}
+
+/**
+ * @brief enable or disable sdio_ck output.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+ sdio_x->clkctrl_bit.clkoen = new_state;
+}
+
+/**
+ * @brief enable or disable dma.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+ sdio_x->dtctrl_bit.dmaen = new_state;
+}
+
+/**
+ * @brief config corresponding interrupt.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @param int_opt
+ * this parameter can be one of the following values:
+ * - SDIO_CMDFAIL_INT
+ * - SDIO_DTFAIL_INT
+ * - SDIO_CMDTIMEOUT_INT
+ * - SDIO_DTTIMEOUT_INT
+ * - SDIO_TXERRU_INT
+ * - SDIO_RXERRO_INT
+ * - SDIO_CMDRSPCMPL_INT
+ * - SDIO_CMDCMPL_INT
+ * - SDIO_DTCMP_INT
+ * - SDIO_SBITERR_INT
+ * - SDIO_DTBLKCMPL_INT
+ * - SDIO_DOCMD_INT
+ * - SDIO_DOTX_INT
+ * - SDIO_DORX_INT
+ * - SDIO_TXBUFH_INT
+ * - SDIO_RXBUFH_INT
+ * - SDIO_TXBUFF_INT
+ * - SDIO_RXBUFF_INT
+ * - SDIO_TXBUFE_INT
+ * - SDIO_RXBUFE_INT
+ * - SDIO_TXBUF_INT
+ * - SDIO_RXBUF_INT
+ * - SDIO_SDIOIF_INT
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state new_state)
+{
+ /* enable interrupt */
+ if(TRUE == new_state)
+ {
+ sdio_x->inten |= int_opt;
+ }
+ /* disable interrupt */
+ else
+ {
+ sdio_x->inten &= ~(int_opt);
+ }
+}
+
+/**
+ * @brief get sdio interrupt flag.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @param flag
+ * this parameter can be one of the following values:
+ * - SDIO_CMDFAIL_FLAG
+ * - SDIO_DTFAIL_FLAG
+ * - SDIO_CMDTIMEOUT_FLAG
+ * - SDIO_DTTIMEOUT_FLAG
+ * - SDIO_TXERRU_FLAG
+ * - SDIO_RXERRO_FLAG
+ * - SDIO_CMDRSPCMPL_FLAG
+ * - SDIO_CMDCMPL_FLAG
+ * - SDIO_DTCMPL_FLAG
+ * - SDIO_SBITERR_FLAG
+ * - SDIO_DTBLKCMPL_FLAG
+ * - SDIO_DOCMD_FLAG
+ * - SDIO_DOTX_FLAG
+ * - SDIO_DORX_FLAG
+ * - SDIO_TXBUFH_FLAG
+ * - SDIO_RXBUFH_FLAG
+ * - SDIO_TXBUFF_FLAG
+ * - SDIO_RXBUFF_FLAG
+ * - SDIO_TXBUFE_FLAG
+ * - SDIO_RXBUFE_FLAG
+ * - SDIO_TXBUF_FLAG
+ * - SDIO_RXBUF_FLAG
+ * - SDIO_SDIOIF_FLAG
+ * @retval flag_status (SET or RESET)
+ */
+flag_status sdio_interrupt_flag_get(sdio_type *sdio_x, uint32_t flag)
+{
+ flag_status status = RESET;
+
+ if((sdio_x->inten & flag) && (sdio_x->sts & flag))
+ {
+ status = SET;
+ }
+
+ return status;
+}
+
+/**
+ * @brief get sdio flag.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @param flag
+ * this parameter can be one of the following values:
+ * - SDIO_CMDFAIL_FLAG
+ * - SDIO_DTFAIL_FLAG
+ * - SDIO_CMDTIMEOUT_FLAG
+ * - SDIO_DTTIMEOUT_FLAG
+ * - SDIO_TXERRU_FLAG
+ * - SDIO_RXERRO_FLAG
+ * - SDIO_CMDRSPCMPL_FLAG
+ * - SDIO_CMDCMPL_FLAG
+ * - SDIO_DTCMPL_FLAG
+ * - SDIO_SBITERR_FLAG
+ * - SDIO_DTBLKCMPL_FLAG
+ * - SDIO_DOCMD_FLAG
+ * - SDIO_DOTX_FLAG
+ * - SDIO_DORX_FLAG
+ * - SDIO_TXBUFH_FLAG
+ * - SDIO_RXBUFH_FLAG
+ * - SDIO_TXBUFF_FLAG
+ * - SDIO_RXBUFF_FLAG
+ * - SDIO_TXBUFE_FLAG
+ * - SDIO_RXBUFE_FLAG
+ * - SDIO_TXBUF_FLAG
+ * - SDIO_RXBUF_FLAG
+ * - SDIO_SDIOIF_FLAG
+ * @retval flag_status (SET or RESET)
+ */
+flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag)
+{
+ flag_status status = RESET;
+
+ if((sdio_x->sts & flag) == flag)
+ {
+ status = SET;
+ }
+ else
+ {
+ status = RESET;
+ }
+
+ return status;
+}
+
+/**
+ * @brief clear sdio flag.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @param int_opt
+ * this parameter can be any combination of the following values:
+ * - SDIO_CMDFAIL_FLAG
+ * - SDIO_DTFAIL_FLAG
+ * - SDIO_CMDTIMEOUT_FLAG
+ * - SDIO_DTTIMEOUT_FLAG
+ * - SDIO_TXERRU_FLAG
+ * - SDIO_RXERRO_FLAG
+ * - SDIO_CMDRSPCMPL_FLAG
+ * - SDIO_CMDCMPL_FLAG
+ * - SDIO_DTCMPL_FLAG
+ * - SDIO_SBITERR_FLAG
+ * - SDIO_DTBLKCMPL_FLAG
+ * - SDIO_SDIOIF_FLAG
+ * @retval none
+ */
+void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag)
+{
+ sdio_x->intclr = flag;
+}
+
+/**
+ * @brief config sdio command.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @param command_struct : pointer to a sdio_command_struct_type structure
+ * that contains the configuration information for the sdio command.
+ * @retval none
+ */
+void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct)
+{
+ /* disable command path state machine */
+ sdio_x->cmdctrl_bit.ccsmen = FALSE;
+
+ /* config command argument */
+ sdio_x->argu = command_struct->argument;
+
+ /* config command register */
+ sdio_x->cmdctrl_bit.cmdidx = command_struct->cmd_index;
+ sdio_x->cmdctrl_bit.rspwt = command_struct->rsp_type;
+ sdio_x->cmdctrl_bit.intwt = (command_struct->wait_type & 0x1); /* [1:0] -> [0] */
+ sdio_x->cmdctrl_bit.pndwt = (command_struct->wait_type & 0x2)>>1; /* [1:0] -> [1] */
+}
+
+/**
+ * @brief enable or disable command path state machine(CPSM).
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+ sdio_x->cmdctrl_bit.ccsmen = new_state;
+}
+
+/**
+ * @brief get command index of last command for which response received.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @param new_state (TRUE or FALSE)
+ * @retval uint8_t: command index
+ */
+uint8_t sdio_command_response_get(sdio_type *sdio_x)
+{
+ return sdio_x->rspcmd_bit.rspcmd;
+}
+
+/**
+ * @brief get response received from the card for the last command.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @param reg_index
+ * this parameter can be one of the following values:
+ * - SDIO_RSP1_INDEX
+ * - SDIO_RSP2_INDEX
+ * - SDIO_RSP3_INDEX
+ * - SDIO_RSP4_INDEX
+ * @retval uint32_t: response register value
+ */
+uint32_t sdio_response_get(sdio_type *sdio_x, sdio_rsp_index_type reg_index)
+{
+ uint32_t response_value = 0;
+
+ switch(reg_index)
+ {
+ case SDIO_RSP1_INDEX:
+ response_value = sdio_x->rsp1;
+ break;
+ case SDIO_RSP2_INDEX:
+ response_value = sdio_x->rsp2;
+ break;
+ case SDIO_RSP3_INDEX:
+ response_value = sdio_x->rsp3;
+ break;
+ case SDIO_RSP4_INDEX:
+ response_value = sdio_x->rsp4;
+ break;
+ default: break;
+ }
+
+ return response_value;
+}
+
+/**
+ * @brief config sdio data.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @param data_struct : pointer to a sdio_data_struct_type structure
+ * that contains the configuration information for the sdio data.
+ * @retval none
+ */
+void sdio_data_config(sdio_type *sdio_x, sdio_data_struct_type *data_struct)
+{
+ /* disable data path state machine */
+ sdio_x->dtctrl_bit.tfren = FALSE;
+
+ /* config data block, transfer mode and transfer direction */
+ sdio_x->dtctrl_bit.blksize = data_struct->block_size;
+ sdio_x->dtctrl_bit.tfrdir = data_struct->transfer_direction;
+ sdio_x->dtctrl_bit.tfrmode = data_struct->transfer_mode;
+
+ /* config data length */
+ sdio_x->dtlen_bit.dtlen = data_struct->data_length;
+
+ /* config data transfer timeout */
+ sdio_x->dttmr_bit.timeout = data_struct->timeout;
+}
+
+/**
+ * @brief enable or disable data path state machine(DPSM).
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void sdio_data_state_machine_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+ sdio_x->dtctrl_bit.tfren = new_state;
+}
+
+/**
+ * @brief get the number of remaining data bytes to be transferred.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @retval uint32_t: number of bytes
+ */
+uint32_t sdio_data_counter_get(sdio_type *sdio_x)
+{
+ return sdio_x->dtcnt;
+}
+
+/**
+ * @brief read a word data from sdio fifo.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @retval uint32_t: data received
+ */
+uint32_t sdio_data_read(sdio_type *sdio_x)
+{
+ return sdio_x->buf;
+}
+
+/**
+ * @brief get the number of words left to be written to or read from fifo..
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @retval uint32_t: number of words
+ */
+uint32_t sdio_buffer_counter_get(sdio_type *sdio_x)
+{
+ return sdio_x->bufcnt;
+}
+
+/**
+ * @brief write one word data to fifo.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @param data: data to be transferred.
+ * @retval none
+ */
+void sdio_data_write(sdio_type *sdio_x, uint32_t data)
+{
+ sdio_x->buf = data;
+}
+
+/**
+ * @brief set the read wait mode.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @param mode
+ * this parameter can be one of the following values:
+ * - SDIO_READ_WAIT_CONTROLLED_BY_D2
+ * - SDIO_READ_WAIT_CONTROLLED_BY_CK
+ * @retval none
+ */
+void sdio_read_wait_mode_set(sdio_type *sdio_x, sdio_read_wait_mode_type mode)
+{
+ sdio_x->dtctrl_bit.rdwtmode = mode;
+}
+
+/**
+ * @brief enable or disable to start sd i/o read wait operation.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void sdio_read_wait_start(sdio_type *sdio_x, confirm_state new_state)
+{
+ sdio_x->dtctrl_bit.rdwtstart = new_state;
+}
+
+/**
+ * @brief enable or disable to stop sd i/o read wait operation.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void sdio_read_wait_stop(sdio_type *sdio_x, confirm_state new_state)
+{
+ sdio_x->dtctrl_bit.rdwtstop = new_state;
+}
+
+/**
+ * @brief enable or disable the sd i/o function.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void sdio_io_function_enable(sdio_type *sdio_x, confirm_state new_state)
+{
+ sdio_x->dtctrl_bit.ioen = new_state;
+}
+
+/**
+ * @brief enable or disable sd i/o suspend command sending.
+ * @param sdio_x: to select the sdio peripheral.
+ * this parameter can be one of the following values:
+ * SDIO1.
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void sdio_io_suspend_command_set(sdio_type *sdio_x, confirm_state new_state)
+{
+ sdio_x->cmdctrl_bit.iosusp = new_state;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_spi.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_spi.c
new file mode 100644
index 00000000000..bc5e08a3eec
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_spi.c
@@ -0,0 +1,842 @@
+/**
+ **************************************************************************
+ * @file at32f45x_spi.c
+ * @brief contains all the functions for the spi firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup SPI
+ * @brief SPI driver modules
+ * @{
+ */
+
+#ifdef SPI_MODULE_ENABLED
+
+/** @defgroup SPI_private_functions
+ * @{
+ */
+
+/**
+ * @brief spi reset by crm reset register
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3, SPI4, I2SF5, I2S2EXT, I2S3EXT
+ * @retval none
+ */
+void spi_i2s_reset(spi_type *spi_x)
+{
+ if(spi_x == SPI1)
+ {
+ crm_periph_reset(CRM_SPI1_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_SPI1_PERIPH_RESET, FALSE);
+ }
+ else if(spi_x == SPI2)
+ {
+ crm_periph_reset(CRM_SPI2_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_SPI2_PERIPH_RESET, FALSE);
+ }
+ else if(spi_x == SPI3)
+ {
+ crm_periph_reset(CRM_SPI3_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_SPI3_PERIPH_RESET, FALSE);
+ }
+ else if(spi_x == SPI4)
+ {
+ crm_periph_reset(CRM_SPI4_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_SPI4_PERIPH_RESET, FALSE);
+ }
+ else if(spi_x == I2SF5)
+ {
+ crm_periph_reset(CRM_I2SF5_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_I2SF5_PERIPH_RESET, FALSE);
+ }
+ else if(spi_x == I2S2EXT)
+ {
+ crm_periph_reset(CRM_I2S2EXT_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_I2S2EXT_PERIPH_RESET, FALSE);
+ }
+ else if(spi_x == I2S3EXT)
+ {
+ crm_periph_reset(CRM_I2S3EXT_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_I2S3EXT_PERIPH_RESET, FALSE);
+ }
+}
+
+/**
+ * @brief spi init config with its default value.
+ * @param spi_init_struct : pointer to a spi_init_type structure which will
+ * be initialized.
+ * @retval none
+ */
+void spi_default_para_init(spi_init_type* spi_init_struct)
+{
+ spi_init_struct->transmission_mode = SPI_TRANSMIT_FULL_DUPLEX;
+ spi_init_struct->master_slave_mode = SPI_MODE_SLAVE;
+ spi_init_struct->mclk_freq_division = SPI_MCLK_DIV_2;
+ spi_init_struct->first_bit_transmission = SPI_FIRST_BIT_MSB;
+ spi_init_struct->frame_bit_num = SPI_FRAME_8BIT;
+ spi_init_struct->clock_polarity = SPI_CLOCK_POLARITY_LOW;
+ spi_init_struct->clock_phase = SPI_CLOCK_PHASE_1EDGE;
+ spi_init_struct->cs_mode_selection = SPI_CS_SOFTWARE_MODE;
+}
+
+/**
+ * @brief spi init config with its setting value.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3, SPI4
+ * @param spi_init_struct : pointer to a spi_init_type structure which will be initialized.
+ * @retval none
+ */
+void spi_init(spi_type* spi_x, spi_init_type* spi_init_struct)
+{
+ spi_x->i2sctrl_bit.i2smsel = FALSE;
+ if(spi_init_struct->transmission_mode == SPI_TRANSMIT_FULL_DUPLEX)
+ {
+ spi_x->ctrl1_bit.slben = FALSE;
+ spi_x->ctrl1_bit.slbtd = FALSE;
+ spi_x->ctrl1_bit.ora = FALSE;
+ }
+ else if(spi_init_struct->transmission_mode == SPI_TRANSMIT_SIMPLEX_RX)
+ {
+ spi_x->ctrl1_bit.slben = FALSE;
+ spi_x->ctrl1_bit.slbtd = FALSE;
+ spi_x->ctrl1_bit.ora = TRUE;
+ }
+ else if(spi_init_struct->transmission_mode == SPI_TRANSMIT_HALF_DUPLEX_RX)
+ {
+ spi_x->ctrl1_bit.slben = TRUE;
+ spi_x->ctrl1_bit.slbtd = FALSE;
+ spi_x->ctrl1_bit.ora = FALSE;
+ }
+ else if(spi_init_struct->transmission_mode == SPI_TRANSMIT_HALF_DUPLEX_TX)
+ {
+ spi_x->ctrl1_bit.slben = TRUE;
+ spi_x->ctrl1_bit.slbtd = TRUE;
+ spi_x->ctrl1_bit.ora = FALSE;
+ }
+
+ spi_x->ctrl1_bit.swcsen = spi_init_struct->cs_mode_selection;
+ if((spi_init_struct->master_slave_mode == SPI_MODE_MASTER) && (spi_init_struct->cs_mode_selection == SPI_CS_SOFTWARE_MODE))
+ {
+ spi_x->ctrl1_bit.swcsil = TRUE;
+ }
+ else
+ {
+ spi_x->ctrl1_bit.swcsil = FALSE;
+ }
+ spi_x->ctrl1_bit.msten = spi_init_struct->master_slave_mode;
+
+ if(spi_init_struct->mclk_freq_division <= SPI_MCLK_DIV_256)
+ {
+ spi_x->ctrl2_bit.mdiv3en = FALSE;
+ spi_x->ctrl2_bit.mdiv_h = FALSE;
+ spi_x->ctrl1_bit.mdiv_l = spi_init_struct->mclk_freq_division;
+ }
+ else if(spi_init_struct->mclk_freq_division == SPI_MCLK_DIV_3)
+ {
+ spi_x->ctrl2_bit.mdiv3en = TRUE;
+ spi_x->ctrl2_bit.mdiv_h = FALSE;
+ spi_x->ctrl1_bit.mdiv_l = 0;
+ }
+ else
+ {
+ spi_x->ctrl2_bit.mdiv3en = FALSE;
+ spi_x->ctrl2_bit.mdiv_h = TRUE;
+ spi_x->ctrl1_bit.mdiv_l = spi_init_struct->mclk_freq_division & 0x7;
+ }
+
+ spi_x->ctrl1_bit.ltf = spi_init_struct->first_bit_transmission;
+ spi_x->ctrl1_bit.fbn = spi_init_struct->frame_bit_num;
+ spi_x->ctrl1_bit.clkpol = spi_init_struct->clock_polarity;
+ spi_x->ctrl1_bit.clkpha = spi_init_struct->clock_phase;
+}
+
+/**
+ * @brief enable or disable the ti mode for the spi peripheral.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3, SPI4
+ * @param new_state: new state of ti mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void spi_ti_mode_enable(spi_type* spi_x, confirm_state new_state)
+{
+ spi_x->ctrl2_bit.tien = new_state;
+}
+
+/**
+ * @brief spi next transmit crc for the spi peripheral.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3, SPI4
+ * @retval none
+ */
+void spi_crc_next_transmit(spi_type* spi_x)
+{
+ spi_x->ctrl1_bit.ntc = TRUE;
+}
+
+/**
+ * @brief set the crc polynomial value for the spi peripheral.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3, SPI4
+ * @param crc_poly: crc polynomial value.
+ * @retval none
+ */
+void spi_crc_polynomial_set(spi_type* spi_x, uint16_t crc_poly)
+{
+ spi_x->cpoly_bit.cpoly = crc_poly;
+}
+
+/**
+ * @brief return the crc polynomial register value for the spi peripheral.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3, SPI4
+ * @retval the select crc polynomial register value
+ */
+uint16_t spi_crc_polynomial_get(spi_type* spi_x)
+{
+ return spi_x->cpoly_bit.cpoly;
+}
+
+/**
+ * @brief enable or disable the hardware crc calculation for the spi peripheral.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3, SPI4
+ * @param new_state: new state of crc calculation.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void spi_crc_enable(spi_type* spi_x, confirm_state new_state)
+{
+ spi_x->ctrl1_bit.ccen = new_state;
+}
+
+/**
+ * @brief return the transmit or the receive crc value for the spi peripheral.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3, SPI4
+ * @param crc_direction: select transmit or receive crc value to be read
+ * - SPI_CRC_RX
+ * - SPI_CRC_TX
+ * @retval the select crc register value
+ */
+uint16_t spi_crc_value_get(spi_type* spi_x, spi_crc_direction_type crc_direction)
+{
+ if(crc_direction == SPI_CRC_RX)
+ return spi_x->rcrc_bit.rcrc;
+ else
+ return spi_x->tcrc_bit.tcrc;
+}
+
+/**
+ * @brief enable or disable the hardware cs output for the spi peripheral.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3, SPI4
+ * @param new_state: new state of spi master cs output.
+ * this parameter can be: TRUE or FALSE.
+ * note:the bit only use in spi master mode
+ * @retval none
+ */
+void spi_hardware_cs_output_enable(spi_type* spi_x, confirm_state new_state)
+{
+ spi_x->ctrl2_bit.hwcsoe = new_state;
+}
+
+/**
+ * @brief set the software cs internal level for the spi peripheral.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3, SPI4
+ * @param level: set the state of spi cs level.
+ * this parameter can be one of the following values:
+ * - SPI_SWCS_INTERNAL_LEVEL_LOW
+ * - SPI_SWCS_INTERNAL_LEVEL_HIGHT
+ * note:the bit only use when swcsen bit is set.
+ * note:when use this bit,io operation on the cs pin are invalid.
+ * @retval none
+ */
+void spi_software_cs_internal_level_set(spi_type* spi_x, spi_software_cs_level_type level)
+{
+ spi_x->ctrl1_bit.swcsil = level;
+}
+
+/**
+ * @brief set the data frame bit num for the spi peripheral.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3, SPI4
+ * @param bit_num: set the data frame size
+ * - SPI_FRAME_8BIT
+ * - SPI_FRAME_16BIT
+ * @retval none
+ */
+void spi_frame_bit_num_set(spi_type* spi_x, spi_frame_bit_num_type bit_num)
+{
+ spi_x->ctrl1_bit.fbn = bit_num;
+}
+
+/**
+ * @brief set the data transmission direction in single line bidirectiona half duplex mode of the spi peripheral.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3, SPI4
+ * @param direction: data transfer direction
+ * this parameter can be one of the following values:
+ * - SPI_HALF_DUPLEX_DIRECTION_RX
+ * - SPI_HALF_DUPLEX_DIRECTION_TX
+ * @retval none
+ */
+void spi_half_duplex_direction_set(spi_type* spi_x, spi_half_duplex_direction_type direction)
+{
+ spi_x->ctrl1_bit.slbtd = direction;
+}
+
+/**
+ * @brief enable or disable spi.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3, SPI4
+ * @param new_state: new state of spi.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void spi_enable(spi_type* spi_x, confirm_state new_state)
+{
+ spi_x->ctrl1_bit.spien = new_state;
+}
+
+/**
+ * @brief i2s init config with its default value.
+ * @param i2s_init_struct : pointer to a i2s_init_type structure which will
+ * be initialized.
+ * @retval none
+ */
+void i2s_default_para_init(i2s_init_type* i2s_init_struct)
+{
+ i2s_init_struct->operation_mode = I2S_MODE_SLAVE_TX;
+ i2s_init_struct->audio_protocol = I2S_AUDIO_PROTOCOL_PHILLIPS;
+ i2s_init_struct->audio_sampling_freq = I2S_AUDIO_FREQUENCY_DEFAULT;
+ i2s_init_struct->data_channel_format = I2S_DATA_16BIT_CHANNEL_16BIT;
+ i2s_init_struct->clock_polarity = I2S_CLOCK_POLARITY_LOW;
+ i2s_init_struct->mclk_output_enable = FALSE;
+ i2s_init_struct->i2s_ckin_value = (uint32_t)8000000;
+ i2s_init_struct->pcm_sample_clock_selection = I2S_PCM_SAMPLE_CLOCK_FALLING;
+}
+
+/**
+ * @brief i2s init config with its setting value.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3, SPI4, I2SF5, I2S2EXT, I2S3EXT
+ * @param i2s_init_struct : pointer to a i2s_init_type structure which will be initialized.
+ * @note
+ * i2s_init_struct->i2s_ckin_value this parameter only used in i2sf.
+ * i2s_init_struct->pcm_sample_clock_selection this parameter only used in i2sf.
+ * @retval none
+ */
+void i2s_init(spi_type* spi_x, i2s_init_type* i2s_init_struct)
+{
+ crm_clocks_freq_type clocks_freq;
+ uint32_t i2s_sclk_index = 0;
+ uint32_t i2sdiv_index = 2, i2sodd_index = 0, frequency_index = 0;
+ uint32_t pll_ns = 0, pll_ms = 0, pll_fr = 0, pll_clock_source = 0, pllrcsfreq = 0;
+ static const uint8_t pll_fp_table[16] = {1, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30};
+
+ /* i2s audio frequency config */
+ if(i2s_init_struct->audio_sampling_freq == I2S_AUDIO_FREQUENCY_DEFAULT)
+ {
+ i2sodd_index = 0;
+ i2sdiv_index = 2;
+ }
+ else
+ {
+ if(spi_x == I2SF5)
+ {
+ if(CRM->cfg_bit.i2sf5clksel == CRM_I2SF5_CLOCK_SOURCE_SCLK)
+ {
+ crm_clocks_freq_get(&clocks_freq);
+ i2s_sclk_index = clocks_freq.sclk_freq;
+ }
+ else if(CRM->cfg_bit.i2sf5clksel == CRM_I2SF5_CLOCK_SOURCE_PLLP)
+ {
+ /* get pll clock source */
+ pll_clock_source = CRM->pllcfg_bit.pllrcs;
+
+ /* get multiplication factor */
+ pll_ns = CRM->pllcfg_bit.pllns;
+ pll_ms = CRM->pllcfg_bit.pllms;
+ pll_fr = pll_fp_table[CRM->pllcfg_bit.pllfp];
+ if (pll_clock_source == CRM_PLL_SOURCE_HICK)
+ {
+ /* hick selected as pll clock entry */
+ pllrcsfreq = HICK_VALUE;
+ }
+ else
+ {
+ /* hext selected as pll clock entry */
+ pllrcsfreq = HEXT_VALUE;
+ }
+ i2s_sclk_index = (pllrcsfreq * pll_ns) / (pll_ms * pll_fr);
+ }
+ else if(CRM->cfg_bit.i2sf5clksel == CRM_I2SF5_CLOCK_SOURCE_HICK)
+ {
+ i2s_sclk_index = (uint32_t)48000000;
+ }
+ else if(CRM->cfg_bit.i2sf5clksel == CRM_I2SF5_CLOCK_SOURCE_EXTERNAL)
+ {
+ i2s_sclk_index = i2s_init_struct->i2s_ckin_value;
+ }
+ if((i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_SHORT) || (i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_LONG))
+ {
+ if(i2s_init_struct->mclk_output_enable == TRUE)
+ {
+ frequency_index = (((i2s_sclk_index / 128) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+ }
+ else
+ {
+ if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
+ frequency_index = (((i2s_sclk_index / 16) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+ else
+ frequency_index = (((i2s_sclk_index / 32) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+ }
+ }
+ else
+ {
+ if(i2s_init_struct->mclk_output_enable == TRUE)
+ {
+ frequency_index = (((i2s_sclk_index / 256) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+ }
+ else
+ {
+ if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
+ frequency_index = (((i2s_sclk_index / 32) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+ else
+ frequency_index = (((i2s_sclk_index / 64) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+ }
+ }
+ }
+ else
+ {
+ crm_clocks_freq_get(&clocks_freq);
+ i2s_sclk_index = clocks_freq.sclk_freq;
+ if((i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_SHORT) || (i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_LONG))
+ {
+ if(i2s_init_struct->mclk_output_enable == TRUE)
+ {
+ frequency_index = (((i2s_sclk_index / 128) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+ }
+ else
+ {
+ if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
+ frequency_index = (((i2s_sclk_index / 16) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+ else
+ frequency_index = (((i2s_sclk_index / 32) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+ }
+ }
+ else
+ {
+ if(i2s_init_struct->mclk_output_enable == TRUE)
+ {
+ frequency_index = (((i2s_sclk_index / 256) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+ }
+ else
+ {
+ if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
+ frequency_index = (((i2s_sclk_index / 32) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+ else
+ frequency_index = (((i2s_sclk_index / 64) * 10) / i2s_init_struct->audio_sampling_freq) + 5;
+ }
+ }
+ }
+ }
+ frequency_index = frequency_index / 10;
+ i2sodd_index = frequency_index & (uint16_t)0x0001;
+ i2sdiv_index = (frequency_index - i2sodd_index) / 2;
+ if((i2sdiv_index < 2) || (i2sdiv_index > 0x03FF))
+ {
+ i2sodd_index = 0;
+ i2sdiv_index = 2;
+ }
+ spi_x->i2sclk_bit.i2sodd = i2sodd_index;
+ if(i2sdiv_index > 0x00FF)
+ {
+ spi_x->i2sclk_bit.i2sdiv_h = (i2sdiv_index >> 8) & 0x0003;
+ spi_x->i2sclk_bit.i2sdiv_l = i2sdiv_index & 0x00FF;
+ }
+ else
+ {
+ spi_x->i2sclk_bit.i2sdiv_h = 0;
+ spi_x->i2sclk_bit.i2sdiv_l = i2sdiv_index;
+ }
+
+ /* i2s audio_protocol set*/
+ if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_LONG)
+ {
+ spi_x->i2sctrl_bit.pcmfssel = 1;
+ spi_x->i2sctrl_bit.stdsel = 3;
+ }
+ else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PCM_SHORT)
+ {
+ spi_x->i2sctrl_bit.pcmfssel = 0;
+ spi_x->i2sctrl_bit.stdsel = 3;
+ }
+ else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_LSB)
+ {
+ spi_x->i2sctrl_bit.pcmfssel = 0;
+ spi_x->i2sctrl_bit.stdsel = 2;
+ }
+ else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_MSB)
+ {
+ spi_x->i2sctrl_bit.pcmfssel = 0;
+ spi_x->i2sctrl_bit.stdsel = 1;
+ }
+ else if(i2s_init_struct->audio_protocol == I2S_AUDIO_PROTOCOL_PHILLIPS)
+ {
+ spi_x->i2sctrl_bit.pcmfssel = 0;
+ spi_x->i2sctrl_bit.stdsel = 0;
+ }
+
+ /* i2s data_channel_format set*/
+ if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_16BIT)
+ {
+ spi_x->i2sctrl_bit.i2scbn = 0;
+ spi_x->i2sctrl_bit.i2sdbn = 0;
+ }
+ else if(i2s_init_struct->data_channel_format == I2S_DATA_16BIT_CHANNEL_32BIT)
+ {
+ spi_x->i2sctrl_bit.i2scbn = 1;
+ spi_x->i2sctrl_bit.i2sdbn = 0;
+ }
+ else if(i2s_init_struct->data_channel_format == I2S_DATA_24BIT_CHANNEL_32BIT)
+ {
+ spi_x->i2sctrl_bit.i2scbn = 1;
+ spi_x->i2sctrl_bit.i2sdbn = 1;
+ }
+ else if(i2s_init_struct->data_channel_format == I2S_DATA_32BIT_CHANNEL_32BIT)
+ {
+ spi_x->i2sctrl_bit.i2scbn = 1;
+ spi_x->i2sctrl_bit.i2sdbn = 2;
+ }
+
+ spi_x->i2sctrl_bit.i2sclkpol = i2s_init_struct->clock_polarity;
+ spi_x->i2sclk_bit.i2smclkoe = i2s_init_struct->mclk_output_enable;
+ spi_x->i2sctrl_bit.opersel = i2s_init_struct->operation_mode;
+ spi_x->i2sctrl_bit.i2smsel = TRUE;
+ if(spi_x == I2SF5)
+ {
+ spi_x->misc1_bit.i2sfpcmcksel = i2s_init_struct->pcm_sample_clock_selection;
+ }
+}
+
+/**
+ * @brief enable or disable i2s.
+ * @param spi_x: select the i2s peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3, SPI4, I2SF5, I2S2EXT, I2S3EXT
+ * @param new_state: new state of i2s.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void i2s_enable(spi_type* spi_x, confirm_state new_state)
+{
+ spi_x->i2sctrl_bit.i2sen = new_state;
+}
+
+/**
+ * @brief enable or disable the specified spi/i2s interrupts.
+ * @param spi_x: select the spi/i2s peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3, SPI4, I2SF5, I2S2EXT, I2S3EXT
+ * @param spi_i2s_int: specifies the spi/i2s interrupt sources to be enabled or disabled.
+ * this parameter can be one of the following values:
+ * - SPI_I2S_ERROR_INT
+ * - SPI_I2S_RDBF_INT
+ * - SPI_I2S_TDBE_INT
+ * @param new_state: new state of the specified spi/i2s interrupts.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void spi_i2s_interrupt_enable(spi_type* spi_x, uint32_t spi_i2s_int, confirm_state new_state)
+{
+ if(new_state != FALSE)
+ {
+ spi_x->ctrl2 |= spi_i2s_int;
+ }
+ else
+ {
+ spi_x->ctrl2 &= ~spi_i2s_int;
+ }
+}
+
+/**
+ * @brief enable or disable the spi/i2s dma transmitter mode.
+ * @param spi_x: select the spi/i2s peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3, SPI4, I2SF5, I2S2EXT, I2S3EXT
+ * @param new_state: new state of the dma request.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void spi_i2s_dma_transmitter_enable(spi_type* spi_x, confirm_state new_state)
+{
+ spi_x->ctrl2_bit.dmaten = new_state;
+}
+
+/**
+ * @brief enable or disable the spi/i2s dma receiver mode.
+ * @param spi_x: select the spi/i2s peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3, SPI4, I2SF5, I2S2EXT, I2S3EXT
+ * @param new_state: new state of the dma request.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state)
+{
+ spi_x->ctrl2_bit.dmaren = new_state;
+}
+
+/**
+ * @brief spi/i2s data transmit
+ * @param spi_x: select the spi/i2s peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3, SPI4, I2SF5, I2S2EXT, I2S3EXT
+ * @param tx_data: the data to be transmit.
+ * this parameter can be:
+ * - (0x0000~0xFFFF)
+ * @retval none
+ */
+void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data)
+{
+ spi_x->dt = tx_data;
+}
+
+/**
+ * @brief spi/i2s data receive
+ * @param spi_x: select the spi/i2s peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3, SPI4, I2SF5, I2S2EXT, I2S3EXT
+ * @retval the received data value
+ */
+uint16_t spi_i2s_data_receive(spi_type* spi_x)
+{
+ return (uint16_t)spi_x->dt;
+}
+
+/**
+ * @brief get flag of the specified spi/i2s peripheral.
+ * @param spi_x: select the spi/i2s peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3, SPI4, I2SF5, I2S2EXT, I2S3EXT
+ * @param spi_i2s_flag: select the spi/i2s flag
+ * this parameter can be one of the following values:
+ * - SPI_I2S_RDBF_FLAG
+ * - SPI_I2S_TDBE_FLAG
+ * - I2S_ACS_FLAG (this flag only use in i2s mode)
+ * - I2S_TUERR_FLAG (this flag only use in i2s mode)
+ * - SPI_CCERR_FLAG (this flag only use in spi mode)
+ * - SPI_MMERR_FLAG (this flag only use in spi mode)
+ * - SPI_I2S_ROERR_FLAG
+ * - SPI_I2S_BF_FLAG
+ * - SPI_I2S_CSPAS_FLAG
+ * @retval the new state of spi/i2s flag
+ */
+flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag)
+{
+ flag_status status = RESET;
+ if ((spi_x->sts & spi_i2s_flag) == RESET)
+ {
+ status = RESET;
+ }
+ else
+ {
+ status = SET;
+ }
+ return status;
+}
+
+/**
+ * @brief get interrupt flag of the specified spi/i2s peripheral.
+ * @param spi_x: select the spi/i2s peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3, SPI4, I2SF5, I2S2EXT, I2S3EXT
+ * @param spi_i2s_flag: select the spi/i2s flag
+ * this parameter can be one of the following values:
+ * - SPI_I2S_RDBF_FLAG
+ * - SPI_I2S_TDBE_FLAG
+ * - I2S_TUERR_FLAG (this flag only use in i2s mode)
+ * - SPI_CCERR_FLAG (this flag only use in spi mode)
+ * - SPI_MMERR_FLAG (this flag only use in spi mode)
+ * - SPI_I2S_ROERR_FLAG
+ * - SPI_I2S_CSPAS_FLAG
+ * @retval the new state of spi/i2s flag
+ */
+flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag)
+{
+ flag_status status = RESET;
+
+ switch(spi_i2s_flag)
+ {
+ case SPI_I2S_RDBF_FLAG:
+ if(spi_x->sts_bit.rdbf && spi_x->ctrl2_bit.rdbfie)
+ {
+ status = SET;
+ }
+ break;
+ case SPI_I2S_TDBE_FLAG:
+ if(spi_x->sts_bit.tdbe && spi_x->ctrl2_bit.tdbeie)
+ {
+ status = SET;
+ }
+ break;
+ case I2S_TUERR_FLAG:
+ if(spi_x->sts_bit.tuerr && spi_x->ctrl2_bit.errie)
+ {
+ status = SET;
+ }
+ break;
+ case SPI_CCERR_FLAG:
+ if(spi_x->sts_bit.ccerr && spi_x->ctrl2_bit.errie)
+ {
+ status = SET;
+ }
+ break;
+ case SPI_MMERR_FLAG:
+ if(spi_x->sts_bit.mmerr && spi_x->ctrl2_bit.errie)
+ {
+ status = SET;
+ }
+ break;
+ case SPI_I2S_ROERR_FLAG:
+ if(spi_x->sts_bit.roerr && spi_x->ctrl2_bit.errie)
+ {
+ status = SET;
+ }
+ break;
+ case SPI_I2S_CSPAS_FLAG:
+ if(spi_x->sts_bit.cspas && spi_x->ctrl2_bit.errie)
+ {
+ status = SET;
+ }
+ break;
+ default:
+ break;
+ }
+ return status;
+}
+
+/**
+ * @brief clear flag of the specified spi/i2s peripheral.
+ * @param spi_x: select the spi/i2s peripheral.
+ * this parameter can be one of the following values:
+ * SPI1, SPI2, SPI3, SPI4, I2SF5, I2S2EXT, I2S3EXT
+ * @param spi_i2s_flag: select the spi/i2s flag
+ * this parameter can be one of the following values:
+ * - SPI_CCERR_FLAG
+ * - SPI_I2S_RDBF_FLAG
+ * - I2S_TUERR_FLAG
+ * - SPI_MMERR_FLAG
+ * - SPI_I2S_ROERR_FLAG
+ * - SPI_I2S_CSPAS_FLAG
+ * @note
+ * SPI_I2S_TDBE_FLAG this flag is cleared when the tx buffer already contain data to be transmit.
+ * I2S_ACS_FLAG this flag cann't cleared by software,the flag indicate the channel side(not use in pcm standard mode).
+ * SPI_I2S_BF_FLAG this flag cann't cleared by software, it's set and cleared by hardware.
+ * @retval none
+ */
+void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag)
+{
+ if(spi_i2s_flag == SPI_CCERR_FLAG)
+ spi_x->sts = ~SPI_CCERR_FLAG;
+ else if(spi_i2s_flag == SPI_I2S_RDBF_FLAG)
+ UNUSED(spi_x->dt);
+ else if(spi_i2s_flag == I2S_TUERR_FLAG)
+ UNUSED(spi_x->sts);
+ else if(spi_i2s_flag == SPI_I2S_CSPAS_FLAG)
+ UNUSED(spi_x->sts);
+ else if(spi_i2s_flag == SPI_MMERR_FLAG)
+ {
+ UNUSED(spi_x->sts);
+ spi_x->ctrl1 = spi_x->ctrl1;
+ }
+ else if(spi_i2s_flag == SPI_I2S_ROERR_FLAG)
+ {
+ UNUSED(spi_x->dt);
+ UNUSED(spi_x->sts);
+ }
+}
+
+/**
+ * @brief enable or disable the i2s fullduplex mode for the spi peripheral.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * I2SF5
+ * @param new_state: new state of i2s fullduplex mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void i2sf_full_duplex_mode_enable(spi_type* spi_x, confirm_state new_state)
+{
+ spi_x->i2sctrl_bit.i2sfdupen = new_state;
+}
+
+/**
+ * @brief set the i2s pcm mode sample clock edge for the spi peripheral.
+ * @param spi_x: select the spi peripheral.
+ * this parameter can be one of the following values:
+ * I2SF5
+ * @param pcm_sample_clock: i2s pcm mode sample clock edge
+ * this parameter can be one of the following values:
+ * - I2S_PCM_SAMPLE_CLOCK_FALLING
+ * - I2S_PCM_SAMPLE_CLOCK_RISING
+ * @retval none
+ */
+void i2sf_pcm_sample_clock_set(spi_type* spi_x, i2s_pcm_sample_clock_type pcm_sample_clock)
+{
+ spi_x->misc1_bit.i2sfpcmcksel = pcm_sample_clock;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_tmr.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_tmr.c
new file mode 100644
index 00000000000..6b3fb5d4a86
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_tmr.c
@@ -0,0 +1,1904 @@
+/**
+ **************************************************************************
+ * @file at32f45x_tmr.c
+ * @brief contains all the functions for the tmr firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup TMR
+ * @brief TMR driver modules
+ * @{
+ */
+
+#ifdef TMR_MODULE_ENABLED
+
+/** @defgroup TMR_private_functions
+ * @{
+ */
+
+/**
+ * @brief tmr reset by crm reset register
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @retval none
+ */
+void tmr_reset(tmr_type *tmr_x)
+{
+ if(tmr_x == TMR1)
+ {
+ crm_periph_reset(CRM_TMR1_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR1_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR2)
+ {
+ crm_periph_reset(CRM_TMR2_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR2_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR3)
+ {
+ crm_periph_reset(CRM_TMR3_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR3_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR4)
+ {
+ crm_periph_reset(CRM_TMR4_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR4_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR5)
+ {
+ crm_periph_reset(CRM_TMR5_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR5_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR6)
+ {
+ crm_periph_reset(CRM_TMR6_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR6_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR7)
+ {
+ crm_periph_reset(CRM_TMR7_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR7_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR8)
+ {
+ crm_periph_reset(CRM_TMR8_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR8_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR9)
+ {
+ crm_periph_reset(CRM_TMR9_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR9_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR10)
+ {
+ crm_periph_reset(CRM_TMR10_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR10_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR11)
+ {
+ crm_periph_reset(CRM_TMR11_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR11_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR12)
+ {
+ crm_periph_reset(CRM_TMR12_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR12_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR13)
+ {
+ crm_periph_reset(CRM_TMR13_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR13_PERIPH_RESET, FALSE);
+ }
+ else if(tmr_x == TMR14)
+ {
+ crm_periph_reset(CRM_TMR14_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TMR14_PERIPH_RESET, FALSE);
+ }
+}
+
+/**
+ * @brief enable or disable tmr counter
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_counter_enable(tmr_type *tmr_x, confirm_state new_state)
+{
+ /* tmr counter enable */
+ tmr_x->ctrl1_bit.tmren = new_state;
+}
+
+/**
+ * @brief init tmr output default para
+ * @param tmr_output_struct
+ * - to the structure of tmr_output_config_type
+ * @retval none
+ */
+void tmr_output_default_para_init(tmr_output_config_type *tmr_output_struct)
+{
+ tmr_output_struct->oc_mode = TMR_OUTPUT_CONTROL_OFF;
+ tmr_output_struct->oc_idle_state = FALSE;
+ tmr_output_struct->occ_idle_state = FALSE;
+ tmr_output_struct->oc_polarity = TMR_OUTPUT_ACTIVE_HIGH;
+ tmr_output_struct->occ_polarity = TMR_OUTPUT_ACTIVE_HIGH;
+ tmr_output_struct->oc_output_state = FALSE;
+ tmr_output_struct->occ_output_state = FALSE;
+}
+
+/**
+ * @brief init tmr input default para
+ * @param tmr_input_struct
+ * - to the structure of tmr_input_config_type
+ * @retval none
+ */
+void tmr_input_default_para_init(tmr_input_config_type *tmr_input_struct)
+{
+ tmr_input_struct->input_channel_select = TMR_SELECT_CHANNEL_1;
+ tmr_input_struct->input_polarity_select = TMR_INPUT_RISING_EDGE;
+ tmr_input_struct->input_mapped_select = TMR_CC_CHANNEL_MAPPED_DIRECT;
+ tmr_input_struct->input_filter_value = 0x0;
+}
+
+/**
+ * @brief init tmr brkdt default para
+ * @param tmr_brkdt_struct
+ * - to the structure of tmr_brkdt_config_type
+ * @retval none
+ */
+void tmr_brkdt_default_para_init(tmr_brkdt_config_type *tmr_brkdt_struct)
+{
+ tmr_brkdt_struct->deadtime = 0x0;
+ tmr_brkdt_struct->brk_polarity = TMR_BRK_INPUT_ACTIVE_LOW;
+ tmr_brkdt_struct->wp_level = TMR_WP_OFF;
+ tmr_brkdt_struct->auto_output_enable = FALSE ;
+ tmr_brkdt_struct->fcsoen_state = FALSE ;
+ tmr_brkdt_struct->fcsodis_state = FALSE ;
+ tmr_brkdt_struct->brk_enable = FALSE ;
+}
+
+/**
+ * @brief init tmr base
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @param tmr_pr (for 16 bit tmr 0x0000~0xFFFF,
+ * for 32 bit tmr 0x0000_0000~0xFFFF_FFFF)
+ * @param tmr_div (timer div value:0x0000~0xFFFF)
+ * @retval none
+ */
+void tmr_base_init(tmr_type* tmr_x, uint32_t tmr_pr, uint32_t tmr_div)
+{
+ /* set the pr value */
+ tmr_x->pr = tmr_pr;
+
+ /* set the div value */
+ tmr_x->div = tmr_div;
+
+ /* trigger the overflow event to immediately reload pr value and div value */
+ tmr_x->swevt_bit.ovfswtr = TRUE;
+}
+
+/**
+ * @brief set tmr clock source division
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14
+ * @param tmr_clock_div
+ * this parameter can be one of the following values:
+ * - TMR_CLOCK_DIV1
+ * - TMR_CLOCK_DIV2
+ * - TMR_CLOCK_DIV4
+ * @retval none
+ */
+void tmr_clock_source_div_set(tmr_type *tmr_x, tmr_clock_division_type tmr_clock_div)
+{
+ /* set tmr clock source division */
+ tmr_x->ctrl1_bit.clkdiv = tmr_clock_div;
+}
+
+/**
+ * @brief set tmr counter count direction
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14
+ * @param tmr_cnt_dir
+ * this parameter can be one of the following values:
+ * - TMR_COUNT_UP
+ * - TMR_COUNT_DOWN
+ * - TMR_COUNT_TWO_WAY_1
+ * - TMR_COUNT_TWO_WAY_2
+ * - TMR_COUNT_TWO_WAY_3
+ * @retval none
+ */
+void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir)
+{
+ /* set the cnt direct */
+ tmr_x->ctrl1_bit.cnt_dir = tmr_cnt_dir;
+}
+
+/**
+ * @brief set the repetition counter register(rpr) value
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR8, TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @param tmr_rpr_value (for TMR1, TMR8 0x0000~0xFFFF,
+ * for other tmr 0x00~0xFF)
+ * @retval none
+ */
+void tmr_repetition_counter_set(tmr_type *tmr_x, uint16_t tmr_rpr_value)
+{
+ /* set the repetition counter value */
+ tmr_x->rpr_bit.rpr = tmr_rpr_value;
+}
+
+/**
+ * @brief set tmr counter value
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @param tmr_cnt_value (for 16 bit tmr 0x0000~0xFFFF,
+ * for 32 bit tmr 0x0000_0000~0xFFFF_FFFF)
+ * @retval none
+ */
+void tmr_counter_value_set(tmr_type *tmr_x, uint32_t tmr_cnt_value)
+{
+ /* set the tmr counter value */
+ tmr_x->cval = tmr_cnt_value;
+}
+
+/**
+ * @brief get tmr counter value
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @retval tmr counter value
+ */
+uint32_t tmr_counter_value_get(tmr_type *tmr_x)
+{
+ return tmr_x->cval;
+}
+
+/**
+ * @brief set tmr div value
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @param tmr_div_value (0x0000~0xFFFF)
+ * @retval none
+ */
+void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value)
+{
+ /* set the tmr div value */
+ tmr_x->div = tmr_div_value;
+}
+
+/**
+ * @brief get tmr div value
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @retval tmr div value
+ */
+uint32_t tmr_div_value_get(tmr_type *tmr_x)
+{
+ return tmr_x->div;
+}
+
+/**
+ * @brief config tmr output channel
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14
+ * @param tmr_channel
+ * this parameter can be one of the following values:
+ * - TMR_SELECT_CHANNEL_1
+ * - TMR_SELECT_CHANNEL_2
+ * - TMR_SELECT_CHANNEL_3
+ * - TMR_SELECT_CHANNEL_4
+ * - TMR_SELECT_CHANNEL_5
+ * @param tmr_output_struct
+ * - to the structure of tmr_output_config_type
+ * @retval none
+ */
+void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_output_config_type *tmr_output_struct)
+{
+ uint16_t channel_index = 0, channel_c_index = 0, channel = 0, chx_offset, chcx_offset;
+
+ chx_offset = (8 + tmr_channel);
+ chcx_offset = (9 + tmr_channel);
+
+ /* get channel idle state bit position in ctrl2 register */
+ channel_index = (uint16_t)(tmr_output_struct->oc_idle_state << chx_offset);
+
+ /* get channel complementary idle state bit position in ctrl2 register */
+ channel_c_index = (uint16_t)(tmr_output_struct->occ_idle_state << chcx_offset);
+
+ /* set output channel complementary idle state */
+ tmr_x->ctrl2 &= ~(1<ctrl2 |= channel_c_index;
+
+ /* set output channel idle state */
+ tmr_x->ctrl2 &= ~(1<ctrl2 |= channel_index;
+
+ /* set channel output mode */
+ channel = tmr_channel;
+
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ tmr_x->cm1_output_bit.c1octrl = tmr_output_struct->oc_mode;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ tmr_x->cm1_output_bit.c2octrl = tmr_output_struct->oc_mode;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ tmr_x->cm2_output_bit.c3octrl = tmr_output_struct->oc_mode;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ tmr_x->cm2_output_bit.c4octrl = tmr_output_struct->oc_mode;
+ break;
+
+ case TMR_SELECT_CHANNEL_5:
+ tmr_x->cm3_output_bit.c5octrl = tmr_output_struct->oc_mode;
+ break;
+
+ default:
+ break;
+ }
+
+ chx_offset = ((tmr_channel * 2) + 1);
+ chcx_offset = ((tmr_channel * 2) + 3);
+
+ /* get channel polarity bit position in cctrl register */
+ channel_index = (uint16_t)(tmr_output_struct->oc_polarity << chx_offset);
+
+ /* get channel complementary polarity bit position in cctrl register */
+ channel_c_index = (uint16_t)(tmr_output_struct->occ_polarity << chcx_offset);
+
+ /* set output channel complementary polarity */
+ tmr_x->cctrl &= ~(1<cctrl |= channel_c_index;
+
+ /* set output channel polarity */
+ tmr_x->cctrl &= ~(1<cctrl |= channel_index;
+
+ chx_offset = (tmr_channel * 2);
+ chcx_offset = ((tmr_channel * 2) + 2);
+
+ /* get channel enable bit position in cctrl register */
+ channel_index = (uint16_t)(tmr_output_struct->oc_output_state << (tmr_channel * 2));
+
+ /* get channel complementary enable bit position in cctrl register */
+ channel_c_index = (uint16_t)(tmr_output_struct->occ_output_state << ((tmr_channel * 2) + 2));
+
+ /* set output channel complementary enable bit */
+ tmr_x->cctrl &= ~(1<cctrl |= channel_c_index;
+
+ /* set output channel enable bit */
+ tmr_x->cctrl &= ~(1<cctrl |= channel_index;
+}
+
+/**
+ * @brief select tmr output channel mode
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14
+ * @param tmr_channel
+ * this parameter can be one of the following values:
+ * - TMR_SELECT_CHANNEL_1
+ * - TMR_SELECT_CHANNEL_2
+ * - TMR_SELECT_CHANNEL_3
+ * - TMR_SELECT_CHANNEL_4
+ * - TMR_SELECT_CHANNEL_5
+ * @param oc_mode
+ * this parameter can be one of the following values:
+ * - TMR_OUTPUT_CONTROL_OFF
+ * - TMR_OUTPUT_CONTROL_HIGH
+ * - TMR_OUTPUT_CONTROL_LOW
+ * - TMR_OUTPUT_CONTROL_SWITCH
+ * - TMR_OUTPUT_CONTROL_FORCE_HIGH
+ * - TMR_OUTPUT_CONTROL_FORCE_LOW
+ * - TMR_OUTPUT_CONTROL_PWM_MODE_A
+ * - TMR_OUTPUT_CONTROL_PWM_MODE_B
+ * @retval none
+ */
+void tmr_output_channel_mode_select(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_output_control_mode_type oc_mode)
+{
+ uint16_t channel;
+
+ channel = tmr_channel;
+
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ tmr_x->cm1_output_bit.c1octrl = oc_mode;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ tmr_x->cm1_output_bit.c2octrl = oc_mode;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ tmr_x->cm2_output_bit.c3octrl = oc_mode;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ tmr_x->cm2_output_bit.c4octrl = oc_mode;
+ break;
+
+ case TMR_SELECT_CHANNEL_5:
+ tmr_x->cm3_output_bit.c5octrl = oc_mode;
+ break;
+
+ default:
+ break;
+ }
+}
+/**
+ * @brief set tmr period value
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @param tmr_pr_value: timer period register value of counter
+ * (for 16 bit tmr 0x0000~0xFFFF,
+ * for 32 bit tmr 0x0000_0000~0xFFFF_FFFF)
+ * @retval none
+ */
+void tmr_period_value_set(tmr_type *tmr_x, uint32_t tmr_pr_value)
+{
+ /* set tmr period value */
+ tmr_x->pr = tmr_pr_value;
+}
+
+/**
+ * @brief get tmr period value
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @retval timer period register value of counter
+ * (for 16 bit tmr 0x0000~0xFFFF, for 32 bit tmr
+ * 0x0000_0000~0xFFFF_FFFF)
+ */
+uint32_t tmr_period_value_get(tmr_type *tmr_x)
+{
+ return tmr_x->pr;
+}
+
+/**
+ * @brief set tmr channel value
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14
+ * @param tmr_channel
+ * this parameter can be one of the following values:
+ * - TMR_SELECT_CHANNEL_1
+ * - TMR_SELECT_CHANNEL_2
+ * - TMR_SELECT_CHANNEL_3
+ * - TMR_SELECT_CHANNEL_4
+ * - TMR_SELECT_CHANNEL_5
+ * @param tmr_channel_value (for 16 bit tmr 0x0000~0xFFFF,
+ * for 32 bit tmr 0x0000_0000~0xFFFF_FFFF)
+ * @retval none
+ */
+void tmr_channel_value_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ uint32_t tmr_channel_value)
+{
+ uint16_t channel;
+
+ channel = tmr_channel;
+
+ /* set tmr channel value */
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ tmr_x->c1dt = tmr_channel_value;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ tmr_x->c2dt = tmr_channel_value;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ tmr_x->c3dt = tmr_channel_value;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ tmr_x->c4dt = tmr_channel_value;
+ break;
+
+ case TMR_SELECT_CHANNEL_5:
+ tmr_x->c5dt = tmr_channel_value;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief get tmr channel value
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14
+ * @param tmr_channel
+ * this parameter can be one of the following values:
+ * - TMR_SELECT_CHANNEL_1
+ * - TMR_SELECT_CHANNEL_2
+ * - TMR_SELECT_CHANNEL_3
+ * - TMR_SELECT_CHANNEL_4
+ * - TMR_SELECT_CHANNEL_5
+ * @retval tmr channel value
+ */
+uint32_t tmr_channel_value_get(tmr_type *tmr_x, tmr_channel_select_type tmr_channel)
+{
+ uint32_t cc_value_get = 0;
+ uint16_t channel;
+
+ channel = tmr_channel;
+
+ /* get tmr channel value */
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ cc_value_get = tmr_x->c1dt;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ cc_value_get = tmr_x->c2dt;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ cc_value_get = tmr_x->c3dt;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ cc_value_get = tmr_x->c4dt;
+ break;
+
+ case TMR_SELECT_CHANNEL_5:
+ cc_value_get = tmr_x->c5dt;
+ break;
+
+ default:
+ break;
+ }
+
+ return cc_value_get;
+}
+/**
+ * @brief set tmr period buffer
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_period_buffer_enable(tmr_type *tmr_x, confirm_state new_state)
+{
+ /* tmr period buffer set */
+ tmr_x->ctrl1_bit.prben = new_state;
+}
+
+/**
+ * @brief set tmr output channel buffer
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14
+ * @param tmr_channel
+ * this parameter can be one of the following values:
+ * - TMR_SELECT_CHANNEL_1
+ * - TMR_SELECT_CHANNEL_2
+ * - TMR_SELECT_CHANNEL_3
+ * - TMR_SELECT_CHANNEL_4
+ * - TMR_SELECT_CHANNEL_5
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_output_channel_buffer_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ confirm_state new_state)
+{
+ uint16_t channel;
+
+ channel = tmr_channel;
+
+ /* get tmr channel value */
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ tmr_x->cm1_output_bit.c1oben = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ tmr_x->cm1_output_bit.c2oben = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ tmr_x->cm2_output_bit.c3oben = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ tmr_x->cm2_output_bit.c4oben = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_5:
+ tmr_x->cm3_output_bit.c5oben = new_state;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief set tmr output channel immediately
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14
+ * @param tmr_channel
+ * this parameter can be one of the following values:
+ * - TMR_SELECT_CHANNEL_1
+ * - TMR_SELECT_CHANNEL_2
+ * - TMR_SELECT_CHANNEL_3
+ * - TMR_SELECT_CHANNEL_4
+ * - TMR_SELECT_CHANNEL_5
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_output_channel_immediately_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ confirm_state new_state)
+{
+ uint16_t channel;
+
+ channel = tmr_channel;
+
+ /* get tmr channel value */
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ tmr_x->cm1_output_bit.c1oien = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ tmr_x->cm1_output_bit.c2oien = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ tmr_x->cm2_output_bit.c3oien = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ tmr_x->cm2_output_bit.c4oien = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_5:
+ tmr_x->cm3_output_bit.c5oien = new_state;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief set tmr output channel switch
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8
+ * @param tmr_channel
+ * this parameter can be one of the following values:
+ * - TMR_SELECT_CHANNEL_1
+ * - TMR_SELECT_CHANNEL_2
+ * - TMR_SELECT_CHANNEL_3
+ * - TMR_SELECT_CHANNEL_4
+ * - TMR_SELECT_CHANNEL_5
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_output_channel_switch_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ confirm_state new_state)
+{
+ uint16_t channel;
+
+ channel = tmr_channel;
+
+ /* get tmr channel value */
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ tmr_x->cm1_output_bit.c1osen = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ tmr_x->cm1_output_bit.c2osen = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ tmr_x->cm2_output_bit.c3osen = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ tmr_x->cm2_output_bit.c4osen = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_5:
+ tmr_x->cm3_output_bit.c5osen = new_state;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief enable or disable tmr one cycle mode
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_one_cycle_mode_enable(tmr_type *tmr_x, confirm_state new_state)
+{
+ /* tmr one cycle mode enable */
+ tmr_x->ctrl1_bit.ocmen = new_state;
+}
+
+/**
+ * @brief enable or disable tmr 32 bit function(plus mode)
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR2, TMR5
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_32_bit_function_enable (tmr_type *tmr_x, confirm_state new_state)
+{
+ /* tmr 32 bit function(plus mode) enable,only for TMR2/TMR5 */
+ if((tmr_x == TMR2) || (tmr_x == TMR5))
+ {
+ tmr_x->ctrl1_bit.pmen = new_state;
+ }
+}
+
+/**
+ * @brief select tmr the overflow event sources
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_overflow_request_source_set(tmr_type *tmr_x, confirm_state new_state)
+{
+ tmr_x->ctrl1_bit.ovfs = new_state;
+}
+
+/**
+ * @brief enable or disable tmr overflow event generation
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_overflow_event_disable(tmr_type *tmr_x, confirm_state new_state)
+{
+ tmr_x->ctrl1_bit.ovfen = new_state;
+}
+
+/**
+ * @brief init tmr input channel
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14
+ * @param input_struct
+ * - to the structure of tmr_input_config_type
+ * @param divider_factor
+ * this parameter can be one of the following values:
+ * - TMR_CHANNEL_INPUT_DIV_1
+ * - TMR_CHANNEL_INPUT_DIV_2
+ * - TMR_CHANNEL_INPUT_DIV_4
+ * - TMR_CHANNEL_INPUT_DIV_8
+ * @retval none
+ */
+void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
+ tmr_channel_input_divider_type divider_factor)
+{
+ uint16_t channel = 0;
+
+ /* get channel selected */
+ channel = input_struct->input_channel_select;
+
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ tmr_x->cctrl_bit.c1en = FALSE;
+ tmr_x->cctrl_bit.c1p = (uint32_t)input_struct->input_polarity_select;
+ tmr_x->cctrl_bit.c1cp = (input_struct->input_polarity_select & 0x2) >> 1;
+ tmr_x->cm1_input_bit.c1c = input_struct->input_mapped_select;
+ tmr_x->cm1_input_bit.c1df = input_struct->input_filter_value;
+ tmr_x->cm1_input_bit.c1idiv = divider_factor;
+ tmr_x->cctrl_bit.c1en = TRUE;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ tmr_x->cctrl_bit.c2en = FALSE;
+ tmr_x->cctrl_bit.c2p = (uint32_t)input_struct->input_polarity_select;
+ tmr_x->cctrl_bit.c2cp = (input_struct->input_polarity_select & 0x2) >> 1;
+ tmr_x->cm1_input_bit.c2c = input_struct->input_mapped_select;
+ tmr_x->cm1_input_bit.c2df = input_struct->input_filter_value;
+ tmr_x->cm1_input_bit.c2idiv = divider_factor;
+ tmr_x->cctrl_bit.c2en = TRUE;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ tmr_x->cctrl_bit.c3en = FALSE;
+ tmr_x->cctrl_bit.c3p = (uint32_t)input_struct->input_polarity_select;
+ tmr_x->cctrl_bit.c3cp = (input_struct->input_polarity_select & 0x2) >> 1;
+ tmr_x->cm2_input_bit.c3c = input_struct->input_mapped_select;
+ tmr_x->cm2_input_bit.c3df = input_struct->input_filter_value;
+ tmr_x->cm2_input_bit.c3idiv = divider_factor;
+ tmr_x->cctrl_bit.c3en = TRUE;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ tmr_x->cctrl_bit.c4en = FALSE;
+ tmr_x->cctrl_bit.c4p = (uint32_t)input_struct->input_polarity_select;
+ tmr_x->cctrl_bit.c4cp = (input_struct->input_polarity_select & 0x2) >> 1;
+ tmr_x->cm2_input_bit.c4c = input_struct->input_mapped_select;
+ tmr_x->cm2_input_bit.c4df = input_struct->input_filter_value;
+ tmr_x->cm2_input_bit.c4idiv = divider_factor;
+ tmr_x->cctrl_bit.c4en = TRUE;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief tmr channel enable
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14
+ * @param tmr_channel
+ * this parameter can be one of the following values:
+ * - TMR_SELECT_CHANNEL_1
+ * - TMR_SELECT_CHANNEL_1C
+ * - TMR_SELECT_CHANNEL_2
+ * - TMR_SELECT_CHANNEL_2C
+ * - TMR_SELECT_CHANNEL_3
+ * - TMR_SELECT_CHANNEL_3C
+ * - TMR_SELECT_CHANNEL_4
+ * - TMR_SELECT_CHANNEL_4C
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_channel_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, confirm_state new_state)
+{
+ uint16_t channel;
+
+ channel = tmr_channel;
+
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ tmr_x->cctrl_bit.c1en = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_1C:
+ tmr_x->cctrl_bit.c1cen = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ tmr_x->cctrl_bit.c2en = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_2C:
+ tmr_x->cctrl_bit.c2cen = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ tmr_x->cctrl_bit.c3en = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_3C:
+ tmr_x->cctrl_bit.c3cen = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ tmr_x->cctrl_bit.c4en = new_state;
+ break;
+
+ case TMR_SELECT_CHANNEL_4C:
+ tmr_x->cctrl_bit.c4cen = new_state;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief set tmr input channel filter
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14
+ * @param tmr_channel
+ * this parameter can be one of the following values:
+ * - TMR_SELECT_CHANNEL_1
+ * - TMR_SELECT_CHANNEL_2
+ * - TMR_SELECT_CHANNEL_3
+ * - TMR_SELECT_CHANNEL_4
+ * @param filter_value (0x0~0xf)
+ * @retval none
+ */
+void tmr_input_channel_filter_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ uint16_t filter_value)
+{
+ uint16_t channel;
+
+ channel = tmr_channel;
+
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ tmr_x->cm1_input_bit.c1df = filter_value;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ tmr_x->cm1_input_bit.c2df = filter_value;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ tmr_x->cm2_input_bit.c3df = filter_value;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ tmr_x->cm2_input_bit.c4df = filter_value;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief config tmr pwm input
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR12
+ * @param input_struct
+ * - to the structure of tmr_input_config_type
+ * @param divider_factor
+ * this parameter can be one of the following values:
+ * - TMR_CHANNEL_INPUT_DIV_1
+ * - TMR_CHANNEL_INPUT_DIV_2
+ * - TMR_CHANNEL_INPUT_DIV_4
+ * - TMR_CHANNEL_INPUT_DIV_8
+ * @retval none
+ */
+void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
+ tmr_channel_input_divider_type divider_factor)
+{
+ uint16_t channel = 0;
+
+ /* get channel selected */
+ channel = input_struct->input_channel_select;
+
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ if(input_struct->input_polarity_select == TMR_INPUT_RISING_EDGE)
+ {
+ /* set channel polarity */
+ tmr_x->cctrl_bit.c1p = TMR_INPUT_RISING_EDGE;
+ tmr_x->cctrl_bit.c2p = TMR_INPUT_FALLING_EDGE;
+ }
+ else if(input_struct->input_polarity_select == TMR_INPUT_FALLING_EDGE)
+ {
+ /* set channel polarity */
+ tmr_x->cctrl_bit.c1p = TMR_INPUT_FALLING_EDGE;
+ tmr_x->cctrl_bit.c2p = TMR_INPUT_RISING_EDGE;
+ }
+
+ if(input_struct->input_mapped_select == TMR_CC_CHANNEL_MAPPED_DIRECT)
+ {
+ /* ic1 is mapped on ti1 */
+ tmr_x->cm1_input_bit.c1c = TMR_CC_CHANNEL_MAPPED_DIRECT;
+
+ /* ic1 is mapped on ti2 */
+ tmr_x->cm1_input_bit.c2c = TMR_CC_CHANNEL_MAPPED_INDIRECT;
+ }
+ else if(input_struct->input_mapped_select == TMR_CC_CHANNEL_MAPPED_INDIRECT)
+ {
+ /* ic1 is mapped on ti1 */
+ tmr_x->cm1_input_bit.c1c = TMR_CC_CHANNEL_MAPPED_INDIRECT;
+
+ /* ic1 is mapped on ti2 */
+ tmr_x->cm1_input_bit.c2c = TMR_CC_CHANNEL_MAPPED_DIRECT;
+ }
+
+ /* set input ch1 and ch2 filter value*/
+ tmr_x->cm1_input_bit.c1df = input_struct->input_filter_value;
+ tmr_x->cm1_input_bit.c2df = input_struct->input_filter_value;
+
+ /*set input ch1 and ch2 divider value*/
+ tmr_x->cm1_input_bit.c1idiv = divider_factor;
+ tmr_x->cm1_input_bit.c2idiv = divider_factor;
+
+ tmr_x->cctrl_bit.c1en = TRUE;
+ tmr_x->cctrl_bit.c2en = TRUE;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ if(input_struct->input_polarity_select == TMR_INPUT_RISING_EDGE)
+ {
+ /* set channel polarity */
+ tmr_x->cctrl_bit.c2p = TMR_INPUT_RISING_EDGE;
+ tmr_x->cctrl_bit.c1p = TMR_INPUT_FALLING_EDGE;
+ }
+ else if(input_struct->input_polarity_select == TMR_INPUT_FALLING_EDGE)
+ {
+ /* set channel polarity */
+ tmr_x->cctrl_bit.c2p = TMR_INPUT_FALLING_EDGE;
+ tmr_x->cctrl_bit.c1p = TMR_INPUT_RISING_EDGE;
+ }
+
+ if(input_struct->input_mapped_select == TMR_CC_CHANNEL_MAPPED_DIRECT)
+ {
+ /* set mapped direct */
+ tmr_x->cm1_input_bit.c2c = TMR_CC_CHANNEL_MAPPED_DIRECT;
+ tmr_x->cm1_input_bit.c1c = TMR_CC_CHANNEL_MAPPED_INDIRECT;
+ }
+ else if(input_struct->input_mapped_select == TMR_CC_CHANNEL_MAPPED_INDIRECT)
+ {
+ /* set mapped direct */
+ tmr_x->cm1_input_bit.c2c = TMR_CC_CHANNEL_MAPPED_INDIRECT;
+ tmr_x->cm1_input_bit.c1c = TMR_CC_CHANNEL_MAPPED_DIRECT;
+ }
+
+ /* set input ch1 and ch2 filter value*/
+ tmr_x->cm1_input_bit.c1df = input_struct->input_filter_value;
+ tmr_x->cm1_input_bit.c2df = input_struct->input_filter_value;
+
+ /*set input ch1 and ch2 divider value*/
+ tmr_x->cm1_input_bit.c1idiv = divider_factor;
+ tmr_x->cm1_input_bit.c2idiv = divider_factor;
+
+ tmr_x->cctrl_bit.c1en = TRUE;
+ tmr_x->cctrl_bit.c2en = TRUE;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief select tmr channel1 input
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8
+ * @param ch1_connect
+ * this parameter can be one of the following values:
+ * - TMR_CHANEL1_CONNECTED_C1IRAW
+ * - TMR_CHANEL1_2_3_CONNECTED_C1IRAW_XOR
+ * @retval none
+ */
+void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect)
+{
+ tmr_x->ctrl2_bit.c1insel = ch1_connect;
+}
+
+/**
+ * @brief set tmr input channel divider
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14
+ * @param tmr_channel
+ * this parameter can be one of the following values:
+ * - TMR_SELECT_CHANNEL_1
+ * - TMR_SELECT_CHANNEL_2
+ * - TMR_SELECT_CHANNEL_3
+ * - TMR_SELECT_CHANNEL_4
+ * @param divider_factor
+ * this parameter can be one of the following values:
+ * - TMR_CHANNEL_INPUT_DIV_1
+ * - TMR_CHANNEL_INPUT_DIV_2
+ * - TMR_CHANNEL_INPUT_DIV_4
+ * - TMR_CHANNEL_INPUT_DIV_8
+ * @retval none
+ */
+void tmr_input_channel_divider_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_channel_input_divider_type divider_factor)
+{
+ uint16_t channel;
+
+ channel = tmr_channel;
+
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ tmr_x->cm1_input_bit.c1idiv = divider_factor;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ tmr_x->cm1_input_bit.c2idiv = divider_factor;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ tmr_x->cm2_input_bit.c3idiv = divider_factor;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ tmr_x->cm2_input_bit.c4idiv = divider_factor;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief select tmr primary mode
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8
+ * @param primary_mode
+ * this parameter can be one of the following values:
+ * - TMR_PRIMARY_SEL_RESET
+ * - TMR_PRIMARY_SEL_ENABLE
+ * - TMR_PRIMARY_SEL_OVERFLOW
+ * - TMR_PRIMARY_SEL_COMPARE
+ * - TMR_PRIMARY_SEL_C1ORAW
+ * - TMR_PRIMARY_SEL_C2ORAW
+ * - TMR_PRIMARY_SEL_C3ORAW
+ * - TMR_PRIMARY_SEL_C4ORAW
+ * @retval none
+ */
+void tmr_primary_mode_select(tmr_type *tmr_x, tmr_primary_select_type primary_mode)
+{
+ tmr_x->ctrl2_bit.ptos = primary_mode;
+}
+
+/**
+ * @brief select tmr subordinate mode
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR12
+ * @param sub_mode
+ * this parameter can be one of the following values:
+ * - TMR_SUB_MODE_DIABLE
+ * - TMR_SUB_ENCODER_MODE_A
+ * - TMR_SUB_ENCODER_MODE_B
+ * - TMR_SUB_ENCODER_MODE_C
+ * - TMR_SUB_RESET_MODE
+ * - TMR_SUB_HANG_MODE
+ * - TMR_SUB_TRIGGER_MODE
+ * - TMR_SUB_EXTERNAL_CLOCK_MODE_A
+
+ * @retval none
+ */
+void tmr_sub_mode_select(tmr_type *tmr_x, tmr_sub_mode_select_type sub_mode)
+{
+ tmr_x->stctrl_bit.smsel = sub_mode;
+}
+
+/**
+ * @brief select tmr channel dma
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14
+ * @param cc_dma_select
+ * this parameter can be one of the following values:
+ * - TMR_DMA_REQUEST_BY_CHANNEL
+ * - TMR_DMA_REQUEST_BY_OVERFLOW
+ * @retval none
+ */
+void tmr_channel_dma_select(tmr_type *tmr_x, tmr_dma_request_source_type cc_dma_select)
+{
+ tmr_x->ctrl2_bit.drs = cc_dma_select;
+}
+
+/**
+ * @brief select tmr hall
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR8, TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_hall_select(tmr_type *tmr_x, confirm_state new_state)
+{
+ tmr_x->ctrl2_bit.ccfs = new_state;
+}
+
+/**
+ * @brief select tmr channel buffer
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR8, TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_channel_buffer_enable(tmr_type *tmr_x, confirm_state new_state)
+{
+ tmr_x->ctrl2_bit.cbctrl = new_state;
+}
+
+/**
+ * @brief select tmr trgout2
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR8
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_trgout2_enable(tmr_type *tmr_x, confirm_state new_state)
+{
+ tmr_x->ctrl2_bit.trgout2en = new_state;
+}
+
+/**
+ * @brief select tmr sub-trigger
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR12
+ * @param trigger_select
+ * this parameter can be one of the following values:
+ * - TMR_SUB_INPUT_SEL_IS0
+ * - TMR_SUB_INPUT_SEL_IS1
+ * - TMR_SUB_INPUT_SEL_IS2
+ * - TMR_SUB_INPUT_SEL_IS3
+ * - TMR_SUB_INPUT_SEL_C1INC
+ * - TMR_SUB_INPUT_SEL_C1DF1
+ * - TMR_SUB_INPUT_SEL_C2DF2
+ * - TMR_SUB_INPUT_SEL_EXTIN
+ * @retval none
+ */
+void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_select)
+{
+ tmr_x->stctrl_bit.stis = trigger_select;
+}
+
+/**
+ * @brief set tmr subordinate synchronization mode
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR12
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state)
+{
+ tmr_x->stctrl_bit.sts = new_state;
+}
+
+/**
+ * @brief enable or disable tmr dma request
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @param dma_request
+ * this parameter can be one of the following values:
+ * - TMR_OVERFLOW_DMA_REQUEST
+ * - TMR_C1_DMA_REQUEST
+ * - TMR_C2_DMA_REQUEST
+ * - TMR_C3_DMA_REQUEST
+ * - TMR_C4_DMA_REQUEST
+ * - TMR_HALL_DMA_REQUEST
+ * - TMR_TRIGGER_DMA_REQUEST
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state)
+{
+ if(new_state == TRUE)
+ {
+ tmr_x->iden |= dma_request;
+ }
+ else if(new_state == FALSE)
+ {
+ tmr_x->iden &= ~dma_request;
+ }
+}
+
+/**
+ * @brief enable or disable tmr interrupt
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @param tmr_interrupt
+ * this parameter can be one of the following values:
+ * - TMR_OVF_INT
+ * - TMR_C1_INT
+ * - TMR_C2_INT
+ * - TMR_C3_INT
+ * - TMR_C4_INT
+ * - TMR_HALL_INT
+ * - TMR_TRIGGER_INT
+ * - TMR_BRK_INT
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state)
+{
+ if(new_state == TRUE)
+ {
+ tmr_x->iden |= tmr_interrupt;
+ }
+ else if(new_state == FALSE)
+ {
+ tmr_x->iden &= ~tmr_interrupt;
+ }
+}
+
+/**
+ * @brief get tmr interrupt flag
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @param tmr_flag
+ * this parameter can be one of the following values:
+ * - TMR_OVF_FLAG
+ * - TMR_C1_FLAG
+ * - TMR_C2_FLAG
+ * - TMR_C3_FLAG
+ * - TMR_C4_FLAG
+ * - TMR_HALL_FLAG
+ * - TMR_TRIGGER_FLAG
+ * - TMR_BRK_FLAG
+ * @retval state of tmr interrupt flag
+ */
+flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag)
+{
+ flag_status status = RESET;
+
+ if((tmr_x->ists & tmr_flag) && (tmr_x->iden & tmr_flag))
+ {
+ status = SET;
+ }
+ else
+ {
+ status = RESET;
+ }
+
+ return status;
+}
+
+/**
+ * @brief get tmr flag
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @param tmr_flag
+ * this parameter can be one of the following values:
+ * - TMR_OVF_FLAG
+ * - TMR_C1_FLAG
+ * - TMR_C2_FLAG
+ * - TMR_C3_FLAG
+ * - TMR_C4_FLAG
+ * - TMR_C5_FLAG
+ * - TMR_HALL_FLAG
+ * - TMR_TRIGGER_FLAG
+ * - TMR_BRK_FLAG
+ * - TMR_C1_RECAPTURE_FLAG
+ * - TMR_C2_RECAPTURE_FLAG
+ * - TMR_C3_RECAPTURE_FLAG
+ * - TMR_C4_RECAPTURE_FLAG
+ * @retval state of tmr flag
+ */
+flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag)
+{
+ flag_status status = RESET;
+
+ if((tmr_x->ists & tmr_flag) != RESET)
+ {
+ status = SET;
+ }
+ else
+ {
+ status = RESET;
+ }
+
+ return status;
+}
+
+/**
+ * @brief clear tmr flag
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @param tmr_flag
+ * this parameter can be any combination of the following values:
+ * - TMR_OVF_FLAG
+ * - TMR_C1_FLAG
+ * - TMR_C2_FLAG
+ * - TMR_C3_FLAG
+ * - TMR_C4_FLAG
+ * - TMR_C5_FLAG
+ * - TMR_HALL_FLAG
+ * - TMR_TRIGGER_FLAG
+ * - TMR_BRK_FLAG
+ * - TMR_C1_RECAPTURE_FLAG
+ * - TMR_C2_RECAPTURE_FLAG
+ * - TMR_C3_RECAPTURE_FLAG
+ * - TMR_C4_RECAPTURE_FLAG
+ * @retval none
+ */
+void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag)
+{
+ tmr_x->ists = ~tmr_flag;
+}
+
+/**
+ * @brief generate tmr event
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR6, TMR7, TMR8,
+ * TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @param tmr_event
+ * this parameter can be one of the following values:
+ * - TMR_OVERFLOW_SWTRIG
+ * - TMR_C1_SWTRIG
+ * - TMR_C2_SWTRIG
+ * - TMR_C3_SWTRIG
+ * - TMR_C4_SWTRIG
+ * - TMR_HALL_SWTRIG
+ * - TMR_TRIGGER_SWTRIG
+ * - TMR_BRK_SWTRIG
+ * @retval none
+ */
+void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event)
+{
+ tmr_x->swevt |= tmr_event;
+}
+
+/**
+ * @brief tmr output enable(oen),this function is important for advtm output enable
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR8, TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void tmr_output_enable(tmr_type *tmr_x, confirm_state new_state)
+{
+ tmr_x->brk_bit.oen = new_state;
+}
+
+/**
+ * @brief set tmr select internal clock
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR12
+ * @retval none
+ */
+void tmr_internal_clock_set(tmr_type *tmr_x)
+{
+ tmr_x->stctrl_bit.smsel = TMR_SUB_MODE_DIABLE;
+}
+
+/**
+ * @brief set tmr output channel polarity
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14
+ * @param tmr_channel
+ * this parameter can be one of the following values:
+ * - TMR_SELECT_CHANNEL_1
+ * - TMR_SELECT_CHANNEL_2
+ * - TMR_SELECT_CHANNEL_3
+ * - TMR_SELECT_CHANNEL_4
+ * - TMR_SELECT_CHANNEL_1C
+ * - TMR_SELECT_CHANNEL_2C
+ * - TMR_SELECT_CHANNEL_3C
+ * - TMR_SELECT_CHANNEL_4C
+ * @param oc_polarity
+ * this parameter can be one of the following values:
+ * - TMR_POLARITY_ACTIVE_HIGH
+ * - TMR_POLARITY_ACTIVE_LOW
+ * @retval none
+ */
+void tmr_output_channel_polarity_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_polarity_active_type oc_polarity)
+{
+ uint16_t channel;
+
+ channel = tmr_channel;
+
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ tmr_x->cctrl_bit.c1p = (uint32_t)oc_polarity;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ tmr_x->cctrl_bit.c2p = (uint32_t)oc_polarity;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ tmr_x->cctrl_bit.c3p = (uint32_t)oc_polarity;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ tmr_x->cctrl_bit.c4p = (uint32_t)oc_polarity;
+ break;
+
+ case TMR_SELECT_CHANNEL_1C:
+ tmr_x->cctrl_bit.c1cp = (uint32_t)oc_polarity;
+ break;
+
+ case TMR_SELECT_CHANNEL_2C:
+ tmr_x->cctrl_bit.c2cp = (uint32_t)oc_polarity;
+ break;
+
+ case TMR_SELECT_CHANNEL_3C:
+ tmr_x->cctrl_bit.c3cp = (uint32_t)oc_polarity;
+ break;
+
+ case TMR_SELECT_CHANNEL_4C:
+ tmr_x->cctrl_bit.c4cp = (uint32_t)oc_polarity;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief config tmr external clock
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8
+ * @param es_divide
+ * this parameter can be one of the following values:
+ * - TMR_ES_FREQUENCY_DIV_1
+ * - TMR_ES_FREQUENCY_DIV_2
+ * - TMR_ES_FREQUENCY_DIV_4
+ * - TMR_ES_FREQUENCY_DIV_8
+ * @param es_polarity
+ * this parameter can be one of the following values:
+ * - TMR_ES_POLARITY_NON_INVERTED
+ * - TMR_ES_POLARITY_INVERTED
+ * @param es_filter (0x0~0xf)
+ * @retval none
+ */
+void tmr_external_clock_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
+ tmr_external_signal_polarity_type es_polarity, uint16_t es_filter)
+{
+ tmr_x->stctrl_bit.esdiv = es_divide;
+ tmr_x->stctrl_bit.esp = es_polarity;
+ tmr_x->stctrl_bit.esf = es_filter;
+}
+
+/**
+ * @brief config tmr external clock mode1
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR12
+ * @param es_divide
+ * this parameter can be one of the following values:
+ * - TMR_ES_FREQUENCY_DIV_1
+ * - TMR_ES_FREQUENCY_DIV_2
+ * - TMR_ES_FREQUENCY_DIV_4
+ * - TMR_ES_FREQUENCY_DIV_8
+ * @param es_polarity
+ * this parameter can be one of the following values:
+ * - TMR_ES_POLARITY_NON_INVERTED
+ * - TMR_ES_POLARITY_INVERTED
+ * @param es_filter (0x0~0xf)
+ * @retval none
+ */
+void tmr_external_clock_mode1_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
+ tmr_external_signal_polarity_type es_polarity, uint16_t es_filter)
+{
+ tmr_external_clock_config(tmr_x, es_divide, es_polarity, es_filter);
+ tmr_x->stctrl_bit.smsel = TMR_SUB_EXTERNAL_CLOCK_MODE_A;
+ tmr_x->stctrl_bit.stis = TMR_SUB_INPUT_SEL_EXTIN;
+}
+
+/**
+ * @brief config tmr external clock mode2
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8
+ * @param es_divide
+ * this parameter can be one of the following values:
+ * - TMR_ES_FREQUENCY_DIV_1
+ * - TMR_ES_FREQUENCY_DIV_2
+ * - TMR_ES_FREQUENCY_DIV_4
+ * - TMR_ES_FREQUENCY_DIV_8
+ * @param es_polarity
+ * this parameter can be one of the following values:
+ * - TMR_ES_POLARITY_NON_INVERTED
+ * - TMR_ES_POLARITY_INVERTED
+ * @param es_filter (0x0~0xf)
+ * @retval none
+ */
+void tmr_external_clock_mode2_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
+ tmr_external_signal_polarity_type es_polarity, uint16_t es_filter)
+{
+ tmr_external_clock_config(tmr_x, es_divide, es_polarity, es_filter);
+ tmr_x->stctrl_bit.ecmben = TRUE;
+}
+
+/**
+ * @brief config tmr encoder mode
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8
+ * @param encoder_mode
+ * this parameter can be one of the following values:
+ * - TMR_ENCODER_MODE_A
+ * - TMR_ENCODER_MODE_B
+ * - TMR_ENCODER_MODE_C
+ * @param ic1_polarity
+ * this parameter can be one of the following values:
+ * - TMR_INPUT_RISING_EDGE
+ * - TMR_INPUT_FALLING_EDGE
+ * - TMR_INPUT_BOTH_EDGE
+ * @param ic2_polarity
+ * this parameter can be one of the following values:
+ * - TMR_INPUT_RISING_EDGE
+ * - TMR_INPUT_FALLING_EDGE
+ * - TMR_INPUT_BOTH_EDGE
+ * @retval none
+ */
+void tmr_encoder_mode_config(tmr_type *tmr_x, tmr_encoder_mode_type encoder_mode, tmr_input_polarity_type \
+ ic1_polarity, tmr_input_polarity_type ic2_polarity)
+{
+ tmr_x->stctrl_bit.smsel = encoder_mode;
+
+ /* set ic1 polarity */
+ tmr_x->cctrl_bit.c1p = (ic1_polarity & 0x1);
+ tmr_x->cctrl_bit.c1cp = (ic1_polarity >> 1);
+ /* set ic1 as input channel */
+ tmr_x->cm1_input_bit.c1c = TMR_CC_CHANNEL_MAPPED_DIRECT;
+
+ /* set ic2 polarity */
+ tmr_x->cctrl_bit.c2p = (ic2_polarity & 0x1);
+ tmr_x->cctrl_bit.c2cp = (ic2_polarity >> 1);
+ /* set ic2 as input channel */
+ tmr_x->cm1_input_bit.c2c = TMR_CC_CHANNEL_MAPPED_DIRECT;
+}
+
+/**
+ * @brief set tmr force output
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14
+ * @param tmr_channel
+ * this parameter can be one of the following values:
+ * - TMR_SELECT_CHANNEL_1
+ * - TMR_SELECT_CHANNEL_2
+ * - TMR_SELECT_CHANNEL_3
+ * - TMR_SELECT_CHANNEL_4
+ * - TMR_SELECT_CHANNEL_5
+ * @param force_output
+ * this parameter can be one of the following values:
+ * - TMR_FORCE_OUTPUT_HIGH
+ * - TMR_FORCE_OUTPUT_LOW
+ * @retval none
+ */
+void tmr_force_output_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
+ tmr_force_output_type force_output)
+{
+ uint16_t channel;
+
+ channel = tmr_channel;
+
+ switch(channel)
+ {
+ case TMR_SELECT_CHANNEL_1:
+ tmr_x->cm1_output_bit.c1octrl = force_output;
+ break;
+
+ case TMR_SELECT_CHANNEL_2:
+ tmr_x->cm1_output_bit.c2octrl = force_output;
+ break;
+
+ case TMR_SELECT_CHANNEL_3:
+ tmr_x->cm2_output_bit.c3octrl = force_output;
+ break;
+
+ case TMR_SELECT_CHANNEL_4:
+ tmr_x->cm2_output_bit.c4octrl = force_output;
+ break;
+
+ case TMR_SELECT_CHANNEL_5:
+ tmr_x->cm3_output_bit.c5octrl = force_output;
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief config tmr dma control
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR2, TMR3, TMR4, TMR5, TMR8, TMR9, TMR10,
+ * TMR11, TMR12, TMR13, TMR14
+ * @param dma_length
+ * this parameter can be one of the following values:
+ * - TMR_DMA_TRANSFER_1BYTE
+ * - TMR_DMA_TRANSFER_2BYTES
+ * - TMR_DMA_TRANSFER_3BYTES
+ * ...
+ * - TMR_DMA_TRANSFER_17BYTES
+ * - TMR_DMA_TRANSFER_18BYTES
+ * @param dma_base_address
+ * this parameter can be one of the following values:
+ * - TMR_CTRL1_ADDRESS
+ * - TMR_CTRL2_ADDRESS
+ * - TMR_STCTRL_ADDRESS
+ * - TMR_IDEN_ADDRESS
+ * - TMR_ISTS_ADDRESS
+ * - TMR_SWEVT_ADDRESS
+ * - TMR_CM1_ADDRESS
+ * - TMR_CM2_ADDRESS
+ * - TMR_CCTRL_ADDRESS
+ * - TMR_CVAL_ADDRESS
+ * - TMR_DIV_ADDRESS
+ * - TMR_PR_ADDRESS
+ * - TMR_RPR_ADDRESS
+ * - TMR_C1DT_ADDRESS
+ * - TMR_C2DT_ADDRESS
+ * - TMR_C3DT_ADDRESS
+ * - TMR_C4DT_ADDRESS
+ * - TMR_BRK_ADDRESS
+ * - TMR_DMACTRL_ADDRESS
+ * @retval none
+ */
+void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_length, \
+ tmr_dma_address_type dma_base_address)
+{
+ tmr_x->dmactrl_bit.dtb = dma_length;
+ tmr_x->dmactrl_bit.addr = dma_base_address;
+}
+
+/**
+ * @brief config tmr brake mode and dead-time
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR8, TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @param brkdt_struct
+ * - to the structure of tmr_brkdt_config_type
+ * @retval none
+ */
+void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct)
+{
+ tmr_x->brk_bit.brken = brkdt_struct->brk_enable;
+ tmr_x->brk_bit.dtc = brkdt_struct->deadtime;
+ tmr_x->brk_bit.fcsodis = brkdt_struct->fcsodis_state;
+ tmr_x->brk_bit.fcsoen = brkdt_struct->fcsoen_state;
+ tmr_x->brk_bit.brkv = brkdt_struct->brk_polarity;
+ tmr_x->brk_bit.aoen = brkdt_struct->auto_output_enable;
+ tmr_x->brk_bit.wpc = brkdt_struct->wp_level;
+}
+
+/**
+ * @brief set tmr break input filter value
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR1, TMR8, TMR9, TMR10, TMR11, TMR12, TMR13, TMR14
+ * @param filter_value (0x0~0xf)
+ * @retval none
+ */
+void tmr_brk_filter_value_set(tmr_type *tmr_x, uint8_t filter_value)
+{
+ tmr_x->brk_bit.brkf = filter_value;
+}
+
+/**
+ * @brief set tmr2/tmr5 input channel remap
+ * @param tmr_x: select the tmr peripheral.
+ * this parameter can be one of the following values:
+ * TMR2, TMR5
+ * @param input_remap
+ * - TMR2_TMR8TRGOUT_TMR5_GPIO_TMR14_GPIO
+ * - TMR2_EMAC_PTP_TMR5_LICK_TMR14_ERTC_CLK
+ * - TMR2_USB_SOF_TMR5_LEXT_TMR14_HEXT_DIV
+ * - TMR5_ERTC_WKUP_TMR14_CLKOUT
+ * @retval none
+ */
+void tmr_iremap_config(tmr_type *tmr_x, tmr_input_remap_type input_remap)
+{
+ if(tmr_x == TMR2)
+ {
+ tmr_x->rmp_bit.tmr2_ch1_irmp = input_remap;
+ }
+ else if(tmr_x == TMR5)
+ {
+ tmr_x->rmp_bit.tmr5_ch4_irmp = input_remap;
+ }
+ else if(tmr_x == TMR14)
+ {
+ tmr_x->rmp_bit.tmr14_ch1_irmp = input_remap;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_trng.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_trng.c
new file mode 100644
index 00000000000..44a54fcd5a8
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_trng.c
@@ -0,0 +1,229 @@
+/**
+ **************************************************************************
+ * @file at32f45x_trng.c
+ * @brief contains all the functions for the trng firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup TRNG
+ * @brief TRNG driver modules
+ * @{
+ */
+
+#ifdef TRNG_MODULE_ENABLED
+
+/** @defgroup TRNG_private_functions
+ * @{
+ */
+
+/**
+ * @brief deinitializes the trng peripheral registers to their default reset values.
+ * @param none
+ * @retval none
+ */
+void trng_reset(void)
+{
+ crm_periph_reset(CRM_TRNG_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_TRNG_PERIPH_RESET, FALSE);
+}
+
+/**
+ * @brief enable or disable the trng peripheral.
+ * @param new_state: new state of the trng peripheral.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void trng_enable(confirm_state new_state)
+{
+ TRNG->ctrl_bit.nsen = new_state;
+}
+
+/**
+ * @brief enable or disable the trng interrupt.
+ * @param trng_int: specifies the trng interrupt sources to be enabled or disabled.
+ * this parameter can be any combination of the following values:
+ * - TRNG_FIE_INT: fail interrupt
+ * - TRNG_DTRIE_INT: data port ready interrupt
+ * @param new_state: new state of the specified trng interrupt.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void trng_interrupt_enable(uint32_t trng_int, confirm_state new_state)
+{
+ if(new_state)
+ {
+ TRNG->ctrl |= trng_int;
+ }else
+ {
+ TRNG->ctrl &= ~trng_int;
+ }
+}
+
+/**
+ * @brief set the trng clock divider factor
+ * @param factor: clock divider value, from 0 to 15
+ * @retval none
+ */
+void trng_clock_divider_set(uint8_t factor)
+{
+ trng_conditioning_and_buffer_enable(FALSE);
+
+ TRNG->ctrl_bit.clkdiv = factor;
+
+ trng_conditioning_and_buffer_enable(TRUE);
+}
+
+/**
+ * @brief enable or disable conditioning unit and output buffer
+ * @param new_state: new state of the conditioning unit and output buffer.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void trng_conditioning_and_buffer_enable(confirm_state new_state)
+{
+ TRNG->ctrl_bit.cudis = !new_state;
+}
+
+/**
+ * @brief lock the programming register
+ * @param none
+ * @retval none
+ */
+void trng_programing_register_lock(void)
+{
+ TRNG->ctrl_bit.prglk = TRUE;
+}
+
+/**
+ * @brief return a 32-bit random number.
+ * @param none
+ * @retval 32-bit random number.
+ */
+uint32_t trng_value_get(void)
+{
+ return TRNG->dt;
+}
+
+/**
+ * @brief check whether the specified trng flag is set or not.
+ * @param flag: specifies the trng flag to check.
+ * this parameter can be one of the following values:
+ * - TRNG_DTRDY_FLAG: data ready flag.
+ * - TRNG_CKFES_FLAG: clock error current flag.
+ * - TRNG_ESFES_FLAG: entropy source error current flag.
+ * - TRNG_CEFIS_FLAG: clock error interrupt flag.
+ * - TRNG_ESFIS_FLAG: entropy source interrupt flag.
+ * @retval the new state of flag (SET or RESET).
+ */
+flag_status trng_flag_get(uint32_t flag)
+{
+ if(TRNG->sts & flag)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief check whether the specified trng interrupt flag is set or not.
+ * @param flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - TRNG_DTRDY_FLAG: data ready flag.
+ * - TRNG_CKFES_FLAG: clock error current flag.
+ * - TRNG_ESFES_FLAG: entropy source error current flag.
+ * - TRNG_CEFIS_FLAG: clock error interrupt flag.
+ * - TRNG_ESFIS_FLAG: entropy source interrupt flag.
+ * @retval the new state of usart_flag (SET or RESET).
+ */
+flag_status trng_interrupt_flag_get(uint32_t flag)
+{
+ flag_status bit_status = RESET;
+ switch(flag)
+ {
+ case TRNG_DTRDY_FLAG:
+ if(TRNG->ctrl & TRNG_DTRIE_INT)
+ {
+ bit_status = (TRNG->sts & flag) ? SET : RESET;
+ }
+ break;
+ case TRNG_CKFES_FLAG:
+ case TRNG_ESFES_FLAG:
+ case TRNG_CEFIS_FLAG:
+ case TRNG_ESFIS_FLAG:
+ if(TRNG->ctrl & TRNG_FIE_INT)
+ {
+ bit_status = (TRNG->sts & flag) ? SET : RESET;
+ }
+ break;
+ default:
+ break;
+ }
+ return bit_status;
+}
+
+/**
+ * @brief clear the trng flag.
+ * @param flag: specifies the flag to clear.
+ * this parameter can be one of the following values:
+ * - TRNG_CKFES_FLAG: clock error current flag.
+ * - TRNG_ESFES_FLAG: entropy source error current flag.
+ * - TRNG_CEFIS_FLAG: clock error interrupt flag.
+ * - TRNG_ESFIS_FLAG: entropy source interrupt flag.
+ * @retval none
+ */
+void trng_flag_clear(uint32_t flag)
+{
+ switch(flag)
+ {
+ case TRNG_CKFES_FLAG:
+ case TRNG_ESFES_FLAG:
+ TRNG->ctrl_bit.fesclr = TRUE;
+ break;
+ case TRNG_CEFIS_FLAG:
+ case TRNG_ESFIS_FLAG:
+ TRNG->sts = flag;
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_usart.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_usart.c
new file mode 100644
index 00000000000..c74f98c7c64
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_usart.c
@@ -0,0 +1,881 @@
+/**
+ **************************************************************************
+ * @file at32f45x_usart.c
+ * @brief contains all the functions for the usart firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+/* includes ------------------------------------------------------------------*/
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup USART
+ * @brief USART driver modules
+ * @{
+ */
+
+#ifdef USART_MODULE_ENABLED
+
+/** @defgroup USART_private_functions
+ * @{
+ */
+
+/**
+ * @brief deinitialize the usart peripheral registers to their default reset values.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @retval none
+ */
+void usart_reset(usart_type* usart_x)
+{
+ if(usart_x == USART1)
+ {
+ crm_periph_reset(CRM_USART1_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_USART1_PERIPH_RESET, FALSE);
+ }
+ else if(usart_x == USART2)
+ {
+ crm_periph_reset(CRM_USART2_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_USART2_PERIPH_RESET, FALSE);
+ }
+}
+
+/**
+ * @brief initialize the usart peripheral according to the specified parameters.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param baud_rate: configure the usart communication baud rate.
+ * @param data_bit: data bits transmitted or received in a frame
+ * this parameter can be one of the following values:
+ * - USART_DATA_7BITS
+ * - USART_DATA_8BITS
+ * - USART_DATA_9BITS.
+ * note:
+ * - when parity check is disabled, the data bit width is the actual data bit number.
+ * - when parity check is enabled, the data bit width is the actual data bit number minus 1, and the MSB bit is replaced with the parity bit.
+ * @param stop_bit: stop bits transmitted
+ * this parameter can be one of the following values:
+ * - USART_STOP_1_BIT
+ * - USART_STOP_0_5_BIT.
+ * - USART_STOP_2_BIT
+ * - USART_STOP_1_5_BIT.
+ * @retval none
+ */
+void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type data_bit, usart_stop_bit_num_type stop_bit)
+{
+ crm_clocks_freq_type clocks_freq;
+ uint32_t apb_clock, temp_val;
+ crm_clocks_freq_get(&clocks_freq);
+ if(usart_x == USART1)
+ {
+ apb_clock = clocks_freq.apb2_freq;
+ }
+ else
+ {
+ apb_clock = clocks_freq.apb1_freq;
+ }
+ temp_val = (apb_clock * 10 / baud_rate);
+ if((temp_val % 10) < 5)
+ {
+ temp_val = (temp_val / 10);
+ }
+ else
+ {
+ temp_val = (temp_val / 10) + 1;
+ }
+ usart_x->baudr_bit.div = temp_val;
+ if(data_bit == USART_DATA_7BITS)
+ {
+ usart_x->ctrl1_bit.dbn1 = 1;
+ usart_x->ctrl1_bit.dbn0 = 0;
+ }
+ else if(data_bit == USART_DATA_8BITS)
+ {
+ usart_x->ctrl1_bit.dbn1 = 0;
+ usart_x->ctrl1_bit.dbn0 = 0;
+ }
+ else
+ {
+ usart_x->ctrl1_bit.dbn1 = 0;
+ usart_x->ctrl1_bit.dbn0 = 1;
+ }
+ usart_x->ctrl2_bit.stopbn = stop_bit;
+}
+
+/**
+ * @brief usart parity selection config.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param parity: select the none, odd or even parity.
+ * this parameter can be one of the following values:
+ * - USART_PARITY_NONE
+ * - USART_PARITY_EVEN.
+ * - USART_PARITY_ODD
+ * @retval none
+ */
+void usart_parity_selection_config(usart_type* usart_x, usart_parity_selection_type parity)
+{
+ if(parity == USART_PARITY_NONE)
+ {
+ usart_x->ctrl1_bit.psel = FALSE;
+ usart_x->ctrl1_bit.pen = FALSE;
+ }
+ else if(parity == USART_PARITY_EVEN)
+ {
+ usart_x->ctrl1_bit.psel = FALSE;
+ usart_x->ctrl1_bit.pen = TRUE;
+ }
+ else if(parity == USART_PARITY_ODD)
+ {
+ usart_x->ctrl1_bit.psel = TRUE;
+ usart_x->ctrl1_bit.pen = TRUE;
+ }
+}
+
+/**
+ * @brief enable or disable the specified usart peripheral.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param new_state: new state of the usart peripheral.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl1_bit.uen = new_state;
+}
+
+/**
+ * @brief usart transmitter enable.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void usart_transmitter_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl1_bit.ten = new_state;
+}
+
+/**
+ * @brief usart receiver enable.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param new_state: TRUE or FALSE.
+ * @retval none
+ */
+void usart_receiver_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl1_bit.ren = new_state;
+}
+
+/**
+ * @brief usart clock config.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param clk_pol: polarity of the clock output on the ck pin.
+ * this parameter can be one of the following values:
+ * - USART_CLOCK_POLARITY_LOW
+ * - USART_CLOCK_POLARITY_HIGH
+ * @param clk_pha: phase of the clock output on the ck pin.
+ * this parameter can be one of the following values:
+ * - USART_CLOCK_PHASE_1EDGE
+ * - USART_CLOCK_PHASE_2EDGE
+ * @param clk_lb: whether the clock pulse of the last data bit transmitted (MSB) is outputted on the ck pin.
+ * this parameter can be one of the following values:
+ * - USART_CLOCK_LAST_BIT_NONE
+ * - USART_CLOCK_LAST_BIT_OUTPUT
+ * @retval none
+ */
+void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, usart_clock_phase_type clk_pha, usart_lbcp_type clk_lb)
+{
+ usart_x->ctrl2_bit.clkpol = clk_pol;
+ usart_x->ctrl2_bit.clkpha = clk_pha;
+ usart_x->ctrl2_bit.lbcp = clk_lb;
+}
+
+/**
+ * @brief usart enable the ck pin.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param new_state: TRUE or FALSE
+ * @retval none
+ */
+void usart_clock_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl2_bit.clken = new_state;
+}
+
+/**
+ * @brief enable or disable the specified usart interrupts.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param usart_int: specifies the USART interrupt sources to be enabled or disabled.
+ * this parameter can be one of the following values:
+ * - USART_IDLE_INT: idle interrupt
+ * - USART_RDBF_INT: rdbf interrupt
+ * - USART_TDC_INT: tdc interrupt
+ * - USART_TDBE_INT: tdbe interrupt
+ * - USART_PERR_INT: perr interrupt
+ * - USART_BF_INT: break frame interrupt
+ * - USART_ERR_INT: err interrupt
+ * - USART_CTSCF_INT: ctscf interrupt
+ * - USART_CMD_INT: cmd interrupt
+ * - USART_RTOD_INT: rtod interrupt
+ * @param new_state: new state of the specified usart interrupts.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_interrupt_enable(usart_type* usart_x, uint32_t usart_int, confirm_state new_state)
+{
+ if(new_state == TRUE)
+ PERIPH_REG((uint32_t)usart_x, usart_int) |= PERIPH_REG_BIT(usart_int);
+ else
+ PERIPH_REG((uint32_t)usart_x, usart_int) &= ~PERIPH_REG_BIT(usart_int);
+}
+
+/**
+ * @brief enable or disable the usart's dma transmitter interface.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param new_state: new state of the dma request sources.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_dma_transmitter_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl3_bit.dmaten = new_state;
+}
+
+/**
+ * @brief enable or disable the usart's dma receiver interface.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param new_state: new state of the dma request sources.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_dma_receiver_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl3_bit.dmaren = new_state;
+}
+
+/**
+ * @brief set the wakeup id of the usart.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param usart_id: the matching id(0x0~0xFF).
+ * @retval none
+ */
+void usart_wakeup_id_set(usart_type* usart_x, uint8_t usart_id)
+{
+ if(usart_x->ctrl2_bit.idbn == USART_ID_FIXED_4_BIT)
+ {
+ usart_x->ctrl2_bit.idl = (usart_id & 0x0F);
+ usart_x->ctrl2_bit.idh = 0;
+ }
+ else
+ {
+ usart_x->ctrl2_bit.idl = (usart_id & 0x0F);
+ usart_x->ctrl2_bit.idh = ((usart_id & 0xF0) >> 4);
+ }
+}
+
+/**
+ * @brief select the usart wakeup method in multi-processor communication.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param wakeup_mode: determines the way to wake up usart method.
+ * this parameter can be one of the following values:
+ * - USART_WAKEUP_BY_IDLE_FRAME
+ * - USART_WAKEUP_BY_MATCHING_ID
+ * @retval none
+ */
+void usart_wakeup_mode_set(usart_type* usart_x, usart_wakeup_mode_type wakeup_mode)
+{
+ usart_x->ctrl1_bit.wum = wakeup_mode;
+}
+
+/**
+ * @brief config the usart in mute mode in multi-processor communication.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param new_state: new state of the usart mute mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_receiver_mute_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl1_bit.rm = new_state;
+}
+
+/**
+ * @brief set the usart break frame bit num.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param break_bit: specifies the break bit num.
+ * this parameter can be one of the following values:
+ * - USART_BREAK_10BITS
+ * - USART_BREAK_11BITS
+ * @retval none
+ */
+void usart_break_bit_num_set(usart_type* usart_x, usart_break_bit_num_type break_bit)
+{
+ usart_x->ctrl2_bit.bfbn = break_bit;
+}
+
+/**
+ * @brief enable or disable the usart lin mode.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param new_state: new state of the usart lin mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_lin_mode_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl2_bit.linen = new_state;
+}
+
+/**
+ * @brief transmit single data through the usart peripheral.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param data: the data to transmit.
+ * @retval none
+ */
+void usart_data_transmit(usart_type* usart_x, uint16_t data)
+{
+ usart_x->dt = (data & 0x01FF);
+}
+
+/**
+ * @brief return the most recent received data by the usart peripheral.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @retval the received data.
+ */
+uint16_t usart_data_receive(usart_type* usart_x)
+{
+ return (uint16_t)(usart_x->dt);
+}
+
+/**
+ * @brief transmit break characters.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @retval none
+ */
+void usart_break_send(usart_type* usart_x)
+{
+ usart_x->ctrl1_bit.sbf = TRUE;
+}
+
+/**
+ * @brief config the specified usart smartcard guard time.
+ * @note The guard time bits are not available for UART4, UART5, UART7 or UART8.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param guard_time_val: specifies the guard time (0x00~0xFF).
+ * @retval none
+ */
+void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val)
+{
+ usart_x->gdiv_bit.scgt = guard_time_val;
+}
+
+/**
+ * @brief config the irda/smartcard division.
+ * @note the division are not available for UART4, UART5, UART7 or UART8.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param div_val: specifies the division.
+ * @retval none
+ */
+void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val)
+{
+ usart_x->gdiv_bit.isdiv = div_val;
+}
+
+/**
+ * @brief enable or disable the usart smart card mode.
+ * @note the smart card mode are not available for UART4, UART5, UART7 or UART8.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param new_state: new state of the smart card mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl3_bit.scmen = new_state;
+}
+
+/**
+ * @brief enable or disable nack transmission in smartcard mode.
+ * @note the smart card nack are not available for UART4, UART5, UART7 or UART8.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param new_state: new state of the nack transmission.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_smartcard_nack_set(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl3_bit.scnacken = new_state;
+}
+
+/**
+ * @brief enable or disable the usart single line bidirectional half-duplex communication.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param new_state: new state of the single line half-duplex select.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_single_line_halfduplex_select(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl3_bit.slben = new_state;
+}
+
+/**
+ * @brief enable or disable the usart's irda interface.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param new_state: new state of the irda mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl3_bit.irdaen = new_state;
+}
+
+/**
+ * @brief configure the usart's irda low power.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param new_state: new state of the irda mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl3_bit.irdalp = new_state;
+}
+
+/**
+ * @brief configure the usart's hardware flow control.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param flow_state: specifies the hardware flow control.
+ * this parameter can be one of the following values:
+ * - USART_HARDWARE_FLOW_NONE
+ * - USART_HARDWARE_FLOW_RTS,
+ * - USART_HARDWARE_FLOW_CTS,
+ * - USART_HARDWARE_FLOW_RTS_CTS
+ * @retval none
+ */
+void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state)
+{
+ if(flow_state == USART_HARDWARE_FLOW_NONE)
+ {
+ usart_x->ctrl3_bit.rtsen = FALSE;
+ usart_x->ctrl3_bit.ctsen = FALSE;
+ }
+ else if(flow_state == USART_HARDWARE_FLOW_RTS)
+ {
+ usart_x->ctrl3_bit.rtsen = TRUE;
+ usart_x->ctrl3_bit.ctsen = FALSE;
+ }
+ else if(flow_state == USART_HARDWARE_FLOW_CTS)
+ {
+ usart_x->ctrl3_bit.rtsen = FALSE;
+ usart_x->ctrl3_bit.ctsen = TRUE;
+ }
+ else if(flow_state == USART_HARDWARE_FLOW_RTS_CTS)
+ {
+ usart_x->ctrl3_bit.rtsen = TRUE;
+ usart_x->ctrl3_bit.ctsen = TRUE;
+ }
+}
+
+/**
+ * @brief check whether the specified usart flag is set or not.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - USART_CMDF_FLAG: character match detection flag (not available for USART4,USART5,USART6,USART7 and USART8)
+ * - USART_RTODF_FLAG: receiver time out detection flag
+ * - USART_CTSCF_FLAG: cts change flag (not available for USART5,USART6,UART7 and UART8)
+ * - USART_BFF_FLAG: break frame flag
+ * - USART_TDBE_FLAG: transmit data buffer empty flag
+ * - USART_TDC_FLAG: transmit data complete flag
+ * - USART_RDBF_FLAG: receive data buffer full flag
+ * - USART_IDLEF_FLAG: idle flag
+ * - USART_ROERR_FLAG: receiver overflow error flag
+ * - USART_NERR_FLAG: noise error flag
+ * - USART_FERR_FLAG: framing error flag
+ * - USART_PERR_FLAG: parity error flag
+ * @retval the new state of usart_flag (SET or RESET).
+ */
+flag_status usart_flag_get(usart_type* usart_x, uint32_t flag)
+{
+ if(usart_x->sts & flag)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+/**
+ * @brief check whether the specified usart interrupt flag is set or not.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param flag: specifies the flag to check.
+ * this parameter can be one of the following values:
+ * - USART_RTODF_FLAG: receiver time out detection flag
+ * - USART_CMDF_FLAG: character match detection flag
+ * - USART_CTSCF_FLAG: cts change flag
+ * - USART_BFF_FLAG: break frame flag
+ * - USART_TDBE_FLAG: transmit data buffer empty flag
+ * - USART_TDC_FLAG: transmit data complete flag
+ * - USART_RDBF_FLAG: receive data buffer full flag
+ * - USART_IDLEF_FLAG: idle flag
+ * - USART_ROERR_FLAG: receiver overflow error flag
+ * - USART_NERR_FLAG: noise error flag
+ * - USART_FERR_FLAG: framing error flag
+ * - USART_PERR_FLAG: parity error flag
+ * @retval the new state of usart_flag (SET or RESET).
+ */
+flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag)
+{
+ flag_status int_status = RESET;
+
+ switch(flag)
+ {
+ case USART_CTSCF_FLAG:
+ int_status = (flag_status)usart_x->ctrl3_bit.ctscfien;
+ break;
+ case USART_BFF_FLAG:
+ int_status = (flag_status)usart_x->ctrl2_bit.bfien;
+ break;
+ case USART_TDBE_FLAG:
+ int_status = (flag_status)usart_x->ctrl1_bit.tdbeien;
+ break;
+ case USART_TDC_FLAG:
+ int_status = (flag_status)usart_x->ctrl1_bit.tdcien;
+ break;
+ case USART_RDBF_FLAG:
+ int_status = (flag_status)usart_x->ctrl1_bit.rdbfien;
+ break;
+ case USART_ROERR_FLAG:
+ int_status = (flag_status)(usart_x->ctrl1_bit.rdbfien || usart_x->ctrl3_bit.errien);
+ break;
+ case USART_IDLEF_FLAG:
+ int_status = (flag_status)usart_x->ctrl1_bit.idleien;
+ break;
+ case USART_NERR_FLAG:
+ case USART_FERR_FLAG:
+ int_status = (flag_status)usart_x->ctrl3_bit.errien;
+ break;
+ case USART_PERR_FLAG:
+ int_status = (flag_status)usart_x->ctrl1_bit.perrien;
+ break;
+ case USART_RTODF_FLAG:
+ int_status = (flag_status)usart_x->ctrl1_bit.retodie;
+ break;
+ case USART_CMDF_FLAG:
+ int_status = (flag_status)usart_x->ctrl1_bit.cmdie;
+ break;
+ default:
+ int_status = RESET;
+ break;
+ }
+
+ if(int_status != SET)
+ {
+ return RESET;
+ }
+
+ if(usart_x->sts & flag)
+ {
+ return SET;
+ }
+ else
+ {
+ return RESET;
+ }
+}
+
+
+/**
+ * @brief clear the usart's pending flags.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param flag: specifies the flag to clear.
+ * this parameter can be any combination of the following values:
+ * - USART_CMDF_FLAG: character match detection flag
+ * - USART_RTODF_FLAG: receiver time out detection flag
+ * - USART_CTSCF_FLAG: (not available for USART5,USART6,UART7 and UART8).
+ * - USART_BFF_FLAG:
+ * - USART_TDC_FLAG:
+ * - USART_RDBF_FLAG:
+ * - USART_PERR_FLAG:
+ * - USART_FERR_FLAG:
+ * - USART_NERR_FLAG:
+ * - USART_ROERR_FLAG:
+ * - USART_IDLEF_FLAG:
+ * @note
+ * - USART_PERR_FLAG, USART_FERR_FLAG, USART_NERR_FLAG, USART_ROERR_FLAG and USART_IDLEF_FLAG are cleared by software
+ * sequence: a read operation to usart sts register (usart_flag_get())
+ * followed by a read operation to usart dt register (usart_data_receive()).
+ * - USART_RDBF_FLAG can be also cleared by a read to the usart dt register(usart_data_receive()).
+ * - USART_TDC_FLAG can be also cleared by software sequence: a read operation to usart sts register (usart_flag_get())
+ * followed by a write operation to usart dt register (usart_data_transmit()).
+ * - USART_TDBE_FLAG is cleared only by a write to the usart dt register(usart_data_transmit()).
+ * @retval none
+ */
+void usart_flag_clear(usart_type* usart_x, uint32_t flag)
+{
+ if(USART_RTODF_FLAG == flag)
+ {
+ usart_x->ifc = USART_RTODF_FLAG;
+ }
+ else if(USART_CMDF_FLAG == flag)
+ {
+ usart_x->ifc = USART_CMDF_FLAG;
+ }
+ else if(flag & (USART_PERR_FLAG | USART_FERR_FLAG | USART_NERR_FLAG | USART_ROERR_FLAG | USART_IDLEF_FLAG))
+ {
+ usart_x->sts;
+ usart_x->dt;
+ }
+ else
+ {
+ usart_x->sts = ~flag;
+ }
+}
+
+/**
+ * @brief configure the usart's rs485 transmit delay time.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param start_delay_time: transmit start delay time.
+ * @param complete_delay_time: transmit complete delay time.
+ * @retval none
+ */
+void usart_rs485_delay_time_config(usart_type* usart_x, uint8_t start_delay_time, uint8_t complete_delay_time)
+{
+ usart_x->ctrl1_bit.tsdt = start_delay_time;
+ usart_x->ctrl1_bit.tcdt = complete_delay_time;
+}
+
+/**
+ * @brief swap the usart's transmit receive pin.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param new_state: new state of the usart peripheral.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl2_bit.trpswap = new_state;
+}
+
+/**
+ * @brief set the usart's identification bit num.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param id_bit_num: the usart wakeup identification bit num.
+ * this parameter can be: USART_ID_FIXED_4_BIT or USART_ID_RELATED_DATA_BIT.
+ * @retval none
+ */
+void usart_id_bit_num_set(usart_type* usart_x, usart_identification_bit_num_type id_bit_num)
+{
+ usart_x->ctrl2_bit.idbn = (uint8_t)id_bit_num;
+}
+
+/**
+ * @brief set the usart's de polarity.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param de_polarity: the usart de polarity selection.
+ * this parameter can be: USART_DE_POLARITY_HIGH or USART_DE_POLARITY_LOW.
+ * @retval none
+ */
+void usart_de_polarity_set(usart_type* usart_x, usart_de_polarity_type de_polarity)
+{
+ usart_x->ctrl3_bit.dep = (uint8_t)de_polarity;
+}
+
+/**
+ * @brief enable or disable the usart's rs485 mode.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param new_state: new state of the irda mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_rs485_mode_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl3_bit.rs485en = new_state;
+}
+
+/**
+ * @brief enable or disable the usart's most significant bit transmit first.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param new_state: new state of the irda mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_msb_transmit_first_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl2_bit.mtf = new_state;
+}
+
+/**
+ * @brief enable or disable the usart's dt register polarity reverse.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param new_state: new state of the irda mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_dt_polarity_reverse(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl2_bit.dtrev = new_state;
+}
+
+/**
+ * @brief enable or disable the usart's tx pin polarity reverse.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param new_state: new state of the irda mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_transmit_pin_polarity_reverse(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl2_bit.txrev = new_state;
+}
+
+/**
+ * @brief enable or disable the usart's rx pin polarity reverse.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param new_state: new state of the irda mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_receive_pin_polarity_reverse(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl2_bit.rxrev = new_state;
+}
+
+/**
+ * @brief enable or disable the usart's receiver timeout detection enable.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param new_state: new state of the irda mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_receiver_timeout_detection_enable(usart_type* usart_x, confirm_state new_state)
+{
+ usart_x->ctrl1_bit.rtoden = new_state;
+}
+
+/**
+ * @brief config the usart receiver timeout value.
+ * @param usart_x: select the usart or the uart peripheral.
+ * this parameter can be one of the following values:
+ * USART1, USART2, USART3, USART4, USART5, USART6, USART7,or USART8.
+ * @param new_state: new state of the irda mode.
+ * this parameter can be: TRUE or FALSE.
+ * @retval none
+ */
+void usart_receiver_timeout_value_set(usart_type* usart_x, uint32_t value)
+{
+ usart_x->rtov_bit.rtov = value;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_usb.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_usb.c
new file mode 100644
index 00000000000..02e701fa718
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_usb.c
@@ -0,0 +1,1063 @@
+/**
+ **************************************************************************
+ * @file at32f45x_usb.c
+ * @brief contains all the functions for the usb firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup USB
+ * @brief USB driver modules
+ * @{
+ */
+
+#ifdef USB_MODULE_ENABLED
+
+/** @defgroup USB_private_functions
+ * @{
+ */
+
+#ifdef OTGFS_USB_GLOBAL
+/**
+ * @brief usb global core soft reset
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @retval error status
+ */
+error_status usb_global_reset(otg_global_type *usbx)
+{
+ uint32_t timeout = 0;
+ while(usbx->grstctl_bit.ahbidle == RESET)
+ {
+ if(timeout ++ > 200000)
+ {
+ break;
+ }
+ }
+ timeout = 0;
+ usbx->grstctl_bit.csftrst = TRUE;
+ while(usbx->grstctl_bit.csftrst == SET)
+ {
+ if(timeout ++ > 200000)
+ {
+ break;
+ }
+ }
+ return SUCCESS;
+}
+
+/**
+ * @brief usb global initialization
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @retval none
+ */
+void usb_global_init(otg_global_type *usbx)
+{
+ /* reset otg moudle */
+ usb_global_reset(usbx);
+
+ /* exit power down mode */
+ usbx->gccfg_bit.pwrdown = TRUE;
+}
+
+/**
+ * @brief usb global select usb core (otg1 or otg2).
+ * @param usb_id: select otg1 or otg2
+ * this parameter can be one of the following values:
+ * - USB_OTG1_ID
+ * @retval usb global register type pointer
+ */
+otg_global_type *usb_global_select_core(uint8_t usb_id)
+{
+ UNUSED(usb_id);
+ return OTG1_GLOBAL;
+}
+
+/**
+ * @brief flush tx fifo
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @param fifo_num: tx fifo num,when fifo_num=16,flush all tx fifo
+ * parameter as following values: 0-16
+ * @retval none
+ */
+void usb_flush_tx_fifo(otg_global_type *usbx, uint32_t fifo_num)
+{
+ uint32_t timeout = 0;
+ /* set flush fifo number */
+ usbx->grstctl_bit.txfnum = fifo_num;
+
+ /* start flush fifo */
+ usbx->grstctl_bit.txfflsh = TRUE;
+
+ while(usbx->grstctl_bit.txfflsh == TRUE)
+ {
+ if(timeout ++ > 200000)
+ {
+ break;
+ }
+ }
+}
+
+/**
+ * @brief flush rx fifo
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @retval none
+ */
+void usb_flush_rx_fifo(otg_global_type *usbx)
+{
+ uint32_t timeout = 0;
+ usbx->grstctl_bit.rxfflsh = TRUE;
+ while(usbx->grstctl_bit.rxfflsh == TRUE)
+ {
+ if(timeout ++ > 200000)
+ {
+ break;
+ }
+ }
+}
+
+/**
+ * @brief usb interrupt mask enable
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @param interrupt:
+ * this parameter can be any combination of the following values:
+ * - USB_OTG_MODEMIS_INT
+ * - USB_OTG_OTGINT_INT
+ * - USB_OTG_SOF_INT
+ * - USB_OTG_RXFLVL_INT
+ * - USB_OTG_NPTXFEMP_INT
+ * - USB_OTG_GINNAKEFF_INT
+ * - USB_OTG_GOUTNAKEFF_INT
+ * - USB_OTG_ERLYSUSP_INT
+ * - USB_OTG_USBSUSP_INT
+ * - USB_OTG_USBRST_INT
+ * - USB_OTG_ENUMDONE_INT
+ * - USB_OTG_ISOOUTDROP_INT
+ * - USB_OTG_IEPT_INT
+ * - USB_OTG_OEPT_INT
+ * - USB_OTG_INCOMISOIN_INT
+ * - USB_OTG_INCOMPIP_INCOMPISOOUT_INT
+ * - USB_OTG_PRT_INT
+ * - USB_OTG_HCH_INT
+ * - USB_OTG_PTXFEMP_INT
+ * - USB_OTG_CONIDSCHG_INT
+ * - USB_OTG_DISCON_INT
+ * - USB_OTG_WKUP_INT
+ * @param new_state: TRUE or FALSE
+ * @retval none
+ */
+void usb_global_interrupt_enable(otg_global_type *usbx, uint16_t interrupt, confirm_state new_state)
+{
+ if(new_state == TRUE)
+ {
+ usbx->gintmsk |= interrupt;
+ }
+ else
+ {
+ usbx->gintmsk &= ~interrupt;
+ }
+}
+
+/**
+ * @brief get all global core interrupt flag
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @retval intterupt flag
+ */
+uint32_t usb_global_get_all_interrupt(otg_global_type *usbx)
+{
+ uint32_t intsts = usbx->gintsts;
+ return intsts & usbx->gintmsk;
+}
+
+/**
+ * @brief clear the global interrupt flag
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * - OTG2_GLOBAL
+ * @param flag: interrupt flag
+ * this parameter can be any combination of the following values:
+ * - USB_OTG_MODEMIS_FLAG
+ * - USB_OTG_OTGINT_FLAG
+ * - USB_OTG_SOF_FLAG
+ * - USB_OTG_RXFLVL_FLAG
+ * - USB_OTG_NPTXFEMP_FLAG
+ * - USB_OTG_GINNAKEFF_FLAG
+ * - USB_OTG_GOUTNAKEFF_FLAG
+ * - USB_OTG_ERLYSUSP_FLAG
+ * - USB_OTG_USBSUSP_FLAG
+ * - USB_OTG_USBRST_FLAG
+ * - USB_OTG_ENUMDONE_FLAG
+ * - USB_OTG_ISOOUTDROP_FLAG
+ * - USB_OTG_EOPF_FLAG
+ * - USB_OTG_IEPT_FLAG
+ * - USB_OTG_OEPT_FLAG
+ * - USB_OTG_INCOMISOIN_FLAG
+ * - USB_OTG_INCOMPIP_INCOMPISOOUT_FLAG
+ * - USB_OTG_PRT_FLAG
+ * - USB_OTG_HCH_FLAG
+ * - USB_OTG_PTXFEMP_FLAG
+ * - USB_OTG_CONIDSCHG_FLAG
+ * - USB_OTG_DISCON_FLAG
+ * - USB_OTG_WKUP_FLAG
+ * @retval none
+ */
+void usb_global_clear_interrupt(otg_global_type *usbx, uint32_t flag)
+{
+ usbx->gintsts = flag;
+}
+
+/**
+ * @brief usb global interrupt enable
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * OTG1_GLOBAL
+ * @retval none
+ */
+void usb_interrupt_enable(otg_global_type *usbx)
+{
+ usbx->gahbcfg_bit.glbintmsk = TRUE;
+}
+
+/**
+ * @brief usb global interrupt disable
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @retval none
+ */
+void usb_interrupt_disable(otg_global_type *usbx)
+{
+ usbx->gahbcfg_bit.glbintmsk = FALSE;
+}
+
+/**
+ * @brief usb set rx fifo size
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @param size: rx fifo size
+ * @retval none
+ */
+void usb_set_rx_fifo(otg_global_type *usbx, uint16_t size)
+{
+ usbx->grxfsiz = size;
+}
+
+/**
+ * @brief usb set tx fifo size
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @param txfifo: the fifo number
+ * @param size: tx fifo size
+ * @retval none
+ */
+void usb_set_tx_fifo(otg_global_type *usbx, uint8_t txfifo, uint16_t size)
+{
+ uint8_t i_index = 0;
+ uint32_t offset = 0;
+
+ offset = usbx->grxfsiz;
+ if(txfifo == 0)
+ {
+ usbx->gnptxfsiz_ept0tx = offset | (size << 16);
+ }
+ else
+ {
+ offset += usbx->gnptxfsiz_ept0tx_bit.nptxfdep;
+ for(i_index = 0; i_index < (txfifo - 1); i_index ++)
+ {
+ offset += usbx->dieptxfn_bit[i_index].ineptxfdep;
+ }
+ usbx->dieptxfn[txfifo - 1] = offset | (size << 16);
+ }
+}
+
+
+/**
+ * @brief set otg mode(device or host mode)
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @param mode:
+ this parameter can be one of the following values:
+ * - OTG_DEVICE_MODE
+ * - OTG_HOST_MODE
+ * - OTG_DRD_MODE
+ * @retval none
+ */
+void usb_global_set_mode(otg_global_type *usbx, uint32_t mode)
+{
+ /* set otg to device mode */
+ if(mode == OTG_DEVICE_MODE)
+ {
+ usbx->gusbcfg_bit.fhstmode = FALSE;
+ usbx->gusbcfg_bit.fdevmode = TRUE;
+ }
+
+ /* set otg to host mode */
+ if(mode == OTG_HOST_MODE)
+ {
+ usbx->gusbcfg_bit.fdevmode = FALSE;
+ usbx->gusbcfg_bit.fhstmode = TRUE;
+ }
+
+ /* set otg to default mode */
+ if(mode == OTG_DRD_MODE)
+ {
+ usbx->gusbcfg_bit.fdevmode = FALSE;
+ usbx->gusbcfg_bit.fhstmode = FALSE;
+ }
+}
+
+
+/**
+ * @brief disable the transceiver power down mode
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @retval none
+ */
+void usb_global_power_on(otg_global_type *usbx)
+{
+ /* core soft reset */
+ usbx->grstctl_bit.csftrst = TRUE;
+ while(usbx->grstctl_bit.csftrst);
+
+ /* disable power down mode */
+ usbx->gccfg_bit.pwrdown = TRUE;
+
+}
+
+/**
+ * @brief usb stop phy clock
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @retval none
+ */
+void usb_stop_phy_clk(otg_global_type *usbx)
+{
+ OTG_PCGCCTL(usbx)->pcgcctl_bit.stoppclk = TRUE;
+}
+
+/**
+ * @brief usb open phy clock
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @retval none
+ */
+void usb_open_phy_clk(otg_global_type *usbx)
+{
+ OTG_PCGCCTL(usbx)->pcgcctl_bit.stoppclk = FALSE;
+}
+
+
+/**
+ * @brief write data from user memory to usb buffer
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @param pusr_buf: point to user buffer
+ * @param offset_addr: endpoint tx offset address
+ * @param nbytes: number of bytes data write to usb buffer
+ * @retval none
+ */
+void usb_write_packet(otg_global_type *usbx, uint8_t *pusr_buf, uint16_t num, uint16_t nbytes)
+{
+ uint32_t n_index;
+ uint32_t nhbytes = (nbytes + 3) / 4;
+ uint32_t *pbuf = (uint32_t *)pusr_buf;
+ for(n_index = 0; n_index < nhbytes; n_index ++)
+ {
+#if defined (__ICCARM__) && (__VER__ < 7000000)
+ USB_FIFO(usbx, num) = *(__packed uint32_t *)pbuf;
+#else
+ USB_FIFO(usbx, num) = __UNALIGNED_UINT32_READ(pbuf);
+#endif
+ pbuf ++;
+ }
+}
+
+/**
+ * @brief read data from usb buffer to user buffer
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @param pusr_buf: point to user buffer
+ * @param offset_addr: endpoint rx offset address
+ * @param nbytes: number of bytes data write to usb buffer
+ * @retval none
+ */
+void usb_read_packet(otg_global_type *usbx, uint8_t *pusr_buf, uint16_t num, uint16_t nbytes)
+{
+ uint32_t n_index;
+ uint32_t nhbytes = (nbytes + 3) / 4;
+ uint32_t *pbuf = (uint32_t *)pusr_buf;
+ UNUSED(num);
+ for(n_index = 0; n_index < nhbytes; n_index ++)
+ {
+#if defined (__ICCARM__) && (__VER__ < 7000000)
+ *(__packed uint32_t *)pbuf = USB_FIFO(usbx, 0);
+#else
+ __UNALIGNED_UINT32_WRITE(pbuf, (USB_FIFO(usbx, 0)));
+#endif
+ pbuf ++;
+ }
+}
+#endif
+
+
+#ifdef OTGFS_USB_DEVICE
+/**
+ * @brief open usb endpoint
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @param ept_info: endpoint information structure
+ * @retval none
+ */
+void usb_ept_open(otg_global_type *usbx, usb_ept_info *ept_info)
+{
+ uint8_t mps = USB_EPT0_MPS_64;
+ if(ept_info->eptn == USB_EPT0)
+ {
+ if(ept_info->maxpacket == 0x40)
+ {
+ mps = USB_EPT0_MPS_64;
+ }
+ else if(ept_info->maxpacket == 0x20)
+ {
+ mps = USB_EPT0_MPS_32;
+ }
+ else if(ept_info->maxpacket == 0x10)
+ {
+ mps = USB_EPT0_MPS_16;
+ }
+ else if(ept_info->maxpacket == 0x08)
+ {
+ mps = USB_EPT0_MPS_8;
+ }
+ }
+ if(ept_info->trans_type == EPT_ISO_TYPE)
+ {
+ OTG_DEVICE(usbx)->dctl |= 1 << 15;
+ }
+ /* endpoint direction is in */
+ if(ept_info->inout == EPT_DIR_IN)
+ {
+ OTG_DEVICE(usbx)->daintmsk |= 1 << ept_info->eptn;
+ if(ept_info->eptn == USB_EPT0)
+ {
+ USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.mps = mps;
+ }
+ else
+ {
+ USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.mps = ept_info->maxpacket;
+ }
+ USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.eptype = ept_info->trans_type;
+ USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.txfnum = ept_info->eptn;
+ USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.setd0pid = TRUE;
+ USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.usbacept = TRUE;
+ }
+ /* endpoint direction is out */
+ else
+ {
+ OTG_DEVICE(usbx)->daintmsk |= (1 << ept_info->eptn) << 16;
+ if(ept_info->eptn == USB_EPT0)
+ {
+ USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.mps = mps;
+ }
+ else
+ {
+ USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.mps = ept_info->maxpacket;
+ }
+ USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.eptype = ept_info->trans_type;
+ USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.setd0pid = TRUE;
+ USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.usbacept = TRUE;
+ }
+}
+
+/**
+ * @brief close usb endpoint
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @param ept_info: endpoint information structure
+ * @retval none
+ */
+void usb_ept_close(otg_global_type *usbx, usb_ept_info *ept_info)
+{
+ if(ept_info->inout == EPT_DIR_IN)
+ {
+ OTG_DEVICE(usbx)->daintmsk &= ~(1 << ept_info->eptn);
+ if(USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.eptena == SET)
+ {
+ USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.eptdis = TRUE;
+ USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.snak = TRUE;
+ }
+ USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.usbacept = FALSE;
+ }
+ else
+ {
+ OTG_DEVICE(usbx)->daintmsk &= ~((1 << ept_info->eptn) << 16);
+ if(USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.eptena == SET)
+ {
+ USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.eptdis = TRUE;
+ USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.snak = TRUE;
+ }
+
+ USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.usbacept = FALSE;
+ }
+}
+
+
+/**
+ * @brief set endpoint tx or rx status to stall
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @param ept_info: endpoint information structure
+ * @retval none
+ */
+void usb_ept_stall(otg_global_type *usbx, usb_ept_info *ept_info)
+{
+ if(ept_info->inout == EPT_DIR_IN)
+ {
+ if(USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.eptena == RESET)
+ {
+ USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.eptdis = FALSE;
+ }
+ USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.stall = SET;
+ }
+ else
+ {
+ if(USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.eptena == RESET)
+ {
+ USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.eptdis = FALSE;
+ }
+ USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.stall = TRUE;
+ }
+}
+
+/**
+ * @brief clear endpoint tx or rx status to stall
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @param ept_info: endpoint information structure
+ * @retval none
+ */
+void usb_ept_clear_stall(otg_global_type *usbx, usb_ept_info *ept_info)
+{
+ if(ept_info->inout == EPT_DIR_IN)
+ {
+ USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.stall = FALSE;
+ if(ept_info->trans_type == EPT_INT_TYPE || ept_info->trans_type == EPT_BULK_TYPE)
+ {
+ USB_INEPT(usbx, ept_info->eptn)->diepctl_bit.setd0pid = TRUE;
+ }
+ }
+ else
+ {
+ USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.stall = FALSE;
+ if(ept_info->trans_type == EPT_INT_TYPE || ept_info->trans_type == EPT_BULK_TYPE)
+ {
+ USB_OUTEPT(usbx, ept_info->eptn)->doepctl_bit.setd0pid = TRUE;
+ }
+ }
+}
+
+/**
+ * @brief get all out endpoint interrupt bits
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @retval out endpoint interrupt bits
+ */
+uint32_t usb_get_all_out_interrupt(otg_global_type *usbx)
+{
+ uint32_t intsts = OTG_DEVICE(usbx)->daint;
+ return ((intsts & (OTG_DEVICE(usbx)->daintmsk)) >> 16);
+}
+
+/**
+ * @brief get all in endpoint interrupt bits
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @retval in endpoint interrupt bits
+ */
+uint32_t usb_get_all_in_interrupt(otg_global_type *usbx)
+{
+ uint32_t intsts = OTG_DEVICE(usbx)->daint;
+ return ((intsts & (OTG_DEVICE(usbx)->daintmsk)) & 0xFFFF);
+}
+
+
+/**
+ * @brief get out endpoint interrupt flag
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @param eptn: endpoint number
+ * @retval out endpoint interrupt flags
+ */
+uint32_t usb_ept_out_interrupt(otg_global_type *usbx, uint32_t eptn)
+{
+ uint32_t intsts = USB_OUTEPT(usbx, eptn)->doepint;
+ return (intsts & (OTG_DEVICE(usbx)->doepmsk));
+}
+
+/**
+ * @brief get in endpoint interrupt flag
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @param eptn: endpoint number
+ * @retval in endpoint intterupt flags
+ */
+uint32_t usb_ept_in_interrupt(otg_global_type *usbx, uint32_t eptn)
+{
+ uint32_t intsts, mask1, mask2;
+ mask1 = OTG_DEVICE(usbx)->diepmsk;
+ mask2 = OTG_DEVICE(usbx)->diepempmsk;
+ mask1 |= ((mask2 >> eptn) & 0x1) << 7;
+ intsts = USB_INEPT(usbx, eptn)->diepint & mask1;
+ return intsts;
+}
+
+/**
+ * @brief clear out endpoint interrupt flag
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @param eptn: endpoint number
+ * @retval flag: interrupt flag
+ * this parameter can be any combination of the following values:
+ * - USB_OTG_DOEPINT_XFERC_FLAG
+ * - USB_OTG_DOEPINT_EPTDISD_FLAG
+ * - USB_OTG_DOEPINT_SETUP_FLAG
+ * - USB_OTG_DOEPINT_OTEPDIS_FLAG
+ * - USB_OTG_DOEPINT_B2BSTUP_FLAG
+ */
+void usb_ept_out_clear(otg_global_type *usbx, uint32_t eptn, uint32_t flag)
+{
+ USB_OUTEPT(usbx, eptn)->doepint = flag;
+}
+
+/**
+ * @brief clear in endpoint interrupt flag
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @param eptn: endpoint number
+ * @retval flag: interrupt flag
+ * this parameter can be any combination of the following values:
+ * - USB_OTG_DIEPINT_XFERC_FLAG
+ * - USB_OTG_DIEPINT_EPTDISD_FLAG
+ * - USB_OTG_DIEPINT_TMROC_FLAG
+ * - USB_OTG_DIEPINT_INTTXFE_FLAG
+ * - USB_OTG_DIEPINT_INEPNE_FLAG
+ * - USB_OTG_DIEPINT_TXFE_FLAG
+ */
+void usb_ept_in_clear(otg_global_type *usbx, uint32_t eptn, uint32_t flag)
+{
+ USB_INEPT(usbx, eptn)->diepint = flag;
+}
+
+
+/**
+ * @brief set the host assignment address
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @param address: host assignment address
+ * @retval none
+ */
+void usb_set_address(otg_global_type *usbx, uint8_t address)
+{
+ OTG_DEVICE(usbx)->dcfg_bit.devaddr = address;
+}
+
+/**
+ * @brief enable endpoint 0 out
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @retval none
+ */
+void usb_ept0_start(otg_global_type *usbx)
+{
+ otg_eptout_type *usb_outept = USB_OUTEPT(usbx, 0);
+ usb_outept->doeptsiz = 0;
+ usb_outept->doeptsiz_bit.pktcnt = 1;
+ usb_outept->doeptsiz_bit.xfersize = 24;
+ usb_outept->doeptsiz_bit.rxdpid_setupcnt = 3;
+}
+
+
+/**
+ * @brief endpoint 0 start setup
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @retval none
+ */
+void usb_ept0_setup(otg_global_type *usbx)
+{
+ USB_INEPT(usbx, 0)->diepctl_bit.mps = 0;
+ OTG_DEVICE(usbx)->dctl_bit.cgnpinak = FALSE;
+}
+
+/**
+ * @brief connect usb device by enable pull-up
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @retval none
+ */
+void usb_connect(otg_global_type *usbx)
+{
+ /* D+ 1.5k pull-up enable */
+ OTG_DEVICE(usbx)->dctl_bit.sftdiscon = FALSE;
+}
+
+/**
+ * @brief disconnect usb device by disable pull-up
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @retval none
+ */
+void usb_disconnect(otg_global_type *usbx)
+{
+ /* D+ 1.5k pull-up disable */
+ OTG_DEVICE(usbx)->dctl_bit.sftdiscon = TRUE;
+}
+
+
+/**
+ * @brief usb remote wakeup set
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @retval none
+ */
+void usb_remote_wkup_set(otg_global_type *usbx)
+{
+ OTG_DEVICE(usbx)->dctl_bit.rwkupsig = TRUE;
+}
+
+/**
+ * @brief usb remote wakeup clear
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @retval none
+ */
+void usb_remote_wkup_clear(otg_global_type *usbx)
+{
+ OTG_DEVICE(usbx)->dctl_bit.rwkupsig = FALSE;
+}
+
+/**
+ * @brief usb suspend status get
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @retval usb suspend status
+ */
+uint8_t usb_suspend_status_get(otg_global_type *usbx)
+{
+ return OTG_DEVICE(usbx)->dsts_bit.suspsts;
+}
+#endif
+
+#ifdef OTGFS_USB_HOST
+/**
+ * @brief usb port power on
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @param state: state (TRUE or FALSE)
+ * @retval none
+ */
+void usb_port_power_on(otg_global_type *usbx, confirm_state state)
+{
+ otg_host_type *usb_host = OTG_HOST(usbx);
+ uint32_t hprt_val = usb_host->hprt;
+
+ hprt_val &= ~(USB_OTG_HPRT_PRTENA | USB_OTG_HPRT_PRTENCHNG |
+ USB_OTG_HPRT_PRTOVRCACT | USB_OTG_HPRT_PRTCONDET);
+
+ if(state == TRUE)
+ {
+ usb_host->hprt = hprt_val | USB_OTG_HPRT_PRTPWR;
+ }
+ else
+ {
+ usb_host->hprt = hprt_val & (~USB_OTG_HPRT_PRTPWR);
+ }
+}
+
+/**
+ * @brief get current frame number
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @retval none
+ */
+uint32_t usbh_get_frame(otg_global_type *usbx)
+{
+ otg_host_type *usb_host = OTG_HOST(usbx);
+ return usb_host->hfnum & 0xFFFF;
+}
+
+/**
+ * @brief enable one host channel
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @param chn: host channel number
+ * @param ept_num: devvice endpoint number
+ * @param dev_address: device address
+ * @param type: channel transfer type
+ * this parameter can be one of the following values:
+ * - EPT_CONTROL_TYPE
+ * - EPT_BULK_TYPE
+ * - EPT_INT_TYPE
+ * - EPT_ISO_TYPE
+ * @param maxpacket: support max packe size for this channel
+ * @param speed: device speed
+ * this parameter can be one of the following values:
+ * - USB_PRTSPD_FULL_SPEED
+ * - USB_PRTSPD_LOW_SPEED
+ * @retval none
+ */
+void usb_hc_enable(otg_global_type *usbx,
+ uint8_t chn,
+ uint8_t ept_num,
+ uint8_t dev_address,
+ uint8_t type,
+ uint16_t maxpacket,
+ uint8_t speed)
+{
+ otg_hchannel_type *hch = USB_CHL(usbx, chn);
+ otg_host_type *usb_host = OTG_HOST(usbx);
+
+ /* clear old interrupt flag */
+ hch->hcint = 0xFFFFFFFF;
+
+ switch(type)
+ {
+ case EPT_CONTROL_TYPE:
+ case EPT_BULK_TYPE:
+ hch->hcintmsk |= USB_OTG_HC_XFERCM_INT | USB_OTG_HC_STALLM_INT |
+ USB_OTG_HC_XACTERRM_INT | USB_OTG_HC_NAKM_INT |
+ USB_OTG_HC_DTGLERRM_INT;
+ if(ept_num & 0x80)
+ {
+ hch->hcintmsk_bit.bblerrmsk = TRUE;
+ }
+ break;
+ case EPT_INT_TYPE:
+ hch->hcintmsk |= USB_OTG_HC_XFERCM_INT | USB_OTG_HC_STALLM_INT |
+ USB_OTG_HC_XACTERRM_INT | USB_OTG_HC_NAKM_INT |
+ USB_OTG_HC_DTGLERRM_INT | USB_OTG_HC_FRMOVRRUN_INT;
+ break;
+ case EPT_ISO_TYPE:
+
+ hch->hcintmsk |= USB_OTG_HC_XFERCM_INT | USB_OTG_HC_ACKM_INT |
+ USB_OTG_HC_FRMOVRRUN_INT;
+ break;
+ }
+ usb_host->haintmsk |= 1 << chn;
+ usbx->gintmsk_bit.hchintmsk = TRUE;
+
+ hch->hcchar_bit.devaddr = dev_address;
+ hch->hcchar_bit.eptnum = ept_num & 0x7F;
+ hch->hcchar_bit.eptdir = (ept_num & 0x80)?1:0;
+ hch->hcchar_bit.lspddev = (speed == USB_PRTSPD_LOW_SPEED)?1:0;
+ hch->hcchar_bit.eptype = type;
+ hch->hcchar_bit.mps = maxpacket;
+
+ if(type == EPT_INT_TYPE)
+ {
+ hch->hcchar_bit.oddfrm = TRUE;
+ }
+}
+
+/**
+ * @brief host read channel interrupt
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @retval interrupt flag
+ */
+uint32_t usb_hch_read_interrupt(otg_global_type *usbx)
+{
+ otg_host_type *usb_host = OTG_HOST(usbx);
+ return usb_host->haint & 0xFFFF;
+}
+
+/**
+ * @brief disable host
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @retval none
+ */
+void usb_host_disable(otg_global_type *usbx)
+{
+ uint32_t i_index = 0;
+ otg_hchannel_type *hch;
+ otg_host_type *usb_host = OTG_HOST(usbx);
+
+ usbx->gahbcfg_bit.glbintmsk = FALSE;
+ usb_flush_rx_fifo(usbx);
+ usb_flush_tx_fifo(usbx, 0x10);
+
+ for(i_index = 0; i_index < 16; i_index ++)
+ {
+ hch = USB_CHL(usbx, i_index);
+ if(hch->hcchar_bit.chena == TRUE)
+ {
+ hch->hcchar_bit.chdis = TRUE;
+ }
+ }
+ usb_host->haint = 0xFFFFFFFF;
+ usbx->gintsts = 0xFFFFFFFF;
+ usbx->gahbcfg_bit.glbintmsk = TRUE;
+}
+
+/**
+ * @brief halt channel
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @param chn: channel number
+ * @retval none
+ */
+void usb_hch_halt(otg_global_type *usbx, uint8_t chn)
+{
+ uint32_t count = 0;
+ otg_hchannel_type *usb_chh = USB_CHL(usbx, chn);
+ otg_host_type *usb_host = OTG_HOST(usbx);
+
+ /* endpoint type is control or bulk */
+ if(usb_chh->hcchar_bit.eptype == EPT_CONTROL_TYPE ||
+ usb_chh->hcchar_bit.eptype == EPT_BULK_TYPE)
+ {
+ usb_chh->hcchar_bit.chdis = TRUE;
+ if((usbx->gnptxsts_bit.nptxqspcavail) == 0)
+ {
+ usb_chh->hcchar_bit.chena = FALSE;
+ if(usb_chh->hcchar_bit.chena != TRUE)
+ usb_chh->hcchar_bit.chena = TRUE;
+ do
+ {
+ if(count ++ > 1000)
+ break;
+ }while(usb_chh->hcchar_bit.chena == SET);
+ }
+ else
+ {
+ if(usb_chh->hcchar_bit.chena != TRUE)
+ usb_chh->hcchar_bit.chena = TRUE;
+ }
+ }
+ else
+ {
+ usb_chh->hcchar_bit.chdis = TRUE;
+ if((usb_host->hptxsts_bit.ptxqspcavil) == 0)
+ {
+ usb_chh->hcchar_bit.chena = FALSE;
+ if(usb_chh->hcchar_bit.chena != TRUE)
+ usb_chh->hcchar_bit.chena = TRUE;
+ do
+ {
+ if(count ++ > 1000)
+ break;
+ }while(usb_chh->hcchar_bit.chena == SET);
+ }
+ else
+ {
+ if(usb_chh->hcchar_bit.chena != TRUE)
+ usb_chh->hcchar_bit.chena = TRUE;
+ }
+ }
+}
+/**
+ * @brief select full or low speed clock
+ * @param usbx: to select the otgfs peripheral.
+ * this parameter can be one of the following values:
+ * - OTG1_GLOBAL
+ * @param clk: clock frequency
+ * @retval none
+ */
+void usbh_fsls_clksel(otg_global_type *usbx, uint8_t clk)
+{
+ otg_host_type *usb_host = OTG_HOST(usbx);
+
+ usb_host->hcfg_bit.fslspclksel = clk;
+ if(clk == USB_HCFG_CLK_6M)
+ {
+ usb_host->hfir = 6000;
+ }
+ else
+ {
+ usb_host->hfir = 48000;
+ }
+}
+#endif
+
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_wdt.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_wdt.c
new file mode 100644
index 00000000000..c7af91cf8f6
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_wdt.c
@@ -0,0 +1,154 @@
+/**
+ **************************************************************************
+ * @file at32f45x_wdt.c
+ * @brief contains all the functions for the wdt firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup WDT
+ * @brief WDT driver modules
+ * @{
+ */
+
+#ifdef WDT_MODULE_ENABLED
+
+/** @defgroup WDT_private_functions
+ * @{
+ */
+
+/**
+ * @brief wdt enable ,the reload value will be sent to the counter
+ * @param none
+ * @retval none
+ */
+void wdt_enable(void)
+{
+ WDT->cmd = WDT_CMD_ENABLE;
+}
+
+/**
+ * @brief reload wdt counter
+ * @param none
+ * @retval none
+ */
+void wdt_counter_reload(void)
+{
+ WDT->cmd = WDT_CMD_RELOAD;
+}
+
+/**
+ * @brief set wdt counter reload value
+ * @param reload_value (0x0000~0x0FFF)
+ * @retval none
+ */
+void wdt_reload_value_set(uint16_t reload_value)
+{
+ WDT->rld = reload_value;
+}
+
+/**
+ * @brief set wdt division divider
+ * @param division
+ * this parameter can be one of the following values:
+ * - WDT_CLK_DIV_4
+ * - WDT_CLK_DIV_8
+ * - WDT_CLK_DIV_16
+ * - WDT_CLK_DIV_32
+ * - WDT_CLK_DIV_64
+ * - WDT_CLK_DIV_128
+ * - WDT_CLK_DIV_256
+ * @retval none
+ */
+void wdt_divider_set(wdt_division_type division)
+{
+ WDT->div_bit.div = division;
+}
+
+/**
+ * @brief enable or disable wdt cmd register write
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void wdt_register_write_enable( confirm_state new_state)
+{
+ if(new_state == FALSE)
+ {
+ WDT->cmd = WDT_CMD_LOCK;
+ }
+ else
+ {
+ WDT->cmd = WDT_CMD_UNLOCK;
+ }
+}
+
+/**
+ * @brief get wdt flag
+ * @param wdt_flag
+ * this parameter can be one of the following values:
+ * - WDT_DIVF_UPDATE_FLAG: division value update complete flag.
+ * - WDT_RLDF_UPDATE_FLAG: reload value update complete flag.
+ * - WDT_WINF_UPDATE_FLAG: window value update complete flag.
+ * @retval state of wdt flag
+ */
+flag_status wdt_flag_get(uint16_t wdt_flag)
+{
+ flag_status status = RESET;
+
+ if ((WDT->sts & wdt_flag) != (uint16_t)RESET)
+ {
+ status = SET;
+ }
+ else
+ {
+ status = RESET;
+ }
+
+ return status;
+}
+
+/**
+ * @brief wdt window counter value set
+ * @param window_cnt (0x0000~0x0FFF)
+ * @retval none
+ */
+void wdt_window_counter_set(uint16_t window_cnt)
+{
+ WDT->win_bit.win = window_cnt;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_wwdt.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_wwdt.c
new file mode 100644
index 00000000000..054f21d1860
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_wwdt.c
@@ -0,0 +1,149 @@
+/**
+ **************************************************************************
+ * @file at32f45x_wwdt.c
+ * @brief contains all the functions for the wwdt firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup WWDT
+ * @brief WWDT driver modules
+ * @{
+ */
+
+#ifdef WWDT_MODULE_ENABLED
+
+/** @defgroup WWDT_private_functions
+ * @{
+ */
+
+/**
+ * @brief wwdt reset by crm reset register
+ * @retval none
+ */
+void wwdt_reset(void)
+{
+ crm_periph_reset(CRM_WWDT_PERIPH_RESET, TRUE);
+ crm_periph_reset(CRM_WWDT_PERIPH_RESET, FALSE);
+}
+
+/**
+ * @brief wwdt division set
+ * @param division
+ * this parameter can be one of the following values:
+ * - WWDT_PCLK1_DIV_4096 (wwdt counter clock = (pclk1/4096)/1)
+ * - WWDT_PCLK1_DIV_8192 (wwdt counter clock = (pclk1/4096)/2)
+ * - WWDT_PCLK1_DIV_16384 (wwdt counter clock = (pclk1/4096)/4)
+ * - WWDT_PCLK1_DIV_32768 (wwdt counter clock = (pclk1/4096)/8)
+ * @retval none
+ */
+void wwdt_divider_set(wwdt_division_type division)
+{
+ WWDT->cfg_bit.div = division;
+}
+
+/**
+ * @brief wwdt reload counter interrupt flag clear
+ * @param none
+ * @retval none
+ */
+void wwdt_flag_clear(void)
+{
+ WWDT->sts = 0;
+}
+
+/**
+ * @brief wwdt enable and the counter value load
+ * @param wwdt_cnt (0x40~0x7f)
+ * @retval none
+ */
+void wwdt_enable(uint8_t wwdt_cnt)
+{
+ WWDT->ctrl = wwdt_cnt | WWDT_EN_BIT;
+}
+
+/**
+ * @brief wwdt reload counter interrupt enable
+ * @param none
+ * @retval none
+ */
+void wwdt_interrupt_enable(void)
+{
+ WWDT->cfg_bit.rldien = TRUE;
+}
+
+/**
+ * @brief wwdt reload counter interrupt flag get
+ * @param none
+ * @retval state of reload counter interrupt flag
+ */
+flag_status wwdt_flag_get(void)
+{
+ return (flag_status)WWDT->sts_bit.rldf;
+}
+
+/**
+ * @brief wwdt reload counter interrupt flag get
+ * @param none
+ * @retval state of reload counter interrupt flag
+ */
+flag_status wwdt_interrupt_flag_get(void)
+{
+ return (flag_status)(WWDT->sts_bit.rldf && WWDT->cfg_bit.rldien);
+}
+
+/**
+ * @brief wwdt counter value set
+ * @param wwdt_cnt (0x40~0x7f)
+ * @retval none
+ */
+void wwdt_counter_set(uint8_t wwdt_cnt)
+{
+ WWDT->ctrl_bit.cnt = wwdt_cnt;
+}
+
+/**
+ * @brief wwdt window counter value set
+ * @param window_cnt (0x40~0x7f)
+ * @retval none
+ */
+void wwdt_window_counter_set(uint8_t window_cnt)
+{
+ WWDT->cfg_bit.win = window_cnt;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_xmc.c b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_xmc.c
new file mode 100644
index 00000000000..87bb02b4200
--- /dev/null
+++ b/bsp/at32/libraries/AT32F45x_Firmware_Library/drivers/src/at32f45x_xmc.c
@@ -0,0 +1,494 @@
+/**
+ **************************************************************************
+ * @file at32f45x_xmc.c
+ * @brief contains all the functions for the xmc firmware library
+ **************************************************************************
+ * Copyright notice & Disclaimer
+ *
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
+ * software is governed by this copyright notice and the following disclaimer.
+ *
+ * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
+ * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
+ * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
+ * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
+ * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
+ *
+ **************************************************************************
+ */
+
+#include "at32f45x_conf.h"
+
+/** @addtogroup AT32F45x_periph_driver
+ * @{
+ */
+
+/** @defgroup XMC
+ * @brief XMC driver modules
+ * @{
+ */
+
+#ifdef XMC_MODULE_ENABLED
+
+/** @defgroup XMC_private_functions
+ * @{
+ */
+
+/**
+ * @brief xmc nor or sram registers reset
+ * @param xmc_subbank
+ * this parameter can be one of the following values:
+ * - XMC_BANK1_NOR_SRAM1
+ * - XMC_BANK1_NOR_SRAM2
+ * - XMC_BANK1_NOR_SRAM3
+ * - XMC_BANK1_NOR_SRAM4
+ * @retval none
+ */
+void xmc_nor_sram_reset(xmc_nor_sram_subbank_type xmc_subbank)
+{
+ /* XMC_BANK1_NORSRAM1 */
+ if(xmc_subbank == XMC_BANK1_NOR_SRAM1)
+ {
+ XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl = 0x000030DB;
+ }
+ /* XMC_BANK1_NORSRAM2, XMC_BANK1_NORSRAM3 or XMC_BANK1_NORSRAM4 */
+ else
+ {
+ XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl = 0x000030D2;
+ }
+ XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1tmg = 0x0FFFFFFF;
+ XMC_BANK1->tmgwr_group[xmc_subbank].bk1tmgwr = 0x0FFFFFFF;
+}
+
+/**
+ * @brief initialize the xmc nor/sram banks according to the specified
+ * parameters in the xmc_norsraminitstruct.
+ * @param xmc_norsram_init_struct : pointer to a xmc_norsram_init_type
+ * structure that contains the configuration information for
+ * the xmc nor/sram specified banks.
+ * @retval none
+ */
+void xmc_nor_sram_init(xmc_norsram_init_type* xmc_norsram_init_struct)
+{
+ /* bank1 nor/sram control register configuration */
+ XMC_BANK1->ctrl_tmg_group[xmc_norsram_init_struct->subbank].bk1ctrl =
+ (uint32_t)xmc_norsram_init_struct->data_addr_multiplex |
+ xmc_norsram_init_struct->device |
+ xmc_norsram_init_struct->bus_type |
+ xmc_norsram_init_struct->burst_mode_enable |
+ xmc_norsram_init_struct->asynwait_enable |
+ xmc_norsram_init_struct->wait_signal_lv |
+ xmc_norsram_init_struct->wrapped_mode_enable |
+ xmc_norsram_init_struct->wait_signal_config |
+ xmc_norsram_init_struct->write_enable |
+ xmc_norsram_init_struct->wait_signal_enable |
+ xmc_norsram_init_struct->write_timing_enable |
+ xmc_norsram_init_struct->write_burst_syn;
+
+ /* if nor flash device */
+ if(xmc_norsram_init_struct->device == XMC_DEVICE_NOR)
+ {
+ XMC_BANK1->ctrl_tmg_group[xmc_norsram_init_struct->subbank].bk1ctrl_bit.noren = 0x1;
+ }
+}
+
+/**
+ * @brief initialize the xmc nor/sram banks according to the specified
+ * parameters in the xmc_rw_timing_struct and xmc_w_timing_struct.
+ * @param xmc_rw_timing_struct : pointer to a xmc_norsram_timing_init_type
+ * structure that contains the configuration information for
+ * the xmc nor/sram specified banks.
+ * @param xmc_w_timing_struct : pointer to a xmc_norsram_timing_init_type
+ * structure that contains the configuration information for
+ * the xmc nor/sram specified banks.
+ * @retval none
+ */
+void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
+ xmc_norsram_timing_init_type* xmc_w_timing_struct)
+{
+ /* bank1 nor/sram timing register configuration */
+ XMC_BANK1->ctrl_tmg_group[xmc_rw_timing_struct->subbank].bk1tmg =
+ (uint32_t)xmc_rw_timing_struct->addr_setup_time |
+ (xmc_rw_timing_struct->addr_hold_time << 4) |
+ (xmc_rw_timing_struct->data_setup_time << 8) |
+ (xmc_rw_timing_struct->bus_latency_time <<16) |
+ (xmc_rw_timing_struct->clk_psc << 20) |
+ (xmc_rw_timing_struct->data_latency_time << 24) |
+ xmc_rw_timing_struct->mode;
+
+ /* bank1 nor/sram timing register for write configuration, if extended mode is used */
+ if(xmc_rw_timing_struct->write_timing_enable == XMC_WRITE_TIMING_ENABLE)
+ {
+ XMC_BANK1->tmgwr_group[xmc_w_timing_struct->subbank].bk1tmgwr =
+ (uint32_t)xmc_w_timing_struct->addr_setup_time |
+ (xmc_w_timing_struct->addr_hold_time << 4) |
+ (xmc_w_timing_struct->data_setup_time << 8) |
+ (xmc_w_timing_struct->bus_latency_time << 16) |
+ (xmc_w_timing_struct->clk_psc << 20) |
+ (xmc_w_timing_struct->data_latency_time << 24) |
+ xmc_w_timing_struct->mode;
+ }
+ else
+ {
+ XMC_BANK1->tmgwr_group[xmc_w_timing_struct->subbank].bk1tmgwr = 0x0FFFFFFF;
+ }
+}
+
+/**
+ * @brief fill each xmc_nor_sram_init_struct member with its default value.
+ * @param xmc_nor_sram_init_struct: pointer to a xmc_norsram_init_type
+ * structure which will be initialized.
+ * @retval none
+ */
+void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_struct)
+{
+ /* reset nor/sram init structure parameters values */
+ xmc_nor_sram_init_struct->subbank = XMC_BANK1_NOR_SRAM1;
+ xmc_nor_sram_init_struct->data_addr_multiplex = XMC_DATA_ADDR_MUX_ENABLE;
+ xmc_nor_sram_init_struct->device = XMC_DEVICE_SRAM;
+ xmc_nor_sram_init_struct->bus_type = XMC_BUSTYPE_8_BITS;
+ xmc_nor_sram_init_struct->burst_mode_enable = XMC_BURST_MODE_DISABLE;
+ xmc_nor_sram_init_struct->asynwait_enable = XMC_ASYN_WAIT_DISABLE;
+ xmc_nor_sram_init_struct->wait_signal_lv = XMC_WAIT_SIGNAL_LEVEL_LOW;
+ xmc_nor_sram_init_struct->wrapped_mode_enable = XMC_WRAPPED_MODE_DISABLE;
+ xmc_nor_sram_init_struct->wait_signal_config = XMC_WAIT_SIGNAL_SYN_BEFORE;
+ xmc_nor_sram_init_struct->write_enable = XMC_WRITE_OPERATION_ENABLE;
+ xmc_nor_sram_init_struct->wait_signal_enable = XMC_WAIT_SIGNAL_ENABLE;
+ xmc_nor_sram_init_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
+ xmc_nor_sram_init_struct->write_burst_syn = XMC_WRITE_BURST_SYN_DISABLE;
+}
+
+/**
+ * @brief fill each xmc_rw_timing_struct and xmc_w_timing_struct member with its default value.
+ * @param xmc_rw_timing_struct: pointer to a xmc_norsram_timing_init_type
+ * structure which will be initialized.
+ * @param xmc_w_timing_struct: pointer to a xmc_norsram_timing_init_type
+ * structure which will be initialized.
+ * @retval none
+ */
+void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
+ xmc_norsram_timing_init_type* xmc_w_timing_struct)
+{
+ xmc_rw_timing_struct->subbank = XMC_BANK1_NOR_SRAM1;
+ xmc_rw_timing_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
+ xmc_rw_timing_struct->addr_setup_time = 0xF;
+ xmc_rw_timing_struct->addr_hold_time = 0xF;
+ xmc_rw_timing_struct->data_setup_time = 0xFF;
+ xmc_rw_timing_struct->bus_latency_time = 0xF;
+ xmc_rw_timing_struct->clk_psc = 0xF;
+ xmc_rw_timing_struct->data_latency_time = 0xF;
+ xmc_rw_timing_struct->mode = XMC_ACCESS_MODE_A;
+ xmc_w_timing_struct->subbank = XMC_BANK1_NOR_SRAM1;
+ xmc_w_timing_struct->write_timing_enable = XMC_WRITE_TIMING_DISABLE;
+ xmc_w_timing_struct->addr_setup_time = 0xF;
+ xmc_w_timing_struct->addr_hold_time = 0xF;
+ xmc_w_timing_struct->data_setup_time = 0xFF;
+ xmc_w_timing_struct->bus_latency_time = 0xF;
+ xmc_w_timing_struct->clk_psc = 0xF;
+ xmc_w_timing_struct->data_latency_time = 0xF;
+ xmc_w_timing_struct->mode = XMC_ACCESS_MODE_A;
+}
+
+/**
+ * @brief enable or disable the specified nor/sram memory bank.
+ * @param xmc_subbank
+ * this parameter can be one of the following values:
+ * - XMC_BANK1_NOR_SRAM1
+ * - XMC_BANK1_NOR_SRAM2
+ * - XMC_BANK1_NOR_SRAM3
+ * - XMC_BANK1_NOR_SRAM4
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state)
+{
+ XMC_BANK1->ctrl_tmg_group[xmc_subbank].bk1ctrl_bit.en = new_state;
+}
+
+/**
+ * @brief config the bus turnaround phase.
+ * @param xmc_sub_bank
+ * this parameter can be one of the following values:
+ * - XMC_BANK1_NOR_SRAM1
+ * - XMC_BANK1_NOR_SRAM2
+ * - XMC_BANK1_NOR_SRAM3
+ * - XMC_BANK1_NOR_SRAM4
+ * @param w2w_timing :write timing
+ * @param r2r_timing :read timing
+ * @retval none
+ */
+void xmc_ext_timing_config(volatile xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing)
+{
+ XMC_BANK1->ext_bit[xmc_sub_bank].buslatr2r = r2r_timing;
+ XMC_BANK1->ext_bit[xmc_sub_bank].buslatw2w = w2w_timing;
+}
+
+/**
+ * @brief xmc sdram registers reset
+ * @param xmc_bank
+ * this parameter can be one of the following values:
+ * - XMC_SDRAM_BANK1
+ * - XMC_SDRAM_BANK2
+ * @retval none
+ */
+void xmc_sdram_reset(xmc_sdram_bank_type xmc_bank)
+{
+ XMC_SDRAM->ctrl[xmc_bank] = 0x000002D0;
+ XMC_SDRAM->tm[xmc_bank] = 0x0FFFFFFF;
+ XMC_SDRAM->cmd = 0x00000000;
+ XMC_SDRAM->rcnt = 0x00000000;
+ XMC_SDRAM->sts = 0x00000000;
+}
+
+/**
+ * @brief initialize the xmc sdram banks according to the specified
+ * parameters in the xmc_sdram_init_struct and xmc_sdram_timing_struct.
+ * @param xmc_sdram_init_struct : pointer to a xmc_sdram_init_type
+ * structure that contains the configuration information for the xmc
+ * sdram specified banks.
+ * @param xmc_sdram_timing_struct : pointer to a xmc_sdram_timing_type
+ * structure that contains the configuration information for the xmc
+ * sdram specified banks.
+ * @retval none
+ */
+void xmc_sdram_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing_type *xmc_sdram_timing_struct)
+{
+ if(xmc_sdram_init_struct->sdram_bank == XMC_SDRAM_BANK1)
+ {
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].ca = xmc_sdram_init_struct->column_address;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].ra = xmc_sdram_init_struct->row_address;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].db = xmc_sdram_init_struct->width;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].inbk = xmc_sdram_init_struct->internel_banks;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].cas = xmc_sdram_init_struct->cas;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].wrp = xmc_sdram_init_struct->write_protection;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].bstr = xmc_sdram_init_struct->burst_read;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].rd = xmc_sdram_init_struct->read_delay;
+ if(xmc_sdram_init_struct->clkdiv == XMC_CLKDIV_1)
+ {
+ XMC_SDRAM->clkdiv1 = XMC_CLKDIV_1;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].clkdiv = 0;
+ }else
+ {
+ XMC_SDRAM->clkdiv1 &= ~XMC_CLKDIV_1;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].clkdiv = xmc_sdram_init_struct->clkdiv;
+ }
+
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].tmrd = xmc_sdram_timing_struct->tmrd;
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].txsr = xmc_sdram_timing_struct->txsr;
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].tras = xmc_sdram_timing_struct->tras;
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trc = xmc_sdram_timing_struct->trc;
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].twr = xmc_sdram_timing_struct->twr;
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trp = xmc_sdram_timing_struct->trp;
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trcd = xmc_sdram_timing_struct->trcd;
+ }
+
+ if(xmc_sdram_init_struct->sdram_bank == XMC_SDRAM_BANK2)
+ {
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].ca = xmc_sdram_init_struct->column_address;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].ra = xmc_sdram_init_struct->row_address;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].db = xmc_sdram_init_struct->width;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].inbk = xmc_sdram_init_struct->internel_banks;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].cas = xmc_sdram_init_struct->cas;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK2].wrp = xmc_sdram_init_struct->write_protection;
+ /* sdctrl2 bstr is not care */
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].bstr = xmc_sdram_init_struct->burst_read;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].rd = xmc_sdram_init_struct->read_delay;
+ /* sdctrl2 clkdiv is not care */
+ if(xmc_sdram_init_struct->clkdiv == XMC_CLKDIV_1)
+ {
+ XMC_SDRAM->clkdiv1 = XMC_CLKDIV_1;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].clkdiv = 0;
+ }else
+ {
+ XMC_SDRAM->clkdiv1 &= ~XMC_CLKDIV_1;
+ XMC_SDRAM->ctrl_bit[XMC_SDRAM_BANK1].clkdiv = xmc_sdram_init_struct->clkdiv;
+ }
+
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].tmrd = xmc_sdram_timing_struct->tmrd;
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].txsr = xmc_sdram_timing_struct->txsr;
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].tras = xmc_sdram_timing_struct->tras;
+ /* sdtm2 trc is not care */
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trc = xmc_sdram_timing_struct->trc;
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].twr = xmc_sdram_timing_struct->twr;
+ /* sdtm2 trp is not care */
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK1].trp = xmc_sdram_timing_struct->trp;
+ XMC_SDRAM->tm_bit[XMC_SDRAM_BANK2].trcd = xmc_sdram_timing_struct->trcd;
+ }
+}
+
+/**
+ * @brief fill each xmc_sdram_init_struct member with its default value.
+ * @param xmc_sdram_init_struct: pointer to a xmc_sdram_init_type
+ * structure which will be initialized.
+ * @param xmc_sdram_timing_struct: pointer to a xmc_sdram_timing_type
+ * structure which will be initialized.
+ * @retval none
+ */
+void xmc_sdram_default_para_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing_type *xmc_sdram_timing_struct)
+{
+ /* reset sdram init structure parameters values */
+ xmc_sdram_init_struct->sdram_bank = XMC_SDRAM_BANK1;
+ xmc_sdram_init_struct->internel_banks = XMC_INBK_4;
+ xmc_sdram_init_struct->clkdiv = XMC_NO_CLK;
+ xmc_sdram_init_struct->write_protection = FALSE;
+ xmc_sdram_init_struct->burst_read = FALSE;
+ xmc_sdram_init_struct->column_address = XMC_COLUMN_8;
+ xmc_sdram_init_struct->row_address = XMC_ROW_11;
+ xmc_sdram_init_struct->cas = XMC_CAS_1;
+ xmc_sdram_init_struct->width = XMC_MEM_WIDTH_8;
+ xmc_sdram_init_struct->read_delay = XMC_READ_DELAY_1;
+
+ xmc_sdram_timing_struct->tmrd = XMC_DELAY_CYCLE_16;
+ xmc_sdram_timing_struct->txsr = XMC_DELAY_CYCLE_16;
+ xmc_sdram_timing_struct->tras = XMC_DELAY_CYCLE_16;
+ xmc_sdram_timing_struct->trc = XMC_DELAY_CYCLE_16;
+ xmc_sdram_timing_struct->twr = XMC_DELAY_CYCLE_16;
+ xmc_sdram_timing_struct->trp = XMC_DELAY_CYCLE_16;
+ xmc_sdram_timing_struct->trcd = XMC_DELAY_CYCLE_16;
+}
+
+/**
+ * @brief sdram command confg
+ * @param xmc_sdram_cmd_struct: pointer to a xmc_sdram_cmd_type
+ * structure which will be initialized.
+ * @retval none
+ */
+void xmc_sdram_cmd(xmc_sdram_cmd_type *xmc_sdram_cmd_struct)
+{
+ XMC_SDRAM->cmd = (xmc_sdram_cmd_struct->auto_refresh << 5) |
+ (xmc_sdram_cmd_struct->data << 9) |
+ xmc_sdram_cmd_struct->cmd |
+ xmc_sdram_cmd_struct->cmd_banks;
+}
+
+
+/**
+ * @brief get sdram bank status
+ * @param xmc_bank: specifies the xmc bank to be used
+ * this parameter can be one of the following values:
+ * - XMC_SDRAM_BANK1
+ * - XMC_SDRAM_BANK1
+ * @retval the bank status
+ */
+uint32_t xmc_sdram_status_get(xmc_sdram_bank_type xmc_bank)
+{
+ if(xmc_bank == XMC_SDRAM_BANK1)
+ {
+ return ((XMC_SDRAM->sts >> 1) & XMC_STATUS_MASK);
+ }
+ else
+ {
+ return ((XMC_SDRAM->sts >> 3) & XMC_STATUS_MASK);
+ }
+}
+
+/**
+ * @brief set sdram refresh counter
+ * @param counter: xmc sdram refresh counter
+ * @retval none
+ */
+void xmc_sdram_refresh_counter_set(uint32_t counter)
+{
+ XMC_SDRAM->rcnt_bit.rc = counter;
+}
+
+/**
+ * @brief set sdram auto refresh number
+ * @param number: xmc sdram auto refresh number
+ * @retval none
+ */
+void xmc_sdram_auto_refresh_set(uint32_t number)
+{
+ XMC_SDRAM->cmd_bit.art = number;
+}
+
+/**
+ * @brief enable or disable the specified xmc interrupts.
+ * @param xmc_bank: specifies the xmc bank to be used
+ * this parameter can be one of the following values:
+ * - XMC_BANK5_6_SDRAM
+ * @param xmc_int: specifies the xmc interrupt sources to be enabled or disabled.
+ * this parameter can be any combination of the following values:
+ * - XMC_INT_RISING_EDGE
+ * - XMC_INT_LEVEL
+ * - XMC_INT_FALLING_EDGE
+ * - XMC_INT_ERR
+ * @param new_state (TRUE or FALSE)
+ * @retval none
+ */
+void xmc_interrupt_enable(xmc_class_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state)
+{
+ if(new_state != FALSE)
+ {
+ XMC_SDRAM->rcnt |= xmc_int;
+ }
+ else
+ {
+ XMC_SDRAM->rcnt &= ~xmc_int;
+ }
+}
+
+/**
+ * @brief check whether the specified xmc flag is set or not.
+ * @param xmc_bank: specifies the xmc bank to be used
+ * this parameter can be one of the following values:
+ * - XMC_BANK5_6_SDRAM
+ * @param xmc_flag: specifies the flag to check.
+ * this parameter can be any combination of the following values:
+ * - XMC_BUSY_FLAG
+ * - XMC_ERR_FLAG
+ * @retval none
+ */
+flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
+{
+ flag_status status = RESET;
+ uint32_t temp = 0;
+
+ temp = XMC_SDRAM->sts;
+
+ /* get the flag status */
+ if((temp & xmc_flag) == RESET)
+ {
+ status = RESET;
+ }
+ else
+ {
+ status = SET;
+ }
+ /* return the flag status */
+ return status;
+}
+
+/**
+ * @brief clear the xmc's pending flags.
+ * @param xmc_bank: specifies the xmc bank to be used
+ * this parameter can be one of the following values:
+ * - XMC_BANK5_6_SDRAM
+ * @param xmc_flag: specifies the flag to check.
+ * this parameter can be any combination of the following values:
+ * - XMC_ERR_FLAG
+ * @retval none
+ */
+void xmc_flag_clear(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag)
+{
+ XMC_SDRAM->rcnt |= xmc_flag;
+}
+
+/**
+ * @}
+ */
+
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/cmsis/cm4/device_support/system_at32m412_416.c b/bsp/at32/libraries/AT32M412_416_Firmware_Library/cmsis/cm4/device_support/system_at32m412_416.c
index d6548fb30e4..c29d9c6db8b 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/cmsis/cm4/device_support/system_at32m412_416.c
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/cmsis/cm4/device_support/system_at32m412_416.c
@@ -88,7 +88,7 @@ void SystemInit (void)
/* reset pllms pllns pllfr pllrcs bits */
CRM->pllcfg = 0x00033002U;
- /* reset clkout[3], hickdiv, clkoutdiv */
+ /* reset clkout[3], clkoutdiv */
CRM->misc1 = 0x000F1000;
/* disable all interrupts enable and clear pending bits */
@@ -124,7 +124,7 @@ void system_core_clock_update(void)
switch(sclk_source)
{
case CRM_SCLK_HICK:
- if(((CRM->misc1_bit.hick_to_sclk) != RESET) && ((CRM->misc1_bit.hickdiv) != RESET))
+ if((CRM->misc1_bit.hick_to_sclk) != RESET)
system_core_clock = HICK_VALUE * 6;
else
system_core_clock = HICK_VALUE;
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_adc.h b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_adc.h
index 8d7ee53f87f..4e1946ae403 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_adc.h
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_adc.h
@@ -5,11 +5,11 @@
**************************************************************************
* Copyright notice & Disclaimer
*
- * The software Board Support Package (BSP) that is made available to
- * download from Artery official website is the copyrighted work of Artery.
- * Artery authorizes customers to use, copy, and distribute the BSP
- * software and its related documentation for the purpose of design and
- * development in conjunction with Artery microcontrollers. Use of the
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -29,8 +29,8 @@
#ifdef __cplusplus
extern "C" {
#endif
-
-
+
+
/* Includes ------------------------------------------------------------------*/
#include "at32m412_416.h"
@@ -43,10 +43,10 @@ extern "C" {
*/
/** @defgroup ADC_interrupts_definition
- * @brief adc interrupt
+ * @brief adc interrupt
* @{
*/
-
+
#define ADC_OCCE_INT ((uint32_t)0x00000020) /*!< ordinary channels conversion end interrupt */
#define ADC_VMOR_INT ((uint32_t)0x00000040) /*!< voltage monitoring out of range interrupt */
#define ADC_PCCE_INT ((uint32_t)0x00000080) /*!< preempt channels conversion end interrupt */
@@ -720,7 +720,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} odt_bit;
};
-
+
/**
* @brief adc spt3 register, offset:0x50
*/
@@ -837,9 +837,9 @@ typedef struct
__IO uint32_t codth : 16; /* [31:16] */
} codt_bit;
};
-
+
__IO uint32_t reserved1;
-
+
/**
* @brief adc1 odt1 register, offset:0x310
*/
@@ -852,7 +852,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc1_odt1_bit;
};
-
+
/**
* @brief adc1 odt2 register, offset:0x314
*/
@@ -865,7 +865,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc1_odt2_bit;
};
-
+
/**
* @brief adc1 odt3 register, offset:0x318
*/
@@ -878,7 +878,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc1_odt3_bit;
};
-
+
/**
* @brief adc1 odt4 register, offset:0x31c
*/
@@ -891,7 +891,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc1_odt4_bit;
};
-
+
/**
* @brief adc1 odt4 register, offset:0x320
*/
@@ -904,7 +904,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc1_odt5_bit;
};
-
+
/**
* @brief adc1 odt6 register, offset:0x324
*/
@@ -917,7 +917,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc1_odt6_bit;
};
-
+
/**
* @brief adc1 odt7 register, offset:0x328
*/
@@ -930,7 +930,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc1_odt7_bit;
};
-
+
/**
* @brief adc1 odt8 register, offset:0x32c
*/
@@ -943,7 +943,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc1_odt8_bit;
};
-
+
/**
* @brief adc1 odt9 register, offset:0x330
*/
@@ -956,7 +956,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc1_odt9_bit;
};
-
+
/**
* @brief adc1 odt10 register, offset:0x334
*/
@@ -969,7 +969,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc1_odt10_bit;
};
-
+
/**
* @brief adc1 odt11 register, offset:0x338
*/
@@ -982,7 +982,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc1_odt11_bit;
};
-
+
/**
* @brief adc1 odt12 register, offset:0x33c
*/
@@ -995,7 +995,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc1_odt12_bit;
};
-
+
/**
* @brief adc1 odt13 register, offset:0x340
*/
@@ -1008,7 +1008,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc1_odt13_bit;
};
-
+
/**
* @brief adc1 odt14 register, offset:0x344
*/
@@ -1021,7 +1021,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc1_odt14_bit;
};
-
+
/**
* @brief adc1 odt15 register, offset:0x348
*/
@@ -1034,7 +1034,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc1_odt15_bit;
};
-
+
/**
* @brief adc1 odt16 register, offset:0x34c
*/
@@ -1047,7 +1047,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc1_odt16_bit;
};
-
+
/**
* @brief adc2 odt1 register, offset:0x350
*/
@@ -1060,7 +1060,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc2_odt1_bit;
};
-
+
/**
* @brief adc2 odt2 register, offset:0x354
*/
@@ -1073,7 +1073,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc2_odt2_bit;
};
-
+
/**
* @brief adc2 odt3 register, offset:0x358
*/
@@ -1086,7 +1086,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc2_odt3_bit;
};
-
+
/**
* @brief adc2 odt4 register, offset:0x35c
*/
@@ -1099,7 +1099,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc2_odt4_bit;
};
-
+
/**
* @brief adc2 odt4 register, offset:0x360
*/
@@ -1112,7 +1112,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc2_odt5_bit;
};
-
+
/**
* @brief adc2 odt6 register, offset:0x364
*/
@@ -1125,7 +1125,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc2_odt6_bit;
};
-
+
/**
* @brief adc2 odt7 register, offset:0x368
*/
@@ -1138,7 +1138,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc2_odt7_bit;
};
-
+
/**
* @brief adc2 odt8 register, offset:0x36c
*/
@@ -1151,7 +1151,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc2_odt8_bit;
};
-
+
/**
* @brief adc2 odt9 register, offset:0x370
*/
@@ -1164,7 +1164,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc2_odt9_bit;
};
-
+
/**
* @brief adc2 odt10 register, offset:0x374
*/
@@ -1177,7 +1177,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc2_odt10_bit;
};
-
+
/**
* @brief adc2 odt11 register, offset:0x378
*/
@@ -1190,7 +1190,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc2_odt11_bit;
};
-
+
/**
* @brief adc2 odt12 register, offset:0x37c
*/
@@ -1203,7 +1203,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc2_odt12_bit;
};
-
+
/**
* @brief adc2 odt13 register, offset:0x380
*/
@@ -1216,7 +1216,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc2_odt13_bit;
};
-
+
/**
* @brief adc2 odt14 register, offset:0x384
*/
@@ -1229,7 +1229,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc2_odt14_bit;
};
-
+
/**
* @brief adc2 odt15 register, offset:0x388
*/
@@ -1242,7 +1242,7 @@ typedef struct
__IO uint32_t reserved1 : 16; /* [31:16] */
} adc2_odt15_bit;
};
-
+
/**
* @brief adc2 odt16 register, offset:0x38c
*/
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_can.h b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_can.h
index 59a9224cecc..d8b8bee98fc 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_can.h
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_can.h
@@ -5,11 +5,11 @@
**************************************************************************
* Copyright notice & Disclaimer
*
- * The software Board Support Package (BSP) that is made available to
- * download from Artery official website is the copyrighted work of Artery.
- * Artery authorizes customers to use, copy, and distribute the BSP
- * software and its related documentation for the purpose of design and
- * development in conjunction with Artery microcontrollers. Use of the
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -44,8 +44,8 @@ extern "C" {
/** @addtogroup CAN
* @{
- */
-
+ */
+
/** @defgroup CAN_interrupts_definition
* @brief can interrupt
* @{
@@ -143,7 +143,7 @@ typedef enum
CAN_ESI_ACTIVE = 0x00, /*!< error_state_indicator active */
CAN_ESI_PASSIVE = 0x01 /*!< error_state_indicator passive */
} can_error_state_type;
-#endif
+#endif
/**
* @brief can data length type
@@ -167,7 +167,7 @@ typedef enum
CAN_DLC_BYTES_32 = 0x0D, /*!< 32 bytes data field */
CAN_DLC_BYTES_48 = 0x0E, /*!< 48 bytes data field */
CAN_DLC_BYTES_64 = 0x0F /*!< 64 bytes data field */
-#endif
+#endif
} can_data_length_type;
/**
@@ -199,7 +199,7 @@ typedef enum
} can_abort_transmit_type;
/**
- * @brief can clear the secondary transmit buffer type
+ * @brief can clear the secondary transmit buffer type
*/
typedef enum
{
@@ -208,7 +208,7 @@ typedef enum
} can_clear_stb_type;
/**
- * @brief can the secondary transmit buffer transmit mode type
+ * @brief can the secondary transmit buffer transmit mode type
*/
typedef enum
{
@@ -372,7 +372,7 @@ typedef enum
} can_tstat_encoding_type;
/**
- * @brief can filter type
+ * @brief can filter type
*/
typedef enum
{
@@ -395,7 +395,7 @@ typedef enum
} can_filter_type;
/**
- * @brief can ttcan txbuf type
+ * @brief can ttcan txbuf type
*/
typedef enum
{
@@ -411,13 +411,13 @@ typedef enum
typedef struct
{
uint8_t current_handle; /*!< specifies current handle for frame identification. */
-
+
can_tstat_encoding_type current_tstat; /*!< specifies current transmission status of transmit frame.*/
-
+
uint8_t final_handle; /*!< specifies final handle for frame identification. */
-
+
can_tstat_encoding_type final_tstat; /*!< specifies final transmission status of transmit frame.*/
-
+
} can_transmit_status_type;
/**
@@ -425,27 +425,27 @@ typedef struct
*/
typedef struct
{
- uint32_t id; /*!< specifies the 11 or 29 bits standard or extended identifier.
+ uint32_t id; /*!< specifies the 11 or 29 bits standard or extended identifier.
this parameter can be a value between 0 to 0x7FF or 0 to 0x1FFFFFFF. */
can_identifier_type id_type; /*!< specifies identifier type for the transmit buffer. */
can_frame_type frame_type; /*!< specifies frame type for the transmit buffer. */
-
+
can_data_length_type data_length; /*!< specifies the frame data length that will be transmitted. */
#ifdef SUPPORT_CAN_FD
can_format_type fd_format; /*!< specifies format for the transmit buffer. */
can_rate_switch_type fd_rate_switch; /*!< specifies bit rate switch for the transmit buffer. */
-
+
uint8_t data[64]; /*!< contains the transmit data. it ranges from 0 to 0xFF. */
#else
uint8_t data[8]; /*!< contains the transmit data. it ranges from 0 to 0xFF. */
#endif
-
+
confirm_state tx_timestamp; /*!< specifies get transmit timestamp for the transmit buffer. */
-
+
uint8_t handle; /*!< The purpose of the handle is frame identification using TSTAT(transmit status). */
} can_txbuf_type;
@@ -454,32 +454,32 @@ typedef struct
* @brief can receive buffer structure definition
*/
typedef struct
-{
+{
uint32_t id; /*!< specifies the 11 or 29 bits standard or extended identifier.
this parameter can be a value between 0 to 0x7FF or 0 to 0x1FFFFFFF. */
-
+
can_identifier_type id_type; /*!< specifies identifier type for the receive buffer. */
-
+
can_frame_type frame_type; /*!< specifies frame type for the receive buffer. */
-
+
can_data_length_type data_length; /*!< specifies the frame data length that will be received. */
-
-#ifdef SUPPORT_CAN_FD
+
+#ifdef SUPPORT_CAN_FD
can_format_type fd_format; /*!< specifies format for the receive buffer. */
-
+
can_rate_switch_type fd_rate_switch; /*!< specifies bit rate switch for the receive buffer. */
-
+
can_error_state_type fd_error_state; /*!< specifies error state indicator type for the receive buffer. */
-
+
uint8_t data[64]; /*!< contains the receive data. it ranges from 0 to 0xFF. */
-#else
+#else
uint8_t data[8]; /*!< contains the receive data. it ranges from 0 to 0xFF. */
-#endif
-
+#endif
+
can_recv_frame_type recv_frame; /*!< specifies receive frame mode for the receive buffer. */
-
+
can_error_type kind_error; /*!< specifies kind of error type for the receive buffer. */
-
+
uint32_t rx_timestamp; /*!< specifies the timestamp for the receive buffer. */
uint16_t cycle_time; /*!< specifies the cycle time for the receive buffer using TTCAN(Time-Triggered CAN). */
@@ -490,63 +490,63 @@ typedef struct
* @brief can filter code type
*/
typedef struct
-{
+{
uint32_t id; /*!< specifies the 11 or 29 bits standard or extended identifier.
this parameter can be a value between 0 to 0x7FF or 0 to 0x1FFFFFFF. */
can_identifier_type id_type; /*!< specifies identifier type for the filter code. */
can_frame_type frame_type; /*!< specifies frame type for the filter code. */
-
+
uint8_t data_length; /*!< specifies frame data length for the filter code. */
-
-#ifdef SUPPORT_CAN_FD
+
+#ifdef SUPPORT_CAN_FD
can_format_type fd_format; /*!< specifies format for the filter code. */
can_rate_switch_type fd_rate_switch; /*!< specifies bit rate switch for the filter code. */
-
+
can_error_state_type fd_error_state; /*!< specifies error state indicator for the filter code. */
-#endif
-
+#endif
+
can_recv_frame_type recv_frame; /*!< specifies receive frame mode for the filter code. */
-} can_filter_code_type;
+} can_filter_code_type;
/**
* @brief can filter mask type
*/
typedef struct
-{
+{
uint32_t id; /*!< specifies the 11 or 29 bits standard or extended identifier.
this parameter can be a value between 0 to 0x7FF or 0 to 0x1FFFFFFF. */
-
+
confirm_state id_type; /*!< specifies identifier type for the filter mask. */
-
+
confirm_state frame_type; /*!< specifies frame type for the filter mask. */
-
- uint8_t data_length; /*!< specifies frame data length for the filter mask. */
-
-#ifdef SUPPORT_CAN_FD
+
+ uint8_t data_length; /*!< specifies frame data length for the filter mask. */
+
+#ifdef SUPPORT_CAN_FD
confirm_state fd_format; /*!< specifies format for the filter mask. */
-
+
confirm_state fd_rate_switch; /*!< specifies bit rate switch for the filter mask. */
-
+
confirm_state fd_error_state; /*!< specifies error state indicator for the filter mask. */
-#endif
-
+#endif
+
confirm_state recv_frame; /*!< specifies receive frame mode for the filter mask. */
-
+
} can_filter_mask_type;
/**
* @brief can filter config type
*/
typedef struct
-{
+{
can_filter_code_type code_para; /*!< specifies the filter code type. */
-
+
can_filter_mask_type mask_para; /*!< specifies the filter mask type. */
-
+
} can_filter_config_type;
/**
@@ -555,32 +555,32 @@ typedef struct
typedef struct
{
uint8_t bittime_div; /*!< bittime division, this parameter can be 0x01~0x20. */
-
+
uint8_t ac_rsaw_size; /*!< classic-can resynchronization adjust width, this parameter can be 0x01~0x80. */
-
+
uint16_t ac_bts1_size; /*!< classic-can bit time segment 1, this parameter can be 0x02~0x201. */
-
+
uint8_t ac_bts2_size; /*!< classic-can bit time segment 2, this parameter can be 0x01~0x80. */
-
-#ifdef SUPPORT_CAN_FD
+
+#ifdef SUPPORT_CAN_FD
uint8_t fd_rsaw_size; /*!< can-fd resynchronization adjust width, this parameter can be 0x01~0x80. */
uint16_t fd_bts1_size; /*!< can-fd bit time segment 1, this parameter can be 0x02~0x101. */
uint8_t fd_bts2_size; /*!< can-fd bit time segment 2, this parameter can be 0x01~0x80. */
-
+
uint8_t fd_ssp_offset; /*!< can-fd secondary sample point offset, this parameter can be 0x00~0xFF. */
-#endif
-
+#endif
+
} can_bittime_type;
/**
* @brief type define can register all
*/
typedef struct
-{
+{
/**
- * @brief can tncfg register, offset:0x00
+ * @brief can tncfg register, offset:0x00
*/
union
{
@@ -589,15 +589,15 @@ typedef struct
{
__IO uint32_t reserved1 : 17;/* [16:0] */
__IO uint32_t rop : 1; /* [17] */
- __IO uint32_t reserved2 : 6; /* [23:18] */
- __IO uint32_t tsen : 1; /* [24] */
- __IO uint32_t tspos : 1; /* [25] */
- __IO uint32_t reserved3 : 6; /* [31:26] */
+ __IO uint32_t reserved2 : 6; /* [23:18] */
+ __IO uint32_t tsen : 1; /* [24] */
+ __IO uint32_t tspos : 1; /* [25] */
+ __IO uint32_t reserved3 : 6; /* [31:26] */
} tncfg_bit;
};
-
+
/**
- * @brief can actime register, offset:0x04
+ * @brief can actime register, offset:0x04
*/
union
{
@@ -608,13 +608,13 @@ typedef struct
__IO uint32_t reserved1 : 7; /* [15:9] */
__IO uint32_t ac_seg_2 : 7; /* [22:16] */
__IO uint32_t reserved2 : 1; /* [23] */
- __IO uint32_t ac_sjw : 7; /* [30:24] */
- __IO uint32_t reserved3 : 1; /* [31] */
+ __IO uint32_t ac_sjw : 7; /* [30:24] */
+ __IO uint32_t reserved3 : 1; /* [31] */
} actime_bit;
};
-
+
/**
- * @brief can fdtime register, offset:0x08
+ * @brief can fdtime register, offset:0x08
*/
union
{
@@ -625,18 +625,18 @@ typedef struct
__IO uint32_t reserved1 : 8; /* [15:8] */
__IO uint32_t fd_seg_2 : 7; /* [22:16] */
__IO uint32_t reserved2 : 1; /* [23] */
- __IO uint32_t fd_sjw : 7; /* [30:24] */
- __IO uint32_t reserved3 : 1; /* [31] */
+ __IO uint32_t fd_sjw : 7; /* [30:24] */
+ __IO uint32_t reserved3 : 1; /* [31] */
} fdtime_bit;
};
-
+
/**
- * @brief can reserved1 register, offset:0x0C
+ * @brief can reserved1 register, offset:0x0C
*/
__IO uint32_t reserved1;
-
+
/**
- * @brief can lbtcfg register, offset:0x10
+ * @brief can lbtcfg register, offset:0x10
*/
union
{
@@ -647,15 +647,15 @@ typedef struct
__IO uint32_t reserved1 : 3; /* [7:5] */
__IO uint32_t fd_sspoff : 8; /* [15:8] */
__IO uint32_t reserved2 : 8; /* [23:16] */
- __IO uint32_t realim : 3; /* [26:24] */
- __IO uint32_t reserved3 : 1; /* [27] */
+ __IO uint32_t realim : 3; /* [26:24] */
+ __IO uint32_t reserved3 : 1; /* [27] */
__IO uint32_t retlim : 3; /* [30:28] */
- __IO uint32_t reserved4 : 1; /* [31] */
+ __IO uint32_t reserved4 : 1; /* [31] */
} lbtcfg_bit;
};
-
+
/**
- * @brief can sts register, offset:0x14
+ * @brief can sts register, offset:0x14
*/
union
{
@@ -666,8 +666,8 @@ typedef struct
__IO uint32_t eif : 1; /* [1] */
__IO uint32_t tsif : 1; /* [2] */
__IO uint32_t tpif : 1; /* [3] */
- __IO uint32_t rafif : 1; /* [4] */
- __IO uint32_t rfif : 1; /* [5] */
+ __IO uint32_t rafif : 1; /* [4] */
+ __IO uint32_t rfif : 1; /* [5] */
__IO uint32_t roif : 1; /* [6] */
__IO uint32_t rif : 1; /* [7] */
__IO uint32_t beif : 1; /* [8] */
@@ -683,12 +683,12 @@ typedef struct
};
/**
- * @brief can reserved register, offset:0x18
+ * @brief can reserved register, offset:0x18
*/
__IO uint32_t reserved2;
/**
- * @brief can tstat register, offset:0x1C
+ * @brief can tstat register, offset:0x1C
*/
union
{
@@ -699,23 +699,23 @@ typedef struct
__IO uint32_t tstat_1 : 3; /* [10:8] */
__IO uint32_t reserved1 : 5; /* [15:11] */
__IO uint32_t handle_2 : 8; /* [23:16] */
- __IO uint32_t tstat_2 : 3; /* [26:24] */
- __IO uint32_t reserved2 : 5; /* [31:27] */
+ __IO uint32_t tstat_2 : 3; /* [26:24] */
+ __IO uint32_t reserved2 : 5; /* [31:27] */
} tstat_bit;
};
-
+
/**
- * @brief can tts register, offset:0x20
+ * @brief can tts register, offset:0x20
*/
__IO uint32_t tts;
-
+
/**
* @brief can reserved register, offset:0x24
*/
__IO uint32_t reserved3;
-
+
/**
- * @brief can ctrlstat register, offset:0x28
+ * @brief can ctrlstat register, offset:0x28
*/
union
{
@@ -726,8 +726,8 @@ typedef struct
__IO uint32_t reserved1 : 4; /* [4:1] */
__IO uint32_t lbmi : 1; /* [5] */
__IO uint32_t lbme : 1; /* [6] */
- __IO uint32_t reset : 1; /* [7] */
- __IO uint32_t tsa : 1; /* [8] */
+ __IO uint32_t reset : 1; /* [7] */
+ __IO uint32_t tsa : 1; /* [8] */
__IO uint32_t tsall : 1; /* [9] */
__IO uint32_t tsone : 1; /* [10] */
__IO uint32_t tpa : 1; /* [11] */
@@ -735,9 +735,9 @@ typedef struct
__IO uint32_t stby : 1; /* [13] */
__IO uint32_t lom : 1; /* [14] */
__IO uint32_t tbsel : 1; /* [15] */
- __IO uint32_t tsstat : 2; /* [17:16] */
- __IO uint32_t tsff : 1; /* [18] */
- __IO uint32_t reserved2 : 1; /* [19] */
+ __IO uint32_t tsstat : 2; /* [17:16] */
+ __IO uint32_t tsff : 1; /* [18] */
+ __IO uint32_t reserved2 : 1; /* [19] */
__IO uint32_t tttbm : 1; /* [20] */
__IO uint32_t tsmode : 1; /* [21] */
__IO uint32_t tsnext : 1; /* [22] */
@@ -751,9 +751,9 @@ typedef struct
__IO uint32_t sack : 1; /* [31] */
} ctrlstat_bit;
};
-
+
/**
- * @brief can err register, offset:0x2C
+ * @brief can err register, offset:0x2C
*/
union
{
@@ -764,13 +764,13 @@ typedef struct
__IO uint32_t afwl : 4; /* [7:4] */
__IO uint32_t alc : 5; /* [12:8] */
__IO uint32_t koer : 3; /* [15:13] */
- __IO uint32_t recnt : 8; /* [23:16] */
- __IO uint32_t tecnt : 8; /* [31:24] */
+ __IO uint32_t recnt : 8; /* [23:16] */
+ __IO uint32_t tecnt : 8; /* [31:24] */
} err_bit;
};
-
+
/**
- * @brief can refmsg register, offset:0x30
+ * @brief can refmsg register, offset:0x30
*/
union
{
@@ -779,12 +779,12 @@ typedef struct
{
__IO uint32_t ref_id : 29; /* [28:0] */
__IO uint32_t reserved1 : 2; /* [30:29] */
- __IO uint32_t ref_ide : 1; /* [31] */
+ __IO uint32_t ref_ide : 1; /* [31] */
} refmsg_bit;
};
-
+
/**
- * @brief can ttcfg register, offset:0x34
+ * @brief can ttcfg register, offset:0x34
*/
union
{
@@ -795,18 +795,18 @@ typedef struct
__IO uint32_t reserved1 : 2; /* [7:6] */
__IO uint32_t ttype : 3; /* [10:8] */
__IO uint32_t reserved2 : 1; /* [11] */
- __IO uint32_t tew : 4; /* [15:12] */
- __IO uint32_t tbptr : 6; /* [21:16] */
- __IO uint32_t tbf : 1; /* [22] */
+ __IO uint32_t tew : 4; /* [15:12] */
+ __IO uint32_t tbptr : 6; /* [21:16] */
+ __IO uint32_t tbf : 1; /* [22] */
__IO uint32_t tbe : 1; /* [23] */
__IO uint32_t tten : 1; /* [24] */
__IO uint32_t t_presc : 2; /* [26:25] */
__IO uint32_t reserved3 : 5; /* [31:27] */
} ttcfg_bit;
};
-
+
/**
- * @brief can tttrig register, offset:0x38
+ * @brief can tttrig register, offset:0x38
*/
union
{
@@ -814,17 +814,17 @@ typedef struct
struct
{
__IO uint32_t tttrig : 16; /* [15:0] */
- __IO uint32_t ttwtrig : 16; /* [31:16] */
+ __IO uint32_t ttwtrig : 16; /* [31:16] */
} tttrig_bit;
};
-
+
/**
- * @brief can reserved register, offset:0x3C-0x40
+ * @brief can reserved register, offset:0x3C-0x40
*/
__IO uint32_t reserved4[2];
-
+
/**
- * @brief can acfctrl register, offset:0x44
+ * @brief can acfctrl register, offset:0x44
*/
union
{
@@ -836,17 +836,16 @@ typedef struct
__IO uint32_t ae_x : 16; /* [31:16] */
} acfctrl_bit;
};
-
+
/**
- * @brief can fcid register, offset:0x48
+ * @brief can fcid register, offset:0x48
*/
__IO uint32_t fcid;
-
/**
- * @brief can fcfmt register, offset:0x4C
+ * @brief can fcfmt register, offset:0x4C
*/
- union
+ union
{
__IO uint32_t fcfmt;
struct
@@ -854,7 +853,7 @@ typedef struct
__IO uint32_t dlc : 4; /* [3:0] */
__IO uint32_t reserved1 : 12; /* [15:4] */
__IO uint32_t ide : 1; /* [16] */
- __IO uint32_t fdf : 1; /* [17] */
+ __IO uint32_t fdf : 1; /* [17] */
__IO uint32_t brs : 1; /* [18] */
__IO uint32_t xlf : 1; /* [19] */
__IO uint32_t rmf : 1; /* [20] */
@@ -863,14 +862,14 @@ typedef struct
__IO uint32_t koer : 3; /* [26:24] */
__IO uint32_t esi : 1; /* [27] */
__IO uint32_t lbf : 1; /* [28] */
- __IO uint32_t reserved3 : 3; /* [31:29] */
+ __IO uint32_t reserved3 : 3; /* [31:29] */
} fcfmt_bit;
};
-
+
/**
- * @brief can fctyp register, offset:0x50
+ * @brief can fctyp register, offset:0x50
*/
- union
+ union
{
__IO uint32_t fctyp;
struct
@@ -878,24 +877,24 @@ typedef struct
__IO uint32_t sdt : 8; /* [7:0] */
__IO uint32_t vcid : 8; /* [15:8] */
__IO uint32_t reserved1 : 8; /* [23:16] */
- __IO uint32_t handle : 8; /* [31:24] */
+ __IO uint32_t handle : 8; /* [31:24] */
} fctyp_bit;
};
/**
- * @brief can fcacf register, offset:0x54
+ * @brief can reserved register, offset:0x54
*/
- __IO uint32_t fcacf;
-
+ __IO uint32_t reserved5;
+
/**
- * @brief can fmid register, offset:0x58
+ * @brief can fmid register, offset:0x58
*/
__IO uint32_t fmid;
-
+
/**
- * @brief can fmfmt register, offset:0x5C
+ * @brief can fmfmt register, offset:0x5C
*/
- union
+ union
{
__IO uint32_t fmfmt;
struct
@@ -903,7 +902,7 @@ typedef struct
__IO uint32_t dlc : 4; /* [3:0] */
__IO uint32_t reserved1 : 12; /* [15:4] */
__IO uint32_t ide : 1; /* [16] */
- __IO uint32_t fdf : 1; /* [17] */
+ __IO uint32_t fdf : 1; /* [17] */
__IO uint32_t brs : 1; /* [18] */
__IO uint32_t xlf : 1; /* [19] */
__IO uint32_t rmf : 1; /* [20] */
@@ -912,14 +911,14 @@ typedef struct
__IO uint32_t koer : 3; /* [26:24] */
__IO uint32_t esi : 1; /* [27] */
__IO uint32_t lbf : 1; /* [28] */
- __IO uint32_t reserved3 : 3; /* [31:29] */
+ __IO uint32_t reserved3 : 3; /* [31:29] */
} fmfmt_bit;
};
-
+
/**
- * @brief can fmtyp register, offset:0x60
+ * @brief can fmtyp register, offset:0x60
*/
- union
+ union
{
__IO uint32_t fmtyp;
struct
@@ -927,29 +926,24 @@ typedef struct
__IO uint32_t sdt : 8; /* [7:0] */
__IO uint32_t vcid : 8; /* [15:8] */
__IO uint32_t reserved1 : 8; /* [23:16] */
- __IO uint32_t handle : 8; /* [31:24] */
+ __IO uint32_t handle : 8; /* [31:24] */
} fmtyp_bit;
};
-
- /**
- * @brief can fmacf register, offset:0x64
- */
- __IO uint32_t fmacf;
-
+
/**
- * @brief can reserved register, offset:0x68-0x6C
+ * @brief can reserved register, offset:0x64-0x6C
*/
- __IO uint32_t reserved5[2];
-
+ __IO uint32_t reserved6[3];
+
/**
* @brief can rbid register, offset:0x70
*/
__IO uint32_t rbid;
-
+
/**
* @brief can rbfmt register, offset:0x74
*/
- union
+ union
{
__IO uint32_t rbfmt;
struct
@@ -957,7 +951,7 @@ typedef struct
__IO uint32_t dlc : 4; /* [3:0] */
__IO uint32_t reserved1 : 12; /* [15:4] */
__IO uint32_t ide : 1; /* [16] */
- __IO uint32_t fdf : 1; /* [17] */
+ __IO uint32_t fdf : 1; /* [17] */
__IO uint32_t brs : 1; /* [18] */
__IO uint32_t xlf : 1; /* [19] */
__IO uint32_t rmf : 1; /* [20] */
@@ -966,14 +960,14 @@ typedef struct
__IO uint32_t koer : 3; /* [26:24] */
__IO uint32_t esi : 1; /* [27] */
__IO uint32_t lbf : 1; /* [28] */
- __IO uint32_t reserved3 : 3; /* [31:29] */
+ __IO uint32_t reserved3 : 3; /* [31:29] */
} rbfmt_bit;
};
-
+
/**
* @brief can rbtyp register, offset:0x78
*/
- union
+ union
{
__IO uint32_t rbtyp;
struct
@@ -981,29 +975,29 @@ typedef struct
__IO uint32_t sdt : 8; /* [7:0] */
__IO uint32_t vcid : 8; /* [15:8] */
__IO uint32_t reserved1 : 8; /* [23:16] */
- __IO uint32_t handle : 8; /* [31:24] */
+ __IO uint32_t handle : 8; /* [31:24] */
} rbtyp_bit;
};
-
+
/**
- * @brief can rbacf register, offset:0x7C
+ * @brief can reserved register, offset:0x7C
*/
- __IO uint32_t rbacf;
-
+ __IO uint32_t reserved7;
+
/**
* @brief can rbdat register, offset:0x80-0xC8
*/
__IO uint32_t rbdat[19];
-
+
/**
* @brief can tbid register, offset:0xCC
*/
__IO uint32_t tbid;
-
+
/**
* @brief can tbfmt register, offset:0xD0
*/
- union
+ union
{
__IO uint32_t tbfmt;
struct
@@ -1011,7 +1005,7 @@ typedef struct
__IO uint32_t dlc : 4; /* [3:0] */
__IO uint32_t reserved1 : 12; /* [15:4] */
__IO uint32_t ide : 1; /* [16] */
- __IO uint32_t fdf : 1; /* [17] */
+ __IO uint32_t fdf : 1; /* [17] */
__IO uint32_t brs : 1; /* [18] */
__IO uint32_t xlf : 1; /* [19] */
__IO uint32_t rmf : 1; /* [20] */
@@ -1020,14 +1014,14 @@ typedef struct
__IO uint32_t koer : 3; /* [26:24] */
__IO uint32_t esi : 1; /* [27] */
__IO uint32_t lbf : 1; /* [28] */
- __IO uint32_t reserved3 : 3; /* [31:29] */
+ __IO uint32_t reserved3 : 3; /* [31:29] */
} tbfmt_bit;
};
-
+
/**
* @brief can tbtyp register, offset:0xD4
*/
- union
+ union
{
__IO uint32_t tbtyp;
struct
@@ -1035,30 +1029,30 @@ typedef struct
__IO uint32_t sdt : 8; /* [7:0] */
__IO uint32_t vcid : 8; /* [15:8] */
__IO uint32_t reserved1 : 8; /* [23:16] */
- __IO uint32_t handle : 8; /* [31:24] */
+ __IO uint32_t handle : 8; /* [31:24] */
} tbtyp_bit;
};
-
+
/**
- * @brief can tbacf register, offset:0xD8
+ * @brief can reserved register, offset:0xD8
*/
- __IO uint32_t tbacf;
-
+ __IO uint32_t reserved8;
+
/**
* @brief can tbdat register, offset:0xDC-0x118
*/
__IO uint32_t tbdat[16];
-
+
/**
* @brief can reserved register, offset:0x11C-0x120
*/
- __IO uint32_t reserved6[2];
-
+ __IO uint32_t reserved9[2];
+
/**
* @brief can llcformat register, offset:0x124
*/
__IO uint32_t llcformat;
-
+
/**
* @brief can llcsize register, offset:0x128
*/
@@ -1071,12 +1065,12 @@ typedef struct
__IO uint32_t llcaot : 16; /* [31:16] */
} llcsize_bit;
};
-
+
/**
* @brief can reserved register, offset:0x12C-0x13C
*/
- __IO uint32_t reserved7[5];
-
+ __IO uint32_t reserved10[5];
+
/**
* @brief can inten register, offset:0x140
*/
@@ -1089,8 +1083,8 @@ typedef struct
__IO uint32_t eien : 1; /* [1] */
__IO uint32_t tsien : 1; /* [2] */
__IO uint32_t tpien : 1; /* [3] */
- __IO uint32_t rafien : 1; /* [4] */
- __IO uint32_t rfien : 1; /* [5] */
+ __IO uint32_t rafien : 1; /* [4] */
+ __IO uint32_t rfien : 1; /* [5] */
__IO uint32_t roien : 1; /* [6] */
__IO uint32_t rien : 1; /* [7] */
__IO uint32_t beien : 1; /* [8] */
@@ -1101,8 +1095,8 @@ typedef struct
__IO uint32_t wtien : 1; /* [13] */
__IO uint32_t reserved1 : 18; /* [31:14] */
} inten_bit;
- };
-} can_type;
+ };
+} can_type;
#define CAN1 ((can_type *) CAN1_BASE)
@@ -1154,8 +1148,8 @@ flag_status can_busoff_get(can_type* can_x);
void can_busoff_reset(can_type* can_x);
void can_ttcan_ref_message_set(can_type* can_x, can_identifier_type id_type, uint32_t id);
-void can_ttcan_timer_div_set(can_type* can_x, can_ttcan_timer_div_type div_value);
-void can_ttcan_enable(can_type* can_x, confirm_state new_state);
+void can_ttcan_timer_div_set(can_type* can_x, can_ttcan_timer_div_type div_value);
+void can_ttcan_enable(can_type* can_x, confirm_state new_state);
void can_ttcan_trigger_type_set(can_type* can_x, can_ttcan_trigger_type trigger_type);
void can_ttcan_trigger_set(can_type* can_x, uint16_t trigger_time);
void can_ttcan_watch_trigger_set(can_type* can_x, uint16_t watch_trigger_time);
@@ -1172,7 +1166,7 @@ flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag);
void can_flag_clear(can_type* can_x, uint32_t can_flag);
/*
-note:
+note:
the following functions is only support can-fd.
- can_fd_iso_mode_enable
the following functions is support classic-can and can-fd.
@@ -1181,7 +1175,7 @@ the following functions is support classic-can and can-fd.
- can_txbuf_write
- can_rxbuf_read
- can_filter_default_para_init
- - can_filter_set
+ - can_filter_set
- can_ttcan_txbuf_write
*/
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_cmp.h b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_cmp.h
index e0db2744a66..8a907de3e13 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_cmp.h
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_cmp.h
@@ -5,11 +5,11 @@
**************************************************************************
* Copyright notice & Disclaimer
*
- * The software Board Support Package (BSP) that is made available to
- * download from Artery official website is the copyrighted work of Artery.
- * Artery authorizes customers to use, copy, and distribute the BSP
- * software and its related documentation for the purpose of design and
- * development in conjunction with Artery microcontrollers. Use of the
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -141,7 +141,7 @@ typedef struct
* @brief type define cmp register all
*/
typedef struct
-{
+{
/**
* @brief cmp1 control and status register, offset:0x30
*/
@@ -161,7 +161,7 @@ typedef struct
__IO uint32_t cmphyst : 2; /* [17:16] */
__IO uint32_t reserved4 : 1; /* [18] */
__IO uint32_t cmpblanking : 7; /* [25:19] */
- __IO uint32_t reserved5 : 4; /* [29:26] */
+ __IO uint32_t reserved5 : 4; /* [29:26] */
__IO uint32_t cmpvalue : 1; /* [30] */
__IO uint32_t cmpwp : 1; /* [31] */
} cmp1_ctrlsts_bit;
@@ -225,7 +225,7 @@ typedef struct
__IO uint32_t cmphyst : 2; /* [17:16] */
__IO uint32_t reserved4 : 1; /* [18] */
__IO uint32_t cmpblanking : 7; /* [25:19] */
- __IO uint32_t reserved5 : 4; /* [29:26] */
+ __IO uint32_t reserved5 : 4; /* [29:26] */
__IO uint32_t cmpvalue : 1; /* [30] */
__IO uint32_t cmpwp : 1; /* [31] */
} cmp2_ctrlsts_bit;
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_crc.h b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_crc.h
index b149ad99cbc..7694e7ee7d7 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_crc.h
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_crc.h
@@ -83,7 +83,7 @@ typedef enum
typedef struct
{
/**
- * @brief crc dt register, offset:0x00
+ * @brief crc dt register, offset:0x00
*/
union
{
@@ -95,7 +95,7 @@ typedef struct
};
/**
- * @brief crc cdt register, offset:0x04
+ * @brief crc cdt register, offset:0x04
*/
union
{
@@ -108,7 +108,7 @@ typedef struct
};
/**
- * @brief crc ctrl register, offset:0x08
+ * @brief crc ctrl register, offset:0x08
*/
union
{
@@ -142,7 +142,7 @@ typedef struct
};
/**
- * @brief crc polynomial register, offset:0x14
+ * @brief crc polynomial register, offset:0x14
*/
union
{
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_crm.h b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_crm.h
index 6fa31bd651f..a5df9fd8d34 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_crm.h
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_crm.h
@@ -5,11 +5,11 @@
**************************************************************************
* Copyright notice & Disclaimer
*
- * The software Board Support Package (BSP) that is made available to
- * download from Artery official website is the copyrighted work of Artery.
- * Artery authorizes customers to use, copy, and distribute the BSP
- * software and its related documentation for the purpose of design and
- * development in conjunction with Artery microcontrollers. Use of the
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -41,15 +41,15 @@ extern "C" {
/** @addtogroup CRM
* @{
*/
-
+
#define CRM_REG(value) PERIPH_REG(CRM_BASE, value)
#define CRM_REG_BIT(value) PERIPH_REG_BIT(value)
-
+
/** @defgroup CRM_flags_definition
- * @brief crm flag
+ * @brief crm flag
* @{
*/
-
+
#define CRM_HICK_STABLE_FLAG MAKE_VALUE(0x00, 1) /*!< high speed internal clock stable flag */
#define CRM_HEXT_STABLE_FLAG MAKE_VALUE(0x00, 17) /*!< high speed external crystal stable flag */
#define CRM_PLL_STABLE_FLAG MAKE_VALUE(0x00, 25) /*!< phase locking loop stable flag */
@@ -73,12 +73,12 @@ extern "C" {
/**
* @}
*/
-
+
/** @defgroup CRM_interrupts_definition
- * @brief crm interrupt
+ * @brief crm interrupt
* @{
*/
-
+
#define CRM_LICK_STABLE_INT ((uint32_t)0x00000100) /*!< low speed internal clock stable interrupt */
#define CRM_LEXT_STABLE_INT ((uint32_t)0x00000200) /*!< low speed external crystal stable interrupt */
#define CRM_HICK_STABLE_INT ((uint32_t)0x00000400) /*!< high speed internal clock stable interrupt */
@@ -316,7 +316,7 @@ typedef enum
CRM_HEXT_SCLK_DIV_8 = 0x03, /*!< hext div8 to sysclk */
CRM_HEXT_SCLK_DIV_16 = 0x04, /*!< hext div16 to sysclk */
CRM_HEXT_SCLK_DIV_32 = 0x05 /*!< hext div32 to sysclk */
-} crm_hext_sclk_div_type;
+} crm_hext_sclk_div_type;
/**
* @brief crm hick to sysclk division
@@ -370,15 +370,6 @@ typedef enum
CRM_ERTC_CLOCK_HEXT_DIV_31 = 0x1F3 /*!< high speed external crystal div31 as ertc clock source */
} crm_ertc_clock_type;
-/**
- * @brief crm hick 48mhz division
- */
-typedef enum
-{
- CRM_HICK48_DIV6 = 0x00, /*!< fixed 8 mhz when hick is selected as sclk */
- CRM_HICK48_NODIV = 0x01 /*!< 8 mhz or 48 mhz depend on hickdiv when hick is selected as sclk */
-} crm_hick_div_6_type;
-
/**
* @brief crm sclk select
*/
@@ -930,8 +921,7 @@ typedef struct
struct
{
__IO uint32_t hickcal_key : 8; /* [7:0] */
- __IO uint32_t reserved1 : 4; /* [11:8] */
- __IO uint32_t hickdiv : 1; /* [12] */
+ __IO uint32_t reserved1 : 5; /* [12:8] */
__IO uint32_t reserved2 : 1; /* [13] */
__IO uint32_t hick_to_sclk : 1; /* [14] */
__IO uint32_t reserved3 : 1; /* [15] */
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_dac.h b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_dac.h
index 8eba9db8868..f8395389ff6 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_dac.h
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_dac.h
@@ -210,7 +210,7 @@ typedef struct
__IO uint32_t reserved3 : 2; /* [31:30] */
} sts_bit;
};
-
+
/**
* @brief dac sts register, offset:0x1c
*/
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_debug.h b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_debug.h
index 4a1fdc33910..70b9b7c83f1 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_debug.h
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_debug.h
@@ -56,12 +56,10 @@ extern "C" {
#define DEBUG_TMR4_PAUSE 0x00000004 /*!< debug timer4 pause */
#define DEBUG_TMR6_PAUSE 0x00000010 /*!< debug timer6 pause */
#define DEBUG_TMR7_PAUSE 0x00000020 /*!< debug timer7 pause */
-
#define DEBUG_WWDT_PAUSE 0x00000800 /*!< debug window watchdog timer pause */
#define DEBUG_WDT_PAUSE 0x00001000 /*!< debug watchdog timer pause */
#define DEBUG_I2C1_SMBUS_TIMEOUT 0x01000000 /*!< debug i2c1 smbus timeout */
#define DEBUG_I2C2_SMBUS_TIMEOUT 0x08000000 /*!< debug i2c2 smbus timeout */
-#define DEBUG_CAN1_PAUSE 0x02000000 /*!< debug can1 pause */
/* debug apb2 frz register bit */
#define DEBUG_TMR1_PAUSE 0x00000001 /*!< debug timer1 pause */
@@ -107,7 +105,7 @@ typedef struct
__IO uint32_t sleep_debug : 1;/* [0] */
__IO uint32_t deepsleep_debug : 1;/* [1] */
__IO uint32_t standby_debug : 1;/* [2] */
- __IO uint32_t reserved1 : 29;/* [31:3] */
+ __IO uint32_t reserved1 : 29;/* [31:3] */
} ctrl_bit;
};
@@ -130,8 +128,7 @@ typedef struct
__IO uint32_t wdt_pause : 1;/* [12] */
__IO uint32_t reserved4 : 11;/* [23:13] */
__IO uint32_t i2c1_smbus_timeout : 1;/* [24] */
- __IO uint32_t can1_pause : 1;/* [25] */
- __IO uint32_t reserved5 : 1;/* [26] */
+ __IO uint32_t reserved5 : 2;/* [26:25] */
__IO uint32_t i2c2_smbus_timeout : 1;/* [27] */
__IO uint32_t reserved6 : 4;/* [31:28] */
} apb1_frz_bit;
@@ -153,7 +150,7 @@ typedef struct
__IO uint32_t reserved2 : 13;/* [31:19] */
} apb2_frz_bit;
};
-
+
/**
* @brief debug apb3 frz register, offset:0x10
*/
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_def.h b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_def.h
index 06f76ac72ad..bd64b087785 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_def.h
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_def.h
@@ -5,11 +5,11 @@
**************************************************************************
* Copyright notice & Disclaimer
*
- * The software Board Support Package (BSP) that is made available to
- * download from Artery official website is the copyrighted work of Artery.
- * Artery authorizes customers to use, copy, and distribute the BSP
- * software and its related documentation for the purpose of design and
- * development in conjunction with Artery microcontrollers. Use of the
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_dma.h b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_dma.h
index 66d87fa935a..5d7634db614 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_dma.h
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_dma.h
@@ -120,7 +120,8 @@ typedef enum
{
DMA_DIR_PERIPHERAL_TO_MEMORY = 0x0000, /*!< dma data transfer direction: peripheral to memory */
DMA_DIR_MEMORY_TO_PERIPHERAL = 0x0010, /*!< dma data transfer direction: memory to peripheral */
- DMA_DIR_MEMORY_TO_MEMORY = 0x4000 /*!< dma data transfer direction: memory to memory */
+ DMA_DIR_MEMORY_TO_MEMORY = 0x4000 /*!< dma data transfer direction: memory to memory,
+ note:if the direction is memory to memory,peripheral_base_addr as source and memory_base_addr as destnation */
} dma_dir_type;
/**
@@ -165,8 +166,9 @@ typedef enum
DMAMUX_DMAREQ_ID_REQ_G3 = 0x03, /*!< dmamux channel dma request inputs resources: generator channel3 */
DMAMUX_DMAREQ_ID_REQ_G4 = 0x04, /*!< dmamux channel dma request inputs resources: generator channel4 */
DMAMUX_DMAREQ_ID_ADC1 = 0x05, /*!< dmamux channel dma request inputs resources: adc1 */
+ DMAMUX_DMAREQ_ID_ADC2 = 0x24, /*!< dmamux channel dma request inputs resources: adc2 */
DMAMUX_DMAREQ_ID_DAC1 = 0x06, /*!< dmamux channel dma request inputs resources: dac1 */
- DMAMUX_DMAREQ_ID_DAC2 = 0x29, /*!< dmamux channel dma request inputs resources: dac2 */
+ DMAMUX_DMAREQ_ID_DAC2 = 0x29, /*!< dmamux channel dma request inputs resources: dac2 */
DMAMUX_DMAREQ_ID_TMR6_OVERFLOW = 0x08, /*!< dmamux channel dma request inputs resources: timer6 overflow */
DMAMUX_DMAREQ_ID_TMR7_OVERFLOW = 0x09, /*!< dmamux channel dma request inputs resources: timer7 overflow */
DMAMUX_DMAREQ_ID_SPI1_RX = 0x0A, /*!< dmamux channel dma request inputs resources: spi1 rx */
@@ -187,7 +189,7 @@ typedef enum
DMAMUX_DMAREQ_ID_TMR1_CH4 = 0x2D, /*!< dmamux channel dma request inputs resources: timer1 ch4 */
DMAMUX_DMAREQ_ID_TMR1_OVERFLOW = 0x2E, /*!< dmamux channel dma request inputs resources: timer1 overflow */
DMAMUX_DMAREQ_ID_TMR1_TRIG = 0x2F, /*!< dmamux channel dma request inputs resources: timer1 trig */
- DMAMUX_DMAREQ_ID_TMR1_HALL = 0x30, /*!< dmamux channel dma request inputs resources: timer1 hall */
+ DMAMUX_DMAREQ_ID_TMR1_HALL = 0x30, /*!< dmamux channel dma request inputs resources: timer1 hall */
DMAMUX_DMAREQ_ID_TMR3_CH1 = 0x3D, /*!< dmamux channel dma request inputs resources: timer3 ch1 */
DMAMUX_DMAREQ_ID_TMR3_CH2 = 0x3E, /*!< dmamux channel dma request inputs resources: timer3 ch2 */
DMAMUX_DMAREQ_ID_TMR3_CH3 = 0x3F, /*!< dmamux channel dma request inputs resources: timer3 ch3 */
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_ertc.h b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_ertc.h
index aed3e5b9c42..8a795cd3a75 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_ertc.h
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_ertc.h
@@ -42,8 +42,8 @@ extern "C" {
* @{
*/
-/** @defgroup ERTC_interrupts_definition
- * @brief ertc interrupt
+/** @defgroup ERTC_interrupts_definition
+ * @brief ertc interrupt
* @{
*/
@@ -57,11 +57,11 @@ extern "C" {
* @}
*/
-/** @defgroup ERTC_flags_definition
- * @brief ertc flag
+/** @defgroup ERTC_flags_definition
+ * @brief ertc flag
* @{
*/
-
+
#define ERTC_ALAWF_FLAG ((uint32_t)0x00000001) /*!< ertc alarm a register allows write flag */
#define ERTC_ALBWF_FLAG ((uint32_t)0x00000002) /*!< ertc alarm b register allows write flag */
#define ERTC_WATWF_FLAG ((uint32_t)0x00000004) /*!< ertc wakeup timer register allows write flag */
@@ -91,11 +91,11 @@ extern "C" {
/**
* @}
*/
-
+
/** @defgroup ERTC_exported_types
* @{
*/
-
+
/**
* @brief ertc hour mode
*/
@@ -369,14 +369,14 @@ typedef enum
*/
typedef struct
{
- uint8_t year; /*!< year */
- uint8_t month; /*!< month */
- uint8_t day; /*!< date */
- uint8_t hour; /*!< hour */
- uint8_t min; /*!< minute */
- uint8_t sec; /*!< second */
- uint8_t week; /*!< week */
- ertc_am_pm_type ampm; /*!< ante meridiem / post meridiem */
+ uint8_t year; /*!< year */
+ uint8_t month; /*!< month */
+ uint8_t day; /*!< date */
+ uint8_t hour; /*!< hour */
+ uint8_t min; /*!< minute */
+ uint8_t sec; /*!< second */
+ uint8_t week; /*!< week */
+ ertc_am_pm_type ampm; /*!< ante meridiem / post meridiem */
} ertc_time_type;
/**
@@ -384,14 +384,14 @@ typedef struct
*/
typedef struct
{
- uint8_t day; /*!< date */
- uint8_t hour; /*!< hour */
- uint8_t min; /*!< minute */
- uint8_t sec; /*!< second */
- ertc_am_pm_type ampm; /*!< ante meridiem / post meridiem */
- uint32_t mask; /*!< alarm mask*/
- uint8_t week_date_sel; /*!< week or date mode */
- uint8_t week; /*!< week */
+ uint8_t day; /*!< date */
+ uint8_t hour; /*!< hour */
+ uint8_t min; /*!< minute */
+ uint8_t sec; /*!< second */
+ ertc_am_pm_type ampm; /*!< ante meridiem / post meridiem */
+ uint32_t mask; /*!< alarm mask*/
+ uint8_t week_date_sel; /*!< week or date mode */
+ uint8_t week; /*!< week */
} ertc_alarm_value_type;
/**
@@ -569,7 +569,7 @@ typedef struct
__IO uint32_t rcden :1; /* [4] */
__IO uint32_t dren :1; /* [5] */
__IO uint32_t hm :1; /* [6] */
- __IO uint32_t reserved0 :1; /* [7] */
+ __IO uint32_t reserved1 :1; /* [7] */
__IO uint32_t alaen :1; /* [8] */
__IO uint32_t alben :1; /* [9] */
__IO uint32_t waten :1; /* [10] */
@@ -585,7 +585,7 @@ typedef struct
__IO uint32_t outp :1; /* [20] */
__IO uint32_t outsel :2; /* [22:21] */
__IO uint32_t caloen :1; /* [23] */
- __IO uint32_t reserved1 :8; /* [31:24] */
+ __IO uint32_t reserved2 :8; /* [31:24] */
} ctrl_bit;
};
@@ -1100,12 +1100,12 @@ typedef struct
} ertc_type;
-
+
/**
* @}
*/
-#define ERTC ((ertc_type *) ERTC_BASE)
+#define ERTC ((ertc_type *) ERTC_BASE)
/** @defgroup ERTC_exported_functions
* @{
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_exint.h b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_exint.h
index 7bf84acfbd5..1259253ea4e 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_exint.h
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_exint.h
@@ -47,25 +47,25 @@ extern "C" {
*/
#define EXINT_LINE_NONE ((uint32_t)0x000000)
-#define EXINT_LINE_0 ((uint32_t)0x000001) /*!< external interrupt line 0 */
-#define EXINT_LINE_1 ((uint32_t)0x000002) /*!< external interrupt line 1 */
-#define EXINT_LINE_2 ((uint32_t)0x000004) /*!< external interrupt line 2 */
-#define EXINT_LINE_3 ((uint32_t)0x000008) /*!< external interrupt line 3 */
-#define EXINT_LINE_4 ((uint32_t)0x000010) /*!< external interrupt line 4 */
-#define EXINT_LINE_5 ((uint32_t)0x000020) /*!< external interrupt line 5 */
-#define EXINT_LINE_6 ((uint32_t)0x000040) /*!< external interrupt line 6 */
-#define EXINT_LINE_7 ((uint32_t)0x000080) /*!< external interrupt line 7 */
-#define EXINT_LINE_8 ((uint32_t)0x000100) /*!< external interrupt line 8 */
-#define EXINT_LINE_9 ((uint32_t)0x000200) /*!< external interrupt line 9 */
-#define EXINT_LINE_10 ((uint32_t)0x000400) /*!< external interrupt line 10 */
-#define EXINT_LINE_11 ((uint32_t)0x000800) /*!< external interrupt line 11 */
-#define EXINT_LINE_12 ((uint32_t)0x001000) /*!< external interrupt line 12 */
-#define EXINT_LINE_13 ((uint32_t)0x002000) /*!< external interrupt line 13 */
-#define EXINT_LINE_14 ((uint32_t)0x004000) /*!< external interrupt line 14 */
-#define EXINT_LINE_15 ((uint32_t)0x008000) /*!< external interrupt line 15 */
-#define EXINT_LINE_16 ((uint32_t)0x010000) /*!< external interrupt line 16 */
-#define EXINT_LINE_17 ((uint32_t)0x020000) /*!< external interrupt line 17 */
-#define EXINT_LINE_19 ((uint32_t)0x080000) /*!< external interrupt line 19 */
+#define EXINT_LINE_0 ((uint32_t)0x000001) /*!< external interrupt line 0 */
+#define EXINT_LINE_1 ((uint32_t)0x000002) /*!< external interrupt line 1 */
+#define EXINT_LINE_2 ((uint32_t)0x000004) /*!< external interrupt line 2 */
+#define EXINT_LINE_3 ((uint32_t)0x000008) /*!< external interrupt line 3 */
+#define EXINT_LINE_4 ((uint32_t)0x000010) /*!< external interrupt line 4 */
+#define EXINT_LINE_5 ((uint32_t)0x000020) /*!< external interrupt line 5 */
+#define EXINT_LINE_6 ((uint32_t)0x000040) /*!< external interrupt line 6 */
+#define EXINT_LINE_7 ((uint32_t)0x000080) /*!< external interrupt line 7 */
+#define EXINT_LINE_8 ((uint32_t)0x000100) /*!< external interrupt line 8 */
+#define EXINT_LINE_9 ((uint32_t)0x000200) /*!< external interrupt line 9 */
+#define EXINT_LINE_10 ((uint32_t)0x000400) /*!< external interrupt line 10 */
+#define EXINT_LINE_11 ((uint32_t)0x000800) /*!< external interrupt line 11 */
+#define EXINT_LINE_12 ((uint32_t)0x001000) /*!< external interrupt line 12 */
+#define EXINT_LINE_13 ((uint32_t)0x002000) /*!< external interrupt line 13 */
+#define EXINT_LINE_14 ((uint32_t)0x004000) /*!< external interrupt line 14 */
+#define EXINT_LINE_15 ((uint32_t)0x008000) /*!< external interrupt line 15 */
+#define EXINT_LINE_16 ((uint32_t)0x010000) /*!< external interrupt line 16 */
+#define EXINT_LINE_17 ((uint32_t)0x020000) /*!< external interrupt line 17 */
+#define EXINT_LINE_19 ((uint32_t)0x080000) /*!< external interrupt line 19 */
#define EXINT_LINE_20 ((uint32_t)0x100000) /*!< external interrupt line 20 */
#define EXINT_LINE_21 ((uint32_t)0x200000) /*!< external interrupt line 21 */
#define EXINT_LINE_22 ((uint32_t)0x400000) /*!< external interrupt line 22 */
@@ -79,7 +79,7 @@ extern "C" {
*/
/**
- * @brief exint line mode type
+ * @brief exint line mode type
*/
typedef enum
{
@@ -89,7 +89,7 @@ typedef enum
} exint_line_mode_type;
/**
- * @brief exint polarity configuration type
+ * @brief exint polarity configuration type
*/
typedef enum
{
@@ -98,7 +98,7 @@ typedef enum
EXINT_TRIGGER_BOTH_EDGE = 0x02 /*!< external interrupt line both rising and falling trigger mode */
} exint_polarity_config_type;
-/**
+/**
* @brief exint init type
*/
typedef struct
@@ -113,10 +113,10 @@ typedef struct
* @brief type define exint register all
*/
typedef struct
-{
-
+{
+
/**
- * @brief exint inten register, offset:0x00
+ * @brief exint inten register, offset:0x00
*/
union
{
@@ -127,9 +127,9 @@ typedef struct
__IO uint32_t reserved1 : 9; /* [31:23] */
} inten_bit;
};
-
+
/**
- * @brief exint evten register, offset:0x04
+ * @brief exint evten register, offset:0x04
*/
union
{
@@ -140,9 +140,9 @@ typedef struct
__IO uint32_t reserved1 : 9; /* [31:23] */
} evten_bit;
};
-
+
/**
- * @brief exint polcfg1 register, offset:0x08
+ * @brief exint polcfg1 register, offset:0x08
*/
union
{
@@ -153,9 +153,9 @@ typedef struct
__IO uint32_t reserved1 : 9; /* [31:23] */
} polcfg1_bit;
};
-
+
/**
- * @brief exint polcfg2 register, offset:0x0C
+ * @brief exint polcfg2 register, offset:0x0C
*/
union
{
@@ -165,10 +165,10 @@ typedef struct
__IO uint32_t fpx : 23;/* [22:0] */
__IO uint32_t reserved1 : 9; /* [31:23] */
} polcfg2_bit;
- };
-
+ };
+
/**
- * @brief exint swtrg register, offset:0x10
+ * @brief exint swtrg register, offset:0x10
*/
union
{
@@ -179,9 +179,9 @@ typedef struct
__IO uint32_t reserved1 : 9; /* [31:23] */
} swtrg_bit;
};
-
+
/**
- * @brief exint intsts register, offset:0x14
+ * @brief exint intsts register, offset:0x14
*/
union
{
@@ -191,14 +191,14 @@ typedef struct
__IO uint32_t linex : 23;/* [22:0] */
__IO uint32_t reserved1 : 9; /* [31:23] */
} intsts_bit;
- };
-} exint_type;
+ };
+} exint_type;
/**
* @}
*/
-
-#define EXINT ((exint_type *) EXINT_BASE)
+
+#define EXINT ((exint_type *) EXINT_BASE)
/** @defgroup EXINT_exported_functions
* @{
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_flash.h b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_flash.h
index e1cb58ffe83..43cd4b6e208 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_flash.h
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_flash.h
@@ -5,11 +5,11 @@
**************************************************************************
* Copyright notice & Disclaimer
*
- * The software Board Support Package (BSP) that is made available to
- * download from Artery official website is the copyrighted work of Artery.
- * Artery authorizes customers to use, copy, and distribute the BSP
- * software and its related documentation for the purpose of design and
- * development in conjunction with Artery microcontrollers. Use of the
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -29,8 +29,8 @@
#ifdef __cplusplus
extern "C" {
#endif
-
-
+
+
/* Includes ------------------------------------------------------------------*/
#include "at32m412_416.h"
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_gpio.h b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_gpio.h
index ab23304f6ec..67b7ff34afa 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_gpio.h
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_gpio.h
@@ -45,7 +45,7 @@ extern "C" {
/** @defgroup GPIO_pins_number_definition
* @{
*/
-
+
#define GPIO_PINS_0 0x0001 /*!< gpio pins number 0 */
#define GPIO_PINS_1 0x0002 /*!< gpio pins number 1 */
#define GPIO_PINS_2 0x0004 /*!< gpio pins number 2 */
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_i2c.h b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_i2c.h
index 6dfff05b040..6faa1cbfed2 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_i2c.h
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_i2c.h
@@ -5,11 +5,11 @@
**************************************************************************
* Copyright notice & Disclaimer
*
- * The software Board Support Package (BSP) that is made available to
- * download from Artery official website is the copyrighted work of Artery.
- * Artery authorizes customers to use, copy, and distribute the BSP
- * software and its related documentation for the purpose of design and
- * development in conjunction with Artery microcontrollers. Use of the
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -41,34 +41,34 @@ extern "C" {
/** @addtogroup I2C
* @{
*/
-
+
/**
* @brief maximum number of single transfers
*/
-#define MAX_TRANSFER_CNT 255 /*!< maximum number of single transfers */
+#define MAX_TRANSFER_CNT 255 /*!< maximum number of single transfers */
/** @defgroup I2C_interrupts_definition
* @brief i2c interrupt
* @{
*/
-
-#define I2C_TD_INT ((uint32_t)0x00000002) /*!< i2c transmit data interrupt */
-#define I2C_RD_INT ((uint32_t)0x00000004) /*!< i2c receive data interrupt */
+
+#define I2C_TD_INT ((uint32_t)0x00000002) /*!< i2c transmit data interrupt */
+#define I2C_RD_INT ((uint32_t)0x00000004) /*!< i2c receive data interrupt */
#define I2C_ADDR_INT ((uint32_t)0x00000008) /*!< i2c address match interrupt */
#define I2C_ACKFIAL_INT ((uint32_t)0x00000010) /*!< i2c ack fail interrupt */
#define I2C_STOP_INT ((uint32_t)0x00000020) /*!< i2c stop detect interrupt */
#define I2C_TDC_INT ((uint32_t)0x00000040) /*!< i2c transmit data complete interrupt */
-#define I2C_ERR_INT ((uint32_t)0x00000080) /*!< i2c bus error interrupt */
+#define I2C_ERR_INT ((uint32_t)0x00000080) /*!< i2c bus error interrupt */
/**
* @}
*/
-
+
/** @defgroup I2C_flags_definition
* @brief i2c flag
* @{
*/
-
+
#define I2C_TDBE_FLAG ((uint32_t)0x00000001) /*!< i2c transmit data buffer empty flag */
#define I2C_TDIS_FLAG ((uint32_t)0x00000002) /*!< i2c send interrupt status */
#define I2C_RDBF_FLAG ((uint32_t)0x00000004) /*!< i2c receive data buffer full flag */
@@ -93,7 +93,7 @@ extern "C" {
/** @defgroup I2C_exported_types
* @{
*/
-
+
/**
* @brief i2c smbus mode set
*/
@@ -135,7 +135,7 @@ typedef enum
*/
typedef enum
{
- I2C_SMBUS_ALERT_HIGH = 0x00, /*!< smbus alert pin set high */
+ I2C_SMBUS_ALERT_HIGH = 0x00, /*!< smbus alert pin set high */
I2C_SMBUS_ALERT_LOW = 0x01 /*!< smbus alert pin set low */
} i2c_smbus_alert_set_type;
@@ -144,7 +144,7 @@ typedef enum
*/
typedef enum
{
- I2C_TIMEOUT_DETCET_LOW = 0x00, /*!< detect low level timeout */
+ I2C_TIMEOUT_DETCET_LOW = 0x00, /*!< detect low level timeout */
I2C_TIMEOUT_DETCET_HIGH = 0x01 /*!< detect high level timeout */
} i2c_timeout_detcet_type;
@@ -168,9 +168,9 @@ typedef enum
*/
typedef enum
{
- I2C_AUTO_STOP_MODE = 0x02000000, /*!< auto generate stop mode */
- I2C_SOFT_STOP_MODE = 0x00000000, /*!< soft generate stop mode */
- I2C_RELOAD_MODE = 0x01000000 /*!< reload mode */
+ I2C_AUTO_STOP_MODE = 0x02000000, /*!< auto generate stop mode */
+ I2C_SOFT_STOP_MODE = 0x00000000, /*!< soft generate stop mode */
+ I2C_RELOAD_MODE = 0x01000000 /*!< reload mode */
} i2c_reload_stop_mode_type;
/**
@@ -189,7 +189,7 @@ typedef enum
typedef struct
{
/**
- * @brief i2c ctrl1 register, offset:0x00
+ * @brief i2c ctrl1 register, offset:0x00
*/
union
{
@@ -221,7 +221,7 @@ typedef struct
};
/**
- * @brief i2c ctrl2 register, offset:0x04
+ * @brief i2c ctrl2 register, offset:0x04
*/
union
{
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_misc.h b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_misc.h
index 32b20f76696..a66dcba07e6 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_misc.h
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_misc.h
@@ -5,11 +5,11 @@
**************************************************************************
* Copyright notice & Disclaimer
*
- * The software Board Support Package (BSP) that is made available to
- * download from Artery official website is the copyrighted work of Artery.
- * Artery authorizes customers to use, copy, and distribute the BSP
- * software and its related documentation for the purpose of design and
- * development in conjunction with Artery microcontrollers. Use of the
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_op.h b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_op.h
index 6d2d1a7e162..ef01f30808c 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_op.h
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_op.h
@@ -21,7 +21,7 @@
*
**************************************************************************
*/
-
+
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AT32M412_416_OP_H
#define __AT32M412_416_OP_H
@@ -40,27 +40,27 @@ extern "C" {
/** @addtogroup OP
* @{
*/
-
+
/** @defgroup op_functional_mode_definition
* @brief op functional mode
* @{
*/
-
+
#define OP_FUNCTIONAL_MODE_MASK ((uint32_t)0x00060860) /*!< op functional mode mask */
typedef enum
{
OP_STANDALONE_MODE = ((uint32_t)0x00000000), /*!< op functional mode, in standalone */
- OP_FOLLOWER_MODE = ((uint32_t)0x00000060), /*!< op functional mode, in follower mode and vm_sel[1:0]=0x3 */
- OP_PGA_MODE = ((uint32_t)0x00000040), /*!< op functional mode, in pga mode and vm_sel[1:0]=0x2 */
- OP_PGA_VINM0_MODE = ((uint32_t)0x00040040), /*!< op functional mode, in pga mode and the inverting input is connected to vinm0 for filtering */
- OP_PGA_VINM0_BIAS_MODE = ((uint32_t)0x00020040), /*!< op functional mode, in pga mode and the inverting input is connected to vinm0
- - input signal on vinm0, bias on vinpx: negative gain
- - bias on vinm0, input signal on vinpx: positive gain */
- OP_PGA_VINM0_VINM1_BIAS_MODE = ((uint32_t)0x00060040), /*!< op functional mode, in pga mode and the inverting input is connected to vinm0
- - input signal on vinm0, bias on vinpx: negative gain
- - bias on vinm0, input signal on vinpx: positive gain
- and vinm1 is connected to for filtering */
+ OP_FOLLOWER_MODE = ((uint32_t)0x00000060), /*!< op functional mode, in follower mode and inmsel[1:0]=0x3 */
+ OP_PGA_MODE = ((uint32_t)0x00000040), /*!< op functional mode, in pga mode and inmsel[1:0]=0x2 */
+ OP_PGA_INM0_MODE = ((uint32_t)0x00040040), /*!< op functional mode, in pga mode and the inverting input is connected to inm0 for filtering */
+ OP_PGA_INM0_BIAS_MODE = ((uint32_t)0x00020040), /*!< op functional mode, in pga mode and the inverting input is connected to inm0
+ - input signal on inm0, bias on inpx: negative gain
+ - bias on inm0, input signal on inpx: positive gain */
+ OP_PGA_INM0_INM1_BIAS_MODE = ((uint32_t)0x00060040), /*!< op functional mode, in pga mode and the inverting input is connected to inm0
+ - input signal on inm0, bias on inpx: negative gain
+ - bias on inm0, input signal on inpx: positive gain
+ and inm1 is connected to for filtering */
} op_functional_mode_type;
/**
* @}
@@ -96,36 +96,36 @@ typedef enum
OP_FUNCTIONAL_MODE = 0x00, /*!< op functional mode */
OP_CALIBRATION_MODE = 0x01, /*!< op calibration mode */
} op_mode_type;
-
+
/**
* @}
- */
-
+ */
+
/**
* @brief op non-inverting input connection
*/
typedef enum
{
- OP_NON_INVERTING_INPUT_VP0 = 0x00, /*!< vinp0 pin connected to op vinp input */
- OP_NON_INVERTING_INPUT_VP1 = 0x01, /*!< vinp1 pin connected to op vinp input */
- OP_NON_INVERTING_INPUT_VP2 = 0x02, /*!< vinp2 pin connected to op vinp input */
- OP_NON_INVERTING_INPUT_VP3 = 0x03, /*!< vinp3 pin connected to op vinp input */
+ OP_NON_INVERTING_INPUT_INP0 = 0x00, /*!< vinp0 pin connected to op inp input */
+ OP_NON_INVERTING_INPUT_INP1 = 0x01, /*!< vinp1 pin connected to op inp input */
+ OP_NON_INVERTING_INPUT_INP2 = 0x02, /*!< vinp2 pin connected to op inp input */
+ OP_NON_INVERTING_INPUT_INP3 = 0x03, /*!< vinp3 pin connected to op inp input */
} op_non_inverting_input_type;
-
+
/**
* @}
- */
-
+ */
+
/**
* @brief op inverting input connection
*/
typedef enum
{
- OP_INVERTING_INPUT_VM0 = 0x00, /*!< vinm0 pin connected to op vinm input */
- OP_INVERTING_INPUT_VM1 = 0x01, /*!< vinm1 pin connected to op vinm input */
+ OP_INVERTING_INPUT_INM0 = 0x00, /*!< vinm0 pin connected to op inm input */
+ OP_INVERTING_INPUT_INM1 = 0x01, /*!< vinm1 pin connected to op inm input */
OP_INVERTING_INPUT_NONE = 0x02, /*!< none pin connected to op vinm input,pga mode or follower mode */
} op_inverting_input_type;
-
+
/**
* @}
*/
@@ -138,10 +138,10 @@ typedef enum
OP_INTERNAL_OUTPUT_GPIO = 0x00, /*!< the op output is connected to the output pin */
OP_INTERNAL_OUTPUT_ADC = 0x01, /*!< the op output is connected internally to an adc channel */
} op_internal_output_type;
-
+
/**
* @}
- */
+ */
/**
* @brief op trimming mode select
@@ -151,10 +151,10 @@ typedef enum
OP_TRIMMING_FACTORY = 0x00, /*!< factory trim code used */
OP_TRIMMING_USER = 0x01, /*!< user trim code used */
} op_trimming_type;
-
+
/**
* @}
- */
+ */
/**
* @brief op calibrate select
@@ -166,7 +166,7 @@ typedef enum
OP_TRIMMING_50VDDA = 0x02, /*!< 0.5*vdda applied on op inputs */
OP_TRIMMING_NMOS = 0x03, /*!< 0.9*vdda applied on op inputs (for nmos calibration) */
} op_calibrate_type;
-
+
/**
* @}
*/
@@ -179,11 +179,11 @@ typedef enum
OP_WPC_CTRL = 0x00, /*!< op ctrl register write protected */
OP_WPC_TC = 0x01, /*!< op tc register write protected */
} op_wpc_type;
-
+
/**
* @}
- */
-
+ */
+
typedef struct
{
/**
@@ -196,9 +196,9 @@ typedef struct
{
__IO uint32_t open : 1; /* [0] */
__IO uint32_t vrfsel : 1; /* [1] */
- __IO uint32_t vpsel : 2; /* [3:2] */
+ __IO uint32_t inpsel : 2; /* [3:2] */
__IO uint32_t usertrim : 1; /* [4] */
- __IO uint32_t vmsel : 2; /* [6:5] */
+ __IO uint32_t inmsel : 2; /* [6:5] */
__IO uint32_t opfstmd : 1; /* [7] */
__IO uint32_t opoutsel : 1; /* [8] */
__IO uint32_t reserved1 : 2; /* [10:9] */
@@ -212,12 +212,12 @@ typedef struct
__IO uint32_t wpc : 1; /* [31] */
} ctrl_bit;
};
-
+
/**
* @brief reserved, offset:0x04~0x14
*/
__IO uint32_t reserved1[5];
-
+
/**
* @brief op tcmr register, offset:0x18
*/
@@ -226,17 +226,17 @@ typedef struct
__IO uint32_t tc;
struct
{
- __IO uint32_t vmssel : 1; /* [0] */
- __IO uint32_t vpssel : 2; /* [2:1] */
+ __IO uint32_t inmssel : 1; /* [0] */
+ __IO uint32_t inpssel : 2; /* [2:1] */
__IO uint32_t tmr1en : 1; /* [3] */
__IO uint32_t reserved1 : 27; /* [30:4] */
__IO uint32_t wpc : 1; /* [31] */
} tc_bit;
};
-
-}op_type;
-
-
+
+}op_type;
+
+
#define OP1 ((op_type*)OP1_BASE)
#define OP2 ((op_type*)OP2_BASE)
#define OP3 ((op_type*)OP3_BASE)
@@ -244,7 +244,7 @@ typedef struct
void op_enable(op_type *op_x, confirm_state new_state);
void op_set_mode(op_type *op_x, op_mode_type mode);
-void op_set_functional_mode(op_type *op_x, op_functional_mode_type functional_mode);
+void op_set_functional_mode(op_type *op_x, op_functional_mode_type functional_mode);
void op_set_gain(op_type *op_x, op_gain_type gain);
void op_set_highspeed_mode_enable(op_type *op_x, confirm_state new_state);
void op_set_input_non_inverting(op_type *op_x, op_non_inverting_input_type non_inverting_input);
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_scfg.h b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_scfg.h
index ef54ce18bfc..761888a0e74 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_scfg.h
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_scfg.h
@@ -123,7 +123,7 @@ typedef enum
SCFG_PINS_SOURCE12 = 0x0C,
SCFG_PINS_SOURCE13 = 0x0D,
SCFG_PINS_SOURCE14 = 0x0E,
- SCFG_PINS_SOURCE15 = 0x0F
+ SCFG_PINS_SOURCE15 = 0x0F
} scfg_pins_source_type;
/**
@@ -353,5 +353,5 @@ void scfg_nrst_rmp_config(scfg_nrst_rmp_type remap);
#ifdef __cplusplus
}
#endif
-
+
#endif
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_spi.h b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_spi.h
index 6d53e249bb3..285377a9353 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_spi.h
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_spi.h
@@ -424,7 +424,7 @@ typedef struct
__IO uint32_t i2smsel : 1; /* [11] */
__IO uint32_t reserved2 : 20;/* [31:12] */
} i2sctrl_bit;
- };
+ };
/**
* @brief spi i2sclk register, offset:0x20
@@ -440,8 +440,8 @@ typedef struct
__IO uint32_t i2sdiv_h : 2; /* [11:10] */
__IO uint32_t reserved1 : 20;/* [31:12] */
} i2sclk_bit;
- };
-} spi_type;
+ };
+} spi_type;
/**
* @}
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_tmr.h b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_tmr.h
index 2cfe8bf2008..8249e55b9c5 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_tmr.h
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_tmr.h
@@ -42,11 +42,11 @@ extern "C" {
* @{
*/
-/** @defgroup TMR_flags_definition
- * @brief tmr flag
+/** @defgroup TMR_flags_definition
+ * @brief tmr flag
* @{
*/
-
+
#define TMR_OVF_FLAG ((uint32_t)0x000001) /*!< tmr flag overflow */
#define TMR_C1_FLAG ((uint32_t)0x000002) /*!< tmr flag channel 1 */
#define TMR_C2_FLAG ((uint32_t)0x000004) /*!< tmr flag channel 2 */
@@ -68,7 +68,7 @@ extern "C" {
* @}
*/
-/** @defgroup TMR_interrupt_select_type_definition
+/** @defgroup TMR_interrupt_select_type_definition
* @brief tmr interrupt select type
* @{
*/
@@ -86,11 +86,11 @@ extern "C" {
* @}
*/
-/** @defgroup tmr_ch5_combined_type_definition
+/** @defgroup tmr_ch5_combined_type_definition
* @brief tmr channel5 combined type
* @{
*/
-
+
#define TMR_CH5_COMBINED_NONE ((uint32_t)0x00000000) /*!< no effect of c5oraw on c1oraw, c2oraw and c3oraw */
#define TMR_CH5_COMBINED_C1ORAW ((uint32_t)0x20000000) /*!< c1oraw is the logical and of c1oraw and c5oraw */
#define TMR_CH5_COMBINED_C2ORAW ((uint32_t)0x40000000) /*!< c2oraw is the logical and of c2oraw and c5oraw */
@@ -100,7 +100,7 @@ extern "C" {
* @}
*/
-/** @defgroup tmr_input_channel_select_type_definition
+/** @defgroup tmr_input_channel_select_type_definition
* @brief tmr input channel select type
* @{
*/
@@ -169,7 +169,7 @@ extern "C" {
*/
/**
- * @brief tmr clock division type
+ * @brief tmr clock division type
*/
typedef enum
{
@@ -179,7 +179,7 @@ typedef enum
} tmr_clock_division_type;
/**
- * @brief tmr counter mode type
+ * @brief tmr counter mode type
*/
typedef enum
{
@@ -191,7 +191,7 @@ typedef enum
} tmr_count_mode_type;
/**
- * @brief tmr primary mode select type
+ * @brief tmr primary mode select type
*/
typedef enum
{
@@ -214,7 +214,7 @@ typedef enum
} tmr_primary_select_type;
/**
- * @brief tmr subordinate mode input select type
+ * @brief tmr subordinate mode input select type
*/
typedef enum
{
@@ -229,7 +229,7 @@ typedef enum
} sub_tmr_input_sel_type;
/**
- * @brief tmr subordinate mode select type
+ * @brief tmr subordinate mode select type
*/
typedef enum
{
@@ -245,7 +245,7 @@ typedef enum
} tmr_sub_mode_select_type;
/**
- * @brief tmr encoder mode type
+ * @brief tmr encoder mode type
*/
typedef enum
{
@@ -255,7 +255,7 @@ typedef enum
} tmr_encoder_mode_type;
/**
- * @brief tmr output control mode type
+ * @brief tmr output control mode type
*/
typedef enum
{
@@ -344,7 +344,7 @@ typedef enum
} tmr_input_direction_mapped_type;
/**
- * @brief tmr input divider type
+ * @brief tmr input divider type
*/
typedef enum
{
@@ -355,7 +355,7 @@ typedef enum
} tmr_channel_input_divider_type;
/**
- * @brief tmr dma request source select type
+ * @brief tmr dma request source select type
*/
typedef enum
{
@@ -364,7 +364,7 @@ typedef enum
} tmr_dma_request_source_type;
/**
- * @brief tmr dma request type
+ * @brief tmr dma request type
*/
typedef enum
{
@@ -378,7 +378,7 @@ typedef enum
} tmr_dma_request_type;
/**
- * @brief tmr event triggered by software type
+ * @brief tmr event triggered by software type
*/
typedef enum
{
@@ -394,7 +394,7 @@ typedef enum
}tmr_event_trigger_type;
/**
- * @brief tmr channel output fast type
+ * @brief tmr channel output fast type
*/
typedef enum
{
@@ -405,7 +405,7 @@ typedef enum
}tmr_channel_output_fast_type;
/**
- * @brief tmr polarity active type
+ * @brief tmr polarity active type
*/
typedef enum
{
@@ -415,7 +415,7 @@ typedef enum
}tmr_polarity_active_type;
/**
- * @brief tmr external signal divider type
+ * @brief tmr external signal divider type
*/
typedef enum
{
@@ -426,7 +426,7 @@ typedef enum
}tmr_external_signal_divider_type;
/**
- * @brief tmr external signal polarity type
+ * @brief tmr external signal polarity type
*/
typedef enum
{
@@ -435,7 +435,7 @@ typedef enum
}tmr_external_signal_polarity_type;
/**
- * @brief tmr dma transfer length type
+ * @brief tmr dma transfer length type
*/
typedef enum
{
@@ -460,7 +460,7 @@ typedef enum
}tmr_dma_transfer_length_type;
/**
- * @brief tmr dma base address type
+ * @brief tmr dma base address type
*/
typedef enum
{
@@ -486,7 +486,7 @@ typedef enum
}tmr_dma_address_type;
/**
- * @brief tmr brk polarity type
+ * @brief tmr brk polarity type
*/
typedef enum
{
@@ -504,7 +504,7 @@ typedef enum
}tmr_blk_state_type;
/**
- * @brief tmr blanking source polarity type
+ * @brief tmr blanking source polarity type
*/
typedef enum
{
@@ -513,28 +513,28 @@ typedef enum
}tmr_blk_source_polarity_type;
/**
- * @brief tmr blanking source select type
+ * @brief tmr blanking source select type
*/
typedef enum
{
- TMR_BLK_SOURCE_0 = 0x00, /*!< tmr blanking source 0 */
+ TMR_BLK_SOURCE_0 = 0x00, /*!< tmr blanking source 0 */
TMR_BLK_SOURCE_1 = 0x01, /*!< tmr blanking source 1 */
TMR_BLK_SOURCE_2 = 0x02, /*!< tmr blanking source 2 */
TMR_BLK_SOURCE_3 = 0x03 /*!< tmr blanking source 3 */
}tmr_blk_source_type;
/**
- * @brief tmr write protect level type
+ * @brief tmr write protect level type
*/
typedef enum
{
- TMR_WP_OFF = 0x00, /*!< tmr write protect off */
+ TMR_WP_OFF = 0x00, /*!< tmr write protect off */
TMR_WP_LEVEL_3 = 0x01, /*!< tmr write protect level 3 */
TMR_WP_LEVEL_2 = 0x02, /*!< tmr write protect level 2 */
TMR_WP_LEVEL_1 = 0x03 /*!< tmr write protect level 1 */
}tmr_wp_level_type;
-/**
+/**
* @brief tmr coraw clear input source
*/
typedef enum
@@ -544,7 +544,7 @@ typedef enum
TMR_CORAW_CLR_EXT = 0x02 /*!< tmr cxoraw clear input from ext */
}tmr_coraw_clear_type;
-/**
+/**
* @brief tmr brake selection
*/
typedef enum
@@ -553,7 +553,7 @@ typedef enum
TMR_BRK_SELECT_2 = 0x02 /*!< tmr brake select 2 */
}tmr_brk_type;
-/**
+/**
* @brief tmr brake selection
*/
typedef enum
@@ -564,7 +564,7 @@ typedef enum
}tmr_brkin_src_type;
/**
- * @brief tmr brk polarity type
+ * @brief tmr brk polarity type
*/
typedef enum
{
@@ -573,7 +573,7 @@ typedef enum
}tmr_brkin_pol_type;
/**
- * @brief tmr brk polarity type
+ * @brief tmr brk polarity type
*/
typedef enum
{
@@ -587,7 +587,7 @@ typedef enum
}tmr_ext_source_type;
/**
- * @brief tmr brk polarity status
+ * @brief tmr brk polarity status
*/
typedef enum
{
@@ -597,21 +597,21 @@ typedef enum
/**
- * @brief tmr output config type
+ * @brief tmr output config type
*/
typedef struct
{
tmr_output_control_mode_type oc_mode; /*!< output channel mode */
confirm_state oc_idle_state; /*!< output channel idle state */
- confirm_state occ_idle_state; /*!< output channel complementary idle state */
- tmr_output_polarity_type oc_polarity; /*!< output channel polarity */
- tmr_output_polarity_type occ_polarity; /*!< output channel complementary polarity */
- confirm_state oc_output_state; /*!< output channel enable */
- confirm_state occ_output_state; /*!< output channel complementary enable */
+ confirm_state occ_idle_state; /*!< output channel complementary idle state */
+ tmr_output_polarity_type oc_polarity; /*!< output channel polarity */
+ tmr_output_polarity_type occ_polarity; /*!< output channel complementary polarity */
+ confirm_state oc_output_state; /*!< output channel enable */
+ confirm_state occ_output_state; /*!< output channel complementary enable */
} tmr_output_config_type;
-/**
- * @brief tmr input capture config type
+/**
+ * @brief tmr input capture config type
*/
typedef struct
{
@@ -621,7 +621,7 @@ typedef struct
uint8_t input_filter_value; /*!< tmr channel filter value */
} tmr_input_config_type;
-/**
+/**
* @brief tmr brkdt config type
*/
typedef struct
@@ -629,13 +629,13 @@ typedef struct
uint8_t deadtime; /*!< dead-time generator setup */
tmr_brk_polarity_type brk_polarity; /*!< tmr brk polarity */
tmr_wp_level_type wp_level; /*!< write protect configuration */
- confirm_state auto_output_enable; /*!< automatic output enable */
+ confirm_state auto_output_enable; /*!< automatic output enable */
confirm_state fcsoen_state; /*!< frozen channel status when output enable */
confirm_state fcsodis_state; /*!< frozen channel status when output disable */
confirm_state brk_enable; /*!< tmr brk enale */
} tmr_brkdt_config_type;
-/**
+/**
* @brief tmr brk2 config type
*/
typedef struct
@@ -645,7 +645,7 @@ typedef struct
uint8_t brk2_filter; /*!< tmr brk2 filter */
} tmr_brk2_config_type;
-/**
+/**
* @brief tmr blanking config type
*/
typedef struct
@@ -674,13 +674,13 @@ typedef struct
typedef struct
{
/**
- * @brief tmr ctrl1 register, offset:0x00
+ * @brief tmr ctrl1 register, offset:0x00
*/
union
{
__IO uint32_t ctrl1;
struct
- {
+ {
__IO uint32_t tmren : 1; /* [0] */
__IO uint32_t ovfen : 1; /* [1] */
__IO uint32_t ovfs : 1; /* [2] */
@@ -695,7 +695,7 @@ typedef struct
};
/**
- * @brief tmr ctrl2 register, offset:0x04
+ * @brief tmr ctrl2 register, offset:0x04
*/
union
{
@@ -728,7 +728,7 @@ typedef struct
};
/**
- * @brief tmr smc register, offset:0x08
+ * @brief tmr smc register, offset:0x08
*/
union
{
@@ -753,7 +753,7 @@ typedef struct
*/
union
{
- __IO uint32_t iden;
+ __IO uint32_t iden;
struct
{
__IO uint32_t ovfien : 1; /* [0] */
@@ -776,7 +776,7 @@ typedef struct
};
/**
- * @brief tmr ists register, offset:0x10
+ * @brief tmr ists register, offset:0x10
*/
union
{
@@ -805,7 +805,7 @@ typedef struct
};
/**
- * @brief tmr eveg register, offset:0x14
+ * @brief tmr eveg register, offset:0x14
*/
union
{
@@ -826,12 +826,12 @@ typedef struct
};
/**
- * @brief tmr ccm1 register, offset:0x18
+ * @brief tmr ccm1 register, offset:0x18
*/
union
{
__IO uint32_t cm1;
-
+
/**
* @brief channel mode
*/
@@ -844,15 +844,15 @@ typedef struct
__IO uint32_t c1osen : 1; /* [7] */
__IO uint32_t c2c : 2; /* [9:8] */
__IO uint32_t c2oien : 1; /* [10] */
- __IO uint32_t c2oben : 1; /* [11] */
- __IO uint32_t c2octrl : 3; /* [14:12] */
+ __IO uint32_t c2oben : 1; /* [11] */
+ __IO uint32_t c2octrl : 3; /* [14:12] */
__IO uint32_t c2osen : 1; /* [15] */
__IO uint32_t c1octrl_3 : 1; /* [16] */
__IO uint32_t reserved1 : 7; /* [23:17] */
__IO uint32_t c2octrl_3 : 1; /* [24] */
__IO uint32_t reserved2 : 7; /* [31:25] */
} cm1_output_bit;
-
+
/**
* @brief input capture mode
*/
@@ -869,12 +869,12 @@ typedef struct
};
/**
- * @brief tmr ccm2 register, offset:0x1C
+ * @brief tmr ccm2 register, offset:0x1C
*/
union
{
__IO uint32_t cm2;
-
+
/**
* @brief channel mode
*/
@@ -887,8 +887,8 @@ typedef struct
__IO uint32_t c3osen : 1; /* [7] */
__IO uint32_t c4c : 2; /* [9:8] */
__IO uint32_t c4oien : 1; /* [10] */
- __IO uint32_t c4oben : 1; /* [11] */
- __IO uint32_t c4octrl : 3; /* [14:12] */
+ __IO uint32_t c4oben : 1; /* [11] */
+ __IO uint32_t c4octrl : 3; /* [14:12] */
__IO uint32_t c4osen : 1; /* [15] */
__IO uint32_t c3octrl_3 : 1; /* [16] */
__IO uint32_t reserved1 : 7; /* [23:17] */
@@ -912,7 +912,7 @@ typedef struct
};
/**
- * @brief tmr cce register, offset:0x20
+ * @brief tmr cce register, offset:0x20
*/
union
{
@@ -945,7 +945,7 @@ typedef struct
};
/**
- * @brief tmr cnt register, offset:0x24
+ * @brief tmr cnt register, offset:0x24
*/
union
{
@@ -959,7 +959,7 @@ typedef struct
};
/**
- * @brief tmr div, offset:0x28
+ * @brief tmr div, offset:0x28
*/
union
{
@@ -972,7 +972,7 @@ typedef struct
};
/**
- * @brief tmr pr register, offset:0x2C
+ * @brief tmr pr register, offset:0x2C
*/
union
{
@@ -985,7 +985,7 @@ typedef struct
};
/**
- * @brief tmr rpr register, offset:0x30
+ * @brief tmr rpr register, offset:0x30
*/
union
{
@@ -998,7 +998,7 @@ typedef struct
};
/**
- * @brief tmr c1dt register, offset:0x34
+ * @brief tmr c1dt register, offset:0x34
*/
union
{
@@ -1011,7 +1011,7 @@ typedef struct
};
/**
- * @brief tmr c2dt register, offset:0x38
+ * @brief tmr c2dt register, offset:0x38
*/
union
{
@@ -1024,7 +1024,7 @@ typedef struct
};
/**
- * @brief tmr c3dt register, offset:0x3C
+ * @brief tmr c3dt register, offset:0x3C
*/
union
{
@@ -1037,7 +1037,7 @@ typedef struct
};
/**
- * @brief tmr c4dt register, offset:0x40
+ * @brief tmr c4dt register, offset:0x40
*/
union
{
@@ -1050,7 +1050,7 @@ typedef struct
};
/**
- * @brief tmr brk register, offset:0x44
+ * @brief tmr brk register, offset:0x44
*/
union
{
@@ -1077,7 +1077,7 @@ typedef struct
} brk_bit;
};
/**
- * @brief tmr dmactrl register, offset:0x48
+ * @brief tmr dmactrl register, offset:0x48
*/
union
{
@@ -1092,7 +1092,7 @@ typedef struct
};
/**
- * @brief tmr dmadt register, offset:0x4C
+ * @brief tmr dmadt register, offset:0x4C
*/
union
{
@@ -1132,8 +1132,8 @@ typedef struct
__IO uint32_t c5osen : 1; /* [7] */
__IO uint32_t reserved2 : 2; /* [9:8] */
__IO uint32_t c6oien : 1; /* [10] */
- __IO uint32_t c6oben : 1; /* [11] */
- __IO uint32_t c6octrl : 3; /* [14:12] */
+ __IO uint32_t c6oben : 1; /* [11] */
+ __IO uint32_t c6octrl : 3; /* [14:12] */
__IO uint32_t c6osen : 1; /* [15] */
__IO uint32_t c5octrl_3 : 1; /* [16] */
__IO uint32_t reserved3 : 7; /* [23:17] */
@@ -1143,7 +1143,7 @@ typedef struct
};
/**
- * @brief tmr c5dt register, offset:0x58
+ * @brief tmr c5dt register, offset:0x58
*/
union
{
@@ -1152,14 +1152,14 @@ typedef struct
{
__IO uint32_t c5dt : 16;/* [15:0] */
__IO uint32_t reserved1 : 13;/* [28:16] */
- __IO uint32_t cc5c1 : 1; /* [29] */
- __IO uint32_t cc5c2 : 1; /* [30] */
- __IO uint32_t cc5c3 : 1; /* [31] */
+ __IO uint32_t cc5c1 : 1; /* [29] */
+ __IO uint32_t cc5c2 : 1; /* [30] */
+ __IO uint32_t cc5c3 : 1; /* [31] */
} c5dt_bit;
};
/**
- * @brief tmr c6dt register, offset:0x5C
+ * @brief tmr c6dt register, offset:0x5C
*/
union
{
@@ -1172,7 +1172,7 @@ typedef struct
};
/**
- * @brief tmr opt2 register, offset:0x60
+ * @brief tmr opt2 register, offset:0x60
*/
union
{
@@ -1180,20 +1180,20 @@ typedef struct
struct
{
__IO uint32_t brkinen : 1; /* [0] */
- __IO uint32_t brkcmp1en : 1; /* [1] */
- __IO uint32_t brkcmp2en : 1; /* [2] */
- __IO uint32_t reserved1 : 6; /* [8:3] */
- __IO uint32_t brkinp : 1; /* [9] */
- __IO uint32_t brkcmp1p : 1; /* [10] */
- __IO uint32_t brkcmp2p : 1; /* [11] */
- __IO uint32_t reserved2 : 2; /* [13:12] */
- __IO uint32_t extsel : 4; /* [17:14] */
+ __IO uint32_t brkcmp1en : 1; /* [1] */
+ __IO uint32_t brkcmp2en : 1; /* [2] */
+ __IO uint32_t reserved1 : 6; /* [8:3] */
+ __IO uint32_t brkinp : 1; /* [9] */
+ __IO uint32_t brkcmp1p : 1; /* [10] */
+ __IO uint32_t brkcmp2p : 1; /* [11] */
+ __IO uint32_t reserved2 : 2; /* [13:12] */
+ __IO uint32_t extsel : 4; /* [17:14] */
__IO uint32_t reserved3 : 14;/* [31:18] */
} opt2_bit;
};
/**
- * @brief tmr opt3 register, offset:0x64
+ * @brief tmr opt3 register, offset:0x64
*/
union
{
@@ -1201,31 +1201,31 @@ typedef struct
struct
{
__IO uint32_t brk2inen : 1; /* [0] */
- __IO uint32_t brk2cmp1en : 1; /* [1] */
- __IO uint32_t brk2cmp2en : 1; /* [2] */
- __IO uint32_t reserved1 : 6; /* [8:3] */
- __IO uint32_t brk2inp : 1; /* [9] */
- __IO uint32_t brk2cmp1p : 1; /* [10] */
+ __IO uint32_t brk2cmp1en : 1; /* [1] */
+ __IO uint32_t brk2cmp2en : 1; /* [2] */
+ __IO uint32_t reserved1 : 6; /* [8:3] */
+ __IO uint32_t brk2inp : 1; /* [9] */
+ __IO uint32_t brk2cmp1p : 1; /* [10] */
__IO uint32_t brk2cmp2p : 1; /* [11] */
__IO uint32_t reserved2 : 20;/* [31:12] */
} opt3_bit;
};
/**
- * @brief tmr chsel register, offset:0x68
+ * @brief tmr chsel register, offset:0x68
*/
union
{
uint32_t chsel;
struct
{
- __IO uint32_t ch1sel : 4; /* [3:0] */
- __IO uint32_t reserved1 : 4; /* [7:4] */
- __IO uint32_t ch2sel : 4; /* [11:8] */
- __IO uint32_t reserved2 : 4; /* [15:12] */
- __IO uint32_t ch3sel : 4; /* [19:16] */
- __IO uint32_t reserved3 : 4; /* [23:20] */
- __IO uint32_t ch4sel : 4; /* [27:24] */
+ __IO uint32_t ch1sel : 4; /* [3:0] */
+ __IO uint32_t reserved1 : 4; /* [7:4] */
+ __IO uint32_t ch2sel : 4; /* [11:8] */
+ __IO uint32_t reserved2 : 4; /* [15:12] */
+ __IO uint32_t ch3sel : 4; /* [19:16] */
+ __IO uint32_t reserved3 : 4; /* [23:20] */
+ __IO uint32_t ch4sel : 4; /* [27:24] */
__IO uint32_t reserved4 : 4; /* [31:28] */
} chsel_bit;
};
@@ -1269,7 +1269,7 @@ typedef struct
__IO uint32_t reserved2[3];
/**
- * @brief tmr c1adt register, offset:0x80
+ * @brief tmr c1adt register, offset:0x80
*/
union
{
@@ -1282,7 +1282,7 @@ typedef struct
};
/**
- * @brief tmr c2adt register, offset:0x84
+ * @brief tmr c2adt register, offset:0x84
*/
union
{
@@ -1295,7 +1295,7 @@ typedef struct
};
/**
- * @brief tmr c3adt register, offset:0x88
+ * @brief tmr c3adt register, offset:0x88
*/
union
{
@@ -1308,7 +1308,7 @@ typedef struct
};
/**
- * @brief tmr c4adt register, offset:0x8C
+ * @brief tmr c4adt register, offset:0x8C
*/
union
{
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_usart.h b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_usart.h
index b87078bb597..7276c90dc96 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_usart.h
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_usart.h
@@ -5,11 +5,11 @@
**************************************************************************
* Copyright notice & Disclaimer
*
- * The software Board Support Package (BSP) that is made available to
- * download from Artery official website is the copyrighted work of Artery.
- * Artery authorizes customers to use, copy, and distribute the BSP
- * software and its related documentation for the purpose of design and
- * development in conjunction with Artery microcontrollers. Use of the
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -29,10 +29,10 @@
#ifdef __cplusplus
extern "C" {
#endif
-
+
/* includes ------------------------------------------------------------------*/
-#include "at32m412_416.h"
+#include "at32m412_416.h"
/** @addtogroup AT32M412_416_periph_driver
* @{
@@ -41,12 +41,12 @@ extern "C" {
/** @addtogroup USART
* @{
*/
-
+
/** @defgroup USART_flags_definition
- * @brief usart flag
+ * @brief usart flag
* @{
*/
-
+
#define USART_PERR_FLAG ((uint32_t)0x00000001) /*!< usart parity error flag */
#define USART_FERR_FLAG ((uint32_t)0x00000002) /*!< usart framing error flag */
#define USART_NERR_FLAG ((uint32_t)0x00000004) /*!< usart noise error flag */
@@ -64,7 +64,7 @@ extern "C" {
* @}
*/
-/** @defgroup USART_interrupts_definition
+/** @defgroup USART_interrupts_definition
* @brief usart interrupt
* @{
*/
@@ -83,11 +83,11 @@ extern "C" {
/**
* @}
*/
-
+
/** @defgroup USART_exported_types
* @{
*/
-
+
/**
* @brief usart parity selection type
*/
@@ -200,7 +200,7 @@ typedef struct
{
/**
* @brief usart sts register, offset:0x00
- */
+ */
union
{
__IO uint32_t sts;
@@ -223,10 +223,10 @@ typedef struct
__IO uint32_t reserved3 : 14;/* [31:18] */
} sts_bit;
};
-
+
/**
* @brief usart dt register, offset:0x04
- */
+ */
union
{
__IO uint32_t dt;
@@ -236,7 +236,7 @@ typedef struct
__IO uint32_t reserved1 : 23;/* [31:9] */
} dt_bit;
};
-
+
/**
* @brief usart baudr register, offset:0x08
*/
@@ -249,7 +249,7 @@ typedef struct
__IO uint32_t reserved1 : 16;/* [31:16] */
} baudr_bit;
};
-
+
/**
* @brief usart ctrl1 register, offset:0x0C
*/
@@ -302,16 +302,16 @@ typedef struct
__IO uint32_t clken : 1; /* [11] */
__IO uint32_t stopbn : 2; /* [13:12] */
__IO uint32_t linen : 1; /* [14] */
- __IO uint32_t trpswap : 1; /* [15] */
- __IO uint32_t rxrev : 1; /* [16] */
- __IO uint32_t txrev : 1; /* [17] */
- __IO uint32_t dtrev : 1; /* [18] */
- __IO uint32_t mtf : 1; /* [19] */
+ __IO uint32_t trpswap : 1; /* [15] */
+ __IO uint32_t rxrev : 1; /* [16] */
+ __IO uint32_t txrev : 1; /* [17] */
+ __IO uint32_t dtrev : 1; /* [18] */
+ __IO uint32_t mtf : 1; /* [19] */
__IO uint32_t reserved2 : 8; /* [27:20] */
__IO uint32_t idh : 4; /* [31:28] */
} ctrl2_bit;
};
-
+
/**
* @brief usart ctrl3 register, offset:0x14
*/
@@ -323,7 +323,7 @@ typedef struct
__IO uint32_t errien : 1; /* [0] */
__IO uint32_t irdaen : 1; /* [1] */
__IO uint32_t irdalp : 1; /* [2] */
- __IO uint32_t slben : 1; /* [3] */
+ __IO uint32_t slben : 1; /* [3] */
__IO uint32_t scnacken : 1; /* [4] */
__IO uint32_t scmen : 1; /* [5] */
__IO uint32_t dmaren : 1; /* [6] */
@@ -334,7 +334,7 @@ typedef struct
__IO uint32_t reserved1 : 3; /* [13:11] */
__IO uint32_t rs485en : 1; /* [14] */
__IO uint32_t dep : 1; /* [15] */
- __IO uint32_t reserved2 : 16;/* [31:16] */
+ __IO uint32_t reserved2 : 16;/* [31:16] */
} ctrl3_bit;
};
@@ -350,8 +350,8 @@ typedef struct
__IO uint32_t scgt : 8; /* [15:8] */
__IO uint32_t reserved1 : 16;/* [31:16] */
} gdiv_bit;
- };
-
+ };
+
/**
* @brief usart rtov register, offset:0x1c
*/
@@ -363,8 +363,8 @@ typedef struct
__IO uint32_t rtov : 24;/* [23:0] */
__IO uint32_t reserved : 8; /* [31:24] */
} rtov_bit;
- };
-
+ };
+
/**
* @brief usart ifc register, offset:0x20
*/
@@ -379,7 +379,7 @@ typedef struct
__IO uint32_t cmdfc : 1; /* [17] */
__IO uint32_t reserved3 : 14;/* [31:18] */
} ifc_bit;
- };
+ };
} usart_type;
/**
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_wdt.h b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_wdt.h
index 0c9c321047a..688c0f728bf 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_wdt.h
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_wdt.h
@@ -43,7 +43,7 @@ extern "C" {
*/
-/** @defgroup WDT_flags_definition
+/** @defgroup WDT_flags_definition
* @brief wdt flag
* @{
*/
@@ -51,7 +51,7 @@ extern "C" {
#define WDT_DIVF_UPDATE_FLAG ((uint16_t)0x0001) /*!< wdt division value update complete flag */
#define WDT_RLDF_UPDATE_FLAG ((uint16_t)0x0002) /*!< wdt reload value update complete flag */
#define WDT_WINF_UPDATE_FLAG ((uint16_t)0x0004) /*!< wdt window value update complete flag */
-
+
/**
* @}
*/
@@ -59,7 +59,7 @@ extern "C" {
/** @defgroup WDT_exported_types
* @{
*/
-
+
/**
* @brief wdt division value type
*/
@@ -157,7 +157,7 @@ typedef struct
} win_bit;
};
} wdt_type;
-
+
/**
* @}
*/
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_wwdt.h b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_wwdt.h
index ca49bff68de..9a031cb30a4 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_wwdt.h
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/inc/at32m412_416_wwdt.h
@@ -41,12 +41,12 @@ extern "C" {
/** @addtogroup WWDT
* @{
*/
-
-/** @defgroup WWDT_enable_bit_definition
+
+/** @defgroup WWDT_enable_bit_definition
* @brief wwdt enable bit
* @{
*/
-
+
#define WWDT_EN_BIT ((uint32_t)0x00000080) /*!< wwdt enable bit */
/**
@@ -122,7 +122,7 @@ typedef struct
* @}
*/
-#define WWDT ((wwdt_type *) WWDT_BASE)
+#define WWDT ((wwdt_type *) WWDT_BASE)
/** @defgroup WWDT_exported_functions
* @{
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_adc.c b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_adc.c
index bdbd8700479..fde365250bd 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_adc.c
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_adc.c
@@ -5,11 +5,11 @@
**************************************************************************
* Copyright notice & Disclaimer
*
- * The software Board Support Package (BSP) that is made available to
- * download from Artery official website is the copyrighted work of Artery.
- * Artery authorizes customers to use, copy, and distribute the BSP
- * software and its related documentation for the purpose of design and
- * development in conjunction with Artery microcontrollers. Use of the
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_can.c b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_can.c
index 7728f443fcc..4e9b4a4e450 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_can.c
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_can.c
@@ -5,11 +5,11 @@
**************************************************************************
* Copyright notice & Disclaimer
*
- * The software Board Support Package (BSP) that is made available to
- * download from Artery official website is the copyrighted work of Artery.
- * Artery authorizes customers to use, copy, and distribute the BSP
- * software and its related documentation for the purpose of design and
- * development in conjunction with Artery microcontrollers. Use of the
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -35,7 +35,7 @@
#ifdef CAN_MODULE_ENABLED
-#ifdef SUPPORT_CAN_FD
+#ifdef SUPPORT_CAN_FD
static const uint8_t dlc_to_bytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
#endif
@@ -180,13 +180,13 @@ error_status can_standby_mode_enable(can_type* can_x, confirm_state new_state)
{
can_x->ctrlstat_bit.stby = FALSE;
}
-
+
return SUCCESS;
}
/**
* @brief enable restricted operation of the can peripheral.
- * a can node which is in restricted operation mode shall not transmit data frames
+ * a can node which is in restricted operation mode shall not transmit data frames
* unless it is a potential time master for ttcan.
* @param can_x: select the can peripheral.
* this parameter can be one of the following values:
@@ -210,12 +210,12 @@ void can_bittime_default_para_init(can_bittime_type* can_bittime_struct)
/* reset can bittime structure parameters values */
can_bittime_struct->bittime_div = 1;
-
+
can_bittime_struct->ac_bts1_size = 12;
can_bittime_struct->ac_bts2_size = 4;
can_bittime_struct->ac_rsaw_size = 4;
-
-#ifdef SUPPORT_CAN_FD
+
+#ifdef SUPPORT_CAN_FD
can_bittime_struct->fd_bts1_size = 6;
can_bittime_struct->fd_bts2_size = 2;
can_bittime_struct->fd_rsaw_size = 2;
@@ -236,12 +236,12 @@ void can_bittime_default_para_init(can_bittime_type* can_bittime_struct)
void can_bittime_set(can_type* can_x, can_bittime_type* can_bittime_struct)
{
can_x->lbtcfg_bit.presc = can_bittime_struct->bittime_div - 1;
-
+
can_x->actime_bit.ac_seg_1 = can_bittime_struct->ac_bts1_size-2;
can_x->actime_bit.ac_seg_2 = can_bittime_struct->ac_bts2_size-1;
can_x->actime_bit.ac_sjw = can_bittime_struct->ac_rsaw_size-1;
-
-#ifdef SUPPORT_CAN_FD
+
+#ifdef SUPPORT_CAN_FD
can_x->fdtime_bit.fd_seg_1 = can_bittime_struct->fd_bts1_size-2;
can_x->fdtime_bit.fd_seg_2 = can_bittime_struct->fd_bts2_size-1;
can_x->fdtime_bit.fd_sjw = can_bittime_struct->fd_rsaw_size-1;
@@ -348,19 +348,19 @@ uint32_t can_transmit_timestamp_get(can_type* can_x)
* @retval SUCCESS or ERROR
*/
error_status can_txbuf_write(can_type* can_x, can_txbuf_select_type txbuf_type, can_txbuf_type* can_txbuf_struct)
-{
-#ifdef SUPPORT_CAN_FD
+{
+#ifdef SUPPORT_CAN_FD
uint8_t len = dlc_to_bytes[can_txbuf_struct->data_length];
-#else
+#else
uint8_t len = can_txbuf_struct->data_length;
-#endif
+#endif
uint32_t* wp = (uint32_t*)can_x->tbdat;
uint8_t* rp = can_txbuf_struct->data;
uint8_t byte_cnt;
-
+
uint8_t* reg;
- uint8_t tmp;
-
+ uint8_t tmp;
+
switch(txbuf_type)
{
case CAN_TXBUF_PTB:
@@ -385,7 +385,7 @@ error_status can_txbuf_write(can_type* can_x, can_txbuf_select_type txbuf_type,
reg = (uint8_t*)&can_x->ctrlstat + 1;
tmp = *reg & 0x60;
*reg = tmp | (txbuf_type<<7);
-
+
switch(can_txbuf_struct->id_type)
{
case CAN_ID_STANDARD:
@@ -398,16 +398,16 @@ error_status can_txbuf_write(can_type* can_x, can_txbuf_select_type txbuf_type,
return ERROR;
}
can_x->tbid |= (can_txbuf_struct->tx_timestamp << 31);
-
+
can_x->tbfmt = 0;
can_x->tbfmt_bit.ide = can_txbuf_struct->id_type;
- can_x->tbfmt_bit.rmf = can_txbuf_struct->frame_type;
+ can_x->tbfmt_bit.rmf = can_txbuf_struct->frame_type;
can_x->tbfmt_bit.dlc = can_txbuf_struct->data_length;
-#ifdef SUPPORT_CAN_FD
+#ifdef SUPPORT_CAN_FD
can_x->tbfmt_bit.brs = can_txbuf_struct->fd_rate_switch;
can_x->tbfmt_bit.fdf = can_txbuf_struct->fd_format;
#endif
-
+
/* write tx payload to the buffer ram. */
for (byte_cnt = 0; byte_cnt < len; byte_cnt += 4U)
{
@@ -416,19 +416,19 @@ error_status can_txbuf_write(can_type* can_x, can_txbuf_select_type txbuf_type,
((uint32_t)rp[byte_cnt + 1U] << 8U) |
(uint32_t)rp[byte_cnt]);
}
-
+
can_x->tbtyp = 0;
can_x->tbtyp_bit.handle = can_txbuf_struct->handle;
- can_x->tbacf = 0;
-
+ can_x->reserved8 = 0;
+
if(txbuf_type == CAN_TXBUF_STB)
{
/* write TSNEXT, mark a slot filled and point to the next frame slot. */
reg = (uint8_t*)&can_x->ctrlstat + 2;
tmp = *reg;
- *reg = tmp | 0x40;
+ *reg = tmp | 0x40;
}
-
+
return SUCCESS;
}
@@ -453,14 +453,14 @@ error_status can_rxbuf_read(can_type* can_x, can_rxbuf_type* can_rxbuf_struct)
uint16_t pos;
uint8_t* reg;
- uint8_t tmp;
+ uint8_t tmp;
if(can_x->ctrlstat_bit.rstat == CAN_RXBUF_STATUS_EMPTY)
{
/* receive buffer is empty. */
- return ERROR;
+ return ERROR;
}
-
+
can_rxbuf_struct->id_type = (can_identifier_type)can_x->rbfmt_bit.ide;
switch(can_rxbuf_struct->id_type)
{
@@ -473,17 +473,17 @@ error_status can_rxbuf_read(can_type* can_x, can_rxbuf_type* can_rxbuf_struct)
default:
return ERROR;
}
-
+
can_rxbuf_struct->frame_type = (can_frame_type)can_x->rbfmt_bit.rmf;
-#ifdef SUPPORT_CAN_FD
+#ifdef SUPPORT_CAN_FD
can_rxbuf_struct->fd_format = (can_format_type)can_x->rbfmt_bit.fdf;
can_rxbuf_struct->fd_rate_switch = (can_rate_switch_type)can_x->rbfmt_bit.brs;
can_rxbuf_struct->fd_error_state = (can_error_state_type)can_x->rbfmt_bit.esi;
-#endif
+#endif
can_rxbuf_struct->kind_error = (can_error_type)can_x->rbfmt_bit.koer;
can_rxbuf_struct->recv_frame = (can_recv_frame_type)can_x->rbfmt_bit.lbf;
can_rxbuf_struct->data_length = (can_data_length_type)can_x->rbfmt_bit.dlc;
-
+
/* read the buffer ram to rx payload */
for (byte_cnt = 0; byte_cnt < len; byte_cnt += 4U)
{
@@ -493,12 +493,12 @@ error_status can_rxbuf_read(can_type* can_x, can_rxbuf_type* can_rxbuf_struct)
wp[byte_cnt+3U] = (*rp >> 24U) & 0xFF;
rp++;
}
-
+
can_x->llcformat = can_x->rbfmt;
pos = (can_x->llcsize_bit.llcaot / 4) - 4;
can_rxbuf_struct->rx_timestamp = (uint32_t)can_x->rbdat[pos];
can_rxbuf_struct->cycle_time = (uint16_t)can_x->rbdat[pos + 2];
-
+
/* set RREL, receive buffer release. */
reg = (uint8_t*)&can_x->ctrlstat + 3;
tmp = *reg;
@@ -513,7 +513,7 @@ error_status can_rxbuf_read(can_type* can_x, can_rxbuf_type* can_rxbuf_struct)
* this parameter can be one of the following values:
* CAN1.
* @param filter_number: point to a specific acceptance filter.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - CAN_FILTER_NUM_0
* - CAN_FILTER_NUM_1
* - CAN_FILTER_NUM_2
@@ -554,7 +554,7 @@ void can_filter_enable(can_type* can_x, can_filter_type filter_number, confirm_s
void can_filter_default_para_init(can_filter_config_type* filter_config_struct)
{
/* reset can filter config structure parameters values */
-
+
filter_config_struct->code_para.id = 0;
filter_config_struct->code_para.id_type = CAN_ID_STANDARD;
filter_config_struct->code_para.frame_type = CAN_FRAME_DATA;
@@ -564,8 +564,8 @@ void can_filter_default_para_init(can_filter_config_type* filter_config_struct)
filter_config_struct->code_para.fd_format = CAN_FORMAT_CLASSIC;
filter_config_struct->code_para.fd_rate_switch = CAN_BRS_OFF;
filter_config_struct->code_para.fd_error_state = CAN_ESI_ACTIVE;
-#endif
-
+#endif
+
filter_config_struct->mask_para.id = 0xFFFFFFFF;
filter_config_struct->mask_para.id_type = TRUE;
filter_config_struct->mask_para.frame_type = TRUE;
@@ -575,7 +575,7 @@ void can_filter_default_para_init(can_filter_config_type* filter_config_struct)
filter_config_struct->mask_para.fd_format = TRUE;
filter_config_struct->mask_para.fd_rate_switch = TRUE;
filter_config_struct->mask_para.fd_error_state = TRUE;
-#endif
+#endif
}
/**
@@ -584,7 +584,7 @@ void can_filter_default_para_init(can_filter_config_type* filter_config_struct)
* this parameter can be one of the following values:
* CAN1.
* @param filter_number: point to a specific acceptance filter number.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - CAN_FILTER_NUM_0
* - CAN_FILTER_NUM_1
* - CAN_FILTER_NUM_2
@@ -607,7 +607,7 @@ void can_filter_default_para_init(can_filter_config_type* filter_config_struct)
void can_filter_set(can_type* can_x, can_filter_type filter_number, can_filter_config_type* filter_config_struct)
{
can_x->acfctrl_bit.acfadr = filter_number;
-
+
switch(filter_config_struct->code_para.id_type)
{
case CAN_ID_STANDARD:
@@ -623,12 +623,12 @@ void can_filter_set(can_type* can_x, can_filter_type filter_number, can_filter_c
can_x->fcfmt_bit.rmf = filter_config_struct->code_para.frame_type;
can_x->fcfmt_bit.dlc = filter_config_struct->code_para.data_length;
can_x->fcfmt_bit.lbf = filter_config_struct->code_para.recv_frame;
-#ifdef SUPPORT_CAN_FD
+#ifdef SUPPORT_CAN_FD
can_x->fcfmt_bit.brs = filter_config_struct->code_para.fd_rate_switch;
can_x->fcfmt_bit.fdf = filter_config_struct->code_para.fd_format;
can_x->fcfmt_bit.esi = filter_config_struct->code_para.fd_error_state;
-#endif
-
+#endif
+
can_x->fmid = 0xFFFFFFFF;
/* write mask_id by id_type of filter_code_struct. */
switch(filter_config_struct->code_para.id_type)
@@ -644,16 +644,16 @@ void can_filter_set(can_type* can_x, can_filter_type filter_number, can_filter_c
}
can_x->fmfmt = 0xFFFFFFFF;
can_x->fmfmt_bit.ide = filter_config_struct->mask_para.id_type;
- can_x->fmfmt_bit.rmf = filter_config_struct->mask_para.frame_type;
+ can_x->fmfmt_bit.rmf = filter_config_struct->mask_para.frame_type;
can_x->fmfmt_bit.dlc = filter_config_struct->mask_para.data_length;
- can_x->fmfmt_bit.lbf = filter_config_struct->mask_para.recv_frame;
-#ifdef SUPPORT_CAN_FD
+ can_x->fmfmt_bit.lbf = filter_config_struct->mask_para.recv_frame;
+#ifdef SUPPORT_CAN_FD
can_x->fmfmt_bit.brs = filter_config_struct->mask_para.fd_rate_switch;
can_x->fmfmt_bit.fdf = filter_config_struct->mask_para.fd_format;
can_x->fmfmt_bit.esi = filter_config_struct->mask_para.fd_error_state;
-#endif
+#endif
can_x->fmtyp = 0xFFFFFFFF;
- can_x->fmacf = 0xFFFFFFFF;
+ can_x->reserved6[0] = 0xFFFFFFFF;
}
/**
@@ -666,7 +666,7 @@ void can_filter_set(can_type* can_x, can_filter_type filter_number, can_filter_c
error_status can_rxbuf_release(can_type* can_x)
{
uint8_t* reg;
- uint8_t tmp;
+ uint8_t tmp;
if(can_x->ctrlstat_bit.rstat == CAN_RXBUF_STATUS_EMPTY)
{
@@ -699,7 +699,7 @@ uint8_t can_arbitration_lost_position_get(can_type* can_x)
* @param can_x: select the can peripheral.
* this parameter can be one of the following values:
* CAN1.
- * @param warning_value: defines the internal warning limit of receive buffer almost full.
+ * @param warning_value: defines the internal warning limit of receive buffer almost full.
* this parameter can be 1~6.
* @retval none
*/
@@ -713,7 +713,7 @@ void can_rxbuf_warning_set(can_type* can_x, uint8_t warning_value)
* @param can_x: select the can peripheral.
* this parameter can be one of the following values:
* CAN1.
- * @param warning_value: programmable error warning limit = (warning_value + 1)*8. possible limit values: 8, 16, ¡ 128.
+ * @param warning_value: programmable error warning limit = (warning_value + 1)*8. possible limit values: 8, 16, ... 128.
* this parameter can be 0~15.
* @retval none
*/
@@ -755,7 +755,7 @@ uint8_t can_transmit_error_counter_get(can_type* can_x)
* @param can_x: select the can peripheral.
* this parameter can be one of the following values:
* CAN1.
- * @retval can kind of error type.
+ * @retval can kind of error type.
* the returned value can be one of the following values:
* - CAN_KOER_NOERR
* - CAN_KOER_BIT
@@ -789,7 +789,7 @@ flag_status can_busoff_get(can_type* can_x)
{
bit_status = SET;
}
- return bit_status;
+ return bit_status;
}
/**
@@ -826,7 +826,7 @@ void can_stb_transmit_mode_set(can_type* can_x, can_stb_transmit_mode_type stb_t
* @param can_x: select the can peripheral.
* this parameter can be one of the following values:
* CAN1.
- * @retval the status of the secondary transmit buffer.
+ * @retval the status of the secondary transmit buffer.
* the returned value can be one of the following values:
* - CAN_STB_STATUS_EMPTY
* - CAN_STB_STATUS_LESS
@@ -860,7 +860,7 @@ void can_transmit_status_get(can_type* can_x, can_transmit_status_type* transmit
* @param can_x: select the can peripheral.
* this parameter can be one of the following values:
* CAN1.
- * @retval the status of can receive buffer.
+ * @retval the status of can receive buffer.
* the returned value can be:
* - CAN_RXBUF_STATUS_EMPTY
* - CAN_RXBUF_STATUS_LESS
@@ -871,12 +871,12 @@ void can_transmit_status_get(can_type* can_x, can_transmit_status_type* transmit
can_rxbuf_status_type can_rxbuf_status_get(can_type* can_x)
{
uint8_t status = can_x->ctrlstat_bit.rstat;
-
+
if(can_x->ctrlstat_bit.rov == SET)
{
status = CAN_RXBUF_STATUS_OVERFLOW;
}
-
+
return (can_rxbuf_status_type)status;
}
@@ -925,7 +925,7 @@ void can_transmit_abort(can_type* can_x, can_abort_transmit_type abort_type)
{
uint8_t* reg = (uint8_t*)&can_x->ctrlstat + 1;
uint8_t tmp;
-
+
/* avoid duplicate setting these bits(TSA, TSALL, TSONE, TPA, TPE). */
tmp = *reg & 0xE0;
*reg = tmp | abort_type;
@@ -946,17 +946,17 @@ error_status can_stb_clear(can_type* can_x, can_clear_stb_type clear_type)
{
uint8_t* reg = (uint8_t*)&can_x->ctrlstat + 1;
uint8_t tmp;
-
+
if(can_x->ctrlstat_bit.tsstat == CAN_STB_STATUS_EMPTY)
{
/* the secondary transmit buffer is empty. */
- return ERROR;
+ return ERROR;
}
-
+
/* avoid duplicate setting these bits(TSA, TSALL, TSONE, TPA, TPE). */
tmp = *reg & 0xE0;
*reg = tmp | clear_type;
-
+
return SUCCESS;
}
@@ -975,8 +975,8 @@ error_status can_stb_clear(can_type* can_x, can_clear_stb_type clear_type)
error_status can_txbuf_transmit(can_type* can_x, can_txbuf_transmit_type transmit_type)
{
uint8_t* reg = (uint8_t*)&can_x->ctrlstat + 1;
- uint8_t tmp;
-
+ uint8_t tmp;
+
/* once standby is activated no transmission is possible. */
if(can_x->ctrlstat_bit.stby == SET)
return ERROR;
@@ -985,23 +985,23 @@ error_status can_txbuf_transmit(can_type* can_x, can_txbuf_transmit_type transmi
{
case CAN_TRANSMIT_PTB:
if(can_x->ctrlstat_bit.tpe || can_x->ctrlstat_bit.tpa)
- return ERROR;
+ return ERROR;
break;
case CAN_TRANSMIT_STB_ONE:
case CAN_TRANSMIT_STB_ALL:
if(can_x->ctrlstat_bit.tsstat == CAN_STB_STATUS_EMPTY)
- return ERROR;
+ return ERROR;
if(can_x->ctrlstat_bit.tsall || can_x->ctrlstat_bit.tsone || can_x->ctrlstat_bit.tsa)
return ERROR;
break;
default:
return ERROR;
}
-
+
/* avoid duplicate setting these bits(TSA, TSALL, TSONE, TPA, TPE). */
tmp = *reg & 0xE0;
*reg = tmp | transmit_type;
-
+
return SUCCESS;
}
@@ -1133,7 +1133,7 @@ void can_ttcan_watch_trigger_set(can_type* can_x, uint16_t watch_trigger_time)
* this parameter can be one of the following values:
* CAN1.
* @param txbuf_number: pointer to a txbuf frame slot.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - CAN_TTCAN_TXBUF_NUM_0
* - CAN_TTCAN_TXBUF_NUM_1
* - CAN_TTCAN_TXBUF_NUM_2
@@ -1141,7 +1141,7 @@ void can_ttcan_watch_trigger_set(can_type* can_x, uint16_t watch_trigger_time)
* @param ttcan_buffer_type: ttcan txbuf slot status.
* this parameter can be one of the following values:
* - CAN_TTCAN_TXBUF_EMPTY
- * - CAN_TTCAN_TXBUF_FILLED
+ * - CAN_TTCAN_TXBUF_FILLED
* @retval none
*/
void can_ttcan_txbuf_status_set(can_type* can_x, can_ttcan_txbuf_type txbuf_number, can_ttcan_txbuf_status_type status_type)
@@ -1166,7 +1166,7 @@ void can_ttcan_txbuf_status_set(can_type* can_x, can_ttcan_txbuf_type txbuf_num
* this parameter can be one of the following values:
* CAN1.
* @param txbuf_number: pointer to a txbuf frame slot.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - CAN_TTCAN_TXBUF_NUM_0
* - CAN_TTCAN_TXBUF_NUM_1
* - CAN_TTCAN_TXBUF_NUM_2
@@ -1194,7 +1194,7 @@ can_ttcan_txbuf_status_type can_ttcan_txbuf_status_get(can_type* can_x, can_ttca
* this parameter can be one of the following values:
* CAN1.
* @param txbuf_number: pointer to a txbuf frame slot.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - CAN_TTCAN_TXBUF_NUM_0
* - CAN_TTCAN_TXBUF_NUM_1
* - CAN_TTCAN_TXBUF_NUM_2
@@ -1204,22 +1204,22 @@ can_ttcan_txbuf_status_type can_ttcan_txbuf_status_get(can_type* can_x, can_ttca
*/
error_status can_ttcan_txbuf_write(can_type* can_x, can_ttcan_txbuf_type txbuf_number, can_txbuf_type* can_txbuf_struct)
{
-#ifdef SUPPORT_CAN_FD
+#ifdef SUPPORT_CAN_FD
uint8_t len = dlc_to_bytes[can_txbuf_struct->data_length];
-#else
+#else
uint8_t len = can_txbuf_struct->data_length;
-#endif
+#endif
uint32_t *wp = (uint32_t*)can_x->tbdat;
uint8_t *rp = can_txbuf_struct->data;
uint8_t byte_cnt;
-
+
can_x->ttcfg_bit.tbptr = txbuf_number;
if(can_x->ctrlstat_bit.tsff == SET)
{
/* the buffer slot selected by tbptr be filled are write-locked. */
return ERROR;
}
-
+
switch(can_txbuf_struct->id_type)
{
case CAN_ID_STANDARD:
@@ -1232,16 +1232,16 @@ error_status can_ttcan_txbuf_write(can_type* can_x, can_ttcan_txbuf_type txbuf_
return ERROR;
}
can_x->tbid |= (can_txbuf_struct->tx_timestamp << 31);
-
+
can_x->tbfmt = 0;
can_x->tbfmt_bit.ide = can_txbuf_struct->id_type;
- can_x->tbfmt_bit.rmf = can_txbuf_struct->frame_type;
+ can_x->tbfmt_bit.rmf = can_txbuf_struct->frame_type;
can_x->tbfmt_bit.dlc = can_txbuf_struct->data_length;
-#ifdef SUPPORT_CAN_FD
+#ifdef SUPPORT_CAN_FD
can_x->tbfmt_bit.brs = can_txbuf_struct->fd_rate_switch;
can_x->tbfmt_bit.fdf = can_txbuf_struct->fd_format;
#endif
-
+
/* Write Tx payload to the message RAM */
for (byte_cnt = 0; byte_cnt < len; byte_cnt += 4U)
{
@@ -1250,14 +1250,14 @@ error_status can_ttcan_txbuf_write(can_type* can_x, can_ttcan_txbuf_type txbuf_
((uint32_t)rp[byte_cnt + 1U] << 8U) |
(uint32_t)rp[byte_cnt]);
}
-
+
can_x->tbtyp = 0;
can_x->tbtyp_bit.handle = can_txbuf_struct->handle;
- can_x->tbacf = 0;
-
+ can_x->reserved8 = 0;
+
/* the buffer slot selected by tbptr shall be marked as filled. */
can_x->ttcfg_bit.tbf = TRUE;
-
+
return SUCCESS;
}
@@ -1267,11 +1267,11 @@ error_status can_ttcan_txbuf_write(can_type* can_x, can_ttcan_txbuf_type txbuf_
* this parameter can be one of the following values:
* CAN1.
* @param txbuf_number: pointer to a txbuf frame slot.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - CAN_TTCAN_TXBUF_NUM_0
* - CAN_TTCAN_TXBUF_NUM_1
* - CAN_TTCAN_TXBUF_NUM_2
- * - CAN_TTCAN_TXBUF_NUM_3
+ * - CAN_TTCAN_TXBUF_NUM_3
* @retval none
*/
void can_ttcan_txbuf_transmit_set(can_type* can_x, can_ttcan_txbuf_type txbuf_number)
@@ -1330,7 +1330,7 @@ void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_s
{
can_x->inten &= ~can_int;
}
-}
+}
/**
* @brief get flag of the specified can peripheral.
@@ -1339,22 +1339,22 @@ void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_s
* CAN1.
* @param can_flag: select the flag.
* this parameter can be one of the following flags:
- * - CAN_AIF_FLAG
- * - CAN_EIF_FLAG
- * - CAN_TSIF_FLAG
- * - CAN_TPIF_FLAG
- * - CAN_RAFIF_FLAG
- * - CAN_RFIF_FLAG
- * - CAN_ROIF_FLAG
- * - CAN_RIF_FLAG
- * - CAN_BEIF_FLAG
- * - CAN_ALIF_FLAG
- * - CAN_EPIF_FLAG
- * - CAN_TTIF_FLAG
- * - CAN_TEIF_FLAG
- * - CAN_WTIE_FLAG
- * - CAN_EPASS_FLAG
- * - CAN_EWARN_FLAG
+ * - CAN_AIF_FLAG
+ * - CAN_EIF_FLAG
+ * - CAN_TSIF_FLAG
+ * - CAN_TPIF_FLAG
+ * - CAN_RAFIF_FLAG
+ * - CAN_RFIF_FLAG
+ * - CAN_ROIF_FLAG
+ * - CAN_RIF_FLAG
+ * - CAN_BEIF_FLAG
+ * - CAN_ALIF_FLAG
+ * - CAN_EPIF_FLAG
+ * - CAN_TTIF_FLAG
+ * - CAN_TEIF_FLAG
+ * - CAN_WTIE_FLAG
+ * - CAN_EPASS_FLAG
+ * - CAN_EWARN_FLAG
* @retval status of can flag, the returned value can be:SET or RESET.
*/
flag_status can_flag_get(can_type* can_x, uint32_t can_flag)
@@ -1374,19 +1374,19 @@ flag_status can_flag_get(can_type* can_x, uint32_t can_flag)
* CAN1.
* @param can_flag: select the flag.
* this parameter can be one of the following flags:
- * - CAN_AIF_FLAG
- * - CAN_EIF_FLAG
- * - CAN_TSIF_FLAG
- * - CAN_TPIF_FLAG
- * - CAN_RAFIF_FLAG
- * - CAN_RFIF_FLAG
- * - CAN_ROIF_FLAG
- * - CAN_RIF_FLAG
- * - CAN_BEIF_FLAG
- * - CAN_ALIF_FLAG
- * - CAN_EPIF_FLAG
- * - CAN_TTIF_FLAG
- * - CAN_TEIF_FLAG
+ * - CAN_AIF_FLAG
+ * - CAN_EIF_FLAG
+ * - CAN_TSIF_FLAG
+ * - CAN_TPIF_FLAG
+ * - CAN_RAFIF_FLAG
+ * - CAN_RFIF_FLAG
+ * - CAN_ROIF_FLAG
+ * - CAN_RIF_FLAG
+ * - CAN_BEIF_FLAG
+ * - CAN_ALIF_FLAG
+ * - CAN_EPIF_FLAG
+ * - CAN_TTIF_FLAG
+ * - CAN_TEIF_FLAG
* - CAN_WTIE_FLAG
* @retval flag_status (SET or RESET)
*/
@@ -1407,23 +1407,23 @@ flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag)
* CAN1.
* @param can_flag: select the flag.
* this parameter can be one of the following flags:
- * - CAN_AIF_FLAG
- * - CAN_EIF_FLAG
- * - CAN_TSIF_FLAG
- * - CAN_TPIF_FLAG
- * - CAN_RAFIF_FLAG
- * - CAN_RFIF_FLAG
- * - CAN_ROIF_FLAG
- * - CAN_RIF_FLAG
- * - CAN_BEIF_FLAG
- * - CAN_ALIF_FLAG
- * - CAN_EPIF_FLAG
- * - CAN_TTIF_FLAG
- * - CAN_TEIF_FLAG
- * - CAN_WTIE_FLAG
- * - CAN_EPASS_FLAG
- * - CAN_EWARN_FLAG
- * - CAN_ALL_FLAG
+ * - CAN_AIF_FLAG
+ * - CAN_EIF_FLAG
+ * - CAN_TSIF_FLAG
+ * - CAN_TPIF_FLAG
+ * - CAN_RAFIF_FLAG
+ * - CAN_RFIF_FLAG
+ * - CAN_ROIF_FLAG
+ * - CAN_RIF_FLAG
+ * - CAN_BEIF_FLAG
+ * - CAN_ALIF_FLAG
+ * - CAN_EPIF_FLAG
+ * - CAN_TTIF_FLAG
+ * - CAN_TEIF_FLAG
+ * - CAN_WTIE_FLAG
+ * - CAN_EPASS_FLAG
+ * - CAN_EWARN_FLAG
+ * - CAN_ALL_FLAG
* @retval none.
*/
void can_flag_clear(can_type* can_x, uint32_t can_flag)
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_crm.c b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_crm.c
index de94f84d802..1a5a6b3db81 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_crm.c
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_crm.c
@@ -5,11 +5,11 @@
**************************************************************************
* Copyright notice & Disclaimer
*
- * The software Board Support Package (BSP) that is made available to
- * download from Artery official website is the copyrighted work of Artery.
- * Artery authorizes customers to use, copy, and distribute the BSP
- * software and its related documentation for the purpose of design and
- * development in conjunction with Artery microcontrollers. Use of the
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -519,7 +519,7 @@ void crm_vbath_div_set(crm_vbath_div_type value)
}
/**
- * @brief set crm lext driving strength
+ * @brief set crm lext driving strength
* @param value
* this parameter can be one of the following values:
* - CRM_DRV_STRENGTH_LOW
@@ -534,7 +534,7 @@ void crm_lextdrv_set(crm_drv_strength_type value)
}
/**
- * @brief set crm hext driving strength
+ * @brief set crm hext driving strength
* @param value
* this parameter can be one of the following values:
* - CRM_DRV_STRENGTH_LOW
@@ -614,7 +614,7 @@ void crm_auto_step_mode_enable(confirm_state new_state)
CRM->misc2_bit.auto_step_en = CRM_AUTO_STEP_MODE_DISABLE;
}
-/**
+/**
* @brief can multi clock source select
* @param can_index
* this parameter can be one of the following values:
@@ -636,7 +636,7 @@ void crm_can_clock_select(crm_can_type can_index, crm_can_clock_source_type valu
}
}
-/**
+/**
* @brief can multi clock source select
* @param can_index
* this parameter can be one of the following values:
@@ -657,7 +657,7 @@ crm_can_clock_source_type crm_can_clock_get(crm_can_type can_index)
return value;
}
-/**
+/**
* @brief hick as system clock frequency select
* @param value
* this parameter can be one of the following values:
@@ -679,7 +679,6 @@ void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value)
}
CRM->misc1_bit.hick_to_sclk = TRUE;
- CRM->misc1_bit.hickdiv = CRM_HICK48_NODIV;
CRM->misc1_bit.hick_to_sclk = value;
crm_hick_sclk_div_set((crm_hick_sclk_div_type)temp_div);
}
@@ -720,10 +719,6 @@ void crm_pll_config(crm_pll_clock_source_type clock_source, uint16_t pll_ns, \
uint16_t pll_ms, crm_pll_fr_type pll_fr)
{
/* config pll clock source */
- if(clock_source == CRM_PLL_SOURCE_HICK)
- {
- CRM->misc1_bit.hickdiv = CRM_HICK48_NODIV;
- }
CRM->pllcfg_bit.pllrcs = clock_source;
/* config pll multiplication factor */
@@ -789,7 +784,7 @@ void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct)
switch(sclk_source)
{
case CRM_SCLK_HICK:
- if(((CRM->misc1_bit.hick_to_sclk) != RESET) && ((CRM->misc1_bit.hickdiv) != RESET))
+ if((CRM->misc1_bit.hick_to_sclk) != RESET)
clocks_struct->sclk_freq = HICK_VALUE * 6;
else
clocks_struct->sclk_freq = HICK_VALUE;
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_debug.c b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_debug.c
index c1b0343c335..c7a5f4e0fc6 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_debug.c
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_debug.c
@@ -5,11 +5,11 @@
**************************************************************************
* Copyright notice & Disclaimer
*
- * The software Board Support Package (BSP) that is made available to
- * download from Artery official website is the copyrighted work of Artery.
- * Artery authorizes customers to use, copy, and distribute the BSP
- * software and its related documentation for the purpose of design and
- * development in conjunction with Artery microcontrollers. Use of the
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -40,7 +40,7 @@
*/
/**
- * @brief get debug device id
+ * @brief get debug device id
* @param none
* @retval the debug device id
*/
@@ -49,87 +49,87 @@ uint32_t debug_device_id_get(void)
return DEBUGMCU->pid;
}
/**
- * @brief set periph debug mode
+ * @brief set periph debug mode
* @param periph_debug_mode
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - DEBUG_SLEEP
* - DEBUG_DEEPSLEEP
* - DEBUG_STANDBY
- * @param new_state (TRUE or FALSE)
+ * @param new_state (TRUE or FALSE)
* @retval none
*/
void debug_low_power_mode_set(uint32_t low_power_mode, confirm_state new_state)
{
if(new_state != FALSE)
{
- DEBUGMCU->ctrl |= low_power_mode;
+ DEBUGMCU->ctrl |= low_power_mode;
}
else
{
- DEBUGMCU->ctrl &= ~low_power_mode;
+ DEBUGMCU->ctrl &= ~low_power_mode;
}
}
/**
- * @brief set apb1 periph debug mode
+ * @brief set apb1 periph debug mode
* @param periph_debug_mode
* this parameter can be any combination of the following values:
* - DEBUG_TMR3_PAUSE - DEBUG_TMR4_PAUSE
* - DEBUG_TMR6_PAUSE - DEBUG_TMR7_PAUSE
* - DEBUG_ERTC_PAUSE - DEBUG_WWDT_PAUSE
* - DEBUG_WDT_PAUSE - DEBUG_I2C1_SMBUS_TIMEOUT
- * - DEBUG_I2C2_SMBUS_TIMEOUT - DEBUG_CAN1_PAUSE
- * @param new_state (TRUE or FALSE)
+ * - DEBUG_I2C2_SMBUS_TIMEOUT
+ * @param new_state (TRUE or FALSE)
* @retval none
*/
void debug_apb1_periph_mode_set(uint32_t apb1_periph, confirm_state new_state)
{
if(new_state != FALSE)
{
- DEBUGMCU->apb1_frz |= apb1_periph;
+ DEBUGMCU->apb1_frz |= apb1_periph;
}
else
{
- DEBUGMCU->apb1_frz &= ~apb1_periph;
+ DEBUGMCU->apb1_frz &= ~apb1_periph;
}
}
/**
- * @brief set apb2 periph debug mode
+ * @brief set apb2 periph debug mode
* @param periph_debug_mode
* this parameter can be any combination of the following values:
- * - DEBUG_TMR1_PAUSE - DEBUG_TMR9_PAUSE
+ * - DEBUG_TMR1_PAUSE - DEBUG_TMR9_PAUSE
* - DEBUG_TMR10_PAUSE - DEBUG_TMR11_PAUSE
- * @param new_state (TRUE or FALSE)
+ * @param new_state (TRUE or FALSE)
* @retval none
*/
void debug_apb2_periph_mode_set(uint32_t apb2_periph, confirm_state new_state)
{
if(new_state != FALSE)
{
- DEBUGMCU->apb2_frz |= apb2_periph;
+ DEBUGMCU->apb2_frz |= apb2_periph;
}
else
{
- DEBUGMCU->apb2_frz &= ~apb2_periph;
+ DEBUGMCU->apb2_frz &= ~apb2_periph;
}
}
/**
- * @brief set apb3 periph debug mode
+ * @brief set apb3 periph debug mode
* @param periph_debug_mode
* this parameter can be any combination of the following values:
* - DEBUG_ERTC_PAUSE
- * @param new_state (TRUE or FALSE)
+ * @param new_state (TRUE or FALSE)
* @retval none
*/
void debug_apb3_periph_mode_set(uint32_t apb3_periph, confirm_state new_state)
{
if(new_state != FALSE)
{
- DEBUGMCU->apb3_frz |= apb3_periph;
+ DEBUGMCU->apb3_frz |= apb3_periph;
}
else
{
- DEBUGMCU->apb3_frz &= ~apb3_periph;
+ DEBUGMCU->apb3_frz &= ~apb3_periph;
}
}
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_dma.c b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_dma.c
index 7416b8befbb..c0ac63b6ace 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_dma.c
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_dma.c
@@ -5,11 +5,11 @@
**************************************************************************
* Copyright notice & Disclaimer
*
- * The software Board Support Package (BSP) that is made available to
- * download from Artery official website is the copyrighted work of Artery.
- * Artery authorizes customers to use, copy, and distribute the BSP
- * software and its related documentation for the purpose of design and
- * development in conjunction with Artery microcontrollers. Use of the
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -41,15 +41,15 @@
/**
* @brief reset dmax channely register.
- * @param dmax_channely:
- * this parameter can be one of the following values:
- * - DMA1_CHANNEL1
- * - DMA1_CHANNEL2
- * - DMA1_CHANNEL3
- * - DMA1_CHANNEL4
- * - DMA1_CHANNEL5
- * - DMA1_CHANNEL6
- * - DMA1_CHANNEL7
+ * @param dmax_channely:
+ * this parameter can be one of the following values:
+ * - DMA1_CHANNEL1
+ * - DMA1_CHANNEL2
+ * - DMA1_CHANNEL3
+ * - DMA1_CHANNEL4
+ * - DMA1_CHANNEL5
+ * - DMA1_CHANNEL6
+ * - DMA1_CHANNEL7
* @retval none.
*/
void dma_reset(dma_channel_type *dmax_channely)
@@ -62,22 +62,22 @@ void dma_reset(dma_channel_type *dmax_channely)
dmax_channely->maddr = 0;
temp = (uint32_t)dmax_channely;
-
+
/* dma1 channel */
- DMA1->clr |= (uint32_t)(0x0F << ((((temp & 0xFF) - 0x08) / 0x14) * 4));
+ DMA1->clr |= (uint32_t)(0x0F << ((((temp & 0xFF) - 0x08) / 0x14) * 4));
}
/**
* @brief set the number of data to be transferred.
- * @param dmax_channely:
- * this parameter can be one of the following values:
- * - DMA1_CHANNEL1
- * - DMA1_CHANNEL2
- * - DMA1_CHANNEL3
- * - DMA1_CHANNEL4
- * - DMA1_CHANNEL5
- * - DMA1_CHANNEL6
- * - DMA1_CHANNEL7
+ * @param dmax_channely:
+ * this parameter can be one of the following values:
+ * - DMA1_CHANNEL1
+ * - DMA1_CHANNEL2
+ * - DMA1_CHANNEL3
+ * - DMA1_CHANNEL4
+ * - DMA1_CHANNEL5
+ * - DMA1_CHANNEL6
+ * - DMA1_CHANNEL7
* @param data_number: the number of data to be transferred (0x0000~0xFFFFFFFF).
* @retval none.
*/
@@ -88,15 +88,15 @@ void dma_data_number_set(dma_channel_type *dmax_channely, uint32_t data_number)
/**
* @brief get the number of data to be transferred.
- * @param dmax_channely:
- * this parameter can be one of the following values:
- * - DMA1_CHANNEL1
- * - DMA1_CHANNEL2
- * - DMA1_CHANNEL3
- * - DMA1_CHANNEL4
- * - DMA1_CHANNEL5
- * - DMA1_CHANNEL6
- * - DMA1_CHANNEL7
+ * @param dmax_channely:
+ * this parameter can be one of the following values:
+ * - DMA1_CHANNEL1
+ * - DMA1_CHANNEL2
+ * - DMA1_CHANNEL3
+ * - DMA1_CHANNEL4
+ * - DMA1_CHANNEL5
+ * - DMA1_CHANNEL6
+ * - DMA1_CHANNEL7
* @retval the number value.
*/
uint16_t dma_data_number_get(dma_channel_type *dmax_channely)
@@ -105,22 +105,22 @@ uint16_t dma_data_number_get(dma_channel_type *dmax_channely)
}
/**
- * @brief enable or disable dma interrupt.
- * @param dmax_channely:
- * this parameter can be one of the following values:
- * - DMA1_CHANNEL1
- * - DMA1_CHANNEL2
- * - DMA1_CHANNEL3
- * - DMA1_CHANNEL4
- * - DMA1_CHANNEL5
- * - DMA1_CHANNEL6
- * - DMA1_CHANNEL7
- * @param dma_int:
+ * @brief enable or disable dma interrupt.
+ * @param dmax_channely:
+ * this parameter can be one of the following values:
+ * - DMA1_CHANNEL1
+ * - DMA1_CHANNEL2
+ * - DMA1_CHANNEL3
+ * - DMA1_CHANNEL4
+ * - DMA1_CHANNEL5
+ * - DMA1_CHANNEL6
+ * - DMA1_CHANNEL7
+ * @param dma_int:
* this parameter can be any combination of the following values:
- * - DMA_FDT_INT
- * - DMA_HDT_INT
- * - DMA_DTERR_INT
- * @param new_state (TRUE or FALSE)
+ * - DMA_FDT_INT
+ * - DMA_HDT_INT
+ * - DMA_DTERR_INT
+ * @param new_state (TRUE or FALSE)
* @retval none.
*/
void dma_interrupt_enable(dma_channel_type *dmax_channely, uint32_t dma_int, confirm_state new_state)
@@ -137,15 +137,15 @@ void dma_interrupt_enable(dma_channel_type *dmax_channely, uint32_t dma_int, con
/**
* @brief enable or disable dma channel.
- * @param dmax_channely:
- * this parameter can be one of the following values:
- * - DMA1_CHANNEL1
- * - DMA1_CHANNEL2
- * - DMA1_CHANNEL3
- * - DMA1_CHANNEL4
- * - DMA1_CHANNEL5
- * - DMA1_CHANNEL6
- * - DMA1_CHANNEL7
+ * @param dmax_channely:
+ * this parameter can be one of the following values:
+ * - DMA1_CHANNEL1
+ * - DMA1_CHANNEL2
+ * - DMA1_CHANNEL3
+ * - DMA1_CHANNEL4
+ * - DMA1_CHANNEL5
+ * - DMA1_CHANNEL6
+ * - DMA1_CHANNEL7
* @param new_state (TRUE or FALSE).
* @retval none.
*/
@@ -189,22 +189,22 @@ flag_status dma_interrupt_flag_get(uint32_t dmax_flag)
/**
* @brief dma flag get.
* @param dma_flag
- * - DMA1_GL1_FLAG - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
- * - DMA1_GL2_FLAG - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
- * - DMA1_GL3_FLAG - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
- * - DMA1_GL4_FLAG - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
- * - DMA1_GL5_FLAG - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
- * - DMA1_GL6_FLAG - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG
- * - DMA1_GL7_FLAG - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG
+ * - DMA1_GL1_FLAG - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
+ * - DMA1_GL2_FLAG - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
+ * - DMA1_GL3_FLAG - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
+ * - DMA1_GL4_FLAG - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
+ * - DMA1_GL5_FLAG - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
+ * - DMA1_GL6_FLAG - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG
+ * - DMA1_GL7_FLAG - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG
* @retval state of dma flag.
*/
flag_status dma_flag_get(uint32_t dmax_flag)
-{
+{
uint32_t temp = 0;
-
- temp = DMA1->sts;
- if((temp & dmax_flag) != RESET)
+ temp = DMA1->sts;
+
+ if((temp & dmax_flag) != RESET)
{
return SET;
}
@@ -217,19 +217,19 @@ flag_status dma_flag_get(uint32_t dmax_flag)
/**
* @brief dma flag clear.
* @param dma_flag
- * this parameter can be one of the following values:
- * - DMA1_GL1_FLAG - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
- * - DMA1_GL2_FLAG - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
- * - DMA1_GL3_FLAG - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
- * - DMA1_GL4_FLAG - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
- * - DMA1_GL5_FLAG - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
- * - DMA1_GL6_FLAG - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG
- * - DMA1_GL7_FLAG - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG
+ * this parameter can be one of the following values:
+ * - DMA1_GL1_FLAG - DMA1_FDT1_FLAG - DMA1_HDT1_FLAG - DMA1_DTERR1_FLAG
+ * - DMA1_GL2_FLAG - DMA1_FDT2_FLAG - DMA1_HDT2_FLAG - DMA1_DTERR2_FLAG
+ * - DMA1_GL3_FLAG - DMA1_FDT3_FLAG - DMA1_HDT3_FLAG - DMA1_DTERR3_FLAG
+ * - DMA1_GL4_FLAG - DMA1_FDT4_FLAG - DMA1_HDT4_FLAG - DMA1_DTERR4_FLAG
+ * - DMA1_GL5_FLAG - DMA1_FDT5_FLAG - DMA1_HDT5_FLAG - DMA1_DTERR5_FLAG
+ * - DMA1_GL6_FLAG - DMA1_FDT6_FLAG - DMA1_HDT6_FLAG - DMA1_DTERR6_FLAG
+ * - DMA1_GL7_FLAG - DMA1_FDT7_FLAG - DMA1_HDT7_FLAG - DMA1_DTERR7_FLAG
* @retval none.
*/
void dma_flag_clear(uint32_t dmax_flag)
{
- DMA1->clr = dmax_flag;
+ DMA1->clr = dmax_flag;
}
/**
@@ -239,29 +239,29 @@ void dma_flag_clear(uint32_t dmax_flag)
*/
void dma_default_para_init(dma_init_type *dma_init_struct)
{
- dma_init_struct->peripheral_base_addr = 0;
- dma_init_struct->memory_base_addr = 0;
- dma_init_struct->direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
- dma_init_struct->buffer_size = 0;
- dma_init_struct->peripheral_inc_enable = FALSE;
- dma_init_struct->memory_inc_enable = FALSE;
- dma_init_struct->peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
- dma_init_struct->memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
- dma_init_struct->loop_mode_enable = FALSE;
- dma_init_struct->priority = DMA_PRIORITY_LOW;
+ dma_init_struct->peripheral_base_addr = 0;
+ dma_init_struct->memory_base_addr = 0;
+ dma_init_struct->direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
+ dma_init_struct->buffer_size = 0;
+ dma_init_struct->peripheral_inc_enable = FALSE;
+ dma_init_struct->memory_inc_enable = FALSE;
+ dma_init_struct->peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
+ dma_init_struct->memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
+ dma_init_struct->loop_mode_enable = FALSE;
+ dma_init_struct->priority = DMA_PRIORITY_LOW;
}
/**
* @brief dma init.
- * @param dmax_channely:
- * this parameter can be one of the following values:
- * - DMA1_CHANNEL1
- * - DMA1_CHANNEL2
- * - DMA1_CHANNEL3
- * - DMA1_CHANNEL4
- * - DMA1_CHANNEL5
- * - DMA1_CHANNEL6
- * - DMA1_CHANNEL7
+ * @param dmax_channely:
+ * this parameter can be one of the following values:
+ * - DMA1_CHANNEL1
+ * - DMA1_CHANNEL2
+ * - DMA1_CHANNEL3
+ * - DMA1_CHANNEL4
+ * - DMA1_CHANNEL5
+ * - DMA1_CHANNEL6
+ * - DMA1_CHANNEL7
* @param dma_init_struct: pointer to a dma_init_type structure.
* @retval none.
*/
@@ -270,13 +270,13 @@ void dma_init(dma_channel_type *dmax_channely, dma_init_type *dma_init_struct)
/* clear ctrl register dtd bit and m2m bit */
dmax_channely->ctrl &= 0xbfef;
dmax_channely->ctrl |= dma_init_struct->direction;
-
- dmax_channely->ctrl_bit.chpl = dma_init_struct->priority;
+
+ dmax_channely->ctrl_bit.chpl = dma_init_struct->priority;
dmax_channely->ctrl_bit.mwidth = dma_init_struct->memory_data_width;
dmax_channely->ctrl_bit.pwidth = dma_init_struct->peripheral_data_width;
- dmax_channely->ctrl_bit.mincm = dma_init_struct->memory_inc_enable;
- dmax_channely->ctrl_bit.pincm = dma_init_struct->peripheral_inc_enable;
- dmax_channely->ctrl_bit.lm = dma_init_struct->loop_mode_enable;
+ dmax_channely->ctrl_bit.mincm = dma_init_struct->memory_inc_enable;
+ dmax_channely->ctrl_bit.pincm = dma_init_struct->peripheral_inc_enable;
+ dmax_channely->ctrl_bit.lm = dma_init_struct->loop_mode_enable;
dmax_channely->dtcnt_bit.cnt = dma_init_struct->buffer_size;
dmax_channely->paddr = dma_init_struct->peripheral_base_addr;
dmax_channely->maddr = dma_init_struct->memory_base_addr;
@@ -284,17 +284,17 @@ void dma_init(dma_channel_type *dmax_channely, dma_init_type *dma_init_struct)
/**
* @brief dmamux init.
* @param dma_x: pointer to a dma_type structure, can be DMA1.
- * @param dmamux_channelx:
- * this parameter can be one of the following values:
- * - DMA1MUX_CHANNEL1
- * - DMA1MUX_CHANNEL2
- * - DMA1MUX_CHANNEL3
- * - DMA1MUX_CHANNEL4
- * - DMA1MUX_CHANNEL5
- * - DMA1MUX_CHANNEL6
- * - DMA1MUX_CHANNEL7
- * @param dmamux_req_sel:
- * this parameter can be one of the following values:
+ * @param dmamux_channelx:
+ * this parameter can be one of the following values:
+ * - DMA1MUX_CHANNEL1
+ * - DMA1MUX_CHANNEL2
+ * - DMA1MUX_CHANNEL3
+ * - DMA1MUX_CHANNEL4
+ * - DMA1MUX_CHANNEL5
+ * - DMA1MUX_CHANNEL6
+ * - DMA1MUX_CHANNEL7
+ * @param dmamux_req_sel:
+ * this parameter can be one of the following values:
* - DMAMUX_DMAREQ_ID_REQ_G1 - DMAMUX_DMAREQ_ID_REQ_G2 - DMAMUX_DMAREQ_ID_REQ_G3 - DMAMUX_DMAREQ_ID_REQ_G4
* - DMAMUX_DMAREQ_ID_ADC1 - DMAMUX_DMAREQ_ID_TMR6_OVERFLOW - DMAMUX_DMAREQ_ID_TMR7_OVERFLOW - DMAMUX_DMAREQ_ID_SPI1_RX
* - DMAMUX_DMAREQ_ID_SPI1_TX - DMAMUX_DMAREQ_ID_SPI2_RX - DMAMUX_DMAREQ_ID_SPI2_TX - DMAMUX_DMAREQ_ID_I2C1_RX
@@ -307,8 +307,8 @@ void dma_init(dma_channel_type *dmax_channely, dma_init_type *dma_init_struct)
* - DMAMUX_DMAREQ_ID_TMR4_CH3 - DMAMUX_DMAREQ_ID_TMR4_CH4 - DMAMUX_DMAREQ_ID_TMR4_OVERFLOW - DMAMUX_DMAREQ_ID_TMR4_TRIG
* - DMAMUX_DMAREQ_ID_TMR9_CH1 - DMAMUX_DMAREQ_ID_TMR9_CH2 - DMAMUX_DMAREQ_ID_TMR9_OVERFLOW - DMAMUX_DMAREQ_ID_TMR9_HALL
* - DMAMUX_DMAREQ_ID_TMR10_CH1 - DMAMUX_DMAREQ_ID_TMR9_TRIG - DMAMUX_DMAREQ_ID_TMR10_OVERFLOW- DMAMUX_DMAREQ_ID_TMR11_CH1
- * - DMAMUX_DMAREQ_ID_TMR11_OVERFLOW
- *
+ * - DMAMUX_DMAREQ_ID_TMR11_OVERFLOW- DMAMUX_DMAREQ_ID_ADC2
+ *
* @retval none.
*/
void dma_flexible_config(dma_type* dma_x, dmamux_channel_type *dmamux_channelx, dmamux_requst_id_sel_type dmamux_req_sel)
@@ -330,17 +330,17 @@ void dmamux_enable(dma_type *dma_x, confirm_state new_state)
/**
* @brief dmamux init.
- * @param dmamux_channelx:
- * this parameter can be one of the following values:
- * - DMA1MUX_CHANNEL1
- * - DMA1MUX_CHANNEL2
- * - DMA1MUX_CHANNEL3
- * - DMA1MUX_CHANNEL4
- * - DMA1MUX_CHANNEL5
- * - DMA1MUX_CHANNEL6
- * - DMA1MUX_CHANNEL7
- * @param dmamux_req_sel:
- * this parameter can be one of the following values:
+ * @param dmamux_channelx:
+ * this parameter can be one of the following values:
+ * - DMA1MUX_CHANNEL1
+ * - DMA1MUX_CHANNEL2
+ * - DMA1MUX_CHANNEL3
+ * - DMA1MUX_CHANNEL4
+ * - DMA1MUX_CHANNEL5
+ * - DMA1MUX_CHANNEL6
+ * - DMA1MUX_CHANNEL7
+ * @param dmamux_req_sel:
+ * this parameter can be one of the following values:
* - DMAMUX_DMAREQ_ID_REQ_G1 - DMAMUX_DMAREQ_ID_REQ_G2 - DMAMUX_DMAREQ_ID_REQ_G3 - DMAMUX_DMAREQ_ID_REQ_G4
* - DMAMUX_DMAREQ_ID_ADC1 - DMAMUX_DMAREQ_ID_TMR6_OVERFLOW - DMAMUX_DMAREQ_ID_TMR7_OVERFLOW - DMAMUX_DMAREQ_ID_SPI1_RX
* - DMAMUX_DMAREQ_ID_SPI1_TX - DMAMUX_DMAREQ_ID_SPI2_RX - DMAMUX_DMAREQ_ID_SPI2_TX - DMAMUX_DMAREQ_ID_I2C1_RX
@@ -353,7 +353,7 @@ void dmamux_enable(dma_type *dma_x, confirm_state new_state)
* - DMAMUX_DMAREQ_ID_TMR4_CH3 - DMAMUX_DMAREQ_ID_TMR4_CH4 - DMAMUX_DMAREQ_ID_TMR4_OVERFLOW - DMAMUX_DMAREQ_ID_TMR4_TRIG
* - DMAMUX_DMAREQ_ID_TMR9_CH1 - DMAMUX_DMAREQ_ID_TMR9_CH2 - DMAMUX_DMAREQ_ID_TMR9_OVERFLOW - DMAMUX_DMAREQ_ID_TMR9_HALL
* - DMAMUX_DMAREQ_ID_TMR10_CH1 - DMAMUX_DMAREQ_ID_TMR9_TRIG - DMAMUX_DMAREQ_ID_TMR10_OVERFLOW- DMAMUX_DMAREQ_ID_TMR11_CH1
- * - DMAMUX_DMAREQ_ID_TMR11_OVERFLOW
+ * - DMAMUX_DMAREQ_ID_TMR11_OVERFLOW- DMAMUX_DMAREQ_ID_ADC2
* @retval none.
*/
void dmamux_init(dmamux_channel_type *dmamux_channelx, dmamux_requst_id_sel_type dmamux_req_sel)
@@ -377,25 +377,25 @@ void dmamux_sync_default_para_init(dmamux_sync_init_type *dmamux_sync_init_struc
/**
* @brief dmamux synchronization config.
- * @param dmamux_channelx:
- * this parameter can be one of the following values:
- * - DMA1MUX_CHANNEL1
- * - DMA1MUX_CHANNEL2
- * - DMA1MUX_CHANNEL3
- * - DMA1MUX_CHANNEL4
- * - DMA1MUX_CHANNEL5
- * - DMA1MUX_CHANNEL6
- * - DMA1MUX_CHANNEL7
+ * @param dmamux_channelx:
+ * this parameter can be one of the following values:
+ * - DMA1MUX_CHANNEL1
+ * - DMA1MUX_CHANNEL2
+ * - DMA1MUX_CHANNEL3
+ * - DMA1MUX_CHANNEL4
+ * - DMA1MUX_CHANNEL5
+ * - DMA1MUX_CHANNEL6
+ * - DMA1MUX_CHANNEL7
* @param dmamux_sync_init_struct: ointer to a dmamux_sync_init_type structure.
* @retval none.
- */
+ */
void dmamux_sync_config(dmamux_channel_type *dmamux_channelx, dmamux_sync_init_type *dmamux_sync_init_struct)
{
dmamux_channelx->muxctrl_bit.syncsel = dmamux_sync_init_struct->sync_signal_sel;
dmamux_channelx->muxctrl_bit.syncpol = dmamux_sync_init_struct->sync_polarity;
dmamux_channelx->muxctrl_bit.reqcnt = dmamux_sync_init_struct->sync_request_number - 1;
dmamux_channelx->muxctrl_bit.evtgen = dmamux_sync_init_struct->sync_event_enable;
- dmamux_channelx->muxctrl_bit.syncen = dmamux_sync_init_struct->sync_enable;
+ dmamux_channelx->muxctrl_bit.syncen = dmamux_sync_init_struct->sync_enable;
}
/**
@@ -413,15 +413,15 @@ void dmamux_generator_default_para_init(dmamux_gen_init_type *dmamux_gen_init_st
/**
* @brief dmamux request generator init.
- * @param dmamux_gen_x :
- * this parameter can be one of the following values:
+ * @param dmamux_gen_x :
+ * this parameter can be one of the following values:
* - DMA1MUX_GENERATOR1
* - DMA1MUX_GENERATOR2
* - DMA1MUX_GENERATOR3
* - DMA1MUX_GENERATOR4
* @param dmamux_gen_init_struct: pointer to a dmamux_gen_init_type structure which will be initialized.
* @retval none.
- */
+ */
void dmamux_generator_config(dmamux_generator_type *dmamux_gen_x, dmamux_gen_init_type *dmamux_gen_init_struct)
{
dmamux_gen_x->gctrl_bit.sigsel = dmamux_gen_init_struct->gen_signal_sel;
@@ -432,9 +432,9 @@ void dmamux_generator_config(dmamux_generator_type *dmamux_gen_x, dmamux_gen_ini
/**
* @brief enable or disable the dmamux sync interrupts.
- * @param dmamux_channelx:
- * this parameter can be one of the following values:
- * - DMA1MUX_CHANNEL1
+ * @param dmamux_channelx:
+ * this parameter can be one of the following values:
+ * - DMA1MUX_CHANNEL1
* - DMA1MUX_CHANNEL2
* - DMA1MUX_CHANNEL3
* - DMA1MUX_CHANNEL4
@@ -459,7 +459,7 @@ void dmamux_sync_interrupt_enable(dmamux_channel_type *dmamux_channelx, confirm_
/**
* @brief enable or disable the dmamux request generator interrupts.
* @param dmamux_gen_x : pointer to a dmamux_generator_type structure.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - DMA1MUX_GENERATOR1
* - DMA1MUX_GENERATOR2
* - DMA1MUX_GENERATOR3
@@ -485,17 +485,17 @@ void dmamux_generator_interrupt_enable(dmamux_generator_type *dmamux_gen_x, conf
* @param flag
* this parameter can be any combination of the following values:
* - DMAMUX_SYNC_OV1_FLAG
- * - DMAMUX_SYNC_OV2_FLAG
+ * - DMAMUX_SYNC_OV2_FLAG
* - DMAMUX_SYNC_OV3_FLAG
- * - DMAMUX_SYNC_OV4_FLAG
+ * - DMAMUX_SYNC_OV4_FLAG
* - DMAMUX_SYNC_OV5_FLAG
- * - DMAMUX_SYNC_OV6_FLAG
- * - DMAMUX_SYNC_OV7_FLAG
+ * - DMAMUX_SYNC_OV6_FLAG
+ * - DMAMUX_SYNC_OV7_FLAG
* @retval state of dmamux sync flag.
*/
flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag)
{
- if((dma_x->muxsyncsts & flag) != RESET)
+ if((dma_x->muxsyncsts & flag) != RESET)
{
return SET;
}
@@ -526,13 +526,13 @@ flag_status dmamux_sync_interrupt_flag_get(dma_type *dma_x, uint32_t flag)
uint32_t index = 0;
uint32_t tmpreg = 0, enablestatus = 0;
uint32_t regoffset = 0x4;
-
+
while((sync_int_temp & 0x00000001) == RESET)
{
sync_int_temp = sync_int_temp >> 1;
index++;
}
-
+
tmpreg = *(uint32_t*)(DMA1MUX_BASE + (index * regoffset));
if((tmpreg & (uint32_t)0x00000100) != (uint32_t)RESET)
@@ -543,7 +543,7 @@ flag_status dmamux_sync_interrupt_flag_get(dma_type *dma_x, uint32_t flag)
{
enablestatus = RESET;
}
-
+
if(((dma_x->muxsyncsts & flag) != (uint32_t)RESET) && (enablestatus != RESET))
{
bitstatus = SET;
@@ -553,7 +553,7 @@ flag_status dmamux_sync_interrupt_flag_get(dma_type *dma_x, uint32_t flag)
bitstatus = RESET;
}
- return bitstatus;
+ return bitstatus;
}
/**
@@ -562,17 +562,17 @@ flag_status dmamux_sync_interrupt_flag_get(dma_type *dma_x, uint32_t flag)
* @param flag
* this parameter can be any combination of the following values:
* - DMAMUX_SYNC_OV1_FLAG
- * - DMAMUX_SYNC_OV2_FLAG
+ * - DMAMUX_SYNC_OV2_FLAG
* - DMAMUX_SYNC_OV3_FLAG
- * - DMAMUX_SYNC_OV4_FLAG
+ * - DMAMUX_SYNC_OV4_FLAG
* - DMAMUX_SYNC_OV5_FLAG
- * - DMAMUX_SYNC_OV6_FLAG
- * - DMAMUX_SYNC_OV7_FLAG
+ * - DMAMUX_SYNC_OV6_FLAG
+ * - DMAMUX_SYNC_OV7_FLAG
* @retval none.
*/
void dmamux_sync_flag_clear(dma_type *dma_x, uint32_t flag)
{
- dma_x->muxsyncclr = flag;
+ dma_x->muxsyncclr = flag;
}
/**
@@ -581,21 +581,21 @@ void dmamux_sync_flag_clear(dma_type *dma_x, uint32_t flag)
* @param flag
* this parameter can be any combination of the following values:
* - DMAMUX_GEN_TRIG_OV1_FLAG
- * - DMAMUX_GEN_TRIG_OV2_FLAG
+ * - DMAMUX_GEN_TRIG_OV2_FLAG
* - DMAMUX_GEN_TRIG_OV3_FLAG
- * - DMAMUX_GEN_TRIG_OV4_FLAG
+ * - DMAMUX_GEN_TRIG_OV4_FLAG
* @retval state of dmamux sync flag.
*/
flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag)
{
if((dma_x->muxgsts & flag) != RESET)
{
- return SET;
+ return SET;
}
else
{
- return RESET;
- }
+ return RESET;
+ }
}
/**
@@ -616,15 +616,15 @@ flag_status dmamux_generator_interrupt_flag_get(dma_type *dma_x, uint32_t flag)
uint32_t index = 0;
uint32_t tmpreg = 0, enablestatus = 0;
uint32_t regoffset = 0x4;
-
+
while((sync_int_temp & 0x00000001) == RESET)
{
sync_int_temp = sync_int_temp >> 1;
index++;
}
-
+
tmpreg = *(uint32_t*)(DMA1MUX_GENERATOR1_BASE + (index * regoffset));
-
+
if((tmpreg & (uint32_t)0x00000100) != (uint32_t)RESET)
{
enablestatus = SET;
@@ -642,8 +642,8 @@ flag_status dmamux_generator_interrupt_flag_get(dma_type *dma_x, uint32_t flag)
{
bitstatus = RESET;
}
-
- return bitstatus;
+
+ return bitstatus;
}
/**
@@ -652,14 +652,14 @@ flag_status dmamux_generator_interrupt_flag_get(dma_type *dma_x, uint32_t flag)
* @param flag
* this parameter can be any combination of the following values:
* - DMAMUX_GEN_TRIG_OV1_FLAG
- * - DMAMUX_GEN_TRIG_OV2_FLAG
+ * - DMAMUX_GEN_TRIG_OV2_FLAG
* - DMAMUX_GEN_TRIG_OV3_FLAG
- * - DMAMUX_GEN_TRIG_OV4_FLAG
+ * - DMAMUX_GEN_TRIG_OV4_FLAG
* @retval none.
*/
void dmamux_generator_flag_clear(dma_type *dma_x, uint32_t flag)
{
- dma_x->muxgclr = flag;
+ dma_x->muxgclr = flag;
}
/**
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_ertc.c b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_ertc.c
index 9eae855f773..55edaad7a2c 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_ertc.c
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_ertc.c
@@ -96,15 +96,9 @@ error_status ertc_wait_update(void)
{
uint32_t timeout = ERTC_TIMEOUT * 2;
- /* disable write protection */
- ertc_write_protect_disable();
-
/* clear updf flag */
ERTC->sts = ~(ERTC_UPDF_FLAG | 0x00000080) | (ERTC->sts_bit.imen << 7);
- /* enable write protection */
- ertc_write_protect_enable();
-
while(ERTC->sts_bit.updf == 0)
{
if(timeout == 0)
@@ -162,9 +156,6 @@ error_status ertc_init_mode_enter(void)
{
uint32_t timeout = ERTC_TIMEOUT * 2;
- /* disable write protection */
- ertc_write_protect_disable();
-
if(ERTC->sts_bit.imf == 0)
{
/* enter init mode */
@@ -195,9 +186,6 @@ error_status ertc_init_mode_enter(void)
void ertc_init_mode_exit(void)
{
ERTC->sts = 0xFFFFFF7F;
-
- /* wait register update finish */
- ertc_wait_update();
}
/**
@@ -331,11 +319,11 @@ error_status ertc_date_set(uint8_t year, uint8_t month, uint8_t date, uint8_t we
return ERROR;
}
- /* Set the ertc_DR register */
+ /* set the ertc_date register */
ERTC->date = reg.date;
/* exit init mode */
- ertc_init_mode_exit();
+ ertc_init_mode_exit();
if(ERTC->ctrl_bit.dren == 0)
{
@@ -545,7 +533,7 @@ void ertc_alarm_set(ertc_alarm_type alarm_x, uint8_t week_date, uint8_t hour, ui
{
reg.ala = ERTC->alb;
}
-
+
reg.ala_bit.d = ertc_num_to_bcd(week_date);
reg.ala_bit.h = ertc_num_to_bcd(hour);
reg.ala_bit.m = ertc_num_to_bcd(min);
@@ -722,8 +710,8 @@ uint32_t ertc_alarm_sub_second_get(ertc_alarm_type alarm_x)
* - ERTC_WAT_CLK_ERTCCLK_DIV8: ERTC_CLK / 8.
* - ERTC_WAT_CLK_ERTCCLK_DIV4: ERTC_CLK / 4.
* - ERTC_WAT_CLK_ERTCCLK_DIV2: ERTC_CLK / 2.
- * - ERTC_WAT_CLK_CK_A_16BITS: CK_A, wakeup counter = ERTC_WAT
- * - ERTC_WAT_CLK_CK_A_17BITS: CK_A, wakeup counter = ERTC_WAT + 65535.
+ * - ERTC_WAT_CLK_CK_B_16BITS: CK_B, wakeup counter = ERTC_WAT
+ * - ERTC_WAT_CLK_CK_B_17BITS: CK_B, wakeup counter = ERTC_WAT + 65535.
* @retval none.
*/
void ertc_wakeup_clock_set(ertc_wakeup_clock_type clock)
@@ -777,7 +765,7 @@ error_status ertc_wakeup_enable(confirm_state new_state)
if(new_state == FALSE)
{
- if(ertc_wait_flag(ERTC_ALAWF_FLAG, RESET) != SUCCESS)
+ if(ertc_wait_flag(ERTC_WATWF_FLAG, RESET) != SUCCESS)
{
return ERROR;
}
@@ -1436,7 +1424,7 @@ flag_status ertc_flag_get(uint32_t flag)
flag_status ertc_interrupt_flag_get(uint32_t flag)
{
__IO uint32_t iten = 0;
-
+
switch(flag)
{
case ERTC_ALAF_FLAG:
@@ -1455,7 +1443,7 @@ flag_status ertc_interrupt_flag_get(uint32_t flag)
case ERTC_TP2F_FLAG:
iten = ERTC->tamp_bit.tpien;
break;
-
+
default:
break;
}
@@ -1514,13 +1502,7 @@ void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data)
reg = ERTC_BASE + 0x50 + (dt * 4);
- /* disable write protection */
- ertc_write_protect_disable();
-
*(__IO uint32_t *)reg = data;
-
- /* enable write protection */
- ertc_write_protect_enable();
}
/**
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_exint.c b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_exint.c
index 2a44425e546..3f48747e93e 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_exint.c
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_exint.c
@@ -5,11 +5,11 @@
**************************************************************************
* Copyright notice & Disclaimer
*
- * The software Board Support Package (BSP) that is made available to
- * download from Artery official website is the copyrighted work of Artery.
- * Artery authorizes customers to use, copy, and distribute the BSP
- * software and its related documentation for the purpose of design and
- * development in conjunction with Artery microcontrollers. Use of the
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -210,7 +210,7 @@ void exint_software_interrupt_event_generate(uint32_t exint_line)
* - EXINT_LINE_22
* @param new_state: new state of exint interrupt.
* this parameter can be: TRUE or FALSE.
- * @retval none
+ * @retval none
*/
void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state)
{
@@ -235,7 +235,7 @@ void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state)
* - EXINT_LINE_22
* @param new_state: new state of exint event.
* this parameter can be: TRUE or FALSE.
- * @retval none
+ * @retval none
*/
void exint_event_enable(uint32_t exint_line, confirm_state new_state)
{
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_flash.c b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_flash.c
index dbfdc531663..b274da766d9 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_flash.c
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_flash.c
@@ -5,11 +5,11 @@
**************************************************************************
* Copyright notice & Disclaimer
*
- * The software Board Support Package (BSP) that is made available to
- * download from Artery official website is the copyrighted work of Artery.
- * Artery authorizes customers to use, copy, and distribute the BSP
- * software and its related documentation for the purpose of design and
- * development in conjunction with Artery microcontrollers. Use of the
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -823,7 +823,7 @@ flash_status_type flash_otp_data_program(uint32_t address, uint8_t *data_buf, ui
/* wait for operation to be completed */
status = flash_operation_wait_for(PROGRAMMING_TIMEOUT);
if(status != FLASH_OPERATE_DONE)
- break;
+ break;
}
/* disable the fprgm bit */
FLASH->ctrl_bit.fprgm = FALSE;
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_gpio.c b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_gpio.c
index c9f7793f243..eb139f7c214 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_gpio.c
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_gpio.c
@@ -5,11 +5,11 @@
**************************************************************************
* Copyright notice & Disclaimer
*
- * The software Board Support Package (BSP) that is made available to
- * download from Artery official website is the copyrighted work of Artery.
- * Artery authorizes customers to use, copy, and distribute the BSP
- * software and its related documentation for the purpose of design and
- * development in conjunction with Artery microcontrollers. Use of the
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -32,17 +32,17 @@
* @brief GPIO driver modules
* @{
*/
-
+
#ifdef GPIO_MODULE_ENABLED
/** @defgroup GPIO_private_functions
* @{
*/
-
-/**
+
+/**
* @brief reset the gpio register
* @param gpio_x: to select the gpio peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @retval none
*/
@@ -73,7 +73,7 @@ void gpio_reset(gpio_type *gpio_x)
/**
* @brief initialize the gpio peripheral.
* @param gpio_x: to select the gpio peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param gpio_init_struct: pointer to gpio init structure.
* @retval none
@@ -81,22 +81,22 @@ void gpio_reset(gpio_type *gpio_x)
void gpio_init(gpio_type *gpio_x, gpio_init_type *gpio_init_struct)
{
uint16_t pinx_value, pin_index = 0;
-
+
pinx_value = (uint16_t)gpio_init_struct->gpio_pins;
-
+
while(pinx_value > 0)
{
if(pinx_value & 0x01)
{
gpio_x->cfgr &= (uint32_t)~(0x03 << (pin_index * 2));
gpio_x->cfgr |= (uint32_t)(gpio_init_struct->gpio_mode << (pin_index * 2));
-
+
gpio_x->omode &= (uint32_t)~(0x01 << (pin_index));
gpio_x->omode |= (uint32_t)(gpio_init_struct->gpio_out_type << (pin_index));
-
+
gpio_x->odrvr &= (uint32_t)~(0x03 << (pin_index * 2));
gpio_x->odrvr |= (uint32_t)(gpio_init_struct->gpio_drive_strength << (pin_index * 2));
-
+
gpio_x->pull &= (uint32_t)~(0x03 << (pin_index * 2));
gpio_x->pull |= (uint32_t)(gpio_init_struct->gpio_pull << (pin_index * 2));
}
@@ -123,10 +123,10 @@ void gpio_default_para_init(gpio_init_type *gpio_init_struct)
/**
* @brief read the specified input port pin.
* @param gpio_x: to select the gpio peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param pins: gpio pin number
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - GPIO_PINS_0
* - GPIO_PINS_1
* - GPIO_PINS_2
@@ -164,7 +164,7 @@ flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins)
/**
* @brief read the specified gpio input data port.
* @param gpio_x: to select the gpio peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @retval gpio input data port value.
*/
@@ -176,10 +176,10 @@ uint16_t gpio_input_data_read(gpio_type *gpio_x)
/**
* @brief read the specified output port pin.
* @param gpio_x: to select the gpio peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param pins: gpio pin number
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - GPIO_PINS_0
* - GPIO_PINS_1
* - GPIO_PINS_2
@@ -217,7 +217,7 @@ flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins)
/**
* @brief read the specified gpio ouput data port.
* @param gpio_x: to select the gpio peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @retval gpio input data port value.
*/
@@ -229,7 +229,7 @@ uint16_t gpio_output_data_read(gpio_type *gpio_x)
/**
* @brief set the selected data port bits.
* @param gpio_x: to select the gpio peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param pins: gpio pin number
* parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
@@ -260,7 +260,7 @@ void gpio_bits_set(gpio_type *gpio_x, uint16_t pins)
/**
* @brief clear the selected data port bits.
* @param gpio_x: to select the gpio peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param pins: gpio pin number
* parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
@@ -291,7 +291,7 @@ void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins)
/**
* @brief toggle the selected data port bits.
* @param gpio_x: to select the gpio peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param pins: gpio pin number
* parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
@@ -322,7 +322,7 @@ void gpio_bits_toggle(gpio_type *gpio_x, uint16_t pins)
/**
* @brief set or clear the selected data port bit.
* @param gpio_x: to select the gpio peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param pins: gpio pin number
* parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
@@ -361,7 +361,7 @@ void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state)
/**
* @brief write data to the specified gpio data port.
* @param gpio_x: to select the gpio peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param port_value: specifies the value to be written to the port output data register.
* @retval none
@@ -374,7 +374,7 @@ void gpio_port_wirte(gpio_type *gpio_x, uint16_t port_value)
/**
* @brief write protect gpio pins configuration registers.
* @param gpio_x: to select the gpio peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param pins: gpio pin number
* this parameter can be any combination of the following:
@@ -417,7 +417,7 @@ void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins)
/**
* @brief enable or disable gpio pins huge driven.
* @param gpio_x: to select the gpio peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param pins: gpio pin number
* parameter can be any combination of gpio_pin_x, gpio_pin_x as following values:
@@ -457,10 +457,10 @@ void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_stat
/**
* @brief configure the pin's muxing function.
* @param gpio_x: to select the gpio peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* GPIOA, GPIOB, GPIOC, GPIOF.
* @param gpio_pin_source: specifies the pin for the muxing function.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - GPIO_PINS_SOURCE0
* - GPIO_PINS_SOURCE1
* - GPIO_PINS_SOURCE2
@@ -478,7 +478,7 @@ void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_stat
* - GPIO_PINS_SOURCE14
* - GPIO_PINS_SOURCE15
* @param gpio_mux: select the pin to used as muxing function.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - GPIO_MUX_0
* - GPIO_MUX_1
* - GPIO_MUX_2
@@ -505,15 +505,15 @@ void gpio_pin_mux_config(gpio_type *gpio_x, gpio_pins_source_type gpio_pin_sourc
temp = ((uint32_t)(gpio_mux) << ((uint32_t)((uint32_t)gpio_pin_source & (uint32_t)0x07) * 4));
if(gpio_pin_source >> 0x03)
{
- gpio_x->muxh &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)gpio_pin_source & (uint32_t)0x07) * 4));
- temp_2 = gpio_x->muxh | temp;
- gpio_x->muxh = temp_2;
+ temp_2 = gpio_x->muxh;
+ temp_2 &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)gpio_pin_source & (uint32_t)0x07) * 4));
+ gpio_x->muxh = temp_2 | temp;
}
else
{
- gpio_x->muxl &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)gpio_pin_source & (uint32_t)0x07) * 4));
- temp_2 = gpio_x->muxl | temp;
- gpio_x->muxl = temp_2;
+ temp_2 = gpio_x->muxl;
+ temp_2 &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)gpio_pin_source & (uint32_t)0x07) * 4));
+ gpio_x->muxl = temp_2 | temp;
}
}
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_i2c.c b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_i2c.c
index 54cd89a50dc..666acad0637 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_i2c.c
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_i2c.c
@@ -5,11 +5,11 @@
**************************************************************************
* Copyright notice & Disclaimer
*
- * The software Board Support Package (BSP) that is made available to
- * download from Artery official website is the copyrighted work of Artery.
- * Artery authorizes customers to use, copy, and distribute the BSP
- * software and its related documentation for the purpose of design and
- * development in conjunction with Artery microcontrollers. Use of the
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -39,10 +39,10 @@
* @{
*/
-/**
+/**
* @brief reset the i2c register
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @retval none
*/
@@ -60,10 +60,10 @@ void i2c_reset(i2c_type *i2c_x)
}
}
-/**
+/**
* @brief init i2c digit filters and clock control register.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param dfilters: number of digit filters (0x00~0x0F).
* @param clk: i2c clock control register (0x00000000~0xFFFFFFFF).
@@ -73,21 +73,21 @@ void i2c_init(i2c_type *i2c_x, uint8_t dfilters, uint32_t clk)
{
/* disable i2c peripheral */
i2c_x->ctrl1_bit.i2cen = FALSE;
-
+
/* write clkctrl register*/
i2c_x->clkctrl = clk;
-
- /* write digital filter register*/
+
+ /* write digital filter register*/
i2c_x->ctrl1_bit.dflt = dfilters;
}
-/**
+/**
* @brief config i2c own address 1.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param mode: i2c address mode.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - I2C_ADDRESS_MODE_7BIT: 7bit address.
* - I2C_ADDRESS_MODE_10BIT: 10bit address.
* @param address: own address 1, such as 0xB0.
@@ -97,22 +97,22 @@ void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t
{
/* config address mode */
i2c_x->oaddr1_bit.addr1mode = mode;
-
+
/* config address */
i2c_x->oaddr1_bit.addr1 = address & 0x03FF;
-
- /* enable address */
+
+ /* enable address */
i2c_x->oaddr1_bit.addr1en = TRUE;
}
/**
* @brief config i2c own address 2 and mask.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param address: own address 1, such as 0xC0.
* @param mask: own address 2 mask.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - I2C_ADDR2_NOMASK: compare bit [7:1].
* - I2C_ADDR2_MASK01: only compare bit [7:2].
* - I2C_ADDR2_MASK02: only compare bit [7:3].
@@ -126,14 +126,14 @@ void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t
void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address, i2c_addr2_mask_type mask)
{
i2c_x->oaddr2_bit.addr2mask = mask;
-
+
i2c_x->oaddr2_bit.addr2 = (address >> 1) & 0x7F;
}
/**
* @brief enable or disable own address 2.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE).
* @retval none
@@ -143,13 +143,13 @@ void i2c_own_address2_enable(i2c_type *i2c_x, confirm_state new_state)
i2c_x->oaddr2_bit.addr2en = new_state;
}
-/**
+/**
* @brief enable or disable smbus mode.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param mode: smbus device mode.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - I2C_SMBUS_MODE_DEVICE: smbus device.
* - I2C_SMBUS_MODE_HOST: smbus host.
* @param new_state (TRUE or FALSE).
@@ -170,10 +170,10 @@ void i2c_smbus_enable(i2c_type *i2c_x, i2c_smbus_mode_type mode, confirm_state n
}
}
-/**
+/**
* @brief enable or disable peripheral.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE).
* @retval none
@@ -186,7 +186,7 @@ void i2c_enable(i2c_type *i2c_x, confirm_state new_state)
/**
* @brief enable or disable clock stretch.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE).
* @retval none
@@ -199,7 +199,7 @@ void i2c_clock_stretch_enable(i2c_type *i2c_x, confirm_state new_state)
/**
* @brief enable or disable ack.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE).
* @retval none.
@@ -212,20 +212,20 @@ void i2c_ack_enable(i2c_type *i2c_x, confirm_state new_state)
/**
* @brief enable or disable 10-bit address mode (master transfer).
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE).
* @retval none
*/
void i2c_addr10_mode_enable(i2c_type *i2c_x, confirm_state new_state)
-{
+{
i2c_x->ctrl2_bit.addr10 = new_state;
}
/**
* @brief config the slave address to be transmitted.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param address: slave address.
* @retval none
@@ -238,7 +238,7 @@ void i2c_transfer_addr_set(i2c_type *i2c_x, uint16_t address)
/**
* @brief get the slave address to be transmitted.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @retval slave address
*/
@@ -246,14 +246,14 @@ uint16_t i2c_transfer_addr_get(i2c_type *i2c_x)
{
return i2c_x->ctrl2_bit.saddr;
}
-
+
/**
* @brief config the master transfer direction.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param i2c_direction: transfer request direction.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - I2C_DIR_TRANSMIT: master request a write transfer.
* - I2C_DIR_RECEIVE: master request a read transfer.
* @retval none
@@ -266,7 +266,7 @@ void i2c_transfer_dir_set(i2c_type *i2c_x, i2c_transfer_dir_type i2c_direction)
/**
* @brief get the i2c slave received direction.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @retval the value of the received direction.
*/
@@ -279,13 +279,13 @@ i2c_transfer_dir_type i2c_transfer_dir_get(i2c_type *i2c_x)
else
{
return I2C_DIR_RECEIVE;
- }
+ }
}
/**
* @brief get the i2c slave matched address.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @retval slave matched address.
*/
@@ -297,33 +297,33 @@ uint8_t i2c_matched_addr_get(i2c_type *i2c_x)
/**
* @brief enable or disable auto send stop mode.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE).
* @retval none
*/
void i2c_auto_stop_enable(i2c_type *i2c_x, confirm_state new_state)
-{
+{
i2c_x->ctrl2_bit.astopen = new_state;
}
/**
* @brief enable or disable cnt reload mode.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE).
* @retval none
*/
void i2c_reload_enable(i2c_type *i2c_x, confirm_state new_state)
-{
+{
i2c_x->ctrl2_bit.rlden = new_state;
}
/**
* @brief config the transfer cnt .
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param cnt: transfer cnt.
* @retval none
@@ -331,13 +331,13 @@ void i2c_reload_enable(i2c_type *i2c_x, confirm_state new_state)
void i2c_cnt_set(i2c_type *i2c_x, uint8_t cnt)
{
i2c_x->ctrl2_bit.cnt = cnt;
-}
+}
/**
- * @brief enable or disable read 10-bit header, this mode
+ * @brief enable or disable read 10-bit header, this mode
* only used in 10-bit address mode read.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE).
* @retval none
@@ -350,7 +350,7 @@ void i2c_addr10_header_enable(i2c_type *i2c_x, confirm_state new_state)
/**
* @brief enable or disable general call mode.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE).
* @retval none
@@ -363,12 +363,12 @@ void i2c_general_call_enable(i2c_type *i2c_x, confirm_state new_state)
/**
* @brief drives the smbus alert pin high or low.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param level
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - I2C_SMBUS_ALERT_LOW: smbus alert set low.
- * - I2C_SMBUS_ALERT_HIGH: smbus alert set high.
+ * - I2C_SMBUS_ALERT_HIGH: smbus alert set high.
* @retval none
*/
void i2c_smbus_alert_set(i2c_type *i2c_x, i2c_smbus_alert_set_type level)
@@ -379,7 +379,7 @@ void i2c_smbus_alert_set(i2c_type *i2c_x, i2c_smbus_alert_set_type level)
/**
* @brief enable or disable slave data control.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE).
* @retval none
@@ -392,33 +392,33 @@ void i2c_slave_data_ctrl_enable(i2c_type *i2c_x, confirm_state new_state)
/**
* @brief enable or disable pec calculate.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE).
* @retval none
*/
void i2c_pec_calculate_enable(i2c_type *i2c_x, confirm_state new_state)
{
- i2c_x->ctrl1_bit.pecen = new_state;
+ i2c_x->ctrl1_bit.pecen = new_state;
}
/**
* @brief enable or disable pec transfer.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE).
* @retval none
*/
void i2c_pec_transmit_enable(i2c_type *i2c_x, confirm_state new_state)
{
- i2c_x->ctrl2_bit.pecten = new_state;
+ i2c_x->ctrl2_bit.pecten = new_state;
}
/**
* @brief get the i2c pec value.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @retval the value of the pec.
*/
@@ -430,85 +430,85 @@ uint8_t i2c_pec_value_get(i2c_type *i2c_x)
/**
* @brief config the i2c bus timeout.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
- * @param timeout: timeout (0x0000~0x0FFF).
+ * @param timeout: timeout (0x0000~0x0FFF).
* @retval none
*/
void i2c_timeout_set(i2c_type *i2c_x, uint16_t timeout)
{
- i2c_x->timeout_bit.totime = timeout;
+ i2c_x->timeout_bit.totime = timeout;
}
/**
* @brief config the bus timeout detcet level.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param level
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - I2C_TIMEOUT_DETCET_HIGH: detect high level timeout.
- * - I2C_TIMEOUT_DETCET_LOW: detect low level timeout.
+ * - I2C_TIMEOUT_DETCET_LOW: detect low level timeout.
* @retval none
*/
void i2c_timeout_detcet_set(i2c_type *i2c_x, i2c_timeout_detcet_type mode)
{
- i2c_x->timeout_bit.tomode = mode;
+ i2c_x->timeout_bit.tomode = mode;
}
/**
* @brief enable or disable bus timeout.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE).
* @retval none
*/
void i2c_timeout_enable(i2c_type *i2c_x, confirm_state new_state)
{
- i2c_x->timeout_bit.toen = new_state;
+ i2c_x->timeout_bit.toen = new_state;
}
/**
* @brief config the i2c extend bus timeout.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param timeout: extend timeout (0x0000~0x0FFF).
* @retval none
*/
void i2c_ext_timeout_set(i2c_type *i2c_x, uint16_t timeout)
{
- i2c_x->timeout_bit.exttime = timeout;
+ i2c_x->timeout_bit.exttime = timeout;
}
/**
* @brief enable or disable extend bus timeout.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param new_state (TRUE or FALSE).
* @retval none
*/
void i2c_ext_timeout_enable(i2c_type *i2c_x, confirm_state new_state)
{
- i2c_x->timeout_bit.exten = new_state;
+ i2c_x->timeout_bit.exten = new_state;
}
/**
* @brief enable or disable interrupts.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param i2c_int: interrupts sources.
- * this parameter can be one of the following values:
- * - I2C_TD_INT: transmit data interrupt.
- * - I2C_RD_INT: receive data interrupt.
+ * this parameter can be one of the following values:
+ * - I2C_TD_INT: transmit data interrupt.
+ * - I2C_RD_INT: receive data interrupt.
* - I2C_ADDR_INT: address match interrupt.
* - I2C_ACKFIAL_INT: ack fail interrupt.
* - I2C_STOP_INT: stop detect interrupt.
- * - I2C_TDC_INT: transmit data complete interrupt.
- * - I2C_ERR_INT: bus error interrupt.
+ * - I2C_TDC_INT: transmit data complete interrupt.
+ * - I2C_ERR_INT: bus error interrupt.
* @param new_state (TRUE or FALSE).
* @retval none
*/
@@ -527,21 +527,21 @@ void i2c_interrupt_enable(i2c_type *i2c_x, uint32_t source, confirm_state new_st
/**
* @brief get interrupt status
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param source
- * this parameter can be one of the following values:
- * - I2C_TD_INT: transmit data interrupt.
- * - I2C_RD_INT: receive data interrupt.
+ * this parameter can be one of the following values:
+ * - I2C_TD_INT: transmit data interrupt.
+ * - I2C_RD_INT: receive data interrupt.
* - I2C_ADDR_INT: address match interrupt.
* - I2C_ACKFIAL_INT: ack fail interrupt.
* - I2C_STOP_INT: stop detect interrupt.
- * - I2C_TDC_INT: transmit data complete interrupt.
- * - I2C_ERR_INT: bus error interrupt.
+ * - I2C_TDC_INT: transmit data complete interrupt.
+ * - I2C_ERR_INT: bus error interrupt.
* @retval flag_status (SET or RESET)
*/
flag_status i2c_interrupt_get(i2c_type *i2c_x, uint16_t source)
-{
+{
if((i2c_x->ctrl1 & source) != RESET)
{
return SET;
@@ -555,10 +555,10 @@ flag_status i2c_interrupt_get(i2c_type *i2c_x, uint16_t source)
/**
* @brief enable or disable dma requests.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param dma_req: dma transfer request.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - I2C_DMA_REQUEST_TX: dma transmit request.
* - I2C_DMA_REQUEST_RX: dma receive request.
* @param new_state (TRUE or FALSE).
@@ -579,7 +579,7 @@ void i2c_dma_enable(i2c_type *i2c_x, i2c_dma_request_type dma_req, confirm_state
/**
* @brief config data transfer.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param address: slave address.
* @param cnt: transfer conuter(0~255)
@@ -589,7 +589,7 @@ void i2c_dma_enable(i2c_type *i2c_x, i2c_dma_request_type dma_req, confirm_state
* - I2C_SOFT_STOP_MODE: soft generate stop mode.
* - I2C_RELOAD_MODE: reload mode.
* @param start: config gen start condition mode.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - I2C_WITHOUT_START: transfer data without start condition.
* - I2C_GEN_START_READ: read data and generate start.
* - I2C_GEN_START_WRITE: send data and generate start.
@@ -598,27 +598,27 @@ void i2c_dma_enable(i2c_type *i2c_x, i2c_dma_request_type dma_req, confirm_state
void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_mode_type start)
{
uint32_t temp;
-
+
/* copy ctrl2 value to temp */
temp = i2c_x->ctrl2;
-
+
/* clear ctrl2_bit specific bits */
temp &= ~0x03FF67FF;
-
+
/* transfer mode and address set */
temp |= address | rld_stop | start;
-
+
/* transfer counter set */
temp |= (uint32_t)cnt << 16;
-
+
/* update ctrl2 value */
- i2c_x->ctrl2 = temp;
+ i2c_x->ctrl2 = temp;
}
/**
* @brief generate start condition.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @retval none
*/
@@ -630,7 +630,7 @@ void i2c_start_generate(i2c_type *i2c_x)
/**
* @brief generate stop condition.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @retval none
*/
@@ -642,7 +642,7 @@ void i2c_stop_generate(i2c_type *i2c_x)
/**
* @brief send a byte through the i2c periph.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param data: byte to be transmitted.
* @retval none
@@ -655,7 +655,7 @@ void i2c_data_send(i2c_type *i2c_x, uint8_t data)
/**
* @brief receive a byte through the i2c periph.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @retval the value of the received data.
*/
@@ -667,10 +667,10 @@ uint8_t i2c_data_receive(i2c_type *i2c_x)
/**
* @brief get flag status.
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
* @param flag: specifies the flag to check.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - I2C_TDBE_FLAG: transmit data buffer empty flag.
* - I2C_TDIS_FLAG: send interrupt status.
* - I2C_RDBF_FLAG: receive data buffer full flag.
@@ -727,7 +727,7 @@ flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag)
flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag)
{
__IO uint32_t iten = 0;
-
+
switch(flag)
{
case I2C_TDIS_FLAG:
@@ -748,7 +748,7 @@ flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag)
case I2C_TDC_FLAG:
case I2C_TCRLD_FLAG:
iten = i2c_x->ctrl1_bit.tdcien;
- break;
+ break;
case I2C_BUSERR_FLAG:
case I2C_ARLOST_FLAG:
case I2C_OUF_FLAG:
@@ -761,7 +761,7 @@ flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag)
default:
break;
}
-
+
if(((i2c_x->sts & flag) != RESET) && (iten))
{
return SET;
@@ -775,9 +775,9 @@ flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag)
/**
* @brief clear flag status
* @param i2c_x: to select the i2c peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* I2C1, I2C2.
- * @param flag: specifies the flag to clear.
+ * @param flag: specifies the flag to clear.
* this parameter can be any combination of the following values:
* - I2C_ADDRF_FLAG: 0~7 bit address match flag.
* - I2C_ACKFAIL_FLAG: acknowledge failure flag.
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_misc.c b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_misc.c
index ac00388c6f1..f2cc184e621 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_misc.c
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_misc.c
@@ -5,11 +5,11 @@
**************************************************************************
* Copyright notice & Disclaimer
*
- * The software Board Support Package (BSP) that is made available to
- * download from Artery official website is the copyrighted work of Artery.
- * Artery authorizes customers to use, copy, and distribute the BSP
- * software and its related documentation for the purpose of design and
- * development in conjunction with Artery microcontrollers. Use of the
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -83,7 +83,7 @@ void nvic_irq_disable(IRQn_Type irqn)
/**
* @brief config nvic priority group
* @param priority_group
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - NVIC_PRIORITY_GROUP_0
* - NVIC_PRIORITY_GROUP_1
* - NVIC_PRIORITY_GROUP_2
@@ -100,8 +100,8 @@ void nvic_priority_group_config(nvic_priority_group_type priority_group)
/**
* @brief set the vector table location and offset.
* @param base
- * this parameter can be one of the following values:
- * - NVIC_VECTTAB_RAM
+ * this parameter can be one of the following values:
+ * - NVIC_VECTTAB_RAM
* - NVIC_VECTTAB_FLASH
* @param offset (vector table base offset field. this value must be a multiple of 0x200)
* @retval none
@@ -114,7 +114,7 @@ void nvic_vector_table_set(uint32_t base, uint32_t offset)
/**
* @brief config nvic lowpower mode
* @param lp_mode
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - NVIC_LP_SEVONPEND
* - NVIC_LP_SLEEPDEEP
* - NVIC_LP_SLEEPONEXIT
@@ -136,8 +136,8 @@ void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state ne
/**
* @brief config systick clock source
* @param source
- * this parameter can be one of the following values:
- * - SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8
+ * this parameter can be one of the following values:
+ * - SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8
* - SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV
* @retval none
*/
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_op.c b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_op.c
index 3ad94b9298e..f8b1f05a6a4 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_op.c
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_op.c
@@ -5,11 +5,11 @@
**************************************************************************
* Copyright notice & Disclaimer
*
- * The software Board Support Package (BSP) that is made available to
- * download from Artery official website is the copyrighted work of Artery.
- * Artery authorizes customers to use, copy, and distribute the BSP
- * software and its related documentation for the purpose of design and
- * development in conjunction with Artery microcontrollers. Use of the
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -32,7 +32,7 @@
* @brief OP driver modules
* @{
*/
-
+
#ifdef OP_MODULE_ENABLED
/** @defgroup OP_private_functions
@@ -42,7 +42,7 @@
/**
* @brief op enable.
* @param op_x: to select the OP peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* OP1, OP2, OP3, OP4.
* @param new_state: OP enable or disable(TRUE or FALSE).
* @retval none
@@ -57,28 +57,28 @@ void op_enable(op_type *op_x, confirm_state new_state)
/**
* @brief set the op peripheral mode.
* @param op_x: to select the OP peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* OP1, OP2, OP3, OP4.
* @param mode: OP mode
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - OP_FUNCTIONAL_MODE
* - OP_CALIBRATION_MODE
* @retval none
*/
void op_set_mode(op_type *op_x, op_mode_type mode)
{
-
+
op_x->ctrl_bit.calen = mode;
-
+
}
/**
* @brief set the op functional mode.
* @param op_x: to select the OP peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* OP1, OP2, OP3, OP4.
* @param functional_mode: OP functional mode
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - OP_STANDALONE_MODE
* - OP_FOLLOWER_MODE
* - OP_PGA_MODE
@@ -91,21 +91,21 @@ void op_set_functional_mode(op_type *op_x, op_functional_mode_type functional_mo
{
/* clear op functional mode bit */
op_x->ctrl &= (~OP_FUNCTIONAL_MODE_MASK);
-
+
/* set op functional mode */
op_x->ctrl |= functional_mode;
-
+
if(OP_FOLLOWER_MODE == functional_mode)
- op_x->tc_bit.vmssel = 0x1;
+ op_x->tc_bit.inmssel = 0x1;
}
/**
* @brief set the op pga gain value.
* @param op_x: to select the OP peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* OP1, OP2, OP3, OP4.
* @param gain: OP pga gain value
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - OP_PGA_GAIN_2_OR_MINUS_1
* - OP_PGA_GAIN_4_OR_MINUS_3
* - OP_PGA_GAIN_8_OR_MINUS_7
@@ -118,15 +118,15 @@ void op_set_gain(op_type *op_x, op_gain_type gain)
{
/* clear op pga gain value bit */
op_x->ctrl &= (~OP_PGA_GAIN_MASK);
-
+
/* set op pga gain value */
op_x->ctrl |= gain;
}
-
+
/**
* @brief set the OP high speed mode.
* @param op_x: to select the OP peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* OP1, OP2, OP3, OP4.
* @param new_state: new mode of the opa high-speed(TRUE or FALSE).
* @retval none
@@ -140,80 +140,80 @@ void op_set_highspeed_mode_enable(op_type *op_x, confirm_state new_state)
/**
* @brief op non inverted input selection.
* @param op_x: to select the OP peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* OP1, OP2, OP3, OP4.
* @param non_inverting_input: non inverted input
- * this parameter can be one of the following values:
- * - OP_NON_INVERTING_INPUT_VP0
- * - OP_NON_INVERTING_INPUT_VP1
- * - OP_NON_INVERTING_INPUT_VP2
- * - OP_NON_INVERTING_INPUT_VP3
+ * this parameter can be one of the following values:
+ * - OP_NON_INVERTING_INPUT_INP0
+ * - OP_NON_INVERTING_INPUT_INP1
+ * - OP_NON_INVERTING_INPUT_INP2
+ * - OP_NON_INVERTING_INPUT_INP3
* @retval none
*/
void op_set_input_non_inverting(op_type *op_x, op_non_inverting_input_type non_inverting_input)
{
/* set the op non inverted input */
- op_x->ctrl_bit.vpsel = non_inverting_input;
+ op_x->ctrl_bit.inpsel = non_inverting_input;
}
/**
* @brief OP inverted input selection.
* @param op_x: to select the OP peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* OP1, OP2, OP3, OP4.
* @param inverting_input: OP inverted input
- * this parameter can be one of the following values:
- * - OP_INVERTING_INPUT_VM0
- * - OP_INVERTING_INPUT_VM1
+ * this parameter can be one of the following values:
+ * - OP_INVERTING_INPUT_INM0
+ * - OP_INVERTING_INPUT_INM1
* - OP_INVERTING_INPUT_NONE
* @retval none
*/
void op_set_input_inverting(op_type *op_x, op_inverting_input_type inverting_input)
{
/* set the op inverted input */
- op_x->ctrl_bit.vmsel = inverting_input;
+ op_x->ctrl_bit.inmsel = inverting_input;
}
/**
* @brief op non inverted input secondary selection.
* @param op_x: to select the OP peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* OP1, OP2, OP3, OP4.
- * @param non_inverting_input: non inverting input secondary
- * this parameter can be one of the following values:
- * - OP_NON_INVERTING_INPUT_VP0
- * - OP_NON_INVERTING_INPUT_VP1
- * - OP_NON_INVERTING_INPUT_VP2
- * - OP_NON_INVERTING_INPUT_VP3
+ * @param non_inverting_input: non inverting input secondary
+ * this parameter can be one of the following values:
+ * - OP_NON_INVERTING_INPUT_INP0
+ * - OP_NON_INVERTING_INPUT_INP1
+ * - OP_NON_INVERTING_INPUT_INP2
+ * - OP_NON_INVERTING_INPUT_INP3
* @retval none
*/
void op_input_non_inverting_switch(op_type *op_x, op_non_inverting_input_type non_inverting_input)
{
/* set the op secondary non inverted input */
- op_x->tc_bit.vpssel = non_inverting_input;
+ op_x->tc_bit.inpssel = non_inverting_input;
}
-
+
/**
* @brief op inverted input secondary selection.
* @param op_x: to select the OP peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* OP1, OP2, OP3, OP4.
* @param inverting_input: OP inverted input secondary selection source
- * this parameter can be one of the following values:
- * - OP_INVERTING_INPUT_VM0(or PGA mode)
- * - OP_INVERTING_INPUT_VM1(or FOLLOWER mode)
+ * this parameter can be one of the following values:
+ * - OP_INVERTING_INPUT_INM0(or PGA mode)
+ * - OP_INVERTING_INPUT_INM1(or FOLLOWER mode)
* @retval none
*/
void op_input_inverting_switch(op_type *op_x, op_inverting_input_type inverting_input)
{
/* set the op secondary inverted input */
- op_x->tc_bit.vmssel = inverting_input;
+ op_x->tc_bit.inmssel = inverting_input;
}
/**
* @brief set the OP input mux mode.
* @param op_x: to select the OP peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* OP1, OP2, OP3, OP4.
* @param new_state: tmr controlled mux mode new state(TRUE or FALSE).
* @retval none
@@ -227,10 +227,10 @@ void op_input_mux_enable(op_type *op_x, confirm_state new_state)
/**
* @brief op internal output selection.
* @param op_x: to select the OP peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* OP1, OP2, OP3, OP4.
* @param internal_output: OP internal output selection source
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - OP_INTERNAL_OUTPUT_GPIO
* - OP_INTERNAL_OUTPUT_ADC
* @retval none
@@ -244,10 +244,10 @@ void op_internal_output_select(op_type *op_x, op_internal_output_type internal_o
/**
* @brief op trimming mode selection.
* @param op_x: to select the OP peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* OP1, OP2, OP3, OP4.
* @param trimming: OP trimming mode selection
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - OP_TRIMMING_FACTORY
* - OP_TRIMMING_USER
* @retval none
@@ -260,10 +260,10 @@ void op_set_trimming_mode(op_type *op_x, op_trimming_type trimming)
/**
* @brief op calibration selection.
* @param op_x: to select the OP peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* OP1, OP2, OP3, OP4.
* @param cal_sel: OP calibration selection
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - OP_TRIMMING_3_3VDDA
* - OP_TRIMMING_PMOS
* - OP_TRIMMING_50VDDA
@@ -279,7 +279,7 @@ void op_calibration_select(op_type *op_x, op_calibrate_type cal_sel)
/**
* @brief op calibration output status get.
* @param op_x: to select the OP peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* OP1, OP2, OP3, OP4.
* @retval state of calibration output
*/
@@ -302,10 +302,10 @@ flag_status op_calout_status_get(op_type *op_x)
/**
* @brief op triming value set.
* @param op_x: to select the OP peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* OP1, OP2, OP3, OP4.
* @param cal_sel: OP calibration selection
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - OP_TRIMMING_PMOS
* - OP_TRIMMING_NMOS
* @param triming_value: OP triming value(0x00...0x1f)
@@ -328,10 +328,10 @@ void op_set_triming_value(op_type *op_x, op_calibrate_type cal_sel, uint16_t tri
/**
* @brief op write protected enable.
* @param op_x: to select the OP peripheral.
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* OP1, OP2, OP3, OP4.
* @param lock_reg: OP lock register selection
- * this parameter can be one of the following values:
+ * this parameter can be one of the following values:
* - OP_WPC_CSR
* - OP_WPC_TMCR
* @retval none
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_pwc.c b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_pwc.c
index b6d7d36ee92..dbdd5324a37 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_pwc.c
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_pwc.c
@@ -91,7 +91,7 @@ void pwc_power_voltage_monitor_enable(confirm_state new_state)
}
/**
- * @brief set wakeup pin's polarity
+ * @brief set wakeup pin's polarity
* @param pin_num: choose the wakeup pin.
* this parameter can be be any combination of the following values:
* - PWC_WAKEUP_PIN_1
@@ -143,22 +143,22 @@ void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state)
}
/**
- * @brief clear flag of pwc
+ * @brief clear flag of pwc
* @param pwc_flag: select the pwc flag.
* this parameter can be any combination of the following values:
* - PWC_WAKEUP_PIN1_FLAG
* - PWC_WAKEUP_PIN2_FLAG
* - PWC_WAKEUP_PIN6_FLAG
* - PWC_WAKEUP_PIN7_FLAG
- * - PWC_STANDBY_FLAG
- * - PWC_WAKEUP_INTERNAL_FLAG
+ * - PWC_STANDBY_FLAG
+ * - PWC_WAKEUP_INTERNAL_FLAG
* - note:"PWC_PVM_OUTPUT_FLAG" cannot be choose!this bit is readonly bit,it means the voltage monitoring output state
- * @retval none
+ * @retval none
*/
void pwc_flag_clear(uint32_t pwc_flag)
{
PWC->clr |= pwc_flag;
-}
+}
/**
* @brief get flag of pwc
@@ -169,12 +169,12 @@ void pwc_flag_clear(uint32_t pwc_flag)
* - PWC_WAKEUP_PIN6_FLAG
* - PWC_WAKEUP_PIN7_FLAG
* - PWC_STANDBY_FLAG
- * - PWC_PVM_OUTPUT_FLAG
- * - PWC_WAKEUP_INTERNAL_FLAG
+ * - PWC_PVM_OUTPUT_FLAG
+ * - PWC_WAKEUP_INTERNAL_FLAG
* @retval state of select flag(SET or RESET).
*/
flag_status pwc_flag_get(uint32_t pwc_flag)
-{
+{
flag_status status = RESET;
if ((PWC->ctrlsts & pwc_flag) == RESET)
{
@@ -260,7 +260,7 @@ void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator)
PWC->ldoov_bit.vrexlpen = TRUE;
PWC->ctrl_bit.vrsel = TRUE;
break;
- default:
+ default:
break;
}
}
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_scfg.c b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_scfg.c
index f55439cfb4a..dd2e36c3034 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_scfg.c
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_scfg.c
@@ -5,11 +5,11 @@
**************************************************************************
* Copyright notice & Disclaimer
*
- * The software Board Support Package (BSP) that is made available to
- * download from Artery official website is the copyrighted work of Artery.
- * Artery authorizes customers to use, copy, and distribute the BSP
- * software and its related documentation for the purpose of design and
- * development in conjunction with Artery microcontrollers. Use of the
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -39,18 +39,18 @@
* @{
*/
-/**
- * @brief scfg reset
+/**
+ * @brief scfg reset
* @param none
* @retval none
*/
void scfg_reset(void)
-{
+{
crm_periph_reset(CRM_SCFG_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_SCFG_PERIPH_RESET, FALSE);
}
-/**
+/**
* @brief scfg infrared config
* @param source
* this parameter can be one of the following values:
@@ -99,8 +99,8 @@ void scfg_pa11pa12_pin_remap (scfg_pa11pa12_remap_type pin_remap)
SCFG->cfg1_bit.pa11_12_rmp = pin_remap;
}
-/**
- * @brief cm4f lockup enable
+/**
+ * @brief cm4f lockup enable
* @param new_state (TRUE or FALSE)
* @retval none
*/
@@ -109,8 +109,8 @@ void scfg_lockup_enable(confirm_state new_state)
SCFG->cfg2_bit.lockup_lk = new_state;
}
-/**
- * @brief power voltage monitoring lock enable
+/**
+ * @brief power voltage monitoring lock enable
* @param new_state (TRUE or FALSE)
* @retval none
*/
@@ -119,8 +119,8 @@ void scfg_pvm_lock_enable(confirm_state new_state)
SCFG->cfg2_bit.pvm_lk = new_state;
}
-/**
- * @brief can timestamp counting source set
+/**
+ * @brief can timestamp counting source set
* @param usart_index
* this parameter can be one of the following values:
* - SCFG_CAN1
@@ -202,8 +202,8 @@ void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_
* @brief enable or disable gpio pins ultra driven.
* @param value:
* this parameter can be one of the following values:
- * - SCFG_ULTRA_DRIVEN_PB9
- * - SCFG_ULTRA_DRIVEN_PB8
+ * - SCFG_ULTRA_DRIVEN_PB9
+ * - SCFG_ULTRA_DRIVEN_PB8
* - SCFG_ULTRA_DRIVEN_PA11
* - SCFG_ULTRA_DRIVEN_PA12
* @param new_state (TRUE or FALSE)
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_spi.c b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_spi.c
index 39f254d9682..3ad087591cb 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_spi.c
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_spi.c
@@ -604,7 +604,7 @@ flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag)
flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag)
{
flag_status status = RESET;
-
+
switch(spi_i2s_flag)
{
case SPI_I2S_RDBF_FLAG:
@@ -659,7 +659,7 @@ flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag)
* @brief clear flag of the specified spi/i2s peripheral.
* @param spi_x: select the spi/i2s peripheral.
* this parameter can be one of the following values:
- * SPI1, SPI2, SPI3, I2SF5
+ * SPI1, SPI2, SPI3, I2SF5
* @param spi_i2s_flag: select the spi/i2s flag
* this parameter can be one of the following values:
* - SPI_CCERR_FLAG
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_tmr.c b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_tmr.c
index 7ecd659dd05..b0efd98bbbd 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_tmr.c
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_tmr.c
@@ -344,7 +344,7 @@ void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_chan
tmr_x->ctrl2_bit.c1ios = tmr_output_struct->oc_idle_state;
tmr_x->ctrl2_bit.c1cios = tmr_output_struct->occ_idle_state;
tmr_x->cm1_output_bit.c1octrl = cxoctrl_bit2_0;
- tmr_x->cm1_output_bit.c1octrl_3 = cxoctrl_bit3;
+ tmr_x->cm1_output_bit.c1octrl_3 = cxoctrl_bit3;
tmr_x->cctrl_bit.c1p = tmr_output_struct->oc_polarity;
tmr_x->cctrl_bit.c1cp = tmr_output_struct->occ_polarity;
tmr_x->cctrl_bit.c1en = tmr_output_struct->oc_output_state;
@@ -426,10 +426,10 @@ void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_chan
* - TMR_OUTPUT_CONTROL_FORCE_LOW
* - TMR_OUTPUT_CONTROL_PWM_MODE_A
* - TMR_OUTPUT_CONTROL_PWM_MODE_B
- * - TMR_OUTPUT_CONTROL_RETRIG_OCM_A
- * - TMR_OUTPUT_CONTROL_RETRIG_OCM_B
- * - TMR_OUTPUT_CONTROL_COMBINED_PWM_A
- * - TMR_OUTPUT_CONTROL_COMBINED_PWM_B
+ * - TMR_OUTPUT_CONTROL_RETRIG_OCM_A
+ * - TMR_OUTPUT_CONTROL_RETRIG_OCM_B
+ * - TMR_OUTPUT_CONTROL_COMBINED_PWM_A
+ * - TMR_OUTPUT_CONTROL_COMBINED_PWM_B
* - TMR_OUTPUT_CONTROL_ASYMMETRIC_PWM_A
* - TMR_OUTPUT_CONTROL_ASYMMETRIC_PWM_B
* @retval none
@@ -576,7 +576,7 @@ void tmr_channel_value_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel,
case TMR_SELECT_CHANNEL_4A:
tmr_x->c4adt = tmr_channel_value;
break;
-
+
default:
break;
}
@@ -971,21 +971,21 @@ void tmr_input_channel_blk_config(tmr_type *tmr_x, tmr_blk_config_type *input_bl
case TMR_SELECT_CHANNEL_2:
tmr_x->blkctrl_bit.ch2blkss = input_blk_struct->blk_source_select;
tmr_x->blkctrl_bit.ch2blkp = input_blk_struct->blk_source_polarity;
- tmr_x->blkctrl_bit.ch2blkst = input_blk_struct->input_blk_state;
+ tmr_x->blkctrl_bit.ch2blkst = input_blk_struct->input_blk_state;
tmr_x->blkctrl_bit.ch2blken = input_blk_struct->blk_enable;
break;
case TMR_SELECT_CHANNEL_3:
tmr_x->blkctrl_bit.ch3blkss = input_blk_struct->blk_source_select;
tmr_x->blkctrl_bit.ch3blkp = input_blk_struct->blk_source_polarity;
- tmr_x->blkctrl_bit.ch3blkst = input_blk_struct->input_blk_state;
+ tmr_x->blkctrl_bit.ch3blkst = input_blk_struct->input_blk_state;
tmr_x->blkctrl_bit.ch3blken = input_blk_struct->blk_enable;
break;
case TMR_SELECT_CHANNEL_4:
tmr_x->blkctrl_bit.ch4blkss = input_blk_struct->blk_source_select;
tmr_x->blkctrl_bit.ch4blkp = input_blk_struct->blk_source_polarity;
- tmr_x->blkctrl_bit.ch4blkst = input_blk_struct->input_blk_state;
+ tmr_x->blkctrl_bit.ch4blkst = input_blk_struct->input_blk_state;
tmr_x->blkctrl_bit.ch4blken = input_blk_struct->blk_enable;
break;
@@ -1960,7 +1960,7 @@ void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct)
tmr_x->brk_bit.fcsodis = brkdt_struct->fcsodis_state;
tmr_x->brk_bit.fcsoen = brkdt_struct->fcsoen_state;
tmr_x->brk_bit.brkv = brkdt_struct->brk_polarity;
- tmr_x->brk_bit.aoen = brkdt_struct->auto_output_enable;
+ tmr_x->brk_bit.aoen = brkdt_struct->auto_output_enable;
tmr_x->brk_bit.brken = brkdt_struct->brk_enable;
tmr_x->brk_bit.wpc = brkdt_struct->wp_level;
}
@@ -2043,7 +2043,7 @@ void tmr_primary_mode2_select(tmr_type *tmr_x, tmr_primary_select_type primary_m
* @param tmr_x: select the tmr peripheral.
* this parameter can be one of the following values:
* TMR1, TMR3, TMR4
- * @param ocrefclearinputsource
+ * @param ocrefclearinputsource
* this parameter can be one of the following values:
* - TMR_CORAW_CLR_EXT
* - TMR_CORAW_CLR_CMP1
@@ -2128,7 +2128,7 @@ void tmr_brk_release(tmr_type *tmr_x, tmr_brk_type brk_sel)
* - TMR_BRK_SELECT_1
* - TMR_BRK_SELECT_2
* @retval tmr_brk_release_status
- * - TMR_BRK_RELEASED
+ * - TMR_BRK_RELEASED
* - TMR_BRK_UNRELEASED
*/
tmr_brk_release_status tmr_brk_release_check(tmr_type *tmr_x, tmr_brk_type brk)
@@ -2150,7 +2150,7 @@ tmr_brk_release_status tmr_brk_release_check(tmr_type *tmr_x, tmr_brk_type brk)
* TMR1
* @param ch5_comb
* this parameter can be a combination of the following values:
- * - TMR_CH5_COMBINED_NONE
+ * - TMR_CH5_COMBINED_NONE
* - TMR_CH5_COMBINED_C1ORAW
* - TMR_CH5_COMBINED_C2ORAW
* - TMR_CH5_COMBINED_C3ORAW
@@ -2222,7 +2222,7 @@ void tmr_brk_input_config(tmr_type *tmr_x, tmr_brkin_config_type *brkin_struct)
}
/**
- * @brief select external source
+ * @brief select external source
* @param tmr_x: select the tmr peripheral.
* this parameter can be one of the following values:
* TMR1, TMR3, TMR4
@@ -2253,60 +2253,60 @@ void tmr_external_source_select(tmr_type *tmr_x, uint32_t ext_src)
* TMR1, TMR3, TMR4, TMR9, TMR10, TMR11
* @param remap
* for tmr1 this parameter can be one of the following values:
- * - TMR_TMR1_CH1_GPIO
- * - TMR_TMR1_CH1_CMP1
- * - TMR_TMR1_CH1_CMP2
- * - TMR_TMR1_CH2_GPIO
- * - TMR_TMR1_CH2_CMP1
- * - TMR_TMR1_CH2_CMP2
+ * - TMR_TMR1_CH1_GPIO
+ * - TMR_TMR1_CH1_CMP1
+ * - TMR_TMR1_CH1_CMP2
+ * - TMR_TMR1_CH2_GPIO
+ * - TMR_TMR1_CH2_CMP1
+ * - TMR_TMR1_CH2_CMP2
* for tmr3 this parameter can be one of the following values:
- * - TMR_TMR3_CH1_GPIO
- * - TMR_TMR3_CH1_CMP1
- * - TMR_TMR3_CH1_CMP2
- * - TMR_TMR3_CH1_TMR4CH1
- * - TMR_TMR3_CH2_GPIO
- * - TMR_TMR3_CH2_CMP1
- * - TMR_TMR3_CH2_CMP2
- * - TMR_TMR3_CH2_TMR4CH2
- * - TMR_TMR3_CH3_GPIO
- * - TMR_TMR3_CH3_CMP1
- * - TMR_TMR3_CH3_TMR4CH3
- * - TMR_TMR3_CH4_GPIO
- * - TMR_TMR3_CH4_CMP2
+ * - TMR_TMR3_CH1_GPIO
+ * - TMR_TMR3_CH1_CMP1
+ * - TMR_TMR3_CH1_CMP2
+ * - TMR_TMR3_CH1_TMR4CH1
+ * - TMR_TMR3_CH2_GPIO
+ * - TMR_TMR3_CH2_CMP1
+ * - TMR_TMR3_CH2_CMP2
+ * - TMR_TMR3_CH2_TMR4CH2
+ * - TMR_TMR3_CH3_GPIO
+ * - TMR_TMR3_CH3_CMP1
+ * - TMR_TMR3_CH3_TMR4CH3
+ * - TMR_TMR3_CH4_GPIO
+ * - TMR_TMR3_CH4_CMP2
* for tmr4 this parameter can be one of the following values:
- * - TMR_TMR4_CH1_GPIO
- * - TMR_TMR4_CH1_CMP1
- - TMR_TMR4_CH1_CMP2
- * - TMR_TMR4_CH1_TMR3CH1
- * - TMR_TMR4_CH2_GPIO
- * - TMR_TMR4_CH2_CMP1
- * - TMR_TMR4_CH2_CMP2
- * - TMR_TMR4_CH2_TMR3CH2
- * - TMR_TMR4_CH3_GPIO
- * - TMR_TMR4_CH3_CMP2
- * - TMR_TMR4_CH3_TMR3CH3
- * - TMR_TMR4_CH4_GPIO
- * - TMR_TMR4_CH4_CMP1
+ * - TMR_TMR4_CH1_GPIO
+ * - TMR_TMR4_CH1_CMP1
+ - TMR_TMR4_CH1_CMP2
+ * - TMR_TMR4_CH1_TMR3CH1
+ * - TMR_TMR4_CH2_GPIO
+ * - TMR_TMR4_CH2_CMP1
+ * - TMR_TMR4_CH2_CMP2
+ * - TMR_TMR4_CH2_TMR3CH2
+ * - TMR_TMR4_CH3_GPIO
+ * - TMR_TMR4_CH3_CMP2
+ * - TMR_TMR4_CH3_TMR3CH3
+ * - TMR_TMR4_CH4_GPIO
+ * - TMR_TMR4_CH4_CMP1
* for tmr9 this parameter can be one of the following values:
- * - TMR_TMR9_CH1_GPIO
- * - TMR_TMR9_CH1_CMP1
- * - TMR_TMR9_CH1_CMP2
- * - TMR_TMR9_CH2_GPIO
- * - TMR_TMR9_CH2_CMP1
- * - TMR_TMR9_CH2_CMP2
+ * - TMR_TMR9_CH1_GPIO
+ * - TMR_TMR9_CH1_CMP1
+ * - TMR_TMR9_CH1_CMP2
+ * - TMR_TMR9_CH2_GPIO
+ * - TMR_TMR9_CH2_CMP1
+ * - TMR_TMR9_CH2_CMP2
* for tmr10 this parameter can be one of the following values:
- * - TMR_TMR10_CH1_GPIO
- * - TMR_TMR10_CH1_CMP1
- * - TMR_TMR10_CH1_CMP2
+ * - TMR_TMR10_CH1_GPIO
+ * - TMR_TMR10_CH1_CMP1
+ * - TMR_TMR10_CH1_CMP2
* for tmr11 this parameter can be one of the following values:
- * - TMR_TMR11_CH1_GPIO
- * - TMR_TMR11_CH1_CMP1
- * - TMR_TMR11_CH1_CMP2
- * - TMR_TMR11_CH1_CLKOUT
+ * - TMR_TMR11_CH1_GPIO
+ * - TMR_TMR11_CH1_CMP1
+ * - TMR_TMR11_CH1_CMP2
+ * - TMR_TMR11_CH1_CLKOUT
* - TMR_TMR11_CH1_HEXTDIV
* - TMR_TMR11_CH1_ERTCCLK
- * - TMR_TMR11_CH1_LEXT
- * - TMR_TMR11_CH1_LICK
+ * - TMR_TMR11_CH1_LEXT
+ * - TMR_TMR11_CH1_LICK
* @retval none
*/
void tmr_input_ch_select(tmr_type *tmr_x, uint32_t ch_src)
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_usart.c b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_usart.c
index 74e9147c4e9..de887a801e4 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_usart.c
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_usart.c
@@ -5,11 +5,11 @@
**************************************************************************
* Copyright notice & Disclaimer
*
- * The software Board Support Package (BSP) that is made available to
- * download from Artery official website is the copyrighted work of Artery.
- * Artery authorizes customers to use, copy, and distribute the BSP
- * software and its related documentation for the purpose of design and
- * development in conjunction with Artery microcontrollers. Use of the
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -33,13 +33,13 @@
* @brief USART driver modules
* @{
*/
-
+
#ifdef USART_MODULE_ENABLED
/** @defgroup USART_private_functions
* @{
*/
-
+
/**
* @brief deinitialize the usart peripheral registers to their default reset values.
* @param usart_x: select the usart or the uart peripheral.
@@ -67,7 +67,7 @@ void usart_reset(usart_type* usart_x)
* this parameter can be one of the following values:
* USART1 or USART2.
* @param baud_rate: configure the usart communication baud rate.
- * @param data_bit: data bits transmitted or received in a frame
+ * @param data_bit: data bits transmitted or received in a frame
* this parameter can be one of the following values:
* - USART_DATA_7BITS
* - USART_DATA_8BITS
@@ -84,7 +84,7 @@ void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type
{
crm_clocks_freq_type clocks_freq;
uint32_t apb_clock, temp_val;
- crm_clocks_freq_get(&clocks_freq);
+ crm_clocks_freq_get(&clocks_freq);
if(usart_x == USART1)
{
apb_clock = clocks_freq.apb2_freq;
@@ -105,20 +105,20 @@ void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type
usart_x->baudr_bit.div = temp_val;
if(data_bit == USART_DATA_7BITS)
{
- usart_x->ctrl1_bit.dbn1 = 1;
- usart_x->ctrl1_bit.dbn0 = 0;
+ usart_x->ctrl1_bit.dbn1 = 1;
+ usart_x->ctrl1_bit.dbn0 = 0;
}
else if(data_bit == USART_DATA_8BITS)
{
- usart_x->ctrl1_bit.dbn1 = 0;
- usart_x->ctrl1_bit.dbn0 = 0;
+ usart_x->ctrl1_bit.dbn1 = 0;
+ usart_x->ctrl1_bit.dbn0 = 0;
}
else
{
- usart_x->ctrl1_bit.dbn1 = 0;
- usart_x->ctrl1_bit.dbn0 = 1;
+ usart_x->ctrl1_bit.dbn1 = 0;
+ usart_x->ctrl1_bit.dbn0 = 1;
}
- usart_x->ctrl2_bit.stopbn = stop_bit;
+ usart_x->ctrl2_bit.stopbn = stop_bit;
}
/**
@@ -138,17 +138,17 @@ void usart_parity_selection_config(usart_type* usart_x, usart_parity_selection_t
if(parity == USART_PARITY_NONE)
{
usart_x->ctrl1_bit.psel = FALSE;
- usart_x->ctrl1_bit.pen = FALSE;
+ usart_x->ctrl1_bit.pen = FALSE;
}
else if(parity == USART_PARITY_EVEN)
{
usart_x->ctrl1_bit.psel = FALSE;
- usart_x->ctrl1_bit.pen = TRUE;
+ usart_x->ctrl1_bit.pen = TRUE;
}
else if(parity == USART_PARITY_ODD)
{
usart_x->ctrl1_bit.psel = TRUE;
- usart_x->ctrl1_bit.pen = TRUE;
+ usart_x->ctrl1_bit.pen = TRUE;
}
}
@@ -213,9 +213,9 @@ void usart_receiver_enable(usart_type* usart_x, confirm_state new_state)
*/
void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, usart_clock_phase_type clk_pha, usart_lbcp_type clk_lb)
{
- usart_x->ctrl2_bit.clkpol = clk_pol;
+ usart_x->ctrl2_bit.clkpol = clk_pol;
usart_x->ctrl2_bit.clkpha = clk_pha;
- usart_x->ctrl2_bit.lbcp = clk_lb;
+ usart_x->ctrl2_bit.lbcp = clk_lb;
}
/**
@@ -253,7 +253,7 @@ void usart_clock_enable(usart_type* usart_x, confirm_state new_state)
* @retval none
*/
void usart_interrupt_enable(usart_type* usart_x, uint32_t usart_int, confirm_state new_state)
-{
+{
if(new_state == TRUE)
PERIPH_REG((uint32_t)usart_x, usart_int) |= PERIPH_REG_BIT(usart_int);
else
@@ -367,7 +367,7 @@ void usart_break_bit_num_set(usart_type* usart_x, usart_break_bit_num_type break
*/
void usart_lin_mode_enable(usart_type* usart_x, confirm_state new_state)
{
- usart_x->ctrl2_bit.linen = new_state;
+ usart_x->ctrl2_bit.linen = new_state;
}
/**
@@ -404,7 +404,7 @@ uint16_t usart_data_receive(usart_type* usart_x)
*/
void usart_break_send(usart_type* usart_x)
{
- usart_x->ctrl1_bit.sbf = TRUE;
+ usart_x->ctrl1_bit.sbf = TRUE;
}
/**
@@ -418,7 +418,7 @@ void usart_break_send(usart_type* usart_x)
*/
void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val)
{
- usart_x->gdiv_bit.scgt = guard_time_val;
+ usart_x->gdiv_bit.scgt = guard_time_val;
}
/**
@@ -432,7 +432,7 @@ void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val)
*/
void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val)
{
- usart_x->gdiv_bit.isdiv = div_val;
+ usart_x->gdiv_bit.isdiv = div_val;
}
/**
@@ -447,7 +447,7 @@ void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val)
*/
void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state)
{
- usart_x->ctrl3_bit.scmen = new_state;
+ usart_x->ctrl3_bit.scmen = new_state;
}
/**
@@ -462,7 +462,7 @@ void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state)
*/
void usart_smartcard_nack_set(usart_type* usart_x, confirm_state new_state)
{
- usart_x->ctrl3_bit.scnacken = new_state;
+ usart_x->ctrl3_bit.scnacken = new_state;
}
/**
@@ -476,7 +476,7 @@ void usart_smartcard_nack_set(usart_type* usart_x, confirm_state new_state)
*/
void usart_single_line_halfduplex_select(usart_type* usart_x, confirm_state new_state)
{
- usart_x->ctrl3_bit.slben = new_state;
+ usart_x->ctrl3_bit.slben = new_state;
}
/**
@@ -490,7 +490,7 @@ void usart_single_line_halfduplex_select(usart_type* usart_x, confirm_state new_
*/
void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state)
{
- usart_x->ctrl3_bit.irdaen = new_state;
+ usart_x->ctrl3_bit.irdaen = new_state;
}
/**
@@ -504,7 +504,7 @@ void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state)
*/
void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state)
{
- usart_x->ctrl3_bit.irdalp = new_state;
+ usart_x->ctrl3_bit.irdalp = new_state;
}
/**
@@ -541,7 +541,7 @@ void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_con
{
usart_x->ctrl3_bit.rtsen = TRUE;
usart_x->ctrl3_bit.ctsen = TRUE;
- }
+ }
}
/**
@@ -624,14 +624,14 @@ flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag)
break;
case USART_IDLEF_FLAG:
int_status = (flag_status)usart_x->ctrl1_bit.idleien;
- break;
+ break;
case USART_NERR_FLAG:
case USART_FERR_FLAG:
int_status = (flag_status)usart_x->ctrl3_bit.errien;
break;
case USART_PERR_FLAG:
int_status = (flag_status)usart_x->ctrl1_bit.perrien;
- break;
+ break;
case USART_RTODF_FLAG:
int_status = (flag_status)usart_x->ctrl1_bit.retodie;
break;
@@ -720,7 +720,7 @@ void usart_flag_clear(usart_type* usart_x, uint32_t flag)
void usart_rs485_delay_time_config(usart_type* usart_x, uint8_t start_delay_time, uint8_t complete_delay_time)
{
usart_x->ctrl1_bit.tsdt = start_delay_time;
- usart_x->ctrl1_bit.tcdt = complete_delay_time;
+ usart_x->ctrl1_bit.tcdt = complete_delay_time;
}
/**
@@ -776,7 +776,7 @@ void usart_de_polarity_set(usart_type* usart_x, usart_de_polarity_type de_polari
*/
void usart_rs485_mode_enable(usart_type* usart_x, confirm_state new_state)
{
- usart_x->ctrl3_bit.rs485en = new_state;
+ usart_x->ctrl3_bit.rs485en = new_state;
}
/**
@@ -790,7 +790,7 @@ void usart_rs485_mode_enable(usart_type* usart_x, confirm_state new_state)
*/
void usart_msb_transmit_first_enable(usart_type* usart_x, confirm_state new_state)
{
- usart_x->ctrl2_bit.mtf = new_state;
+ usart_x->ctrl2_bit.mtf = new_state;
}
/**
@@ -832,7 +832,7 @@ void usart_transmit_pin_polarity_reverse(usart_type* usart_x, confirm_state new_
*/
void usart_receive_pin_polarity_reverse(usart_type* usart_x, confirm_state new_state)
{
- usart_x->ctrl2_bit.rxrev = new_state;
+ usart_x->ctrl2_bit.rxrev = new_state;
}
/**
@@ -846,7 +846,7 @@ void usart_receive_pin_polarity_reverse(usart_type* usart_x, confirm_state new_s
*/
void usart_receiver_timeout_detection_enable(usart_type* usart_x, confirm_state new_state)
{
- usart_x->ctrl1_bit.rtoden = new_state;
+ usart_x->ctrl1_bit.rtoden = new_state;
}
/**
@@ -860,7 +860,7 @@ void usart_receiver_timeout_detection_enable(usart_type* usart_x, confirm_state
*/
void usart_receiver_timeout_value_set(usart_type* usart_x, uint32_t value)
{
- usart_x->rtov_bit.rtov = value;
+ usart_x->rtov_bit.rtov = value;
}
/**
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_wdt.c b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_wdt.c
index f2c9d16f19e..7667518b559 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_wdt.c
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_wdt.c
@@ -5,11 +5,11 @@
**************************************************************************
* Copyright notice & Disclaimer
*
- * The software Board Support Package (BSP) that is made available to
- * download from Artery official website is the copyrighted work of Artery.
- * Artery authorizes customers to use, copy, and distribute the BSP
- * software and its related documentation for the purpose of design and
- * development in conjunction with Artery microcontrollers. Use of the
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -50,7 +50,7 @@ void wdt_enable(void)
}
/**
- * @brief reload wdt counter
+ * @brief reload wdt counter
* @param none
* @retval none
*/
@@ -60,7 +60,7 @@ void wdt_counter_reload(void)
}
/**
- * @brief set wdt counter reload value
+ * @brief set wdt counter reload value
* @param reload_value (0x0000~0x0FFF)
* @retval none
*/
@@ -70,54 +70,54 @@ void wdt_reload_value_set(uint16_t reload_value)
}
/**
- * @brief set wdt division divider
- * @param division
- * this parameter can be one of the following values:
- * - WDT_CLK_DIV_4
- * - WDT_CLK_DIV_8
- * - WDT_CLK_DIV_16
- * - WDT_CLK_DIV_32
- * - WDT_CLK_DIV_64
- * - WDT_CLK_DIV_128
- * - WDT_CLK_DIV_256
- * @retval none
+ * @brief set wdt division divider
+ * @param division
+ * this parameter can be one of the following values:
+ * - WDT_CLK_DIV_4
+ * - WDT_CLK_DIV_8
+ * - WDT_CLK_DIV_16
+ * - WDT_CLK_DIV_32
+ * - WDT_CLK_DIV_64
+ * - WDT_CLK_DIV_128
+ * - WDT_CLK_DIV_256
+ * @retval none
*/
void wdt_divider_set(wdt_division_type division)
-{
+{
WDT->div_bit.div = division;
}
/**
- * @brief enable or disable wdt cmd register write
- * @param new_state (TRUE or FALSE)
- * @retval none
+ * @brief enable or disable wdt cmd register write
+ * @param new_state (TRUE or FALSE)
+ * @retval none
*/
void wdt_register_write_enable( confirm_state new_state)
-{
+{
if(new_state == FALSE)
{
WDT->cmd = WDT_CMD_LOCK;
}
- else
+ else
{
WDT->cmd = WDT_CMD_UNLOCK;
- }
+ }
}
/**
- * @brief get wdt flag
- * @param wdt_flag
- * this parameter can be one of the following values:
- * - WDT_DIVF_UPDATE_FLAG: division value update complete flag.
- * - WDT_RLDF_UPDATE_FLAG: reload value update complete flag.
- * - WDT_WINF_UPDATE_FLAG: window value update complete flag.
- * @retval state of wdt flag
+ * @brief get wdt flag
+ * @param wdt_flag
+ * this parameter can be one of the following values:
+ * - WDT_DIVF_UPDATE_FLAG: division value update complete flag.
+ * - WDT_RLDF_UPDATE_FLAG: reload value update complete flag.
+ * - WDT_WINF_UPDATE_FLAG: window value update complete flag.
+ * @retval state of wdt flag
*/
flag_status wdt_flag_get(uint16_t wdt_flag)
-{
+{
flag_status status = RESET;
- if ((WDT->sts & wdt_flag) != (uint16_t)RESET)
+ if ((WDT->sts & wdt_flag) != (uint16_t)RESET)
{
status = SET;
}
diff --git a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_wwdt.c b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_wwdt.c
index 32e5b0e0bb7..ff0012197fe 100644
--- a/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_wwdt.c
+++ b/bsp/at32/libraries/AT32M412_416_Firmware_Library/drivers/src/at32m412_416_wwdt.c
@@ -5,11 +5,11 @@
**************************************************************************
* Copyright notice & Disclaimer
*
- * The software Board Support Package (BSP) that is made available to
- * download from Artery official website is the copyrighted work of Artery.
- * Artery authorizes customers to use, copy, and distribute the BSP
- * software and its related documentation for the purpose of design and
- * development in conjunction with Artery microcontrollers. Use of the
+ * The software Board Support Package (BSP) that is made available to
+ * download from Artery official website is the copyrighted work of Artery.
+ * Artery authorizes customers to use, copy, and distribute the BSP
+ * software and its related documentation for the purpose of design and
+ * development in conjunction with Artery microcontrollers. Use of the
* software is governed by this copyright notice and the following disclaimer.
*
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
@@ -39,33 +39,33 @@
* @{
*/
-/**
+/**
* @brief wwdt reset by crm reset register
* @retval none
*/
void wwdt_reset(void)
-{
+{
crm_periph_reset(CRM_WWDT_PERIPH_RESET, TRUE);
crm_periph_reset(CRM_WWDT_PERIPH_RESET, FALSE);
}
/**
- * @brief wwdt division set
- * @param division
+ * @brief wwdt division set
+ * @param division
* this parameter can be one of the following values:
- * - WWDT_PCLK1_DIV_4096 (wwdt counter clock = (pclk1/4096)/1)
- * - WWDT_PCLK1_DIV_8192 (wwdt counter clock = (pclk1/4096)/2)
- * - WWDT_PCLK1_DIV_16384 (wwdt counter clock = (pclk1/4096)/4)
- * - WWDT_PCLK1_DIV_32768 (wwdt counter clock = (pclk1/4096)/8)
- * @retval none
+ * - WWDT_PCLK1_DIV_4096 (wwdt counter clock = (pclk1/4096)/1)
+ * - WWDT_PCLK1_DIV_8192 (wwdt counter clock = (pclk1/4096)/2)
+ * - WWDT_PCLK1_DIV_16384 (wwdt counter clock = (pclk1/4096)/4)
+ * - WWDT_PCLK1_DIV_32768 (wwdt counter clock = (pclk1/4096)/8)
+ * @retval none
*/
void wwdt_divider_set(wwdt_division_type division)
-{
+{
WWDT->cfg_bit.div = division;
}
/**
- * @brief wwdt reload counter interrupt flag clear
+ * @brief wwdt reload counter interrupt flag clear
* @param none
* @retval none
*/
@@ -85,7 +85,7 @@ void wwdt_enable(uint8_t wwdt_cnt)
}
/**
- * @brief wwdt reload counter interrupt enable
+ * @brief wwdt reload counter interrupt enable
* @param none
* @retval none
*/
@@ -95,12 +95,12 @@ void wwdt_interrupt_enable(void)
}
/**
- * @brief wwdt reload counter interrupt flag get
- * @param none
- * @retval state of reload counter interrupt flag
+ * @brief wwdt reload counter interrupt flag get
+ * @param none
+ * @retval state of reload counter interrupt flag
*/
flag_status wwdt_flag_get(void)
-{
+{
return (flag_status)WWDT->sts_bit.rldf;
}
diff --git a/bsp/at32/libraries/Kconfig b/bsp/at32/libraries/Kconfig
index 274ae759614..4a643eb178a 100644
--- a/bsp/at32/libraries/Kconfig
+++ b/bsp/at32/libraries/Kconfig
@@ -71,6 +71,21 @@ config SOC_SERIES_AT32F437
select ARCH_ARM_CORTEX_M4
select SOC_FAMILY_AT32
+config SOC_SERIES_AT32F455
+ bool
+ select ARCH_ARM_CORTEX_M4
+ select SOC_FAMILY_AT32
+
+config SOC_SERIES_AT32F456
+ bool
+ select ARCH_ARM_CORTEX_M4
+ select SOC_FAMILY_AT32
+
+config SOC_SERIES_AT32F457
+ bool
+ select ARCH_ARM_CORTEX_M4
+ select SOC_FAMILY_AT32
+
config SOC_SERIES_AT32M412
bool
select ARCH_ARM_CORTEX_M4
diff --git a/bsp/at32/libraries/rt_drivers/config/f45x/can_config.h b/bsp/at32/libraries/rt_drivers/config/f45x/can_config.h
new file mode 100644
index 00000000000..d91f975f140
--- /dev/null
+++ b/bsp/at32/libraries/rt_drivers/config/f45x/can_config.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-12-18 shelton first version
+ */
+
+#ifndef __CAN_CONFIG_H__
+#define __CAN_CONFIG_H__
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CAN1_TX_IRQHandler CAN1_TX_IRQHandler
+#define CAN1_RX_IRQHandler CAN1_RX_IRQHandler
+#define CAN1_STAT_IRQHandler CAN1_STAT_IRQHandler
+#define CAN1_ERR_IRQHandler CAN1_ERR_IRQHandler
+
+#define CAN2_TX_IRQHandler CAN2_TX_IRQHandler
+#define CAN2_RX_IRQHandler CAN2_RX_IRQHandler
+#define CAN2_STAT_IRQHandler CAN2_STAT_IRQHandler
+#define CAN2_ERR_IRQHandler CAN2_ERR_IRQHandler
+
+#define CAN3_TX_IRQHandler CAN3_TX_IRQHandler
+#define CAN3_RX_IRQHandler CAN3_RX_IRQHandler
+#define CAN3_STAT_IRQHandler CAN3_STAT_IRQHandler
+#define CAN3_ERR_IRQHandler CAN3_ERR_IRQHandler
+
+#if defined(BSP_USING_CAN1)
+#define CAN1_CONFIG \
+ { \
+ .name = "can1", \
+ .can_x = CAN1, \
+ .tx_irqn = CAN1_TX_IRQn, \
+ .rx_irqn = CAN1_RX_IRQn, \
+ .stat_irqn = CAN1_STAT_IRQn, \
+ .err_irqn = CAN1_ERR_IRQn, \
+ }
+#endif /* BSP_USING_CAN1 */
+
+#if defined(BSP_USING_CAN2)
+#define CAN2_CONFIG \
+ { \
+ .name = "can2", \
+ .can_x = CAN2, \
+ .tx_irqn = CAN2_TX_IRQn, \
+ .rx_irqn = CAN2_RX_IRQn, \
+ .stat_irqn = CAN2_STAT_IRQn, \
+ .err_irqn = CAN2_ERR_IRQn, \
+ }
+#endif /* BSP_USING_CAN2 */
+
+#if defined(BSP_USING_CAN3)
+#define CAN3_CONFIG \
+ { \
+ .name = "can3", \
+ .can_x = CAN3, \
+ .tx_irqn = CAN3_TX_IRQn, \
+ .rx_irqn = CAN3_RX_IRQn, \
+ .stat_irqn = CAN3_STAT_IRQn, \
+ .err_irqn = CAN3_ERR_IRQn, \
+ }
+#endif /* BSP_USING_CAN3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/rt_drivers/config/f45x/dac_config.h b/bsp/at32/libraries/rt_drivers/config/f45x/dac_config.h
new file mode 100644
index 00000000000..eeb2567093f
--- /dev/null
+++ b/bsp/at32/libraries/rt_drivers/config/f45x/dac_config.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-12-18 shelton first version
+ */
+
+#ifndef __DAC_CONFIG_H__
+#define __DAC_CONFIG_H__
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_DAC1)
+#define DAC1_CONFIG \
+ { \
+ .name = "dac1", \
+ .dac_x = DAC, \
+ }
+#endif /* BSP_USING_DAC1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/rt_drivers/config/f45x/dma_config.h b/bsp/at32/libraries/rt_drivers/config/f45x/dma_config.h
new file mode 100644
index 00000000000..061d1ac4833
--- /dev/null
+++ b/bsp/at32/libraries/rt_drivers/config/f45x/dma_config.h
@@ -0,0 +1,248 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-12-18 shelton first version
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 channel1 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_CHANNEL)
+#define SPI1_RX_DMA_IRQHandler DMA1_Channel1_IRQHandler
+#define SPI1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
+#define SPI1_RX_DMA_CHANNEL DMA1_CHANNEL1
+#define SPI1_RX_DMA_IRQ DMA1_Channel1_IRQn
+#define SPI1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1
+#define SPI1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_SPI1_RX
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_CHANNEL)
+#define UART1_RX_DMA_IRQHandler DMA1_Channel1_IRQHandler
+#define UART1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
+#define UART1_RX_DMA_CHANNEL DMA1_CHANNEL1
+#define UART1_RX_DMA_IRQ DMA1_Channel1_IRQn
+#define UART1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1
+#define UART1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART1_RX
+#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_CHANNEL)
+#define I2C1_RX_DMA_IRQHandler DMA1_Channel1_IRQHandler
+#define I2C1_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
+#define I2C1_RX_DMA_CHANNEL DMA1_CHANNEL1
+#define I2C1_RX_DMA_IRQ DMA1_Channel1_IRQn
+#define I2C1_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL1
+#define I2C1_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C1_RX
+#endif
+
+/* DMA1 channel2 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_CHANNEL)
+#define SPI1_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler
+#define SPI1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
+#define SPI1_TX_DMA_CHANNEL DMA1_CHANNEL2
+#define SPI1_TX_DMA_IRQ DMA1_Channel2_IRQn
+#define SPI1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2
+#define SPI1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_SPI1_TX
+#elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_CHANNEL)
+#define UART1_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler
+#define UART1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
+#define UART1_TX_DMA_CHANNEL DMA1_CHANNEL2
+#define UART1_TX_DMA_IRQ DMA1_Channel2_IRQn
+#define UART1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2
+#define UART1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART1_TX
+#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_CHANNEL)
+#define I2C1_TX_DMA_IRQHandler DMA1_Channel2_IRQHandler
+#define I2C1_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
+#define I2C1_TX_DMA_CHANNEL DMA1_CHANNEL2
+#define I2C1_TX_DMA_IRQ DMA1_Channel2_IRQn
+#define I2C1_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL2
+#define I2C1_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C1_TX
+#endif
+
+/* DMA1 channel3 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_CHANNEL)
+#define SPI2_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler
+#define SPI2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
+#define SPI2_RX_DMA_CHANNEL DMA1_CHANNEL3
+#define SPI2_RX_DMA_IRQ DMA1_Channel3_IRQn
+#define SPI2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL3
+#define SPI2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_SPI2_RX
+#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_CHANNEL)
+#define UART2_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler
+#define UART2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
+#define UART2_RX_DMA_CHANNEL DMA1_CHANNEL3
+#define UART2_RX_DMA_IRQ DMA1_Channel3_IRQn
+#define UART2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL3
+#define UART2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART2_RX
+#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_CHANNEL)
+#define I2C2_RX_DMA_IRQHandler DMA1_Channel3_IRQHandler
+#define I2C2_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
+#define I2C2_RX_DMA_CHANNEL DMA1_CHANNEL3
+#define I2C2_RX_DMA_IRQ DMA1_Channel3_IRQn
+#define I2C2_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL3
+#define I2C2_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C2_RX
+#endif
+
+/* DMA1 channel4 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_CHANNEL)
+#define SPI2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler
+#define SPI2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
+#define SPI2_TX_DMA_CHANNEL DMA1_CHANNEL4
+#define SPI2_TX_DMA_IRQ DMA1_Channel4_IRQn
+#define SPI2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL4
+#define SPI2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_SPI2_TX
+#elif defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_CHANNEL)
+#define UART2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler
+#define UART2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
+#define UART2_TX_DMA_CHANNEL DMA1_CHANNEL4
+#define UART2_TX_DMA_IRQ DMA1_Channel4_IRQn
+#define UART2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL4
+#define UART2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART2_TX
+#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_CHANNEL)
+#define I2C2_TX_DMA_IRQHandler DMA1_Channel4_IRQHandler
+#define I2C2_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
+#define I2C2_TX_DMA_CHANNEL DMA1_CHANNEL4
+#define I2C2_TX_DMA_IRQ DMA1_Channel4_IRQn
+#define I2C2_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL4
+#define I2C2_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C2_TX
+#endif
+
+/* DMA1 channel5 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_CHANNEL)
+#define SPI3_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler
+#define SPI3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
+#define SPI3_RX_DMA_CHANNEL DMA1_CHANNEL5
+#define SPI3_RX_DMA_IRQ DMA1_Channel5_IRQn
+#define SPI3_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL5
+#define SPI3_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_SPI3_RX
+#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_CHANNEL)
+#define UART3_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler
+#define UART3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
+#define UART3_RX_DMA_CHANNEL DMA1_CHANNEL5
+#define UART3_RX_DMA_IRQ DMA1_Channel5_IRQn
+#define UART3_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL5
+#define UART3_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART3_RX
+#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_CHANNEL)
+#define I2C3_RX_DMA_IRQHandler DMA1_Channel5_IRQHandler
+#define I2C3_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
+#define I2C3_RX_DMA_CHANNEL DMA1_CHANNEL5
+#define I2C3_RX_DMA_IRQ DMA1_Channel5_IRQn
+#define I2C3_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL5
+#define I2C3_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C3_RX
+#endif
+
+/* DMA1 channel6 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_CHANNEL)
+#define SPI3_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler
+#define SPI3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
+#define SPI3_TX_DMA_CHANNEL DMA1_CHANNEL6
+#define SPI3_TX_DMA_IRQ DMA1_Channel6_IRQn
+#define SPI3_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL6
+#define SPI3_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_SPI3_TX
+#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_CHANNEL)
+#define UART3_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler
+#define UART3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
+#define UART3_TX_DMA_CHANNEL DMA1_CHANNEL6
+#define UART3_TX_DMA_IRQ DMA1_Channel6_IRQn
+#define UART3_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL6
+#define UART3_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART3_TX
+#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_CHANNEL)
+#define I2C3_TX_DMA_IRQHandler DMA1_Channel6_IRQHandler
+#define I2C3_TX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
+#define I2C3_TX_DMA_CHANNEL DMA1_CHANNEL6
+#define I2C3_TX_DMA_IRQ DMA1_Channel6_IRQn
+#define I2C3_TX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL6
+#define I2C3_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_I2C3_TX
+#endif
+
+/* DMA1 channel7 */
+#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_CHANNEL)
+#define UART4_RX_DMA_IRQHandler DMA1_Channel7_IRQHandler
+#define UART4_RX_DMA_CLOCK CRM_DMA1_PERIPH_CLOCK
+#define UART4_RX_DMA_CHANNEL DMA1_CHANNEL7
+#define UART4_RX_DMA_IRQ DMA1_Channel7_IRQn
+#define UART4_RX_DMA_MUX_CHANNEL DMA1MUX_CHANNEL7
+#define UART4_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART4_RX
+#endif
+
+/* DMA2 channel1 */
+#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_CHANNEL)
+#define UART4_TX_DMA_IRQHandler DMA2_Channel1_IRQHandler
+#define UART4_TX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK
+#define UART4_TX_DMA_CHANNEL DMA2_CHANNEL1
+#define UART4_TX_DMA_IRQ DMA2_Channel1_IRQn
+#define UART4_TX_DMA_MUX_CHANNEL DMA2MUX_CHANNEL1
+#define UART4_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART4_TX
+#endif
+
+/* DMA2 channel2 */
+#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_CHANNEL)
+#define UART5_RX_DMA_IRQHandler DMA2_Channel2_IRQHandler
+#define UART5_RX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK
+#define UART5_RX_DMA_CHANNEL DMA2_CHANNEL2
+#define UART5_RX_DMA_IRQ DMA2_Channel2_IRQn
+#define UART5_RX_DMA_MUX_CHANNEL DMA2MUX_CHANNEL2
+#define UART5_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART5_RX
+#endif
+
+/* DMA2 channel3 */
+#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_CHANNEL)
+#define UART5_TX_DMA_IRQHandler DMA2_Channel3_IRQHandler
+#define UART5_TX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK
+#define UART5_TX_DMA_CHANNEL DMA2_CHANNEL3
+#define UART5_TX_DMA_IRQ DMA2_Channel3_IRQn
+#define UART5_TX_DMA_MUX_CHANNEL DMA2MUX_CHANNEL3
+#define UART5_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART5_TX
+#endif
+
+/* DMA2 channel4 */
+#if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_CHANNEL)
+#define UART6_RX_DMA_IRQHandler DMA2_Channel4_IRQHandler
+#define UART6_RX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK
+#define UART6_RX_DMA_CHANNEL DMA2_CHANNEL4
+#define UART6_RX_DMA_IRQ DMA2_Channel4_IRQn
+#define UART6_RX_DMA_MUX_CHANNEL DMA2MUX_CHANNEL4
+#define UART6_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART6_RX
+#endif
+
+/* DMA2 channel5 */
+#if defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_CHANNEL)
+#define UART6_TX_DMA_IRQHandler DMA2_Channel5_IRQHandler
+#define UART6_TX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK
+#define UART6_TX_DMA_CHANNEL DMA2_CHANNEL5
+#define UART6_TX_DMA_IRQ DMA2_Channel5_IRQn
+#define UART6_TX_DMA_MUX_CHANNEL DMA2MUX_CHANNEL5
+#define UART6_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART6_TX
+#endif
+
+/* DMA2 channel6 */
+#if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_CHANNEL)
+#define UART7_RX_DMA_IRQHandler DMA2_Channel6_IRQHandler
+#define UART7_RX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK
+#define UART7_RX_DMA_CHANNEL DMA2_CHANNEL6
+#define UART7_RX_DMA_IRQ DMA2_Channel6_IRQn
+#define UART7_RX_DMA_MUX_CHANNEL DMA2MUX_CHANNEL6
+#define UART7_RX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART7_RX
+#endif
+
+/* DMA2 channel7 */
+#if defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_CHANNEL)
+#define UART7_TX_DMA_IRQHandler DMA2_Channel7_IRQHandler
+#define UART7_TX_DMA_CLOCK CRM_DMA2_PERIPH_CLOCK
+#define UART7_TX_DMA_CHANNEL DMA2_CHANNEL7
+#define UART7_TX_DMA_IRQ DMA2_Channel7_IRQn
+#define UART7_TX_DMA_MUX_CHANNEL DMA2MUX_CHANNEL7
+#define UART7_TX_DMA_REQ_ID DMAMUX_DMAREQ_ID_USART7_TX
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */
diff --git a/bsp/at32/libraries/rt_drivers/config/f45x/i2c_config.h b/bsp/at32/libraries/rt_drivers/config/f45x/i2c_config.h
new file mode 100644
index 00000000000..b816e5735ca
--- /dev/null
+++ b/bsp/at32/libraries/rt_drivers/config/f45x/i2c_config.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-12-18 shelton first version
+ */
+
+#ifndef __I2C_CONFIG_H__
+#define __I2C_CONFIG_H__
+
+#include
+#include "dma_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define HWI2C_OWN_ADDRESS 0x0
+
+#define I2C1_EVT_IRQHandler I2C1_EVT_IRQHandler
+#define I2C1_ERR_IRQHandler I2C1_ERR_IRQHandler
+#define I2C2_EVT_IRQHandler I2C2_EVT_IRQHandler
+#define I2C2_ERR_IRQHandler I2C2_ERR_IRQHandler
+#define I2C3_EVT_IRQHandler I2C3_EVT_IRQHandler
+#define I2C3_ERR_IRQHandler I2C3_ERR_IRQHandler
+
+#ifdef BSP_USING_HARD_I2C1
+#define I2C1_CONFIG \
+ { \
+ .i2c_x = I2C1, \
+ .i2c_name = "hwi2c1", \
+ .timing = 0x01F03333, \
+ .ev_irqn = I2C1_EVT_IRQn, \
+ .er_irqn = I2C1_ERR_IRQn, \
+ }
+#endif /* BSP_USING_HARD_I2C1 */
+
+#ifdef BSP_I2C1_RX_USING_DMA
+#define I2C1_RX_DMA_CONFIG \
+ { \
+ .dma_channel = I2C1_RX_DMA_CHANNEL, \
+ .dma_clock = I2C1_RX_DMA_CLOCK, \
+ .dma_irqn = I2C1_RX_DMA_IRQ, \
+ .dmamux_channel = I2C1_RX_DMA_MUX_CHANNEL, \
+ .request_id = I2C1_RX_DMA_REQ_ID, \
+ }
+#endif /* BSP_I2C1_RX_USING_DMA */
+
+#ifdef BSP_I2C1_TX_USING_DMA
+#define I2C1_TX_DMA_CONFIG \
+ { \
+ .dma_channel = I2C1_TX_DMA_CHANNEL, \
+ .dma_clock = I2C1_TX_DMA_CLOCK, \
+ .dma_irqn = I2C1_TX_DMA_IRQ, \
+ .dmamux_channel = I2C1_TX_DMA_MUX_CHANNEL, \
+ .request_id = I2C1_TX_DMA_REQ_ID, \
+ }
+#endif /* BSP_I2C1_TX_USING_DMA */
+
+#ifdef BSP_USING_HARD_I2C2
+#define I2C2_CONFIG \
+ { \
+ .i2c_x = I2C2, \
+ .i2c_name = "hwi2c2", \
+ .timing = 0x01F03333, \
+ .ev_irqn = I2C2_EVT_IRQn, \
+ .er_irqn = I2C2_ERR_IRQn, \
+ }
+#endif /* BSP_USING_HARD_I2C2 */
+
+#ifdef BSP_I2C2_RX_USING_DMA
+#define I2C2_RX_DMA_CONFIG \
+ { \
+ .dma_channel = I2C2_RX_DMA_CHANNEL, \
+ .dma_clock = I2C2_RX_DMA_CLOCK, \
+ .dma_irqn = I2C2_RX_DMA_IRQ, \
+ .dmamux_channel = I2C2_RX_DMA_MUX_CHANNEL, \
+ .request_id = I2C2_RX_DMA_REQ_ID, \
+ }
+#endif /* BSP_I2C2_RX_USING_DMA */
+
+#ifdef BSP_I2C2_TX_USING_DMA
+#define I2C2_TX_DMA_CONFIG \
+ { \
+ .dma_channel = I2C2_TX_DMA_CHANNEL, \
+ .dma_clock = I2C2_TX_DMA_CLOCK, \
+ .dma_irqn = I2C2_TX_DMA_IRQ, \
+ .dmamux_channel = I2C2_TX_DMA_MUX_CHANNEL, \
+ .request_id = I2C2_TX_DMA_REQ_ID, \
+ }
+#endif /* BSP_I2C2_TX_USING_DMA */
+
+#ifdef BSP_USING_HARD_I2C3
+#define I2C3_CONFIG \
+ { \
+ .i2c_x = I2C3, \
+ .i2c_name = "hwi2c3", \
+ .timing = 0x01F03333, \
+ .ev_irqn = I2C3_EVT_IRQn, \
+ .er_irqn = I2C3_ERR_IRQn, \
+ }
+#endif /* BSP_USING_HARD_I2C3 */
+
+#ifdef BSP_I2C3_RX_USING_DMA
+#define I2C3_RX_DMA_CONFIG \
+ { \
+ .dma_channel = I2C3_RX_DMA_CHANNEL, \
+ .dma_clock = I2C3_RX_DMA_CLOCK, \
+ .dma_irqn = I2C3_RX_DMA_IRQ, \
+ .dmamux_channel = I2C3_RX_DMA_MUX_CHANNEL, \
+ .request_id = I2C3_RX_DMA_REQ_ID, \
+ }
+#endif /* BSP_I2C3_RX_USING_DMA */
+
+#ifdef BSP_I2C3_TX_USING_DMA
+#define I2C3_TX_DMA_CONFIG \
+ { \
+ .dma_channel = I2C3_TX_DMA_CHANNEL, \
+ .dma_clock = I2C3_TX_DMA_CLOCK, \
+ .dma_irqn = I2C3_TX_DMA_IRQ, \
+ .dmamux_channel = I2C3_TX_DMA_MUX_CHANNEL, \
+ .request_id = I2C3_TX_DMA_REQ_ID, \
+ }
+#endif /* BSP_I2C3_TX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__I2C_CONFIG_H__ */
+
diff --git a/bsp/at32/libraries/rt_drivers/config/f45x/spi_config.h b/bsp/at32/libraries/rt_drivers/config/f45x/spi_config.h
new file mode 100644
index 00000000000..5bb287ec8bf
--- /dev/null
+++ b/bsp/at32/libraries/rt_drivers/config/f45x/spi_config.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-12-18 shelton first version
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include
+#include "dma_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SPI1_IRQHandler SPI1_IRQHandler
+#define SPI2_IRQHandler SPI2_I2S2EXT_IRQHandler
+#define SPI3_IRQHandler SPI3_I2S3EXT_IRQHandler
+
+#ifdef BSP_USING_SPI1
+#define SPI1_CONFIG \
+ { \
+ .spi_x = SPI1, \
+ .spi_name = "spi1", \
+ .irqn = SPI1_IRQn, \
+ }
+#endif /* BSP_USING_SPI1 */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#define SPI1_RX_DMA_CONFIG \
+ { \
+ .dma_channel = SPI1_RX_DMA_CHANNEL, \
+ .dma_clock = SPI1_RX_DMA_CLOCK, \
+ .dma_irqn = SPI1_RX_DMA_IRQ, \
+ .dmamux_channel = SPI1_RX_DMA_MUX_CHANNEL, \
+ .request_id = SPI1_RX_DMA_REQ_ID, \
+ }
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_SPI1_TX_USING_DMA
+#define SPI1_TX_DMA_CONFIG \
+ { \
+ .dma_channel = SPI1_TX_DMA_CHANNEL, \
+ .dma_clock = SPI1_TX_DMA_CLOCK, \
+ .dma_irqn = SPI1_TX_DMA_IRQ, \
+ .dmamux_channel = SPI1_TX_DMA_MUX_CHANNEL, \
+ .request_id = SPI1_TX_DMA_REQ_ID, \
+ }
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#define SPI2_CONFIG \
+ { \
+ .spi_x = SPI2, \
+ .spi_name = "spi2", \
+ .irqn = SPI2_I2S2EXT_IRQn, \
+ }
+#endif /* BSP_USING_SPI2 */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#define SPI2_RX_DMA_CONFIG \
+ { \
+ .dma_channel = SPI2_RX_DMA_CHANNEL, \
+ .dma_clock = SPI2_RX_DMA_CLOCK, \
+ .dma_irqn = SPI2_RX_DMA_IRQ, \
+ .dmamux_channel = SPI2_RX_DMA_MUX_CHANNEL, \
+ .request_id = SPI2_RX_DMA_REQ_ID, \
+ }
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_SPI2_TX_USING_DMA
+#define SPI2_TX_DMA_CONFIG \
+ { \
+ .dma_channel = SPI2_TX_DMA_CHANNEL, \
+ .dma_clock = SPI2_TX_DMA_CLOCK, \
+ .dma_irqn = SPI2_TX_DMA_IRQ, \
+ .dmamux_channel = SPI2_TX_DMA_MUX_CHANNEL, \
+ .request_id = SPI2_TX_DMA_REQ_ID, \
+ }
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#define SPI3_CONFIG \
+ { \
+ .spi_x = SPI3, \
+ .spi_name = "spi3", \
+ .irqn = SPI3_I2S3EXT_IRQn, \
+ }
+#endif /* BSP_USING_SPI3 */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#define SPI3_RX_DMA_CONFIG \
+ { \
+ .dma_channel = SPI3_RX_DMA_CHANNEL, \
+ .dma_clock = SPI3_RX_DMA_CLOCK, \
+ .dma_irqn = SPI3_RX_DMA_IRQ, \
+ .dmamux_channel = SPI3_RX_DMA_MUX_CHANNEL, \
+ .request_id = SPI3_RX_DMA_REQ_ID, \
+ }
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef BSP_SPI3_TX_USING_DMA
+#define SPI3_TX_DMA_CONFIG \
+ { \
+ .dma_channel = SPI3_TX_DMA_CHANNEL, \
+ .dma_clock = SPI3_TX_DMA_CLOCK, \
+ .dma_irqn = SPI3_TX_DMA_IRQ, \
+ .dmamux_channel = SPI3_TX_DMA_MUX_CHANNEL, \
+ .request_id = SPI3_TX_DMA_REQ_ID, \
+ }
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */
diff --git a/bsp/at32/libraries/rt_drivers/config/f45x/uart_config.h b/bsp/at32/libraries/rt_drivers/config/f45x/uart_config.h
new file mode 100644
index 00000000000..2e3d2f826f0
--- /dev/null
+++ b/bsp/at32/libraries/rt_drivers/config/f45x/uart_config.h
@@ -0,0 +1,260 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-12-18 shelton first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include
+#include "dma_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define UART1_IRQHandler USART1_IRQHandler
+#define UART2_IRQHandler USART2_IRQHandler
+#define UART3_IRQHandler USART3_IRQHandler
+#define UART4_IRQHandler USART4_IRQHandler
+#define UART5_IRQHandler USART5_IRQHandler
+#define UART6_IRQHandler USART6_IRQHandler
+#define UART7_IRQHandler USART7_IRQHandler
+#define UART8_IRQHandler USART8_IRQHandler
+
+#if defined(BSP_USING_UART1)
+#define UART1_CONFIG \
+ { \
+ .name = "uart1", \
+ .uart_x = USART1, \
+ .irqn = USART1_IRQn, \
+ }
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#define UART1_RX_DMA_CONFIG \
+ { \
+ .dma_channel = UART1_RX_DMA_CHANNEL, \
+ .dma_clock = UART1_RX_DMA_CLOCK, \
+ .dma_irqn = UART1_RX_DMA_IRQ, \
+ .dmamux_channel = UART1_RX_DMA_MUX_CHANNEL, \
+ .request_id = UART1_RX_DMA_REQ_ID, \
+ }
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#define UART1_TX_DMA_CONFIG \
+ { \
+ .dma_channel = UART1_TX_DMA_CHANNEL, \
+ .dma_clock = UART1_TX_DMA_CLOCK, \
+ .dma_irqn = UART1_TX_DMA_IRQ, \
+ .dmamux_channel = UART1_TX_DMA_MUX_CHANNEL, \
+ .request_id = UART1_TX_DMA_REQ_ID, \
+ }
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#define UART2_CONFIG \
+ { \
+ .name = "uart2", \
+ .uart_x = USART2, \
+ .irqn = USART2_IRQn, \
+ }
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#define UART2_RX_DMA_CONFIG \
+ { \
+ .dma_channel = UART2_RX_DMA_CHANNEL, \
+ .dma_clock = UART2_RX_DMA_CLOCK, \
+ .dma_irqn = UART2_RX_DMA_IRQ, \
+ .dmamux_channel = UART2_RX_DMA_MUX_CHANNEL, \
+ .request_id = UART2_RX_DMA_REQ_ID, \
+ }
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_UART2_TX_USING_DMA)
+#define UART2_TX_DMA_CONFIG \
+ { \
+ .dma_channel = UART2_TX_DMA_CHANNEL, \
+ .dma_clock = UART2_TX_DMA_CLOCK, \
+ .dma_irqn = UART2_TX_DMA_IRQ, \
+ .dmamux_channel = UART2_TX_DMA_MUX_CHANNEL, \
+ .request_id = UART2_TX_DMA_REQ_ID, \
+ }
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#define UART3_CONFIG \
+ { \
+ .name = "uart3", \
+ .uart_x = USART3, \
+ .irqn = USART3_IRQn, \
+ }
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#define UART3_RX_DMA_CONFIG \
+ { \
+ .dma_channel = UART3_RX_DMA_CHANNEL, \
+ .dma_clock = UART3_RX_DMA_CLOCK, \
+ .dma_irqn = UART3_RX_DMA_IRQ, \
+ .dmamux_channel = UART3_RX_DMA_MUX_CHANNEL, \
+ .request_id = UART3_RX_DMA_REQ_ID, \
+ }
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#if defined(BSP_UART3_TX_USING_DMA)
+#define UART3_TX_DMA_CONFIG \
+ { \
+ .dma_channel = UART3_TX_DMA_CHANNEL, \
+ .dma_clock = UART3_TX_DMA_CLOCK, \
+ .dma_irqn = UART3_TX_DMA_IRQ, \
+ .dmamux_channel = UART3_TX_DMA_MUX_CHANNEL, \
+ .request_id = UART3_TX_DMA_REQ_ID, \
+ }
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#define UART4_CONFIG \
+ { \
+ .name = "uart4", \
+ .uart_x = USART4, \
+ .irqn = USART4_IRQn, \
+ }
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#define UART4_RX_DMA_CONFIG \
+ { \
+ .dma_channel = UART4_RX_DMA_CHANNEL, \
+ .dma_clock = UART4_RX_DMA_CLOCK, \
+ .dma_irqn = UART4_RX_DMA_IRQ, \
+ .dmamux_channel = UART4_RX_DMA_MUX_CHANNEL, \
+ .request_id = UART4_RX_DMA_REQ_ID, \
+ }
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_UART4_TX_USING_DMA)
+#define UART4_TX_DMA_CONFIG \
+ { \
+ .dma_channel = UART4_TX_DMA_CHANNEL, \
+ .dma_clock = UART4_TX_DMA_CLOCK, \
+ .dma_irqn = UART4_TX_DMA_IRQ, \
+ .dmamux_channel = UART4_TX_DMA_MUX_CHANNEL, \
+ .request_id = UART4_TX_DMA_REQ_ID, \
+ }
+#endif /* BSP_UART4_TX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#define UART5_CONFIG \
+ { \
+ .name = "uart5", \
+ .uart_x = USART5, \
+ .irqn = USART5_IRQn, \
+ }
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#define UART5_RX_DMA_CONFIG \
+ { \
+ .dma_channel = UART5_RX_DMA_CHANNEL, \
+ .dma_clock = UART5_RX_DMA_CLOCK, \
+ .dma_irqn = UART5_RX_DMA_IRQ, \
+ .dmamux_channel = UART5_RX_DMA_MUX_CHANNEL, \
+ .request_id = UART5_RX_DMA_REQ_ID, \
+ }
+#endif /* BSP_UART5_RX_USING_DMA */
+
+#if defined(BSP_UART5_TX_USING_DMA)
+#define UART5_TX_DMA_CONFIG \
+ { \
+ .dma_channel = UART5_TX_DMA_CHANNEL, \
+ .dma_clock = UART5_TX_DMA_CLOCK, \
+ .dma_irqn = UART5_TX_DMA_IRQ, \
+ .dmamux_channel = UART5_TX_DMA_MUX_CHANNEL, \
+ .request_id = UART5_TX_DMA_REQ_ID, \
+ }
+#endif /* BSP_UART5_TX_USING_DMA */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_USING_UART6)
+#define UART6_CONFIG \
+ { \
+ .name = "uart6", \
+ .uart_x = USART6, \
+ .irqn = USART6_IRQn, \
+ }
+
+#if defined(BSP_UART6_RX_USING_DMA)
+#define UART6_RX_DMA_CONFIG \
+ { \
+ .dma_channel = UART6_RX_DMA_CHANNEL, \
+ .dma_clock = UART6_RX_DMA_CLOCK, \
+ .dma_irqn = UART6_RX_DMA_IRQ, \
+ .dmamux_channel = UART6_RX_DMA_MUX_CHANNEL, \
+ .request_id = UART6_RX_DMA_REQ_ID, \
+ }
+#endif /* BSP_UART6_RX_USING_DMA */
+
+#if defined(BSP_UART6_TX_USING_DMA)
+#define UART6_TX_DMA_CONFIG \
+ { \
+ .dma_channel = UART6_TX_DMA_CHANNEL, \
+ .dma_clock = UART6_TX_DMA_CLOCK, \
+ .dma_irqn = UART6_TX_DMA_IRQ, \
+ .dmamux_channel = UART6_TX_DMA_MUX_CHANNEL, \
+ .request_id = UART6_TX_DMA_REQ_ID, \
+ }
+#endif /* BSP_UART6_TX_USING_DMA */
+#endif /* BSP_USING_UART6 */
+
+#if defined(BSP_USING_UART7)
+#define UART7_CONFIG \
+ { \
+ .name = "uart7", \
+ .uart_x = USART7, \
+ .irqn = USART7_IRQn, \
+ }
+
+#if defined(BSP_UART7_RX_USING_DMA)
+#define UART7_RX_DMA_CONFIG \
+ { \
+ .dma_channel = UART7_RX_DMA_CHANNEL, \
+ .dma_clock = UART7_RX_DMA_CLOCK, \
+ .dma_irqn = UART7_RX_DMA_IRQ, \
+ .dmamux_channel = UART7_RX_DMA_MUX_CHANNEL, \
+ .request_id = UART7_RX_DMA_REQ_ID, \
+ }
+#endif /* BSP_UART7_RX_USING_DMA */
+
+#if defined(BSP_UART7_TX_USING_DMA)
+#define UART7_TX_DMA_CONFIG \
+ { \
+ .dma_channel = UART7_TX_DMA_CHANNEL, \
+ .dma_clock = UART7_TX_DMA_CLOCK, \
+ .dma_irqn = UART7_TX_DMA_IRQ, \
+ .dmamux_channel = UART7_TX_DMA_MUX_CHANNEL, \
+ .request_id = UART7_TX_DMA_REQ_ID, \
+ }
+#endif /* BSP_UART7_TX_USING_DMA */
+#endif /* BSP_USING_UART7 */
+
+#if defined(BSP_USING_UART8)
+#define UART8_CONFIG \
+ { \
+ .name = "uart8", \
+ .uart_x = USART8, \
+ .irqn = USART8_IRQn, \
+ }
+#endif /* BSP_USING_UART8 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/rt_drivers/config/f45x/usb_config.h b/bsp/at32/libraries/rt_drivers/config/f45x/usb_config.h
new file mode 100644
index 00000000000..39f09e37d6f
--- /dev/null
+++ b/bsp/at32/libraries/rt_drivers/config/f45x/usb_config.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2024-12-18 shelton first version
+ */
+
+#ifndef __USB_CONFIG_H__
+#define __USB_CONFIG_H__
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined BSP_USING_DEVICE_USBOTG1
+#define USE_OTG_DEVICE_MODE
+#endif
+
+#if defined BSP_USING_HOST_USBOTG1
+#define USE_OTG_HOST_MODE
+#endif
+
+/* usb irqhandler */
+#define OTGFS1_IRQHandler OTGFS1_IRQHandler
+
+/**
+ * @brief usb device mode config
+ */
+#define USB_EPT_MAX_NUM 8
+
+/* otg1 device fifo */
+#define USBD_RX_SIZE 128
+#define USBD_EP0_TX_SIZE 24
+#define USBD_EP1_TX_SIZE 20
+#define USBD_EP2_TX_SIZE 20
+#define USBD_EP3_TX_SIZE 20
+#define USBD_EP4_TX_SIZE 20
+#define USBD_EP5_TX_SIZE 20
+#define USBD_EP6_TX_SIZE 20
+#define USBD_EP7_TX_SIZE 20
+
+/* otg2 device fifo */
+#define USBD2_RX_SIZE 256
+#define USBD2_EP0_TX_SIZE 64
+#define USBD2_EP1_TX_SIZE 256
+#define USBD2_EP2_TX_SIZE 256
+#define USBD2_EP3_TX_SIZE 20
+#define USBD2_EP4_TX_SIZE 20
+#define USBD2_EP5_TX_SIZE 20
+#define USBD2_EP6_TX_SIZE 20
+#define USBD2_EP7_TX_SIZE 20
+
+/**
+ * @brief usb host mode config
+ */
+#define USB_HOST_CHANNEL_NUM 16
+
+/* otg1 host fifo */
+#define USBH_RX_FIFO_SIZE 128
+#define USBH_NP_TX_FIFO_SIZE 96
+#define USBH_P_TX_FIFO_SIZE 96
+
+/* otg2 host fifo */
+#define USBH2_RX_FIFO_SIZE 256
+#define USBH2_NP_TX_FIFO_SIZE 256
+#define USBH2_P_TX_FIFO_SIZE 256
+
+/**
+ * @brief usb sof output enable
+ */
+// #define USB_SOF_OUTPUT_ENABLE
+
+/**
+ * @brief usb vbus ignore, not use vbus pin
+ */
+#define USB_VBUS_IGNORE
+
+/**
+ * @brief usb high speed support dma mode
+ */
+// #define OTG_USE_DMA
+
+/**
+ * @brief usb low power wakeup handler enable
+ */
+// #define USB_LOW_POWER_WAKUP
+
+#if defined(BSP_USING_HOST_USBOTG1)
+#undef BSP_USING_DEVICE_USBOTG1
+#define USBOTG1_CONFIG \
+ { \
+ .name = "usbh1", \
+ .id = USB_OTG1_ID, \
+ .dev_spd = USB_FULL_SPEED_CORE_ID, \
+ .irqn = OTGFS1_IRQn, \
+ }
+#endif /* BSP_USING_HOST_USBOTG1 */
+
+#if defined(BSP_USING_DEVICE_USBOTG1)
+#define USBOTG1_CONFIG \
+ { \
+ .name = "usbd", \
+ .id = USB_OTG1_ID, \
+ .dev_spd = USB_FULL_SPEED_CORE_ID, \
+ .irqn = OTGFS1_IRQn, \
+ }
+#endif /* BSP_USING_DEVICE_USBOTG1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/at32/libraries/rt_drivers/drv_adc.c b/bsp/at32/libraries/rt_drivers/drv_adc.c
index f989cc8c373..e217cd23111 100644
--- a/bsp/at32/libraries/rt_drivers/drv_adc.c
+++ b/bsp/at32/libraries/rt_drivers/drv_adc.c
@@ -11,6 +11,7 @@
* 2023-10-18 shelton add support f402/f405
* 2024-04-12 shelton add support a403a and a423
* 2024-08-30 shelton add support m412 and m416
+ * 2024-12-18 shelton add support f455/f456 and f457
*/
#include "drv_common.h"
@@ -51,7 +52,9 @@ static rt_err_t at32_adc_enabled(struct rt_adc_device *device, rt_int8_t channel
adc_base_config_type adc_config_struct;
#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32A423) || \
- defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416)
+ defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416) || \
+ defined (SOC_SERIES_AT32F455) || defined (SOC_SERIES_AT32F456) || \
+ defined (SOC_SERIES_AT32F457)
adc_common_config_type adc_common_struct;
adc_common_default_para_init(&adc_common_struct);
#endif
@@ -62,7 +65,9 @@ static rt_err_t at32_adc_enabled(struct rt_adc_device *device, rt_int8_t channel
at32_msp_adc_init(adc_x);
#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
- defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416)
+ defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416) || \
+ defined (SOC_SERIES_AT32F455) || defined (SOC_SERIES_AT32F456) || \
+ defined (SOC_SERIES_AT32F457)
/* config combine mode */
adc_common_struct.combine_mode = ADC_INDEPENDENT_MODE;
/* config division, adcclk is division by hclk */
@@ -76,7 +81,9 @@ static rt_err_t at32_adc_enabled(struct rt_adc_device *device, rt_int8_t channel
/* config inner temperature sensor and vintrv */
adc_common_struct.tempervintrv_state = FALSE;
/* config voltage battery */
-#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437)
+#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
+ defined (SOC_SERIES_AT32F455) || defined (SOC_SERIES_AT32F456) || \
+ defined (SOC_SERIES_AT32F457)
adc_common_struct.vbat_state = FALSE;
#endif
adc_common_config(&adc_common_struct);
@@ -140,7 +147,9 @@ static rt_err_t at32_get_adc_value(struct rt_adc_device *device, rt_int8_t chann
/* adc_x regular channels configuration */
#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
- defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32A423)
+ defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32A423) || \
+ defined (SOC_SERIES_AT32F455) || defined (SOC_SERIES_AT32F456) || \
+ defined (SOC_SERIES_AT32F457)
adc_flag_clear(adc_x, ADC_OCCE_FLAG);
adc_ordinary_channel_set(adc_x, (adc_channel_select_type)channel, 1, ADC_SAMPLETIME_247_5);
#else
@@ -158,7 +167,9 @@ static rt_err_t at32_get_adc_value(struct rt_adc_device *device, rt_int8_t chann
/* wait for the adc to convert */
#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32A423) || \
- defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416)
+ defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416) || \
+ defined (SOC_SERIES_AT32F455) || defined (SOC_SERIES_AT32F456) || \
+ defined (SOC_SERIES_AT32F457)
while((adc_flag_get(adc_x, ADC_OCCE_FLAG) == RESET) && timeout < 0xFFFF)
#else
while((adc_flag_get(adc_x, ADC_CCE_FLAG) == RESET) && timeout < 0xFFFF)
diff --git a/bsp/at32/libraries/rt_drivers/drv_can_v2.c b/bsp/at32/libraries/rt_drivers/drv_can_v2.c
index 6bb41f80402..5bf46b57851 100644
--- a/bsp/at32/libraries/rt_drivers/drv_can_v2.c
+++ b/bsp/at32/libraries/rt_drivers/drv_can_v2.c
@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2024-08-30 shelton first version
+ * 2024-12-18 shelton add support f455/f456 and f457
*/
#include "drv_can_v2.h"
@@ -68,6 +69,83 @@ static const struct at32_baud_rate_fd canfd_baud_rate_tab[] =
#endif
#endif
+#ifdef SOC_SERIES_AT32F455
+/* attention !!! baud calculation example: apbclk / ((bs1 + bs2) * bittime_div), ep: 192 / ((48 + 144) * 1) = 1MHz*/
+/* attention !!! default apbclk 192 mhz */
+static const struct at32_baud_rate can_baud_rate_tab[] =
+{
+ {CAN1MBaud, 1 , 48, 144, 48},
+ {CAN800kBaud, 1 , 60, 180, 60},
+ {CAN500kBaud, 1 , 96, 288, 96},
+ {CAN250kBaud, 2 , 96, 288, 96},
+ {CAN125kBaud, 3 , 128, 384, 128},
+ {CAN100kBaud, 4 , 120, 260, 120},
+ {CAN50kBaud, 8, 120, 260, 120},
+ {CAN20kBaud, 16, 150, 450, 150},
+ {CAN10kBaud, 24, 200, 600, 200},
+};
+#endif
+
+#ifdef SOC_SERIES_AT32F456
+/* attention !!! baud calculation example: apbclk / ((bs1 + bs2) * bittime_div), ep: 192 / ((48 + 144) * 1) = 1MHz*/
+/* attention !!! default apbclk 192 mhz */
+static const struct at32_baud_rate can_baud_rate_tab[] =
+{
+ {CAN1MBaud, 1 , 48, 144, 48},
+ {CAN800kBaud, 1 , 60, 180, 60},
+ {CAN500kBaud, 1 , 96, 288, 96},
+ {CAN250kBaud, 2 , 96, 288, 96},
+ {CAN125kBaud, 3 , 128, 384, 128},
+ {CAN100kBaud, 4 , 120, 260, 120},
+ {CAN50kBaud, 8, 120, 260, 120},
+ {CAN20kBaud, 16, 150, 450, 150},
+ {CAN10kBaud, 24, 200, 600, 200},
+};
+
+#ifdef RT_CAN_USING_CANFD
+/* attention !!! baud calculation example: apbclk / ((bs1 + bs2) * bittime_div), ep: 192 / ((48 + 144) * 1) = 1MHz*/
+/* attention !!! default apbclk 192 mhz, ssoffset default value is 'seg1 + 1', baud_rate_fd.div must equal to baud_rate.div */
+static const struct at32_baud_rate_fd canfd_baud_rate_tab[] =
+{
+ {CANFD_DATA_1MBaud, 1 , 48, 144, 48, 145},
+ {CANFD_DATA_2MBaud, 1 , 24, 72, 24, 25},
+ {CANFD_DATA_3MBaud, 1 , 16, 48, 16, 49},
+ {CANFD_DATA_4MBaud, 1 , 12, 36, 12, 37},
+ {CANFD_DATA_6MBaud, 1 , 12, 24, 12, 25},
+};
+#endif
+#endif
+
+#ifdef SOC_SERIES_AT32F457
+/* attention !!! baud calculation example: apbclk / ((bs1 + bs2) * bittime_div), ep: 192 / ((48 + 144) * 1) = 1MHz*/
+/* attention !!! default apbclk 192 mhz */
+static const struct at32_baud_rate can_baud_rate_tab[] =
+{
+ {CAN1MBaud, 1 , 48, 144, 48},
+ {CAN800kBaud, 1 , 60, 180, 60},
+ {CAN500kBaud, 1 , 96, 288, 96},
+ {CAN250kBaud, 2 , 96, 288, 96},
+ {CAN125kBaud, 3 , 128, 384, 128},
+ {CAN100kBaud, 4 , 120, 260, 120},
+ {CAN50kBaud, 8, 120, 260, 120},
+ {CAN20kBaud, 16, 150, 450, 150},
+ {CAN10kBaud, 24, 200, 600, 200},
+};
+
+#ifdef RT_CAN_USING_CANFD
+/* attention !!! baud calculation example: apbclk / ((bs1 + bs2) * bittime_div), ep: 192 / ((48 + 144) * 1) = 1MHz*/
+/* attention !!! default apbclk 192 mhz, ssoffset default value is 'seg1 + 1', baud_rate_fd.div must equal to baud_rate.div */
+static const struct at32_baud_rate_fd canfd_baud_rate_tab[] =
+{
+ {CANFD_DATA_1MBaud, 1 , 48, 144, 48, 145},
+ {CANFD_DATA_2MBaud, 1 , 24, 72, 24, 25},
+ {CANFD_DATA_3MBaud, 1 , 16, 48, 16, 49},
+ {CANFD_DATA_4MBaud, 1 , 12, 36, 12, 37},
+ {CANFD_DATA_6MBaud, 1 , 12, 24, 12, 25},
+};
+#endif
+#endif
+
enum {
#ifdef BSP_USING_CAN1
CAN1_INDEX,
diff --git a/bsp/at32/libraries/rt_drivers/drv_config.h b/bsp/at32/libraries/rt_drivers/drv_config.h
index 7c04323b2d8..c3fb387e70a 100644
--- a/bsp/at32/libraries/rt_drivers/drv_config.h
+++ b/bsp/at32/libraries/rt_drivers/drv_config.h
@@ -12,6 +12,7 @@
* 2024-04-12 shelton add support a403a and a423
* 2024-07-31 shelton add support hwi2c driver
* 2024-08-30 shelton add support m412 and m416
+ * 2024-12-18 shelton add support f455/f456 and f457
*/
#ifndef __DRV_CONFIG_H__
@@ -95,6 +96,15 @@ extern "C" {
#include "m412_416/i2c_config.h"
#include "m412_416/spi_config.h"
#include "m412_416/dac_config.h"
+#elif defined(SOC_SERIES_AT32F455) || defined (SOC_SERIES_AT32F456) || \
+ defined(SOC_SERIES_AT32F457)
+#include "f45x/can_config.h"
+#include "f45x/dma_config.h"
+#include "f45x/uart_config.h"
+#include "f45x/i2c_config.h"
+#include "f45x/spi_config.h"
+#include "f45x/usb_config.h"
+#include "f45x/dac_config.h"
#endif
#ifdef __cplusplus
diff --git a/bsp/at32/libraries/rt_drivers/drv_dma.h b/bsp/at32/libraries/rt_drivers/drv_dma.h
index cfcbda8815b..38591e12692 100644
--- a/bsp/at32/libraries/rt_drivers/drv_dma.h
+++ b/bsp/at32/libraries/rt_drivers/drv_dma.h
@@ -10,6 +10,7 @@
* 2023-04-08 shelton add support f423
* 2024-04-12 shelton add support a403a and a423
* 2024-08-30 shelton add support m412 and m416
+ * 2024-12-18 shelton add support f455/f456 and f457
*/
#ifndef __DRV_DMA_H__
@@ -42,7 +43,9 @@ struct dma_config {
#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F402) || \
defined (SOC_SERIES_AT32F405) || defined (SOC_SERIES_AT32A423) || \
- defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416)
+ defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416) || \
+ defined (SOC_SERIES_AT32F455) || defined (SOC_SERIES_AT32F456) || \
+ defined (SOC_SERIES_AT32F457)
dmamux_channel_type *dmamux_channel;
rt_uint32_t request_id;
#endif
diff --git a/bsp/at32/libraries/rt_drivers/drv_emac.c b/bsp/at32/libraries/rt_drivers/drv_emac.c
index 23b4fcdd553..f7d93f2719e 100644
--- a/bsp/at32/libraries/rt_drivers/drv_emac.c
+++ b/bsp/at32/libraries/rt_drivers/drv_emac.c
@@ -11,6 +11,7 @@
* 2022-10-15 shelton optimize code
* 2023-10-18 shelton optimize code
* 2024-09-02 shelton add support phy lan8720 and yt8512
+ * 2024-12-18 shelton add support f457
*/
#include "drv_emac.h"
@@ -101,7 +102,7 @@ static void phy_reset(void)
{
gpio_init_type gpio_init_struct;
-#if defined (SOC_SERIES_AT32F437)
+#if defined (SOC_SERIES_AT32F437) || defined (SOC_SERIES_AT32F457)
crm_periph_clock_enable(CRM_GPIOE_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_GPIOG_PERIPH_CLOCK, TRUE);
@@ -1000,7 +1001,7 @@ static int rt_hw_at32_emac_init(void)
#if defined (SOC_SERIES_AT32F407)
gpio_pin_remap_config(MII_RMII_SEL_GMUX, TRUE);
#endif
-#if defined (SOC_SERIES_AT32F437)
+#if defined (SOC_SERIES_AT32F437) || defined (SOC_SERIES_AT32F457)
scfg_emac_interface_set(SCFG_EMAC_SELECT_RMII);
#endif
diff --git a/bsp/at32/libraries/rt_drivers/drv_gpio.c b/bsp/at32/libraries/rt_drivers/drv_gpio.c
index d2f400cc904..87c601f108b 100644
--- a/bsp/at32/libraries/rt_drivers/drv_gpio.c
+++ b/bsp/at32/libraries/rt_drivers/drv_gpio.c
@@ -11,6 +11,7 @@
* 2023-10-18 shelton add support f402/f405
* 2024-04-12 shelton add support a403a and a423
* 2024-08-30 shelton add support m412 and m416
+ * 2024-12-18 shelton add support f455/f456 and f457
*/
#include "drv_common.h"
@@ -26,7 +27,9 @@
defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32F425) || \
defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F402) || \
defined (SOC_SERIES_AT32F405) || defined (SOC_SERIES_AT32A423) || \
- defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416)
+ defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416) || \
+ defined (SOC_SERIES_AT32F455) || defined (SOC_SERIES_AT32F456) || \
+ defined (SOC_SERIES_AT32F457)
#define PIN_ATPORTSOURCE(pin) (scfg_port_source_type)((uint8_t)(((pin) & 0xF0u) >> 4))
#define PIN_ATPINSOURCE(pin) (scfg_pins_source_type)((uint8_t)((pin) & 0xFu))
#else
@@ -377,7 +380,6 @@ static rt_err_t at32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
gpio_init_type gpio_init_struct;
exint_init_type exint_init_struct;
gpio_type *gpio_port;
- IRQn_Type irqn;
uint16_t gpio_pin;
const struct pin_irq_map *irqmap;
rt_base_t level;
@@ -418,7 +420,7 @@ static rt_err_t at32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
gpio_init_struct.gpio_pins = irqmap->pinbit;
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
exint_init_struct.line_select = irqmap->pinbit;
- exint_init_struct.line_mode = EXINT_LINE_INTERRUPUT;
+ exint_init_struct.line_mode = EXINT_LINE_INTERRUPT;
exint_init_struct.line_enable = TRUE;
switch (pin_irq_handler_tab[irqindex].mode)
{
@@ -438,7 +440,9 @@ static rt_err_t at32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32F425) || \
defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F402) || \
defined (SOC_SERIES_AT32F405) || defined (SOC_SERIES_AT32A423) || \
- defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416)
+ defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416) || \
+ defined (SOC_SERIES_AT32F455) || defined (SOC_SERIES_AT32F456) || \
+ defined (SOC_SERIES_AT32F457)
scfg_exint_line_config(PIN_ATPORTSOURCE(pin), PIN_ATPINSOURCE(pin));
#else
gpio_exint_line_config(PIN_ATPORTSOURCE(pin), PIN_ATPINSOURCE(pin));
@@ -461,27 +465,26 @@ static rt_err_t at32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
level = rt_hw_interrupt_disable();
pin_irq_enable_mask &= ~irqmap->pinbit;
-
+ exint_interrupt_enable(irqmap->lineno, FALSE);
if ((irqmap->pinbit >= GPIO_PINS_5) && (irqmap->pinbit <= GPIO_PINS_9))
{
if (!(pin_irq_enable_mask & (GPIO_PINS_5 | GPIO_PINS_6 | GPIO_PINS_7 | GPIO_PINS_8 | GPIO_PINS_9)))
{
- irqn = irqmap->irqno;
+ nvic_irq_disable(irqmap->irqno);
}
}
else if ((irqmap->pinbit >= GPIO_PINS_10) && (irqmap->pinbit <= GPIO_PINS_15))
{
if (!(pin_irq_enable_mask & (GPIO_PINS_10 | GPIO_PINS_11 | GPIO_PINS_12 | GPIO_PINS_13 | GPIO_PINS_14 | GPIO_PINS_15)))
{
- irqn = irqmap->irqno;
+ nvic_irq_disable(irqmap->irqno);
}
}
else
{
- irqn = irqmap->irqno;
+ nvic_irq_disable(irqmap->irqno);
}
- nvic_irq_disable(irqn);
rt_hw_interrupt_enable(level);
}
else
@@ -724,7 +727,9 @@ int rt_hw_pin_init(void)
defined (SOC_SERIES_AT32F421) || defined (SOC_SERIES_AT32F425) || \
defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F402) || \
defined (SOC_SERIES_AT32F405) || defined (SOC_SERIES_AT32A423) || \
- defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416)
+ defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416) || \
+ defined (SOC_SERIES_AT32F455) || defined (SOC_SERIES_AT32F456) || \
+ defined (SOC_SERIES_AT32F457)
crm_periph_clock_enable(CRM_SCFG_PERIPH_CLOCK, TRUE);
#else
crm_periph_clock_enable(CRM_IOMUX_PERIPH_CLOCK, TRUE);
diff --git a/bsp/at32/libraries/rt_drivers/drv_hard_i2c.c b/bsp/at32/libraries/rt_drivers/drv_hard_i2c.c
index 100eb4ec272..6bc3db1bb1e 100644
--- a/bsp/at32/libraries/rt_drivers/drv_hard_i2c.c
+++ b/bsp/at32/libraries/rt_drivers/drv_hard_i2c.c
@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2024-07-31 shelton first version
+ * 2024-12-18 shelton add support f455/f456 and f457
*/
#include "drv_common.h"
@@ -74,7 +75,8 @@ static rt_err_t at32_i2c_configure(struct rt_i2c_bus_device *bus)
defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F425) || \
defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
defined (SOC_SERIES_AT32A423) || defined (SOC_SERIES_AT32M412) || \
- defined (SOC_SERIES_AT32M416)
+ defined (SOC_SERIES_AT32M416) || defined (SOC_SERIES_AT32F455) || \
+ defined (SOC_SERIES_AT32F456) || defined (SOC_SERIES_AT32F457)
i2c_init(instance->handle->i2c_x, 0x0F, instance->handle->timing);
#endif
i2c_own_address1_set(instance->handle->i2c_x, I2C_ADDRESS_MODE_7BIT, HWI2C_OWN_ADDRESS);
@@ -103,7 +105,8 @@ static void i2c_dma_config(struct at32_i2c_handle *handle, rt_uint8_t *buffer, r
defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F425) || \
defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
defined (SOC_SERIES_AT32A423) || defined (SOC_SERIES_AT32M412) || \
- defined (SOC_SERIES_AT32M416)
+ defined (SOC_SERIES_AT32M416) || defined (SOC_SERIES_AT32F455) || \
+ defined (SOC_SERIES_AT32F456) || defined (SOC_SERIES_AT32F457)
dma->dma_channel->paddr = (rt_uint32_t)&(handle->i2c_x->txdt);
#endif
}
@@ -119,7 +122,8 @@ static void i2c_dma_config(struct at32_i2c_handle *handle, rt_uint8_t *buffer, r
defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F425) || \
defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
defined (SOC_SERIES_AT32A423) || defined (SOC_SERIES_AT32M412) || \
- defined (SOC_SERIES_AT32M416)
+ defined (SOC_SERIES_AT32M416) || defined (SOC_SERIES_AT32F455) || \
+ defined (SOC_SERIES_AT32F456) || defined (SOC_SERIES_AT32F457)
dma->dma_channel->paddr = (rt_uint32_t)&(handle->i2c_x->rxdt);
#endif
}
@@ -140,7 +144,8 @@ static void i2c_dma_config(struct at32_i2c_handle *handle, rt_uint8_t *buffer, r
defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F425) || \
defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
defined (SOC_SERIES_AT32A423) || defined (SOC_SERIES_AT32M412) || \
- defined (SOC_SERIES_AT32M416)
+ defined (SOC_SERIES_AT32M416) || defined (SOC_SERIES_AT32F455) || \
+ defined (SOC_SERIES_AT32F456) || defined (SOC_SERIES_AT32F457)
void i2c_refresh_txdt_register(i2c_type *i2c_x)
{
/* clear tdis flag */
@@ -236,7 +241,8 @@ i2c_status_type i2c_wait_flag(struct at32_i2c_handle *handle, uint32_t flag, uin
defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F425) || \
defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
defined (SOC_SERIES_AT32A423) || defined (SOC_SERIES_AT32M412) || \
- defined (SOC_SERIES_AT32M416)
+ defined (SOC_SERIES_AT32M416) || defined (SOC_SERIES_AT32F455) || \
+ defined (SOC_SERIES_AT32F456) || defined (SOC_SERIES_AT32F457)
i2c_reset_ctrl2_register(handle->i2c_x);
#endif
handle->comm.error_code = I2C_ERR_STOP;
@@ -741,7 +747,8 @@ void i2c_evt_isr(struct at32_i2c_handle *handle)
defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F425) || \
defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
defined (SOC_SERIES_AT32A423) || defined (SOC_SERIES_AT32M412) || \
- defined (SOC_SERIES_AT32M416)
+ defined (SOC_SERIES_AT32M416) || defined (SOC_SERIES_AT32F455) || \
+ defined (SOC_SERIES_AT32F456) || defined (SOC_SERIES_AT32F457)
void i2c_start_transfer(struct at32_i2c_handle *handle, uint16_t address, i2c_start_mode_type start)
{
if (handle->comm.pcount > MAX_TRANSFER_CNT)
@@ -1233,7 +1240,9 @@ static void at32_i2c_dma_init(struct at32_i2c *instance)
#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F402) || \
defined (SOC_SERIES_AT32F405) || defined (SOC_SERIES_AT32A423) || \
- defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416)
+ defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416) || \
+ defined (SOC_SERIES_AT32F455) || defined (SOC_SERIES_AT32F456) || \
+ defined (SOC_SERIES_AT32F457)
dmamux_enable(instance->handle->dma_rx->dma_x, TRUE);
dmamux_init(instance->handle->dma_rx->dmamux_channel, (dmamux_requst_id_sel_type)instance->handle->dma_rx->request_id);
#endif
@@ -1255,7 +1264,9 @@ static void at32_i2c_dma_init(struct at32_i2c *instance)
#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F402) || \
defined (SOC_SERIES_AT32F405) || defined (SOC_SERIES_AT32A423) || \
- defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416)
+ defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416) || \
+ defined (SOC_SERIES_AT32F455) || defined (SOC_SERIES_AT32F456) || \
+ defined (SOC_SERIES_AT32F457)
dmamux_enable(instance->handle->dma_tx->dma_x, TRUE);
dmamux_init(instance->handle->dma_tx->dmamux_channel, (dmamux_requst_id_sel_type)instance->handle->dma_tx->request_id);
#endif
@@ -1382,7 +1393,8 @@ void i2c_dma_isr(struct at32_i2c_handle *handle)
defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F425) || \
defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
defined (SOC_SERIES_AT32A423) || defined (SOC_SERIES_AT32M412) || \
- defined (SOC_SERIES_AT32M416)
+ defined (SOC_SERIES_AT32M416) || defined (SOC_SERIES_AT32F455) || \
+ defined (SOC_SERIES_AT32F456) || defined (SOC_SERIES_AT32F457)
/* disable dma request */
if(handle->comm.mode == I2C_DMA_MA_TX)
i2c_dma_enable(handle->i2c_x, I2C_DMA_REQUEST_TX, FALSE);
@@ -1420,7 +1432,8 @@ void i2c_dma_isr(struct at32_i2c_handle *handle)
defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F425) || \
defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
defined (SOC_SERIES_AT32A423) || defined (SOC_SERIES_AT32M412) || \
- defined (SOC_SERIES_AT32M416)
+ defined (SOC_SERIES_AT32M416) || defined (SOC_SERIES_AT32F455) || \
+ defined (SOC_SERIES_AT32F456) || defined (SOC_SERIES_AT32F457)
case I2C_DMA_MA_TX:
case I2C_DMA_MA_RX:
{
diff --git a/bsp/at32/libraries/rt_drivers/drv_rtc.c b/bsp/at32/libraries/rt_drivers/drv_rtc.c
index 774c194b074..7a677800154 100644
--- a/bsp/at32/libraries/rt_drivers/drv_rtc.c
+++ b/bsp/at32/libraries/rt_drivers/drv_rtc.c
@@ -10,6 +10,7 @@
* 2023-10-18 shelton add support f402/f405
* 2024-04-12 shelton add support a403a and a423
* 2024-08-30 shelton add support m412 and m416
+ * 2024-12-18 shelton add support f455/f456 and f457
*/
#include
@@ -54,7 +55,8 @@ static time_t get_rtc_timestamp(void)
defined (SOC_SERIES_AT32F425) || defined (SOC_SERIES_AT32F423) || \
defined (SOC_SERIES_AT32F402) || defined (SOC_SERIES_AT32F405) || \
defined (SOC_SERIES_AT32A423) || defined (SOC_SERIES_AT32M412) || \
- defined (SOC_SERIES_AT32M416)
+ defined (SOC_SERIES_AT32M416) || defined (SOC_SERIES_AT32F455) || \
+ defined (SOC_SERIES_AT32F456) || defined (SOC_SERIES_AT32F457)
struct tm tm_new;
ertc_time_type ertc_time_struct;
@@ -82,7 +84,8 @@ static rt_err_t set_rtc_time_stamp(time_t time_stamp)
defined (SOC_SERIES_AT32F425) || defined (SOC_SERIES_AT32F423) || \
defined (SOC_SERIES_AT32F402) || defined (SOC_SERIES_AT32F405) || \
defined (SOC_SERIES_AT32A423) || defined (SOC_SERIES_AT32M412) || \
- defined (SOC_SERIES_AT32M416)
+ defined (SOC_SERIES_AT32M416) || defined (SOC_SERIES_AT32F455) || \
+ defined (SOC_SERIES_AT32F456) || defined (SOC_SERIES_AT32F457)
struct tm now;
gmtime_r(&time_stamp, &now);
@@ -130,7 +133,8 @@ static rt_err_t rt_rtc_config(void)
defined (SOC_SERIES_AT32F425) || defined (SOC_SERIES_AT32F423) || \
defined (SOC_SERIES_AT32F402) || defined (SOC_SERIES_AT32F405) || \
defined (SOC_SERIES_AT32A423) || defined (SOC_SERIES_AT32M412) || \
- defined (SOC_SERIES_AT32M416)
+ defined (SOC_SERIES_AT32M416) || defined (SOC_SERIES_AT32F455) || \
+ defined (SOC_SERIES_AT32F456) || defined (SOC_SERIES_AT32F457)
/* select rtc clock source */
#ifdef BSP_RTC_USING_LICK
diff --git a/bsp/at32/libraries/rt_drivers/drv_sdio.c b/bsp/at32/libraries/rt_drivers/drv_sdio.c
index 4127de5a7ff..7ec52ea3d39 100644
--- a/bsp/at32/libraries/rt_drivers/drv_sdio.c
+++ b/bsp/at32/libraries/rt_drivers/drv_sdio.c
@@ -710,7 +710,9 @@ void sd_lowlevel_dmatx_config(uint32_t *src, uint32_t *dst, uint32_t buffer_size
dma_init(sdio_obj.dma.handle_tx, &dma_init_struct);
dma_interrupt_enable(sdio_obj.dma.handle_tx, DMA_FDT_INT, TRUE);
-#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437)
+#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
+ defined (SOC_SERIES_AT32F455) || defined (SOC_SERIES_AT32F456) || \
+ defined (SOC_SERIES_AT32F457)
dmamux_init(sdio_config.dma_tx.dmamux_channel, sdio_config.dma_tx.dmamux_id);
dmamux_enable(sdio_config.dma_tx.dma_x, TRUE);
#endif
@@ -747,7 +749,9 @@ void sd_lowlevel_dmarx_config(uint32_t *src, uint32_t *dst, uint32_t buffer_size
dma_init(sdio_obj.dma.handle_rx, &dma_init_struct);
dma_interrupt_enable(sdio_obj.dma.handle_rx, DMA_FDT_INT, TRUE);
-#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437)
+#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
+ defined (SOC_SERIES_AT32F455) || defined (SOC_SERIES_AT32F456) || \
+ defined (SOC_SERIES_AT32F457)
dmamux_init(sdio_config.dma_rx.dmamux_channel, sdio_config.dma_rx.dmamux_id);
dmamux_enable(sdio_config.dma_rx.dma_x, TRUE);
#endif
@@ -755,7 +759,9 @@ void sd_lowlevel_dmarx_config(uint32_t *src, uint32_t *dst, uint32_t buffer_size
dma_channel_enable(sdio_obj.dma.handle_rx, TRUE);
}
-#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437)
+#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
+ defined (SOC_SERIES_AT32F455) || defined (SOC_SERIES_AT32F456) || \
+ defined (SOC_SERIES_AT32F457)
void DMA2_Channel4_IRQHandler(void)
#else
void DMA2_Channel4_5_IRQHandler(void)
diff --git a/bsp/at32/libraries/rt_drivers/drv_sdio.h b/bsp/at32/libraries/rt_drivers/drv_sdio.h
index bfcd76bd487..82bd2e6ee36 100644
--- a/bsp/at32/libraries/rt_drivers/drv_sdio.h
+++ b/bsp/at32/libraries/rt_drivers/drv_sdio.h
@@ -150,7 +150,9 @@ typedef rt_err_t (*dma_txconfig)(rt_uint32_t *src, rt_uint32_t *dst, int size);
typedef rt_err_t (*dma_rxconfig)(rt_uint32_t *src, rt_uint32_t *dst, int size);
typedef rt_uint32_t (*sdio_clk_get)(struct at32_sdio *hw_sdio);
-#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437)
+#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
+ defined (SOC_SERIES_AT32F455) || defined (SOC_SERIES_AT32F456) || \
+ defined (SOC_SERIES_AT32F457)
#define SDIO_BUS_CONFIG \
{ \
.sdio_x = SDIO1, \
@@ -183,7 +185,9 @@ typedef rt_uint32_t (*sdio_clk_get)(struct at32_sdio *hw_sdio);
struct dma_config {
dma_type *dma_x;
dma_channel_type *dma_channel;
-#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437)
+#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
+ defined (SOC_SERIES_AT32F455) || defined (SOC_SERIES_AT32F456) || \
+ defined (SOC_SERIES_AT32F457)
dmamux_channel_type *dmamux_channel;
dmamux_requst_id_sel_type dmamux_id;
#endif
diff --git a/bsp/at32/libraries/rt_drivers/drv_spi.c b/bsp/at32/libraries/rt_drivers/drv_spi.c
index fdfa6e62d96..e4a3f11be23 100644
--- a/bsp/at32/libraries/rt_drivers/drv_spi.c
+++ b/bsp/at32/libraries/rt_drivers/drv_spi.c
@@ -12,6 +12,7 @@
* 2023-10-18 shelton add support f402/f405
* 2024-04-12 shelton add support a403a and a423
* 2024-08-30 shelton add support m412 and m416
+ * 2024-12-18 shelton add support f455/f456 and f457
*/
#include "drv_common.h"
@@ -537,7 +538,9 @@ static void at32_spi_dma_init(struct at32_spi *instance)
#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F402) || \
defined (SOC_SERIES_AT32F405) || defined (SOC_SERIES_AT32A423) || \
- defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416)
+ defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416) || \
+ defined (SOC_SERIES_AT32F455) || defined (SOC_SERIES_AT32F456) || \
+ defined (SOC_SERIES_AT32F457)
dmamux_enable(instance->config->dma_rx->dma_x, TRUE);
dmamux_init(instance->config->dma_rx->dmamux_channel, (dmamux_requst_id_sel_type)instance->config->dma_rx->request_id);
#endif
@@ -559,7 +562,9 @@ static void at32_spi_dma_init(struct at32_spi *instance)
#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F402) || \
defined (SOC_SERIES_AT32F405) || defined (SOC_SERIES_AT32A423) || \
- defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416)
+ defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416) || \
+ defined (SOC_SERIES_AT32F455) || defined (SOC_SERIES_AT32F456) || \
+ defined (SOC_SERIES_AT32F457)
dmamux_enable(instance->config->dma_tx->dma_x, TRUE);
dmamux_init(instance->config->dma_tx->dmamux_channel, (dmamux_requst_id_sel_type)instance->config->dma_tx->request_id);
#endif
diff --git a/bsp/at32/libraries/rt_drivers/drv_usart.c b/bsp/at32/libraries/rt_drivers/drv_usart.c
index c1ddc96e536..c75d72c5ead 100644
--- a/bsp/at32/libraries/rt_drivers/drv_usart.c
+++ b/bsp/at32/libraries/rt_drivers/drv_usart.c
@@ -12,6 +12,7 @@
* 2023-10-18 shelton add support f402/f405
* 2024-04-12 shelton add support a403a and a423
* 2024-08-30 shelton add support m412 and m416
+ * 2024-12-18 shelton add support f455/f456 and f457
*/
#include "drv_common.h"
@@ -338,7 +339,9 @@ static void at32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F402) || \
defined (SOC_SERIES_AT32F405) || defined (SOC_SERIES_AT32A423) || \
- defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416)
+ defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416) || \
+ defined (SOC_SERIES_AT32F455) || defined (SOC_SERIES_AT32F456) || \
+ defined (SOC_SERIES_AT32F457)
dmamux_enable(dma_config->dma_x, TRUE);
dmamux_init(dma_config->dmamux_channel, (dmamux_requst_id_sel_type)dma_config->request_id);
#endif
diff --git a/bsp/at32/libraries/rt_drivers/drv_usart_v2.c b/bsp/at32/libraries/rt_drivers/drv_usart_v2.c
index 02f6e7277d0..e7a33d59d34 100644
--- a/bsp/at32/libraries/rt_drivers/drv_usart_v2.c
+++ b/bsp/at32/libraries/rt_drivers/drv_usart_v2.c
@@ -10,6 +10,7 @@
* 2023-11-16 shelton add support at32f402/405 series
* 2024-04-12 shelton add support a403a and a423
* 2024-08-30 shelton add support m412 and m416
+ * 2024-12-18 shelton add support f455/f456 and f457
*/
#include "drv_common.h"
@@ -370,7 +371,9 @@ static void at32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
#if defined (SOC_SERIES_AT32F435) || defined (SOC_SERIES_AT32F437) || \
defined (SOC_SERIES_AT32F423) || defined (SOC_SERIES_AT32F402) || \
defined (SOC_SERIES_AT32F405) || defined (SOC_SERIES_AT32A423) || \
- defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416)
+ defined (SOC_SERIES_AT32M412) || defined (SOC_SERIES_AT32M416) || \
+ defined (SOC_SERIES_AT32F455) || defined (SOC_SERIES_AT32F456) || \
+ defined (SOC_SERIES_AT32F457)
dmamux_enable(dma_config->dma_x, TRUE);
dmamux_init(dma_config->dmamux_channel, (dmamux_requst_id_sel_type)dma_config->request_id);
#endif
diff --git a/bsp/at32/libraries/rt_drivers/drv_usbotgh.c b/bsp/at32/libraries/rt_drivers/drv_usbotgh.c
index 3eb13295d0a..53cdc379d5d 100644
--- a/bsp/at32/libraries/rt_drivers/drv_usbotgh.c
+++ b/bsp/at32/libraries/rt_drivers/drv_usbotgh.c
@@ -7,6 +7,7 @@
* Date Author Notes
* 2023-02-28 leo first version
* 2024-02-26 shelton update drv_pipe_xfer
+ * 2024-12-18 shelton update drv_pipe_xfer
*/
#include
@@ -108,128 +109,152 @@ static rt_err_t drv_reset_port(rt_uint8_t port)
static int drv_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes, int timeouts)
{
int timeout = timeouts;
- volatile int retry = 0;
+ static uint8_t data_pid = 0;
+ uint32_t direction = (pipe->ep.bEndpointAddress & 0x80) >> 7;
- if(!connect_status)
+ while(1)
{
- return -1;
- }
- rt_completion_init(&urb_completion);
+ if(!connect_status)
+ {
+ return -1;
+ }
- p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].dir = (pipe->ep.bEndpointAddress & 0x80) >> 7;
+ rt_completion_init(&urb_completion);
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].dir = direction;
- if(token == 0U)
- {
- p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_SETUP;
- }
- else
- {
- p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA1;
- }
+ if(token == 0U)
+ {
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_SETUP;
+ data_pid = 0;
+ }
- /* endpoint type */
- switch(pipe->ep.bmAttributes)
- {
- /* endpoint is control type */
- case EPT_CONTROL_TYPE:
- if((token == 1U) && (((pipe->ep.bEndpointAddress & 0x80) >> 7) == 0U))
- {
- if(nbytes == 0U)
- {
- p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].toggle_out = 1U;
- }
- if((&p_usbotg_instance->p_otg_core->host)->hch[pipe->pipe_index].toggle_out == 0U)
- {
- p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA0;
- }
- else
- {
- p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA1;
- }
- }
- break;
- /* endpoint is bulk type */
- case EPT_BULK_TYPE:
- if(((pipe->ep.bEndpointAddress & 0x80) >> 7) == 0U)
- {
- if( p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].toggle_out == 0U)
+ /* endpoint type */
+ switch(pipe->ep.bmAttributes)
+ {
+ /* endpoint is control type */
+ case EPT_CONTROL_TYPE:
+ if((token == 1U) && (direction == 0U))
{
- p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA0;
+ if(nbytes == 0U)
+ {
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].toggle_out = 1U;
+ }
+ if(p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].toggle_out == 0U)
+ {
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA0;
+ }
+ else
+ {
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA1;
+ }
}
- else
+ else if(token == 1U)
{
- p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA1;
+ if(data_pid == 0)
+ {
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA1;
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].toggle_in = 1;
+ data_pid = 1;
+ }
+ else
+ {
+ if(nbytes == 0U)
+ {
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].toggle_in = 1U;
+ }
+ if(p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].toggle_in == 0U)
+ {
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA0;
+ }
+ else
+ {
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA1;
+ }
+ }
}
- }
- else
- {
- if( p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].toggle_in == 0U)
+ break;
+ /* endpoint is bulk type */
+ case EPT_BULK_TYPE:
+ if(direction == 0U)
{
- p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA0;
+ if( p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].toggle_out == 0U)
+ {
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA0;
+ }
+ else
+ {
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA1;
+ }
}
else
{
- p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA1;
+ if( p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].toggle_in == 0U)
+ {
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA0;
+ }
+ else
+ {
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA1;
+ }
}
- }
- break;
- /* endpoint is int type */
- case EPT_INT_TYPE:
- if(((pipe->ep.bEndpointAddress & 0x80) >> 7) == 0U)
- {
- if( p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].toggle_out == 0U)
+ break;
+ /* endpoint is int type */
+ case EPT_INT_TYPE:
+ if(direction == 0U)
{
- p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA0;
+ if( p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].toggle_out == 0U)
+ {
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA0;
+ }
+ else
+ {
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA1;
+ }
}
else
{
- p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA1;
- }
- }
- else
- {
- if( p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].toggle_in == 0U)
- {
- p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA0;
+ if( p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].toggle_in == 0U)
+ {
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA0;
+ }
+ else
+ {
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA1;
+ }
}
- else
- {
- p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA1;
- }
- }
- break;
- /* endpoint is isoc type */
- case EPT_ISO_TYPE:
- p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA0;
- break;
-
- default:
- break;
- }
+ break;
+ /* endpoint is isoc type */
+ case EPT_ISO_TYPE:
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].data_pid = HCH_PID_DATA0;
+ break;
+
+ default:
+ break;
+ }
+
+ /* set transfer buffer */
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].trans_buf = buffer;
+ /* set transfer len*/
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].trans_len = nbytes;
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].urb_sts = URB_IDLE;
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].ch_num = pipe->pipe_index;
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].trans_count = 0;
+ p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].state = HCH_IDLE;
+
+ /* data in/out for host */
+ usbh_in_out_request((&p_usbotg_instance->p_otg_core->host), pipe->pipe_index);
- /* set transfer buffer */
- p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].trans_buf = buffer;
- /* set transfer len*/
- p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].trans_len = nbytes;
- p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].urb_sts = URB_IDLE;
- p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].ch_num = pipe->pipe_index;
- p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].trans_count = 0;
- p_usbotg_instance->p_otg_core->host.hch[pipe->pipe_index].state = HCH_IDLE;
-
-__resend:
- /* data in/out for host */
- usbh_in_out_request((&p_usbotg_instance->p_otg_core->host), pipe->pipe_index);
-
- retry = 0xFFFFFFFF;
- while(retry --)
- {
rt_completion_wait(&urb_completion, timeout);
+ rt_thread_mdelay(1);
+
if(usbh_get_urb_status((&p_usbotg_instance->p_otg_core->host), pipe->pipe_index) == URB_NOTREADY)
{
- if((pipe->ep.bEndpointAddress & 0x80) == 0)
+ LOG_D("nak");
+ if (pipe->ep.bmAttributes == USB_EP_ATTR_INT)
{
- goto __resend;
+ rt_thread_delay((pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) > 0 ? (pipe->ep.bInterval * RT_TICK_PER_SECOND / 1000) : 1);
}
+ continue;
}
else if (usbh_get_urb_status(&p_usbotg_instance->p_otg_core->host, pipe->pipe_index) == URB_STALL)
{
@@ -270,8 +295,8 @@ static int drv_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbyte
}
return nbytes;
}
+ continue;
}
- return 0;
}
static rt_uint16_t pipe_index = 0;
diff --git a/bsp/at32/libraries/usbotg_library/src/usbh_int.c b/bsp/at32/libraries/usbotg_library/src/usbh_int.c
index 5803319bb99..4f76ac4da6f 100644
--- a/bsp/at32/libraries/usbotg_library/src/usbh_int.c
+++ b/bsp/at32/libraries/usbotg_library/src/usbh_int.c
@@ -252,8 +252,11 @@ void usbh_hch_in_handler(usbh_core_type *uhost, uint8_t chn)
}
else if(uhost->hch[chn].state == HCH_NAK)
{
- usb_chh->hcchar_bit.chdis = FALSE;
- usb_chh->hcchar_bit.chena = TRUE;
+ if(usb_chh->hcchar_bit.eptype != EPT_INT_TYPE)
+ {
+ usb_chh->hcchar_bit.chdis = FALSE;
+ usb_chh->hcchar_bit.chena = TRUE;
+ }
uhost->urb_state[chn] = URB_NOTREADY;
}
usb_chh->hcint = USB_OTG_HC_CHHLTD_FLAG;