diff --git a/hw/amdc_revf.bd b/hw/amdc_revf.bd index 35a06aeb..7aba83b4 100644 --- a/hw/amdc_revf.bd +++ b/hw/amdc_revf.bd @@ -2963,17 +2963,17 @@ } }, "interface_nets": { - "i04_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - }, "auto_pc_to_i04_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] + }, + "i04_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] } }, "nets": { @@ -3055,12 +3055,6 @@ } }, "interface_nets": { - "s00_data_fifo_to_s00_couplers": { - "interface_ports": [ - "M_AXI", - "s00_data_fifo/M_AXI" - ] - }, "auto_pc_to_s00_data_fifo": { "interface_ports": [ "s00_data_fifo/S_AXI", @@ -3072,6 +3066,12 @@ "S_AXI", "auto_pc/S_AXI" ] + }, + "s00_data_fifo_to_s00_couplers": { + "interface_ports": [ + "M_AXI", + "s00_data_fifo/M_AXI" + ] } }, "nets": { @@ -3797,17 +3797,17 @@ } }, "interface_nets": { - "auto_pc_to_m08_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m08_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m08_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -4609,17 +4609,17 @@ } }, "interface_nets": { - "auto_pc_to_m18_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m18_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m18_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -4697,17 +4697,17 @@ } }, "interface_nets": { - "auto_pc_to_m19_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m19_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m19_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -4839,17 +4839,17 @@ } }, "interface_nets": { - "m21_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - }, "auto_pc_to_m21_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] + }, + "m21_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] } }, "nets": { @@ -5103,17 +5103,17 @@ } }, "interface_nets": { - "auto_pc_to_m24_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m24_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m24_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -5421,17 +5421,17 @@ } }, "interface_nets": { - "m28_couplers_to_auto_pc": { - "interface_ports": [ - "S_AXI", - "auto_pc/S_AXI" - ] - }, "auto_pc_to_m28_couplers": { "interface_ports": [ "M_AXI", "auto_pc/M_AXI" ] + }, + "m28_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] } }, "nets": { @@ -5509,17 +5509,17 @@ } }, "interface_nets": { - "auto_pc_to_m29_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m29_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m29_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -5597,17 +5597,17 @@ } }, "interface_nets": { - "auto_pc_to_m30_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m30_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m30_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -5685,17 +5685,17 @@ } }, "interface_nets": { - "auto_pc_to_m31_couplers": { - "interface_ports": [ - "M_AXI", - "auto_pc/M_AXI" - ] - }, "m31_couplers_to_auto_pc": { "interface_ports": [ "S_AXI", "auto_pc/S_AXI" ] + }, + "auto_pc_to_m31_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] } }, "nets": { @@ -6039,22 +6039,82 @@ } }, "interface_nets": { - "m00_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_0_to_m06_couplers": { "interface_ports": [ - "M00_AXI", - "m00_couplers/M_AXI" + "tier2_xbar_0/M06_AXI", + "m06_couplers/S_AXI" ] }, - "s00_couplers_to_xbar": { + "m07_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "s00_couplers/M_AXI", - "xbar/S00_AXI" + "M07_AXI", + "m07_couplers/M_AXI" ] }, - "ps7_0_axi_periph_to_s00_couplers": { + "tier2_xbar_0_to_m07_couplers": { "interface_ports": [ - "S00_AXI", - "s00_couplers/S_AXI" + "tier2_xbar_0/M07_AXI", + "m07_couplers/S_AXI" + ] + }, + "m08_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M08_AXI", + "m08_couplers/M_AXI" + ] + }, + "tier2_xbar_1_to_m08_couplers": { + "interface_ports": [ + "tier2_xbar_1/M00_AXI", + "m08_couplers/S_AXI" + ] + }, + "tier2_xbar_1_to_m11_couplers": { + "interface_ports": [ + "tier2_xbar_1/M03_AXI", + "m11_couplers/S_AXI" + ] + }, + "m12_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M12_AXI", + "m12_couplers/M_AXI" + ] + }, + "m09_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M09_AXI", + "m09_couplers/M_AXI" + ] + }, + "i04_couplers_to_tier2_xbar_4": { + "interface_ports": [ + "i04_couplers/M_AXI", + "tier2_xbar_4/S00_AXI" + ] + }, + "m10_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M10_AXI", + "m10_couplers/M_AXI" + ] + }, + "tier2_xbar_1_to_m09_couplers": { + "interface_ports": [ + "tier2_xbar_1/M01_AXI", + "m09_couplers/S_AXI" + ] + }, + "tier2_xbar_1_to_m10_couplers": { + "interface_ports": [ + "tier2_xbar_1/M02_AXI", + "m10_couplers/S_AXI" + ] + }, + "m11_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M11_AXI", + "m11_couplers/M_AXI" ] }, "tier2_xbar_0_to_m00_couplers": { @@ -6069,18 +6129,18 @@ "m01_couplers/M_AXI" ] }, - "m02_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M02_AXI", - "m02_couplers/M_AXI" - ] - }, "tier2_xbar_0_to_m01_couplers": { "interface_ports": [ "tier2_xbar_0/M01_AXI", "m01_couplers/S_AXI" ] }, + "m02_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M02_AXI", + "m02_couplers/M_AXI" + ] + }, "tier2_xbar_0_to_m02_couplers": { "interface_ports": [ "tier2_xbar_0/M02_AXI", @@ -6129,82 +6189,160 @@ "m05_couplers/S_AXI" ] }, - "m07_couplers_to_ps7_0_axi_periph": { + "s00_couplers_to_xbar": { "interface_ports": [ - "M07_AXI", - "m07_couplers/M_AXI" + "s00_couplers/M_AXI", + "xbar/S00_AXI" ] }, - "tier2_xbar_0_to_m06_couplers": { + "ps7_0_axi_periph_to_s00_couplers": { "interface_ports": [ - "tier2_xbar_0/M06_AXI", - "m06_couplers/S_AXI" + "S00_AXI", + "s00_couplers/S_AXI" ] }, - "tier2_xbar_0_to_m07_couplers": { + "m00_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_0/M07_AXI", - "m07_couplers/S_AXI" + "M00_AXI", + "m00_couplers/M_AXI" ] }, - "m08_couplers_to_ps7_0_axi_periph": { + "xbar_to_i00_couplers": { "interface_ports": [ - "M08_AXI", - "m08_couplers/M_AXI" + "xbar/M00_AXI", + "i00_couplers/S_AXI" ] }, - "m09_couplers_to_ps7_0_axi_periph": { + "i00_couplers_to_tier2_xbar_0": { "interface_ports": [ - "M09_AXI", - "m09_couplers/M_AXI" + "i00_couplers/M_AXI", + "tier2_xbar_0/S00_AXI" ] }, - "tier2_xbar_1_to_m08_couplers": { + "xbar_to_i01_couplers": { "interface_ports": [ - "tier2_xbar_1/M00_AXI", - "m08_couplers/S_AXI" + "xbar/M01_AXI", + "i01_couplers/S_AXI" ] }, - "tier2_xbar_1_to_m09_couplers": { + "i01_couplers_to_tier2_xbar_1": { "interface_ports": [ - "tier2_xbar_1/M01_AXI", - "m09_couplers/S_AXI" + "i01_couplers/M_AXI", + "tier2_xbar_1/S00_AXI" ] }, - "m10_couplers_to_ps7_0_axi_periph": { + "xbar_to_i02_couplers": { "interface_ports": [ - "M10_AXI", - "m10_couplers/M_AXI" + "xbar/M02_AXI", + "i02_couplers/S_AXI" ] }, - "tier2_xbar_1_to_m10_couplers": { + "i02_couplers_to_tier2_xbar_2": { "interface_ports": [ - "tier2_xbar_1/M02_AXI", - "m10_couplers/S_AXI" + "i02_couplers/M_AXI", + "tier2_xbar_2/S00_AXI" ] }, - "m11_couplers_to_ps7_0_axi_periph": { + "xbar_to_i03_couplers": { "interface_ports": [ - "M11_AXI", - "m11_couplers/M_AXI" + "xbar/M03_AXI", + "i03_couplers/S_AXI" ] }, - "tier2_xbar_1_to_m11_couplers": { + "xbar_to_i04_couplers": { "interface_ports": [ - "tier2_xbar_1/M03_AXI", - "m11_couplers/S_AXI" + "xbar/M04_AXI", + "i04_couplers/S_AXI" ] }, - "m12_couplers_to_ps7_0_axi_periph": { + "i03_couplers_to_tier2_xbar_3": { "interface_ports": [ - "M12_AXI", - "m12_couplers/M_AXI" + "i03_couplers/M_AXI", + "tier2_xbar_3/S00_AXI" ] }, - "tier2_xbar_3_to_m24_couplers": { + "tier2_xbar_3_to_m31_couplers": { "interface_ports": [ - "tier2_xbar_3/M00_AXI", - "m24_couplers/S_AXI" + "tier2_xbar_3/M07_AXI", + "m31_couplers/S_AXI" + ] + }, + "m32_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M32_AXI", + "m32_couplers/M_AXI" + ] + }, + "tier2_xbar_4_to_m32_couplers": { + "interface_ports": [ + "tier2_xbar_4/M00_AXI", + "m32_couplers/S_AXI" + ] + }, + "m33_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M33_AXI", + "m33_couplers/M_AXI" + ] + }, + "tier2_xbar_4_to_m33_couplers": { + "interface_ports": [ + "tier2_xbar_4/M01_AXI", + "m33_couplers/S_AXI" + ] + }, + "m34_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M34_AXI", + "m34_couplers/M_AXI" + ] + }, + "m35_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M35_AXI", + "m35_couplers/M_AXI" + ] + }, + "tier2_xbar_4_to_m34_couplers": { + "interface_ports": [ + "tier2_xbar_4/M02_AXI", + "m34_couplers/S_AXI" + ] + }, + "m36_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M36_AXI", + "m36_couplers/M_AXI" + ] + }, + "tier2_xbar_4_to_m35_couplers": { + "interface_ports": [ + "tier2_xbar_4/M03_AXI", + "m35_couplers/S_AXI" + ] + }, + "m37_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M37_AXI", + "m37_couplers/M_AXI" + ] + }, + "tier2_xbar_4_to_m36_couplers": { + "interface_ports": [ + "tier2_xbar_4/M04_AXI", + "m36_couplers/S_AXI" + ] + }, + "tier2_xbar_4_to_m37_couplers": { + "interface_ports": [ + "tier2_xbar_4/M05_AXI", + "m37_couplers/S_AXI" + ] + }, + "m21_couplers_to_ps7_0_axi_periph": { + "interface_ports": [ + "M21_AXI", + "m21_couplers/M_AXI" ] }, "tier2_xbar_1_to_m12_couplers": { @@ -6219,18 +6357,18 @@ "m13_couplers/M_AXI" ] }, - "tier2_xbar_1_to_m13_couplers": { - "interface_ports": [ - "tier2_xbar_1/M05_AXI", - "m13_couplers/S_AXI" - ] - }, "m14_couplers_to_ps7_0_axi_periph": { "interface_ports": [ "M14_AXI", "m14_couplers/M_AXI" ] }, + "tier2_xbar_1_to_m13_couplers": { + "interface_ports": [ + "tier2_xbar_1/M05_AXI", + "m13_couplers/S_AXI" + ] + }, "tier2_xbar_1_to_m14_couplers": { "interface_ports": [ "tier2_xbar_1/M06_AXI", @@ -6243,22 +6381,16 @@ "m15_couplers/M_AXI" ] }, - "tier2_xbar_1_to_m15_couplers": { - "interface_ports": [ - "tier2_xbar_1/M07_AXI", - "m15_couplers/S_AXI" - ] - }, "m16_couplers_to_ps7_0_axi_periph": { "interface_ports": [ "M16_AXI", "m16_couplers/M_AXI" ] }, - "tier2_xbar_2_to_m16_couplers": { + "tier2_xbar_1_to_m15_couplers": { "interface_ports": [ - "tier2_xbar_2/M00_AXI", - "m16_couplers/S_AXI" + "tier2_xbar_1/M07_AXI", + "m15_couplers/S_AXI" ] }, "m17_couplers_to_ps7_0_axi_periph": { @@ -6267,10 +6399,10 @@ "m17_couplers/M_AXI" ] }, - "tier2_xbar_2_to_m17_couplers": { + "tier2_xbar_2_to_m16_couplers": { "interface_ports": [ - "tier2_xbar_2/M01_AXI", - "m17_couplers/S_AXI" + "tier2_xbar_2/M00_AXI", + "m16_couplers/S_AXI" ] }, "m18_couplers_to_ps7_0_axi_periph": { @@ -6279,10 +6411,10 @@ "m18_couplers/M_AXI" ] }, - "m19_couplers_to_ps7_0_axi_periph": { + "tier2_xbar_2_to_m17_couplers": { "interface_ports": [ - "M19_AXI", - "m19_couplers/M_AXI" + "tier2_xbar_2/M01_AXI", + "m17_couplers/S_AXI" ] }, "tier2_xbar_2_to_m18_couplers": { @@ -6291,10 +6423,10 @@ "m18_couplers/S_AXI" ] }, - "tier2_xbar_2_to_m19_couplers": { + "m19_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "tier2_xbar_2/M03_AXI", - "m19_couplers/S_AXI" + "M19_AXI", + "m19_couplers/M_AXI" ] }, "m20_couplers_to_ps7_0_axi_periph": { @@ -6303,22 +6435,28 @@ "m20_couplers/M_AXI" ] }, + "tier2_xbar_2_to_m19_couplers": { + "interface_ports": [ + "tier2_xbar_2/M03_AXI", + "m19_couplers/S_AXI" + ] + }, "tier2_xbar_2_to_m20_couplers": { "interface_ports": [ "tier2_xbar_2/M04_AXI", "m20_couplers/S_AXI" ] }, - "m21_couplers_to_ps7_0_axi_periph": { + "m31_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M21_AXI", - "m21_couplers/M_AXI" + "M31_AXI", + "m31_couplers/M_AXI" ] }, - "tier2_xbar_2_to_m21_couplers": { + "tier2_xbar_3_to_m30_couplers": { "interface_ports": [ - "tier2_xbar_2/M05_AXI", - "m21_couplers/S_AXI" + "tier2_xbar_3/M06_AXI", + "m30_couplers/S_AXI" ] }, "m22_couplers_to_ps7_0_axi_periph": { @@ -6327,6 +6465,12 @@ "m22_couplers/M_AXI" ] }, + "tier2_xbar_2_to_m21_couplers": { + "interface_ports": [ + "tier2_xbar_2/M05_AXI", + "m21_couplers/S_AXI" + ] + }, "tier2_xbar_2_to_m22_couplers": { "interface_ports": [ "tier2_xbar_2/M06_AXI", @@ -6351,78 +6495,18 @@ "m24_couplers/M_AXI" ] }, - "tier2_xbar_4_to_m37_couplers": { - "interface_ports": [ - "tier2_xbar_4/M05_AXI", - "m37_couplers/S_AXI" - ] - }, - "xbar_to_i00_couplers": { - "interface_ports": [ - "xbar/M00_AXI", - "i00_couplers/S_AXI" - ] - }, - "i00_couplers_to_tier2_xbar_0": { - "interface_ports": [ - "i00_couplers/M_AXI", - "tier2_xbar_0/S00_AXI" - ] - }, - "xbar_to_i01_couplers": { - "interface_ports": [ - "xbar/M01_AXI", - "i01_couplers/S_AXI" - ] - }, - "xbar_to_i02_couplers": { - "interface_ports": [ - "xbar/M02_AXI", - "i02_couplers/S_AXI" - ] - }, - "i01_couplers_to_tier2_xbar_1": { - "interface_ports": [ - "i01_couplers/M_AXI", - "tier2_xbar_1/S00_AXI" - ] - }, - "i02_couplers_to_tier2_xbar_2": { - "interface_ports": [ - "i02_couplers/M_AXI", - "tier2_xbar_2/S00_AXI" - ] - }, - "xbar_to_i03_couplers": { - "interface_ports": [ - "xbar/M03_AXI", - "i03_couplers/S_AXI" - ] - }, - "i03_couplers_to_tier2_xbar_3": { - "interface_ports": [ - "i03_couplers/M_AXI", - "tier2_xbar_3/S00_AXI" - ] - }, - "xbar_to_i04_couplers": { - "interface_ports": [ - "xbar/M04_AXI", - "i04_couplers/S_AXI" - ] - }, - "i04_couplers_to_tier2_xbar_4": { - "interface_ports": [ - "i04_couplers/M_AXI", - "tier2_xbar_4/S00_AXI" - ] - }, "m25_couplers_to_ps7_0_axi_periph": { "interface_ports": [ "M25_AXI", "m25_couplers/M_AXI" ] }, + "tier2_xbar_3_to_m24_couplers": { + "interface_ports": [ + "tier2_xbar_3/M00_AXI", + "m24_couplers/S_AXI" + ] + }, "tier2_xbar_3_to_m25_couplers": { "interface_ports": [ "tier2_xbar_3/M01_AXI", @@ -6479,92 +6563,8 @@ }, "m30_couplers_to_ps7_0_axi_periph": { "interface_ports": [ - "M30_AXI", - "m30_couplers/M_AXI" - ] - }, - "m31_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M31_AXI", - "m31_couplers/M_AXI" - ] - }, - "tier2_xbar_3_to_m30_couplers": { - "interface_ports": [ - "tier2_xbar_3/M06_AXI", - "m30_couplers/S_AXI" - ] - }, - "tier2_xbar_3_to_m31_couplers": { - "interface_ports": [ - "tier2_xbar_3/M07_AXI", - "m31_couplers/S_AXI" - ] - }, - "m32_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M32_AXI", - "m32_couplers/M_AXI" - ] - }, - "tier2_xbar_4_to_m32_couplers": { - "interface_ports": [ - "tier2_xbar_4/M00_AXI", - "m32_couplers/S_AXI" - ] - }, - "m33_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M33_AXI", - "m33_couplers/M_AXI" - ] - }, - "tier2_xbar_4_to_m33_couplers": { - "interface_ports": [ - "tier2_xbar_4/M01_AXI", - "m33_couplers/S_AXI" - ] - }, - "m34_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M34_AXI", - "m34_couplers/M_AXI" - ] - }, - "m35_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M35_AXI", - "m35_couplers/M_AXI" - ] - }, - "tier2_xbar_4_to_m34_couplers": { - "interface_ports": [ - "tier2_xbar_4/M02_AXI", - "m34_couplers/S_AXI" - ] - }, - "tier2_xbar_4_to_m35_couplers": { - "interface_ports": [ - "tier2_xbar_4/M03_AXI", - "m35_couplers/S_AXI" - ] - }, - "m36_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M36_AXI", - "m36_couplers/M_AXI" - ] - }, - "m37_couplers_to_ps7_0_axi_periph": { - "interface_ports": [ - "M37_AXI", - "m37_couplers/M_AXI" - ] - }, - "tier2_xbar_4_to_m36_couplers": { - "interface_ports": [ - "tier2_xbar_4/M04_AXI", - "m36_couplers/S_AXI" + "M30_AXI", + "m30_couplers/M_AXI" ] } }, @@ -7161,10 +7161,40 @@ } }, "interface_nets": { - "Conn22": { + "Conn14": { "interface_ports": [ - "M22_AXI", - "ps7_0_axi_periph/M22_AXI" + "M14_AXI", + "ps7_0_axi_periph/M14_AXI" + ] + }, + "Conn5": { + "interface_ports": [ + "M04_AXI", + "ps7_0_axi_periph/M04_AXI" + ] + }, + "ps7_0_axi_periph_M35_AXI": { + "interface_ports": [ + "M35_AXI", + "ps7_0_axi_periph/M35_AXI" + ] + }, + "Conn25": { + "interface_ports": [ + "M25_AXI", + "ps7_0_axi_periph/M25_AXI" + ] + }, + "Conn8": { + "interface_ports": [ + "M07_AXI", + "ps7_0_axi_periph/M07_AXI" + ] + }, + "Conn15": { + "interface_ports": [ + "M15_AXI", + "ps7_0_axi_periph/M15_AXI" ] }, "Conn28": { @@ -7173,10 +7203,16 @@ "ps7_0_axi_periph/M28_AXI" ] }, - "Conn23": { + "ps7_0_axi_periph_M34_AXI": { "interface_ports": [ - "M23_AXI", - "ps7_0_axi_periph/M23_AXI" + "M34_AXI", + "ps7_0_axi_periph/M34_AXI" + ] + }, + "Conn22": { + "interface_ports": [ + "M22_AXI", + "ps7_0_axi_periph/M22_AXI" ] }, "processing_system7_0_M_AXI_GP0": { @@ -7185,6 +7221,18 @@ "ps7_0_axi_periph/S00_AXI" ] }, + "Conn23": { + "interface_ports": [ + "M23_AXI", + "ps7_0_axi_periph/M23_AXI" + ] + }, + "Conn13": { + "interface_ports": [ + "M12_AXI", + "ps7_0_axi_periph/M12_AXI" + ] + }, "Conn6": { "interface_ports": [ "M05_AXI", @@ -7203,16 +7251,22 @@ "ps7_0_axi_periph/M19_AXI" ] }, + "Conn27": { + "interface_ports": [ + "M27_AXI", + "ps7_0_axi_periph/M27_AXI" + ] + }, "Conn9": { "interface_ports": [ "M08_AXI", "ps7_0_axi_periph/M08_AXI" ] }, - "Conn13": { + "ps7_0_axi_periph_M31_AXI": { "interface_ports": [ - "M12_AXI", - "ps7_0_axi_periph/M12_AXI" + "M31_AXI", + "ps7_0_axi_periph/M31_AXI" ] }, "Conn16": { @@ -7221,28 +7275,40 @@ "ps7_0_axi_periph/M16_AXI" ] }, - "Conn27": { + "Conn26": { "interface_ports": [ - "M27_AXI", - "ps7_0_axi_periph/M27_AXI" + "M26_AXI", + "ps7_0_axi_periph/M26_AXI" ] }, - "Conn15": { + "Conn4": { "interface_ports": [ - "M15_AXI", - "ps7_0_axi_periph/M15_AXI" + "M03_AXI", + "ps7_0_axi_periph/M03_AXI" ] }, - "Conn12": { + "Conn20": { "interface_ports": [ - "M11_AXI", - "ps7_0_axi_periph/M11_AXI" + "M20_AXI", + "ps7_0_axi_periph/M20_AXI" ] }, - "ps7_0_axi_periph_M36_AXI": { + "ps7_0_axi_periph_M13_AXI": { "interface_ports": [ - "M36_AXI", - "ps7_0_axi_periph/M36_AXI" + "M13_AXI", + "ps7_0_axi_periph/M13_AXI" + ] + }, + "Conn11": { + "interface_ports": [ + "M10_AXI", + "ps7_0_axi_periph/M10_AXI" + ] + }, + "Conn12": { + "interface_ports": [ + "M11_AXI", + "ps7_0_axi_periph/M11_AXI" ] }, "ps7_0_axi_periph_M37_AXI": { @@ -7251,10 +7317,10 @@ "ps7_0_axi_periph/M37_AXI" ] }, - "Conn17": { + "ps7_0_axi_periph_M36_AXI": { "interface_ports": [ - "M17_AXI", - "ps7_0_axi_periph/M17_AXI" + "M36_AXI", + "ps7_0_axi_periph/M36_AXI" ] }, "Conn1": { @@ -7263,10 +7329,10 @@ "ps7_0_axi_periph/M00_AXI" ] }, - "processing_system7_0_DDR": { + "Conn17": { "interface_ports": [ - "DDR", - "processing_system7_0/DDR" + "M17_AXI", + "ps7_0_axi_periph/M17_AXI" ] }, "Conn18": { @@ -7275,28 +7341,22 @@ "ps7_0_axi_periph/M18_AXI" ] }, - "ps7_0_axi_periph_M32_AXI": { - "interface_ports": [ - "M32_AXI", - "ps7_0_axi_periph/M32_AXI" - ] - }, "Conn10": { "interface_ports": [ "M09_AXI", "ps7_0_axi_periph/M09_AXI" ] }, - "ps7_0_axi_periph_M30_AXI": { + "processing_system7_0_DDR": { "interface_ports": [ - "M30_AXI", - "ps7_0_axi_periph/M30_AXI" + "DDR", + "processing_system7_0/DDR" ] }, - "Conn21": { + "ps7_0_axi_periph_M32_AXI": { "interface_ports": [ - "M21_AXI", - "ps7_0_axi_periph/M21_AXI" + "M32_AXI", + "ps7_0_axi_periph/M32_AXI" ] }, "Conn2": { @@ -7305,10 +7365,10 @@ "ps7_0_axi_periph/M01_AXI" ] }, - "processing_system7_0_FIXED_IO": { + "ps7_0_axi_periph_M30_AXI": { "interface_ports": [ - "FIXED_IO", - "processing_system7_0/FIXED_IO" + "M30_AXI", + "ps7_0_axi_periph/M30_AXI" ] }, "Conn3": { @@ -7317,40 +7377,10 @@ "ps7_0_axi_periph/M02_AXI" ] }, - "Conn8": { - "interface_ports": [ - "M07_AXI", - "ps7_0_axi_periph/M07_AXI" - ] - }, - "Conn14": { - "interface_ports": [ - "M14_AXI", - "ps7_0_axi_periph/M14_AXI" - ] - }, - "Conn11": { - "interface_ports": [ - "M10_AXI", - "ps7_0_axi_periph/M10_AXI" - ] - }, - "Conn25": { - "interface_ports": [ - "M25_AXI", - "ps7_0_axi_periph/M25_AXI" - ] - }, - "ps7_0_axi_periph_M13_AXI": { - "interface_ports": [ - "M13_AXI", - "ps7_0_axi_periph/M13_AXI" - ] - }, - "Conn20": { + "Conn21": { "interface_ports": [ - "M20_AXI", - "ps7_0_axi_periph/M20_AXI" + "M21_AXI", + "ps7_0_axi_periph/M21_AXI" ] }, "Conn24": { @@ -7359,28 +7389,16 @@ "ps7_0_axi_periph/M24_AXI" ] }, - "Conn7": { - "interface_ports": [ - "M06_AXI", - "ps7_0_axi_periph/M06_AXI" - ] - }, - "Conn26": { - "interface_ports": [ - "M26_AXI", - "ps7_0_axi_periph/M26_AXI" - ] - }, - "Conn5": { + "processing_system7_0_FIXED_IO": { "interface_ports": [ - "M04_AXI", - "ps7_0_axi_periph/M04_AXI" + "FIXED_IO", + "processing_system7_0/FIXED_IO" ] }, - "Conn4": { + "Conn7": { "interface_ports": [ - "M03_AXI", - "ps7_0_axi_periph/M03_AXI" + "M06_AXI", + "ps7_0_axi_periph/M06_AXI" ] }, "ps7_0_axi_periph_M29_AXI": { @@ -7388,24 +7406,6 @@ "M29_AXI", "ps7_0_axi_periph/M29_AXI" ] - }, - "ps7_0_axi_periph_M31_AXI": { - "interface_ports": [ - "M31_AXI", - "ps7_0_axi_periph/M31_AXI" - ] - }, - "ps7_0_axi_periph_M35_AXI": { - "interface_ports": [ - "M35_AXI", - "ps7_0_axi_periph/M35_AXI" - ] - }, - "ps7_0_axi_periph_M34_AXI": { - "interface_ports": [ - "M34_AXI", - "ps7_0_axi_periph/M34_AXI" - ] } }, "nets": { @@ -7648,10 +7648,10 @@ } }, "interface_nets": { - "Conn1": { + "ps7_0_axi_periph_M06_AXI": { "interface_ports": [ - "S00_AXI2", - "amdc_inv_status_mux_0/S00_AXI" + "S00_AXI1", + "amdc_pwm_mux_0/S00_AXI" ] }, "ps7_0_axi_periph_M02_AXI": { @@ -7660,10 +7660,10 @@ "amdc_inverters_0/S00_AXI" ] }, - "ps7_0_axi_periph_M06_AXI": { + "Conn1": { "interface_ports": [ - "S00_AXI1", - "amdc_pwm_mux_0/S00_AXI" + "S00_AXI2", + "amdc_inv_status_mux_0/S00_AXI" ] } }, @@ -8182,17 +8182,11 @@ "xci_name": "amdc_revf_amdc_eddy_current_se_0_0" }, "amdc_amds_0": { - "vlnv": "xilinx.com:user:amdc_amds:1.0", + "vlnv": "xilinx.com:user:amdc_amds:2.0", "xci_name": "amdc_revf_amdc_amds_0_0" } }, "interface_nets": { - "S00_AXI6_1": { - "interface_ports": [ - "S00_AXI6", - "amdc_amds_0/S00_AXI" - ] - }, "hier_ps_M48_AXI": { "interface_ports": [ "S00_AXI", @@ -8205,6 +8199,12 @@ "hier_ild1420_0/S00_AXI1" ] }, + "S00_AXI6_1": { + "interface_ports": [ + "S00_AXI6", + "amdc_amds_0/S00_AXI" + ] + }, "S00_AXI1_1": { "interface_ports": [ "S00_AXI1", @@ -8526,16 +8526,16 @@ } }, "interface_nets": { - "hier_ps_M13_AXI": { + "hier_ps_M12_AXI": { "interface_ports": [ - "S00_AXI1", - "amdc_ild1420_1/S00_AXI" + "S00_AXI", + "amdc_ild1420_0/S00_AXI" ] }, - "hier_ps_M12_AXI": { + "hier_ps_M13_AXI": { "interface_ports": [ - "S00_AXI", - "amdc_ild1420_0/S00_AXI" + "S00_AXI1", + "amdc_ild1420_1/S00_AXI" ] } }, @@ -8705,27 +8705,27 @@ "xci_name": "amdc_revf_amdc_eddy_current_se_0_1" }, "amdc_amds_0": { - "vlnv": "xilinx.com:user:amdc_amds:1.0", + "vlnv": "xilinx.com:user:amdc_amds:2.0", "xci_name": "amdc_revf_amdc_amds_0_1" } }, "interface_nets": { - "S00_AXI5_1": { + "S00_AXI3_1": { "interface_ports": [ - "S00_AXI5", - "amdc_gpio_direct_0/S00_AXI" + "S00_AXI3", + "hier_ild1420_0/S00_AXI" ] }, - "hier_ps_M48_AXI": { + "S00_AXI4_1": { "interface_ports": [ - "S00_AXI", - "amdc_gp3io_mux_0/S00_AXI" + "S00_AXI4", + "hier_ild1420_0/S00_AXI1" ] }, - "S00_AXI6_1": { + "S00_AXI5_1": { "interface_ports": [ - "S00_AXI6", - "amdc_amds_0/S00_AXI" + "S00_AXI5", + "amdc_gpio_direct_0/S00_AXI" ] }, "S00_AXI1_1": { @@ -8734,16 +8734,16 @@ "amdc_eddy_current_se_0/S00_AXI" ] }, - "S00_AXI3_1": { + "S00_AXI6_1": { "interface_ports": [ - "S00_AXI3", - "hier_ild1420_0/S00_AXI" + "S00_AXI6", + "amdc_amds_0/S00_AXI" ] }, - "S00_AXI4_1": { + "hier_ps_M48_AXI": { "interface_ports": [ - "S00_AXI4", - "hier_ild1420_0/S00_AXI1" + "S00_AXI", + "amdc_gp3io_mux_0/S00_AXI" ] } }, @@ -9228,23 +9228,23 @@ "xci_name": "amdc_revf_amdc_eddy_current_se_0_2" }, "amdc_amds_0": { - "vlnv": "xilinx.com:user:amdc_amds:1.0", + "vlnv": "xilinx.com:user:amdc_amds:2.0", "xci_name": "amdc_revf_amdc_amds_0_2" } }, "interface_nets": { - "S00_AXI1_1": { - "interface_ports": [ - "S00_AXI1", - "amdc_eddy_current_se_0/S00_AXI" - ] - }, "S00_AXI5_1": { "interface_ports": [ "S00_AXI5", "amdc_gpio_direct_0/S00_AXI" ] }, + "S00_AXI1_1": { + "interface_ports": [ + "S00_AXI1", + "amdc_eddy_current_se_0/S00_AXI" + ] + }, "S00_AXI3_1": { "interface_ports": [ "S00_AXI3", @@ -9751,11 +9751,17 @@ "xci_name": "amdc_revf_amdc_eddy_current_se_0_3" }, "amdc_amds_0": { - "vlnv": "xilinx.com:user:amdc_amds:1.0", + "vlnv": "xilinx.com:user:amdc_amds:2.0", "xci_name": "amdc_revf_amdc_amds_0_3" } }, "interface_nets": { + "hier_ps_M48_AXI": { + "interface_ports": [ + "S00_AXI", + "amdc_gp3io_mux_0/S00_AXI" + ] + }, "S00_AXI5_1": { "interface_ports": [ "S00_AXI5", @@ -9768,18 +9774,6 @@ "amdc_amds_0/S00_AXI" ] }, - "S00_AXI3_1": { - "interface_ports": [ - "S00_AXI3", - "hier_ild1420_0/S00_AXI" - ] - }, - "hier_ps_M48_AXI": { - "interface_ports": [ - "S00_AXI", - "amdc_gp3io_mux_0/S00_AXI" - ] - }, "S00_AXI4_1": { "interface_ports": [ "S00_AXI4", @@ -9791,6 +9785,12 @@ "S00_AXI1", "amdc_eddy_current_se_0/S00_AXI" ] + }, + "S00_AXI3_1": { + "interface_ports": [ + "S00_AXI3", + "hier_ild1420_0/S00_AXI" + ] } }, "nets": { @@ -10000,28 +10000,22 @@ "hier_gpio_2/S00_AXI5" ] }, - "S00_AXI1_5": { - "interface_ports": [ - "hier_gpio_3/S00_AXI1", - "hier_ps/M26_AXI" - ] - }, - "hier_ps_M37_AXI1": { + "processing_system7_0_DDR": { "interface_ports": [ - "hier_ps/M37_AXI", - "hier_gpio_3/S00_AXI6" + "DDR", + "hier_ps/DDR" ] }, - "S00_AXI3_3": { + "S00_AXI4_2": { "interface_ports": [ - "hier_gpio_2/S00_AXI3", - "hier_ps/M22_AXI" + "hier_gpio_1/S00_AXI4", + "hier_ps/M18_AXI" ] }, - "hier_ps_M37_AXI": { + "S00_AXI1_5": { "interface_ports": [ - "amdc_dac_0/S00_AXI", - "hier_ps/M05_AXI" + "hier_gpio_3/S00_AXI1", + "hier_ps/M26_AXI" ] }, "S00_AXI3_2": { @@ -10030,76 +10024,76 @@ "hier_ps/M17_AXI" ] }, - "hier_ps_M34_AXI": { + "S00_AXI2_1": { "interface_ports": [ - "amdc_encoder_0/S00_AXI", - "hier_ps/M02_AXI" + "hier_powerstack/S00_AXI2", + "hier_ps/M08_AXI" ] }, - "processing_system7_0_DDR": { + "S00_AXI1_4": { "interface_ports": [ - "DDR", - "hier_ps/DDR" + "hier_gpio_2/S00_AXI1", + "hier_ps/M21_AXI" ] }, - "hier_ps_M36_AXI1": { + "hier_ps_M34_AXI1": { "interface_ports": [ - "hier_ps/M36_AXI", - "hier_gpio_1/S00_AXI6" + "hier_ps/M34_AXI", + "hier_gpio_2/S00_AXI6" ] }, - "hier_ps_M30_AXI": { + "S00_AXI_3": { "interface_ports": [ - "hier_ps/M30_AXI", - "hier_gpio_1/S00_AXI5" + "hier_gpio_1/S00_AXI", + "hier_ps/M14_AXI" ] }, - "S00_AXI1_3": { + "S00_AXI_4": { "interface_ports": [ - "hier_gpio_1/S00_AXI1", - "hier_ps/M16_AXI" + "hier_gpio_2/S00_AXI", + "hier_ps/M19_AXI" ] }, - "S00_AXI1_1": { + "S00_AXI_1": { "interface_ports": [ - "hier_powerstack/S00_AXI1", - "hier_ps/M07_AXI" + "hier_powerstack/S00_AXI", + "hier_ps/M06_AXI" ] }, - "S00_AXI4_4": { + "S00_AXI_2": { "interface_ports": [ - "hier_gpio_3/S00_AXI4", - "hier_ps/M28_AXI" + "hier_gpio_0/S00_AXI", + "hier_ps/M09_AXI" ] }, - "S00_AXI1_4": { + "S00_AXI3_4": { "interface_ports": [ - "hier_gpio_2/S00_AXI1", - "hier_ps/M21_AXI" + "hier_gpio_3/S00_AXI3", + "hier_ps/M27_AXI" ] }, - "hier_ps_M35_AXI1": { + "S00_AXI4_4": { "interface_ports": [ - "hier_ps/M35_AXI", - "hier_gpio_0/S00_AXI6" + "hier_gpio_3/S00_AXI4", + "hier_ps/M28_AXI" ] }, - "S00_AXI4_2": { + "S00_AXI3_3": { "interface_ports": [ - "hier_gpio_1/S00_AXI4", - "hier_ps/M18_AXI" + "hier_gpio_2/S00_AXI3", + "hier_ps/M22_AXI" ] }, - "S00_AXI3_4": { + "hier_ps_M37_AXI1": { "interface_ports": [ - "hier_gpio_3/S00_AXI3", - "hier_ps/M27_AXI" + "hier_ps/M37_AXI", + "hier_gpio_3/S00_AXI6" ] }, - "S00_AXI3_1": { + "S00_AXI4_1": { "interface_ports": [ - "hier_gpio_0/S00_AXI3", - "hier_ps/M12_AXI" + "hier_gpio_0/S00_AXI4", + "hier_ps/M13_AXI" ] }, "hier_ps_M35_AXI": { @@ -10108,34 +10102,40 @@ "hier_ps/M03_AXI" ] }, - "hier_ps_M33_AXI1": { + "S00_AXI_5": { "interface_ports": [ - "amdc_timing_manager_0/S00_AXI", - "hier_ps/M33_AXI" + "hier_gpio_3/S00_AXI", + "hier_ps/M24_AXI" ] }, - "S00_AXI_1": { + "hier_ps_M37_AXI": { "interface_ports": [ - "hier_powerstack/S00_AXI", - "hier_ps/M06_AXI" + "amdc_dac_0/S00_AXI", + "hier_ps/M05_AXI" ] }, - "S00_AXI_5": { + "hier_ps_M32_AXI1": { "interface_ports": [ - "hier_gpio_3/S00_AXI", - "hier_ps/M24_AXI" + "hier_ps/M32_AXI", + "hier_gpio_3/S00_AXI5" ] }, - "hier_ps_M29_AXI": { + "processing_system7_0_FIXED_IO": { "interface_ports": [ - "hier_ps/M29_AXI", - "hier_gpio_0/S00_AXI5" + "FIXED_IO", + "hier_ps/FIXED_IO" ] }, - "S00_AXI_3": { + "hier_ps_M36_AXI1": { "interface_ports": [ - "hier_gpio_1/S00_AXI", - "hier_ps/M14_AXI" + "hier_ps/M36_AXI", + "hier_gpio_1/S00_AXI6" + ] + }, + "hier_ps_M34_AXI": { + "interface_ports": [ + "amdc_encoder_0/S00_AXI", + "hier_ps/M02_AXI" ] }, "S00_AXI1_2": { @@ -10144,58 +10144,58 @@ "hier_ps/M11_AXI" ] }, - "hier_ps_M34_AXI1": { + "hier_ps_M33_AXI1": { "interface_ports": [ - "hier_ps/M34_AXI", - "hier_gpio_2/S00_AXI6" + "amdc_timing_manager_0/S00_AXI", + "hier_ps/M33_AXI" ] }, - "S00_AXI_4": { + "S00_AXI4_3": { "interface_ports": [ - "hier_gpio_2/S00_AXI", - "hier_ps/M19_AXI" + "hier_gpio_2/S00_AXI4", + "hier_ps/M23_AXI" ] }, - "S00_AXI4_1": { + "hier_ps_M35_AXI1": { "interface_ports": [ - "hier_gpio_0/S00_AXI4", - "hier_ps/M13_AXI" + "hier_ps/M35_AXI", + "hier_gpio_0/S00_AXI6" ] }, - "hier_ps_M32_AXI1": { + "hier_ps_M30_AXI": { "interface_ports": [ - "hier_ps/M32_AXI", - "hier_gpio_3/S00_AXI5" + "hier_ps/M30_AXI", + "hier_gpio_1/S00_AXI5" ] }, - "hier_ps_M36_AXI": { + "S00_AXI1_1": { "interface_ports": [ - "amdc_adc_0/S00_AXI", - "hier_ps/M04_AXI" + "hier_powerstack/S00_AXI1", + "hier_ps/M07_AXI" ] }, - "S00_AXI4_3": { + "hier_ps_M36_AXI": { "interface_ports": [ - "hier_gpio_2/S00_AXI4", - "hier_ps/M23_AXI" + "amdc_adc_0/S00_AXI", + "hier_ps/M04_AXI" ] }, - "S00_AXI2_1": { + "S00_AXI3_1": { "interface_ports": [ - "hier_powerstack/S00_AXI2", - "hier_ps/M08_AXI" + "hier_gpio_0/S00_AXI3", + "hier_ps/M12_AXI" ] }, - "S00_AXI_2": { + "S00_AXI1_3": { "interface_ports": [ - "hier_gpio_0/S00_AXI", - "hier_ps/M09_AXI" + "hier_gpio_1/S00_AXI1", + "hier_ps/M16_AXI" ] }, - "processing_system7_0_FIXED_IO": { + "hier_ps_M29_AXI": { "interface_ports": [ - "FIXED_IO", - "hier_ps/FIXED_IO" + "hier_ps/M29_AXI", + "hier_gpio_0/S00_AXI5" ] } }, diff --git a/ip_repo/amdc_amds_1.0/component.xml b/ip_repo/amdc_amds_1.0/component.xml index 62c22bc2..0d98a995 100644 --- a/ip_repo/amdc_amds_1.0/component.xml +++ b/ip_repo/amdc_amds_1.0/component.xml @@ -3,7 +3,7 @@ xilinx.com user amdc_amds - 1.0 + 2.0 S00_AXI @@ -266,7 +266,7 @@ viewChecksum - 99650e73 + 6ff36aad @@ -282,7 +282,7 @@ viewChecksum - 99650e73 + 6ff36aad @@ -404,7 +404,7 @@ in - 5 + 6 0 @@ -567,7 +567,7 @@ in - 5 + 6 0 @@ -720,7 +720,7 @@ C_S00_AXI_ADDR_WIDTH C S00 AXI ADDR WIDTH Width of S_AXI address bus - 6 + 7 @@ -758,7 +758,7 @@ hdl/amdc_amds_v1_0.v verilogSource - CHECKSUM_1d57cb6b + CHECKSUM_b8610412 @@ -815,7 +815,7 @@ xilinx_xpgui_view_fileset - xgui/amdc_amds_v1_0.tcl + xgui/amdc_amds_v2_0.tcl tclSource CHECKSUM_dda4df14 XGUI_VERSION_2 @@ -848,7 +848,7 @@ C_S00_AXI_ADDR_WIDTH C S00 AXI ADDR WIDTH Width of S_AXI address bus - 6 + 7 @@ -894,9 +894,9 @@ AXI_Peripheral - amdc_amds_v1.0 - 15 - 2024-08-13T19:26:58Z + amdc_amds_v2.0 + 26 + 2026-03-19T15:24:18Z s:/School/WEMPEC/firmware-amds/ip_repo/amdc_amds_1.0 s:/School/WEMPEC/firmware-amds/ip_repo/amdc_amds_1.0 @@ -1042,16 +1042,142 @@ s:/School/WEMPEC/firmware-amds/ip_repo/amdc_amds_1.0 s:/School/WEMPEC/firmware-amds/ip_repo/amdc_amds_1.0 s:/School/WEMPEC/firmware-amds/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 + c:/Users/moha2063/Desktop/eLev/AMDC-Firmware/ip_repo/amdc_amds_1.0 2019.1 - - - - + + + + diff --git a/ip_repo/amdc_amds_1.0/hdl/amdc_amds_v1_0.v b/ip_repo/amdc_amds_1.0/hdl/amdc_amds_v1_0.v index 67173603..957984d1 100644 --- a/ip_repo/amdc_amds_1.0/hdl/amdc_amds_v1_0.v +++ b/ip_repo/amdc_amds_1.0/hdl/amdc_amds_v1_0.v @@ -11,7 +11,7 @@ // Parameters of Axi Slave Bus Interface S00_AXI parameter integer C_S00_AXI_DATA_WIDTH = 32, - parameter integer C_S00_AXI_ADDR_WIDTH = 6 + parameter integer C_S00_AXI_ADDR_WIDTH = 7 ) ( // Users to add ports here diff --git a/ip_repo/amdc_amds_1.0/hdl/amdc_amds_v1_0_S00_AXI.v b/ip_repo/amdc_amds_1.0/hdl/amdc_amds_v1_0_S00_AXI.v index dd755152..66f28281 100644 --- a/ip_repo/amdc_amds_1.0/hdl/amdc_amds_v1_0_S00_AXI.v +++ b/ip_repo/amdc_amds_1.0/hdl/amdc_amds_v1_0_S00_AXI.v @@ -11,7 +11,7 @@ // Width of S_AXI data bus parameter integer C_S_AXI_DATA_WIDTH = 32, // Width of S_AXI address bus - parameter integer C_S_AXI_ADDR_WIDTH = 6 + parameter integer C_S_AXI_ADDR_WIDTH = 7 ) ( // Users to add ports here @@ -99,6 +99,22 @@ reg [31:0] valid_reg; reg [31:0] corrupt_reg; reg [31:0] timeout_reg; + reg [31:0] adc_dout8; + reg [31:0] adc_dout9; + reg [31:0] adc_dout10; + reg [31:0] adc_dout11; + reg [31:0] adc_dout12; + reg [31:0] adc_dout13; + reg [31:0] adc_dout14; + reg [31:0] adc_dout15; + reg [31:0] adc_dout16; + reg [31:0] adc_dout17; + reg [31:0] adc_dout18; + reg [31:0] adc_dout19; + reg [31:0] adc_dout20; + reg [31:0] adc_dout21; + reg [31:0] adc_dout22; + reg [31:0] adc_dout23; // Debugging counters: Valid and Corrupt Counters are in each instance of adc_uart // Timeout Counters are just below in this module @@ -129,11 +145,11 @@ // ADDR_LSB = 2 for 32 bits (n downto 2) // ADDR_LSB = 3 for 64 bits (n downto 3) localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1; - localparam integer OPT_MEM_ADDR_BITS = 3; + localparam integer OPT_MEM_ADDR_BITS = 4; //---------------------------------------------- //-- Signals for user logic register space example //------------------------------------------------ - //-- Number of Slave Registers 16 + //-- Number of Slave Registers 32 reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0; reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1; reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2; @@ -150,6 +166,22 @@ reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg13; reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg14; reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg15; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg16; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg17; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg18; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg19; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg20; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg21; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg22; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg23; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg24; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg25; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg26; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg27; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg28; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg29; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30; + reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31; wire slv_reg_rden; wire slv_reg_wren; reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out; @@ -278,123 +310,251 @@ slv_reg13 <= 0; slv_reg14 <= 0; slv_reg15 <= 0; + slv_reg16 <= 0; + slv_reg17 <= 0; + slv_reg18 <= 0; + slv_reg19 <= 0; + slv_reg20 <= 0; + slv_reg21 <= 0; + slv_reg22 <= 0; + slv_reg23 <= 0; + slv_reg24 <= 0; + slv_reg25 <= 0; + slv_reg26 <= 0; + slv_reg27 <= 0; + slv_reg28 <= 0; + slv_reg29 <= 0; + slv_reg30 <= 0; + slv_reg31 <= 0; end else begin if (slv_reg_wren) begin case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) - 4'h0: + 5'h0: for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) if ( S_AXI_WSTRB[byte_index] == 1 ) begin // Respective byte enables are asserted as per write strobes // Slave register 0 slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; end - 4'h1: + 5'h1: for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) if ( S_AXI_WSTRB[byte_index] == 1 ) begin // Respective byte enables are asserted as per write strobes // Slave register 1 slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; end - 4'h2: + 5'h2: for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) if ( S_AXI_WSTRB[byte_index] == 1 ) begin // Respective byte enables are asserted as per write strobes // Slave register 2 slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; end - 4'h3: + 5'h3: for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) if ( S_AXI_WSTRB[byte_index] == 1 ) begin // Respective byte enables are asserted as per write strobes // Slave register 3 slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; end - 4'h4: + 5'h4: for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) if ( S_AXI_WSTRB[byte_index] == 1 ) begin // Respective byte enables are asserted as per write strobes // Slave register 4 slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; end - 4'h5: + 5'h5: for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) if ( S_AXI_WSTRB[byte_index] == 1 ) begin // Respective byte enables are asserted as per write strobes // Slave register 5 slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; end - 4'h6: + 5'h6: for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) if ( S_AXI_WSTRB[byte_index] == 1 ) begin // Respective byte enables are asserted as per write strobes // Slave register 6 slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; end - 4'h7: + 5'h7: for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) if ( S_AXI_WSTRB[byte_index] == 1 ) begin // Respective byte enables are asserted as per write strobes // Slave register 7 slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; end - 4'h8: + 5'h8: for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) if ( S_AXI_WSTRB[byte_index] == 1 ) begin // Respective byte enables are asserted as per write strobes // Slave register 8 slv_reg8[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; end - 4'h9: + 5'h9: for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) if ( S_AXI_WSTRB[byte_index] == 1 ) begin // Respective byte enables are asserted as per write strobes // Slave register 9 slv_reg9[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; end - 4'hA: + 5'hA: for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) if ( S_AXI_WSTRB[byte_index] == 1 ) begin // Respective byte enables are asserted as per write strobes // Slave register 10 slv_reg10[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; end - 4'hB: + 5'hB: for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) if ( S_AXI_WSTRB[byte_index] == 1 ) begin // Respective byte enables are asserted as per write strobes // Slave register 11 slv_reg11[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; end - 4'hC: + 5'hC: for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) if ( S_AXI_WSTRB[byte_index] == 1 ) begin // Respective byte enables are asserted as per write strobes // Slave register 12 slv_reg12[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; end - 4'hD: + 5'hD: for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) if ( S_AXI_WSTRB[byte_index] == 1 ) begin // Respective byte enables are asserted as per write strobes // Slave register 13 slv_reg13[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; end - 4'hE: + 5'hE: for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) if ( S_AXI_WSTRB[byte_index] == 1 ) begin // Respective byte enables are asserted as per write strobes // Slave register 14 slv_reg14[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; end - 4'hF: + 5'hF: for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) if ( S_AXI_WSTRB[byte_index] == 1 ) begin // Respective byte enables are asserted as per write strobes // Slave register 15 slv_reg15[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; end + 5'h10: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 16 + slv_reg16[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h11: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 17 + slv_reg17[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h12: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 18 + slv_reg18[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h13: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 19 + slv_reg19[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h14: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 20 + slv_reg20[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h15: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 21 + slv_reg21[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h16: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 22 + slv_reg22[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h17: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 23 + slv_reg23[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h18: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 24 + slv_reg24[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h19: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 25 + slv_reg25[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h1A: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 26 + slv_reg26[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h1B: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 27 + slv_reg27[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h1C: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 28 + slv_reg28[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h1D: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 29 + slv_reg29[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h1E: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 30 + slv_reg30[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end + 5'h1F: + for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 ) + if ( S_AXI_WSTRB[byte_index] == 1 ) begin + // Respective byte enables are asserted as per write strobes + // Slave register 31 + slv_reg31[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8]; + end default : begin slv_reg0 <= slv_reg0; slv_reg1 <= slv_reg1; @@ -412,6 +572,22 @@ slv_reg13 <= slv_reg13; slv_reg14 <= slv_reg14; slv_reg15 <= slv_reg15; + slv_reg16 <= slv_reg16; + slv_reg17 <= slv_reg17; + slv_reg18 <= slv_reg18; + slv_reg19 <= slv_reg19; + slv_reg20 <= slv_reg20; + slv_reg21 <= slv_reg21; + slv_reg22 <= slv_reg22; + slv_reg23 <= slv_reg23; + slv_reg24 <= slv_reg24; + slv_reg25 <= slv_reg25; + slv_reg26 <= slv_reg26; + slv_reg27 <= slv_reg27; + slv_reg28 <= slv_reg28; + slv_reg29 <= slv_reg29; + slv_reg30 <= slv_reg30; + slv_reg31 <= slv_reg31; end endcase end @@ -520,22 +696,38 @@ begin // Address decoding for reading registers case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] ) - 4'h0 : reg_data_out <= adc_dout0; - 4'h1 : reg_data_out <= adc_dout1; - 4'h2 : reg_data_out <= adc_dout2; - 4'h3 : reg_data_out <= adc_dout3; - 4'h4 : reg_data_out <= adc_dout4; - 4'h5 : reg_data_out <= adc_dout5; - 4'h6 : reg_data_out <= adc_dout6; - 4'h7 : reg_data_out <= adc_dout7; - 4'h8 : reg_data_out <= {trigger_to_fe1_timer, trigger_to_fe0_timer}; - 4'h9 : reg_data_out <= ch_valid_reg; - 4'hA : reg_data_out <= {counter_line1_bytes_valid, counter_line0_bytes_valid}; // slv_reg10 - 4'hB : reg_data_out <= {counter_line1_bytes_corrupt, counter_line0_bytes_corrupt}; // slv_reg11 - 4'hC : reg_data_out <= {counter_line1_bytes_timed_out, counter_line0_bytes_timed_out}; // slv_reg12 - 4'hD : reg_data_out <= {counter_line1_data_timed_out, counter_line0_data_timed_out}; // slv_reg13 - 4'hE : reg_data_out <= slv_reg14; - 4'hF : reg_data_out <= slv_reg15; + 5'h0 : reg_data_out <= adc_dout0; + 5'h1 : reg_data_out <= adc_dout1; + 5'h2 : reg_data_out <= adc_dout2; + 5'h3 : reg_data_out <= adc_dout3; + 5'h4 : reg_data_out <= adc_dout4; + 5'h5 : reg_data_out <= adc_dout5; + 5'h6 : reg_data_out <= adc_dout6; + 5'h7 : reg_data_out <= adc_dout7; + 5'h8 : reg_data_out <= {trigger_to_fe1_timer, trigger_to_fe0_timer}; + 5'h9 : reg_data_out <= ch_valid_reg; + 5'hA : reg_data_out <= {counter_line1_bytes_valid, counter_line0_bytes_valid}; // slv_reg10 + 5'hB : reg_data_out <= {counter_line1_bytes_corrupt, counter_line0_bytes_corrupt}; // slv_reg11 + 5'hC : reg_data_out <= {counter_line1_bytes_timed_out, counter_line0_bytes_timed_out}; // slv_reg12 + 5'hD : reg_data_out <= {counter_line1_data_timed_out, counter_line0_data_timed_out}; // slv_reg13 + 5'hE : reg_data_out <= adc_dout8; + 5'hF : reg_data_out <= adc_dout9; + 5'h10 : reg_data_out <= adc_dout10; + 5'h11 : reg_data_out <= adc_dout11; + 5'h12 : reg_data_out <= adc_dout12; + 5'h13 : reg_data_out <= adc_dout13; + 5'h14 : reg_data_out <= adc_dout14; + 5'h15 : reg_data_out <= adc_dout15; + 5'h16 : reg_data_out <= adc_dout16; + 5'h17 : reg_data_out <= adc_dout17; + 5'h18 : reg_data_out <= adc_dout18; + 5'h19 : reg_data_out <= adc_dout19; + 5'h1A : reg_data_out <= adc_dout20; + 5'h1B : reg_data_out <= adc_dout21; + 5'h1C : reg_data_out <= adc_dout22; + 5'h1D : reg_data_out <= adc_dout23; + 5'h1E : reg_data_out <= slv_reg30; + 5'h1F : reg_data_out <= slv_reg31; default : reg_data_out <= 0; endcase end @@ -584,9 +776,13 @@ // When a data line first goes low after a trigger event, this module // knows to expect a new data packet transmission. Therefore, it will // start a state machine internally to read each UART word. - wire [3:0] is_dout0_valid, is_dout1_valid; + wire [11:0] is_dout0_valid, is_dout1_valid; + wire [11:0] is_dout0_enabled, is_dout1_enabled; wire adc_uart0_done, assert_done_0; wire adc_uart1_done, assert_done_1; + + assign is_dout0_enabled = {slv_reg30[19:16], slv_reg30[11:8], slv_reg30[3:0]}; + assign is_dout1_enabled = {slv_reg30[23:20], slv_reg30[15:12], slv_reg30[7:4]}; wire [15:0] my_adc_data0; wire [15:0] my_adc_data1; @@ -596,6 +792,23 @@ wire [15:0] my_adc_data5; wire [15:0] my_adc_data6; wire [15:0] my_adc_data7; + wire [15:0] my_adc_data8; + wire [15:0] my_adc_data9; + wire [15:0] my_adc_data10; + wire [15:0] my_adc_data11; + wire [15:0] my_adc_data12; + wire [15:0] my_adc_data13; + wire [15:0] my_adc_data14; + wire [15:0] my_adc_data15; + wire [15:0] my_adc_data16; + wire [15:0] my_adc_data17; + wire [15:0] my_adc_data18; + wire [15:0] my_adc_data19; + wire [15:0] my_adc_data20; + wire [15:0] my_adc_data21; + wire [15:0] my_adc_data22; + wire [15:0] my_adc_data23; + // Timing Out: @@ -611,8 +824,8 @@ // In the event of either timeout, the driver must say that it is done, so that the timing // manager does not freeze. wire first_packet_timeout0, first_packet_timeout1; - assign first_packet_timeout0 = (trigger_to_fe0_timer > 11'd2000); - assign first_packet_timeout1 = (trigger_to_fe1_timer > 11'd2000); + assign first_packet_timeout0 = (trigger_to_fe0_timer > 13'd6000); + assign first_packet_timeout1 = (trigger_to_fe1_timer > 13'd6000); always @(posedge S_AXI_ACLK) begin if (~S_AXI_ARESETN) @@ -722,12 +935,21 @@ .start_rx(start_rx0), .din(amds_data_ff2[0]), .is_dout_valid(is_dout0_valid), + .is_dout_enabled(is_dout0_enabled), .adc_uart_done(adc_uart0_done), .assert_done(assert_done_0), .adc_dout0(my_adc_data0), .adc_dout1(my_adc_data1), .adc_dout2(my_adc_data2), .adc_dout3(my_adc_data3), + .adc_dout4(my_adc_data8), + .adc_dout5(my_adc_data9), + .adc_dout6(my_adc_data10), + .adc_dout7(my_adc_data11), + .adc_dout8(my_adc_data16), + .adc_dout9(my_adc_data17), + .adc_dout10(my_adc_data18), + .adc_dout11(my_adc_data19), .counter_bytes_valid(counter_line0_bytes_valid), .counter_bytes_corrupt(counter_line0_bytes_corrupt), .counter_bytes_timed_out(counter_line0_bytes_timed_out) @@ -739,12 +961,21 @@ .start_rx(start_rx1), .din(amds_data_ff2[1]), .is_dout_valid(is_dout1_valid), + .is_dout_enabled(is_dout1_enabled), .adc_uart_done(adc_uart1_done), .assert_done(assert_done_1), .adc_dout0(my_adc_data4), .adc_dout1(my_adc_data5), .adc_dout2(my_adc_data6), .adc_dout3(my_adc_data7), + .adc_dout4(my_adc_data12), + .adc_dout5(my_adc_data13), + .adc_dout6(my_adc_data14), + .adc_dout7(my_adc_data15), + .adc_dout8(my_adc_data20), + .adc_dout9(my_adc_data21), + .adc_dout10(my_adc_data22), + .adc_dout11(my_adc_data23), .counter_bytes_valid(counter_line1_bytes_valid), .counter_bytes_corrupt(counter_line1_bytes_corrupt), .counter_bytes_timed_out(counter_line1_bytes_timed_out) @@ -756,51 +987,153 @@ always @(posedge S_AXI_ACLK) begin if (~S_AXI_ARESETN) adc_dout0 <= 32'b0; - else if (adc_uart0_done) + else if (adc_uart0_done & slv_reg30[0]) adc_dout0 <= {{16{my_adc_data0[15]}}, my_adc_data0}; end always @(posedge S_AXI_ACLK) begin if (~S_AXI_ARESETN) adc_dout1 <= 32'b0; - else if (adc_uart0_done) + else if (adc_uart0_done & slv_reg30[1]) adc_dout1 <= {{16{my_adc_data1[15]}}, my_adc_data1}; end always @(posedge S_AXI_ACLK) begin if (~S_AXI_ARESETN) adc_dout2 <= 32'b0; - else if (adc_uart0_done) + else if (adc_uart0_done & slv_reg30[2]) adc_dout2 <= {{16{my_adc_data2[15]}}, my_adc_data2}; end always @(posedge S_AXI_ACLK) begin if (~S_AXI_ARESETN) adc_dout3 <= 32'b0; - else if (adc_uart0_done) + else if (adc_uart0_done & slv_reg30[3]) adc_dout3 <= {{16{my_adc_data3[15]}}, my_adc_data3}; end always @(posedge S_AXI_ACLK) begin if (~S_AXI_ARESETN) adc_dout4 <= 32'b0; - else if (adc_uart1_done) + else if (adc_uart1_done & slv_reg30[4]) adc_dout4 <= {{16{my_adc_data4[15]}}, my_adc_data4}; end always @(posedge S_AXI_ACLK) begin if (~S_AXI_ARESETN) adc_dout5 <= 32'b0; - else if (adc_uart1_done) + else if (adc_uart1_done & slv_reg30[5]) adc_dout5 <= {{16{my_adc_data5[15]}}, my_adc_data5}; end always @(posedge S_AXI_ACLK) begin if (~S_AXI_ARESETN) adc_dout6 <= 32'b0; - else if (adc_uart1_done) + else if (adc_uart1_done & slv_reg30[6]) adc_dout6 <= {{16{my_adc_data6[15]}}, my_adc_data6}; end always @(posedge S_AXI_ACLK) begin if (~S_AXI_ARESETN) adc_dout7 <= 32'b0; - else if (adc_uart1_done) + else if (adc_uart1_done & slv_reg30[7]) adc_dout7 <= {{16{my_adc_data7[15]}}, my_adc_data7}; end + + + + always @(posedge S_AXI_ACLK) begin + if (~S_AXI_ARESETN) + adc_dout8 <= 32'b0; + else if (adc_uart0_done & slv_reg30[8]) + adc_dout8 <= {{16{my_adc_data8[15]}}, my_adc_data8}; + end + always @(posedge S_AXI_ACLK) begin + if (~S_AXI_ARESETN) + adc_dout9 <= 32'b0; + else if (adc_uart0_done & slv_reg30[9]) + adc_dout9 <= {{16{my_adc_data9[15]}}, my_adc_data9}; + end + always @(posedge S_AXI_ACLK) begin + if (~S_AXI_ARESETN) + adc_dout10 <= 32'b0; + else if (adc_uart0_done & slv_reg30[10]) + adc_dout10 <= {{16{my_adc_data10[15]}}, my_adc_data10}; + end + always @(posedge S_AXI_ACLK) begin + if (~S_AXI_ARESETN) + adc_dout11 <= 32'b0; + else if (adc_uart0_done & slv_reg30[11]) + adc_dout11 <= {{16{my_adc_data11[15]}}, my_adc_data11}; + end + always @(posedge S_AXI_ACLK) begin + if (~S_AXI_ARESETN) + adc_dout12 <= 32'b0; + else if (adc_uart1_done & slv_reg30[12]) + adc_dout12 <= {{16{my_adc_data12[15]}}, my_adc_data12}; + end + always @(posedge S_AXI_ACLK) begin + if (~S_AXI_ARESETN) + adc_dout13 <= 32'b0; + else if (adc_uart1_done & slv_reg30[13]) + adc_dout13 <= {{16{my_adc_data13[15]}}, my_adc_data13}; + end + always @(posedge S_AXI_ACLK) begin + if (~S_AXI_ARESETN) + adc_dout14 <= 32'b0; + else if (adc_uart1_done & slv_reg30[14]) + adc_dout14 <= {{16{my_adc_data14[15]}}, my_adc_data14}; + end + always @(posedge S_AXI_ACLK) begin + if (~S_AXI_ARESETN) + adc_dout15 <= 32'b0; + else if (adc_uart1_done & slv_reg30[15]) + adc_dout15 <= {{16{my_adc_data15[15]}}, my_adc_data15}; + end + + + + always @(posedge S_AXI_ACLK) begin + if (~S_AXI_ARESETN) + adc_dout16 <= 32'b0; + else if (adc_uart0_done & slv_reg30[16]) + adc_dout16 <= {{16{my_adc_data16[15]}}, my_adc_data16}; + end + always @(posedge S_AXI_ACLK) begin + if (~S_AXI_ARESETN) + adc_dout17 <= 32'b0; + else if (adc_uart0_done & slv_reg30[17]) + adc_dout17 <= {{16{my_adc_data17[15]}}, my_adc_data17}; + end + always @(posedge S_AXI_ACLK) begin + if (~S_AXI_ARESETN) + adc_dout18 <= 32'b0; + else if (adc_uart0_done & slv_reg30[18]) + adc_dout18 <= {{16{my_adc_data18[15]}}, my_adc_data18}; + end + always @(posedge S_AXI_ACLK) begin + if (~S_AXI_ARESETN) + adc_dout19 <= 32'b0; + else if (adc_uart0_done & slv_reg30[19]) + adc_dout19 <= {{16{my_adc_data19[15]}}, my_adc_data19}; + end + always @(posedge S_AXI_ACLK) begin + if (~S_AXI_ARESETN) + adc_dout20 <= 32'b0; + else if (adc_uart1_done & slv_reg30[20]) + adc_dout20 <= {{16{my_adc_data20[15]}}, my_adc_data20}; + end + always @(posedge S_AXI_ACLK) begin + if (~S_AXI_ARESETN) + adc_dout21 <= 32'b0; + else if (adc_uart1_done & slv_reg30[21]) + adc_dout21 <= {{16{my_adc_data21[15]}}, my_adc_data21}; + end + always @(posedge S_AXI_ACLK) begin + if (~S_AXI_ARESETN) + adc_dout22 <= 32'b0; + else if (adc_uart1_done & slv_reg30[22]) + adc_dout22 <= {{16{my_adc_data22[15]}}, my_adc_data22}; + end + always @(posedge S_AXI_ACLK) begin + if (~S_AXI_ARESETN) + adc_dout23 <= 32'b0; + else if (adc_uart1_done & slv_reg30[23]) + adc_dout23 <= {{16{my_adc_data23[15]}}, my_adc_data23}; + end // ============================================= // Channel Valid Register @@ -810,7 +1143,7 @@ if (~S_AXI_ARESETN) ch_valid_reg <= 32'b0; else if (done) - ch_valid_reg <= {24'b0, is_dout1_valid, is_dout0_valid}; + ch_valid_reg <= {8'b0, is_dout1_valid, is_dout0_valid}; end // Receiving is done when both sub-receivers are done, but diff --git a/ip_repo/amdc_amds_1.0/src/adc_uart_rx.v b/ip_repo/amdc_amds_1.0/src/adc_uart_rx.v index 330fae46..22451cf4 100644 --- a/ip_repo/amdc_amds_1.0/src/adc_uart_rx.v +++ b/ip_repo/amdc_amds_1.0/src/adc_uart_rx.v @@ -9,14 +9,23 @@ module adc_uart_rx( // The data line coming from the AMDS input wire din, + input wire [11:0] is_dout_enabled, - output wire [3:0] is_dout_valid, // is_dout_valid[0] == 1 implies that adc_dout0 is valid + output wire [11:0] is_dout_valid, // is_dout_valid[0] == 1 implies that adc_dout0 is valid output reg adc_uart_done, output reg assert_done, output reg [15:0] adc_dout0, output reg [15:0] adc_dout1, output reg [15:0] adc_dout2, output reg [15:0] adc_dout3, + output reg [15:0] adc_dout4, + output reg [15:0] adc_dout5, + output reg [15:0] adc_dout6, + output reg [15:0] adc_dout7, + output reg [15:0] adc_dout8, + output reg [15:0] adc_dout9, + output reg [15:0] adc_dout10, + output reg [15:0] adc_dout11, output reg [15:0] counter_bytes_valid, output reg [15:0] counter_bytes_corrupt, @@ -30,13 +39,13 @@ module adc_uart_rx( reg rst_packet_counter; reg inc_packet_counter; -reg [1:0] packet_counter; +reg [11:0] packet_counter; always @(posedge clk, negedge rst_n) begin if (!rst_n) - packet_counter <= 2'b0; + packet_counter <= 12'b0; else if (rst_packet_counter) - packet_counter <= 2'b0; + packet_counter <= 12'b0; else if (inc_packet_counter) packet_counter <= packet_counter + 1; end @@ -47,6 +56,9 @@ end reg is_dout0_valid, is_dout1_valid, is_dout2_valid, is_dout3_valid; +reg is_dout4_valid, is_dout5_valid, is_dout6_valid, is_dout7_valid; +reg is_dout8_valid, is_dout9_valid, is_dout10_valid, is_dout11_valid; + reg assert_data_valid, clr_all_data_valid; always @(posedge clk, negedge rst_n) begin @@ -54,7 +66,7 @@ always @(posedge clk, negedge rst_n) begin is_dout0_valid <= 1'b0; else if (clr_all_data_valid) is_dout0_valid <= 1'b0; - else if (assert_data_valid & packet_counter == 0) + else if (assert_data_valid & packet_counter == 0 & is_dout_enabled[0]) is_dout0_valid <= 1'b1; end @@ -63,7 +75,7 @@ always @(posedge clk, negedge rst_n) begin is_dout1_valid <= 1'b0; else if (clr_all_data_valid) is_dout1_valid <= 1'b0; - else if (assert_data_valid & packet_counter == 1) + else if (assert_data_valid & packet_counter == 1 & is_dout_enabled[1]) is_dout1_valid <= 1'b1; end @@ -72,7 +84,7 @@ always @(posedge clk, negedge rst_n) begin is_dout2_valid <= 1'b0; else if (clr_all_data_valid) is_dout2_valid <= 1'b0; - else if (assert_data_valid & packet_counter == 2) + else if (assert_data_valid & packet_counter == 2 & is_dout_enabled[2]) is_dout2_valid <= 1'b1; end @@ -81,12 +93,97 @@ always @(posedge clk, negedge rst_n) begin is_dout3_valid <= 1'b0; else if (clr_all_data_valid) is_dout3_valid <= 1'b0; - else if (assert_data_valid & packet_counter == 3) + else if (assert_data_valid & packet_counter == 3 & is_dout_enabled[3]) is_dout3_valid <= 1'b1; end +always @(posedge clk, negedge rst_n) begin + if (~rst_n) + is_dout4_valid <= 1'b0; + else if (clr_all_data_valid) + is_dout4_valid <= 1'b0; + else if (assert_data_valid & packet_counter == 4 & is_dout_enabled[4]) + is_dout4_valid <= 1'b1; +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) + is_dout5_valid <= 1'b0; + else if (clr_all_data_valid) + is_dout5_valid <= 1'b0; + else if (assert_data_valid & packet_counter == 5 & is_dout_enabled[5]) + is_dout5_valid <= 1'b1; +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) + is_dout6_valid <= 1'b0; + else if (clr_all_data_valid) + is_dout6_valid <= 1'b0; + else if (assert_data_valid & packet_counter == 6 & is_dout_enabled[6]) + is_dout6_valid <= 1'b1; +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) + is_dout7_valid <= 1'b0; + else if (clr_all_data_valid) + is_dout7_valid <= 1'b0; + else if (assert_data_valid & packet_counter == 7 & is_dout_enabled[7]) + is_dout7_valid <= 1'b1; +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) + is_dout8_valid <= 1'b0; + else if (clr_all_data_valid) + is_dout8_valid <= 1'b0; + else if (assert_data_valid & packet_counter == 8 & is_dout_enabled[8]) + is_dout8_valid <= 1'b1; +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) + is_dout9_valid <= 1'b0; + else if (clr_all_data_valid) + is_dout9_valid <= 1'b0; + else if (assert_data_valid & packet_counter == 9 & is_dout_enabled[9]) + is_dout9_valid <= 1'b1; +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) + is_dout10_valid <= 1'b0; + else if (clr_all_data_valid) + is_dout10_valid <= 1'b0; + else if (assert_data_valid & packet_counter == 10 & is_dout_enabled[10]) + is_dout10_valid <= 1'b1; +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) + is_dout11_valid <= 1'b0; + else if (clr_all_data_valid) + is_dout11_valid <= 1'b0; + else if (assert_data_valid & packet_counter == 11 & is_dout_enabled[11]) + is_dout11_valid <= 1'b1; +end + // Concatenate the individual valid registers into output bus -assign is_dout_valid = {is_dout3_valid, is_dout2_valid, is_dout1_valid, is_dout0_valid}; +assign is_dout_valid = { + is_dout11_valid, + is_dout10_valid, + is_dout9_valid, + is_dout8_valid, + is_dout7_valid, + is_dout6_valid, + is_dout5_valid, + is_dout4_valid, + is_dout3_valid, + is_dout2_valid, + is_dout1_valid, + is_dout0_valid +}; // =================== @@ -178,39 +275,47 @@ always @(posedge clk, negedge rst_n) begin adc_dout1 <= 16'b0; adc_dout2 <= 16'b0; adc_dout3 <= 16'b0; + adc_dout4 <= 16'b0; + adc_dout5 <= 16'b0; + adc_dout6 <= 16'b0; + adc_dout7 <= 16'b0; + adc_dout8 <= 16'b0; + adc_dout9 <= 16'b0; + adc_dout10 <= 16'b0; + adc_dout11 <= 16'b0; end else if (load_doutN_LSB) begin case (packet_counter) - 4'd0: begin - adc_dout0[7:0] <= uart_data_byte; - end - 4'd1: begin - adc_dout1[7:0] <= uart_data_byte; - end - 4'd2: begin - adc_dout2[7:0] <= uart_data_byte; - end - 4'd3: begin - adc_dout3[7:0] <= uart_data_byte; - end + 4'd0: adc_dout0[7:0] <= uart_data_byte; + 4'd1: adc_dout1[7:0] <= uart_data_byte; + 4'd2: adc_dout2[7:0] <= uart_data_byte; + 4'd3: adc_dout3[7:0] <= uart_data_byte; + 4'd4: adc_dout4[7:0] <= uart_data_byte; + 4'd5: adc_dout5[7:0] <= uart_data_byte; + 4'd6: adc_dout6[7:0] <= uart_data_byte; + 4'd7: adc_dout7[7:0] <= uart_data_byte; + 4'd8: adc_dout8[7:0] <= uart_data_byte; + 4'd9: adc_dout9[7:0] <= uart_data_byte; + 4'd10: adc_dout10[7:0] <= uart_data_byte; + 4'd11: adc_dout11[7:0] <= uart_data_byte; endcase end else if (load_doutN_MSB) begin case (packet_counter) - 4'd0: begin - adc_dout0[15:8] <= uart_data_byte; - end - 4'd1: begin - adc_dout1[15:8] <= uart_data_byte; - end - 4'd2: begin - adc_dout2[15:8] <= uart_data_byte; - end - 4'd3: begin - adc_dout3[15:8] <= uart_data_byte; - end + 4'd0: adc_dout0[15:8] <= uart_data_byte; + 4'd1: adc_dout1[15:8] <= uart_data_byte; + 4'd2: adc_dout2[15:8] <= uart_data_byte; + 4'd3: adc_dout3[15:8] <= uart_data_byte; + 4'd4: adc_dout4[15:8] <= uart_data_byte; + 4'd5: adc_dout5[15:8] <= uart_data_byte; + 4'd6: adc_dout6[15:8] <= uart_data_byte; + 4'd7: adc_dout7[15:8] <= uart_data_byte; + 4'd8: adc_dout8[15:8] <= uart_data_byte; + 4'd9: adc_dout9[15:8] <= uart_data_byte; + 4'd10: adc_dout10[15:8] <= uart_data_byte; + 4'd11: adc_dout11[15:8] <= uart_data_byte; endcase end end @@ -417,7 +522,7 @@ always @(*) begin assert_data_valid = 1; end - if (packet_counter == 4'd3) begin + if (packet_counter == 12'd11 || (is_dout_enabled >> (packet_counter + 1)) == 0) begin // Done (for real)! Captured all 4 data packets, so assert done and return to idle next_state = `SM_IDLE; assert_done = 1; diff --git a/ip_repo/amdc_amds_1.0/xgui/amdc_amds_v2_0.tcl b/ip_repo/amdc_amds_1.0/xgui/amdc_amds_v2_0.tcl new file mode 100644 index 00000000..d8bf1744 --- /dev/null +++ b/ip_repo/amdc_amds_1.0/xgui/amdc_amds_v2_0.tcl @@ -0,0 +1,62 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + set C_S00_AXI_DATA_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_DATA_WIDTH" -parent ${Page_0} -widget comboBox] + set_property tooltip {Width of S_AXI data bus} ${C_S00_AXI_DATA_WIDTH} + set C_S00_AXI_ADDR_WIDTH [ipgui::add_param $IPINST -name "C_S00_AXI_ADDR_WIDTH" -parent ${Page_0}] + set_property tooltip {Width of S_AXI address bus} ${C_S00_AXI_ADDR_WIDTH} + ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { + # Procedure called to update C_S00_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXI_DATA_WIDTH { PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { + # Procedure called to validate C_S00_AXI_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { + # Procedure called to update C_S00_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXI_ADDR_WIDTH { PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { + # Procedure called to validate C_S00_AXI_ADDR_WIDTH + return true +} + +proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } { + # Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } { + # Procedure called to validate C_S00_AXI_BASEADDR + return true +} + +proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } { + # Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } { + # Procedure called to validate C_S00_AXI_HIGHADDR + return true +} + + +proc update_MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH PARAM_VALUE.C_S00_AXI_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH PARAM_VALUE.C_S00_AXI_ADDR_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_S00_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH} +} + diff --git a/scripts/test.py b/scripts/test.py new file mode 100644 index 00000000..90fe8327 --- /dev/null +++ b/scripts/test.py @@ -0,0 +1,19 @@ +from AMDC import AMDC + +amdc = AMDC() + +# Set comm defaults for ETHERNET +amdc.setup_comm_defaults('eth') + +# Init ethernet +amdc.eth_init() + +# Set up the default ASCII command socket +s0, s0_id = amdc.eth_new_socket('ascii_cmd') +amdc.eth_set_default_ascii_cmd_socket(s0) + +amdc.connect() +amdc.comm_cmd_delay_cmd = .01 +amdc.cmd('ctrl get enc') +amdc.cmd('test analog') +amdc.disconnect() \ No newline at end of file diff --git a/sdk/app_cpu1/.project b/sdk/app_cpu1/.project new file mode 100644 index 00000000..738cd7df --- /dev/null +++ b/sdk/app_cpu1/.project @@ -0,0 +1,11 @@ + + + app_cpu1 + + + + + + + + diff --git a/sdk/app_cpu1/common/drv/amds.c b/sdk/app_cpu1/common/drv/amds.c index 9d4ee194..d2676ddb 100644 --- a/sdk/app_cpu1/common/drv/amds.c +++ b/sdk/app_cpu1/common/drv/amds.c @@ -11,6 +11,13 @@ #include #include +volatile uint32_t AMDS_PORT_CH_ENABLE[AMDS_MAX_IP_CORES] = { + 0x00FFFFFF, + 0x00FFFFFF, + 0x00FFFFFF, + 0x00FFFFFF +}; + void amds_init(void) { xil_printf("AMDS: Initializing...\r\n"); @@ -31,7 +38,7 @@ void amds_init(void) * NOTE: Because the AMDS mainboard firmware does not do anything different for unpopulated * SensorCards, the validity of those channels is meaningless */ -uint8_t amds_check_data_validity(uint8_t port) +uint32_t amds_check_data_validity(uint8_t port) { uint32_t base_addr = amds_port_to_base_addr(port); @@ -40,7 +47,7 @@ uint8_t amds_check_data_validity(uint8_t port) return 0; } - return Xil_In8(base_addr + AMDS_CH_VALID_REG_OFFSET); + return Xil_In32(base_addr + AMDS_CH_VALID_REG_OFFSET); } /* Retrieves the raw ADC data for a single channel on a single AMDS. @@ -62,7 +69,7 @@ int amds_get_data(uint8_t port, amds_channel_e channel, int32_t *out) return FAILURE; } - if (!is_amds_channel_in_bounds(channel)) { + if (!is_amds_channel_in_bounds(channel) || !is_amds_channel_enabled(port - 1, channel)) { return FAILURE; } else { *out = (int32_t) (Xil_In32(base_addr + channel * sizeof(uint32_t))); @@ -136,9 +143,18 @@ void amds_print_data(uint8_t port) // Cast the address to a pointer for array-like access volatile uint32_t *arr_base_addr = (volatile uint32_t *) base_addr; - for (int i = 0; i < 8; i++) { - uint32_t val = arr_base_addr[i]; - cmd_resp_printf("CH_%i: %04X\r\n", i + 1, val); + for (int i = 0; i < 24; i++) { + if (!is_amds_channel_enabled(port - 1, i)) { + continue; + } + + if (i < 8) { + uint32_t val = arr_base_addr[i]; + cmd_resp_printf("CH_%i: %04X\r\n", i + 1, val); + } else { + uint32_t val = arr_base_addr[i + 6]; + cmd_resp_printf("CH_%i: %04X\r\n", i + 1, val); + } } } } @@ -208,11 +224,15 @@ int amds_get_trigger_to_edge_delay(uint8_t port, amds_channel_e channel, double // Data line 0 is bits [15:0] and Data line 1 is bits [31:16] uint32_t delay_cycles_both_lines = Xil_In32(base_addr + AMDS_DELAY_TIMER_REG_OFFSET); - if (channel >= AMDS_CH_1 && channel <= AMDS_CH_4) { + if ((channel >= AMDS_CH_1 && channel <= AMDS_CH_4) || + (channel >= AMDS_CH_9 && channel <= AMDS_CH_12) || + (channel >= AMDS_CH_17 && channel <= AMDS_CH_20)) { // Delay time in us for data line 0 *out = (double) (delay_cycles_both_lines & 0xFFFF) / CLOCK_FPGA_CLK_FREQ_MHZ; return SUCCESS; - } else if (channel >= AMDS_CH_5 && channel <= AMDS_CH_8) { + } else if ((channel >= AMDS_CH_5 && channel <= AMDS_CH_8) || + (channel >= AMDS_CH_13 && channel <= AMDS_CH_16) || + (channel >= AMDS_CH_21 && channel <= AMDS_CH_24)) { // Delay time in us for data line 1 *out = (double) (delay_cycles_both_lines >> 16) / CLOCK_FPGA_CLK_FREQ_MHZ; return SUCCESS; diff --git a/sdk/app_cpu1/common/drv/amds.h b/sdk/app_cpu1/common/drv/amds.h index 9ee1ebf5..30257d07 100644 --- a/sdk/app_cpu1/common/drv/amds.h +++ b/sdk/app_cpu1/common/drv/amds.h @@ -23,30 +23,66 @@ #endif // Offsets for relevant slave registers, to be added to one of the AMDS_N_BASE_ADDR -#define AMDS_CH_1_DATA_REG_OFFSET (0) -#define AMDS_CH_2_DATA_REG_OFFSET (1 * sizeof(uint32_t)) -#define AMDS_CH_3_DATA_REG_OFFSET (2 * sizeof(uint32_t)) -#define AMDS_CH_4_DATA_REG_OFFSET (3 * sizeof(uint32_t)) -#define AMDS_CH_5_DATA_REG_OFFSET (4 * sizeof(uint32_t)) -#define AMDS_CH_6_DATA_REG_OFFSET (5 * sizeof(uint32_t)) -#define AMDS_CH_7_DATA_REG_OFFSET (6 * sizeof(uint32_t)) -#define AMDS_CH_8_DATA_REG_OFFSET (7 * sizeof(uint32_t)) -#define AMDS_DELAY_TIMER_REG_OFFSET (8 * sizeof(uint32_t)) -#define AMDS_CH_VALID_REG_OFFSET (9 * sizeof(uint32_t)) -#define AMDS_BYTES_VALID_REG_OFFSET (10 * sizeof(uint32_t)) -#define AMDS_BYTES_CORRUPT_REG_OFFSET (11 * sizeof(uint32_t)) -#define AMDS_BYTES_TIMED_OUT_REG_OFFSET (12 * sizeof(uint32_t)) -#define AMDS_DATA_TIMED_OUT_REG_OFFSET (13 * sizeof(uint32_t)) +#define AMDS_CH_1_DATA_REG_OFFSET (0) +#define AMDS_CH_2_DATA_REG_OFFSET (1 * sizeof(uint32_t)) +#define AMDS_CH_3_DATA_REG_OFFSET (2 * sizeof(uint32_t)) +#define AMDS_CH_4_DATA_REG_OFFSET (3 * sizeof(uint32_t)) +#define AMDS_CH_5_DATA_REG_OFFSET (4 * sizeof(uint32_t)) +#define AMDS_CH_6_DATA_REG_OFFSET (5 * sizeof(uint32_t)) +#define AMDS_CH_7_DATA_REG_OFFSET (6 * sizeof(uint32_t)) +#define AMDS_CH_8_DATA_REG_OFFSET (7 * sizeof(uint32_t)) +#define AMDS_DELAY_TIMER_REG_OFFSET (8 * sizeof(uint32_t)) +#define AMDS_CH_VALID_REG_OFFSET (9 * sizeof(uint32_t)) +#define AMDS_BYTES_VALID_REG_OFFSET (10 * sizeof(uint32_t)) +#define AMDS_BYTES_CORRUPT_REG_OFFSET (11 * sizeof(uint32_t)) +#define AMDS_BYTES_TIMED_OUT_REG_OFFSET (12 * sizeof(uint32_t)) +#define AMDS_DATA_TIMED_OUT_REG_OFFSET (13 * sizeof(uint32_t)) +#define AMDS_CH_9_DATA_REG_OFFSET (14 * sizeof(uint32_t)) +#define AMDS_CH_10_DATA_REG_OFFSET (15 * sizeof(uint32_t)) +#define AMDS_CH_11_DATA_REG_OFFSET (16 * sizeof(uint32_t)) +#define AMDS_CH_12_DATA_REG_OFFSET (17 * sizeof(uint32_t)) +#define AMDS_CH_13_DATA_REG_OFFSET (18 * sizeof(uint32_t)) +#define AMDS_CH_14_DATA_REG_OFFSET (19 * sizeof(uint32_t)) +#define AMDS_CH_15_DATA_REG_OFFSET (20 * sizeof(uint32_t)) +#define AMDS_CH_16_DATA_REG_OFFSET (21 * sizeof(uint32_t)) +#define AMDS_CH_17_DATA_REG_OFFSET (22 * sizeof(uint32_t)) +#define AMDS_CH_18_DATA_REG_OFFSET (23 * sizeof(uint32_t)) +#define AMDS_CH_19_DATA_REG_OFFSET (24 * sizeof(uint32_t)) +#define AMDS_CH_20_DATA_REG_OFFSET (25 * sizeof(uint32_t)) +#define AMDS_CH_21_DATA_REG_OFFSET (26 * sizeof(uint32_t)) +#define AMDS_CH_22_DATA_REG_OFFSET (27 * sizeof(uint32_t)) +#define AMDS_CH_23_DATA_REG_OFFSET (28 * sizeof(uint32_t)) +#define AMDS_CH_24_DATA_REG_OFFSET (29 * sizeof(uint32_t)) +#define AMDS_CH_ENABLE_REG_OFFSET (30 * sizeof(uint32_t)) + +// Bit mask selecting channels to enable +extern volatile uint32_t AMDS_PORT_CH_ENABLE[AMDS_MAX_IP_CORES]; // Bit masks for use with amds_check_data_validity() -#define AMDS_CH_1_VALID_MASK 0x01 -#define AMDS_CH_2_VALID_MASK 0x02 -#define AMDS_CH_3_VALID_MASK 0x04 -#define AMDS_CH_4_VALID_MASK 0x08 -#define AMDS_CH_5_VALID_MASK 0x10 -#define AMDS_CH_6_VALID_MASK 0x20 -#define AMDS_CH_7_VALID_MASK 0x40 -#define AMDS_CH_8_VALID_MASK 0x80 +#define AMDS_CH_1_VALID_MASK 0x1 +#define AMDS_CH_2_VALID_MASK 0x2 +#define AMDS_CH_3_VALID_MASK 0x4 +#define AMDS_CH_4_VALID_MASK 0x8 +#define AMDS_CH_5_VALID_MASK 0x10 +#define AMDS_CH_6_VALID_MASK 0x20 +#define AMDS_CH_7_VALID_MASK 0x40 +#define AMDS_CH_8_VALID_MASK 0x80 +#define AMDS_CH_9_VALID_MASK 0x100 +#define AMDS_CH_10_VALID_MASK 0x200 +#define AMDS_CH_11_VALID_MASK 0x400 +#define AMDS_CH_12_VALID_MASK 0x800 +#define AMDS_CH_13_VALID_MASK 0x1000 +#define AMDS_CH_14_VALID_MASK 0x2000 +#define AMDS_CH_15_VALID_MASK 0x4000 +#define AMDS_CH_16_VALID_MASK 0x8000 +#define AMDS_CH_17_VALID_MASK 0x10000 +#define AMDS_CH_18_VALID_MASK 0x20000 +#define AMDS_CH_19_VALID_MASK 0x40000 +#define AMDS_CH_20_VALID_MASK 0x80000 +#define AMDS_CH_21_VALID_MASK 0x100000 +#define AMDS_CH_22_VALID_MASK 0x200000 +#define AMDS_CH_23_VALID_MASK 0x400000 +#define AMDS_CH_24_VALID_MASK 0x800000 // Default offset and gain values #define AMDS_LOW_VOLTAGE_DEFAULT_GAIN 10 @@ -68,9 +104,26 @@ typedef enum { AMDS_CH_6, AMDS_CH_7, AMDS_CH_8, + AMDS_CH_9 = 14, + AMDS_CH_10, + AMDS_CH_11, + AMDS_CH_12, + AMDS_CH_13, + AMDS_CH_14, + AMDS_CH_15, + AMDS_CH_16, + AMDS_CH_17, + AMDS_CH_18, + AMDS_CH_19, + AMDS_CH_20, + AMDS_CH_21, + AMDS_CH_22, + AMDS_CH_23, + AMDS_CH_24, + // Keep this as last entry! - AMDS_NUM_CHANNELS, + AMDS_NUM_CHANNELS = 24, } amds_channel_e; typedef enum { @@ -89,6 +142,11 @@ static inline bool is_amds_channel_in_bounds(amds_channel_e channel) return false; } +static inline bool is_amds_channel_enabled(uint8_t port, amds_channel_e channel) +{ + return (AMDS_PORT_CH_ENABLE[port] & (1u << channel)) != 0; +} + static inline bool is_amds_port_in_bounds(int port) { if (port >= 1 && port <= AMDS_MAX_IP_CORES) { @@ -120,7 +178,7 @@ static inline uint32_t amds_port_to_base_addr(int port) void amds_init(void); -uint8_t amds_check_data_validity(uint8_t port); +uint32_t amds_check_data_validity(uint8_t port); int amds_get_data(uint8_t port, amds_channel_e channel, int32_t *out); int amds_get_voltage(uint8_t port, amds_channel_e channel, amds_card_t card, double *out); int amds_convert_voltage(double voltage, double offset, double gain, double *out); diff --git a/sdk/app_cpu1/common/sys/cmd/cmd_amds.c b/sdk/app_cpu1/common/sys/cmd/cmd_amds.c index 49a8e485..0275390b 100644 --- a/sdk/app_cpu1/common/sys/cmd/cmd_amds.c +++ b/sdk/app_cpu1/common/sys/cmd/cmd_amds.c @@ -45,20 +45,20 @@ int cmd_amds(int argc, char **argv) // Handle 'amds valid' command if (argc == 3 && STREQ("valid", argv[2])) { - uint8_t valid_bits = amds_check_data_validity(port); - - uint8_t mask = 0x01; - uint8_t channel = 1; - - while (mask) { - if (valid_bits & mask) - cmd_resp_printf("Channel %i: Valid data\r\n", channel); - else - cmd_resp_printf("Channel %i: Invalid data\r\n", channel); - - mask = mask << 1; - channel++; - } + uint32_t valid_bits = amds_check_data_validity(port); + + for (int ch = 0; ch < 24; ch++) { + uint32_t mask = (1 << ch); // Shift 1 by 'ch' positions + + // Only print if the channel is enabled for this port + if (AMDS_PORT_CH_ENABLE[port - 1] & mask) { + if (valid_bits & mask) { + cmd_resp_printf("Channel %i:\tValid data\r\n", ch); + } else { + cmd_resp_printf("Channel %i:\tInvalid data\r\n", ch); + } + } + } return CMD_SUCCESS; } diff --git a/sdk/app_cpu1/user/.cproject b/sdk/app_cpu1/user/.cproject index eb596242..48dbd8e9 100644 --- a/sdk/app_cpu1/user/.cproject +++ b/sdk/app_cpu1/user/.cproject @@ -18,8 +18,18 @@ - + + + + + + + @@ -30,12 +40,14 @@ @@ -52,8 +64,6 @@ - + + diff --git a/sdk/app_cpu1/user/.gitignore b/sdk/app_cpu1/user/.gitignore new file mode 100644 index 00000000..3df573fe --- /dev/null +++ b/sdk/app_cpu1/user/.gitignore @@ -0,0 +1 @@ +/Debug/ diff --git a/sdk/app_cpu1/user/.project b/sdk/app_cpu1/user/.project index 1d6d8913..9973377c 100644 --- a/sdk/app_cpu1/user/.project +++ b/sdk/app_cpu1/user/.project @@ -23,4 +23,11 @@ org.eclipse.cdt.managedbuilder.core.managedBuildNature org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + common + 2 + C:/Users/moha2063/Desktop/eLev/AMDC-Firmware/sdk/app_cpu1/common + + diff --git a/sdk/app_cpu1/user/usr/beta_labs/machine.h b/sdk/app_cpu1/user/usr/beta_labs/machine.h index d2e34071..aaa7b656 100644 --- a/sdk/app_cpu1/user/usr/beta_labs/machine.h +++ b/sdk/app_cpu1/user/usr/beta_labs/machine.h @@ -20,9 +20,9 @@ #define Tu_HAT (0.0025) // kg-m/s^2 #define Kt_HAT (1.0 / (4.0 / (3.0 * POLES * Lambda_pm_HAT))) -// #define Kt_HAT (0.177768) // Nm / Arms -// #define Km_HAT (0.330) // Nm / sqrt(W) -// #define Ke_HAT (0.160) // Vpkll / (rads/s) +//#define Kt_HAT (0.177768) // Nm / Arms +//#define Km_HAT (0.330) // Nm / sqrt(W) +//#define Ke_HAT (0.160) // Vpkll / (rads/s) #define POLE_PAIRS (16.0) #define POLES (32.0) @@ -30,7 +30,7 @@ // NOTE: use this to artificially limit current #define I_rated_rms (10.0) // Arms -// #define I_rated_rms (24.2) // Arms +//#define I_rated_rms (24.2) // Arms #define I_rated_pk (I_rated_rms * SQRT2) // Apk #define I_rated_dq (I_rated_pk / SQRT23) // A_dq diff --git a/sdk/app_cpu1/user/usr/controller/app_controller.c b/sdk/app_cpu1/user/usr/controller/app_controller.c new file mode 100644 index 00000000..e4188074 --- /dev/null +++ b/sdk/app_cpu1/user/usr/controller/app_controller.c @@ -0,0 +1,37 @@ +#ifdef APP_CONTROLLER + +#include "usr/controller/app_controller.h" +#include "usr/controller/cmd/cmd_ctrl.h" +#include "drv/timing_manager.h" +#include "drv/gp3io_mux.h" +#include "drv/amds.h" +#include "drv/pwm.h" +#include "xil_io.h" + +void app_controller_init(void) +{ + // Configure GP3IO mux for the AMDS + // GP3IO_MUX_#_BASE_ADDR means AMDC GPIO Port # + // GP3IO_MUX_DEVICE1 is AMDS driver IP block + // GP3IO_MUX_DEVICE2 is Eddy Current Sensor IP block + gp3io_mux_set_device(GP3IO_MUX_1_BASE_ADDR, GP3IO_MUX_DEVICE1); + + // Enable data sampling for ADC + timing_manager_enable_sensor(ADC); + + // Enable data sampling for AMDS on GPIO Port # + timing_manager_enable_sensor(AMDS_1); + + pwm_disable(); + pwm_set_switching_freq(PWM_MIN_SWITCHING_FREQ_HZ); + + +// uint32_t reg_addr = AMDS_1_BASE_ADDR + AMDS_CH_ENABLE_REG_OFFSET; +// AMDS_PORT_CH_ENABLE[0] = 0x0000FFFF; +// Xil_Out32(reg_addr, AMDS_PORT_CH_ENABLE[0]); // enable 16 channels + + // register commands + cmd_ctrl_register(); +} + +#endif // APP_CONTROLLER diff --git a/sdk/app_cpu1/user/usr/controller/app_controller.h b/sdk/app_cpu1/user/usr/controller/app_controller.h new file mode 100644 index 00000000..c096e466 --- /dev/null +++ b/sdk/app_cpu1/user/usr/controller/app_controller.h @@ -0,0 +1,6 @@ +#ifndef APP_CONTROLLER_H +#define APP_CONTROLLER_H + +void app_controller_init(void); + +#endif // APP_CONTROLLER_H diff --git a/sdk/app_cpu1/user/usr/controller/cmd/cmd_ctrl.c b/sdk/app_cpu1/user/usr/controller/cmd/cmd_ctrl.c new file mode 100644 index 00000000..77d5cb51 --- /dev/null +++ b/sdk/app_cpu1/user/usr/controller/cmd/cmd_ctrl.c @@ -0,0 +1,108 @@ +#ifdef APP_CONTROLLER + +#include "usr/controller/cmd/cmd_ctrl.h" +#include "sys/commands.h" +#include "sys/defines.h" +#include "sys/util.h" +#include "usr/controller/task_controller.h" +#include "drv/pwm.h" +#include +#include +#include "drv/amds.h" +#include "xil_io.h" + +// Stores command entry for command system module +static command_entry_t cmd_entry; + +// Defines help content displayed for this command +// when user types "help" at command prompt +static command_help_t cmd_help[] = { + { "init", "Start task" }, + { "deinit", "Stop task" }, + { "freq ", "Set frequency of voltage output (rad/s)" }, + { "amplitude ", "Set amplitude of voltage output (0 to 1)" }, + { "print amds", "print raw AMDS channels" }, + { "read ", "read data out of channel" }, +}; + +void cmd_ctrl_register(void) +{ + commands_cmd_init(&cmd_entry, "ctrl", "Controller commands", + cmd_help, ARRAY_SIZE(cmd_help), cmd_ctrl); + commands_cmd_register(&cmd_entry); +} + +int cmd_ctrl(int argc, char **argv) +{ + if (argc == 2 && STREQ("read", argv[1])) { + uint32_t test = Xil_In32(AMDS_1_BASE_ADDR + AMDS_CH_VALID_REG_OFFSET); + printf("\nValid = 0x%08lX\r\n", test); // should be 0xDEADBEEF + + return CMD_SUCCESS; + } + + if (argc == 4 && STREQ("set", argv[1]) && STREQ("enable", argv[2])) { + + } + + if (argc == 2 && STREQ("init", argv[1])) { + if (task_controller_init() != SUCCESS) { + return CMD_FAILURE; + } + if (pwm_enable() != SUCCESS) { + return CMD_FAILURE; + } + + return CMD_SUCCESS; + } + + if (argc == 2 && STREQ("deinit", argv[1])) { + if (task_controller_deinit() != SUCCESS) { + return CMD_FAILURE; + } + if (pwm_disable() != SUCCESS) { + return CMD_FAILURE; + } + + return CMD_SUCCESS; + } + + if (argc == 3 && STREQ("freq", argv[1])) { + double new_freq = strtod(argv[2], NULL); + + if (task_controller_set_frequency(new_freq) != SUCCESS) { + return CMD_FAILURE; + } + + return CMD_SUCCESS; + } + + if (argc == 3 && STREQ("amplitude", argv[1])) { + double new_amplitude = strtod(argv[2], NULL); + + if (task_controller_set_amplitude(new_amplitude) != SUCCESS) { + return CMD_FAILURE; + } + + return CMD_SUCCESS; + } + + if (argc == 3 && STREQ("print", argv[1]) && STREQ("amds", argv[2])) { + task_controller_get_raw(); + return CMD_SUCCESS; + } + + if (argc == 3 && STREQ("read", argv[1])) { + double channel = strtod(argv[2], NULL); + + if (task_controller_get_data(channel) != SUCCESS) { + return CMD_FAILURE; + } + + return CMD_SUCCESS; + } + + return CMD_INVALID_ARGUMENTS; +} + +#endif // APP_CONTROLLER diff --git a/sdk/app_cpu1/user/usr/controller/cmd/cmd_ctrl.h b/sdk/app_cpu1/user/usr/controller/cmd/cmd_ctrl.h new file mode 100644 index 00000000..6d96d1bd --- /dev/null +++ b/sdk/app_cpu1/user/usr/controller/cmd/cmd_ctrl.h @@ -0,0 +1,7 @@ +#ifndef CMD_CTRL_H +#define CMD_CTRL_H + +void cmd_ctrl_register(void); +int cmd_ctrl(int argc, char **argv); + +#endif // CMD_CTRL_H diff --git a/sdk/app_cpu1/user/usr/controller/task_controller.c b/sdk/app_cpu1/user/usr/controller/task_controller.c new file mode 100644 index 00000000..435a899c --- /dev/null +++ b/sdk/app_cpu1/user/usr/controller/task_controller.c @@ -0,0 +1,154 @@ +#ifdef APP_CONTROLLER + +#include "usr/controller/task_controller.h" +#include "sys/scheduler.h" +#include "drv/pwm.h" +#include "drv/amds.h" +#include + +#define FBC_CURRENT_DEFAULT_GAIN 312 +#define FBC_CURRENT_DEFAULT_OFFSET 2.500351 + +// Scheduler TCB which holds task "context" +static task_control_block_t tcb; + +int task_controller_init(void) +{ + if (scheduler_tcb_is_registered(&tcb)) { + return FAILURE; + } + + // Fill TCB with parameters + scheduler_tcb_init(&tcb, task_controller_callback, + NULL, "ctrl", TASK_CONTROLLER_INTERVAL_USEC); + + // Register task with scheduler + return scheduler_tcb_register(&tcb); +} + +int task_controller_deinit(void) +{ + return scheduler_tcb_unregister(&tcb); +} + +double Ts = 1.0 / (double) TASK_CONTROLLER_UPDATES_PER_SEC; +double theta = 0.0; // [rad] +double omega = 377.0; // [rad/s] +double Do = 0.8; // [--] + +const uint8_t amds_port = 1; +int32_t out_ch_1, out_ch_2, out_ch_3, out_ch_4; +int32_t out_ch_5, out_ch_6, out_ch_7, out_ch_8; + +void task_controller_callback(void *arg) +{ + // Update theta + theta += (Ts * omega); + + // Wrap to 2*pi + theta = fmod(theta, 2.0 * M_PI); + + // Calculate desired duty ratios + double duty_a = 0.5 + Do/2.0 * cos(theta); + double duty_b = 0.5 + Do/2.0 * cos(theta - 2.0*M_PI/3.0); + double duty_c = 0.5 + Do/2.0 * cos(theta - 4.0*M_PI/3.0); + + // Update PWM peripheral in FPGA + pwm_set_duty(0, duty_a); // Set HB1 duty ratio (INV1, PWM1 and PWM2) + pwm_set_duty(1, duty_b); // Set HB2 duty ratio (INV1, PWM3 and PWM4) + pwm_set_duty(2, duty_c); // Set HB3 duty ratio (INV1, PWM5 and PWM6) + + // Check validity of latest data for the AMDS plugged into your GPIO port + uint32_t valid = amds_check_data_validity(amds_port); + + if ((valid << 8) == 0xFFFFFF) { + // 0xFF means the bits for all channels are valid! + // Read in values sampled on the AMDS (plugged into your GPIO port) from all channels: + + amds_get_data(amds_port, AMDS_CH_1, &out_ch_1); + amds_get_data(amds_port, AMDS_CH_2, &out_ch_2); + amds_get_data(amds_port, AMDS_CH_3, &out_ch_3); + amds_get_data(amds_port, AMDS_CH_4, &out_ch_4); + amds_get_data(amds_port, AMDS_CH_5, &out_ch_5); + amds_get_data(amds_port, AMDS_CH_6, &out_ch_6); + amds_get_data(amds_port, AMDS_CH_7, &out_ch_7); + amds_get_data(amds_port, AMDS_CH_8, &out_ch_8); + + // Now, "out" variables contain the sign-extended 16-bit + // sample value for each channel + } +} + +int task_controller_set_frequency(double freq) +{ + omega = freq; + return SUCCESS; +} + +int task_controller_set_amplitude(double amplitude) +{ + int err = FAILURE; + + if (amplitude >= 0.0 && amplitude <= 1.0) { + Do = amplitude; + err = SUCCESS; + } + + return err; +} + +void task_controller_get_raw(void) { + printf("\nRaw AMDS Channel 1: %ld\r\n", out_ch_1); + printf("Raw AMDS Channel 2: %ld\r\n", out_ch_2); + printf("Raw AMDS Channel 3: %ld\r\n", out_ch_3); + printf("Raw AMDS Channel 4: %ld\r\n", out_ch_4); + printf("Raw AMDS Channel 5: %ld\r\n", out_ch_5); + printf("Raw AMDS Channel 6: %ld\r\n", out_ch_6); + printf("Raw AMDS Channel 7: %ld\r\n", out_ch_7); + printf("Raw AMDS Channel 8: %ld\r\n", out_ch_8); +} + + +int task_controller_get_data(int ch) { + + double raw_voltage; + double voltage; + int channel; + + switch (ch) { + case 1: + channel = AMDS_CH_1; + break; + case 2: + channel = AMDS_CH_2; + break; + case 3: + channel = AMDS_CH_3; + break; + case 4: + channel = AMDS_CH_4; + break; + case 5: + channel = AMDS_CH_5; + break; + case 6: + channel = AMDS_CH_6; + break; + case 7: + channel = AMDS_CH_7; + break; + case 8: + channel = AMDS_CH_8; + break; + default: + return FAILURE; + } + + amds_get_voltage(1, channel, AMDS_CURRENT_CARD, &raw_voltage); + amds_convert_voltage(raw_voltage, FBC_CURRENT_DEFAULT_OFFSET, FBC_CURRENT_DEFAULT_GAIN, &voltage); + printf("\nCurrent Sensor Reading: %f\r\n", voltage); + + return SUCCESS; +} + +#endif // APP_CONTROLLER diff --git a/sdk/app_cpu1/user/usr/controller/task_controller.h b/sdk/app_cpu1/user/usr/controller/task_controller.h new file mode 100644 index 00000000..1b1ed229 --- /dev/null +++ b/sdk/app_cpu1/user/usr/controller/task_controller.h @@ -0,0 +1,20 @@ +#ifndef TASK_CONTROLLER_H +#define TASK_CONTROLLER_H + +#include "sys/scheduler.h" + +#define TASK_CONTROLLER_UPDATES_PER_SEC (10000) +#define TASK_CONTROLLER_INTERVAL_USEC (USEC_IN_SEC / TASK_CONTROLLER_UPDATES_PER_SEC) + +int task_controller_init(void); +int task_controller_deinit(void); + +void task_controller_callback(void *arg); + +int task_controller_set_frequency(double freq); +int task_controller_set_amplitude(double amplitude); + +void task_controller_get_raw(void); +int task_controller_get_data(int channel); + +#endif // TASK_CONTROLLER_H diff --git a/sdk/app_cpu1/user/usr/example_controller/app_ex_controller.c b/sdk/app_cpu1/user/usr/example_controller/app_ex_controller.c new file mode 100644 index 00000000..30eab5c5 --- /dev/null +++ b/sdk/app_cpu1/user/usr/example_controller/app_ex_controller.c @@ -0,0 +1,19 @@ + +#ifdef APP_EXAMPLE_CONTROLLER + +#include "usr/controller/app_controller.h" +#include "usr/controller/cmd/cmd_ctrl.h" +#include "drv/timing_manager.h" +#include "drv/gp3io_mux.h" +#include + +void app_ex_controller_init(void) +{ + // register commands + cmd_ctrl_register(); + + // Initialize controller with system + task_ex_controller_init(); +} + +#endif // APP_EXAMPLE_CONTROLLER diff --git a/sdk/app_cpu1/user/usr/example_controller/app_ex_controller.h b/sdk/app_cpu1/user/usr/example_controller/app_ex_controller.h new file mode 100644 index 00000000..217007ea --- /dev/null +++ b/sdk/app_cpu1/user/usr/example_controller/app_ex_controller.h @@ -0,0 +1,6 @@ +#ifndef APP_EXAMPLE_CONTROLLER_H +#define APP_EXAMPLE_CONTROLLER_H + +void app_ex_controller_init(void); + +#endif // APP_EXAMPLE_CONTROLLER_H diff --git a/sdk/app_cpu1/user/usr/example_controller/simulink/ert_main.c b/sdk/app_cpu1/user/usr/example_controller/simulink/ert_main.c new file mode 100644 index 00000000..da0e6cf9 --- /dev/null +++ b/sdk/app_cpu1/user/usr/example_controller/simulink/ert_main.c @@ -0,0 +1,108 @@ +///* +// * Academic License - for use in teaching, academic research, and meeting +// * course requirements at degree granting institutions only. Not for +// * government, commercial, or other organizational use. +// * +// * File: ert_main.c +// * +// * Code generated for Simulink model 'exampleController'. +// * +// * Model version : 9.1 +// * Simulink Coder version : 9.5 (R2021a) 14-Nov-2020 +// * C/C++ source code generated on : Sat May 8 10:51:56 2021 +// * +// * Target selection: ert.tlc +// * Embedded hardware selection: Intel->x86-64 (Windows64) +// * Code generation objectives: Unspecified +// * Validation result: Not run +// */ +// +//#include +//#include /* This ert_main.c example uses printf/fflush */ +//#include "exampleController.h" /* Model's header file */ +//#include "rtwtypes.h" +// +///* +// * Associating rt_OneStep with a real-time clock or interrupt service routine +// * is what makes the generated code "real-time". The function rt_OneStep is +// * always associated with the base rate of the model. Subrates are managed +// * by the base rate from inside the generated code. Enabling/disabling +// * interrupts and floating point context switches are target specific. This +// * example code indicates where these should take place relative to executing +// * the generated code step function. Overrun behavior should be tailored to +// * your application needs. This example simply sets an error status in the +// * real-time model and returns from rt_OneStep. +// */ +//void rt_OneStep(void); +//void rt_OneStep(void) +//{ +// static boolean_T OverrunFlag = false; +// +// /* Disable interrupts here */ +// +// /* Check for overrun */ +// if (OverrunFlag) { +// rtmSetErrorStatus(exampleController_M, "Overrun"); +// return; +// } +// +// OverrunFlag = true; +// +// /* Save FPU context here (if necessary) */ +// /* Re-enable timer or interrupt here */ +// /* Set model inputs here */ +// +// /* Step the model */ +// exampleController_step(); +// +// /* Get model outputs here */ +// +// /* Indicate task complete */ +// OverrunFlag = false; +// +// /* Disable interrupts here */ +// /* Restore FPU context here (if necessary) */ +// /* Enable interrupts here */ +//} +// +///* +// * The example "main" function illustrates what is required by your +// * application code to initialize, execute, and terminate the generated code. +// * Attaching rt_OneStep to a real-time clock is target specific. This example +// * illustrates how you do this relative to initializing the model. +// */ +//int_T main(int_T argc, const char *argv[]) +//{ +// /* Unused arguments */ +// (void)(argc); +// (void)(argv); +// +// /* Initialize model */ +// exampleController_initialize(); +// +// /* Attach rt_OneStep to a timer or interrupt service routine with +// * period 1.0E-6 seconds (the model's base sample time) here. The +// * call syntax for rt_OneStep is +// * +// * rt_OneStep(); +// */ +// printf("Warning: The simulation will run forever. " +// "Generated ERT main won't simulate model step behavior. " +// "To change this behavior select the 'MAT-file logging' option.\n"); +// fflush((NULL)); +// while (rtmGetErrorStatus(exampleController_M) == (NULL)) { +// /* Perform other application tasks here */ +// } +// +// /* Disable rt_OneStep() here */ +// +// /* Terminate model */ +// exampleController_terminate(); +// return 0; +//} +// +///* +// * File trailer for generated code. +// * +// * [EOF] +// */ diff --git a/sdk/app_cpu1/user/usr/example_controller/simulink/exampleController.c b/sdk/app_cpu1/user/usr/example_controller/simulink/exampleController.c new file mode 100644 index 00000000..3e0ab76c --- /dev/null +++ b/sdk/app_cpu1/user/usr/example_controller/simulink/exampleController.c @@ -0,0 +1,73 @@ +/* + * Academic License - for use in teaching, academic research, and meeting + * course requirements at degree granting institutions only. Not for + * government, commercial, or other organizational use. + * + * File: exampleController.c + * + * Code generated for Simulink model 'exampleController'. + * + * Model version : 9.1 + * Simulink Coder version : 9.5 (R2021a) 14-Nov-2020 + * C/C++ source code generated on : Sat May 8 10:51:56 2021 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#include "exampleController.h" +#include "exampleController_private.h" + +/* External inputs (root inport signals with default storage) */ +ExtU_exampleController_T exampleController_U; + +/* External outputs (root outports fed by signals with default storage) */ +ExtY_exampleController_T exampleController_Y; + +/* Real-time model */ +static RT_MODEL_exampleController_T exampleController_M_; +RT_MODEL_exampleController_T *const exampleController_M = &exampleController_M_; + +/* Model step function */ +void exampleController_step(void) +{ + /* Gain: '/Gain' incorporates: + * Inport: '/Input' + */ + exampleController_Y.Output = 0.1 * exampleController_U.Input; + + /* Saturate: '/Sat' */ + if (exampleController_Y.Output > 0.9) { + /* Gain: '/Gain' incorporates: + * Outport: '/Output' + */ + exampleController_Y.Output = 0.9; + } else if (exampleController_Y.Output < 0.0) { + /* Gain: '/Gain' incorporates: + * Outport: '/Output' + */ + exampleController_Y.Output = 0.0; + } + + /* End of Saturate: '/Sat' */ +} + +/* Model initialize function */ +void exampleController_initialize(void) +{ + /* (no initialization code required) */ +} + +/* Model terminate function */ +void exampleController_terminate(void) +{ + /* (no terminate code required) */ +} + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/sdk/app_cpu1/user/usr/example_controller/simulink/exampleController.h b/sdk/app_cpu1/user/usr/example_controller/simulink/exampleController.h new file mode 100644 index 00000000..d145b8d3 --- /dev/null +++ b/sdk/app_cpu1/user/usr/example_controller/simulink/exampleController.h @@ -0,0 +1,89 @@ +/* + * Academic License - for use in teaching, academic research, and meeting + * course requirements at degree granting institutions only. Not for + * government, commercial, or other organizational use. + * + * File: exampleController.h + * + * Code generated for Simulink model 'exampleController'. + * + * Model version : 9.1 + * Simulink Coder version : 9.5 (R2021a) 14-Nov-2020 + * C/C++ source code generated on : Sat May 8 10:51:56 2021 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_exampleController_h_ +#define RTW_HEADER_exampleController_h_ +#ifndef exampleController_COMMON_INCLUDES_ +#define exampleController_COMMON_INCLUDES_ +#include "rtwtypes.h" +#endif /* exampleController_COMMON_INCLUDES_ */ + +#include "exampleController_types.h" + +/* Macros for accessing real-time model data structure */ +#ifndef rtmGetErrorStatus +#define rtmGetErrorStatus(rtm) ((rtm)->errorStatus) +#endif + +#ifndef rtmSetErrorStatus +#define rtmSetErrorStatus(rtm, val) ((rtm)->errorStatus = (val)) +#endif + +/* External inputs (root inport signals with default storage) */ +typedef struct { + real_T Input; /* '/Input' */ +} ExtU_exampleController_T; + +/* External outputs (root outports fed by signals with default storage) */ +typedef struct { + real_T Output; /* '/Output' */ +} ExtY_exampleController_T; + +/* Real-time Model Data Structure */ +struct tag_RTM_exampleController_T { + const char_T * volatile errorStatus; +}; + +/* External inputs (root inport signals with default storage) */ +extern ExtU_exampleController_T exampleController_U; + +/* External outputs (root outports fed by signals with default storage) */ +extern ExtY_exampleController_T exampleController_Y; + +/* Model entry point functions */ +extern void exampleController_initialize(void); +extern void exampleController_step(void); +extern void exampleController_terminate(void); + +/* Real-time Model object */ +extern RT_MODEL_exampleController_T *const exampleController_M; + +/*- + * The generated code includes comments that allow you to trace directly + * back to the appropriate location in the model. The basic format + * is /block_name, where system is the system number (uniquely + * assigned by Simulink) and block_name is the name of the block. + * + * Use the MATLAB hilite_system command to trace the generated code back + * to the model. For example, + * + * hilite_system('') - opens system 3 + * hilite_system('/Kp') - opens and selects block Kp which resides in S3 + * + * Here is the system hierarchy for this model + * + * '' : 'exampleController' + */ +#endif /* RTW_HEADER_exampleController_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/sdk/app_cpu1/user/usr/example_controller/simulink/exampleController_private.h b/sdk/app_cpu1/user/usr/example_controller/simulink/exampleController_private.h new file mode 100644 index 00000000..fa0438ed --- /dev/null +++ b/sdk/app_cpu1/user/usr/example_controller/simulink/exampleController_private.h @@ -0,0 +1,29 @@ +/* + * Academic License - for use in teaching, academic research, and meeting + * course requirements at degree granting institutions only. Not for + * government, commercial, or other organizational use. + * + * File: exampleController_private.h + * + * Code generated for Simulink model 'exampleController'. + * + * Model version : 9.1 + * Simulink Coder version : 9.5 (R2021a) 14-Nov-2020 + * C/C++ source code generated on : Sat May 8 10:51:56 2021 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_exampleController_private_h_ +#define RTW_HEADER_exampleController_private_h_ +#include "rtwtypes.h" +#endif /* RTW_HEADER_exampleController_private_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/sdk/app_cpu1/user/usr/example_controller/simulink/exampleController_types.h b/sdk/app_cpu1/user/usr/example_controller/simulink/exampleController_types.h new file mode 100644 index 00000000..e320c28f --- /dev/null +++ b/sdk/app_cpu1/user/usr/example_controller/simulink/exampleController_types.h @@ -0,0 +1,34 @@ +/* + * Academic License - for use in teaching, academic research, and meeting + * course requirements at degree granting institutions only. Not for + * government, commercial, or other organizational use. + * + * File: exampleController_types.h + * + * Code generated for Simulink model 'exampleController'. + * + * Model version : 9.1 + * Simulink Coder version : 9.5 (R2021a) 14-Nov-2020 + * C/C++ source code generated on : Sat May 8 10:51:56 2021 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTW_HEADER_exampleController_types_h_ +#define RTW_HEADER_exampleController_types_h_ + +/* Model Code Variants */ + +/* Forward declaration for rtModel */ +typedef struct tag_RTM_exampleController_T RT_MODEL_exampleController_T; + +#endif /* RTW_HEADER_exampleController_types_h_ */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/sdk/app_cpu1/user/usr/example_controller/simulink/rtwtypes.h b/sdk/app_cpu1/user/usr/example_controller/simulink/rtwtypes.h new file mode 100644 index 00000000..f8ca4e4c --- /dev/null +++ b/sdk/app_cpu1/user/usr/example_controller/simulink/rtwtypes.h @@ -0,0 +1,160 @@ +/* + * Academic License - for use in teaching, academic research, and meeting + * course requirements at degree granting institutions only. Not for + * government, commercial, or other organizational use. + * + * File: rtwtypes.h + * + * Code generated for Simulink model 'exampleController'. + * + * Model version : 9.1 + * Simulink Coder version : 9.5 (R2021a) 14-Nov-2020 + * C/C++ source code generated on : Sat May 8 10:51:56 2021 + * + * Target selection: ert.tlc + * Embedded hardware selection: Intel->x86-64 (Windows64) + * Code generation objectives: Unspecified + * Validation result: Not run + */ + +#ifndef RTWTYPES_H +#define RTWTYPES_H + +/* Logical type definitions */ +#if (!defined(__cplusplus)) +#ifndef false +#define false (0U) +#endif + +#ifndef true +#define true (1U) +#endif +#endif + +/*=======================================================================* + * Target hardware information + * Device type: Intel->x86-64 (Windows64) + * Number of bits: char: 8 short: 16 int: 32 + * long: 32 + * native word size: 64 + * Byte ordering: LittleEndian + * Signed integer division rounds to: Zero + * Shift right on a signed integer as arithmetic shift: on + *=======================================================================*/ + +/*=======================================================================* + * Fixed width word size data types: * + * int8_T, int16_T, int32_T - signed 8, 16, or 32 bit integers * + * uint8_T, uint16_T, uint32_T - unsigned 8, 16, or 32 bit integers * + * real32_T, real64_T - 32 and 64 bit floating point numbers * + *=======================================================================*/ +typedef signed char int8_T; +typedef unsigned char uint8_T; +typedef short int16_T; +typedef unsigned short uint16_T; +typedef int int32_T; +typedef unsigned int uint32_T; +typedef float real32_T; +typedef double real64_T; + +/*===========================================================================* + * Generic type definitions: boolean_T, char_T, byte_T, int_T, uint_T, * + * real_T, time_T, ulong_T. * + *===========================================================================*/ +typedef double real_T; +typedef double time_T; +typedef unsigned char boolean_T; +typedef int int_T; +typedef unsigned int uint_T; +typedef unsigned long ulong_T; +typedef char char_T; +typedef unsigned char uchar_T; +typedef char_T byte_T; + +/*===========================================================================* + * Complex number type definitions * + *===========================================================================*/ +#define CREAL_T + +typedef struct { + real32_T re; + real32_T im; +} creal32_T; + +typedef struct { + real64_T re; + real64_T im; +} creal64_T; + +typedef struct { + real_T re; + real_T im; +} creal_T; + +#define CINT8_T + +typedef struct { + int8_T re; + int8_T im; +} cint8_T; + +#define CUINT8_T + +typedef struct { + uint8_T re; + uint8_T im; +} cuint8_T; + +#define CINT16_T + +typedef struct { + int16_T re; + int16_T im; +} cint16_T; + +#define CUINT16_T + +typedef struct { + uint16_T re; + uint16_T im; +} cuint16_T; + +#define CINT32_T + +typedef struct { + int32_T re; + int32_T im; +} cint32_T; + +#define CUINT32_T + +typedef struct { + uint32_T re; + uint32_T im; +} cuint32_T; + +/*=======================================================================* + * Min and Max: * + * int8_T, int16_T, int32_T - signed 8, 16, or 32 bit integers * + * uint8_T, uint16_T, uint32_T - unsigned 8, 16, or 32 bit integers * + *=======================================================================*/ +#define MAX_int8_T ((int8_T)(127)) +#define MIN_int8_T ((int8_T)(-128)) +#define MAX_uint8_T ((uint8_T)(255U)) +#define MAX_int16_T ((int16_T)(32767)) +#define MIN_int16_T ((int16_T)(-32768)) +#define MAX_uint16_T ((uint16_T)(65535U)) +#define MAX_int32_T ((int32_T)(2147483647)) +#define MIN_int32_T ((int32_T)(-2147483647-1)) +#define MAX_uint32_T ((uint32_T)(0xFFFFFFFFU)) + +/* Block D-Work pointer type */ +typedef void * pointer_T; + +#endif /* RTWTYPES_H */ + +/* + * File trailer for generated code. + * + * [EOF] + */ diff --git a/sdk/app_cpu1/user/usr/example_controller/task_ex_controller.c b/sdk/app_cpu1/user/usr/example_controller/task_ex_controller.c new file mode 100644 index 00000000..2d2ddf9a --- /dev/null +++ b/sdk/app_cpu1/user/usr/example_controller/task_ex_controller.c @@ -0,0 +1,55 @@ + +#ifdef APP_EXAMPLE_CONTROLLER + +#include +#include "sys/scheduler.h" +#include "sys/commands.h" +#include +#include "simulink/exampleController.h" /* Model's header file */ +#include "simulink/rtwtypes.h" + +// Scheduler TCB which holds task "context" +static task_control_block_t tcb; + +int task_ex_controller_init(void) +{ + if (scheduler_tcb_is_registered(&tcb)) { + return FAILURE; + } + + /* Initialize model */ + exampleController_initialize(); + + // Fill TCB with parameters + scheduler_tcb_init(&tcb, task_ex_controller_callback, + NULL, "exctrl", TASK_EX_CONTROLLER_INTERVAL_USEC); + + // Register task with scheduler + return scheduler_tcb_register(&tcb); +} + +int task_ex_controller_deinit(void) +{ + return scheduler_tcb_unregister(&tcb); +} + +double out = 0; + +void task_ex_controller_callback(void *arg) +{ + /* Attach rt_OneStep to a timer or interrupt service routine with + * period 1.0E-6 seconds (the model's base sample time) here. + */ + + /* Set model inputs here */ + exampleController_U.Input = (real_T) 5.0; + + /* Step the model */ + exampleController_step(); + + + /* Get model outputs here */ + out = (double) exampleController_Y.Output; +} + +#endif // APP_EXAMPLE_CONTROLLER diff --git a/sdk/app_cpu1/user/usr/example_controller/task_ex_controller.h b/sdk/app_cpu1/user/usr/example_controller/task_ex_controller.h new file mode 100644 index 00000000..628081a8 --- /dev/null +++ b/sdk/app_cpu1/user/usr/example_controller/task_ex_controller.h @@ -0,0 +1,14 @@ +#ifndef TASK_EXAMPLE_CONTROLLER_H +#define TASK_EXAMPLE_CONTROLLER_H + +#include "sys/scheduler.h" + +#define TASK_EX_CONTROLLER_UPDATES_PER_SEC (1000000) +#define TASK_EX_CONTROLLER_INTERVAL_USEC (USEC_IN_SEC / TASK_EX_CONTROLLER_UPDATES_PER_SEC) + +int task_ex_controller_init(void); +int task_ex_controller_deinit(void); + +void task_ex_controller_callback(void *arg); + +#endif // TASK_EXAMPLE_CONTROLLER_H diff --git a/sdk/app_cpu1/user/usr/user_apps.c b/sdk/app_cpu1/user/usr/user_apps.c index d87a85f4..8f4bf915 100644 --- a/sdk/app_cpu1/user/usr/user_apps.c +++ b/sdk/app_cpu1/user/usr/user_apps.c @@ -16,6 +16,14 @@ #include "usr/blink/app_blink.h" #endif +#ifdef APP_CONTROLLER +#include "usr/controller/app_controller.h" +#endif + +#ifdef APP_EXAMPLE_CONTROLLER +#include "usr/example_controller/app_ex_controller.h" +#endif + #ifdef APP_BETA_LABS #include "usr/beta_labs/app_beta_labs.h" #endif @@ -38,6 +46,14 @@ void user_apps_init(void) app_blink_init(); #endif +#ifdef APP_CONTROLLER + app_controller_init(); +#endif + +#ifdef APP_EXAMPLE_CONTROLLER + app_ex_controller_init(); +#endif + #ifdef APP_BETA_LABS app_beta_labs_init(); #endif diff --git a/sdk/app_cpu1/user/usr/user_config.h b/sdk/app_cpu1/user/usr/user_config.h index e70ed6a0..0c20e08c 100644 --- a/sdk/app_cpu1/user/usr/user_config.h +++ b/sdk/app_cpu1/user/usr/user_config.h @@ -18,7 +18,7 @@ // Enforce time quantum limits // set to 1 for enabled, 0 for disabled -#define USER_CONFIG_ENABLE_TIME_QUANTUM_CHECKING (1) +#define USER_CONFIG_ENABLE_TIME_QUANTUM_CHECKING (0) // Enable task statistic collection by default // NOTE: The user can still go and enable the stats themselves if this is set to 0! @@ -35,11 +35,11 @@ // Override default number of available logging variables // when defined, this takes precedence over system default of 32 -// #define USER_CONFIG_LOGGING_MAX_NUM_VARIABLES (150) +//#define USER_CONFIG_LOGGING_MAX_NUM_VARIABLES (150) // Override default logging sample depth per variable // when defined, this takes precedence over system default of 100k -// #define USER_CONFIG_LOGGING_SAMPLE_DEPTH_PER_VARIABLE (50000) +//#define USER_CONFIG_LOGGING_SAMPLE_DEPTH_PER_VARIABLE (50000) // Enable injection functionality // set to 1 for enabled, 0 for disabled @@ -47,7 +47,7 @@ // Enable support for AMDS (Advanced Motor Drive Sensing) platform // set to 1 for enabled, 0 for disabled -#define USER_CONFIG_ENABLE_AMDS_SUPPORT (0) +#define USER_CONFIG_ENABLE_AMDS_SUPPORT (1) // Scheduler Interval Tolerance Override // as of AMDC Firmware v1.3, all timing variables for tasks (runtime, loop time, etc) @@ -55,6 +55,6 @@ // that require a margin of tolerance. sometimes non-default PWM frequency and/or // timing manager ratios may necessitate un-commenting the following define to override // the default tolerance in common/sys/scheduler.h -// #define USER_CONFIG_SCHEDULER_INTERVAL_TOLERANCE_USEC (0.15) +//#define USER_CONFIG_SCHEDULER_INTERVAL_TOLERANCE_USEC (0.15) #endif // USER_CONFIG_H