diff --git a/Mainboard/Firmware/motherboard_v1/Core/Inc/drv_uart.h b/Mainboard/Firmware/motherboard_v1/Core/Inc/drv_uart.h index 976bcc4..5470590 100644 --- a/Mainboard/Firmware/motherboard_v1/Core/Inc/drv_uart.h +++ b/Mainboard/Firmware/motherboard_v1/Core/Inc/drv_uart.h @@ -10,18 +10,19 @@ void drv_uart_init(void); extern UART_HandleTypeDef huart2; extern UART_HandleTypeDef huart3; -// 16-byte accumulator -// Layout: [UART4 pkt0-3 | UART5 pkt0-3][UART4 pkt4-7 | UART5 pkt4-7] -extern volatile uint16_t latest_valid_amds_samples[2][8]; -extern volatile bool amds_samples_ready[2]; -extern volatile uint8_t uart4_amds_sample_count; -extern volatile uint8_t uart5_amds_sample_count; +extern UART_HandleTypeDef huart4; +extern UART_HandleTypeDef huart5; +extern DMA_HandleTypeDef hdma_usart2_tx; +extern DMA_HandleTypeDef hdma_usart3_tx; + +extern DMA_HandleTypeDef hdma_uart4_rx; +extern DMA_HandleTypeDef hdma_uart5_rx; typedef enum { STATE_IDLE, STATE_GOT_HEADER, - STATE_GOT_BYTE1 + STATE_GOT_MSB } rx_state_t; typedef struct { @@ -38,18 +39,24 @@ extern uart_rx_tracker_t tracker5; extern uint8_t UART4_DMA_Pool[AMDS_RX_BUF_SIZE]; extern uint8_t UART5_DMA_Pool[AMDS_RX_BUF_SIZE]; -// Define large buffers for outgoing data -#define TX_BUF_SIZE 512 -extern uint8_t usart2_tx_ring[TX_BUF_SIZE]; -extern uint8_t usart3_tx_ring[TX_BUF_SIZE]; - -extern uint32_t usart2_tx_write_idx; -extern uint32_t usart3_tx_write_idx; +extern volatile uint8_t uart2_dma_queue[AMDS_RX_BUF_SIZE]; +extern volatile uint8_t uart3_dma_queue[AMDS_RX_BUF_SIZE]; +extern volatile uint8_t uart2_dma_buffer[AMDS_RX_BUF_SIZE]; +extern volatile uint8_t uart3_dma_buffer[AMDS_RX_BUF_SIZE]; +// Queue tracking indices +extern volatile uint16_t u2_q_head; +extern volatile uint16_t u2_q_tail; +extern volatile uint16_t u3_q_head; +extern volatile uint16_t u3_q_tail; void process_uart_fifo(uint8_t *pool, uart_rx_tracker_t *track, uint8_t uart_id); +void dma_queue(uint8_t uart_id, uint8_t *data, uint8_t len); + + +void process_single_byte(uint8_t *pool, uart_rx_tracker_t *track, USART_TypeDef *target_uart); +void process_routing(void); -void dma_send(uint8_t uart_id, uint8_t *data, uint8_t len); static inline void drv_uart_putc_fast(USART_TypeDef *uart, uint8_t data) { @@ -62,17 +69,6 @@ static inline void drv_uart_putc_fast(USART_TypeDef *uart, uint8_t data) uart->TDR = data; } -static inline void drv_uart_putc_dma(USART_TypeDef *uart, uint8_t data) -{ - if (uart == USART2) { - usart2_tx_ring[usart2_tx_write_idx] = data; - usart2_tx_write_idx = (usart2_tx_write_idx + 1) % TX_BUF_SIZE; - } else if (uart == USART3) { - usart3_tx_ring[usart3_tx_write_idx] = data; - usart3_tx_write_idx = (usart3_tx_write_idx + 1) % TX_BUF_SIZE; - } -} - static inline void drv_uart_wait_TC(USART_TypeDef *uart) { // After done sending characters, must wait for TC flag!! @@ -92,4 +88,36 @@ static inline void drv_uart_send_fast(USART_TypeDef *uart, uint8_t *data, uint16 drv_uart_wait_TC(uart); } +static inline void drv_uart_dma_send_fast(UART_HandleTypeDef *huart, uint8_t *data, uint16_t len) +{ + DMA_Stream_TypeDef *dma = (DMA_Stream_TypeDef *)huart->hdmatx->Instance; + + // 1. Disable the DMA channel + dma->CR &= ~DMA_SxCR_EN; + + // 2. CRITICAL FIX: Wait for the hardware to actually halt. + // Writing to address registers while EN is still high causes a silent failure. + while ((dma->CR & DMA_SxCR_EN) != 0) { + asm("nop"); + } + + // 3. Clear the DMA Transfer Complete and Half Transfer flags + __HAL_DMA_CLEAR_FLAG(huart->hdmatx, __HAL_DMA_GET_TC_FLAG_INDEX(huart->hdmatx)); + __HAL_DMA_CLEAR_FLAG(huart->hdmatx, __HAL_DMA_GET_HT_FLAG_INDEX(huart->hdmatx)); + + // 4. CRITICAL FIX: Tell the DMA exactly *where* to push the bytes. + // It must point directly to the UART's Transmit Data Register. + dma->PAR = (uint32_t)&huart->Instance->TDR; + + // 5. Load the Memory Address and Length registers + dma->M0AR = (uint32_t)data; + dma->NDTR = len; + + // 6. Clear UART Transmission Complete flag to ensure it's ready for a fresh burst + huart->Instance->ICR = USART_ICR_TCCF; + + // 7. Fire! + dma->CR |= DMA_SxCR_EN; +} + #endif // DRV_UART_H diff --git a/Mainboard/Firmware/motherboard_v1/Core/Inc/tx.h b/Mainboard/Firmware/motherboard_v1/Core/Inc/tx.h index a55e8c8..e4ee904 100644 --- a/Mainboard/Firmware/motherboard_v1/Core/Inc/tx.h +++ b/Mainboard/Firmware/motherboard_v1/Core/Inc/tx.h @@ -1,6 +1,32 @@ #ifndef TX_H #define TX_H +#include "adc.h" +#include "drv_uart.h" + +#include "platform.h" +#include +#include + +#define NUM_SETS 3 // 0 = local data, 1 = AMDS 1, 2 = AMDS 2 +#define PACKETS_PER_SET 8 + +typedef struct { + uint8_t header; + uint8_t msb; + uint8_t lsb; +} packet_t; + +// Global state arrays +extern volatile packet_t tx_packets[NUM_SETS * PACKETS_PER_SET]; +extern volatile bool packet_ready[NUM_SETS * PACKETS_PER_SET]; +extern bool packet_sent[NUM_SETS * PACKETS_PER_SET]; + +// Flag set by EXTI Sync Interrupt +extern volatile bool sync_event_flag; + +void process_transmissions(void); + void transmit_samples(void); #endif // TX_H diff --git a/Mainboard/Firmware/motherboard_v1/Core/Src/adc.c b/Mainboard/Firmware/motherboard_v1/Core/Src/adc.c index cff541a..db29d3f 100644 --- a/Mainboard/Firmware/motherboard_v1/Core/Src/adc.c +++ b/Mainboard/Firmware/motherboard_v1/Core/Src/adc.c @@ -179,26 +179,30 @@ static void adc_sample_all_daughtercards(uint16_t *sample_data_out) // this ISR, all the motherboard ADCs should be sampled. void EXTI3_IRQHandler(void) { - // Perform the actual SPI transactions + // alert daisy chained AMDSs to begin converting GPIO_TOGGLE_PIN(GPIOD, GPIO_PIN_1); + // Perform the actual SPI transactions uint16_t new_data[8] = { 0 }; adc_sample_all_daughtercards(new_data); - // Copy data into write buffer destination - volatile uint16_t *dest = latest_valid_adc_data; - - // Unrolled loop for speed - dest[0] = new_data[0]; - dest[1] = new_data[1]; - dest[2] = new_data[2]; - dest[3] = new_data[3]; - dest[4] = new_data[4]; - dest[5] = new_data[5]; - dest[6] = new_data[6]; - dest[7] = new_data[7]; - - // Call the function in tx.c to transmit the sampled data back to the AMDC - transmit_samples(); + for (int i = 0; i < 4; i++) { + uint8_t header = 0x90 | i; + + // Pack UART2 data (Channels 0-3) + drv_uart_putc_fast(USART2, header); + drv_uart_putc_fast(USART3, header); + + // Send ADC sample data MSBs + drv_uart_putc_fast(USART2, (uint8_t)(new_data[i] >> 8)); + drv_uart_putc_fast(USART3, (uint8_t)(new_data[i + 4] >> 8)); + + // Send ADC sample data LSBs + drv_uart_putc_fast(USART2, (uint8_t)(new_data[i] & 0xFF)); + drv_uart_putc_fast(USART3, (uint8_t)(new_data[i + 4] & 0xFF)); + } + + drv_uart_wait_TC(USART2); + drv_uart_wait_TC(USART3); // Clear all pending IRQs for ADC conversions at the // end of this ISR so that the system realigns the diff --git a/Mainboard/Firmware/motherboard_v1/Core/Src/drv_uart.c b/Mainboard/Firmware/motherboard_v1/Core/Src/drv_uart.c index 7f10763..cb668a8 100644 --- a/Mainboard/Firmware/motherboard_v1/Core/Src/drv_uart.c +++ b/Mainboard/Firmware/motherboard_v1/Core/Src/drv_uart.c @@ -1,4 +1,5 @@ #include "drv_uart.h" +#include "tx.h" #include "defines.h" #include "drv_clock.h" #include "platform.h" @@ -9,31 +10,14 @@ static void MX_USART_UART_Init(UART_HandleTypeDef *huart, USART_TypeDef *handle) UART_HandleTypeDef huart2; UART_HandleTypeDef huart3; -static DMA_HandleTypeDef hdma_usart2_tx; -static DMA_HandleTypeDef hdma_usart3_tx; +DMA_HandleTypeDef hdma_usart2_tx; +DMA_HandleTypeDef hdma_usart3_tx; -static UART_HandleTypeDef huart4; -static UART_HandleTypeDef huart5; - -static DMA_HandleTypeDef hdma_uart4_rx; -static DMA_HandleTypeDef hdma_uart5_rx; - -uint8_t usart2_tx_ring[TX_BUF_SIZE]; -uint8_t usart3_tx_ring[TX_BUF_SIZE]; - -uint32_t usart2_tx_write_idx = 0; -uint32_t usart3_tx_write_idx = 0; - -// 3-byte packet buffers for each UART -#define PACKET_SIZE 3 -#define PACKETS_PER_UART 4 -#define TOTAL_PACKETS (PACKETS_PER_UART * 2) // 8 packets, 24 bytes total - -//static uint8_t uart4_packet_count = 0; -//static uint8_t uart5_packet_count = 0; -volatile uint8_t uart4_amds_sample_count = 0; -volatile uint8_t uart5_amds_sample_count = 0; +UART_HandleTypeDef huart4; +UART_HandleTypeDef huart5; +DMA_HandleTypeDef hdma_uart4_rx; +DMA_HandleTypeDef hdma_uart5_rx; uart_rx_tracker_t tracker4 = {0}; uart_rx_tracker_t tracker5 = {0}; @@ -41,16 +25,20 @@ uart_rx_tracker_t tracker5 = {0}; uint8_t UART4_DMA_Pool[AMDS_RX_BUF_SIZE]; uint8_t UART5_DMA_Pool[AMDS_RX_BUF_SIZE]; +volatile uint8_t uart2_dma_queue[AMDS_RX_BUF_SIZE]; +volatile uint8_t uart3_dma_queue[AMDS_RX_BUF_SIZE]; +volatile uint8_t uart2_dma_buffer[AMDS_RX_BUF_SIZE]; +volatile uint8_t uart3_dma_buffer[AMDS_RX_BUF_SIZE]; + +volatile uint16_t u2_q_head = 0; +volatile uint16_t u2_q_tail = 0; +volatile uint16_t u3_q_head = 0; +volatile uint16_t u3_q_tail = 0; + void process_uart_fifo(uint8_t *pool, uart_rx_tracker_t *track, uint8_t uart_id) { // Calculate current DMA write position (NDTR counts down) - UART_HandleTypeDef *huart; - if (uart_id == 4) { - huart = &huart4; - } else { - huart = &huart5; - } - - uint32_t dma_write_ptr = AMDS_RX_BUF_SIZE - __HAL_DMA_GET_COUNTER(huart->hdmarx); + UART_HandleTypeDef *huart = (uart_id == 4) ? &huart4 : &huart5; + uint32_t dma_write_ptr = AMDS_RX_BUF_SIZE - __HAL_DMA_GET_COUNTER(huart->hdmarx); while (track->read_index != dma_write_ptr) { uint8_t byte = pool[track->read_index]; @@ -67,88 +55,100 @@ void process_uart_fifo(uint8_t *pool, uart_rx_tracker_t *track, uint8_t uart_id) case STATE_GOT_HEADER: track->data[0] = byte; - track->state = STATE_GOT_BYTE1; + track->state = STATE_GOT_MSB; break; - case STATE_GOT_BYTE1: + case STATE_GOT_MSB: track->data[1] = byte; - // Packet Complete: Reconstruct 16-bit value - uint16_t value = ((uint16_t)track->data[0] << 8) | track->data[1]; + // --- CUT-THROUGH TRANSMISSION --- + // Determine our target hardware register + USART_TypeDef *target_uart = (uart_id == 4) ? USART2 : USART3; - // 1. Calculate the absolute global channel index (e.g., 0 to 23) - uint8_t base_index = track->header & 0x03; - uint8_t sample_set = (track->header & 0x0C) >> 2; + // Fire the 3 bytes instantly + drv_uart_putc_fast(target_uart, track->header + 4); + drv_uart_putc_fast(target_uart, track->data[0]); + drv_uart_putc_fast(target_uart, track->data[1]); - // This gives a flat number from 0 up to 23 regardless of which UART it came from - uint8_t global_index = base_index + (uart_id == 5 ? 4 : 0) + (sample_set * 8); + track->state = STATE_IDLE; + break; + } + } +} - // 2. Map the global index to your desired 2D array structure - // Assuming you want exactly 12 packets per bank (0-11 in bank 0, 12-23 in bank 1) - uint8_t bank = (global_index < 12) ? 0 : 1; - uint8_t local_index = (global_index < 12) ? global_index : (global_index - 12); - // 3. Store the value logically rather than physically - latest_valid_amds_samples[bank][local_index] = value; +void process_single_byte(uint8_t *pool, uart_rx_tracker_t *track, USART_TypeDef *target_uart) { + uint8_t byte = pool[track->read_index]; + track->read_index = (track->read_index + 1) % AMDS_RX_BUF_SIZE; - // 4. Update the ready flag for the specific bank - amds_samples_ready[bank] = true; + switch (track->state) { + case STATE_IDLE: + // Look for any valid header (0x90, 0x94, 0x98 ranges) + if ((byte & 0xF0) == 0x90) { + track->header = byte; + track->state = STATE_GOT_HEADER; + drv_uart_putc_fast(target_uart, track->header + 4); + } + break; - track->state = STATE_IDLE; - break; + case STATE_GOT_HEADER: + track->data[0] = byte; + track->state = STATE_GOT_MSB; + break; + + case STATE_GOT_MSB: + track->data[1] = byte; + + // --- CUT-THROUGH TRANSMISSION --- + // The exact microsecond the packet is complete, blast it out + drv_uart_putc_fast(target_uart, track->data[0]); + drv_uart_putc_fast(target_uart, track->data[1]); + + track->state = STATE_IDLE; + break; + } +} + +void process_routing(void) { + // Get the current write head for both DMA channels + uint32_t dma_ptr4 = AMDS_RX_BUF_SIZE - __HAL_DMA_GET_COUNTER(huart4.hdmarx); + uint32_t dma_ptr5 = AMDS_RX_BUF_SIZE - __HAL_DMA_GET_COUNTER(huart5.hdmarx); + + // Loop as long as EITHER buffer has unread data + while ((tracker4.read_index != dma_ptr4) || (tracker5.read_index != dma_ptr5)) { + + // Process exactly ONE byte for UART4 + if (tracker4.read_index != dma_ptr4) { + process_single_byte(UART4_DMA_Pool, &tracker4, USART2); + } + + // Process exactly ONE byte for UART5 + if (tracker5.read_index != dma_ptr5) { + process_single_byte(UART5_DMA_Pool, &tracker5, USART3); } + + // Re-read the DMA counters at the end of the loop in case + // new bytes physically arrived while we were parsing the last ones! + dma_ptr4 = AMDS_RX_BUF_SIZE - __HAL_DMA_GET_COUNTER(huart4.hdmarx); + dma_ptr5 = AMDS_RX_BUF_SIZE - __HAL_DMA_GET_COUNTER(huart5.hdmarx); } } -void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) -{ -// if (huart->Instance == UART4) { -// if (uart4_packet_count < PACKETS_PER_UART) { -// -// uint8_t offset = uart4_packet_count; -// -// uint16_t value = ((uint16_t)UART4_RxBuf[1] << 8) | (uint16_t)UART4_RxBuf[2]; -// -// latest_valid_amds_samples[uart4_amds_sample_count][offset] = value; -// -// uart4_packet_count++; -// } -// -// if (uart4_packet_count == PACKETS_PER_UART) { -// amds_samples_ready[uart4_amds_sample_count] = true; -// uart4_amds_sample_count++; -// uart4_packet_count = 0; -// } -// -// if (uart4_amds_sample_count == 2) { -// amds_samples_ready[uart4_amds_sample_count + 1] = true; -// uart4_amds_sample_count = 0; -// } -//// HAL_UART_Receive_DMA(huart, UART4_RxBuf, PACKET_SIZE); -// } else if (huart->Instance == UART5) { -// if (uart5_packet_count < PACKETS_PER_UART) { -// -// uint8_t offset = uart5_packet_count + 4; -// -// uint16_t value = ((uint16_t)UART5_RxBuf[1] << 8) | (uint16_t)UART5_RxBuf[2]; -// -// latest_valid_amds_samples[uart5_amds_sample_count][offset] = value; -// -// uart5_packet_count++; -// } -// -// if (uart5_packet_count == PACKETS_PER_UART) { -// amds_samples_ready[uart5_amds_sample_count] = true; -// uart5_amds_sample_count++; -// uart5_packet_count = 0; -// } -// -// if (uart5_amds_sample_count == 2) { -// amds_samples_ready[uart5_amds_sample_count + 2] = true; -// uart5_amds_sample_count = 0; -// } -//// HAL_UART_Receive_DMA(huart, UART5_RxBuf, PACKET_SIZE); -// } + + + +void dma_queue(uint8_t uart_id, uint8_t *data, uint8_t len) { + if (uart_id == 2) { + for (int i = 0; i < len; i++) { + uart2_dma_queue[u2_q_head] = data[i]; + u2_q_head = (u2_q_head + 1) % AMDS_RX_BUF_SIZE; + } + } else if (uart_id == 3) { + for (int i = 0; i < len; i++) { + uart3_dma_queue[u3_q_head] = data[i]; + u3_q_head = (u3_q_head + 1) % AMDS_RX_BUF_SIZE; + } + } } void UART4_IRQHandler(void) diff --git a/Mainboard/Firmware/motherboard_v1/Core/Src/main.c b/Mainboard/Firmware/motherboard_v1/Core/Src/main.c index f63b311..5a02a5c 100644 --- a/Mainboard/Firmware/motherboard_v1/Core/Src/main.c +++ b/Mainboard/Firmware/motherboard_v1/Core/Src/main.c @@ -24,11 +24,16 @@ int main(void) drv_uart_init(); drv_led_init(); + // Tell the UART to constantly route TX requests to the DMA controller +// huart2.Instance->CR3 |= USART_CR3_DMAT; +// huart3.Instance->CR3 |= USART_CR3_DMAT; + // Initialize the main modules adc_init(); // Infinite loop (all real work is done in ISRs) uint8_t led = 0; + uint32_t ledDelta = HAL_GetTick(); // Disable the SysTick ISR // @@ -37,22 +42,34 @@ int main(void) // we do not need it to run during operation! // // Set bit 0 to 0 - SysTick->CTRL &= 0xFFFFFFFE; +// SysTick->CTRL &= 0xFFFFFFFE; while (1) { - drv_led_clear(); - drv_led_on(1 << led); - drv_led_display(); +// // 1. Process and instantly forward UART4 data -> UART2 +// if (tracker4.read_index != (AMDS_RX_BUF_SIZE - __HAL_DMA_GET_COUNTER(huart4.hdmarx))) { +// process_uart_fifo(UART4_DMA_Pool, &tracker4, 4); +// } +// +// // 2. Process and instantly forward UART5 data -> UART3 +// if (tracker5.read_index != (AMDS_RX_BUF_SIZE - __HAL_DMA_GET_COUNTER(huart5.hdmarx))) { +// process_uart_fifo(UART5_DMA_Pool, &tracker5, 5); +// } + + // Interleave the parsing and routing for both lines simultaneously + process_routing(); - if (++led >= DRV_LED_NUM_TOTAL) { - led = 0; - } + // 3. Handle slow UI tasks (LEDs) + if (HAL_GetTick() - ledDelta >= 250) { + ledDelta = HAL_GetTick(); + drv_led_clear(); + drv_led_on(1 << led); + drv_led_display(); - volatile int i; - for (i = 0; i < 10000000; i++) { - asm("nop"); - } - } + if (++led >= DRV_LED_NUM_TOTAL) { + led = 0; + } + } +} } void HAL_MspInit(void) diff --git a/Mainboard/Firmware/motherboard_v1/Core/Src/tx.c b/Mainboard/Firmware/motherboard_v1/Core/Src/tx.c index a2e04c5..793c71f 100644 --- a/Mainboard/Firmware/motherboard_v1/Core/Src/tx.c +++ b/Mainboard/Firmware/motherboard_v1/Core/Src/tx.c @@ -1,7 +1,51 @@ #include "tx.h" -#include "adc.h" -#include "drv_uart.h" -#include "platform.h" + +volatile packet_t tx_packets[NUM_SETS * PACKETS_PER_SET]; +volatile bool packet_ready[NUM_SETS * PACKETS_PER_SET]; +bool packet_sent[NUM_SETS * PACKETS_PER_SET]; + +volatile bool sync_event_flag = false; // Set this to true in your EXTI ISR + +void process_transmissions(void) { + // Loop as long as there is data in EITHER queue + while ((u2_q_tail != u2_q_head) || (u3_q_tail != u3_q_head)) { + + // If UART2 has data, pop one byte and push it straight to the hardware + if (u2_q_tail != u2_q_head) { + drv_uart_putc_fast(USART2, uart2_dma_queue[u2_q_tail]); + u2_q_tail = (u2_q_tail + 1) % AMDS_RX_BUF_SIZE; + } + + // If UART3 has data, pop one byte and push it straight to the hardware + if (u3_q_tail != u3_q_head) { + drv_uart_putc_fast(USART3, uart3_dma_queue[u3_q_tail]); + u3_q_tail = (u3_q_tail + 1) % AMDS_RX_BUF_SIZE; + } + } +} + + + + + + + + + + + + + + + + + + + + + + + // clang-format off @@ -17,110 +61,110 @@ // clang-format on -// Called after ADC conversions have been completed, -// to send sampled data back to AMDC +//// Called after ADC conversions have been completed, +//// to send sampled data back to AMDC +//// +//void transmit_samples(void) +//{ +// // 2. Create a local buffer for this transmission "burst" +// static uint8_t tx_data2[36]; +// static uint8_t tx_data3[36]; +// uint8_t idx = 0; // -void transmit_samples(void) -{ - // 2. Create a local buffer for this transmission "burst" - static uint8_t tx_data2[36]; - static uint8_t tx_data3[36]; - uint8_t idx = 0; - - uint16_t bits[8]; - adc_latest_bits(bits); - - for (int i = 0; i < 4; i++) { - uint8_t header = (i == 0) ? 0x90 : (0x90 | (0x03 & i)); - - tx_data2[idx] = header; - tx_data3[idx] = header; - idx++; - - tx_data2[idx] = (uint8_t)(bits[i] >> 8); // MSB - tx_data3[idx] = (uint8_t)(bits[i + 4] >> 8); // MSB - idx++; - - tx_data2[idx] = (uint8_t)(bits[i] & 0xFF); // LSB - tx_data3[idx] = (uint8_t)(bits[i + 4] & 0xFF); // LSB - idx++; - } - - // 1. Process incoming UARTs first - NOP256; - NOP256; - NOP256; - NOP256; - NOP256; - NOP256; - NOP256; - NOP256; - NOP256; - NOP256; - NOP256; - NOP256; - NOP256; - NOP256; - NOP256; - NOP256; - NOP256; - NOP256; - process_uart_fifo(UART4_DMA_Pool, &tracker4, 4); - process_uart_fifo(UART5_DMA_Pool, &tracker5, 5); - - uint16_t amds[16] = {1}; - adc_latest_amds(amds); - - // ... Add AMDS data to tx_data if ready ... - if (amds_samples_ready[0]) { - for (int i = 0; i < 4; i++) { - uint8_t header = (i == 0) ? 0x94 : (0x94 | (0x07 & i)); - - tx_data2[idx] = header; - tx_data3[idx] = header; - idx++; - - tx_data2[idx] = (uint8_t)(amds[i] >> 8); // MSB - tx_data3[idx] = (uint8_t)(amds[i + 4] >> 8); // MSB - idx++; - - tx_data2[idx] = (uint8_t)(amds[i] & 0xFF); // LSB - tx_data3[idx] = (uint8_t)(amds[i + 4] & 0xFF); // LSB - idx++; - } - - // Clear flags for this set - amds_samples_ready[0] = false; - - if (amds_samples_ready[1]) { - for (int i = 0; i < 4; i++) { - uint8_t header = (i == 0) ? 0x98 : (0x98 | (0x0B & i)); - - tx_data2[idx] = header; - tx_data3[idx] = header; - idx++; - - tx_data2[idx] = (uint8_t)(amds[i] >> 8); // MSB - tx_data3[idx] = (uint8_t)(amds[i + 4] >> 8); // MSB - idx++; - - tx_data2[idx] = (uint8_t)(amds[i] & 0xFF); // LSB - tx_data3[idx] = (uint8_t)(amds[i + 4] & 0xFF); // LSB - idx++; - } - - // Clear flags for this set - amds_samples_ready[1] = false; - } - } - - // 4. Trigger the DMA to send exactly 'idx' bytes - // This function returns immediately while the hardware sends the data - if (huart2.gState == HAL_UART_STATE_READY && huart3.gState == HAL_UART_STATE_READY) { - HAL_UART_Transmit_DMA(&huart2, tx_data2, idx); - HAL_UART_Transmit_DMA(&huart3, tx_data3, idx); - } -} +// uint16_t bits[8]; +// adc_latest_bits(bits); +// +// for (int i = 0; i < 4; i++) { +// uint8_t header = (i == 0) ? 0x90 : (0x90 | (0x03 & i)); +// +// tx_data2[idx] = header; +// tx_data3[idx] = header; +// idx++; +// +// tx_data2[idx] = (uint8_t)(bits[i] >> 8); // MSB +// tx_data3[idx] = (uint8_t)(bits[i + 4] >> 8); // MSB +// idx++; +// +// tx_data2[idx] = (uint8_t)(bits[i] & 0xFF); // LSB +// tx_data3[idx] = (uint8_t)(bits[i + 4] & 0xFF); // LSB +// idx++; +// } +// +// // 1. Process incoming UARTs first +// NOP256; +// NOP256; +// NOP256; +// NOP256; +// NOP256; +// NOP256; +// NOP256; +// NOP256; +// NOP256; +// NOP256; +// NOP256; +// NOP256; +// NOP256; +// NOP256; +// NOP256; +// NOP256; +// NOP256; +// NOP256; +// process_uart_fifo(UART4_DMA_Pool, &tracker4, 4); +// process_uart_fifo(UART5_DMA_Pool, &tracker5, 5); +// +// uint16_t amds[16] = {1}; +// adc_latest_amds(amds); +// +// // ... Add AMDS data to tx_data if ready ... +// if (amds_samples_ready[0]) { +// for (int i = 0; i < 4; i++) { +// uint8_t header = (i == 0) ? 0x94 : (0x94 | (0x07 & i)); +// +// tx_data2[idx] = header; +// tx_data3[idx] = header; +// idx++; +// +// tx_data2[idx] = (uint8_t)(amds[i] >> 8); // MSB +// tx_data3[idx] = (uint8_t)(amds[i + 4] >> 8); // MSB +// idx++; +// +// tx_data2[idx] = (uint8_t)(amds[i] & 0xFF); // LSB +// tx_data3[idx] = (uint8_t)(amds[i + 4] & 0xFF); // LSB +// idx++; +// } +// +// // Clear flags for this set +// amds_samples_ready[0] = false; +// +// if (amds_samples_ready[1]) { +// for (int i = 0; i < 4; i++) { +// uint8_t header = (i == 0) ? 0x98 : (0x98 | (0x0B & i)); +// +// tx_data2[idx] = header; +// tx_data3[idx] = header; +// idx++; +// +// tx_data2[idx] = (uint8_t)(amds[i] >> 8); // MSB +// tx_data3[idx] = (uint8_t)(amds[i + 4] >> 8); // MSB +// idx++; +// +// tx_data2[idx] = (uint8_t)(amds[i] & 0xFF); // LSB +// tx_data3[idx] = (uint8_t)(amds[i + 4] & 0xFF); // LSB +// idx++; +// } +// +// // Clear flags for this set +// amds_samples_ready[1] = false; +// } +// } +// +// // 4. Trigger the DMA to send exactly 'idx' bytes +// // This function returns immediately while the hardware sends the data +// if (huart2.gState == HAL_UART_STATE_READY && huart3.gState == HAL_UART_STATE_READY) { +// HAL_UART_Transmit_DMA(&huart2, tx_data2, idx); +// HAL_UART_Transmit_DMA(&huart3, tx_data3, idx); +// } +//}