LFU-609 ddr: imx95: add QB training data collect function

Add DDR PHY training data collect function for iMX95.
Function allows transfering training data over USB
connection to host machine using fastboot
"upload -v snps-ddr-phy-qb -f qb_data.bin"
command on host side.

Signed-off-by: Viorel Suman <[email protected]>
Reviewed-by: Ye Li <[email protected]>

Author: Viorel Suman

arch/arm/include/asm/arch-imx9/ddr.h

@@ -101,6 +101,7 @@ struct dram_timing_info {
 
 extern struct dram_timing_info dram_timing;
 
+#if defined(CONFIG_IMX93)	/* CONFIG_IMX93 */
 #if (defined(CONFIG_IMX_SNPS_DDR_PHY_QB_GEN) || defined(CONFIG_IMX_SNPS_DDR_PHY_QB))
 #define DDRPHY_QB_FSP_SIZE	3
 #define DDRPHY_QB_ERR_SIZE	6
@@ -126,6 +127,43 @@ int ddrphy_qb_save(void);
 int ddr_cfg_phy_qb(struct dram_timing_info *timing_info, int fsp_id);
 #endif
 #endif
+#elif defined(CONFIG_IMX95)	/* CONFIG_IMX95 */
+#if   defined(CONFIG_IMX_SNPS_DDR_PHY_QB_GEN)
+/* Quick Boot related */
+#define DDRPHY_QB_CSR_SIZE	5168
+#define DDRPHY_QB_ACSM_SIZE	4 * 1024
+#define DDRPHY_QB_MSB_SIZE	0x200
+#define DDRPHY_QB_PSTATES	0
+#define DDRPHY_QB_PST_SIZE	DDRPHY_QB_PSTATES * 4 * 1024
+struct ddrphy_qb_state {
+	u8 TrainedVREFCA_A0;
+	u8 TrainedVREFCA_A1;
+	u8 TrainedVREFCA_B0;
+	u8 TrainedVREFCA_B1;
+	u8 TrainedVREFDQ_A0;
+	u8 TrainedVREFDQ_A1;
+	u8 TrainedVREFDQ_B0;
+	u8 TrainedVREFDQ_B1;
+	u8 TrainedVREFDQU_A0;
+	u8 TrainedVREFDQU_A1;
+	u8 TrainedVREFDQU_B0;
+	u8 TrainedVREFDQU_B1;
+	u8 TrainedDRAMDFE_A0;
+	u8 TrainedDRAMDFE_A1;
+	u8 TrainedDRAMDFE_B0;
+	u8 TrainedDRAMDFE_B1;
+	u8 TrainedDRAMDCA_A0;
+	u8 TrainedDRAMDCA_A1;
+	u8 TrainedDRAMDCA_B0;
+	u8 TrainedDRAMDCA_B1;
+	u16 csr[DDRPHY_QB_CSR_SIZE];
+	u16 acsm[DDRPHY_QB_ACSM_SIZE];
+	u16 pst[DDRPHY_QB_PST_SIZE];
+};
+#elif  defined(CONFIG_IMX_SNPS_DDR_PHY_QB)
+	#error "Quick Boot flow not supported in SPL for iMX95, please use DDR OEI!"
+#endif /* #if   defined(CONFIG_IMX_SNPS_DDR_PHY_QB_GEN)  */
+#endif /* #elif defined(CONFIG_IMX95) */
 
 void ddr_load_train_firmware(enum fw_type type);
 int ddr_init(struct dram_timing_info *timing_info);

configs/imx95_19x19_evk_defconfig

@@ -218,3 +218,6 @@ CONFIG_CLK_CCF=y
 CONFIG_SPL_CLK_CCF=y
 
 CONFIG_SPL_RECOVER_DATA_SECTION=y
+
+CONFIG_IMX_SNPS_DDR_PHY_QB_GEN=y
+CONFIG_SAVED_QB_STATE_BASE=0x4aa00000

drivers/ddr/imx/phy/Kconfig

@@ -5,7 +5,7 @@ config IMX_SNPS_DDR_PHY
 
 config IMX_SNPS_DDR_PHY_QB_GEN
 	bool "i.MX Synopsys DDR PHY training data generation for QuickBoot mode"
-	depends on IMX_SNPS_DDR_PHY
+	depends on IMX_SNPS_DDR_PHY || IMX95
 	help
 	  Select the DDR PHY training data generation for QuickBoot support on i.MX9 SOC.
 

drivers/ddr/imx/phy/Makefile

@@ -6,6 +6,8 @@
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_IMX_SNPS_DDR_PHY) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o
+ifdef CONFIG_IMX93
 obj-$(CONFIG_IMX_SNPS_DDR_PHY_QB_GEN) += ddrphy_qb_gen.o ddrphy_qb_errata.o
 obj-$(CONFIG_IMX_SNPS_DDR_PHY_QB) += ddrphy_qb.o ddrphy_qb_errata.o
 endif
+endif

drivers/fastboot/fb_fsl/fb_fsl_command.c

@@ -225,15 +225,17 @@ static void upload(char *cmd_parameter, char *response)
 	#if CONFIG_IS_ENABLED(IMX_SNPS_DDR_PHY_QB_GEN)
 	if (endswith(cmd_parameter, "snps-ddr-phy-qb")) {
 		struct ddrphy_qb_state *qb_state;
+	#if CONFIG_IS_ENABLED(IMX93)
 		uint32_t crc;
-
+	#endif
 		qb_state = (struct ddrphy_qb_state *)CONFIG_SAVED_QB_STATE_BASE;
+	#if CONFIG_IS_ENABLED(IMX93)
 		crc = crc32(0, (void *)&(qb_state->flags), DDRPHY_QB_STATE_SIZE);
 
 		if (crc != qb_state->crc)
 			log_err("DDRPHY TD CRC error SPL->U-Boot: spl=0x%08x, uboot=0x%08x\n",
 				qb_state->crc, crc);
-
+	#endif
 		send(response, (const char *)qb_state, sizeof(struct ddrphy_qb_state));
 		return;
 	}