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tinebptinebp
committed
ramulator memory addressing bug fix + platform memory refactoring
1 parent e80ee2c commit 22398c9

33 files changed

+310
-281
lines changed

‎ci/regression.sh.in

+8-8
Original file line numberDiff line numberDiff line change
@@ -301,11 +301,11 @@ config2()
301301

302302
# test single-bank memory
303303
if [ "$XLEN" == "64" ]; then
304-
CONFIGS="-DPLATFORM_MEMORY_BANKS=1 -DPLATFORM_MEMORY_ADDR_WIDTH=48" ./ci/blackbox.sh --driver=opae --app=mstress
305-
CONFIGS="-DPLATFORM_MEMORY_BANKS=1 -DPLATFORM_MEMORY_ADDR_WIDTH=48" ./ci/blackbox.sh --driver=xrt --app=mstress
304+
CONFIGS="-DPLATFORM_MEMORY_NUM_BANKS=1" ./ci/blackbox.sh --driver=opae --app=mstress
305+
CONFIGS="-DPLATFORM_MEMORY_NUM_BANKS=1" ./ci/blackbox.sh --driver=xrt --app=mstress
306306
else
307-
CONFIGS="-DPLATFORM_MEMORY_BANKS=1 -DPLATFORM_MEMORY_ADDR_WIDTH=32" ./ci/blackbox.sh --driver=opae --app=mstress
308-
CONFIGS="-DPLATFORM_MEMORY_BANKS=1 -DPLATFORM_MEMORY_ADDR_WIDTH=32" ./ci/blackbox.sh --driver=xrt --app=mstress
307+
CONFIGS="-DPLATFORM_MEMORY_NUM_BANKS=1" ./ci/blackbox.sh --driver=opae --app=mstress
308+
CONFIGS="-DPLATFORM_MEMORY_NUM_BANKS=1" ./ci/blackbox.sh --driver=xrt --app=mstress
309309
fi
310310

311311
# test larger memory address
@@ -322,10 +322,10 @@ config2()
322322
CONFIGS="-DPLATFORM_MEMORY_INTERLEAVE=0" ./ci/blackbox.sh --driver=opae --app=mstress
323323

324324
# test memory ports
325-
CONFIGS="-DMEM_BLOCK_SIZE=8 -DPLATFORM_MEMORY_BANKS=2" ./ci/blackbox.sh --driver=simx --app=mstress
326-
CONFIGS="-DMEM_BLOCK_SIZE=8 -DPLATFORM_MEMORY_BANKS=2" ./ci/blackbox.sh --driver=simx --app=mstress --threads=8
327-
CONFIGS="-DMEM_BLOCK_SIZE=8 -DPLATFORM_MEMORY_BANKS=2" ./ci/blackbox.sh --driver=rtlsim --app=mstress
328-
CONFIGS="-DMEM_BLOCK_SIZE=8 -DPLATFORM_MEMORY_BANKS=2" ./ci/blackbox.sh --driver=rtlsim --app=mstress --threads=8
325+
CONFIGS="-DMEM_BLOCK_SIZE=8 -DPLATFORM_MEMORY_NUM_BANKS=2" ./ci/blackbox.sh --driver=simx --app=mstress
326+
CONFIGS="-DMEM_BLOCK_SIZE=8 -DPLATFORM_MEMORY_NUM_BANKS=2" ./ci/blackbox.sh --driver=simx --app=mstress --threads=8
327+
CONFIGS="-DMEM_BLOCK_SIZE=8 -DPLATFORM_MEMORY_NUM_BANKS=2" ./ci/blackbox.sh --driver=rtlsim --app=mstress
328+
CONFIGS="-DMEM_BLOCK_SIZE=8 -DPLATFORM_MEMORY_NUM_BANKS=2" ./ci/blackbox.sh --driver=rtlsim --app=mstress --threads=8
329329
CONFIGS="-DMEM_BLOCK_SIZE=8" ./ci/blackbox.sh --driver=opae --app=mstress --threads=8
330330
CONFIGS="-DMEM_BLOCK_SIZE=8" ./ci/blackbox.sh --driver=xrt --app=mstress --threads=8
331331

‎hw/rtl/VX_config.vh

+26-8
Original file line numberDiff line numberDiff line change
@@ -172,8 +172,26 @@
172172
`define L3_LINE_SIZE `MEM_BLOCK_SIZE
173173
`endif
174174

175-
`ifndef PLATFORM_MEMORY_BANKS
176-
`define PLATFORM_MEMORY_BANKS 2
175+
// Platform memory parameters
176+
177+
`ifndef PLATFORM_MEMORY_NUM_BANKS
178+
`define PLATFORM_MEMORY_NUM_BANKS 2
179+
`endif
180+
181+
`ifndef PLATFORM_MEMORY_ADDR_WIDTH
182+
`ifdef XLEN_64
183+
`define PLATFORM_MEMORY_ADDR_WIDTH 48
184+
`else
185+
`define PLATFORM_MEMORY_ADDR_WIDTH 32
186+
`endif
187+
`endif
188+
189+
`ifndef PLATFORM_MEMORY_DATA_SIZE
190+
`define PLATFORM_MEMORY_DATA_SIZE 64
191+
`endif
192+
193+
`ifndef PLATFORM_MEMORY_INTERLEAVE
194+
`define PLATFORM_MEMORY_INTERLEAVE 1
177195
`endif
178196

179197
`ifdef XLEN_64
@@ -656,9 +674,9 @@
656674
// Number of Memory Ports
657675
`ifndef L1_MEM_PORTS
658676
`ifdef L1_DISABLE
659-
`define L1_MEM_PORTS `MIN(DCACHE_NUM_REQS, `PLATFORM_MEMORY_BANKS)
677+
`define L1_MEM_PORTS `MIN(DCACHE_NUM_REQS, `PLATFORM_MEMORY_NUM_BANKS)
660678
`else
661-
`define L1_MEM_PORTS `MIN(`DCACHE_NUM_BANKS, `PLATFORM_MEMORY_BANKS)
679+
`define L1_MEM_PORTS `MIN(`DCACHE_NUM_BANKS, `PLATFORM_MEMORY_NUM_BANKS)
662680
`endif
663681
`endif
664682

@@ -735,9 +753,9 @@
735753
// Number of Memory Ports
736754
`ifndef L2_MEM_PORTS
737755
`ifdef L2_ENABLE
738-
`define L2_MEM_PORTS `MIN(`L2_NUM_BANKS, `PLATFORM_MEMORY_BANKS)
756+
`define L2_MEM_PORTS `MIN(`L2_NUM_BANKS, `PLATFORM_MEMORY_NUM_BANKS)
739757
`else
740-
`define L2_MEM_PORTS `MIN(L2_NUM_REQS, `PLATFORM_MEMORY_BANKS)
758+
`define L2_MEM_PORTS `MIN(L2_NUM_REQS, `PLATFORM_MEMORY_NUM_BANKS)
741759
`endif
742760
`endif
743761

@@ -796,9 +814,9 @@
796814
// Number of Memory Ports
797815
`ifndef L3_MEM_PORTS
798816
`ifdef L3_ENABLE
799-
`define L3_MEM_PORTS `MIN(`L3_NUM_BANKS, `PLATFORM_MEMORY_BANKS)
817+
`define L3_MEM_PORTS `MIN(`L3_NUM_BANKS, `PLATFORM_MEMORY_NUM_BANKS)
800818
`else
801-
`define L3_MEM_PORTS `MIN(L3_NUM_REQS, `PLATFORM_MEMORY_BANKS)
819+
`define L3_MEM_PORTS `MIN(L3_NUM_REQS, `PLATFORM_MEMORY_NUM_BANKS)
802820
`endif
803821
`endif
804822

‎hw/rtl/Vortex_axi.sv

+1-1
Original file line numberDiff line numberDiff line change
@@ -193,7 +193,7 @@ module Vortex_axi import VX_gpu_pkg::*; #(
193193
.TAG_WIDTH_OUT (AXI_TID_WIDTH),
194194
.NUM_PORTS_IN (`VX_MEM_PORTS),
195195
.NUM_BANKS_OUT (AXI_NUM_BANKS),
196-
.INTERLEAVE (0),
196+
.INTERLEAVE (`PLATFORM_MEMORY_INTERLEAVE),
197197
.REQ_OUT_BUF ((`VX_MEM_PORTS > 1) ? 2 : 0),
198198
.RSP_OUT_BUF ((`VX_MEM_PORTS > 1 || AXI_NUM_BANKS > 1) ? 2 : 0)
199199
) axi_adapter (

‎hw/rtl/afu/opae/local_mem_cfg_pkg.sv

+4-4
Original file line numberDiff line numberDiff line change
@@ -28,18 +28,18 @@
2828
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
2929
// POSSIBILITY OF SUCH DAMAGE.
3030

31-
//`include "platform_afu_top_config.vh"
31+
`include "VX_define.vh"
3232

3333
`ifndef PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH
34-
`define PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH (`PLATFORM_MEMORY_ADDR_WIDTH - $clog2(`PLATFORM_MEMORY_DATA_WIDTH/8))
34+
`define PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH ((`PLATFORM_MEMORY_ADDR_WIDTH - $clog2(`PLATFORM_MEMORY_NUM_BANKS)) - $clog2(`PLATFORM_MEMORY_DATA_SIZE))
3535
`endif
3636

3737
`ifndef PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH
38-
`define PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH `PLATFORM_MEMORY_DATA_WIDTH
38+
`define PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH (`PLATFORM_MEMORY_DATA_SIZE * 8)
3939
`endif
4040

4141
`ifndef PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH
42-
`define PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH `PLATFORM_MEMORY_BURST_CNT_WIDTH
42+
`define PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH 4
4343
`endif
4444

4545
package local_mem_cfg_pkg;

‎hw/rtl/afu/opae/vortex_afu.sv

+2-6
Original file line numberDiff line numberDiff line change
@@ -11,18 +11,14 @@
1111
// See the License for the specific language governing permissions and
1212
// limitations under the License.
1313

14+
`include "VX_define.vh"
15+
1416
`ifndef NOPAE
1517
`include "afu_json_info.vh"
1618
`else
1719
`include "vortex_afu.vh"
1820
`endif
1921

20-
`include "VX_define.vh"
21-
22-
`ifndef PLATFORM_MEMORY_INTERLEAVE
23-
`define PLATFORM_MEMORY_INTERLEAVE 1
24-
`endif
25-
2622
module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_gpu_pkg::*; #(
2723
parameter NUM_LOCAL_MEM_BANKS = 2
2824
) (

‎hw/rtl/afu/xrt/VX_afu_ctrl.sv

+4-2
Original file line numberDiff line numberDiff line change
@@ -134,10 +134,12 @@ module VX_afu_ctrl #(
134134
RSTATE_RESP = 2'd2,
135135
RSTATE_WIDTH = 2;
136136

137+
localparam MEMORY_BANK_ADDR_WIDTH = `PLATFORM_MEMORY_ADDR_WIDTH - `CLOG2(`PLATFORM_MEMORY_NUM_BANKS);
138+
137139
// device caps
138140
wire [63:0] dev_caps = {8'b0,
139-
5'(`PLATFORM_MEMORY_ADDR_WIDTH-20),
140-
3'(`CLOG2(`PLATFORM_MEMORY_BANKS)),
141+
5'(MEMORY_BANK_ADDR_WIDTH-20),
142+
3'(`CLOG2(`PLATFORM_MEMORY_NUM_BANKS)),
141143
8'(`LMEM_ENABLED ? `LMEM_LOG_SIZE : 0),
142144
16'(`NUM_CORES * `NUM_CLUSTERS),
143145
8'(`NUM_WARPS),

‎hw/rtl/afu/xrt/VX_afu_wrap.sv

+11-15
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ module VX_afu_wrap #(
3131
`ifdef PLATFORM_MERGED_MEMORY_INTERFACE
3232
`REPEAT (1, GEN_AXI_MEM, REPEAT_COMMA),
3333
`else
34-
`REPEAT (`PLATFORM_MEMORY_BANKS, GEN_AXI_MEM, REPEAT_COMMA),
34+
`REPEAT (`PLATFORM_MEMORY_NUM_BANKS, GEN_AXI_MEM, REPEAT_COMMA),
3535
`endif
3636
// AXI4-Lite slave interface
3737
input wire s_axi_ctrl_awvalid,
@@ -58,11 +58,7 @@ module VX_afu_wrap #(
5858

5959
output wire interrupt
6060
);
61-
`ifdef PLATFORM_MERGED_MEMORY_INTERFACE
62-
localparam M_AXI_MEM_ADDR_WIDTH = `PLATFORM_MEMORY_ADDR_WIDTH + $clog2(`PLATFORM_MEMORY_BANKS);
63-
`else
64-
localparam M_AXI_MEM_ADDR_WIDTH = `PLATFORM_MEMORY_ADDR_WIDTH;
65-
`endif
61+
localparam M_AXI_MEM_ADDR_WIDTH = `PLATFORM_MEMORY_ADDR_WIDTH - $clog2(C_M_AXI_MEM_NUM_BANKS);
6662

6763
typedef enum logic [1:0] {
6864
STATE_IDLE = 0,
@@ -71,8 +67,8 @@ module VX_afu_wrap #(
7167
STATE_DONE = 3
7268
} state_e;
7369

74-
localparam PENDING_SIZEW = 12; // max outstanding requests size
75-
localparam C_M_AXI_MEM_NUM_BANKS_SW = `CLOG2(C_M_AXI_MEM_NUM_BANKS+1);
70+
localparam PENDING_WR_SIZEW = 12; // max outstanding requests size
71+
localparam NUM_MEM_BANKS_SIZEW = `CLOG2(C_M_AXI_MEM_NUM_BANKS+1);
7672

7773
wire m_axi_mem_awvalid_a [C_M_AXI_MEM_NUM_BANKS];
7874
wire m_axi_mem_awready_a [C_M_AXI_MEM_NUM_BANKS];
@@ -108,11 +104,11 @@ module VX_afu_wrap #(
108104
`ifdef PLATFORM_MERGED_MEMORY_INTERFACE
109105
`REPEAT (1, AXI_MEM_TO_ARRAY, REPEAT_SEMICOLON);
110106
`else
111-
`REPEAT (`PLATFORM_MEMORY_BANKS, AXI_MEM_TO_ARRAY, REPEAT_SEMICOLON);
107+
`REPEAT (`PLATFORM_MEMORY_NUM_BANKS, AXI_MEM_TO_ARRAY, REPEAT_SEMICOLON);
112108
`endif
113109

114110
reg [`CLOG2(`RESET_DELAY+1)-1:0] vx_reset_ctr;
115-
reg [PENDING_SIZEW-1:0] vx_pending_writes;
111+
reg [PENDING_WR_SIZEW-1:0] vx_pending_writes;
116112
reg vx_reset = 1; // asserted at initialization
117113
wire vx_busy;
118114

@@ -200,7 +196,7 @@ module VX_afu_wrap #(
200196
end
201197

202198
wire [C_M_AXI_MEM_NUM_BANKS-1:0] m_axi_wr_req_fire, m_axi_wr_rsp_fire;
203-
wire [C_M_AXI_MEM_NUM_BANKS_SW-1:0] cur_wr_reqs, cur_wr_rsps;
199+
wire [NUM_MEM_BANKS_SIZEW-1:0] cur_wr_reqs, cur_wr_rsps;
204200

205201
for (genvar i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin : g_m_axi_wr_req_fire
206202
VX_axi_write_ack axi_write_ack (
@@ -224,14 +220,14 @@ module VX_afu_wrap #(
224220
`POP_COUNT(cur_wr_reqs, m_axi_wr_req_fire);
225221
`POP_COUNT(cur_wr_rsps, m_axi_wr_rsp_fire);
226222

227-
wire signed [C_M_AXI_MEM_NUM_BANKS_SW:0] reqs_sub = (C_M_AXI_MEM_NUM_BANKS_SW+1)'(cur_wr_reqs) -
228-
(C_M_AXI_MEM_NUM_BANKS_SW+1)'(cur_wr_rsps);
223+
wire signed [NUM_MEM_BANKS_SIZEW:0] reqs_sub = (NUM_MEM_BANKS_SIZEW+1)'(cur_wr_reqs) -
224+
(NUM_MEM_BANKS_SIZEW+1)'(cur_wr_rsps);
229225

230226
always @(posedge clk) begin
231227
if (reset) begin
232228
vx_pending_writes <= '0;
233229
end else begin
234-
vx_pending_writes <= vx_pending_writes + PENDING_SIZEW'(reqs_sub);
230+
vx_pending_writes <= vx_pending_writes + PENDING_WR_SIZEW'(reqs_sub);
235231
end
236232
end
237233

@@ -270,7 +266,7 @@ module VX_afu_wrap #(
270266
.ap_ready (ap_ready),
271267
.ap_idle (ap_idle),
272268
.interrupt (interrupt),
273-
269+
274270
.ap_ctrl_read (ap_ctrl_read),
275271

276272
`ifdef SCOPE

‎hw/rtl/afu/xrt/vortex_afu.v

+5-5
Original file line numberDiff line numberDiff line change
@@ -17,12 +17,12 @@ module vortex_afu #(
1717
parameter C_S_AXI_CTRL_ADDR_WIDTH = 8,
1818
parameter C_S_AXI_CTRL_DATA_WIDTH = 32,
1919
parameter C_M_AXI_MEM_ID_WIDTH = `PLATFORM_MEMORY_ID_WIDTH,
20-
parameter C_M_AXI_MEM_DATA_WIDTH = `PLATFORM_MEMORY_DATA_WIDTH,
20+
parameter C_M_AXI_MEM_DATA_WIDTH = (`PLATFORM_MEMORY_DATA_SIZE * 8),
2121
parameter C_M_AXI_MEM_ADDR_WIDTH = 64,
2222
`ifdef PLATFORM_MERGED_MEMORY_INTERFACE
2323
parameter C_M_AXI_MEM_NUM_BANKS = 1
2424
`else
25-
parameter C_M_AXI_MEM_NUM_BANKS = `PLATFORM_MEMORY_BANKS
25+
parameter C_M_AXI_MEM_NUM_BANKS = `PLATFORM_MEMORY_NUM_BANKS
2626
`endif
2727
) (
2828
// System signals
@@ -33,7 +33,7 @@ module vortex_afu #(
3333
`ifdef PLATFORM_MERGED_MEMORY_INTERFACE
3434
`REPEAT (1, GEN_AXI_MEM, REPEAT_COMMA),
3535
`else
36-
`REPEAT (`PLATFORM_MEMORY_BANKS, GEN_AXI_MEM, REPEAT_COMMA),
36+
`REPEAT (`PLATFORM_MEMORY_NUM_BANKS, GEN_AXI_MEM, REPEAT_COMMA),
3737
`endif
3838

3939
// AXI4-Lite slave interface
@@ -75,7 +75,7 @@ module vortex_afu #(
7575
`ifdef PLATFORM_MERGED_MEMORY_INTERFACE
7676
`REPEAT (1, AXI_MEM_ARGS, REPEAT_COMMA),
7777
`else
78-
`REPEAT (`PLATFORM_MEMORY_BANKS, AXI_MEM_ARGS, REPEAT_COMMA),
78+
`REPEAT (`PLATFORM_MEMORY_NUM_BANKS, AXI_MEM_ARGS, REPEAT_COMMA),
7979
`endif
8080
.s_axi_ctrl_awvalid (s_axi_ctrl_awvalid),
8181
.s_axi_ctrl_awready (s_axi_ctrl_awready),
@@ -94,7 +94,7 @@ module vortex_afu #(
9494
.s_axi_ctrl_rready (s_axi_ctrl_rready),
9595
.s_axi_ctrl_rdata (s_axi_ctrl_rdata),
9696
.s_axi_ctrl_rresp (s_axi_ctrl_rresp),
97-
97+
9898
.s_axi_ctrl_bvalid (s_axi_ctrl_bvalid),
9999
.s_axi_ctrl_bready (s_axi_ctrl_bready),
100100
.s_axi_ctrl_bresp (s_axi_ctrl_bresp),

‎hw/rtl/afu/xrt/vortex_afu.vh

-12
Original file line numberDiff line numberDiff line change
@@ -14,18 +14,6 @@
1414
`ifndef VORTEX_AFU_VH
1515
`define VORTEX_AFU_VH
1616

17-
`ifndef PLATFORM_MEMORY_BANKS
18-
`define PLATFORM_MEMORY_BANKS 2
19-
`endif
20-
21-
`ifndef PLATFORM_MEMORY_ADDR_WIDTH
22-
`define PLATFORM_MEMORY_ADDR_WIDTH 31
23-
`endif
24-
25-
`ifndef PLATFORM_MEMORY_DATA_WIDTH
26-
`define PLATFORM_MEMORY_DATA_WIDTH 512
27-
`endif
28-
2917
`ifndef PLATFORM_MEMORY_OFFSET
3018
`define PLATFORM_MEMORY_OFFSET 0
3119
`endif

‎hw/rtl/libs/VX_async_ram_patch.sv

+1-1
Original file line numberDiff line numberDiff line change
@@ -221,7 +221,7 @@ module VX_async_ram_patch #(
221221
VX_placeholder #(
222222
.O (1)
223223
) placeholder2 (
224-
.in (),
224+
.in (1'b0),
225225
.out (is_raddr_reg)
226226
);
227227
wire [DATAW-1:0] rdata_a;

‎hw/rtl/libs/VX_axi_adapter.sv

+7-1
Original file line numberDiff line numberDiff line change
@@ -280,7 +280,13 @@ module VX_axi_adapter #(
280280
end
281281

282282
assign m_axi_arvalid[i] = req_xbar_valid_out[i] && ~xbar_rw_out;
283-
assign m_axi_araddr[i] = ADDR_WIDTH_OUT'(xbar_addr_out) << LOG2_DATA_SIZE;
283+
284+
// convert address to byte-addressable space
285+
if (INTERLEAVE) begin : g_m_axi_araddr_i
286+
assign m_axi_araddr[i] = (ADDR_WIDTH_OUT'(xbar_addr_out) << (BANK_SEL_BITS + LOG2_DATA_SIZE)) | (ADDR_WIDTH_OUT'(i) << LOG2_DATA_SIZE);
287+
end else begin : g_m_axi_araddr_ni
288+
assign m_axi_araddr[i] = (ADDR_WIDTH_OUT'(xbar_addr_out) << LOG2_DATA_SIZE) | (ADDR_WIDTH_OUT'(i) << (BANK_ADDR_WIDTH + LOG2_DATA_SIZE));
289+
end
284290
assign m_axi_arid[i] = TAG_WIDTH_OUT'(xbar_tag_r_out);
285291
assign m_axi_arlen[i] = 8'b00000000;
286292
assign m_axi_arsize[i] = 3'(LOG2_DATA_SIZE);

‎hw/syn/altera/dut/top/Makefile

-16
Original file line numberDiff line numberDiff line change
@@ -7,22 +7,6 @@ include ../../common.mk
77
# AFU parameters
88
CONFIGS += -DNOPAE
99
CONFIGS += -DPLATFORM_PROVIDES_LOCAL_MEMORY
10-
ifeq (,$(findstring PLATFORM_MEMORY_BANKS,$(CONFIGS)))
11-
CONFIGS += -DPLATFORM_MEMORY_BANKS=2
12-
endif
13-
ifeq (,$(findstring PLATFORM_MEMORY_ADDR_WIDTH,$(CONFIGS)))
14-
ifeq ($(XLEN),64)
15-
CONFIGS += -DPLATFORM_MEMORY_ADDR_WIDTH=47
16-
else
17-
CONFIGS += -DPLATFORM_MEMORY_ADDR_WIDTH=31
18-
endif
19-
endif
20-
ifeq (,$(findstring PLATFORM_MEMORY_DATA_WIDTH,$(CONFIGS)))
21-
CONFIGS += -DPLATFORM_MEMORY_DATA_WIDTH=512
22-
endif
23-
ifeq (,$(findstring PLATFORM_MEMORY_BURST_CNT_WIDTH,$(CONFIGS)))
24-
CONFIGS += -DPLATFORM_MEMORY_BURST_CNT_WIDTH=4
25-
endif
2610

2711
#CONFIGS += -DNUM_CORES=2
2812
#CONFIGS += -DNUM_WARPS=32

‎hw/syn/altera/opae/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -99,7 +99,7 @@ ifdef PERF
9999
endif
100100

101101
# ast dump flags
102-
XML_CFLAGS = $(filter-out -DSYNTHESIS -DQUARTUS, $(CFLAGS)) $(RTL_PKGS) -I$(AFU_DIR)/ccip -I$(DPI_DIR) -DPLATFORM_PROVIDES_LOCAL_MEMORY -DPLATFORM_MEMORY_BANKS=1 -DPLATFORM_MEMORY_ADDR_WIDTH=32 -DPLATFORM_MEMORY_DATA_WIDTH=512 -DPLATFORM_MEMORY_BURST_CNT_WIDTH=4 -DNOPAE -DSV_DPI
102+
XML_CFLAGS = $(filter-out -DSYNTHESIS -DQUARTUS, $(CFLAGS)) $(RTL_PKGS) -I$(AFU_DIR)/ccip -I$(DPI_DIR) -DPLATFORM_PROVIDES_LOCAL_MEMORY -DPLATFORM_MEMORY_NUM_BANKS=1 -DNOPAE -DSV_DPI
103103

104104
all: swconfig ip-gen setup build
105105

‎hw/syn/xilinx/xrt/package_kernel.tcl

+1-1
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,7 @@ foreach def $vdefines_list {
5252
if { $name == "CHIPSCOPE" } {
5353
set chipscope 1
5454
}
55-
if { $name == "PLATFORM_MEMORY_BANKS" } {
55+
if { $name == "PLATFORM_MEMORY_NUM_BANKS" } {
5656
set num_banks [lindex $fields 1]
5757
}
5858
if { $name == "PLATFORM_MERGED_MEMORY_INTERFACE" } {

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