minor updates

Author: tinebp

hw/rtl/VX_config.vh

@@ -191,7 +191,7 @@
 `endif
 
 `ifndef PLATFORM_MEMORY_INTERLEAVE
-`define PLATFORM_MEMORY_INTERLEAVE 0
+`define PLATFORM_MEMORY_INTERLEAVE 1
 `endif
 
 `ifdef XLEN_64

hw/rtl/afu/xrt/VX_afu_wrap.sv

@@ -16,12 +16,16 @@
 `include "vortex_afu.vh"
 
 module VX_afu_wrap #(
-	  parameter C_S_AXI_CTRL_ADDR_WIDTH = 8,
-	  parameter C_S_AXI_CTRL_DATA_WIDTH	= 32,
-	  parameter C_M_AXI_MEM_ID_WIDTH    = 32,
-	  parameter C_M_AXI_MEM_DATA_WIDTH  = 512,
-	  parameter C_M_AXI_MEM_ADDR_WIDTH  = 25,
-      parameter C_M_AXI_MEM_NUM_BANKS   = 2
+	parameter C_S_AXI_CTRL_ADDR_WIDTH = 8,
+	parameter C_S_AXI_CTRL_DATA_WIDTH = 32,
+	parameter C_M_AXI_MEM_ID_WIDTH    = `PLATFORM_MEMORY_ID_WIDTH,
+	parameter C_M_AXI_MEM_DATA_WIDTH  = `PLATFORM_MEMORY_DATA_SIZE * 8,
+	parameter C_M_AXI_MEM_ADDR_WIDTH  = 64,
+`ifdef PLATFORM_MERGED_MEMORY_INTERFACE
+	parameter C_M_AXI_MEM_NUM_BANKS   = 1
+`else
+	parameter C_M_AXI_MEM_NUM_BANKS   = `PLATFORM_MEMORY_NUM_BANKS
+`endif
 ) (
     // System signals
     input wire clk,
@@ -58,7 +62,7 @@ module VX_afu_wrap #(
 
     output wire                                 interrupt
 );
-	localparam M_AXI_MEM_ADDR_WIDTH = `PLATFORM_MEMORY_ADDR_WIDTH - $clog2(C_M_AXI_MEM_NUM_BANKS);
+	localparam M_AXI_MEM_ADDR_WIDTH = `PLATFORM_MEMORY_ADDR_WIDTH;
 
 	typedef enum logic [1:0] {
 		STATE_IDLE = 0,
@@ -283,9 +287,8 @@ module VX_afu_wrap #(
 	wire [M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_araddr_u [C_M_AXI_MEM_NUM_BANKS];
 
 	for (genvar i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin : g_addressing
-		localparam [C_M_AXI_MEM_ADDR_WIDTH-1:0] BANK_OFFSET = C_M_AXI_MEM_ADDR_WIDTH'(`PLATFORM_MEMORY_OFFSET) + C_M_AXI_MEM_ADDR_WIDTH'(i) << M_AXI_MEM_ADDR_WIDTH;
-		assign m_axi_mem_awaddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_awaddr_u[i]) + BANK_OFFSET;
-		assign m_axi_mem_araddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_araddr_u[i]) + BANK_OFFSET;
+		assign m_axi_mem_awaddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_awaddr_u[i]) + C_M_AXI_MEM_ADDR_WIDTH'(`PLATFORM_MEMORY_OFFSET);
+		assign m_axi_mem_araddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_araddr_u[i]) + C_M_AXI_MEM_ADDR_WIDTH'(`PLATFORM_MEMORY_OFFSET);
 	end
 
 	`SCOPE_IO_SWITCH (2);

hw/rtl/libs/VX_axi_adapter.sv

@@ -251,7 +251,13 @@ module VX_axi_adapter #(
         // AXI write address channel
 
         assign m_axi_awvalid[i] = req_xbar_valid_out[i] && xbar_rw_out && ~m_axi_aw_ack;
-        assign m_axi_awaddr[i]  = ADDR_WIDTH_OUT'(xbar_addr_out) << LOG2_DATA_SIZE;
+
+    if (INTERLEAVE) begin : g_m_axi_awaddr_i
+        assign m_axi_awaddr[i]  = (ADDR_WIDTH_OUT'(xbar_addr_out) << (BANK_SEL_BITS + LOG2_DATA_SIZE)) | (ADDR_WIDTH_OUT'(i) << LOG2_DATA_SIZE);
+    end else begin : g_m_axi_awaddr_ni
+        assign m_axi_awaddr[i]  = (ADDR_WIDTH_OUT'(xbar_addr_out) << LOG2_DATA_SIZE) | (ADDR_WIDTH_OUT'(i) << (BANK_ADDR_WIDTH + LOG2_DATA_SIZE));
+    end
+
         assign m_axi_awid[i]    = TAG_WIDTH_OUT'(xbar_tag_out);
         assign m_axi_awlen[i]   = 8'b00000000;
         assign m_axi_awsize[i]  = 3'(LOG2_DATA_SIZE);

sim/xrtsim/xrt_sim.cpp

@@ -490,7 +490,7 @@ class xrt_sim::Impl {
 
         /*printf("%0ld: [sim] axi-mem-read[%d]: addr=0x%lx, tag=0x%x, data=0x", timestamp, b, mem_req->addr, mem_req->tag);
         for (int i = PLATFORM_MEMORY_DATA_SIZE-1; i >= 0; --i) {
-          printf("%02x", mem_req->data[b]);
+          printf("%02x", mem_req->data[i]);
         }
         printf("\n");*/
 
@@ -533,7 +533,7 @@ class xrt_sim::Impl {
 
         /*printf("%0ld: [sim] axi-mem-write[%d]: addr=0x%lx, byteen=0x%lx, tag=0x%x, data=0x", timestamp, b, mem_req->addr, byteen, mem_req->tag);
         for (int i = PLATFORM_MEMORY_DATA_SIZE-1; i >= 0; --i) {
-          printf("%02x", m_axi_states_[b].write_req_data[i]]);
+          printf("%02x", m_axi_states_[b].write_req_data[i]);
         }
         printf("\n");*/