Remove unused EXTV code, clean up code, pragma once around vpu.h

Author: MichaelJSr

sim/simx/Makefile

@@ -22,7 +22,7 @@ SRCS += $(SRC_DIR)/processor.cpp $(SRC_DIR)/cluster.cpp $(SRC_DIR)/socket.cpp $(
 
 # Add V extension sources
 ifneq ($(findstring -DEXT_V_ENABLE, $(CONFIGS)),)
-  SRCS += $(SRC_DIR)/execute_v.cpp
+  SRCS += $(SRC_DIR)/vpu.cpp
 endif
 
 # Debugging

sim/simx/arch.h

@@ -29,7 +29,6 @@ class Arch {
   uint16_t num_cores_;
   uint16_t num_clusters_;
   uint16_t socket_size_;
-  uint16_t vsize_;
   uint16_t num_barriers_;
   uint64_t local_mem_base_;
 
@@ -40,7 +39,6 @@ class Arch {
     , num_cores_(num_cores)
     , num_clusters_(NUM_CLUSTERS)
     , socket_size_(SOCKET_SIZE)
-    , vsize_(VLEN / 8)
     , num_barriers_(NUM_BARRIERS)
     , local_mem_base_(LMEM_BASE_ADDR)
   {}
@@ -73,10 +71,6 @@ class Arch {
     return socket_size_;
   }
 
-  uint16_t vsize() const {
-    return vsize_;
-  }
-
 };
 
 }

sim/simx/emulator.cpp

@@ -33,7 +33,7 @@ using namespace vortex;
 Emulator::warp_t::warp_t(const Arch& arch)
   : ireg_file(arch.num_threads(), std::vector<Word>(MAX_NUM_REGS))
   , freg_file(arch.num_threads(), std::vector<uint64_t>(MAX_NUM_REGS))
-  , vreg_file(MAX_NUM_REGS, std::vector<Byte>(arch.vsize()))
+  , vreg_file(MAX_NUM_REGS, std::vector<Byte>(MAX_NUM_REGS))
   , uuid(0)
 {}
 
@@ -77,16 +77,6 @@ void Emulator::warp_t::clear(uint64_t startup_addr) {
     #endif
     }
   }
-
-  for (auto& reg_file : this->vreg_file) {
-    for (auto& reg : reg_file) {
-    #ifndef NDEBUG
-      reg = 0;
-    #else
-      reg = std::rand();
-    #endif
-    }
-  }
 }
 
 ///////////////////////////////////////////////////////////////////////////////

sim/simx/execute.cpp

@@ -932,7 +932,7 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
     for (uint32_t t = thread_start; t < num_threads; ++t) {
       if (!warp.tmask.test(t))
         continue;
-      uint32_t frm = (func3 == 0x7) ? this->get_csr(VX_CSR_FRM, t, wid) : func3;
+      uint32_t frm = this->get_fpu_rm(func3, t, wid);
       uint32_t fflags = 0;
       switch (func7) {
       case 0x00: { // RV32F: FADD.S
@@ -1247,10 +1247,7 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
         break;
       }
       }
-      if (fflags) {
-        this->set_csr(VX_CSR_FCSR, this->get_csr(VX_CSR_FCSR, t, wid) | fflags, t, wid);
-        this->set_csr(VX_CSR_FFLAGS, this->get_csr(VX_CSR_FFLAGS, t, wid) | fflags, t, wid);
-      }
+      this->update_fcrs(fflags, t, wid);
     }
     rd_write = true;
     break;
@@ -1304,10 +1301,7 @@ void Emulator::execute(const Instr &instr, uint32_t wid, instr_trace_t *trace) {
       default:
         break;
       }
-      if (fflags) {
-        this->set_csr(VX_CSR_FCSR, this->get_csr(VX_CSR_FCSR, t, wid) | fflags, t, wid);
-        this->set_csr(VX_CSR_FFLAGS, this->get_csr(VX_CSR_FFLAGS, t, wid) | fflags, t, wid);
-      }
+      this->update_fcrs(fflags, t, wid);
     }
     rd_write = true;
     break;

sim/simx/execute_v.cpp sim/simx/vpu.cpp

@@ -11,7 +11,7 @@ XLEN=64 ./run-test.sh
 
 ## Adding a new testcase
 
-The source code for the vector extension can be found in `sim/simx/execute_vector.cpp`.
+The source code for the vector extension can be found in `sim/simx/vpu.cpp`.
 If you add support for a new vector instruction please go to `run-test.sh` and it to the default testcases.
 This will ensure your instruction is included in the regression test suite.
 

sim/simx/vpu.h

@@ -1,7 +1,4 @@
 #!/bin/bash
-VLEN=${VLEN:-256}
-XLEN=${XLEN:-32}
-
 RISCV_TOOLCHAIN_PATH=${RISCV_TOOLCHAIN_PATH:-$TOOLDIR"/riscv"$XLEN"-gnu-toolchain"}
 
 SCRIPT_DIR=$( cd -- "$( dirname -- "${BASH_SOURCE[0]}" )" &> /dev/null && pwd )